Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
42 | #include <linux/sched.h> | |
87507cfd | 43 | #include <linux/dma-mapping.h> |
a9524a76 | 44 | #include <linux/device.h> |
1da177e4 | 45 | #include <scsi/scsi_host.h> |
193515d5 | 46 | #include <scsi/scsi_cmnd.h> |
1da177e4 LT |
47 | #include <linux/libata.h> |
48 | #include <asm/io.h> | |
49 | ||
50 | #define DRV_NAME "ahci" | |
8676ce07 | 51 | #define DRV_VERSION "2.0" |
1da177e4 LT |
52 | |
53 | ||
54 | enum { | |
55 | AHCI_PCI_BAR = 5, | |
56 | AHCI_MAX_SG = 168, /* hardware max is 64K */ | |
57 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
58 | AHCI_USE_CLUSTERING = 0, | |
12fad3f9 | 59 | AHCI_MAX_CMDS = 32, |
dd410ff1 | 60 | AHCI_CMD_SZ = 32, |
12fad3f9 | 61 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
1da177e4 | 62 | AHCI_RX_FIS_SZ = 256, |
a0ea7328 | 63 | AHCI_CMD_TBL_CDB = 0x40, |
dd410ff1 TH |
64 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
65 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), | |
66 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, | |
67 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + | |
1da177e4 LT |
68 | AHCI_RX_FIS_SZ, |
69 | AHCI_IRQ_ON_SG = (1 << 31), | |
70 | AHCI_CMD_ATAPI = (1 << 5), | |
71 | AHCI_CMD_WRITE = (1 << 6), | |
4b10e559 | 72 | AHCI_CMD_PREFETCH = (1 << 7), |
22b49985 TH |
73 | AHCI_CMD_RESET = (1 << 8), |
74 | AHCI_CMD_CLR_BUSY = (1 << 10), | |
1da177e4 LT |
75 | |
76 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
78cd52d0 | 77 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
1da177e4 LT |
78 | |
79 | board_ahci = 0, | |
bf2af2a2 | 80 | board_ahci_vt8251 = 1, |
1da177e4 LT |
81 | |
82 | /* global controller registers */ | |
83 | HOST_CAP = 0x00, /* host capabilities */ | |
84 | HOST_CTL = 0x04, /* global host control */ | |
85 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
86 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
87 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
88 | ||
89 | /* HOST_CTL bits */ | |
90 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
91 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
92 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
93 | ||
94 | /* HOST_CAP bits */ | |
0be0aa98 | 95 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
22b49985 | 96 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
0be0aa98 | 97 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
979db803 | 98 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
dd410ff1 | 99 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
1da177e4 LT |
100 | |
101 | /* registers for each SATA port */ | |
102 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
103 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
104 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
105 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
106 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
107 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
108 | PORT_CMD = 0x18, /* port command */ | |
109 | PORT_TFDATA = 0x20, /* taskfile data */ | |
110 | PORT_SIG = 0x24, /* device TF signature */ | |
111 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
112 | PORT_SCR = 0x28, /* SATA phy register block */ | |
113 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ | |
114 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
115 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
116 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
117 | ||
118 | /* PORT_IRQ_{STAT,MASK} bits */ | |
119 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
120 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
121 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
122 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
123 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
124 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
125 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
126 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
127 | ||
128 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
129 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
130 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
131 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
132 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
133 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
134 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
135 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
136 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
137 | ||
78cd52d0 TH |
138 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
139 | PORT_IRQ_IF_ERR | | |
140 | PORT_IRQ_CONNECT | | |
4296971d | 141 | PORT_IRQ_PHYRDY | |
78cd52d0 TH |
142 | PORT_IRQ_UNK_FIS, |
143 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | | |
144 | PORT_IRQ_TF_ERR | | |
145 | PORT_IRQ_HBUS_DATA_ERR, | |
146 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | | |
147 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | | |
148 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, | |
1da177e4 LT |
149 | |
150 | /* PORT_CMD bits */ | |
02eaa666 | 151 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
1da177e4 LT |
152 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
153 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
154 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
22b49985 | 155 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
1da177e4 LT |
156 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
157 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
158 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
159 | ||
0be0aa98 | 160 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
1da177e4 LT |
161 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
162 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
163 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 JG |
164 | |
165 | /* hpriv->flags bits */ | |
166 | AHCI_FLAG_MSI = (1 << 0), | |
bf2af2a2 BJ |
167 | |
168 | /* ap->flags bits */ | |
169 | AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24), | |
71f0737b | 170 | AHCI_FLAG_NO_NCQ = (1 << 25), |
1da177e4 LT |
171 | }; |
172 | ||
173 | struct ahci_cmd_hdr { | |
174 | u32 opts; | |
175 | u32 status; | |
176 | u32 tbl_addr; | |
177 | u32 tbl_addr_hi; | |
178 | u32 reserved[4]; | |
179 | }; | |
180 | ||
181 | struct ahci_sg { | |
182 | u32 addr; | |
183 | u32 addr_hi; | |
184 | u32 reserved; | |
185 | u32 flags_size; | |
186 | }; | |
187 | ||
188 | struct ahci_host_priv { | |
189 | unsigned long flags; | |
190 | u32 cap; /* cache of HOST_CAP register */ | |
191 | u32 port_map; /* cache of HOST_PORTS_IMPL reg */ | |
192 | }; | |
193 | ||
194 | struct ahci_port_priv { | |
195 | struct ahci_cmd_hdr *cmd_slot; | |
196 | dma_addr_t cmd_slot_dma; | |
197 | void *cmd_tbl; | |
198 | dma_addr_t cmd_tbl_dma; | |
1da177e4 LT |
199 | void *rx_fis; |
200 | dma_addr_t rx_fis_dma; | |
201 | }; | |
202 | ||
203 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
204 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
205 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
9a3d9eb0 | 206 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
1da177e4 | 207 | static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs); |
1da177e4 | 208 | static void ahci_irq_clear(struct ata_port *ap); |
1da177e4 LT |
209 | static int ahci_port_start(struct ata_port *ap); |
210 | static void ahci_port_stop(struct ata_port *ap); | |
1da177e4 LT |
211 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
212 | static void ahci_qc_prep(struct ata_queued_cmd *qc); | |
213 | static u8 ahci_check_status(struct ata_port *ap); | |
78cd52d0 TH |
214 | static void ahci_freeze(struct ata_port *ap); |
215 | static void ahci_thaw(struct ata_port *ap); | |
216 | static void ahci_error_handler(struct ata_port *ap); | |
217 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); | |
907f4678 | 218 | static void ahci_remove_one (struct pci_dev *pdev); |
1da177e4 | 219 | |
193515d5 | 220 | static struct scsi_host_template ahci_sht = { |
1da177e4 LT |
221 | .module = THIS_MODULE, |
222 | .name = DRV_NAME, | |
223 | .ioctl = ata_scsi_ioctl, | |
224 | .queuecommand = ata_scsi_queuecmd, | |
12fad3f9 TH |
225 | .change_queue_depth = ata_scsi_change_queue_depth, |
226 | .can_queue = AHCI_MAX_CMDS - 1, | |
1da177e4 LT |
227 | .this_id = ATA_SHT_THIS_ID, |
228 | .sg_tablesize = AHCI_MAX_SG, | |
1da177e4 LT |
229 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
230 | .emulated = ATA_SHT_EMULATED, | |
231 | .use_clustering = AHCI_USE_CLUSTERING, | |
232 | .proc_name = DRV_NAME, | |
233 | .dma_boundary = AHCI_DMA_BOUNDARY, | |
234 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 235 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 236 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
237 | }; |
238 | ||
057ace5e | 239 | static const struct ata_port_operations ahci_ops = { |
1da177e4 LT |
240 | .port_disable = ata_port_disable, |
241 | ||
242 | .check_status = ahci_check_status, | |
243 | .check_altstatus = ahci_check_status, | |
1da177e4 LT |
244 | .dev_select = ata_noop_dev_select, |
245 | ||
246 | .tf_read = ahci_tf_read, | |
247 | ||
1da177e4 LT |
248 | .qc_prep = ahci_qc_prep, |
249 | .qc_issue = ahci_qc_issue, | |
250 | ||
1da177e4 LT |
251 | .irq_handler = ahci_interrupt, |
252 | .irq_clear = ahci_irq_clear, | |
253 | ||
254 | .scr_read = ahci_scr_read, | |
255 | .scr_write = ahci_scr_write, | |
256 | ||
78cd52d0 TH |
257 | .freeze = ahci_freeze, |
258 | .thaw = ahci_thaw, | |
259 | ||
260 | .error_handler = ahci_error_handler, | |
261 | .post_internal_cmd = ahci_post_internal_cmd, | |
262 | ||
1da177e4 LT |
263 | .port_start = ahci_port_start, |
264 | .port_stop = ahci_port_stop, | |
1da177e4 LT |
265 | }; |
266 | ||
98ac62de | 267 | static const struct ata_port_info ahci_port_info[] = { |
1da177e4 LT |
268 | /* board_ahci */ |
269 | { | |
270 | .sht = &ahci_sht, | |
271 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
4296971d TH |
272 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
273 | ATA_FLAG_SKIP_D2H_BSY, | |
7da79312 | 274 | .pio_mask = 0x1f, /* pio0-4 */ |
1da177e4 LT |
275 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
276 | .port_ops = &ahci_ops, | |
277 | }, | |
bf2af2a2 BJ |
278 | /* board_ahci_vt8251 */ |
279 | { | |
280 | .sht = &ahci_sht, | |
281 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
282 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
4296971d | 283 | ATA_FLAG_SKIP_D2H_BSY | |
71f0737b | 284 | AHCI_FLAG_RESET_NEEDS_CLO | AHCI_FLAG_NO_NCQ, |
bf2af2a2 BJ |
285 | .pio_mask = 0x1f, /* pio0-4 */ |
286 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
287 | .port_ops = &ahci_ops, | |
288 | }, | |
1da177e4 LT |
289 | }; |
290 | ||
3b7d697d | 291 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 292 | /* Intel */ |
1da177e4 LT |
293 | { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
294 | board_ahci }, /* ICH6 */ | |
295 | { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
296 | board_ahci }, /* ICH6M */ | |
297 | { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
298 | board_ahci }, /* ICH7 */ | |
299 | { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
300 | board_ahci }, /* ICH7M */ | |
301 | { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
302 | board_ahci }, /* ICH7R */ | |
303 | { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
304 | board_ahci }, /* ULi M5288 */ | |
680d3235 JG |
305 | { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
306 | board_ahci }, /* ESB2 */ | |
307 | { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
308 | board_ahci }, /* ESB2 */ | |
309 | { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
310 | board_ahci }, /* ESB2 */ | |
3db368f7 JG |
311 | { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
312 | board_ahci }, /* ICH7-M DH */ | |
f285757c JG |
313 | { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
314 | board_ahci }, /* ICH8 */ | |
315 | { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
316 | board_ahci }, /* ICH8 */ | |
317 | { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
318 | board_ahci }, /* ICH8 */ | |
319 | { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
320 | board_ahci }, /* ICH8M */ | |
321 | { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
322 | board_ahci }, /* ICH8M */ | |
fe7fa31a JG |
323 | |
324 | /* JMicron */ | |
bd12097c JG |
325 | { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
326 | board_ahci }, /* JMicron JMB360 */ | |
8fa29b23 JG |
327 | { 0x197b, 0x2361, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
328 | board_ahci }, /* JMicron JMB361 */ | |
9220a2d0 JG |
329 | { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
330 | board_ahci }, /* JMicron JMB363 */ | |
8fa29b23 JG |
331 | { 0x197b, 0x2365, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
332 | board_ahci }, /* JMicron JMB365 */ | |
333 | { 0x197b, 0x2366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
334 | board_ahci }, /* JMicron JMB366 */ | |
fe7fa31a JG |
335 | |
336 | /* ATI */ | |
8b316a39 JG |
337 | { PCI_VENDOR_ID_ATI, 0x4380, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
338 | board_ahci }, /* ATI SB600 non-raid */ | |
339 | { PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
340 | board_ahci }, /* ATI SB600 raid */ | |
fe7fa31a JG |
341 | |
342 | /* VIA */ | |
bf2af2a2 BJ |
343 | { PCI_VENDOR_ID_VIA, 0x3349, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
344 | board_ahci_vt8251 }, /* VIA VT8251 */ | |
fe7fa31a JG |
345 | |
346 | /* NVIDIA */ | |
347 | { PCI_VENDOR_ID_NVIDIA, 0x044c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
348 | board_ahci }, /* MCP65 */ | |
349 | { PCI_VENDOR_ID_NVIDIA, 0x044d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
350 | board_ahci }, /* MCP65 */ | |
351 | { PCI_VENDOR_ID_NVIDIA, 0x044e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
352 | board_ahci }, /* MCP65 */ | |
353 | { PCI_VENDOR_ID_NVIDIA, 0x044f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
354 | board_ahci }, /* MCP65 */ | |
355 | ||
1da177e4 LT |
356 | { } /* terminate list */ |
357 | }; | |
358 | ||
359 | ||
360 | static struct pci_driver ahci_pci_driver = { | |
361 | .name = DRV_NAME, | |
362 | .id_table = ahci_pci_tbl, | |
363 | .probe = ahci_init_one, | |
907f4678 | 364 | .remove = ahci_remove_one, |
1da177e4 LT |
365 | }; |
366 | ||
367 | ||
368 | static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port) | |
369 | { | |
370 | return base + 0x100 + (port * 0x80); | |
371 | } | |
372 | ||
ea6ba10b | 373 | static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port) |
1da177e4 | 374 | { |
ea6ba10b | 375 | return (void __iomem *) ahci_port_base_ul((unsigned long)base, port); |
1da177e4 LT |
376 | } |
377 | ||
1da177e4 LT |
378 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) |
379 | { | |
380 | unsigned int sc_reg; | |
381 | ||
382 | switch (sc_reg_in) { | |
383 | case SCR_STATUS: sc_reg = 0; break; | |
384 | case SCR_CONTROL: sc_reg = 1; break; | |
385 | case SCR_ERROR: sc_reg = 2; break; | |
386 | case SCR_ACTIVE: sc_reg = 3; break; | |
387 | default: | |
388 | return 0xffffffffU; | |
389 | } | |
390 | ||
1e4f2a96 | 391 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
392 | } |
393 | ||
394 | ||
395 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, | |
396 | u32 val) | |
397 | { | |
398 | unsigned int sc_reg; | |
399 | ||
400 | switch (sc_reg_in) { | |
401 | case SCR_STATUS: sc_reg = 0; break; | |
402 | case SCR_CONTROL: sc_reg = 1; break; | |
403 | case SCR_ERROR: sc_reg = 2; break; | |
404 | case SCR_ACTIVE: sc_reg = 3; break; | |
405 | default: | |
406 | return; | |
407 | } | |
408 | ||
1e4f2a96 | 409 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
410 | } |
411 | ||
9f592056 | 412 | static void ahci_start_engine(void __iomem *port_mmio) |
7c76d1e8 | 413 | { |
7c76d1e8 TH |
414 | u32 tmp; |
415 | ||
d8fcd116 | 416 | /* start DMA */ |
9f592056 | 417 | tmp = readl(port_mmio + PORT_CMD); |
7c76d1e8 TH |
418 | tmp |= PORT_CMD_START; |
419 | writel(tmp, port_mmio + PORT_CMD); | |
420 | readl(port_mmio + PORT_CMD); /* flush */ | |
421 | } | |
422 | ||
254950cd TH |
423 | static int ahci_stop_engine(void __iomem *port_mmio) |
424 | { | |
425 | u32 tmp; | |
426 | ||
427 | tmp = readl(port_mmio + PORT_CMD); | |
428 | ||
d8fcd116 | 429 | /* check if the HBA is idle */ |
254950cd TH |
430 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
431 | return 0; | |
432 | ||
d8fcd116 | 433 | /* setting HBA to idle */ |
254950cd TH |
434 | tmp &= ~PORT_CMD_START; |
435 | writel(tmp, port_mmio + PORT_CMD); | |
436 | ||
d8fcd116 | 437 | /* wait for engine to stop. This could be as long as 500 msec */ |
254950cd TH |
438 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
439 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); | |
d8fcd116 | 440 | if (tmp & PORT_CMD_LIST_ON) |
254950cd TH |
441 | return -EIO; |
442 | ||
443 | return 0; | |
444 | } | |
445 | ||
0be0aa98 TH |
446 | static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap, |
447 | dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma) | |
448 | { | |
449 | u32 tmp; | |
450 | ||
451 | /* set FIS registers */ | |
452 | if (cap & HOST_CAP_64) | |
453 | writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI); | |
454 | writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
455 | ||
456 | if (cap & HOST_CAP_64) | |
457 | writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI); | |
458 | writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
459 | ||
460 | /* enable FIS reception */ | |
461 | tmp = readl(port_mmio + PORT_CMD); | |
462 | tmp |= PORT_CMD_FIS_RX; | |
463 | writel(tmp, port_mmio + PORT_CMD); | |
464 | ||
465 | /* flush */ | |
466 | readl(port_mmio + PORT_CMD); | |
467 | } | |
468 | ||
469 | static int ahci_stop_fis_rx(void __iomem *port_mmio) | |
470 | { | |
471 | u32 tmp; | |
472 | ||
473 | /* disable FIS reception */ | |
474 | tmp = readl(port_mmio + PORT_CMD); | |
475 | tmp &= ~PORT_CMD_FIS_RX; | |
476 | writel(tmp, port_mmio + PORT_CMD); | |
477 | ||
478 | /* wait for completion, spec says 500ms, give it 1000 */ | |
479 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, | |
480 | PORT_CMD_FIS_ON, 10, 1000); | |
481 | if (tmp & PORT_CMD_FIS_ON) | |
482 | return -EBUSY; | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
487 | static void ahci_power_up(void __iomem *port_mmio, u32 cap) | |
488 | { | |
489 | u32 cmd; | |
490 | ||
491 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
492 | ||
493 | /* spin up device */ | |
494 | if (cap & HOST_CAP_SSS) { | |
495 | cmd |= PORT_CMD_SPIN_UP; | |
496 | writel(cmd, port_mmio + PORT_CMD); | |
497 | } | |
498 | ||
499 | /* wake up link */ | |
500 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); | |
501 | } | |
502 | ||
503 | static void ahci_power_down(void __iomem *port_mmio, u32 cap) | |
504 | { | |
505 | u32 cmd, scontrol; | |
506 | ||
507 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
508 | ||
509 | if (cap & HOST_CAP_SSC) { | |
510 | /* enable transitions to slumber mode */ | |
511 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
512 | if ((scontrol & 0x0f00) > 0x100) { | |
513 | scontrol &= ~0xf00; | |
514 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
515 | } | |
516 | ||
517 | /* put device into slumber mode */ | |
518 | writel(cmd | PORT_CMD_ICC_SLUMBER, port_mmio + PORT_CMD); | |
519 | ||
520 | /* wait for the transition to complete */ | |
521 | ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_ICC_SLUMBER, | |
522 | PORT_CMD_ICC_SLUMBER, 1, 50); | |
523 | } | |
524 | ||
525 | /* put device into listen mode */ | |
526 | if (cap & HOST_CAP_SSS) { | |
527 | /* first set PxSCTL.DET to 0 */ | |
528 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
529 | scontrol &= ~0xf; | |
530 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
531 | ||
532 | /* then set PxCMD.SUD to 0 */ | |
533 | cmd &= ~PORT_CMD_SPIN_UP; | |
534 | writel(cmd, port_mmio + PORT_CMD); | |
535 | } | |
536 | } | |
537 | ||
538 | static void ahci_init_port(void __iomem *port_mmio, u32 cap, | |
539 | dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma) | |
540 | { | |
541 | /* power up */ | |
542 | ahci_power_up(port_mmio, cap); | |
543 | ||
544 | /* enable FIS reception */ | |
545 | ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma); | |
546 | ||
547 | /* enable DMA */ | |
548 | ahci_start_engine(port_mmio); | |
549 | } | |
550 | ||
551 | static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg) | |
552 | { | |
553 | int rc; | |
554 | ||
555 | /* disable DMA */ | |
556 | rc = ahci_stop_engine(port_mmio); | |
557 | if (rc) { | |
558 | *emsg = "failed to stop engine"; | |
559 | return rc; | |
560 | } | |
561 | ||
562 | /* disable FIS reception */ | |
563 | rc = ahci_stop_fis_rx(port_mmio); | |
564 | if (rc) { | |
565 | *emsg = "failed stop FIS RX"; | |
566 | return rc; | |
567 | } | |
568 | ||
569 | /* put device into slumber mode */ | |
570 | ahci_power_down(port_mmio, cap); | |
571 | ||
572 | return 0; | |
573 | } | |
574 | ||
d91542c1 TH |
575 | static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev) |
576 | { | |
577 | u32 cap_save, tmp; | |
578 | ||
579 | cap_save = readl(mmio + HOST_CAP); | |
580 | cap_save &= ( (1<<28) | (1<<17) ); | |
581 | cap_save |= (1 << 27); | |
582 | ||
583 | /* global controller reset */ | |
584 | tmp = readl(mmio + HOST_CTL); | |
585 | if ((tmp & HOST_RESET) == 0) { | |
586 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
587 | readl(mmio + HOST_CTL); /* flush */ | |
588 | } | |
589 | ||
590 | /* reset must complete within 1 second, or | |
591 | * the hardware should be considered fried. | |
592 | */ | |
593 | ssleep(1); | |
594 | ||
595 | tmp = readl(mmio + HOST_CTL); | |
596 | if (tmp & HOST_RESET) { | |
597 | dev_printk(KERN_ERR, &pdev->dev, | |
598 | "controller reset failed (0x%x)\n", tmp); | |
599 | return -EIO; | |
600 | } | |
601 | ||
602 | writel(HOST_AHCI_EN, mmio + HOST_CTL); | |
603 | (void) readl(mmio + HOST_CTL); /* flush */ | |
604 | writel(cap_save, mmio + HOST_CAP); | |
605 | writel(0xf, mmio + HOST_PORTS_IMPL); | |
606 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | |
607 | ||
608 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { | |
609 | u16 tmp16; | |
610 | ||
611 | /* configure PCS */ | |
612 | pci_read_config_word(pdev, 0x92, &tmp16); | |
613 | tmp16 |= 0xf; | |
614 | pci_write_config_word(pdev, 0x92, tmp16); | |
615 | } | |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
620 | static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev, | |
621 | int n_ports, u32 cap) | |
622 | { | |
623 | int i, rc; | |
624 | u32 tmp; | |
625 | ||
626 | for (i = 0; i < n_ports; i++) { | |
627 | void __iomem *port_mmio = ahci_port_base(mmio, i); | |
628 | const char *emsg = NULL; | |
629 | ||
630 | #if 0 /* BIOSen initialize this incorrectly */ | |
631 | if (!(hpriv->port_map & (1 << i))) | |
632 | continue; | |
633 | #endif | |
634 | ||
635 | /* make sure port is not active */ | |
636 | rc = ahci_deinit_port(port_mmio, cap, &emsg); | |
637 | if (rc) | |
638 | dev_printk(KERN_WARNING, &pdev->dev, | |
639 | "%s (%d)\n", emsg, rc); | |
640 | ||
641 | /* clear SError */ | |
642 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
643 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
644 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
645 | ||
646 | /* clear & turn off port IRQ */ | |
647 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
648 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
649 | if (tmp) | |
650 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
651 | ||
652 | writel(1 << i, mmio + HOST_IRQ_STAT); | |
653 | writel(0, port_mmio + PORT_IRQ_MASK); | |
654 | } | |
655 | ||
656 | tmp = readl(mmio + HOST_CTL); | |
657 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
658 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
659 | tmp = readl(mmio + HOST_CTL); | |
660 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
661 | } | |
662 | ||
422b7595 | 663 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
1da177e4 LT |
664 | { |
665 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
666 | struct ata_taskfile tf; | |
422b7595 TH |
667 | u32 tmp; |
668 | ||
669 | tmp = readl(port_mmio + PORT_SIG); | |
670 | tf.lbah = (tmp >> 24) & 0xff; | |
671 | tf.lbam = (tmp >> 16) & 0xff; | |
672 | tf.lbal = (tmp >> 8) & 0xff; | |
673 | tf.nsect = (tmp) & 0xff; | |
674 | ||
675 | return ata_dev_classify(&tf); | |
676 | } | |
677 | ||
12fad3f9 TH |
678 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
679 | u32 opts) | |
cc9278ed | 680 | { |
12fad3f9 TH |
681 | dma_addr_t cmd_tbl_dma; |
682 | ||
683 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
684 | ||
685 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
686 | pp->cmd_slot[tag].status = 0; | |
687 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
688 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
cc9278ed TH |
689 | } |
690 | ||
bf2af2a2 | 691 | static int ahci_clo(struct ata_port *ap) |
4658f79b | 692 | { |
bf2af2a2 | 693 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
4658f79b | 694 | struct ahci_host_priv *hpriv = ap->host_set->private_data; |
bf2af2a2 BJ |
695 | u32 tmp; |
696 | ||
697 | if (!(hpriv->cap & HOST_CAP_CLO)) | |
698 | return -EOPNOTSUPP; | |
699 | ||
700 | tmp = readl(port_mmio + PORT_CMD); | |
701 | tmp |= PORT_CMD_CLO; | |
702 | writel(tmp, port_mmio + PORT_CMD); | |
703 | ||
704 | tmp = ata_wait_register(port_mmio + PORT_CMD, | |
705 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); | |
706 | if (tmp & PORT_CMD_CLO) | |
707 | return -EIO; | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
4296971d TH |
712 | static int ahci_prereset(struct ata_port *ap) |
713 | { | |
714 | if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) && | |
715 | (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) { | |
716 | /* ATA_BUSY hasn't cleared, so send a CLO */ | |
717 | ahci_clo(ap); | |
718 | } | |
719 | ||
720 | return ata_std_prereset(ap); | |
721 | } | |
722 | ||
bf2af2a2 BJ |
723 | static int ahci_softreset(struct ata_port *ap, unsigned int *class) |
724 | { | |
4658f79b TH |
725 | struct ahci_port_priv *pp = ap->private_data; |
726 | void __iomem *mmio = ap->host_set->mmio_base; | |
727 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
728 | const u32 cmd_fis_len = 5; /* five dwords */ | |
729 | const char *reason = NULL; | |
730 | struct ata_taskfile tf; | |
75fe1806 | 731 | u32 tmp; |
4658f79b TH |
732 | u8 *fis; |
733 | int rc; | |
734 | ||
735 | DPRINTK("ENTER\n"); | |
736 | ||
81952c54 | 737 | if (ata_port_offline(ap)) { |
c2a65852 TH |
738 | DPRINTK("PHY reports no device\n"); |
739 | *class = ATA_DEV_NONE; | |
740 | return 0; | |
741 | } | |
742 | ||
4658f79b | 743 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
5457f219 | 744 | rc = ahci_stop_engine(port_mmio); |
4658f79b TH |
745 | if (rc) { |
746 | reason = "failed to stop engine"; | |
747 | goto fail_restart; | |
748 | } | |
749 | ||
750 | /* check BUSY/DRQ, perform Command List Override if necessary */ | |
751 | ahci_tf_read(ap, &tf); | |
752 | if (tf.command & (ATA_BUSY | ATA_DRQ)) { | |
bf2af2a2 | 753 | rc = ahci_clo(ap); |
4658f79b | 754 | |
bf2af2a2 BJ |
755 | if (rc == -EOPNOTSUPP) { |
756 | reason = "port busy but CLO unavailable"; | |
757 | goto fail_restart; | |
758 | } else if (rc) { | |
759 | reason = "port busy but CLO failed"; | |
4658f79b TH |
760 | goto fail_restart; |
761 | } | |
762 | } | |
763 | ||
764 | /* restart engine */ | |
5457f219 | 765 | ahci_start_engine(port_mmio); |
4658f79b | 766 | |
3373efd8 | 767 | ata_tf_init(ap->device, &tf); |
4658f79b TH |
768 | fis = pp->cmd_tbl; |
769 | ||
770 | /* issue the first D2H Register FIS */ | |
12fad3f9 TH |
771 | ahci_fill_cmd_slot(pp, 0, |
772 | cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY); | |
4658f79b TH |
773 | |
774 | tf.ctl |= ATA_SRST; | |
775 | ata_tf_to_fis(&tf, fis, 0); | |
776 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ | |
777 | ||
778 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
4658f79b | 779 | |
75fe1806 TH |
780 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500); |
781 | if (tmp & 0x1) { | |
4658f79b TH |
782 | rc = -EIO; |
783 | reason = "1st FIS failed"; | |
784 | goto fail; | |
785 | } | |
786 | ||
787 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
788 | msleep(1); | |
789 | ||
790 | /* issue the second D2H Register FIS */ | |
12fad3f9 | 791 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len); |
4658f79b TH |
792 | |
793 | tf.ctl &= ~ATA_SRST; | |
794 | ata_tf_to_fis(&tf, fis, 0); | |
795 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ | |
796 | ||
797 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
798 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
799 | ||
800 | /* spec mandates ">= 2ms" before checking status. | |
801 | * We wait 150ms, because that was the magic delay used for | |
802 | * ATAPI devices in Hale Landis's ATADRVR, for the period of time | |
803 | * between when the ATA command register is written, and then | |
804 | * status is checked. Because waiting for "a while" before | |
805 | * checking status is fine, post SRST, we perform this magic | |
806 | * delay here as well. | |
807 | */ | |
808 | msleep(150); | |
809 | ||
810 | *class = ATA_DEV_NONE; | |
81952c54 | 811 | if (ata_port_online(ap)) { |
4658f79b TH |
812 | if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) { |
813 | rc = -EIO; | |
814 | reason = "device not ready"; | |
815 | goto fail; | |
816 | } | |
817 | *class = ahci_dev_classify(ap); | |
818 | } | |
819 | ||
820 | DPRINTK("EXIT, class=%u\n", *class); | |
821 | return 0; | |
822 | ||
823 | fail_restart: | |
5457f219 | 824 | ahci_start_engine(port_mmio); |
4658f79b | 825 | fail: |
f15a1daf | 826 | ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); |
4658f79b TH |
827 | return rc; |
828 | } | |
829 | ||
2bf2cb26 | 830 | static int ahci_hardreset(struct ata_port *ap, unsigned int *class) |
422b7595 | 831 | { |
4296971d TH |
832 | struct ahci_port_priv *pp = ap->private_data; |
833 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
834 | struct ata_taskfile tf; | |
5457f219 | 835 | void __iomem *mmio = ap->host_set->mmio_base; |
836 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
4bd00f6a TH |
837 | int rc; |
838 | ||
839 | DPRINTK("ENTER\n"); | |
1da177e4 | 840 | |
5457f219 | 841 | ahci_stop_engine(port_mmio); |
4296971d TH |
842 | |
843 | /* clear D2H reception area to properly wait for D2H FIS */ | |
844 | ata_tf_init(ap->device, &tf); | |
845 | tf.command = 0xff; | |
846 | ata_tf_to_fis(&tf, d2h_fis, 0); | |
847 | ||
2bf2cb26 | 848 | rc = sata_std_hardreset(ap, class); |
4296971d | 849 | |
5457f219 | 850 | ahci_start_engine(port_mmio); |
1da177e4 | 851 | |
81952c54 | 852 | if (rc == 0 && ata_port_online(ap)) |
4bd00f6a TH |
853 | *class = ahci_dev_classify(ap); |
854 | if (*class == ATA_DEV_UNKNOWN) | |
855 | *class = ATA_DEV_NONE; | |
1da177e4 | 856 | |
4bd00f6a TH |
857 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
858 | return rc; | |
859 | } | |
860 | ||
861 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) | |
862 | { | |
863 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
864 | u32 new_tmp, tmp; | |
865 | ||
866 | ata_std_postreset(ap, class); | |
02eaa666 JG |
867 | |
868 | /* Make sure port's ATAPI bit is set appropriately */ | |
869 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
4bd00f6a | 870 | if (*class == ATA_DEV_ATAPI) |
02eaa666 JG |
871 | new_tmp |= PORT_CMD_ATAPI; |
872 | else | |
873 | new_tmp &= ~PORT_CMD_ATAPI; | |
874 | if (new_tmp != tmp) { | |
875 | writel(new_tmp, port_mmio + PORT_CMD); | |
876 | readl(port_mmio + PORT_CMD); /* flush */ | |
877 | } | |
1da177e4 LT |
878 | } |
879 | ||
880 | static u8 ahci_check_status(struct ata_port *ap) | |
881 | { | |
1e4f2a96 | 882 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
1da177e4 LT |
883 | |
884 | return readl(mmio + PORT_TFDATA) & 0xFF; | |
885 | } | |
886 | ||
1da177e4 LT |
887 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
888 | { | |
889 | struct ahci_port_priv *pp = ap->private_data; | |
890 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
891 | ||
892 | ata_tf_from_fis(d2h_fis, tf); | |
893 | } | |
894 | ||
12fad3f9 | 895 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
1da177e4 | 896 | { |
cedc9a47 JG |
897 | struct scatterlist *sg; |
898 | struct ahci_sg *ahci_sg; | |
828d09de | 899 | unsigned int n_sg = 0; |
1da177e4 LT |
900 | |
901 | VPRINTK("ENTER\n"); | |
902 | ||
903 | /* | |
904 | * Next, the S/G list. | |
905 | */ | |
12fad3f9 | 906 | ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
cedc9a47 JG |
907 | ata_for_each_sg(sg, qc) { |
908 | dma_addr_t addr = sg_dma_address(sg); | |
909 | u32 sg_len = sg_dma_len(sg); | |
910 | ||
911 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); | |
912 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
913 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); | |
828d09de | 914 | |
cedc9a47 | 915 | ahci_sg++; |
828d09de | 916 | n_sg++; |
1da177e4 | 917 | } |
828d09de JG |
918 | |
919 | return n_sg; | |
1da177e4 LT |
920 | } |
921 | ||
922 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
923 | { | |
a0ea7328 JG |
924 | struct ata_port *ap = qc->ap; |
925 | struct ahci_port_priv *pp = ap->private_data; | |
cc9278ed | 926 | int is_atapi = is_atapi_taskfile(&qc->tf); |
12fad3f9 | 927 | void *cmd_tbl; |
1da177e4 LT |
928 | u32 opts; |
929 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 930 | unsigned int n_elem; |
1da177e4 | 931 | |
1da177e4 LT |
932 | /* |
933 | * Fill in command table information. First, the header, | |
934 | * a SATA Register - Host to Device command FIS. | |
935 | */ | |
12fad3f9 TH |
936 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
937 | ||
938 | ata_tf_to_fis(&qc->tf, cmd_tbl, 0); | |
cc9278ed | 939 | if (is_atapi) { |
12fad3f9 TH |
940 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
941 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
a0ea7328 | 942 | } |
1da177e4 | 943 | |
cc9278ed TH |
944 | n_elem = 0; |
945 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
12fad3f9 | 946 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
1da177e4 | 947 | |
cc9278ed TH |
948 | /* |
949 | * Fill in command slot information. | |
950 | */ | |
951 | opts = cmd_fis_len | n_elem << 16; | |
952 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
953 | opts |= AHCI_CMD_WRITE; | |
954 | if (is_atapi) | |
4b10e559 | 955 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
828d09de | 956 | |
12fad3f9 | 957 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
1da177e4 LT |
958 | } |
959 | ||
78cd52d0 | 960 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 961 | { |
78cd52d0 TH |
962 | struct ahci_port_priv *pp = ap->private_data; |
963 | struct ata_eh_info *ehi = &ap->eh_info; | |
964 | unsigned int err_mask = 0, action = 0; | |
965 | struct ata_queued_cmd *qc; | |
966 | u32 serror; | |
1da177e4 | 967 | |
78cd52d0 | 968 | ata_ehi_clear_desc(ehi); |
1da177e4 | 969 | |
78cd52d0 TH |
970 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
971 | serror = ahci_scr_read(ap, SCR_ERROR); | |
972 | ahci_scr_write(ap, SCR_ERROR, serror); | |
1da177e4 | 973 | |
78cd52d0 TH |
974 | /* analyze @irq_stat */ |
975 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); | |
976 | ||
977 | if (irq_stat & PORT_IRQ_TF_ERR) | |
978 | err_mask |= AC_ERR_DEV; | |
979 | ||
980 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
981 | err_mask |= AC_ERR_HOST_BUS; | |
982 | action |= ATA_EH_SOFTRESET; | |
1da177e4 LT |
983 | } |
984 | ||
78cd52d0 TH |
985 | if (irq_stat & PORT_IRQ_IF_ERR) { |
986 | err_mask |= AC_ERR_ATA_BUS; | |
987 | action |= ATA_EH_SOFTRESET; | |
988 | ata_ehi_push_desc(ehi, ", interface fatal error"); | |
989 | } | |
1da177e4 | 990 | |
78cd52d0 | 991 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
4296971d | 992 | ata_ehi_hotplugged(ehi); |
78cd52d0 TH |
993 | ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ? |
994 | "connection status changed" : "PHY RDY changed"); | |
995 | } | |
996 | ||
997 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
998 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); | |
1da177e4 | 999 | |
78cd52d0 TH |
1000 | err_mask |= AC_ERR_HSM; |
1001 | action |= ATA_EH_SOFTRESET; | |
1002 | ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x", | |
1003 | unk[0], unk[1], unk[2], unk[3]); | |
1004 | } | |
1da177e4 | 1005 | |
78cd52d0 TH |
1006 | /* okay, let's hand over to EH */ |
1007 | ehi->serror |= serror; | |
1008 | ehi->action |= action; | |
b8f6153e | 1009 | |
1da177e4 | 1010 | qc = ata_qc_from_tag(ap, ap->active_tag); |
78cd52d0 TH |
1011 | if (qc) |
1012 | qc->err_mask |= err_mask; | |
1013 | else | |
1014 | ehi->err_mask |= err_mask; | |
a72ec4ce | 1015 | |
78cd52d0 TH |
1016 | if (irq_stat & PORT_IRQ_FREEZE) |
1017 | ata_port_freeze(ap); | |
1018 | else | |
1019 | ata_port_abort(ap); | |
1da177e4 LT |
1020 | } |
1021 | ||
78cd52d0 | 1022 | static void ahci_host_intr(struct ata_port *ap) |
1da177e4 | 1023 | { |
ea6ba10b JG |
1024 | void __iomem *mmio = ap->host_set->mmio_base; |
1025 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
12fad3f9 TH |
1026 | struct ata_eh_info *ehi = &ap->eh_info; |
1027 | u32 status, qc_active; | |
1028 | int rc; | |
1da177e4 LT |
1029 | |
1030 | status = readl(port_mmio + PORT_IRQ_STAT); | |
1031 | writel(status, port_mmio + PORT_IRQ_STAT); | |
1032 | ||
78cd52d0 TH |
1033 | if (unlikely(status & PORT_IRQ_ERROR)) { |
1034 | ahci_error_intr(ap, status); | |
1035 | return; | |
1da177e4 LT |
1036 | } |
1037 | ||
12fad3f9 TH |
1038 | if (ap->sactive) |
1039 | qc_active = readl(port_mmio + PORT_SCR_ACT); | |
1040 | else | |
1041 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
1042 | ||
1043 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); | |
1044 | if (rc > 0) | |
1045 | return; | |
1046 | if (rc < 0) { | |
1047 | ehi->err_mask |= AC_ERR_HSM; | |
1048 | ehi->action |= ATA_EH_SOFTRESET; | |
1049 | ata_port_freeze(ap); | |
1050 | return; | |
1da177e4 LT |
1051 | } |
1052 | ||
2a3917a8 TH |
1053 | /* hmmm... a spurious interupt */ |
1054 | ||
12fad3f9 TH |
1055 | /* some devices send D2H reg with I bit set during NCQ command phase */ |
1056 | if (ap->sactive && status & PORT_IRQ_D2H_REG_FIS) | |
1057 | return; | |
1058 | ||
2a3917a8 TH |
1059 | /* ignore interim PIO setup fis interrupts */ |
1060 | if (ata_tag_valid(ap->active_tag)) { | |
1061 | struct ata_queued_cmd *qc = | |
1062 | ata_qc_from_tag(ap, ap->active_tag); | |
1063 | ||
1064 | if (qc && qc->tf.protocol == ATA_PROT_PIO && | |
1065 | (status & PORT_IRQ_PIOS_FIS)) | |
1066 | return; | |
1067 | } | |
1068 | ||
78cd52d0 TH |
1069 | if (ata_ratelimit()) |
1070 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " | |
12fad3f9 TH |
1071 | "(irq_stat 0x%x active_tag %d sactive 0x%x)\n", |
1072 | status, ap->active_tag, ap->sactive); | |
1da177e4 LT |
1073 | } |
1074 | ||
1075 | static void ahci_irq_clear(struct ata_port *ap) | |
1076 | { | |
1077 | /* TODO */ | |
1078 | } | |
1079 | ||
12fad3f9 | 1080 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance, struct pt_regs *regs) |
1da177e4 LT |
1081 | { |
1082 | struct ata_host_set *host_set = dev_instance; | |
1083 | struct ahci_host_priv *hpriv; | |
1084 | unsigned int i, handled = 0; | |
ea6ba10b | 1085 | void __iomem *mmio; |
1da177e4 LT |
1086 | u32 irq_stat, irq_ack = 0; |
1087 | ||
1088 | VPRINTK("ENTER\n"); | |
1089 | ||
1090 | hpriv = host_set->private_data; | |
1091 | mmio = host_set->mmio_base; | |
1092 | ||
1093 | /* sigh. 0xffffffff is a valid return from h/w */ | |
1094 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1095 | irq_stat &= hpriv->port_map; | |
1096 | if (!irq_stat) | |
1097 | return IRQ_NONE; | |
1098 | ||
1099 | spin_lock(&host_set->lock); | |
1100 | ||
1101 | for (i = 0; i < host_set->n_ports; i++) { | |
1102 | struct ata_port *ap; | |
1da177e4 | 1103 | |
67846b30 JG |
1104 | if (!(irq_stat & (1 << i))) |
1105 | continue; | |
1106 | ||
1da177e4 | 1107 | ap = host_set->ports[i]; |
67846b30 | 1108 | if (ap) { |
78cd52d0 | 1109 | ahci_host_intr(ap); |
67846b30 JG |
1110 | VPRINTK("port %u\n", i); |
1111 | } else { | |
1112 | VPRINTK("port %u (no irq)\n", i); | |
6971ed1f TH |
1113 | if (ata_ratelimit()) |
1114 | dev_printk(KERN_WARNING, host_set->dev, | |
a9524a76 | 1115 | "interrupt on disabled port %u\n", i); |
1da177e4 | 1116 | } |
67846b30 JG |
1117 | |
1118 | irq_ack |= (1 << i); | |
1da177e4 LT |
1119 | } |
1120 | ||
1121 | if (irq_ack) { | |
1122 | writel(irq_ack, mmio + HOST_IRQ_STAT); | |
1123 | handled = 1; | |
1124 | } | |
1125 | ||
78cd52d0 | 1126 | spin_unlock(&host_set->lock); |
1da177e4 LT |
1127 | |
1128 | VPRINTK("EXIT\n"); | |
1129 | ||
1130 | return IRQ_RETVAL(handled); | |
1131 | } | |
1132 | ||
9a3d9eb0 | 1133 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
1134 | { |
1135 | struct ata_port *ap = qc->ap; | |
ea6ba10b | 1136 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
1da177e4 | 1137 | |
12fad3f9 TH |
1138 | if (qc->tf.protocol == ATA_PROT_NCQ) |
1139 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | |
1140 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); | |
1da177e4 LT |
1141 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
1142 | ||
1143 | return 0; | |
1144 | } | |
1145 | ||
78cd52d0 TH |
1146 | static void ahci_freeze(struct ata_port *ap) |
1147 | { | |
1148 | void __iomem *mmio = ap->host_set->mmio_base; | |
1149 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
1150 | ||
1151 | /* turn IRQ off */ | |
1152 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1153 | } | |
1154 | ||
1155 | static void ahci_thaw(struct ata_port *ap) | |
1156 | { | |
1157 | void __iomem *mmio = ap->host_set->mmio_base; | |
1158 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
1159 | u32 tmp; | |
1160 | ||
1161 | /* clear IRQ */ | |
1162 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1163 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1164 | writel(1 << ap->id, mmio + HOST_IRQ_STAT); | |
1165 | ||
1166 | /* turn IRQ back on */ | |
1167 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); | |
1168 | } | |
1169 | ||
1170 | static void ahci_error_handler(struct ata_port *ap) | |
1171 | { | |
5457f219 | 1172 | void __iomem *mmio = ap->host_set->mmio_base; |
1173 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
1174 | ||
b51e9e5d | 1175 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
78cd52d0 | 1176 | /* restart engine */ |
5457f219 | 1177 | ahci_stop_engine(port_mmio); |
1178 | ahci_start_engine(port_mmio); | |
78cd52d0 TH |
1179 | } |
1180 | ||
1181 | /* perform recovery */ | |
4296971d | 1182 | ata_do_eh(ap, ahci_prereset, ahci_softreset, ahci_hardreset, |
f5914a46 | 1183 | ahci_postreset); |
78cd52d0 TH |
1184 | } |
1185 | ||
1186 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) | |
1187 | { | |
1188 | struct ata_port *ap = qc->ap; | |
5457f219 | 1189 | void __iomem *mmio = ap->host_set->mmio_base; |
1190 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
78cd52d0 TH |
1191 | |
1192 | if (qc->flags & ATA_QCFLAG_FAILED) | |
1193 | qc->err_mask |= AC_ERR_OTHER; | |
1194 | ||
1195 | if (qc->err_mask) { | |
1196 | /* make DMA engine forget about the failed command */ | |
5457f219 | 1197 | ahci_stop_engine(port_mmio); |
1198 | ahci_start_engine(port_mmio); | |
78cd52d0 TH |
1199 | } |
1200 | } | |
1201 | ||
254950cd TH |
1202 | static int ahci_port_start(struct ata_port *ap) |
1203 | { | |
1204 | struct device *dev = ap->host_set->dev; | |
1205 | struct ahci_host_priv *hpriv = ap->host_set->private_data; | |
1206 | struct ahci_port_priv *pp; | |
1207 | void __iomem *mmio = ap->host_set->mmio_base; | |
1208 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
1209 | void *mem; | |
1210 | dma_addr_t mem_dma; | |
1211 | int rc; | |
1212 | ||
1213 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); | |
1214 | if (!pp) | |
1215 | return -ENOMEM; | |
1216 | memset(pp, 0, sizeof(*pp)); | |
1217 | ||
1218 | rc = ata_pad_alloc(ap, dev); | |
1219 | if (rc) { | |
1220 | kfree(pp); | |
1221 | return rc; | |
1222 | } | |
1223 | ||
1224 | mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL); | |
1225 | if (!mem) { | |
1226 | ata_pad_free(ap, dev); | |
1227 | kfree(pp); | |
1228 | return -ENOMEM; | |
1229 | } | |
1230 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); | |
1231 | ||
1232 | /* | |
1233 | * First item in chunk of DMA memory: 32-slot command table, | |
1234 | * 32 bytes each in size | |
1235 | */ | |
1236 | pp->cmd_slot = mem; | |
1237 | pp->cmd_slot_dma = mem_dma; | |
1238 | ||
1239 | mem += AHCI_CMD_SLOT_SZ; | |
1240 | mem_dma += AHCI_CMD_SLOT_SZ; | |
1241 | ||
1242 | /* | |
1243 | * Second item: Received-FIS area | |
1244 | */ | |
1245 | pp->rx_fis = mem; | |
1246 | pp->rx_fis_dma = mem_dma; | |
1247 | ||
1248 | mem += AHCI_RX_FIS_SZ; | |
1249 | mem_dma += AHCI_RX_FIS_SZ; | |
1250 | ||
1251 | /* | |
1252 | * Third item: data area for storing a single command | |
1253 | * and its scatter-gather table | |
1254 | */ | |
1255 | pp->cmd_tbl = mem; | |
1256 | pp->cmd_tbl_dma = mem_dma; | |
1257 | ||
1258 | ap->private_data = pp; | |
1259 | ||
0be0aa98 TH |
1260 | /* initialize port */ |
1261 | ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma); | |
254950cd TH |
1262 | |
1263 | return 0; | |
1264 | } | |
1265 | ||
1266 | static void ahci_port_stop(struct ata_port *ap) | |
1267 | { | |
1268 | struct device *dev = ap->host_set->dev; | |
0be0aa98 | 1269 | struct ahci_host_priv *hpriv = ap->host_set->private_data; |
254950cd TH |
1270 | struct ahci_port_priv *pp = ap->private_data; |
1271 | void __iomem *mmio = ap->host_set->mmio_base; | |
1272 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
0be0aa98 TH |
1273 | const char *emsg = NULL; |
1274 | int rc; | |
254950cd | 1275 | |
0be0aa98 TH |
1276 | /* de-initialize port */ |
1277 | rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); | |
1278 | if (rc) | |
1279 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | |
254950cd TH |
1280 | |
1281 | ap->private_data = NULL; | |
1282 | dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, | |
1283 | pp->cmd_slot, pp->cmd_slot_dma); | |
1284 | ata_pad_free(ap, dev); | |
1285 | kfree(pp); | |
1286 | } | |
1287 | ||
1da177e4 LT |
1288 | static void ahci_setup_port(struct ata_ioports *port, unsigned long base, |
1289 | unsigned int port_idx) | |
1290 | { | |
1291 | VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx); | |
1292 | base = ahci_port_base_ul(base, port_idx); | |
1293 | VPRINTK("base now==0x%lx\n", base); | |
1294 | ||
1295 | port->cmd_addr = base; | |
1296 | port->scr_addr = base + PORT_SCR; | |
1297 | ||
1298 | VPRINTK("EXIT\n"); | |
1299 | } | |
1300 | ||
1301 | static int ahci_host_init(struct ata_probe_ent *probe_ent) | |
1302 | { | |
1303 | struct ahci_host_priv *hpriv = probe_ent->private_data; | |
1304 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
1305 | void __iomem *mmio = probe_ent->mmio_base; | |
0be0aa98 | 1306 | unsigned int i, using_dac; |
1da177e4 | 1307 | int rc; |
1da177e4 | 1308 | |
d91542c1 TH |
1309 | rc = ahci_reset_controller(mmio, pdev); |
1310 | if (rc) | |
1311 | return rc; | |
1da177e4 LT |
1312 | |
1313 | hpriv->cap = readl(mmio + HOST_CAP); | |
1314 | hpriv->port_map = readl(mmio + HOST_PORTS_IMPL); | |
1315 | probe_ent->n_ports = (hpriv->cap & 0x1f) + 1; | |
1316 | ||
1317 | VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n", | |
1318 | hpriv->cap, hpriv->port_map, probe_ent->n_ports); | |
1319 | ||
1320 | using_dac = hpriv->cap & HOST_CAP_64; | |
1321 | if (using_dac && | |
1322 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
1323 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1324 | if (rc) { | |
1325 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1326 | if (rc) { | |
a9524a76 JG |
1327 | dev_printk(KERN_ERR, &pdev->dev, |
1328 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
1329 | return rc; |
1330 | } | |
1331 | } | |
1da177e4 LT |
1332 | } else { |
1333 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1334 | if (rc) { | |
a9524a76 JG |
1335 | dev_printk(KERN_ERR, &pdev->dev, |
1336 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
1337 | return rc; |
1338 | } | |
1339 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1340 | if (rc) { | |
a9524a76 JG |
1341 | dev_printk(KERN_ERR, &pdev->dev, |
1342 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
1343 | return rc; |
1344 | } | |
1345 | } | |
1346 | ||
d91542c1 TH |
1347 | for (i = 0; i < probe_ent->n_ports; i++) |
1348 | ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i); | |
1da177e4 | 1349 | |
d91542c1 | 1350 | ahci_init_controller(mmio, pdev, probe_ent->n_ports, hpriv->cap); |
1da177e4 LT |
1351 | |
1352 | pci_set_master(pdev); | |
1353 | ||
1354 | return 0; | |
1355 | } | |
1356 | ||
1da177e4 LT |
1357 | static void ahci_print_info(struct ata_probe_ent *probe_ent) |
1358 | { | |
1359 | struct ahci_host_priv *hpriv = probe_ent->private_data; | |
1360 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
ea6ba10b | 1361 | void __iomem *mmio = probe_ent->mmio_base; |
1da177e4 LT |
1362 | u32 vers, cap, impl, speed; |
1363 | const char *speed_s; | |
1364 | u16 cc; | |
1365 | const char *scc_s; | |
1366 | ||
1367 | vers = readl(mmio + HOST_VERSION); | |
1368 | cap = hpriv->cap; | |
1369 | impl = hpriv->port_map; | |
1370 | ||
1371 | speed = (cap >> 20) & 0xf; | |
1372 | if (speed == 1) | |
1373 | speed_s = "1.5"; | |
1374 | else if (speed == 2) | |
1375 | speed_s = "3"; | |
1376 | else | |
1377 | speed_s = "?"; | |
1378 | ||
1379 | pci_read_config_word(pdev, 0x0a, &cc); | |
1380 | if (cc == 0x0101) | |
1381 | scc_s = "IDE"; | |
1382 | else if (cc == 0x0106) | |
1383 | scc_s = "SATA"; | |
1384 | else if (cc == 0x0104) | |
1385 | scc_s = "RAID"; | |
1386 | else | |
1387 | scc_s = "unknown"; | |
1388 | ||
a9524a76 JG |
1389 | dev_printk(KERN_INFO, &pdev->dev, |
1390 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 LT |
1391 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
1392 | , | |
1da177e4 LT |
1393 | |
1394 | (vers >> 24) & 0xff, | |
1395 | (vers >> 16) & 0xff, | |
1396 | (vers >> 8) & 0xff, | |
1397 | vers & 0xff, | |
1398 | ||
1399 | ((cap >> 8) & 0x1f) + 1, | |
1400 | (cap & 0x1f) + 1, | |
1401 | speed_s, | |
1402 | impl, | |
1403 | scc_s); | |
1404 | ||
a9524a76 JG |
1405 | dev_printk(KERN_INFO, &pdev->dev, |
1406 | "flags: " | |
1da177e4 LT |
1407 | "%s%s%s%s%s%s" |
1408 | "%s%s%s%s%s%s%s\n" | |
1409 | , | |
1da177e4 LT |
1410 | |
1411 | cap & (1 << 31) ? "64bit " : "", | |
1412 | cap & (1 << 30) ? "ncq " : "", | |
1413 | cap & (1 << 28) ? "ilck " : "", | |
1414 | cap & (1 << 27) ? "stag " : "", | |
1415 | cap & (1 << 26) ? "pm " : "", | |
1416 | cap & (1 << 25) ? "led " : "", | |
1417 | ||
1418 | cap & (1 << 24) ? "clo " : "", | |
1419 | cap & (1 << 19) ? "nz " : "", | |
1420 | cap & (1 << 18) ? "only " : "", | |
1421 | cap & (1 << 17) ? "pmp " : "", | |
1422 | cap & (1 << 15) ? "pio " : "", | |
1423 | cap & (1 << 14) ? "slum " : "", | |
1424 | cap & (1 << 13) ? "part " : "" | |
1425 | ); | |
1426 | } | |
1427 | ||
1428 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
1429 | { | |
1430 | static int printed_version; | |
1431 | struct ata_probe_ent *probe_ent = NULL; | |
1432 | struct ahci_host_priv *hpriv; | |
1433 | unsigned long base; | |
ea6ba10b | 1434 | void __iomem *mmio_base; |
1da177e4 | 1435 | unsigned int board_idx = (unsigned int) ent->driver_data; |
907f4678 | 1436 | int have_msi, pci_dev_busy = 0; |
1da177e4 LT |
1437 | int rc; |
1438 | ||
1439 | VPRINTK("ENTER\n"); | |
1440 | ||
12fad3f9 TH |
1441 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
1442 | ||
1da177e4 | 1443 | if (!printed_version++) |
a9524a76 | 1444 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 1445 | |
9545b578 | 1446 | /* JMicron-specific fixup: make sure we're in AHCI mode */ |
1447 | /* This is protected from races with ata_jmicron by the pci probe | |
1448 | locking */ | |
1449 | if (pdev->vendor == PCI_VENDOR_ID_JMICRON) { | |
1450 | /* AHCI enable, AHCI on function 0 */ | |
1451 | pci_write_config_byte(pdev, 0x41, 0xa1); | |
1452 | /* Function 1 is the PATA controller */ | |
1453 | if (PCI_FUNC(pdev->devfn)) | |
1454 | return -ENODEV; | |
1455 | } | |
1456 | ||
1da177e4 LT |
1457 | rc = pci_enable_device(pdev); |
1458 | if (rc) | |
1459 | return rc; | |
1460 | ||
1461 | rc = pci_request_regions(pdev, DRV_NAME); | |
1462 | if (rc) { | |
1463 | pci_dev_busy = 1; | |
1464 | goto err_out; | |
1465 | } | |
1466 | ||
907f4678 JG |
1467 | if (pci_enable_msi(pdev) == 0) |
1468 | have_msi = 1; | |
1469 | else { | |
1470 | pci_intx(pdev, 1); | |
1471 | have_msi = 0; | |
1472 | } | |
1da177e4 LT |
1473 | |
1474 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
1475 | if (probe_ent == NULL) { | |
1476 | rc = -ENOMEM; | |
907f4678 | 1477 | goto err_out_msi; |
1da177e4 LT |
1478 | } |
1479 | ||
1480 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
1481 | probe_ent->dev = pci_dev_to_dev(pdev); | |
1482 | INIT_LIST_HEAD(&probe_ent->node); | |
1483 | ||
374b1873 | 1484 | mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0); |
1da177e4 LT |
1485 | if (mmio_base == NULL) { |
1486 | rc = -ENOMEM; | |
1487 | goto err_out_free_ent; | |
1488 | } | |
1489 | base = (unsigned long) mmio_base; | |
1490 | ||
1491 | hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL); | |
1492 | if (!hpriv) { | |
1493 | rc = -ENOMEM; | |
1494 | goto err_out_iounmap; | |
1495 | } | |
1496 | memset(hpriv, 0, sizeof(*hpriv)); | |
1497 | ||
1498 | probe_ent->sht = ahci_port_info[board_idx].sht; | |
1499 | probe_ent->host_flags = ahci_port_info[board_idx].host_flags; | |
1500 | probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask; | |
1501 | probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask; | |
1502 | probe_ent->port_ops = ahci_port_info[board_idx].port_ops; | |
1503 | ||
1504 | probe_ent->irq = pdev->irq; | |
1d6f359a | 1505 | probe_ent->irq_flags = IRQF_SHARED; |
1da177e4 LT |
1506 | probe_ent->mmio_base = mmio_base; |
1507 | probe_ent->private_data = hpriv; | |
1508 | ||
4b0060f4 JG |
1509 | if (have_msi) |
1510 | hpriv->flags |= AHCI_FLAG_MSI; | |
907f4678 | 1511 | |
1da177e4 LT |
1512 | /* initialize adapter */ |
1513 | rc = ahci_host_init(probe_ent); | |
1514 | if (rc) | |
1515 | goto err_out_hpriv; | |
1516 | ||
71f0737b TH |
1517 | if (!(probe_ent->host_flags & AHCI_FLAG_NO_NCQ) && |
1518 | (hpriv->cap & HOST_CAP_NCQ)) | |
12fad3f9 TH |
1519 | probe_ent->host_flags |= ATA_FLAG_NCQ; |
1520 | ||
1da177e4 LT |
1521 | ahci_print_info(probe_ent); |
1522 | ||
1523 | /* FIXME: check ata_device_add return value */ | |
1524 | ata_device_add(probe_ent); | |
1525 | kfree(probe_ent); | |
1526 | ||
1527 | return 0; | |
1528 | ||
1529 | err_out_hpriv: | |
1530 | kfree(hpriv); | |
1531 | err_out_iounmap: | |
374b1873 | 1532 | pci_iounmap(pdev, mmio_base); |
1da177e4 LT |
1533 | err_out_free_ent: |
1534 | kfree(probe_ent); | |
907f4678 JG |
1535 | err_out_msi: |
1536 | if (have_msi) | |
1537 | pci_disable_msi(pdev); | |
1538 | else | |
1539 | pci_intx(pdev, 0); | |
1da177e4 LT |
1540 | pci_release_regions(pdev); |
1541 | err_out: | |
1542 | if (!pci_dev_busy) | |
1543 | pci_disable_device(pdev); | |
1544 | return rc; | |
1545 | } | |
1546 | ||
907f4678 JG |
1547 | static void ahci_remove_one (struct pci_dev *pdev) |
1548 | { | |
1549 | struct device *dev = pci_dev_to_dev(pdev); | |
1550 | struct ata_host_set *host_set = dev_get_drvdata(dev); | |
1551 | struct ahci_host_priv *hpriv = host_set->private_data; | |
907f4678 JG |
1552 | unsigned int i; |
1553 | int have_msi; | |
1554 | ||
720ba126 TH |
1555 | for (i = 0; i < host_set->n_ports; i++) |
1556 | ata_port_detach(host_set->ports[i]); | |
907f4678 | 1557 | |
4b0060f4 | 1558 | have_msi = hpriv->flags & AHCI_FLAG_MSI; |
907f4678 | 1559 | free_irq(host_set->irq, host_set); |
907f4678 JG |
1560 | |
1561 | for (i = 0; i < host_set->n_ports; i++) { | |
720ba126 | 1562 | struct ata_port *ap = host_set->ports[i]; |
907f4678 JG |
1563 | |
1564 | ata_scsi_release(ap->host); | |
1565 | scsi_host_put(ap->host); | |
1566 | } | |
1567 | ||
e005f01d | 1568 | kfree(hpriv); |
374b1873 | 1569 | pci_iounmap(pdev, host_set->mmio_base); |
ead5de99 JG |
1570 | kfree(host_set); |
1571 | ||
907f4678 JG |
1572 | if (have_msi) |
1573 | pci_disable_msi(pdev); | |
1574 | else | |
1575 | pci_intx(pdev, 0); | |
1576 | pci_release_regions(pdev); | |
907f4678 JG |
1577 | pci_disable_device(pdev); |
1578 | dev_set_drvdata(dev, NULL); | |
1579 | } | |
1da177e4 LT |
1580 | |
1581 | static int __init ahci_init(void) | |
1582 | { | |
1583 | return pci_module_init(&ahci_pci_driver); | |
1584 | } | |
1585 | ||
1da177e4 LT |
1586 | static void __exit ahci_exit(void) |
1587 | { | |
1588 | pci_unregister_driver(&ahci_pci_driver); | |
1589 | } | |
1590 | ||
1591 | ||
1592 | MODULE_AUTHOR("Jeff Garzik"); | |
1593 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
1594 | MODULE_LICENSE("GPL"); | |
1595 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 1596 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
1597 | |
1598 | module_init(ahci_init); | |
1599 | module_exit(ahci_exit); |