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[PATCH] sata_sil: convert to new probing mechanism and add hotplug support
[deliverable/linux.git] / drivers / scsi / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
87507cfd 43#include <linux/dma-mapping.h>
a9524a76 44#include <linux/device.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4
LT		 47#include <linux/libata.h>
48#include <asm/io.h>
49
50#define DRV_NAME "ahci"
af64371a 51#define DRV_VERSION "1.3"
1da177e4
LT		 52
53
54enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
12fad3f9 59 AHCI_MAX_CMDS = 32,
dd410ff1 60 AHCI_CMD_SZ = 32,
12fad3f9 61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 62 AHCI_RX_FIS_SZ = 256,
a0ea7328 63 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 68 AHCI_RX_FIS_SZ,
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
4b10e559 72 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 75
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
78cd52d0 77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 78
79 board_ahci = 0,
bf2af2a2 80 board_ahci_vt8251 = 1,
1da177e4
LT		 81
82 /* global controller registers */
83 HOST_CAP = 0x00, /* host capabilities */
84 HOST_CTL = 0x04, /* global host control */
85 HOST_IRQ_STAT = 0x08, /* interrupt status */
86 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
87 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
88
89 /* HOST_CTL bits */
90 HOST_RESET = (1 << 0), /* reset controller; self-clear */
91 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
92 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
93
94 /* HOST_CAP bits */
22b49985 95 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
979db803 96 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 97 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 98
99 /* registers for each SATA port */
100 PORT_LST_ADDR = 0x00, /* command list DMA addr */
101 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
102 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
103 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
104 PORT_IRQ_STAT = 0x10, /* interrupt status */
105 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
106 PORT_CMD = 0x18, /* port command */
107 PORT_TFDATA = 0x20, /* taskfile data */
108 PORT_SIG = 0x24, /* device TF signature */
109 PORT_CMD_ISSUE = 0x38, /* command issue */
110 PORT_SCR = 0x28, /* SATA phy register block */
111 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
112 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
113 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
114 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
115
116 /* PORT_IRQ_{STAT,MASK} bits */
117 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
118 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
119 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
120 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
121 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
122 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
123 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
124 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
125
126 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
127 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
128 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
129 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
130 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
131 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
132 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
133 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
134 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
135
78cd52d0
TH		 136 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
137 PORT_IRQ_IF_ERR |
138 PORT_IRQ_CONNECT |
139 PORT_IRQ_UNK_FIS,
140 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
141 PORT_IRQ_TF_ERR |
142 PORT_IRQ_HBUS_DATA_ERR,
143 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
144 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
145 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 146
147 /* PORT_CMD bits */
02eaa666 148 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
1da177e4
LT		 149 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
150 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
151 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 152 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 153 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
154 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
155 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
156
157 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
158 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
159 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4
JG		 160
161 /* hpriv->flags bits */
162 AHCI_FLAG_MSI = (1 << 0),
bf2af2a2
BJ		 163
164 /* ap->flags bits */
165 AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24),
1da177e4
LT		 166};
167
168struct ahci_cmd_hdr {
169 u32 opts;
170 u32 status;
171 u32 tbl_addr;
172 u32 tbl_addr_hi;
173 u32 reserved[4];
174};
175
176struct ahci_sg {
177 u32 addr;
178 u32 addr_hi;
179 u32 reserved;
180 u32 flags_size;
181};
182
183struct ahci_host_priv {
184 unsigned long flags;
185 u32 cap; /* cache of HOST_CAP register */
186 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
187};
188
189struct ahci_port_priv {
190 struct ahci_cmd_hdr *cmd_slot;
191 dma_addr_t cmd_slot_dma;
192 void *cmd_tbl;
193 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 194 void *rx_fis;
195 dma_addr_t rx_fis_dma;
196};
197
198static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
199static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
200static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 201static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
1da177e4 202static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
4bd00f6a 203static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes);
1da177e4 204static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 205static int ahci_port_start(struct ata_port *ap);
206static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 207static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
208static void ahci_qc_prep(struct ata_queued_cmd *qc);
209static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 210static void ahci_freeze(struct ata_port *ap);
211static void ahci_thaw(struct ata_port *ap);
212static void ahci_error_handler(struct ata_port *ap);
213static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
907f4678 214static void ahci_remove_one (struct pci_dev *pdev);
1da177e4 215
193515d5 216static struct scsi_host_template ahci_sht = {
1da177e4
LT		 217 .module = THIS_MODULE,
218 .name = DRV_NAME,
219 .ioctl = ata_scsi_ioctl,
220 .queuecommand = ata_scsi_queuecmd,
12fad3f9
TH		 221 .change_queue_depth = ata_scsi_change_queue_depth,
222 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4
LT		 223 .this_id = ATA_SHT_THIS_ID,
224 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 225 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
226 .emulated = ATA_SHT_EMULATED,
227 .use_clustering = AHCI_USE_CLUSTERING,
228 .proc_name = DRV_NAME,
229 .dma_boundary = AHCI_DMA_BOUNDARY,
230 .slave_configure = ata_scsi_slave_config,
ccf68c34 231 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 232 .bios_param = ata_std_bios_param,
1da177e4
LT		 233};
234
057ace5e 235static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 236 .port_disable = ata_port_disable,
237
238 .check_status = ahci_check_status,
239 .check_altstatus = ahci_check_status,
1da177e4
LT		 240 .dev_select = ata_noop_dev_select,
241
242 .tf_read = ahci_tf_read,
243
4bd00f6a 244 .probe_reset = ahci_probe_reset,
1da177e4
LT		 245
246 .qc_prep = ahci_qc_prep,
247 .qc_issue = ahci_qc_issue,
248
1da177e4
LT		 249 .irq_handler = ahci_interrupt,
250 .irq_clear = ahci_irq_clear,
251
252 .scr_read = ahci_scr_read,
253 .scr_write = ahci_scr_write,
254
78cd52d0
TH		 255 .freeze = ahci_freeze,
256 .thaw = ahci_thaw,
257
258 .error_handler = ahci_error_handler,
259 .post_internal_cmd = ahci_post_internal_cmd,
260
1da177e4
LT		 261 .port_start = ahci_port_start,
262 .port_stop = ahci_port_stop,
1da177e4
LT		 263};
264
98ac62de 265static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 266 /* board_ahci */
267 {
268 .sht = &ahci_sht,
269 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
4bd00f6a 270 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
7da79312 271 .pio_mask = 0x1f, /* pio0-4 */
1da177e4
LT		 272 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
273 .port_ops = &ahci_ops,
274 },
bf2af2a2
BJ		 275 /* board_ahci_vt8251 */
276 {
277 .sht = &ahci_sht,
278 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
279 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
280 AHCI_FLAG_RESET_NEEDS_CLO,
281 .pio_mask = 0x1f, /* pio0-4 */
282 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
283 .port_ops = &ahci_ops,
284 },
1da177e4
LT		 285};
286
3b7d697d 287static const struct pci_device_id ahci_pci_tbl[] = {
1da177e4
LT		 288 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
289 board_ahci }, /* ICH6 */
290 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
291 board_ahci }, /* ICH6M */
292 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
293 board_ahci }, /* ICH7 */
294 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
295 board_ahci }, /* ICH7M */
296 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
297 board_ahci }, /* ICH7R */
298 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
299 board_ahci }, /* ULi M5288 */
680d3235
JG		 300 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
301 board_ahci }, /* ESB2 */
302 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
303 board_ahci }, /* ESB2 */
304 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
305 board_ahci }, /* ESB2 */
3db368f7
JG		 306 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
307 board_ahci }, /* ICH7-M DH */
f285757c
JG		 308 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
309 board_ahci }, /* ICH8 */
310 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
311 board_ahci }, /* ICH8 */
312 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
313 board_ahci }, /* ICH8 */
314 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
315 board_ahci }, /* ICH8M */
316 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
317 board_ahci }, /* ICH8M */
bd12097c
JG		 318 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
319 board_ahci }, /* JMicron JMB360 */
9220a2d0
JG		 320 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
321 board_ahci }, /* JMicron JMB363 */
8b316a39
JG		 322 { PCI_VENDOR_ID_ATI, 0x4380, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
323 board_ahci }, /* ATI SB600 non-raid */
324 { PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
325 board_ahci }, /* ATI SB600 raid */
bf2af2a2
BJ		 326 { PCI_VENDOR_ID_VIA, 0x3349, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
327 board_ahci_vt8251 }, /* VIA VT8251 */
1da177e4
LT		 328 { } /* terminate list */
329};
330
331
332static struct pci_driver ahci_pci_driver = {
333 .name = DRV_NAME,
334 .id_table = ahci_pci_tbl,
335 .probe = ahci_init_one,
907f4678 336 .remove = ahci_remove_one,
1da177e4
LT		 337};
338
339
340static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
341{
342 return base + 0x100 + (port * 0x80);
343}
344
ea6ba10b 345static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
1da177e4 346{
ea6ba10b 347 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
1da177e4
LT		 348}
349
1da177e4
LT		 350static int ahci_port_start(struct ata_port *ap)
351{
352 struct device *dev = ap->host_set->dev;
353 struct ahci_host_priv *hpriv = ap->host_set->private_data;
354 struct ahci_port_priv *pp;
ea6ba10b
JG		 355 void __iomem *mmio = ap->host_set->mmio_base;
356 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
357 void *mem;
1da177e4 358 dma_addr_t mem_dma;
6037d6bb 359 int rc;
1da177e4 360
1da177e4 361 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
0a139e79
TH		 362 if (!pp)
363 return -ENOMEM;
1da177e4
LT		 364 memset(pp, 0, sizeof(*pp));
365
6037d6bb
JG		 366 rc = ata_pad_alloc(ap, dev);
367 if (rc) {
cedc9a47 368 kfree(pp);
6037d6bb 369 return rc;
cedc9a47
JG		 370 }
371
1da177e4
LT		 372 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
373 if (!mem) {
6037d6bb 374 ata_pad_free(ap, dev);
0a139e79
TH		 375 kfree(pp);
376 return -ENOMEM;
1da177e4
LT		 377 }
378 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
379
380 /*
381 * First item in chunk of DMA memory: 32-slot command table,
382 * 32 bytes each in size
383 */
384 pp->cmd_slot = mem;
385 pp->cmd_slot_dma = mem_dma;
386
387 mem += AHCI_CMD_SLOT_SZ;
388 mem_dma += AHCI_CMD_SLOT_SZ;
389
390 /*
391 * Second item: Received-FIS area
392 */
393 pp->rx_fis = mem;
394 pp->rx_fis_dma = mem_dma;
395
396 mem += AHCI_RX_FIS_SZ;
397 mem_dma += AHCI_RX_FIS_SZ;
398
399 /*
400 * Third item: data area for storing a single command
401 * and its scatter-gather table
402 */
403 pp->cmd_tbl = mem;
404 pp->cmd_tbl_dma = mem_dma;
405
1da177e4
LT		 406 ap->private_data = pp;
407
408 if (hpriv->cap & HOST_CAP_64)
409 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
410 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
411 readl(port_mmio + PORT_LST_ADDR); /* flush */
412
413 if (hpriv->cap & HOST_CAP_64)
414 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
415 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
416 readl(port_mmio + PORT_FIS_ADDR); /* flush */
417
418 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
419 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
420 PORT_CMD_START, port_mmio + PORT_CMD);
421 readl(port_mmio + PORT_CMD); /* flush */
422
423 return 0;
1da177e4
LT		 424}
425
426
427static void ahci_port_stop(struct ata_port *ap)
428{
429 struct device *dev = ap->host_set->dev;
430 struct ahci_port_priv *pp = ap->private_data;
ea6ba10b
JG		 431 void __iomem *mmio = ap->host_set->mmio_base;
432 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1da177e4
LT		 433 u32 tmp;
434
435 tmp = readl(port_mmio + PORT_CMD);
436 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
437 writel(tmp, port_mmio + PORT_CMD);
438 readl(port_mmio + PORT_CMD); /* flush */
439
440 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
441 * this is slightly incorrect.
442 */
443 msleep(500);
444
445 ap->private_data = NULL;
446 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
447 pp->cmd_slot, pp->cmd_slot_dma);
6037d6bb 448 ata_pad_free(ap, dev);
1da177e4 449 kfree(pp);
1da177e4
LT		 450}
451
452static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
453{
454 unsigned int sc_reg;
455
456 switch (sc_reg_in) {
457 case SCR_STATUS: sc_reg = 0; break;
458 case SCR_CONTROL: sc_reg = 1; break;
459 case SCR_ERROR: sc_reg = 2; break;
460 case SCR_ACTIVE: sc_reg = 3; break;
461 default:
462 return 0xffffffffU;
463 }
464
1e4f2a96 465 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 466}
467
468
469static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
470 u32 val)
471{
472 unsigned int sc_reg;
473
474 switch (sc_reg_in) {
475 case SCR_STATUS: sc_reg = 0; break;
476 case SCR_CONTROL: sc_reg = 1; break;
477 case SCR_ERROR: sc_reg = 2; break;
478 case SCR_ACTIVE: sc_reg = 3; break;
479 default:
480 return;
481 }
482
1e4f2a96 483 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 484}
485
7c76d1e8
TH		 486static int ahci_stop_engine(struct ata_port *ap)
487{
488 void __iomem *mmio = ap->host_set->mmio_base;
489 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
490 int work;
491 u32 tmp;
492
493 tmp = readl(port_mmio + PORT_CMD);
494 tmp &= ~PORT_CMD_START;
495 writel(tmp, port_mmio + PORT_CMD);
496
497 /* wait for engine to stop. TODO: this could be
498 * as long as 500 msec
499 */
500 work = 1000;
501 while (work-- > 0) {
502 tmp = readl(port_mmio + PORT_CMD);
503 if ((tmp & PORT_CMD_LIST_ON) == 0)
504 return 0;
505 udelay(10);
506 }
507
508 return -EIO;
509}
510
511static void ahci_start_engine(struct ata_port *ap)
512{
513 void __iomem *mmio = ap->host_set->mmio_base;
514 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
515 u32 tmp;
516
517 tmp = readl(port_mmio + PORT_CMD);
518 tmp |= PORT_CMD_START;
519 writel(tmp, port_mmio + PORT_CMD);
520 readl(port_mmio + PORT_CMD); /* flush */
521}
522
422b7595 523static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4
LT		 524{
525 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
526 struct ata_taskfile tf;
422b7595
TH		 527 u32 tmp;
528
529 tmp = readl(port_mmio + PORT_SIG);
530 tf.lbah = (tmp >> 24) & 0xff;
531 tf.lbam = (tmp >> 16) & 0xff;
532 tf.lbal = (tmp >> 8) & 0xff;
533 tf.nsect = (tmp) & 0xff;
534
535 return ata_dev_classify(&tf);
536}
537
12fad3f9
TH		 538static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
539 u32 opts)
cc9278ed 540{
12fad3f9
TH		 541 dma_addr_t cmd_tbl_dma;
542
543 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
544
545 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
546 pp->cmd_slot[tag].status = 0;
547 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
548 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 549}
550
bf2af2a2 551static int ahci_clo(struct ata_port *ap)
4658f79b 552{
bf2af2a2 553 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
4658f79b 554 struct ahci_host_priv *hpriv = ap->host_set->private_data;
bf2af2a2
BJ		 555 u32 tmp;
556
557 if (!(hpriv->cap & HOST_CAP_CLO))
558 return -EOPNOTSUPP;
559
560 tmp = readl(port_mmio + PORT_CMD);
561 tmp |= PORT_CMD_CLO;
562 writel(tmp, port_mmio + PORT_CMD);
563
564 tmp = ata_wait_register(port_mmio + PORT_CMD,
565 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
566 if (tmp & PORT_CMD_CLO)
567 return -EIO;
568
569 return 0;
570}
571
572static int ahci_softreset(struct ata_port *ap, unsigned int *class)
573{
4658f79b
TH		 574 struct ahci_port_priv *pp = ap->private_data;
575 void __iomem *mmio = ap->host_set->mmio_base;
576 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
577 const u32 cmd_fis_len = 5; /* five dwords */
578 const char *reason = NULL;
579 struct ata_taskfile tf;
75fe1806 580 u32 tmp;
4658f79b
TH		 581 u8 *fis;
582 int rc;
583
584 DPRINTK("ENTER\n");
585
81952c54 586 if (ata_port_offline(ap)) {
c2a65852
TH		 587 DPRINTK("PHY reports no device\n");
588 *class = ATA_DEV_NONE;
589 return 0;
590 }
591
4658f79b
TH		 592 /* prepare for SRST (AHCI-1.1 10.4.1) */
593 rc = ahci_stop_engine(ap);
594 if (rc) {
595 reason = "failed to stop engine";
596 goto fail_restart;
597 }
598
599 /* check BUSY/DRQ, perform Command List Override if necessary */
600 ahci_tf_read(ap, &tf);
601 if (tf.command & (ATA_BUSY | ATA_DRQ)) {
bf2af2a2 602 rc = ahci_clo(ap);
4658f79b 603
bf2af2a2
BJ		 604 if (rc == -EOPNOTSUPP) {
605 reason = "port busy but CLO unavailable";
606 goto fail_restart;
607 } else if (rc) {
608 reason = "port busy but CLO failed";
4658f79b
TH		 609 goto fail_restart;
610 }
611 }
612
613 /* restart engine */
614 ahci_start_engine(ap);
615
3373efd8 616 ata_tf_init(ap->device, &tf);
4658f79b
TH		 617 fis = pp->cmd_tbl;
618
619 /* issue the first D2H Register FIS */
12fad3f9
TH		 620 ahci_fill_cmd_slot(pp, 0,
621 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
4658f79b
TH		 622
623 tf.ctl |= ATA_SRST;
624 ata_tf_to_fis(&tf, fis, 0);
625 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
626
627 writel(1, port_mmio + PORT_CMD_ISSUE);
4658f79b 628
75fe1806
TH		 629 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
630 if (tmp & 0x1) {
4658f79b
TH		 631 rc = -EIO;
632 reason = "1st FIS failed";
633 goto fail;
634 }
635
636 /* spec says at least 5us, but be generous and sleep for 1ms */
637 msleep(1);
638
639 /* issue the second D2H Register FIS */
12fad3f9 640 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
4658f79b
TH		 641
642 tf.ctl &= ~ATA_SRST;
643 ata_tf_to_fis(&tf, fis, 0);
644 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
645
646 writel(1, port_mmio + PORT_CMD_ISSUE);
647 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
648
649 /* spec mandates ">= 2ms" before checking status.
650 * We wait 150ms, because that was the magic delay used for
651 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
652 * between when the ATA command register is written, and then
653 * status is checked. Because waiting for "a while" before
654 * checking status is fine, post SRST, we perform this magic
655 * delay here as well.
656 */
657 msleep(150);
658
659 *class = ATA_DEV_NONE;
81952c54 660 if (ata_port_online(ap)) {
4658f79b
TH		 661 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
662 rc = -EIO;
663 reason = "device not ready";
664 goto fail;
665 }
666 *class = ahci_dev_classify(ap);
667 }
668
669 DPRINTK("EXIT, class=%u\n", *class);
670 return 0;
671
672 fail_restart:
673 ahci_start_engine(ap);
674 fail:
f15a1daf 675 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 676 return rc;
677}
678
2bf2cb26 679static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
422b7595 680{
4bd00f6a
TH		 681 int rc;
682
683 DPRINTK("ENTER\n");
1da177e4 684
e0bfd149 685 ahci_stop_engine(ap);
2bf2cb26 686 rc = sata_std_hardreset(ap, class);
e0bfd149 687 ahci_start_engine(ap);
1da177e4 688
81952c54 689 if (rc == 0 && ata_port_online(ap))
4bd00f6a
TH		 690 *class = ahci_dev_classify(ap);
691 if (*class == ATA_DEV_UNKNOWN)
692 *class = ATA_DEV_NONE;
1da177e4 693
4bd00f6a
TH		 694 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
695 return rc;
696}
697
698static void ahci_postreset(struct ata_port *ap, unsigned int *class)
699{
700 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
701 u32 new_tmp, tmp;
702
703 ata_std_postreset(ap, class);
02eaa666
JG		 704
705 /* Make sure port's ATAPI bit is set appropriately */
706 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 707 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 708 new_tmp |= PORT_CMD_ATAPI;
709 else
710 new_tmp &= ~PORT_CMD_ATAPI;
711 if (new_tmp != tmp) {
712 writel(new_tmp, port_mmio + PORT_CMD);
713 readl(port_mmio + PORT_CMD); /* flush */
714 }
1da177e4
LT		 715}
716
4bd00f6a
TH		 717static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes)
718{
bf2af2a2
BJ		 719 if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) &&
720 (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) {
721 /* ATA_BUSY hasn't cleared, so send a CLO */
722 ahci_clo(ap);
723 }
724
4658f79b
TH		 725 return ata_drive_probe_reset(ap, ata_std_probeinit,
726 ahci_softreset, ahci_hardreset,
4bd00f6a
TH		 727 ahci_postreset, classes);
728}
729
1da177e4
LT		 730static u8 ahci_check_status(struct ata_port *ap)
731{
1e4f2a96 732 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4
LT		 733
734 return readl(mmio + PORT_TFDATA) & 0xFF;
735}
736
1da177e4
LT		 737static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
738{
739 struct ahci_port_priv *pp = ap->private_data;
740 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
741
742 ata_tf_from_fis(d2h_fis, tf);
743}
744
12fad3f9 745static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 746{
cedc9a47
JG		 747 struct scatterlist *sg;
748 struct ahci_sg *ahci_sg;
828d09de 749 unsigned int n_sg = 0;
1da177e4
LT		 750
751 VPRINTK("ENTER\n");
752
753 /*
754 * Next, the S/G list.
755 */
12fad3f9 756 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
cedc9a47
JG		 757 ata_for_each_sg(sg, qc) {
758 dma_addr_t addr = sg_dma_address(sg);
759 u32 sg_len = sg_dma_len(sg);
760
761 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
762 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
763 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 764
cedc9a47 765 ahci_sg++;
828d09de 766 n_sg++;
1da177e4 767 }
828d09de
JG		 768
769 return n_sg;
1da177e4
LT		 770}
771
772static void ahci_qc_prep(struct ata_queued_cmd *qc)
773{
a0ea7328
JG		 774 struct ata_port *ap = qc->ap;
775 struct ahci_port_priv *pp = ap->private_data;
cc9278ed 776 int is_atapi = is_atapi_taskfile(&qc->tf);
12fad3f9 777 void *cmd_tbl;
1da177e4
LT		 778 u32 opts;
779 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 780 unsigned int n_elem;
1da177e4 781
1da177e4
LT		 782 /*
783 * Fill in command table information. First, the header,
784 * a SATA Register - Host to Device command FIS.
785 */
12fad3f9
TH		 786 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
787
788 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
cc9278ed 789 if (is_atapi) {
12fad3f9
TH		 790 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
791 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 792 }
1da177e4 793
cc9278ed
TH		 794 n_elem = 0;
795 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 796 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 797
cc9278ed
TH		 798 /*
799 * Fill in command slot information.
800 */
801 opts = cmd_fis_len | n_elem << 16;
802 if (qc->tf.flags & ATA_TFLAG_WRITE)
803 opts |= AHCI_CMD_WRITE;
804 if (is_atapi)
4b10e559 805 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 806
12fad3f9 807 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 808}
809
78cd52d0 810static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 811{
78cd52d0
TH		 812 struct ahci_port_priv *pp = ap->private_data;
813 struct ata_eh_info *ehi = &ap->eh_info;
814 unsigned int err_mask = 0, action = 0;
815 struct ata_queued_cmd *qc;
816 u32 serror;
1da177e4 817
78cd52d0 818 ata_ehi_clear_desc(ehi);
1da177e4 819
78cd52d0
TH		 820 /* AHCI needs SError cleared; otherwise, it might lock up */
821 serror = ahci_scr_read(ap, SCR_ERROR);
822 ahci_scr_write(ap, SCR_ERROR, serror);
1da177e4 823
78cd52d0
TH		 824 /* analyze @irq_stat */
825 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
826
827 if (irq_stat & PORT_IRQ_TF_ERR)
828 err_mask |= AC_ERR_DEV;
829
830 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
831 err_mask |= AC_ERR_HOST_BUS;
832 action |= ATA_EH_SOFTRESET;
1da177e4
LT		 833 }
834
78cd52d0
TH		 835 if (irq_stat & PORT_IRQ_IF_ERR) {
836 err_mask |= AC_ERR_ATA_BUS;
837 action |= ATA_EH_SOFTRESET;
838 ata_ehi_push_desc(ehi, ", interface fatal error");
839 }
1da177e4 840
78cd52d0
TH		 841 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
842 err_mask |= AC_ERR_ATA_BUS;
843 action |= ATA_EH_SOFTRESET;
844 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
845 "connection status changed" : "PHY RDY changed");
846 }
847
848 if (irq_stat & PORT_IRQ_UNK_FIS) {
849 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1da177e4 850
78cd52d0
TH		 851 err_mask |= AC_ERR_HSM;
852 action |= ATA_EH_SOFTRESET;
853 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
854 unk[0], unk[1], unk[2], unk[3]);
855 }
1da177e4 856
78cd52d0
TH		 857 /* okay, let's hand over to EH */
858 ehi->serror |= serror;
859 ehi->action |= action;
b8f6153e 860
1da177e4 861 qc = ata_qc_from_tag(ap, ap->active_tag);
78cd52d0
TH		 862 if (qc)
863 qc->err_mask |= err_mask;
864 else
865 ehi->err_mask |= err_mask;
a72ec4ce 866
78cd52d0
TH		 867 if (irq_stat & PORT_IRQ_FREEZE)
868 ata_port_freeze(ap);
869 else
870 ata_port_abort(ap);
1da177e4
LT		 871}
872
78cd52d0 873static void ahci_host_intr(struct ata_port *ap)
1da177e4 874{
ea6ba10b
JG		 875 void __iomem *mmio = ap->host_set->mmio_base;
876 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
12fad3f9
TH		 877 struct ata_eh_info *ehi = &ap->eh_info;
878 u32 status, qc_active;
879 int rc;
1da177e4
LT		 880
881 status = readl(port_mmio + PORT_IRQ_STAT);
882 writel(status, port_mmio + PORT_IRQ_STAT);
883
78cd52d0
TH		 884 if (unlikely(status & PORT_IRQ_ERROR)) {
885 ahci_error_intr(ap, status);
886 return;
1da177e4
LT		 887 }
888
12fad3f9
TH		 889 if (ap->sactive)
890 qc_active = readl(port_mmio + PORT_SCR_ACT);
891 else
892 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
893
894 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
895 if (rc > 0)
896 return;
897 if (rc < 0) {
898 ehi->err_mask |= AC_ERR_HSM;
899 ehi->action |= ATA_EH_SOFTRESET;
900 ata_port_freeze(ap);
901 return;
1da177e4
LT		 902 }
903
2a3917a8
TH		 904 /* hmmm... a spurious interupt */
905
12fad3f9
TH		 906 /* some devices send D2H reg with I bit set during NCQ command phase */
907 if (ap->sactive && status & PORT_IRQ_D2H_REG_FIS)
908 return;
909
2a3917a8
TH		 910 /* ignore interim PIO setup fis interrupts */
911 if (ata_tag_valid(ap->active_tag)) {
912 struct ata_queued_cmd *qc =
913 ata_qc_from_tag(ap, ap->active_tag);
914
915 if (qc && qc->tf.protocol == ATA_PROT_PIO &&
916 (status & PORT_IRQ_PIOS_FIS))
917 return;
918 }
919
78cd52d0
TH		 920 if (ata_ratelimit())
921 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
12fad3f9
TH		 922 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
923 status, ap->active_tag, ap->sactive);
1da177e4
LT		 924}
925
926static void ahci_irq_clear(struct ata_port *ap)
927{
928 /* TODO */
929}
930
12fad3f9 931static irqreturn_t ahci_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1da177e4
LT		 932{
933 struct ata_host_set *host_set = dev_instance;
934 struct ahci_host_priv *hpriv;
935 unsigned int i, handled = 0;
ea6ba10b 936 void __iomem *mmio;
1da177e4
LT		 937 u32 irq_stat, irq_ack = 0;
938
939 VPRINTK("ENTER\n");
940
941 hpriv = host_set->private_data;
942 mmio = host_set->mmio_base;
943
944 /* sigh. 0xffffffff is a valid return from h/w */
945 irq_stat = readl(mmio + HOST_IRQ_STAT);
946 irq_stat &= hpriv->port_map;
947 if (!irq_stat)
948 return IRQ_NONE;
949
950 spin_lock(&host_set->lock);
951
952 for (i = 0; i < host_set->n_ports; i++) {
953 struct ata_port *ap;
1da177e4 954
67846b30
JG		 955 if (!(irq_stat & (1 << i)))
956 continue;
957
1da177e4 958 ap = host_set->ports[i];
67846b30 959 if (ap) {
78cd52d0 960 ahci_host_intr(ap);
67846b30
JG		 961 VPRINTK("port %u\n", i);
962 } else {
963 VPRINTK("port %u (no irq)\n", i);
6971ed1f
TH		 964 if (ata_ratelimit())
965 dev_printk(KERN_WARNING, host_set->dev,
a9524a76 966 "interrupt on disabled port %u\n", i);
1da177e4 967 }
67846b30
JG		 968
969 irq_ack |= (1 << i);
1da177e4
LT		 970 }
971
972 if (irq_ack) {
973 writel(irq_ack, mmio + HOST_IRQ_STAT);
974 handled = 1;
975 }
976
78cd52d0 977 spin_unlock(&host_set->lock);
1da177e4
LT		 978
979 VPRINTK("EXIT\n");
980
981 return IRQ_RETVAL(handled);
982}
983
9a3d9eb0 984static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 985{
986 struct ata_port *ap = qc->ap;
ea6ba10b 987 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4 988
12fad3f9
TH		 989 if (qc->tf.protocol == ATA_PROT_NCQ)
990 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
991 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 992 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
993
994 return 0;
995}
996
78cd52d0
TH		 997static void ahci_freeze(struct ata_port *ap)
998{
999 void __iomem *mmio = ap->host_set->mmio_base;
1000 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1001
1002 /* turn IRQ off */
1003 writel(0, port_mmio + PORT_IRQ_MASK);
1004}
1005
1006static void ahci_thaw(struct ata_port *ap)
1007{
1008 void __iomem *mmio = ap->host_set->mmio_base;
1009 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1010 u32 tmp;
1011
1012 /* clear IRQ */
1013 tmp = readl(port_mmio + PORT_IRQ_STAT);
1014 writel(tmp, port_mmio + PORT_IRQ_STAT);
1015 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
1016
1017 /* turn IRQ back on */
1018 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1019}
1020
1021static void ahci_error_handler(struct ata_port *ap)
1022{
1023 if (!(ap->flags & ATA_FLAG_FROZEN)) {
1024 /* restart engine */
1025 ahci_stop_engine(ap);
1026 ahci_start_engine(ap);
1027 }
1028
1029 /* perform recovery */
f5914a46
TH		 1030 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1031 ahci_postreset);
78cd52d0
TH		 1032}
1033
1034static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1035{
1036 struct ata_port *ap = qc->ap;
1037
1038 if (qc->flags & ATA_QCFLAG_FAILED)
1039 qc->err_mask |= AC_ERR_OTHER;
1040
1041 if (qc->err_mask) {
1042 /* make DMA engine forget about the failed command */
1043 ahci_stop_engine(ap);
1044 ahci_start_engine(ap);
1045 }
1046}
1047
1da177e4
LT		 1048static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1049 unsigned int port_idx)
1050{
1051 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1052 base = ahci_port_base_ul(base, port_idx);
1053 VPRINTK("base now==0x%lx\n", base);
1054
1055 port->cmd_addr = base;
1056 port->scr_addr = base + PORT_SCR;
1057
1058 VPRINTK("EXIT\n");
1059}
1060
1061static int ahci_host_init(struct ata_probe_ent *probe_ent)
1062{
1063 struct ahci_host_priv *hpriv = probe_ent->private_data;
1064 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1065 void __iomem *mmio = probe_ent->mmio_base;
1066 u32 tmp, cap_save;
1da177e4
LT		 1067 unsigned int i, j, using_dac;
1068 int rc;
1069 void __iomem *port_mmio;
1070
1071 cap_save = readl(mmio + HOST_CAP);
1072 cap_save &= ( (1<<28) | (1<<17) );
1073 cap_save |= (1 << 27);
1074
1075 /* global controller reset */
1076 tmp = readl(mmio + HOST_CTL);
1077 if ((tmp & HOST_RESET) == 0) {
1078 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1079 readl(mmio + HOST_CTL); /* flush */
1080 }
1081
1082 /* reset must complete within 1 second, or
1083 * the hardware should be considered fried.
1084 */
1085 ssleep(1);
1086
1087 tmp = readl(mmio + HOST_CTL);
1088 if (tmp & HOST_RESET) {
a9524a76
JG		 1089 dev_printk(KERN_ERR, &pdev->dev,
1090 "controller reset failed (0x%x)\n", tmp);
1da177e4
LT		 1091 return -EIO;
1092 }
1093
1094 writel(HOST_AHCI_EN, mmio + HOST_CTL);
1095 (void) readl(mmio + HOST_CTL); /* flush */
1096 writel(cap_save, mmio + HOST_CAP);
1097 writel(0xf, mmio + HOST_PORTS_IMPL);
1098 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1099
bd12097c
JG		 1100 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1101 u16 tmp16;
1102
1103 pci_read_config_word(pdev, 0x92, &tmp16);
1104 tmp16 |= 0xf;
1105 pci_write_config_word(pdev, 0x92, tmp16);
1106 }
1da177e4
LT		 1107
1108 hpriv->cap = readl(mmio + HOST_CAP);
1109 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1110 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1111
1112 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1113 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1114
1115 using_dac = hpriv->cap & HOST_CAP_64;
1116 if (using_dac &&
1117 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1118 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1119 if (rc) {
1120 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1121 if (rc) {
a9524a76
JG		 1122 dev_printk(KERN_ERR, &pdev->dev,
1123 "64-bit DMA enable failed\n");
1da177e4
LT		 1124 return rc;
1125 }
1126 }
1da177e4
LT		 1127 } else {
1128 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1129 if (rc) {
a9524a76
JG		 1130 dev_printk(KERN_ERR, &pdev->dev,
1131 "32-bit DMA enable failed\n");
1da177e4
LT		 1132 return rc;
1133 }
1134 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1135 if (rc) {
a9524a76
JG		 1136 dev_printk(KERN_ERR, &pdev->dev,
1137 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 1138 return rc;
1139 }
1140 }
1141
1142 for (i = 0; i < probe_ent->n_ports; i++) {
1143#if 0 /* BIOSen initialize this incorrectly */
1144 if (!(hpriv->port_map & (1 << i)))
1145 continue;
1146#endif
1147
1148 port_mmio = ahci_port_base(mmio, i);
1149 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
1150
1151 ahci_setup_port(&probe_ent->port[i],
1152 (unsigned long) mmio, i);
1153
1154 /* make sure port is not active */
1155 tmp = readl(port_mmio + PORT_CMD);
1156 VPRINTK("PORT_CMD 0x%x\n", tmp);
1157 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1158 PORT_CMD_FIS_RX | PORT_CMD_START)) {
1159 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1160 PORT_CMD_FIS_RX | PORT_CMD_START);
1161 writel(tmp, port_mmio + PORT_CMD);
1162 readl(port_mmio + PORT_CMD); /* flush */
1163
1164 /* spec says 500 msecs for each bit, so
1165 * this is slightly incorrect.
1166 */
1167 msleep(500);
1168 }
1169
1170 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
1171
1172 j = 0;
1173 while (j < 100) {
1174 msleep(10);
1175 tmp = readl(port_mmio + PORT_SCR_STAT);
1176 if ((tmp & 0xf) == 0x3)
1177 break;
1178 j++;
1179 }
1180
1181 tmp = readl(port_mmio + PORT_SCR_ERR);
1182 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1183 writel(tmp, port_mmio + PORT_SCR_ERR);
1184
1185 /* ack any pending irq events for this port */
1186 tmp = readl(port_mmio + PORT_IRQ_STAT);
1187 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1188 if (tmp)
1189 writel(tmp, port_mmio + PORT_IRQ_STAT);
1190
1191 writel(1 << i, mmio + HOST_IRQ_STAT);
1da177e4
LT		 1192 }
1193
1194 tmp = readl(mmio + HOST_CTL);
1195 VPRINTK("HOST_CTL 0x%x\n", tmp);
1196 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1197 tmp = readl(mmio + HOST_CTL);
1198 VPRINTK("HOST_CTL 0x%x\n", tmp);
1199
1200 pci_set_master(pdev);
1201
1202 return 0;
1203}
1204
1da177e4
LT		 1205static void ahci_print_info(struct ata_probe_ent *probe_ent)
1206{
1207 struct ahci_host_priv *hpriv = probe_ent->private_data;
1208 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
ea6ba10b 1209 void __iomem *mmio = probe_ent->mmio_base;
1da177e4
LT		 1210 u32 vers, cap, impl, speed;
1211 const char *speed_s;
1212 u16 cc;
1213 const char *scc_s;
1214
1215 vers = readl(mmio + HOST_VERSION);
1216 cap = hpriv->cap;
1217 impl = hpriv->port_map;
1218
1219 speed = (cap >> 20) & 0xf;
1220 if (speed == 1)
1221 speed_s = "1.5";
1222 else if (speed == 2)
1223 speed_s = "3";
1224 else
1225 speed_s = "?";
1226
1227 pci_read_config_word(pdev, 0x0a, &cc);
1228 if (cc == 0x0101)
1229 scc_s = "IDE";
1230 else if (cc == 0x0106)
1231 scc_s = "SATA";
1232 else if (cc == 0x0104)
1233 scc_s = "RAID";
1234 else
1235 scc_s = "unknown";
1236
a9524a76
JG		 1237 dev_printk(KERN_INFO, &pdev->dev,
1238 "AHCI %02x%02x.%02x%02x "
1da177e4
LT		 1239 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1240 ,
1da177e4
LT		 1241
1242 (vers >> 24) & 0xff,
1243 (vers >> 16) & 0xff,
1244 (vers >> 8) & 0xff,
1245 vers & 0xff,
1246
1247 ((cap >> 8) & 0x1f) + 1,
1248 (cap & 0x1f) + 1,
1249 speed_s,
1250 impl,
1251 scc_s);
1252
a9524a76
JG		 1253 dev_printk(KERN_INFO, &pdev->dev,
1254 "flags: "
1da177e4
LT		 1255 "%s%s%s%s%s%s"
1256 "%s%s%s%s%s%s%s\n"
1257 ,
1da177e4
LT		 1258
1259 cap & (1 << 31) ? "64bit " : "",
1260 cap & (1 << 30) ? "ncq " : "",
1261 cap & (1 << 28) ? "ilck " : "",
1262 cap & (1 << 27) ? "stag " : "",
1263 cap & (1 << 26) ? "pm " : "",
1264 cap & (1 << 25) ? "led " : "",
1265
1266 cap & (1 << 24) ? "clo " : "",
1267 cap & (1 << 19) ? "nz " : "",
1268 cap & (1 << 18) ? "only " : "",
1269 cap & (1 << 17) ? "pmp " : "",
1270 cap & (1 << 15) ? "pio " : "",
1271 cap & (1 << 14) ? "slum " : "",
1272 cap & (1 << 13) ? "part " : ""
1273 );
1274}
1275
1276static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1277{
1278 static int printed_version;
1279 struct ata_probe_ent *probe_ent = NULL;
1280 struct ahci_host_priv *hpriv;
1281 unsigned long base;
ea6ba10b 1282 void __iomem *mmio_base;
1da177e4 1283 unsigned int board_idx = (unsigned int) ent->driver_data;
907f4678 1284 int have_msi, pci_dev_busy = 0;
1da177e4
LT		 1285 int rc;
1286
1287 VPRINTK("ENTER\n");
1288
12fad3f9
TH		 1289 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1290
1da177e4 1291 if (!printed_version++)
a9524a76 1292 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4
LT		 1293
1294 rc = pci_enable_device(pdev);
1295 if (rc)
1296 return rc;
1297
1298 rc = pci_request_regions(pdev, DRV_NAME);
1299 if (rc) {
1300 pci_dev_busy = 1;
1301 goto err_out;
1302 }
1303
907f4678
JG		 1304 if (pci_enable_msi(pdev) == 0)
1305 have_msi = 1;
1306 else {
1307 pci_intx(pdev, 1);
1308 have_msi = 0;
1309 }
1da177e4
LT		 1310
1311 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1312 if (probe_ent == NULL) {
1313 rc = -ENOMEM;
907f4678 1314 goto err_out_msi;
1da177e4
LT		 1315 }
1316
1317 memset(probe_ent, 0, sizeof(*probe_ent));
1318 probe_ent->dev = pci_dev_to_dev(pdev);
1319 INIT_LIST_HEAD(&probe_ent->node);
1320
374b1873 1321 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1da177e4
LT		 1322 if (mmio_base == NULL) {
1323 rc = -ENOMEM;
1324 goto err_out_free_ent;
1325 }
1326 base = (unsigned long) mmio_base;
1327
1328 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1329 if (!hpriv) {
1330 rc = -ENOMEM;
1331 goto err_out_iounmap;
1332 }
1333 memset(hpriv, 0, sizeof(*hpriv));
1334
1335 probe_ent->sht = ahci_port_info[board_idx].sht;
1336 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1337 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1338 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1339 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1340
1341 probe_ent->irq = pdev->irq;
1342 probe_ent->irq_flags = SA_SHIRQ;
1343 probe_ent->mmio_base = mmio_base;
1344 probe_ent->private_data = hpriv;
1345
4b0060f4
JG		 1346 if (have_msi)
1347 hpriv->flags |= AHCI_FLAG_MSI;
907f4678 1348
bd12097c
JG		 1349 /* JMicron-specific fixup: make sure we're in AHCI mode */
1350 if (pdev->vendor == 0x197b)
1351 pci_write_config_byte(pdev, 0x41, 0xa1);
1352
1da177e4
LT		 1353 /* initialize adapter */
1354 rc = ahci_host_init(probe_ent);
1355 if (rc)
1356 goto err_out_hpriv;
1357
12fad3f9
TH		 1358 if (hpriv->cap & HOST_CAP_NCQ)
1359 probe_ent->host_flags |= ATA_FLAG_NCQ;
1360
1da177e4
LT		 1361 ahci_print_info(probe_ent);
1362
1363 /* FIXME: check ata_device_add return value */
1364 ata_device_add(probe_ent);
1365 kfree(probe_ent);
1366
1367 return 0;
1368
1369err_out_hpriv:
1370 kfree(hpriv);
1371err_out_iounmap:
374b1873 1372 pci_iounmap(pdev, mmio_base);
1da177e4
LT		 1373err_out_free_ent:
1374 kfree(probe_ent);
907f4678
JG		 1375err_out_msi:
1376 if (have_msi)
1377 pci_disable_msi(pdev);
1378 else
1379 pci_intx(pdev, 0);
1da177e4
LT		 1380 pci_release_regions(pdev);
1381err_out:
1382 if (!pci_dev_busy)
1383 pci_disable_device(pdev);
1384 return rc;
1385}
1386
907f4678
JG		 1387static void ahci_remove_one (struct pci_dev *pdev)
1388{
1389 struct device *dev = pci_dev_to_dev(pdev);
1390 struct ata_host_set *host_set = dev_get_drvdata(dev);
1391 struct ahci_host_priv *hpriv = host_set->private_data;
907f4678
JG		 1392 unsigned int i;
1393 int have_msi;
1394
720ba126
TH		 1395 for (i = 0; i < host_set->n_ports; i++)
1396 ata_port_detach(host_set->ports[i]);
907f4678 1397
4b0060f4 1398 have_msi = hpriv->flags & AHCI_FLAG_MSI;
907f4678 1399 free_irq(host_set->irq, host_set);
907f4678
JG		 1400
1401 for (i = 0; i < host_set->n_ports; i++) {
720ba126 1402 struct ata_port *ap = host_set->ports[i];
907f4678
JG		 1403
1404 ata_scsi_release(ap->host);
1405 scsi_host_put(ap->host);
1406 }
1407
e005f01d 1408 kfree(hpriv);
374b1873 1409 pci_iounmap(pdev, host_set->mmio_base);
ead5de99
JG		 1410 kfree(host_set);
1411
907f4678
JG		 1412 if (have_msi)
1413 pci_disable_msi(pdev);
1414 else
1415 pci_intx(pdev, 0);
1416 pci_release_regions(pdev);
907f4678
JG		 1417 pci_disable_device(pdev);
1418 dev_set_drvdata(dev, NULL);
1419}
1da177e4
LT		 1420
1421static int __init ahci_init(void)
1422{
1423 return pci_module_init(&ahci_pci_driver);
1424}
1425
1da177e4
LT		 1426static void __exit ahci_exit(void)
1427{
1428 pci_unregister_driver(&ahci_pci_driver);
1429}
1430
1431
1432MODULE_AUTHOR("Jeff Garzik");
1433MODULE_DESCRIPTION("AHCI SATA low-level driver");
1434MODULE_LICENSE("GPL");
1435MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1436MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1437
1438module_init(ahci_init);
1439module_exit(ahci_exit);
Linux kernel - Deliverables
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