Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * DO NOT EDIT - This file is automatically generated | |
3 | * from the following source files: | |
4 | * | |
53467e63 HR |
5 | * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#120 $ |
6 | * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $ | |
1da177e4 LT |
7 | */ |
8 | typedef int (ahd_reg_print_t)(u_int, u_int *, u_int); | |
9 | typedef struct ahd_reg_parse_entry { | |
10 | char *name; | |
11 | uint8_t value; | |
12 | uint8_t mask; | |
13 | } ahd_reg_parse_entry_t; | |
14 | ||
15 | #if AIC_DEBUG_REGISTERS | |
16 | ahd_reg_print_t ahd_mode_ptr_print; | |
17 | #else | |
18 | #define ahd_mode_ptr_print(regvalue, cur_col, wrap) \ | |
19 | ahd_print_register(NULL, 0, "MODE_PTR", 0x00, regvalue, cur_col, wrap) | |
20 | #endif | |
21 | ||
22 | #if AIC_DEBUG_REGISTERS | |
23 | ahd_reg_print_t ahd_intstat_print; | |
24 | #else | |
25 | #define ahd_intstat_print(regvalue, cur_col, wrap) \ | |
26 | ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap) | |
27 | #endif | |
28 | ||
29 | #if AIC_DEBUG_REGISTERS | |
30 | ahd_reg_print_t ahd_seqintcode_print; | |
31 | #else | |
32 | #define ahd_seqintcode_print(regvalue, cur_col, wrap) \ | |
33 | ahd_print_register(NULL, 0, "SEQINTCODE", 0x02, regvalue, cur_col, wrap) | |
34 | #endif | |
35 | ||
1da177e4 LT |
36 | #if AIC_DEBUG_REGISTERS |
37 | ahd_reg_print_t ahd_error_print; | |
38 | #else | |
39 | #define ahd_error_print(regvalue, cur_col, wrap) \ | |
40 | ahd_print_register(NULL, 0, "ERROR", 0x04, regvalue, cur_col, wrap) | |
41 | #endif | |
42 | ||
1da177e4 LT |
43 | #if AIC_DEBUG_REGISTERS |
44 | ahd_reg_print_t ahd_hescb_qoff_print; | |
45 | #else | |
46 | #define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \ | |
47 | ahd_print_register(NULL, 0, "HESCB_QOFF", 0x08, regvalue, cur_col, wrap) | |
48 | #endif | |
49 | ||
50 | #if AIC_DEBUG_REGISTERS | |
51 | ahd_reg_print_t ahd_hs_mailbox_print; | |
52 | #else | |
53 | #define ahd_hs_mailbox_print(regvalue, cur_col, wrap) \ | |
54 | ahd_print_register(NULL, 0, "HS_MAILBOX", 0x0b, regvalue, cur_col, wrap) | |
55 | #endif | |
56 | ||
57 | #if AIC_DEBUG_REGISTERS | |
11668bb6 | 58 | ahd_reg_print_t ahd_seqintstat_print; |
1da177e4 | 59 | #else |
11668bb6 HR |
60 | #define ahd_seqintstat_print(regvalue, cur_col, wrap) \ |
61 | ahd_print_register(NULL, 0, "SEQINTSTAT", 0x0c, regvalue, cur_col, wrap) | |
1da177e4 LT |
62 | #endif |
63 | ||
64 | #if AIC_DEBUG_REGISTERS | |
11668bb6 | 65 | ahd_reg_print_t ahd_clrseqintstat_print; |
1da177e4 | 66 | #else |
11668bb6 HR |
67 | #define ahd_clrseqintstat_print(regvalue, cur_col, wrap) \ |
68 | ahd_print_register(NULL, 0, "CLRSEQINTSTAT", 0x0c, regvalue, cur_col, wrap) | |
1da177e4 LT |
69 | #endif |
70 | ||
71 | #if AIC_DEBUG_REGISTERS | |
72 | ahd_reg_print_t ahd_swtimer_print; | |
73 | #else | |
74 | #define ahd_swtimer_print(regvalue, cur_col, wrap) \ | |
75 | ahd_print_register(NULL, 0, "SWTIMER", 0x0e, regvalue, cur_col, wrap) | |
76 | #endif | |
77 | ||
1da177e4 LT |
78 | #if AIC_DEBUG_REGISTERS |
79 | ahd_reg_print_t ahd_sescb_qoff_print; | |
80 | #else | |
81 | #define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \ | |
82 | ahd_print_register(NULL, 0, "SESCB_QOFF", 0x12, regvalue, cur_col, wrap) | |
83 | #endif | |
84 | ||
1da177e4 LT |
85 | #if AIC_DEBUG_REGISTERS |
86 | ahd_reg_print_t ahd_intctl_print; | |
87 | #else | |
88 | #define ahd_intctl_print(regvalue, cur_col, wrap) \ | |
89 | ahd_print_register(NULL, 0, "INTCTL", 0x18, regvalue, cur_col, wrap) | |
90 | #endif | |
91 | ||
92 | #if AIC_DEBUG_REGISTERS | |
93 | ahd_reg_print_t ahd_dfcntrl_print; | |
94 | #else | |
95 | #define ahd_dfcntrl_print(regvalue, cur_col, wrap) \ | |
96 | ahd_print_register(NULL, 0, "DFCNTRL", 0x19, regvalue, cur_col, wrap) | |
97 | #endif | |
98 | ||
1da177e4 LT |
99 | #if AIC_DEBUG_REGISTERS |
100 | ahd_reg_print_t ahd_dfstatus_print; | |
101 | #else | |
102 | #define ahd_dfstatus_print(regvalue, cur_col, wrap) \ | |
103 | ahd_print_register(NULL, 0, "DFSTATUS", 0x1a, regvalue, cur_col, wrap) | |
104 | #endif | |
105 | ||
106 | #if AIC_DEBUG_REGISTERS | |
107 | ahd_reg_print_t ahd_sg_cache_shadow_print; | |
108 | #else | |
109 | #define ahd_sg_cache_shadow_print(regvalue, cur_col, wrap) \ | |
110 | ahd_print_register(NULL, 0, "SG_CACHE_SHADOW", 0x1b, regvalue, cur_col, wrap) | |
111 | #endif | |
112 | ||
1da177e4 LT |
113 | #if AIC_DEBUG_REGISTERS |
114 | ahd_reg_print_t ahd_lqin_print; | |
115 | #else | |
116 | #define ahd_lqin_print(regvalue, cur_col, wrap) \ | |
117 | ahd_print_register(NULL, 0, "LQIN", 0x20, regvalue, cur_col, wrap) | |
118 | #endif | |
119 | ||
1da177e4 LT |
120 | #if AIC_DEBUG_REGISTERS |
121 | ahd_reg_print_t ahd_lunptr_print; | |
122 | #else | |
123 | #define ahd_lunptr_print(regvalue, cur_col, wrap) \ | |
124 | ahd_print_register(NULL, 0, "LUNPTR", 0x22, regvalue, cur_col, wrap) | |
125 | #endif | |
126 | ||
1da177e4 LT |
127 | #if AIC_DEBUG_REGISTERS |
128 | ahd_reg_print_t ahd_cmdlenptr_print; | |
129 | #else | |
130 | #define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \ | |
131 | ahd_print_register(NULL, 0, "CMDLENPTR", 0x25, regvalue, cur_col, wrap) | |
132 | #endif | |
133 | ||
134 | #if AIC_DEBUG_REGISTERS | |
135 | ahd_reg_print_t ahd_attrptr_print; | |
136 | #else | |
137 | #define ahd_attrptr_print(regvalue, cur_col, wrap) \ | |
138 | ahd_print_register(NULL, 0, "ATTRPTR", 0x26, regvalue, cur_col, wrap) | |
139 | #endif | |
140 | ||
141 | #if AIC_DEBUG_REGISTERS | |
142 | ahd_reg_print_t ahd_flagptr_print; | |
143 | #else | |
144 | #define ahd_flagptr_print(regvalue, cur_col, wrap) \ | |
145 | ahd_print_register(NULL, 0, "FLAGPTR", 0x27, regvalue, cur_col, wrap) | |
146 | #endif | |
147 | ||
148 | #if AIC_DEBUG_REGISTERS | |
149 | ahd_reg_print_t ahd_cmdptr_print; | |
150 | #else | |
151 | #define ahd_cmdptr_print(regvalue, cur_col, wrap) \ | |
152 | ahd_print_register(NULL, 0, "CMDPTR", 0x28, regvalue, cur_col, wrap) | |
153 | #endif | |
154 | ||
155 | #if AIC_DEBUG_REGISTERS | |
156 | ahd_reg_print_t ahd_qnextptr_print; | |
157 | #else | |
158 | #define ahd_qnextptr_print(regvalue, cur_col, wrap) \ | |
159 | ahd_print_register(NULL, 0, "QNEXTPTR", 0x29, regvalue, cur_col, wrap) | |
160 | #endif | |
161 | ||
1da177e4 LT |
162 | #if AIC_DEBUG_REGISTERS |
163 | ahd_reg_print_t ahd_abrtbyteptr_print; | |
164 | #else | |
165 | #define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \ | |
166 | ahd_print_register(NULL, 0, "ABRTBYTEPTR", 0x2b, regvalue, cur_col, wrap) | |
167 | #endif | |
168 | ||
169 | #if AIC_DEBUG_REGISTERS | |
170 | ahd_reg_print_t ahd_abrtbitptr_print; | |
171 | #else | |
172 | #define ahd_abrtbitptr_print(regvalue, cur_col, wrap) \ | |
173 | ahd_print_register(NULL, 0, "ABRTBITPTR", 0x2c, regvalue, cur_col, wrap) | |
174 | #endif | |
175 | ||
1da177e4 LT |
176 | #if AIC_DEBUG_REGISTERS |
177 | ahd_reg_print_t ahd_lunlen_print; | |
178 | #else | |
179 | #define ahd_lunlen_print(regvalue, cur_col, wrap) \ | |
180 | ahd_print_register(NULL, 0, "LUNLEN", 0x30, regvalue, cur_col, wrap) | |
181 | #endif | |
182 | ||
183 | #if AIC_DEBUG_REGISTERS | |
184 | ahd_reg_print_t ahd_cdblimit_print; | |
185 | #else | |
186 | #define ahd_cdblimit_print(regvalue, cur_col, wrap) \ | |
187 | ahd_print_register(NULL, 0, "CDBLIMIT", 0x31, regvalue, cur_col, wrap) | |
188 | #endif | |
189 | ||
190 | #if AIC_DEBUG_REGISTERS | |
191 | ahd_reg_print_t ahd_maxcmd_print; | |
192 | #else | |
193 | #define ahd_maxcmd_print(regvalue, cur_col, wrap) \ | |
194 | ahd_print_register(NULL, 0, "MAXCMD", 0x32, regvalue, cur_col, wrap) | |
195 | #endif | |
196 | ||
197 | #if AIC_DEBUG_REGISTERS | |
198 | ahd_reg_print_t ahd_maxcmdcnt_print; | |
199 | #else | |
200 | #define ahd_maxcmdcnt_print(regvalue, cur_col, wrap) \ | |
201 | ahd_print_register(NULL, 0, "MAXCMDCNT", 0x33, regvalue, cur_col, wrap) | |
202 | #endif | |
203 | ||
1da177e4 LT |
204 | #if AIC_DEBUG_REGISTERS |
205 | ahd_reg_print_t ahd_lqctl1_print; | |
206 | #else | |
207 | #define ahd_lqctl1_print(regvalue, cur_col, wrap) \ | |
208 | ahd_print_register(NULL, 0, "LQCTL1", 0x38, regvalue, cur_col, wrap) | |
209 | #endif | |
210 | ||
1da177e4 LT |
211 | #if AIC_DEBUG_REGISTERS |
212 | ahd_reg_print_t ahd_lqctl2_print; | |
213 | #else | |
214 | #define ahd_lqctl2_print(regvalue, cur_col, wrap) \ | |
215 | ahd_print_register(NULL, 0, "LQCTL2", 0x39, regvalue, cur_col, wrap) | |
216 | #endif | |
217 | ||
1da177e4 LT |
218 | #if AIC_DEBUG_REGISTERS |
219 | ahd_reg_print_t ahd_scsiseq0_print; | |
220 | #else | |
221 | #define ahd_scsiseq0_print(regvalue, cur_col, wrap) \ | |
222 | ahd_print_register(NULL, 0, "SCSISEQ0", 0x3a, regvalue, cur_col, wrap) | |
223 | #endif | |
224 | ||
225 | #if AIC_DEBUG_REGISTERS | |
226 | ahd_reg_print_t ahd_scsiseq1_print; | |
227 | #else | |
228 | #define ahd_scsiseq1_print(regvalue, cur_col, wrap) \ | |
229 | ahd_print_register(NULL, 0, "SCSISEQ1", 0x3b, regvalue, cur_col, wrap) | |
230 | #endif | |
231 | ||
232 | #if AIC_DEBUG_REGISTERS | |
233 | ahd_reg_print_t ahd_sxfrctl0_print; | |
234 | #else | |
235 | #define ahd_sxfrctl0_print(regvalue, cur_col, wrap) \ | |
236 | ahd_print_register(NULL, 0, "SXFRCTL0", 0x3c, regvalue, cur_col, wrap) | |
237 | #endif | |
238 | ||
1da177e4 LT |
239 | #if AIC_DEBUG_REGISTERS |
240 | ahd_reg_print_t ahd_dffstat_print; | |
241 | #else | |
242 | #define ahd_dffstat_print(regvalue, cur_col, wrap) \ | |
243 | ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap) | |
244 | #endif | |
245 | ||
246 | #if AIC_DEBUG_REGISTERS | |
d10c2e46 | 247 | ahd_reg_print_t ahd_multargid_print; |
1da177e4 | 248 | #else |
d10c2e46 HR |
249 | #define ahd_multargid_print(regvalue, cur_col, wrap) \ |
250 | ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap) | |
1da177e4 LT |
251 | #endif |
252 | ||
1da177e4 LT |
253 | #if AIC_DEBUG_REGISTERS |
254 | ahd_reg_print_t ahd_scsisigi_print; | |
255 | #else | |
256 | #define ahd_scsisigi_print(regvalue, cur_col, wrap) \ | |
257 | ahd_print_register(NULL, 0, "SCSISIGI", 0x41, regvalue, cur_col, wrap) | |
258 | #endif | |
259 | ||
260 | #if AIC_DEBUG_REGISTERS | |
261 | ahd_reg_print_t ahd_scsiphase_print; | |
262 | #else | |
263 | #define ahd_scsiphase_print(regvalue, cur_col, wrap) \ | |
264 | ahd_print_register(NULL, 0, "SCSIPHASE", 0x42, regvalue, cur_col, wrap) | |
265 | #endif | |
266 | ||
1da177e4 LT |
267 | #if AIC_DEBUG_REGISTERS |
268 | ahd_reg_print_t ahd_scsidat_print; | |
269 | #else | |
270 | #define ahd_scsidat_print(regvalue, cur_col, wrap) \ | |
271 | ahd_print_register(NULL, 0, "SCSIDAT", 0x44, regvalue, cur_col, wrap) | |
272 | #endif | |
273 | ||
274 | #if AIC_DEBUG_REGISTERS | |
275 | ahd_reg_print_t ahd_scsibus_print; | |
276 | #else | |
277 | #define ahd_scsibus_print(regvalue, cur_col, wrap) \ | |
278 | ahd_print_register(NULL, 0, "SCSIBUS", 0x46, regvalue, cur_col, wrap) | |
279 | #endif | |
280 | ||
281 | #if AIC_DEBUG_REGISTERS | |
282 | ahd_reg_print_t ahd_targidin_print; | |
283 | #else | |
284 | #define ahd_targidin_print(regvalue, cur_col, wrap) \ | |
285 | ahd_print_register(NULL, 0, "TARGIDIN", 0x48, regvalue, cur_col, wrap) | |
286 | #endif | |
287 | ||
288 | #if AIC_DEBUG_REGISTERS | |
289 | ahd_reg_print_t ahd_selid_print; | |
290 | #else | |
291 | #define ahd_selid_print(regvalue, cur_col, wrap) \ | |
292 | ahd_print_register(NULL, 0, "SELID", 0x49, regvalue, cur_col, wrap) | |
293 | #endif | |
294 | ||
1da177e4 | 295 | #if AIC_DEBUG_REGISTERS |
11668bb6 | 296 | ahd_reg_print_t ahd_sblkctl_print; |
1da177e4 | 297 | #else |
11668bb6 HR |
298 | #define ahd_sblkctl_print(regvalue, cur_col, wrap) \ |
299 | ahd_print_register(NULL, 0, "SBLKCTL", 0x4a, regvalue, cur_col, wrap) | |
1da177e4 LT |
300 | #endif |
301 | ||
11668bb6 HR |
302 | #if AIC_DEBUG_REGISTERS |
303 | ahd_reg_print_t ahd_sstat0_print; | |
304 | #else | |
305 | #define ahd_sstat0_print(regvalue, cur_col, wrap) \ | |
306 | ahd_print_register(NULL, 0, "SSTAT0", 0x4b, regvalue, cur_col, wrap) | |
307 | #endif | |
308 | ||
1da177e4 LT |
309 | #if AIC_DEBUG_REGISTERS |
310 | ahd_reg_print_t ahd_simode0_print; | |
311 | #else | |
312 | #define ahd_simode0_print(regvalue, cur_col, wrap) \ | |
313 | ahd_print_register(NULL, 0, "SIMODE0", 0x4b, regvalue, cur_col, wrap) | |
314 | #endif | |
315 | ||
1da177e4 LT |
316 | #if AIC_DEBUG_REGISTERS |
317 | ahd_reg_print_t ahd_sstat1_print; | |
318 | #else | |
319 | #define ahd_sstat1_print(regvalue, cur_col, wrap) \ | |
320 | ahd_print_register(NULL, 0, "SSTAT1", 0x4c, regvalue, cur_col, wrap) | |
321 | #endif | |
322 | ||
1da177e4 | 323 | #if AIC_DEBUG_REGISTERS |
d10c2e46 | 324 | ahd_reg_print_t ahd_sstat2_print; |
1da177e4 | 325 | #else |
d10c2e46 HR |
326 | #define ahd_sstat2_print(regvalue, cur_col, wrap) \ |
327 | ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap) | |
1da177e4 LT |
328 | #endif |
329 | ||
330 | #if AIC_DEBUG_REGISTERS | |
11668bb6 | 331 | ahd_reg_print_t ahd_clrsint2_print; |
1da177e4 | 332 | #else |
11668bb6 HR |
333 | #define ahd_clrsint2_print(regvalue, cur_col, wrap) \ |
334 | ahd_print_register(NULL, 0, "CLRSINT2", 0x4d, regvalue, cur_col, wrap) | |
1da177e4 LT |
335 | #endif |
336 | ||
337 | #if AIC_DEBUG_REGISTERS | |
338 | ahd_reg_print_t ahd_perrdiag_print; | |
339 | #else | |
340 | #define ahd_perrdiag_print(regvalue, cur_col, wrap) \ | |
341 | ahd_print_register(NULL, 0, "PERRDIAG", 0x4e, regvalue, cur_col, wrap) | |
342 | #endif | |
343 | ||
344 | #if AIC_DEBUG_REGISTERS | |
345 | ahd_reg_print_t ahd_lqistate_print; | |
346 | #else | |
347 | #define ahd_lqistate_print(regvalue, cur_col, wrap) \ | |
348 | ahd_print_register(NULL, 0, "LQISTATE", 0x4e, regvalue, cur_col, wrap) | |
349 | #endif | |
350 | ||
351 | #if AIC_DEBUG_REGISTERS | |
352 | ahd_reg_print_t ahd_soffcnt_print; | |
353 | #else | |
354 | #define ahd_soffcnt_print(regvalue, cur_col, wrap) \ | |
355 | ahd_print_register(NULL, 0, "SOFFCNT", 0x4f, regvalue, cur_col, wrap) | |
356 | #endif | |
357 | ||
358 | #if AIC_DEBUG_REGISTERS | |
359 | ahd_reg_print_t ahd_lqostate_print; | |
360 | #else | |
361 | #define ahd_lqostate_print(regvalue, cur_col, wrap) \ | |
362 | ahd_print_register(NULL, 0, "LQOSTATE", 0x4f, regvalue, cur_col, wrap) | |
363 | #endif | |
364 | ||
365 | #if AIC_DEBUG_REGISTERS | |
366 | ahd_reg_print_t ahd_lqistat0_print; | |
367 | #else | |
368 | #define ahd_lqistat0_print(regvalue, cur_col, wrap) \ | |
369 | ahd_print_register(NULL, 0, "LQISTAT0", 0x50, regvalue, cur_col, wrap) | |
370 | #endif | |
371 | ||
372 | #if AIC_DEBUG_REGISTERS | |
060ae855 | 373 | ahd_reg_print_t ahd_clrlqiint0_print; |
1da177e4 | 374 | #else |
060ae855 DV |
375 | #define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \ |
376 | ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap) | |
1da177e4 LT |
377 | #endif |
378 | ||
379 | #if AIC_DEBUG_REGISTERS | |
060ae855 | 380 | ahd_reg_print_t ahd_lqimode0_print; |
1da177e4 | 381 | #else |
060ae855 DV |
382 | #define ahd_lqimode0_print(regvalue, cur_col, wrap) \ |
383 | ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap) | |
1da177e4 LT |
384 | #endif |
385 | ||
386 | #if AIC_DEBUG_REGISTERS | |
387 | ahd_reg_print_t ahd_lqimode1_print; | |
388 | #else | |
389 | #define ahd_lqimode1_print(regvalue, cur_col, wrap) \ | |
390 | ahd_print_register(NULL, 0, "LQIMODE1", 0x51, regvalue, cur_col, wrap) | |
391 | #endif | |
392 | ||
393 | #if AIC_DEBUG_REGISTERS | |
394 | ahd_reg_print_t ahd_lqistat1_print; | |
395 | #else | |
396 | #define ahd_lqistat1_print(regvalue, cur_col, wrap) \ | |
397 | ahd_print_register(NULL, 0, "LQISTAT1", 0x51, regvalue, cur_col, wrap) | |
398 | #endif | |
399 | ||
400 | #if AIC_DEBUG_REGISTERS | |
401 | ahd_reg_print_t ahd_clrlqiint1_print; | |
402 | #else | |
403 | #define ahd_clrlqiint1_print(regvalue, cur_col, wrap) \ | |
404 | ahd_print_register(NULL, 0, "CLRLQIINT1", 0x51, regvalue, cur_col, wrap) | |
405 | #endif | |
406 | ||
407 | #if AIC_DEBUG_REGISTERS | |
408 | ahd_reg_print_t ahd_lqistat2_print; | |
409 | #else | |
410 | #define ahd_lqistat2_print(regvalue, cur_col, wrap) \ | |
411 | ahd_print_register(NULL, 0, "LQISTAT2", 0x52, regvalue, cur_col, wrap) | |
412 | #endif | |
413 | ||
414 | #if AIC_DEBUG_REGISTERS | |
415 | ahd_reg_print_t ahd_sstat3_print; | |
416 | #else | |
417 | #define ahd_sstat3_print(regvalue, cur_col, wrap) \ | |
418 | ahd_print_register(NULL, 0, "SSTAT3", 0x53, regvalue, cur_col, wrap) | |
419 | #endif | |
420 | ||
421 | #if AIC_DEBUG_REGISTERS | |
422 | ahd_reg_print_t ahd_simode3_print; | |
423 | #else | |
424 | #define ahd_simode3_print(regvalue, cur_col, wrap) \ | |
425 | ahd_print_register(NULL, 0, "SIMODE3", 0x53, regvalue, cur_col, wrap) | |
426 | #endif | |
427 | ||
428 | #if AIC_DEBUG_REGISTERS | |
429 | ahd_reg_print_t ahd_clrsint3_print; | |
430 | #else | |
431 | #define ahd_clrsint3_print(regvalue, cur_col, wrap) \ | |
432 | ahd_print_register(NULL, 0, "CLRSINT3", 0x53, regvalue, cur_col, wrap) | |
433 | #endif | |
434 | ||
1da177e4 LT |
435 | #if AIC_DEBUG_REGISTERS |
436 | ahd_reg_print_t ahd_lqostat0_print; | |
437 | #else | |
438 | #define ahd_lqostat0_print(regvalue, cur_col, wrap) \ | |
439 | ahd_print_register(NULL, 0, "LQOSTAT0", 0x54, regvalue, cur_col, wrap) | |
440 | #endif | |
441 | ||
442 | #if AIC_DEBUG_REGISTERS | |
443 | ahd_reg_print_t ahd_clrlqoint0_print; | |
444 | #else | |
445 | #define ahd_clrlqoint0_print(regvalue, cur_col, wrap) \ | |
446 | ahd_print_register(NULL, 0, "CLRLQOINT0", 0x54, regvalue, cur_col, wrap) | |
447 | #endif | |
448 | ||
11668bb6 HR |
449 | #if AIC_DEBUG_REGISTERS |
450 | ahd_reg_print_t ahd_lqomode0_print; | |
451 | #else | |
452 | #define ahd_lqomode0_print(regvalue, cur_col, wrap) \ | |
453 | ahd_print_register(NULL, 0, "LQOMODE0", 0x54, regvalue, cur_col, wrap) | |
454 | #endif | |
455 | ||
456 | #if AIC_DEBUG_REGISTERS | |
457 | ahd_reg_print_t ahd_lqomode1_print; | |
458 | #else | |
459 | #define ahd_lqomode1_print(regvalue, cur_col, wrap) \ | |
460 | ahd_print_register(NULL, 0, "LQOMODE1", 0x55, regvalue, cur_col, wrap) | |
461 | #endif | |
462 | ||
1da177e4 LT |
463 | #if AIC_DEBUG_REGISTERS |
464 | ahd_reg_print_t ahd_lqostat1_print; | |
465 | #else | |
466 | #define ahd_lqostat1_print(regvalue, cur_col, wrap) \ | |
467 | ahd_print_register(NULL, 0, "LQOSTAT1", 0x55, regvalue, cur_col, wrap) | |
468 | #endif | |
469 | ||
470 | #if AIC_DEBUG_REGISTERS | |
471 | ahd_reg_print_t ahd_clrlqoint1_print; | |
472 | #else | |
473 | #define ahd_clrlqoint1_print(regvalue, cur_col, wrap) \ | |
474 | ahd_print_register(NULL, 0, "CLRLQOINT1", 0x55, regvalue, cur_col, wrap) | |
475 | #endif | |
476 | ||
1da177e4 LT |
477 | #if AIC_DEBUG_REGISTERS |
478 | ahd_reg_print_t ahd_lqostat2_print; | |
479 | #else | |
480 | #define ahd_lqostat2_print(regvalue, cur_col, wrap) \ | |
481 | ahd_print_register(NULL, 0, "LQOSTAT2", 0x56, regvalue, cur_col, wrap) | |
482 | #endif | |
483 | ||
484 | #if AIC_DEBUG_REGISTERS | |
485 | ahd_reg_print_t ahd_os_space_cnt_print; | |
486 | #else | |
487 | #define ahd_os_space_cnt_print(regvalue, cur_col, wrap) \ | |
488 | ahd_print_register(NULL, 0, "OS_SPACE_CNT", 0x56, regvalue, cur_col, wrap) | |
489 | #endif | |
490 | ||
491 | #if AIC_DEBUG_REGISTERS | |
492 | ahd_reg_print_t ahd_simode1_print; | |
493 | #else | |
494 | #define ahd_simode1_print(regvalue, cur_col, wrap) \ | |
495 | ahd_print_register(NULL, 0, "SIMODE1", 0x57, regvalue, cur_col, wrap) | |
496 | #endif | |
497 | ||
498 | #if AIC_DEBUG_REGISTERS | |
499 | ahd_reg_print_t ahd_gsfifo_print; | |
500 | #else | |
501 | #define ahd_gsfifo_print(regvalue, cur_col, wrap) \ | |
502 | ahd_print_register(NULL, 0, "GSFIFO", 0x58, regvalue, cur_col, wrap) | |
503 | #endif | |
504 | ||
505 | #if AIC_DEBUG_REGISTERS | |
506 | ahd_reg_print_t ahd_dffsxfrctl_print; | |
507 | #else | |
508 | #define ahd_dffsxfrctl_print(regvalue, cur_col, wrap) \ | |
509 | ahd_print_register(NULL, 0, "DFFSXFRCTL", 0x5a, regvalue, cur_col, wrap) | |
510 | #endif | |
511 | ||
512 | #if AIC_DEBUG_REGISTERS | |
513 | ahd_reg_print_t ahd_lqoscsctl_print; | |
514 | #else | |
515 | #define ahd_lqoscsctl_print(regvalue, cur_col, wrap) \ | |
516 | ahd_print_register(NULL, 0, "LQOSCSCTL", 0x5a, regvalue, cur_col, wrap) | |
517 | #endif | |
518 | ||
519 | #if AIC_DEBUG_REGISTERS | |
520 | ahd_reg_print_t ahd_nextscb_print; | |
521 | #else | |
522 | #define ahd_nextscb_print(regvalue, cur_col, wrap) \ | |
523 | ahd_print_register(NULL, 0, "NEXTSCB", 0x5a, regvalue, cur_col, wrap) | |
524 | #endif | |
525 | ||
526 | #if AIC_DEBUG_REGISTERS | |
527 | ahd_reg_print_t ahd_clrseqintsrc_print; | |
528 | #else | |
529 | #define ahd_clrseqintsrc_print(regvalue, cur_col, wrap) \ | |
530 | ahd_print_register(NULL, 0, "CLRSEQINTSRC", 0x5b, regvalue, cur_col, wrap) | |
531 | #endif | |
532 | ||
533 | #if AIC_DEBUG_REGISTERS | |
534 | ahd_reg_print_t ahd_seqintsrc_print; | |
535 | #else | |
536 | #define ahd_seqintsrc_print(regvalue, cur_col, wrap) \ | |
537 | ahd_print_register(NULL, 0, "SEQINTSRC", 0x5b, regvalue, cur_col, wrap) | |
538 | #endif | |
539 | ||
1da177e4 | 540 | #if AIC_DEBUG_REGISTERS |
060ae855 | 541 | ahd_reg_print_t ahd_currscb_print; |
1da177e4 | 542 | #else |
060ae855 DV |
543 | #define ahd_currscb_print(regvalue, cur_col, wrap) \ |
544 | ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap) | |
1da177e4 LT |
545 | #endif |
546 | ||
547 | #if AIC_DEBUG_REGISTERS | |
060ae855 | 548 | ahd_reg_print_t ahd_seqimode_print; |
1da177e4 | 549 | #else |
060ae855 DV |
550 | #define ahd_seqimode_print(regvalue, cur_col, wrap) \ |
551 | ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap) | |
1da177e4 LT |
552 | #endif |
553 | ||
554 | #if AIC_DEBUG_REGISTERS | |
d10c2e46 | 555 | ahd_reg_print_t ahd_mdffstat_print; |
1da177e4 | 556 | #else |
d10c2e46 HR |
557 | #define ahd_mdffstat_print(regvalue, cur_col, wrap) \ |
558 | ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap) | |
1da177e4 LT |
559 | #endif |
560 | ||
561 | #if AIC_DEBUG_REGISTERS | |
562 | ahd_reg_print_t ahd_lastscb_print; | |
563 | #else | |
564 | #define ahd_lastscb_print(regvalue, cur_col, wrap) \ | |
565 | ahd_print_register(NULL, 0, "LASTSCB", 0x5e, regvalue, cur_col, wrap) | |
566 | #endif | |
567 | ||
1da177e4 LT |
568 | #if AIC_DEBUG_REGISTERS |
569 | ahd_reg_print_t ahd_negoaddr_print; | |
570 | #else | |
571 | #define ahd_negoaddr_print(regvalue, cur_col, wrap) \ | |
572 | ahd_print_register(NULL, 0, "NEGOADDR", 0x60, regvalue, cur_col, wrap) | |
573 | #endif | |
574 | ||
1da177e4 LT |
575 | #if AIC_DEBUG_REGISTERS |
576 | ahd_reg_print_t ahd_negperiod_print; | |
577 | #else | |
578 | #define ahd_negperiod_print(regvalue, cur_col, wrap) \ | |
579 | ahd_print_register(NULL, 0, "NEGPERIOD", 0x61, regvalue, cur_col, wrap) | |
580 | #endif | |
581 | ||
1da177e4 LT |
582 | #if AIC_DEBUG_REGISTERS |
583 | ahd_reg_print_t ahd_negoffset_print; | |
584 | #else | |
585 | #define ahd_negoffset_print(regvalue, cur_col, wrap) \ | |
586 | ahd_print_register(NULL, 0, "NEGOFFSET", 0x62, regvalue, cur_col, wrap) | |
587 | #endif | |
588 | ||
589 | #if AIC_DEBUG_REGISTERS | |
590 | ahd_reg_print_t ahd_negppropts_print; | |
591 | #else | |
592 | #define ahd_negppropts_print(regvalue, cur_col, wrap) \ | |
593 | ahd_print_register(NULL, 0, "NEGPPROPTS", 0x63, regvalue, cur_col, wrap) | |
594 | #endif | |
595 | ||
596 | #if AIC_DEBUG_REGISTERS | |
597 | ahd_reg_print_t ahd_negconopts_print; | |
598 | #else | |
599 | #define ahd_negconopts_print(regvalue, cur_col, wrap) \ | |
600 | ahd_print_register(NULL, 0, "NEGCONOPTS", 0x64, regvalue, cur_col, wrap) | |
601 | #endif | |
602 | ||
603 | #if AIC_DEBUG_REGISTERS | |
604 | ahd_reg_print_t ahd_annexcol_print; | |
605 | #else | |
606 | #define ahd_annexcol_print(regvalue, cur_col, wrap) \ | |
607 | ahd_print_register(NULL, 0, "ANNEXCOL", 0x65, regvalue, cur_col, wrap) | |
608 | #endif | |
609 | ||
610 | #if AIC_DEBUG_REGISTERS | |
11668bb6 | 611 | ahd_reg_print_t ahd_annexdat_print; |
1da177e4 | 612 | #else |
11668bb6 HR |
613 | #define ahd_annexdat_print(regvalue, cur_col, wrap) \ |
614 | ahd_print_register(NULL, 0, "ANNEXDAT", 0x66, regvalue, cur_col, wrap) | |
1da177e4 LT |
615 | #endif |
616 | ||
617 | #if AIC_DEBUG_REGISTERS | |
11668bb6 | 618 | ahd_reg_print_t ahd_scschkn_print; |
1da177e4 | 619 | #else |
11668bb6 HR |
620 | #define ahd_scschkn_print(regvalue, cur_col, wrap) \ |
621 | ahd_print_register(NULL, 0, "SCSCHKN", 0x66, regvalue, cur_col, wrap) | |
1da177e4 LT |
622 | #endif |
623 | ||
624 | #if AIC_DEBUG_REGISTERS | |
625 | ahd_reg_print_t ahd_iownid_print; | |
626 | #else | |
627 | #define ahd_iownid_print(regvalue, cur_col, wrap) \ | |
628 | ahd_print_register(NULL, 0, "IOWNID", 0x67, regvalue, cur_col, wrap) | |
629 | #endif | |
630 | ||
1da177e4 LT |
631 | #if AIC_DEBUG_REGISTERS |
632 | ahd_reg_print_t ahd_shcnt_print; | |
633 | #else | |
634 | #define ahd_shcnt_print(regvalue, cur_col, wrap) \ | |
635 | ahd_print_register(NULL, 0, "SHCNT", 0x68, regvalue, cur_col, wrap) | |
636 | #endif | |
637 | ||
638 | #if AIC_DEBUG_REGISTERS | |
639 | ahd_reg_print_t ahd_townid_print; | |
640 | #else | |
641 | #define ahd_townid_print(regvalue, cur_col, wrap) \ | |
642 | ahd_print_register(NULL, 0, "TOWNID", 0x69, regvalue, cur_col, wrap) | |
643 | #endif | |
644 | ||
1da177e4 LT |
645 | #if AIC_DEBUG_REGISTERS |
646 | ahd_reg_print_t ahd_seloid_print; | |
647 | #else | |
648 | #define ahd_seloid_print(regvalue, cur_col, wrap) \ | |
649 | ahd_print_register(NULL, 0, "SELOID", 0x6b, regvalue, cur_col, wrap) | |
650 | #endif | |
651 | ||
1da177e4 LT |
652 | #if AIC_DEBUG_REGISTERS |
653 | ahd_reg_print_t ahd_scbhaddr_print; | |
654 | #else | |
655 | #define ahd_scbhaddr_print(regvalue, cur_col, wrap) \ | |
656 | ahd_print_register(NULL, 0, "SCBHADDR", 0x7c, regvalue, cur_col, wrap) | |
657 | #endif | |
658 | ||
659 | #if AIC_DEBUG_REGISTERS | |
060ae855 | 660 | ahd_reg_print_t ahd_sghaddr_print; |
1da177e4 | 661 | #else |
060ae855 DV |
662 | #define ahd_sghaddr_print(regvalue, cur_col, wrap) \ |
663 | ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap) | |
1da177e4 LT |
664 | #endif |
665 | ||
666 | #if AIC_DEBUG_REGISTERS | |
667 | ahd_reg_print_t ahd_scbhcnt_print; | |
668 | #else | |
669 | #define ahd_scbhcnt_print(regvalue, cur_col, wrap) \ | |
670 | ahd_print_register(NULL, 0, "SCBHCNT", 0x84, regvalue, cur_col, wrap) | |
671 | #endif | |
672 | ||
673 | #if AIC_DEBUG_REGISTERS | |
060ae855 | 674 | ahd_reg_print_t ahd_sghcnt_print; |
1da177e4 | 675 | #else |
060ae855 DV |
676 | #define ahd_sghcnt_print(regvalue, cur_col, wrap) \ |
677 | ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap) | |
1da177e4 LT |
678 | #endif |
679 | ||
680 | #if AIC_DEBUG_REGISTERS | |
d10c2e46 | 681 | ahd_reg_print_t ahd_pcixctl_print; |
1da177e4 | 682 | #else |
d10c2e46 HR |
683 | #define ahd_pcixctl_print(regvalue, cur_col, wrap) \ |
684 | ahd_print_register(NULL, 0, "PCIXCTL", 0x93, regvalue, cur_col, wrap) | |
1da177e4 LT |
685 | #endif |
686 | ||
687 | #if AIC_DEBUG_REGISTERS | |
d10c2e46 | 688 | ahd_reg_print_t ahd_dchspltstat0_print; |
1da177e4 | 689 | #else |
d10c2e46 HR |
690 | #define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \ |
691 | ahd_print_register(NULL, 0, "DCHSPLTSTAT0", 0x96, regvalue, cur_col, wrap) | |
1da177e4 LT |
692 | #endif |
693 | ||
694 | #if AIC_DEBUG_REGISTERS | |
d10c2e46 | 695 | ahd_reg_print_t ahd_dchspltstat1_print; |
1da177e4 | 696 | #else |
d10c2e46 HR |
697 | #define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \ |
698 | ahd_print_register(NULL, 0, "DCHSPLTSTAT1", 0x97, regvalue, cur_col, wrap) | |
1da177e4 LT |
699 | #endif |
700 | ||
701 | #if AIC_DEBUG_REGISTERS | |
d10c2e46 | 702 | ahd_reg_print_t ahd_sgspltstat0_print; |
1da177e4 | 703 | #else |
d10c2e46 HR |
704 | #define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \ |
705 | ahd_print_register(NULL, 0, "SGSPLTSTAT0", 0x9e, regvalue, cur_col, wrap) | |
1da177e4 LT |
706 | #endif |
707 | ||
708 | #if AIC_DEBUG_REGISTERS | |
d10c2e46 | 709 | ahd_reg_print_t ahd_sgspltstat1_print; |
1da177e4 | 710 | #else |
d10c2e46 HR |
711 | #define ahd_sgspltstat1_print(regvalue, cur_col, wrap) \ |
712 | ahd_print_register(NULL, 0, "SGSPLTSTAT1", 0x9f, regvalue, cur_col, wrap) | |
1da177e4 LT |
713 | #endif |
714 | ||
715 | #if AIC_DEBUG_REGISTERS | |
d10c2e46 | 716 | ahd_reg_print_t ahd_df0pcistat_print; |
1da177e4 | 717 | #else |
d10c2e46 HR |
718 | #define ahd_df0pcistat_print(regvalue, cur_col, wrap) \ |
719 | ahd_print_register(NULL, 0, "DF0PCISTAT", 0xa0, regvalue, cur_col, wrap) | |
1da177e4 LT |
720 | #endif |
721 | ||
722 | #if AIC_DEBUG_REGISTERS | |
d10c2e46 | 723 | ahd_reg_print_t ahd_reg0_print; |
1da177e4 | 724 | #else |
d10c2e46 HR |
725 | #define ahd_reg0_print(regvalue, cur_col, wrap) \ |
726 | ahd_print_register(NULL, 0, "REG0", 0xa0, regvalue, cur_col, wrap) | |
1da177e4 LT |
727 | #endif |
728 | ||
729 | #if AIC_DEBUG_REGISTERS | |
d10c2e46 | 730 | ahd_reg_print_t ahd_reg_isr_print; |
1da177e4 LT |
731 | #else |
732 | #define ahd_reg_isr_print(regvalue, cur_col, wrap) \ | |
733 | ahd_print_register(NULL, 0, "REG_ISR", 0xa4, regvalue, cur_col, wrap) | |
734 | #endif | |
735 | ||
736 | #if AIC_DEBUG_REGISTERS | |
737 | ahd_reg_print_t ahd_sg_state_print; | |
738 | #else | |
739 | #define ahd_sg_state_print(regvalue, cur_col, wrap) \ | |
740 | ahd_print_register(NULL, 0, "SG_STATE", 0xa6, regvalue, cur_col, wrap) | |
741 | #endif | |
742 | ||
1da177e4 LT |
743 | #if AIC_DEBUG_REGISTERS |
744 | ahd_reg_print_t ahd_targpcistat_print; | |
745 | #else | |
746 | #define ahd_targpcistat_print(regvalue, cur_col, wrap) \ | |
747 | ahd_print_register(NULL, 0, "TARGPCISTAT", 0xa7, regvalue, cur_col, wrap) | |
748 | #endif | |
749 | ||
1da177e4 LT |
750 | #if AIC_DEBUG_REGISTERS |
751 | ahd_reg_print_t ahd_scbautoptr_print; | |
752 | #else | |
753 | #define ahd_scbautoptr_print(regvalue, cur_col, wrap) \ | |
754 | ahd_print_register(NULL, 0, "SCBAUTOPTR", 0xab, regvalue, cur_col, wrap) | |
755 | #endif | |
756 | ||
1da177e4 | 757 | #if AIC_DEBUG_REGISTERS |
11668bb6 | 758 | ahd_reg_print_t ahd_ccscbaddr_print; |
1da177e4 | 759 | #else |
11668bb6 HR |
760 | #define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \ |
761 | ahd_print_register(NULL, 0, "CCSCBADDR", 0xac, regvalue, cur_col, wrap) | |
1da177e4 LT |
762 | #endif |
763 | ||
1da177e4 | 764 | #if AIC_DEBUG_REGISTERS |
11668bb6 | 765 | ahd_reg_print_t ahd_ccscbctl_print; |
1da177e4 | 766 | #else |
11668bb6 HR |
767 | #define ahd_ccscbctl_print(regvalue, cur_col, wrap) \ |
768 | ahd_print_register(NULL, 0, "CCSCBCTL", 0xad, regvalue, cur_col, wrap) | |
1da177e4 LT |
769 | #endif |
770 | ||
771 | #if AIC_DEBUG_REGISTERS | |
11668bb6 | 772 | ahd_reg_print_t ahd_ccsgctl_print; |
1da177e4 | 773 | #else |
11668bb6 HR |
774 | #define ahd_ccsgctl_print(regvalue, cur_col, wrap) \ |
775 | ahd_print_register(NULL, 0, "CCSGCTL", 0xad, regvalue, cur_col, wrap) | |
1da177e4 LT |
776 | #endif |
777 | ||
1da177e4 LT |
778 | #if AIC_DEBUG_REGISTERS |
779 | ahd_reg_print_t ahd_ccscbram_print; | |
780 | #else | |
781 | #define ahd_ccscbram_print(regvalue, cur_col, wrap) \ | |
782 | ahd_print_register(NULL, 0, "CCSCBRAM", 0xb0, regvalue, cur_col, wrap) | |
783 | #endif | |
784 | ||
1da177e4 LT |
785 | #if AIC_DEBUG_REGISTERS |
786 | ahd_reg_print_t ahd_brddat_print; | |
787 | #else | |
788 | #define ahd_brddat_print(regvalue, cur_col, wrap) \ | |
789 | ahd_print_register(NULL, 0, "BRDDAT", 0xb8, regvalue, cur_col, wrap) | |
790 | #endif | |
791 | ||
1da177e4 LT |
792 | #if AIC_DEBUG_REGISTERS |
793 | ahd_reg_print_t ahd_seeadr_print; | |
794 | #else | |
795 | #define ahd_seeadr_print(regvalue, cur_col, wrap) \ | |
796 | ahd_print_register(NULL, 0, "SEEADR", 0xba, regvalue, cur_col, wrap) | |
797 | #endif | |
798 | ||
799 | #if AIC_DEBUG_REGISTERS | |
800 | ahd_reg_print_t ahd_seedat_print; | |
801 | #else | |
802 | #define ahd_seedat_print(regvalue, cur_col, wrap) \ | |
803 | ahd_print_register(NULL, 0, "SEEDAT", 0xbc, regvalue, cur_col, wrap) | |
804 | #endif | |
805 | ||
806 | #if AIC_DEBUG_REGISTERS | |
807 | ahd_reg_print_t ahd_seectl_print; | |
808 | #else | |
809 | #define ahd_seectl_print(regvalue, cur_col, wrap) \ | |
810 | ahd_print_register(NULL, 0, "SEECTL", 0xbe, regvalue, cur_col, wrap) | |
811 | #endif | |
812 | ||
813 | #if AIC_DEBUG_REGISTERS | |
814 | ahd_reg_print_t ahd_seestat_print; | |
815 | #else | |
816 | #define ahd_seestat_print(regvalue, cur_col, wrap) \ | |
817 | ahd_print_register(NULL, 0, "SEESTAT", 0xbe, regvalue, cur_col, wrap) | |
818 | #endif | |
819 | ||
1da177e4 LT |
820 | #if AIC_DEBUG_REGISTERS |
821 | ahd_reg_print_t ahd_dspdatactl_print; | |
822 | #else | |
823 | #define ahd_dspdatactl_print(regvalue, cur_col, wrap) \ | |
824 | ahd_print_register(NULL, 0, "DSPDATACTL", 0xc1, regvalue, cur_col, wrap) | |
825 | #endif | |
826 | ||
1da177e4 LT |
827 | #if AIC_DEBUG_REGISTERS |
828 | ahd_reg_print_t ahd_dspselect_print; | |
829 | #else | |
830 | #define ahd_dspselect_print(regvalue, cur_col, wrap) \ | |
831 | ahd_print_register(NULL, 0, "DSPSELECT", 0xc4, regvalue, cur_col, wrap) | |
832 | #endif | |
833 | ||
834 | #if AIC_DEBUG_REGISTERS | |
835 | ahd_reg_print_t ahd_wrtbiasctl_print; | |
836 | #else | |
837 | #define ahd_wrtbiasctl_print(regvalue, cur_col, wrap) \ | |
838 | ahd_print_register(NULL, 0, "WRTBIASCTL", 0xc5, regvalue, cur_col, wrap) | |
839 | #endif | |
840 | ||
1da177e4 LT |
841 | #if AIC_DEBUG_REGISTERS |
842 | ahd_reg_print_t ahd_seqctl0_print; | |
843 | #else | |
844 | #define ahd_seqctl0_print(regvalue, cur_col, wrap) \ | |
845 | ahd_print_register(NULL, 0, "SEQCTL0", 0xd6, regvalue, cur_col, wrap) | |
846 | #endif | |
847 | ||
1da177e4 LT |
848 | #if AIC_DEBUG_REGISTERS |
849 | ahd_reg_print_t ahd_seqintctl_print; | |
850 | #else | |
851 | #define ahd_seqintctl_print(regvalue, cur_col, wrap) \ | |
852 | ahd_print_register(NULL, 0, "SEQINTCTL", 0xd9, regvalue, cur_col, wrap) | |
853 | #endif | |
854 | ||
1da177e4 LT |
855 | #if AIC_DEBUG_REGISTERS |
856 | ahd_reg_print_t ahd_prgmcnt_print; | |
857 | #else | |
858 | #define ahd_prgmcnt_print(regvalue, cur_col, wrap) \ | |
859 | ahd_print_register(NULL, 0, "PRGMCNT", 0xde, regvalue, cur_col, wrap) | |
860 | #endif | |
861 | ||
1da177e4 LT |
862 | #if AIC_DEBUG_REGISTERS |
863 | ahd_reg_print_t ahd_none_print; | |
864 | #else | |
865 | #define ahd_none_print(regvalue, cur_col, wrap) \ | |
866 | ahd_print_register(NULL, 0, "NONE", 0xea, regvalue, cur_col, wrap) | |
867 | #endif | |
868 | ||
1da177e4 LT |
869 | #if AIC_DEBUG_REGISTERS |
870 | ahd_reg_print_t ahd_intvec1_addr_print; | |
871 | #else | |
872 | #define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \ | |
873 | ahd_print_register(NULL, 0, "INTVEC1_ADDR", 0xf4, regvalue, cur_col, wrap) | |
874 | #endif | |
875 | ||
876 | #if AIC_DEBUG_REGISTERS | |
11668bb6 | 877 | ahd_reg_print_t ahd_curaddr_print; |
1da177e4 | 878 | #else |
11668bb6 HR |
879 | #define ahd_curaddr_print(regvalue, cur_col, wrap) \ |
880 | ahd_print_register(NULL, 0, "CURADDR", 0xf4, regvalue, cur_col, wrap) | |
1da177e4 LT |
881 | #endif |
882 | ||
11668bb6 HR |
883 | #if AIC_DEBUG_REGISTERS |
884 | ahd_reg_print_t ahd_intvec2_addr_print; | |
885 | #else | |
886 | #define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \ | |
887 | ahd_print_register(NULL, 0, "INTVEC2_ADDR", 0xf6, regvalue, cur_col, wrap) | |
888 | #endif | |
889 | ||
1da177e4 LT |
890 | #if AIC_DEBUG_REGISTERS |
891 | ahd_reg_print_t ahd_longjmp_addr_print; | |
892 | #else | |
893 | #define ahd_longjmp_addr_print(regvalue, cur_col, wrap) \ | |
894 | ahd_print_register(NULL, 0, "LONGJMP_ADDR", 0xf8, regvalue, cur_col, wrap) | |
895 | #endif | |
896 | ||
897 | #if AIC_DEBUG_REGISTERS | |
898 | ahd_reg_print_t ahd_accum_save_print; | |
899 | #else | |
900 | #define ahd_accum_save_print(regvalue, cur_col, wrap) \ | |
901 | ahd_print_register(NULL, 0, "ACCUM_SAVE", 0xfa, regvalue, cur_col, wrap) | |
902 | #endif | |
903 | ||
904 | #if AIC_DEBUG_REGISTERS | |
060ae855 | 905 | ahd_reg_print_t ahd_waiting_scb_tails_print; |
1da177e4 | 906 | #else |
060ae855 DV |
907 | #define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \ |
908 | ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap) | |
1da177e4 LT |
909 | #endif |
910 | ||
911 | #if AIC_DEBUG_REGISTERS | |
060ae855 | 912 | ahd_reg_print_t ahd_sram_base_print; |
1da177e4 | 913 | #else |
060ae855 DV |
914 | #define ahd_sram_base_print(regvalue, cur_col, wrap) \ |
915 | ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap) | |
1da177e4 LT |
916 | #endif |
917 | ||
918 | #if AIC_DEBUG_REGISTERS | |
919 | ahd_reg_print_t ahd_waiting_tid_head_print; | |
920 | #else | |
921 | #define ahd_waiting_tid_head_print(regvalue, cur_col, wrap) \ | |
922 | ahd_print_register(NULL, 0, "WAITING_TID_HEAD", 0x120, regvalue, cur_col, wrap) | |
923 | #endif | |
924 | ||
925 | #if AIC_DEBUG_REGISTERS | |
926 | ahd_reg_print_t ahd_waiting_tid_tail_print; | |
927 | #else | |
928 | #define ahd_waiting_tid_tail_print(regvalue, cur_col, wrap) \ | |
929 | ahd_print_register(NULL, 0, "WAITING_TID_TAIL", 0x122, regvalue, cur_col, wrap) | |
930 | #endif | |
931 | ||
932 | #if AIC_DEBUG_REGISTERS | |
933 | ahd_reg_print_t ahd_next_queued_scb_addr_print; | |
934 | #else | |
935 | #define ahd_next_queued_scb_addr_print(regvalue, cur_col, wrap) \ | |
936 | ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR", 0x124, regvalue, cur_col, wrap) | |
937 | #endif | |
938 | ||
939 | #if AIC_DEBUG_REGISTERS | |
940 | ahd_reg_print_t ahd_complete_scb_head_print; | |
941 | #else | |
942 | #define ahd_complete_scb_head_print(regvalue, cur_col, wrap) \ | |
943 | ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD", 0x128, regvalue, cur_col, wrap) | |
944 | #endif | |
945 | ||
946 | #if AIC_DEBUG_REGISTERS | |
947 | ahd_reg_print_t ahd_complete_scb_dmainprog_head_print; | |
948 | #else | |
949 | #define ahd_complete_scb_dmainprog_head_print(regvalue, cur_col, wrap) \ | |
950 | ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD", 0x12a, regvalue, cur_col, wrap) | |
951 | #endif | |
952 | ||
953 | #if AIC_DEBUG_REGISTERS | |
954 | ahd_reg_print_t ahd_complete_dma_scb_head_print; | |
955 | #else | |
956 | #define ahd_complete_dma_scb_head_print(regvalue, cur_col, wrap) \ | |
957 | ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD", 0x12c, regvalue, cur_col, wrap) | |
958 | #endif | |
959 | ||
11668bb6 HR |
960 | #if AIC_DEBUG_REGISTERS |
961 | ahd_reg_print_t ahd_complete_dma_scb_tail_print; | |
962 | #else | |
963 | #define ahd_complete_dma_scb_tail_print(regvalue, cur_col, wrap) \ | |
964 | ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL", 0x12e, regvalue, cur_col, wrap) | |
965 | #endif | |
966 | ||
967 | #if AIC_DEBUG_REGISTERS | |
968 | ahd_reg_print_t ahd_complete_on_qfreeze_head_print; | |
969 | #else | |
970 | #define ahd_complete_on_qfreeze_head_print(regvalue, cur_col, wrap) \ | |
971 | ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD", 0x130, regvalue, cur_col, wrap) | |
972 | #endif | |
973 | ||
1da177e4 LT |
974 | #if AIC_DEBUG_REGISTERS |
975 | ahd_reg_print_t ahd_qfreeze_count_print; | |
976 | #else | |
977 | #define ahd_qfreeze_count_print(regvalue, cur_col, wrap) \ | |
11668bb6 HR |
978 | ahd_print_register(NULL, 0, "QFREEZE_COUNT", 0x132, regvalue, cur_col, wrap) |
979 | #endif | |
980 | ||
981 | #if AIC_DEBUG_REGISTERS | |
982 | ahd_reg_print_t ahd_kernel_qfreeze_count_print; | |
983 | #else | |
984 | #define ahd_kernel_qfreeze_count_print(regvalue, cur_col, wrap) \ | |
985 | ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT", 0x134, regvalue, cur_col, wrap) | |
1da177e4 LT |
986 | #endif |
987 | ||
988 | #if AIC_DEBUG_REGISTERS | |
989 | ahd_reg_print_t ahd_saved_mode_print; | |
990 | #else | |
991 | #define ahd_saved_mode_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 992 | ahd_print_register(NULL, 0, "SAVED_MODE", 0x136, regvalue, cur_col, wrap) |
1da177e4 LT |
993 | #endif |
994 | ||
995 | #if AIC_DEBUG_REGISTERS | |
996 | ahd_reg_print_t ahd_msg_out_print; | |
997 | #else | |
998 | #define ahd_msg_out_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 999 | ahd_print_register(NULL, 0, "MSG_OUT", 0x137, regvalue, cur_col, wrap) |
1da177e4 LT |
1000 | #endif |
1001 | ||
1da177e4 LT |
1002 | #if AIC_DEBUG_REGISTERS |
1003 | ahd_reg_print_t ahd_seq_flags_print; | |
1004 | #else | |
1005 | #define ahd_seq_flags_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 1006 | ahd_print_register(NULL, 0, "SEQ_FLAGS", 0x139, regvalue, cur_col, wrap) |
1da177e4 LT |
1007 | #endif |
1008 | ||
1da177e4 LT |
1009 | #if AIC_DEBUG_REGISTERS |
1010 | ahd_reg_print_t ahd_lastphase_print; | |
1011 | #else | |
1012 | #define ahd_lastphase_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 1013 | ahd_print_register(NULL, 0, "LASTPHASE", 0x13c, regvalue, cur_col, wrap) |
1da177e4 LT |
1014 | #endif |
1015 | ||
1016 | #if AIC_DEBUG_REGISTERS | |
1017 | ahd_reg_print_t ahd_qoutfifo_entry_valid_tag_print; | |
1018 | #else | |
1019 | #define ahd_qoutfifo_entry_valid_tag_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 1020 | ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG", 0x13d, regvalue, cur_col, wrap) |
1da177e4 LT |
1021 | #endif |
1022 | ||
1023 | #if AIC_DEBUG_REGISTERS | |
11668bb6 | 1024 | ahd_reg_print_t ahd_kernel_tqinpos_print; |
1da177e4 | 1025 | #else |
11668bb6 HR |
1026 | #define ahd_kernel_tqinpos_print(regvalue, cur_col, wrap) \ |
1027 | ahd_print_register(NULL, 0, "KERNEL_TQINPOS", 0x13e, regvalue, cur_col, wrap) | |
1da177e4 LT |
1028 | #endif |
1029 | ||
1da177e4 | 1030 | #if AIC_DEBUG_REGISTERS |
11668bb6 | 1031 | ahd_reg_print_t ahd_qoutfifo_next_addr_print; |
1da177e4 | 1032 | #else |
11668bb6 HR |
1033 | #define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \ |
1034 | ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR", 0x144, regvalue, cur_col, wrap) | |
1da177e4 LT |
1035 | #endif |
1036 | ||
1da177e4 LT |
1037 | #if AIC_DEBUG_REGISTERS |
1038 | ahd_reg_print_t ahd_last_msg_print; | |
1039 | #else | |
1040 | #define ahd_last_msg_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 1041 | ahd_print_register(NULL, 0, "LAST_MSG", 0x14a, regvalue, cur_col, wrap) |
1da177e4 LT |
1042 | #endif |
1043 | ||
1044 | #if AIC_DEBUG_REGISTERS | |
1045 | ahd_reg_print_t ahd_scsiseq_template_print; | |
1046 | #else | |
1047 | #define ahd_scsiseq_template_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 1048 | ahd_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x14b, regvalue, cur_col, wrap) |
1da177e4 LT |
1049 | #endif |
1050 | ||
1051 | #if AIC_DEBUG_REGISTERS | |
1052 | ahd_reg_print_t ahd_initiator_tag_print; | |
1053 | #else | |
1054 | #define ahd_initiator_tag_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 1055 | ahd_print_register(NULL, 0, "INITIATOR_TAG", 0x14c, regvalue, cur_col, wrap) |
1da177e4 LT |
1056 | #endif |
1057 | ||
1058 | #if AIC_DEBUG_REGISTERS | |
1059 | ahd_reg_print_t ahd_seq_flags2_print; | |
1060 | #else | |
1061 | #define ahd_seq_flags2_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 1062 | ahd_print_register(NULL, 0, "SEQ_FLAGS2", 0x14d, regvalue, cur_col, wrap) |
1da177e4 LT |
1063 | #endif |
1064 | ||
1065 | #if AIC_DEBUG_REGISTERS | |
1066 | ahd_reg_print_t ahd_allocfifo_scbptr_print; | |
1067 | #else | |
1068 | #define ahd_allocfifo_scbptr_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 1069 | ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR", 0x14e, regvalue, cur_col, wrap) |
1da177e4 LT |
1070 | #endif |
1071 | ||
1072 | #if AIC_DEBUG_REGISTERS | |
1073 | ahd_reg_print_t ahd_int_coalescing_timer_print; | |
1074 | #else | |
1075 | #define ahd_int_coalescing_timer_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 1076 | ahd_print_register(NULL, 0, "INT_COALESCING_TIMER", 0x150, regvalue, cur_col, wrap) |
1da177e4 LT |
1077 | #endif |
1078 | ||
1079 | #if AIC_DEBUG_REGISTERS | |
1080 | ahd_reg_print_t ahd_int_coalescing_maxcmds_print; | |
1081 | #else | |
1082 | #define ahd_int_coalescing_maxcmds_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 1083 | ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS", 0x152, regvalue, cur_col, wrap) |
1da177e4 LT |
1084 | #endif |
1085 | ||
1086 | #if AIC_DEBUG_REGISTERS | |
1087 | ahd_reg_print_t ahd_int_coalescing_mincmds_print; | |
1088 | #else | |
1089 | #define ahd_int_coalescing_mincmds_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 1090 | ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS", 0x153, regvalue, cur_col, wrap) |
1da177e4 LT |
1091 | #endif |
1092 | ||
1093 | #if AIC_DEBUG_REGISTERS | |
1094 | ahd_reg_print_t ahd_cmds_pending_print; | |
1095 | #else | |
1096 | #define ahd_cmds_pending_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 1097 | ahd_print_register(NULL, 0, "CMDS_PENDING", 0x154, regvalue, cur_col, wrap) |
1da177e4 LT |
1098 | #endif |
1099 | ||
1100 | #if AIC_DEBUG_REGISTERS | |
1101 | ahd_reg_print_t ahd_int_coalescing_cmdcount_print; | |
1102 | #else | |
1103 | #define ahd_int_coalescing_cmdcount_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 1104 | ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT", 0x156, regvalue, cur_col, wrap) |
1da177e4 LT |
1105 | #endif |
1106 | ||
1107 | #if AIC_DEBUG_REGISTERS | |
1108 | ahd_reg_print_t ahd_local_hs_mailbox_print; | |
1109 | #else | |
1110 | #define ahd_local_hs_mailbox_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 1111 | ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX", 0x157, regvalue, cur_col, wrap) |
1da177e4 LT |
1112 | #endif |
1113 | ||
1114 | #if AIC_DEBUG_REGISTERS | |
1115 | ahd_reg_print_t ahd_cmdsize_table_print; | |
1116 | #else | |
1117 | #define ahd_cmdsize_table_print(regvalue, cur_col, wrap) \ | |
11668bb6 | 1118 | ahd_print_register(NULL, 0, "CMDSIZE_TABLE", 0x158, regvalue, cur_col, wrap) |
1da177e4 LT |
1119 | #endif |
1120 | ||
53467e63 HR |
1121 | #if AIC_DEBUG_REGISTERS |
1122 | ahd_reg_print_t ahd_mk_message_scb_print; | |
1123 | #else | |
1124 | #define ahd_mk_message_scb_print(regvalue, cur_col, wrap) \ | |
1125 | ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", 0x160, regvalue, cur_col, wrap) | |
1126 | #endif | |
1127 | ||
1128 | #if AIC_DEBUG_REGISTERS | |
1129 | ahd_reg_print_t ahd_mk_message_scsiid_print; | |
1130 | #else | |
1131 | #define ahd_mk_message_scsiid_print(regvalue, cur_col, wrap) \ | |
1132 | ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID", 0x162, regvalue, cur_col, wrap) | |
1133 | #endif | |
1134 | ||
1da177e4 | 1135 | #if AIC_DEBUG_REGISTERS |
d10c2e46 | 1136 | ahd_reg_print_t ahd_scb_base_print; |
1da177e4 | 1137 | #else |
d10c2e46 HR |
1138 | #define ahd_scb_base_print(regvalue, cur_col, wrap) \ |
1139 | ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap) | |
1da177e4 LT |
1140 | #endif |
1141 | ||
1142 | #if AIC_DEBUG_REGISTERS | |
060ae855 | 1143 | ahd_reg_print_t ahd_scb_residual_datacnt_print; |
1da177e4 | 1144 | #else |
060ae855 DV |
1145 | #define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \ |
1146 | ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap) | |
1da177e4 LT |
1147 | #endif |
1148 | ||
1da177e4 LT |
1149 | #if AIC_DEBUG_REGISTERS |
1150 | ahd_reg_print_t ahd_scb_sense_busaddr_print; | |
1151 | #else | |
1152 | #define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \ | |
1153 | ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR", 0x18c, regvalue, cur_col, wrap) | |
1154 | #endif | |
1155 | ||
1156 | #if AIC_DEBUG_REGISTERS | |
1157 | ahd_reg_print_t ahd_scb_tag_print; | |
1158 | #else | |
1159 | #define ahd_scb_tag_print(regvalue, cur_col, wrap) \ | |
1160 | ahd_print_register(NULL, 0, "SCB_TAG", 0x190, regvalue, cur_col, wrap) | |
1161 | #endif | |
1162 | ||
1163 | #if AIC_DEBUG_REGISTERS | |
1164 | ahd_reg_print_t ahd_scb_control_print; | |
1165 | #else | |
1166 | #define ahd_scb_control_print(regvalue, cur_col, wrap) \ | |
1167 | ahd_print_register(NULL, 0, "SCB_CONTROL", 0x192, regvalue, cur_col, wrap) | |
1168 | #endif | |
1169 | ||
1170 | #if AIC_DEBUG_REGISTERS | |
1171 | ahd_reg_print_t ahd_scb_scsiid_print; | |
1172 | #else | |
1173 | #define ahd_scb_scsiid_print(regvalue, cur_col, wrap) \ | |
1174 | ahd_print_register(NULL, 0, "SCB_SCSIID", 0x193, regvalue, cur_col, wrap) | |
1175 | #endif | |
1176 | ||
1177 | #if AIC_DEBUG_REGISTERS | |
1178 | ahd_reg_print_t ahd_scb_lun_print; | |
1179 | #else | |
1180 | #define ahd_scb_lun_print(regvalue, cur_col, wrap) \ | |
1181 | ahd_print_register(NULL, 0, "SCB_LUN", 0x194, regvalue, cur_col, wrap) | |
1182 | #endif | |
1183 | ||
1184 | #if AIC_DEBUG_REGISTERS | |
1185 | ahd_reg_print_t ahd_scb_task_attribute_print; | |
1186 | #else | |
1187 | #define ahd_scb_task_attribute_print(regvalue, cur_col, wrap) \ | |
1188 | ahd_print_register(NULL, 0, "SCB_TASK_ATTRIBUTE", 0x195, regvalue, cur_col, wrap) | |
1189 | #endif | |
1190 | ||
1da177e4 LT |
1191 | #if AIC_DEBUG_REGISTERS |
1192 | ahd_reg_print_t ahd_scb_task_management_print; | |
1193 | #else | |
1194 | #define ahd_scb_task_management_print(regvalue, cur_col, wrap) \ | |
1195 | ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT", 0x197, regvalue, cur_col, wrap) | |
1196 | #endif | |
1197 | ||
1198 | #if AIC_DEBUG_REGISTERS | |
1199 | ahd_reg_print_t ahd_scb_dataptr_print; | |
1200 | #else | |
1201 | #define ahd_scb_dataptr_print(regvalue, cur_col, wrap) \ | |
1202 | ahd_print_register(NULL, 0, "SCB_DATAPTR", 0x198, regvalue, cur_col, wrap) | |
1203 | #endif | |
1204 | ||
1205 | #if AIC_DEBUG_REGISTERS | |
1206 | ahd_reg_print_t ahd_scb_datacnt_print; | |
1207 | #else | |
1208 | #define ahd_scb_datacnt_print(regvalue, cur_col, wrap) \ | |
1209 | ahd_print_register(NULL, 0, "SCB_DATACNT", 0x1a0, regvalue, cur_col, wrap) | |
1210 | #endif | |
1211 | ||
1212 | #if AIC_DEBUG_REGISTERS | |
1213 | ahd_reg_print_t ahd_scb_sgptr_print; | |
1214 | #else | |
1215 | #define ahd_scb_sgptr_print(regvalue, cur_col, wrap) \ | |
1216 | ahd_print_register(NULL, 0, "SCB_SGPTR", 0x1a4, regvalue, cur_col, wrap) | |
1217 | #endif | |
1218 | ||
1219 | #if AIC_DEBUG_REGISTERS | |
1220 | ahd_reg_print_t ahd_scb_busaddr_print; | |
1221 | #else | |
1222 | #define ahd_scb_busaddr_print(regvalue, cur_col, wrap) \ | |
1223 | ahd_print_register(NULL, 0, "SCB_BUSADDR", 0x1a8, regvalue, cur_col, wrap) | |
1224 | #endif | |
1225 | ||
1da177e4 LT |
1226 | #if AIC_DEBUG_REGISTERS |
1227 | ahd_reg_print_t ahd_scb_next2_print; | |
1228 | #else | |
1229 | #define ahd_scb_next2_print(regvalue, cur_col, wrap) \ | |
1230 | ahd_print_register(NULL, 0, "SCB_NEXT2", 0x1ae, regvalue, cur_col, wrap) | |
1231 | #endif | |
1232 | ||
1da177e4 LT |
1233 | #if AIC_DEBUG_REGISTERS |
1234 | ahd_reg_print_t ahd_scb_disconnected_lists_print; | |
1235 | #else | |
1236 | #define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \ | |
1237 | ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS", 0x1b8, regvalue, cur_col, wrap) | |
1238 | #endif | |
1239 | ||
1240 | ||
1241 | #define MODE_PTR 0x00 | |
1242 | #define DST_MODE 0x70 | |
1243 | #define SRC_MODE 0x07 | |
1244 | ||
1245 | #define INTSTAT 0x01 | |
1246 | #define INT_PEND 0xff | |
1247 | #define HWERRINT 0x80 | |
1248 | #define BRKADRINT 0x40 | |
1249 | #define SWTMINT 0x20 | |
1250 | #define PCIINT 0x10 | |
1251 | #define SCSIINT 0x08 | |
1252 | #define SEQINT 0x04 | |
1253 | #define CMDCMPLT 0x02 | |
1254 | #define SPLTINT 0x01 | |
1255 | ||
1256 | #define SEQINTCODE 0x02 | |
1257 | #define BAD_SCB_STATUS 0x1a | |
1258 | #define SAW_HWERR 0x19 | |
1259 | #define TRACEPOINT3 0x18 | |
1260 | #define TRACEPOINT2 0x17 | |
1261 | #define TRACEPOINT1 0x16 | |
1262 | #define TRACEPOINT0 0x15 | |
1263 | #define TASKMGMT_CMD_CMPLT_OKAY 0x14 | |
1264 | #define TASKMGMT_FUNC_COMPLETE 0x13 | |
1265 | #define ENTERING_NONPACK 0x12 | |
1266 | #define CFG4OVERRUN 0x11 | |
1267 | #define STATUS_OVERRUN 0x10 | |
1268 | #define CFG4ISTAT_INTR 0x0f | |
1269 | #define INVALID_SEQINT 0x0e | |
1270 | #define ILLEGAL_PHASE 0x0d | |
1271 | #define DUMP_CARD_STATE 0x0c | |
1272 | #define MISSED_BUSFREE 0x0b | |
1273 | #define MKMSG_FAILED 0x0a | |
1274 | #define DATA_OVERRUN 0x09 | |
1275 | #define BAD_STATUS 0x08 | |
1276 | #define HOST_MSG_LOOP 0x07 | |
1277 | #define PDATA_REINIT 0x06 | |
1278 | #define IGN_WIDE_RES 0x05 | |
1279 | #define NO_MATCH 0x04 | |
1280 | #define PROTO_VIOLATION 0x03 | |
1281 | #define SEND_REJECT 0x02 | |
1282 | #define BAD_PHASE 0x01 | |
1283 | #define NO_SEQINT 0x00 | |
1284 | ||
1285 | #define CLRINT 0x03 | |
1286 | #define CLRHWERRINT 0x80 | |
1287 | #define CLRBRKADRINT 0x40 | |
1288 | #define CLRSWTMINT 0x20 | |
1289 | #define CLRPCIINT 0x10 | |
1290 | #define CLRSCSIINT 0x08 | |
1291 | #define CLRSEQINT 0x04 | |
1292 | #define CLRCMDINT 0x02 | |
1293 | #define CLRSPLTINT 0x01 | |
1294 | ||
1295 | #define ERROR 0x04 | |
1296 | #define CIOPARERR 0x80 | |
1297 | #define CIOACCESFAIL 0x40 | |
1298 | #define MPARERR 0x20 | |
1299 | #define DPARERR 0x10 | |
1300 | #define SQPARERR 0x08 | |
1301 | #define ILLOPCODE 0x04 | |
1302 | #define DSCTMOUT 0x02 | |
1303 | ||
1304 | #define CLRERR 0x04 | |
1305 | #define CLRCIOPARERR 0x80 | |
1306 | #define CLRCIOACCESFAIL 0x40 | |
1307 | #define CLRMPARERR 0x20 | |
1308 | #define CLRDPARERR 0x10 | |
1309 | #define CLRSQPARERR 0x08 | |
1310 | #define CLRILLOPCODE 0x04 | |
1311 | #define CLRDSCTMOUT 0x02 | |
1312 | ||
1313 | #define HCNTRL 0x05 | |
1314 | #define SEQ_RESET 0x80 | |
1315 | #define POWRDN 0x40 | |
1316 | #define SWINT 0x10 | |
1317 | #define SWTIMER_START_B 0x08 | |
1318 | #define PAUSE 0x04 | |
1319 | #define INTEN 0x02 | |
1320 | #define CHIPRST 0x01 | |
1321 | #define CHIPRSTACK 0x01 | |
1322 | ||
1323 | #define HNSCB_QOFF 0x06 | |
1324 | ||
1325 | #define HESCB_QOFF 0x08 | |
1326 | ||
1327 | #define HS_MAILBOX 0x0b | |
1328 | #define HOST_TQINPOS 0x80 | |
1329 | #define ENINT_COALESCE 0x40 | |
1330 | ||
1da177e4 LT |
1331 | #define SEQINTSTAT 0x0c |
1332 | #define SEQ_SWTMRTO 0x10 | |
1333 | #define SEQ_SEQINT 0x08 | |
1334 | #define SEQ_SCSIINT 0x04 | |
1335 | #define SEQ_PCIINT 0x02 | |
1336 | #define SEQ_SPLTINT 0x01 | |
1337 | ||
11668bb6 HR |
1338 | #define CLRSEQINTSTAT 0x0c |
1339 | #define CLRSEQ_SWTMRTO 0x10 | |
1340 | #define CLRSEQ_SEQINT 0x08 | |
1341 | #define CLRSEQ_SCSIINT 0x04 | |
1342 | #define CLRSEQ_PCIINT 0x02 | |
1343 | #define CLRSEQ_SPLTINT 0x01 | |
1344 | ||
1da177e4 LT |
1345 | #define SWTIMER 0x0e |
1346 | ||
1347 | #define SNSCB_QOFF 0x10 | |
1348 | ||
1349 | #define SESCB_QOFF 0x12 | |
1350 | ||
1351 | #define SDSCB_QOFF 0x14 | |
1352 | ||
1353 | #define QOFF_CTLSTA 0x16 | |
1354 | #define EMPTY_SCB_AVAIL 0x80 | |
1355 | #define NEW_SCB_AVAIL 0x40 | |
1356 | #define SDSCB_ROLLOVR 0x20 | |
1357 | #define HS_MAILBOX_ACT 0x10 | |
1358 | #define SCB_QSIZE 0x0f | |
1359 | #define SCB_QSIZE_16384 0x0c | |
1360 | #define SCB_QSIZE_8192 0x0b | |
1361 | #define SCB_QSIZE_4096 0x0a | |
1362 | #define SCB_QSIZE_2048 0x09 | |
1363 | #define SCB_QSIZE_1024 0x08 | |
1364 | #define SCB_QSIZE_512 0x07 | |
1365 | #define SCB_QSIZE_256 0x06 | |
1366 | #define SCB_QSIZE_128 0x05 | |
1367 | #define SCB_QSIZE_64 0x04 | |
1368 | #define SCB_QSIZE_32 0x03 | |
1369 | #define SCB_QSIZE_16 0x02 | |
1370 | #define SCB_QSIZE_8 0x01 | |
1371 | #define SCB_QSIZE_4 0x00 | |
1372 | ||
1373 | #define INTCTL 0x18 | |
1374 | #define SWTMINTMASK 0x80 | |
1375 | #define SWTMINTEN 0x40 | |
1376 | #define SWTIMER_START 0x20 | |
1377 | #define AUTOCLRCMDINT 0x10 | |
1378 | #define PCIINTEN 0x08 | |
1379 | #define SCSIINTEN 0x04 | |
1380 | #define SEQINTEN 0x02 | |
1381 | #define SPLTINTEN 0x01 | |
1382 | ||
1383 | #define DFCNTRL 0x19 | |
1384 | #define SCSIENWRDIS 0x40 | |
1385 | #define SCSIENACK 0x20 | |
1386 | #define DIRECTIONACK 0x04 | |
1387 | #define FIFOFLUSHACK 0x02 | |
1388 | #define DIRECTIONEN 0x01 | |
1389 | ||
1390 | #define DSCOMMAND0 0x19 | |
1391 | #define CACHETHEN 0x80 | |
1392 | #define DPARCKEN 0x40 | |
1393 | #define MPARCKEN 0x20 | |
1394 | #define EXTREQLCK 0x10 | |
1395 | #define DISABLE_TWATE 0x02 | |
1396 | #define CIOPARCKEN 0x01 | |
1397 | ||
1398 | #define DFSTATUS 0x1a | |
1399 | #define PRELOAD_AVAIL 0x80 | |
1400 | #define PKT_PRELOAD_AVAIL 0x40 | |
1401 | #define MREQPEND 0x10 | |
1402 | #define HDONE 0x08 | |
1403 | #define DFTHRESH 0x04 | |
1404 | #define FIFOFULL 0x02 | |
1405 | #define FIFOEMP 0x01 | |
1406 | ||
1407 | #define SG_CACHE_SHADOW 0x1b | |
1408 | #define ODD_SEG 0x04 | |
1409 | #define LAST_SEG 0x02 | |
1410 | #define LAST_SEG_DONE 0x01 | |
1411 | ||
1412 | #define ARBCTL 0x1b | |
1413 | #define RESET_HARB 0x80 | |
1414 | #define RETRY_SWEN 0x08 | |
1415 | #define USE_TIME 0x07 | |
1416 | ||
1417 | #define SG_CACHE_PRE 0x1b | |
1418 | ||
d10c2e46 HR |
1419 | #define LQIN 0x20 |
1420 | ||
060ae855 DV |
1421 | #define TYPEPTR 0x20 |
1422 | ||
1da177e4 LT |
1423 | #define TAGPTR 0x21 |
1424 | ||
1425 | #define LUNPTR 0x22 | |
1426 | ||
1427 | #define DATALENPTR 0x23 | |
1428 | ||
1429 | #define STATLENPTR 0x24 | |
1430 | ||
1431 | #define CMDLENPTR 0x25 | |
1432 | ||
1433 | #define ATTRPTR 0x26 | |
1434 | ||
1435 | #define FLAGPTR 0x27 | |
1436 | ||
1437 | #define CMDPTR 0x28 | |
1438 | ||
1439 | #define QNEXTPTR 0x29 | |
1440 | ||
1441 | #define IDPTR 0x2a | |
1442 | ||
1443 | #define ABRTBYTEPTR 0x2b | |
1444 | ||
1445 | #define ABRTBITPTR 0x2c | |
1446 | ||
1447 | #define MAXCMDBYTES 0x2d | |
1448 | ||
1449 | #define MAXCMD2RCV 0x2e | |
1450 | ||
1451 | #define SHORTTHRESH 0x2f | |
1452 | ||
1453 | #define LUNLEN 0x30 | |
1454 | #define TLUNLEN 0xf0 | |
1455 | #define ILUNLEN 0x0f | |
1456 | ||
1457 | #define CDBLIMIT 0x31 | |
1458 | ||
1459 | #define MAXCMD 0x32 | |
1460 | ||
1461 | #define MAXCMDCNT 0x33 | |
1462 | ||
1463 | #define LQRSVD01 0x34 | |
1464 | ||
1465 | #define LQRSVD16 0x35 | |
1466 | ||
1467 | #define LQRSVD17 0x36 | |
1468 | ||
1469 | #define CMDRSVD0 0x37 | |
1470 | ||
1471 | #define LQCTL0 0x38 | |
1472 | #define LQITARGCLT 0xc0 | |
1473 | #define LQIINITGCLT 0x30 | |
1474 | #define LQ0TARGCLT 0x0c | |
1475 | #define LQ0INITGCLT 0x03 | |
1476 | ||
1477 | #define LQCTL1 0x38 | |
1478 | #define PCI2PCI 0x04 | |
1479 | #define SINGLECMD 0x02 | |
1480 | #define ABORTPENDING 0x01 | |
1481 | ||
060ae855 DV |
1482 | #define SCSBIST0 0x39 |
1483 | #define GSBISTERR 0x40 | |
1484 | #define GSBISTDONE 0x20 | |
1485 | #define GSBISTRUN 0x10 | |
1486 | #define OSBISTERR 0x04 | |
1487 | #define OSBISTDONE 0x02 | |
1488 | #define OSBISTRUN 0x01 | |
1489 | ||
1da177e4 LT |
1490 | #define LQCTL2 0x39 |
1491 | #define LQIRETRY 0x80 | |
1492 | #define LQICONTINUE 0x40 | |
1493 | #define LQITOIDLE 0x20 | |
1494 | #define LQIPAUSE 0x10 | |
1495 | #define LQORETRY 0x08 | |
1496 | #define LQOCONTINUE 0x04 | |
1497 | #define LQOTOIDLE 0x02 | |
1498 | #define LQOPAUSE 0x01 | |
1499 | ||
060ae855 DV |
1500 | #define SCSBIST1 0x3a |
1501 | #define NTBISTERR 0x04 | |
1502 | #define NTBISTDONE 0x02 | |
1503 | #define NTBISTRUN 0x01 | |
1da177e4 LT |
1504 | |
1505 | #define SCSISEQ0 0x3a | |
1506 | #define TEMODEO 0x80 | |
1507 | #define ENSELO 0x40 | |
1508 | #define ENARBO 0x20 | |
1509 | #define FORCEBUSFREE 0x10 | |
1510 | #define SCSIRSTO 0x01 | |
1511 | ||
1512 | #define SCSISEQ1 0x3b | |
1513 | ||
1514 | #define SXFRCTL0 0x3c | |
1515 | #define DFON 0x80 | |
1516 | #define DFPEXP 0x40 | |
1517 | #define BIOSCANCELEN 0x10 | |
1518 | #define SPIOEN 0x08 | |
1519 | ||
1da177e4 LT |
1520 | #define DLCOUNT 0x3c |
1521 | ||
060ae855 DV |
1522 | #define BUSINITID 0x3c |
1523 | ||
1da177e4 LT |
1524 | #define SXFRCTL1 0x3d |
1525 | #define BITBUCKET 0x80 | |
1526 | #define ENSACHK 0x40 | |
1527 | #define ENSPCHK 0x20 | |
1528 | #define STIMESEL 0x18 | |
1529 | #define ENSTIMER 0x04 | |
1530 | #define ACTNEGEN 0x02 | |
1531 | #define STPWEN 0x01 | |
1532 | ||
1533 | #define BUSTARGID 0x3e | |
1534 | ||
1535 | #define SXFRCTL2 0x3e | |
1536 | #define AUTORSTDIS 0x10 | |
1537 | #define CMDDMAEN 0x08 | |
1538 | #define ASU 0x07 | |
1539 | ||
1540 | #define DFFSTAT 0x3f | |
1541 | #define CURRFIFO 0x03 | |
1542 | #define FIFO1FREE 0x20 | |
1543 | #define FIFO0FREE 0x10 | |
1544 | #define CURRFIFO_NONE 0x03 | |
1545 | #define CURRFIFO_1 0x01 | |
1546 | #define CURRFIFO_0 0x00 | |
1547 | ||
1548 | #define SCSISIGO 0x40 | |
1549 | #define CDO 0x80 | |
1550 | #define IOO 0x40 | |
1551 | #define MSGO 0x20 | |
1552 | #define ATNO 0x10 | |
1553 | #define SELO 0x08 | |
1554 | #define BSYO 0x04 | |
1555 | #define REQO 0x02 | |
1556 | #define ACKO 0x01 | |
1557 | ||
060ae855 DV |
1558 | #define MULTARGID 0x40 |
1559 | ||
1da177e4 LT |
1560 | #define SCSISIGI 0x41 |
1561 | #define ATNI 0x10 | |
1562 | #define SELI 0x08 | |
1563 | #define BSYI 0x04 | |
1564 | #define REQI 0x02 | |
1565 | #define ACKI 0x01 | |
1566 | ||
1567 | #define SCSIPHASE 0x42 | |
1568 | #define STATUS_PHASE 0x20 | |
1569 | #define COMMAND_PHASE 0x10 | |
1570 | #define MSG_IN_PHASE 0x08 | |
1571 | #define MSG_OUT_PHASE 0x04 | |
1572 | #define DATA_PHASE_MASK 0x03 | |
1573 | #define DATA_IN_PHASE 0x02 | |
1574 | #define DATA_OUT_PHASE 0x01 | |
1575 | ||
1576 | #define SCSIDAT0_IMG 0x43 | |
1577 | ||
1578 | #define SCSIDAT 0x44 | |
1579 | ||
1580 | #define SCSIBUS 0x46 | |
1581 | ||
1582 | #define TARGIDIN 0x48 | |
1583 | #define CLKOUT 0x80 | |
1584 | #define TARGID 0x0f | |
1585 | ||
1586 | #define SELID 0x49 | |
1587 | #define SELID_MASK 0xf0 | |
1588 | #define ONEBIT 0x08 | |
1589 | ||
1da177e4 LT |
1590 | #define OPTIONMODE 0x4a |
1591 | #define OPTIONMODE_DEFAULTS 0x02 | |
1592 | #define BIOSCANCTL 0x80 | |
1593 | #define AUTOACKEN 0x40 | |
1594 | #define BIASCANCTL 0x20 | |
1595 | #define BUSFREEREV 0x10 | |
1596 | #define ENDGFORMCHK 0x04 | |
1597 | #define AUTO_MSGOUT_DE 0x02 | |
1598 | ||
11668bb6 HR |
1599 | #define SBLKCTL 0x4a |
1600 | #define DIAGLEDEN 0x80 | |
1601 | #define DIAGLEDON 0x40 | |
1602 | #define ENAB40 0x08 | |
1603 | #define ENAB20 0x04 | |
1604 | #define SELWIDE 0x02 | |
1da177e4 | 1605 | |
060ae855 DV |
1606 | #define CLRSINT0 0x4b |
1607 | #define CLRSELDO 0x40 | |
1608 | #define CLRSELDI 0x20 | |
1609 | #define CLRSELINGO 0x10 | |
1610 | #define CLRIOERR 0x08 | |
1611 | #define CLROVERRUN 0x04 | |
1612 | #define CLRSPIORDY 0x02 | |
1613 | #define CLRARBDO 0x01 | |
1614 | ||
11668bb6 HR |
1615 | #define SSTAT0 0x4b |
1616 | #define TARGET 0x80 | |
1617 | #define SELDO 0x40 | |
1618 | #define SELDI 0x20 | |
1619 | #define SELINGO 0x10 | |
1620 | #define IOERR 0x08 | |
1621 | #define OVERRUN 0x04 | |
1622 | #define SPIORDY 0x02 | |
1623 | #define ARBDO 0x01 | |
1624 | ||
1da177e4 LT |
1625 | #define SIMODE0 0x4b |
1626 | #define ENSELDO 0x40 | |
1627 | #define ENSELDI 0x20 | |
1628 | #define ENSELINGO 0x10 | |
1629 | #define ENIOERR 0x08 | |
1630 | #define ENOVERRUN 0x04 | |
1631 | #define ENSPIORDY 0x02 | |
1632 | #define ENARBDO 0x01 | |
1633 | ||
060ae855 DV |
1634 | #define CLRSINT1 0x4c |
1635 | #define CLRSELTIMEO 0x80 | |
1636 | #define CLRATNO 0x40 | |
1637 | #define CLRSCSIRSTI 0x20 | |
1638 | #define CLRBUSFREE 0x08 | |
1639 | #define CLRSCSIPERR 0x04 | |
1640 | #define CLRSTRB2FAST 0x02 | |
1641 | #define CLRREQINIT 0x01 | |
1da177e4 LT |
1642 | |
1643 | #define SSTAT1 0x4c | |
1644 | #define SELTO 0x80 | |
1645 | #define ATNTARG 0x40 | |
1646 | #define SCSIRSTI 0x20 | |
1647 | #define PHASEMIS 0x10 | |
1648 | #define BUSFREE 0x08 | |
1649 | #define SCSIPERR 0x04 | |
1650 | #define STRB2FAST 0x02 | |
1651 | #define REQINIT 0x01 | |
1652 | ||
1653 | #define SSTAT2 0x4d | |
1654 | #define BUSFREETIME 0xc0 | |
1655 | #define NONPACKREQ 0x20 | |
1656 | #define EXP_ACTIVE 0x10 | |
1657 | #define BSYX 0x08 | |
1658 | #define WIDE_RES 0x04 | |
1659 | #define SDONE 0x02 | |
1660 | #define DMADONE 0x01 | |
1661 | #define BUSFREE_DFF1 0xc0 | |
1662 | #define BUSFREE_DFF0 0x80 | |
1663 | #define BUSFREE_LQO 0x40 | |
1664 | ||
11668bb6 HR |
1665 | #define SIMODE2 0x4d |
1666 | #define ENWIDE_RES 0x04 | |
1667 | #define ENSDONE 0x02 | |
1668 | #define ENDMADONE 0x01 | |
1669 | ||
1da177e4 LT |
1670 | #define CLRSINT2 0x4d |
1671 | #define CLRNONPACKREQ 0x20 | |
1672 | #define CLRWIDE_RES 0x04 | |
1673 | #define CLRSDONE 0x02 | |
1674 | #define CLRDMADONE 0x01 | |
1675 | ||
1da177e4 LT |
1676 | #define PERRDIAG 0x4e |
1677 | #define HIZERO 0x80 | |
1678 | #define HIPERR 0x40 | |
1679 | #define PREVPHASE 0x20 | |
1680 | #define PARITYERR 0x10 | |
1681 | #define AIPERR 0x08 | |
1682 | #define CRCERR 0x04 | |
1683 | #define DGFORMERR 0x02 | |
1684 | #define DTERR 0x01 | |
1685 | ||
1686 | #define LQISTATE 0x4e | |
1687 | ||
1688 | #define SOFFCNT 0x4f | |
1689 | ||
1690 | #define LQOSTATE 0x4f | |
1691 | ||
1692 | #define LQISTAT0 0x50 | |
1693 | #define LQIATNQAS 0x20 | |
1694 | #define LQICRCT1 0x10 | |
1695 | #define LQICRCT2 0x08 | |
1696 | #define LQIBADLQT 0x04 | |
1697 | #define LQIATNLQ 0x02 | |
1698 | #define LQIATNCMD 0x01 | |
1699 | ||
d10c2e46 HR |
1700 | #define CLRLQIINT0 0x50 |
1701 | #define CLRLQIATNQAS 0x20 | |
1702 | #define CLRLQICRCT1 0x10 | |
1703 | #define CLRLQICRCT2 0x08 | |
1704 | #define CLRLQIBADLQT 0x04 | |
1705 | #define CLRLQIATNLQ 0x02 | |
1706 | #define CLRLQIATNCMD 0x01 | |
1707 | ||
060ae855 DV |
1708 | #define LQIMODE0 0x50 |
1709 | #define ENLQIATNQASK 0x20 | |
1710 | #define ENLQICRCT1 0x10 | |
1711 | #define ENLQICRCT2 0x08 | |
1712 | #define ENLQIBADLQT 0x04 | |
1713 | #define ENLQIATNLQ 0x02 | |
1714 | #define ENLQIATNCMD 0x01 | |
1715 | ||
1da177e4 LT |
1716 | #define LQIMODE1 0x51 |
1717 | #define ENLQIPHASE_LQ 0x80 | |
1718 | #define ENLQIPHASE_NLQ 0x40 | |
1719 | #define ENLIQABORT 0x20 | |
1720 | #define ENLQICRCI_LQ 0x10 | |
1721 | #define ENLQICRCI_NLQ 0x08 | |
1722 | #define ENLQIBADLQI 0x04 | |
1723 | #define ENLQIOVERI_LQ 0x02 | |
1724 | #define ENLQIOVERI_NLQ 0x01 | |
1725 | ||
1726 | #define LQISTAT1 0x51 | |
1727 | #define LQIPHASE_LQ 0x80 | |
1728 | #define LQIPHASE_NLQ 0x40 | |
1729 | #define LQIABORT 0x20 | |
1730 | #define LQICRCI_LQ 0x10 | |
1731 | #define LQICRCI_NLQ 0x08 | |
1732 | #define LQIBADLQI 0x04 | |
1733 | #define LQIOVERI_LQ 0x02 | |
1734 | #define LQIOVERI_NLQ 0x01 | |
1735 | ||
1736 | #define CLRLQIINT1 0x51 | |
1737 | #define CLRLQIPHASE_LQ 0x80 | |
1738 | #define CLRLQIPHASE_NLQ 0x40 | |
1739 | #define CLRLIQABORT 0x20 | |
1740 | #define CLRLQICRCI_LQ 0x10 | |
1741 | #define CLRLQICRCI_NLQ 0x08 | |
1742 | #define CLRLQIBADLQI 0x04 | |
1743 | #define CLRLQIOVERI_LQ 0x02 | |
1744 | #define CLRLQIOVERI_NLQ 0x01 | |
1745 | ||
1746 | #define LQISTAT2 0x52 | |
1747 | #define PACKETIZED 0x80 | |
1748 | #define LQIPHASE_OUTPKT 0x40 | |
1749 | #define LQIWORKONLQ 0x20 | |
1750 | #define LQIWAITFIFO 0x10 | |
1751 | #define LQISTOPPKT 0x08 | |
1752 | #define LQISTOPLQ 0x04 | |
1753 | #define LQISTOPCMD 0x02 | |
1754 | #define LQIGSAVAIL 0x01 | |
1755 | ||
1756 | #define SSTAT3 0x53 | |
1757 | #define NTRAMPERR 0x02 | |
1758 | #define OSRAMPERR 0x01 | |
1759 | ||
1760 | #define SIMODE3 0x53 | |
1761 | #define ENNTRAMPERR 0x02 | |
1762 | #define ENOSRAMPERR 0x01 | |
1763 | ||
1764 | #define CLRSINT3 0x53 | |
1765 | #define CLRNTRAMPERR 0x02 | |
1766 | #define CLROSRAMPERR 0x01 | |
1767 | ||
1da177e4 LT |
1768 | #define LQOSTAT0 0x54 |
1769 | #define LQOTARGSCBPERR 0x10 | |
1770 | #define LQOSTOPT2 0x08 | |
1771 | #define LQOATNLQ 0x04 | |
1772 | #define LQOATNPKT 0x02 | |
1773 | #define LQOTCRC 0x01 | |
1774 | ||
1775 | #define CLRLQOINT0 0x54 | |
1776 | #define CLRLQOTARGSCBPERR 0x10 | |
1777 | #define CLRLQOSTOPT2 0x08 | |
1778 | #define CLRLQOATNLQ 0x04 | |
1779 | #define CLRLQOATNPKT 0x02 | |
1780 | #define CLRLQOTCRC 0x01 | |
1781 | ||
11668bb6 HR |
1782 | #define LQOMODE0 0x54 |
1783 | #define ENLQOTARGSCBPERR 0x10 | |
1784 | #define ENLQOSTOPT2 0x08 | |
1785 | #define ENLQOATNLQ 0x04 | |
1786 | #define ENLQOATNPKT 0x02 | |
1787 | #define ENLQOTCRC 0x01 | |
1788 | ||
1789 | #define LQOMODE1 0x55 | |
1790 | #define ENLQOINITSCBPERR 0x10 | |
1791 | #define ENLQOSTOPI2 0x08 | |
1792 | #define ENLQOBADQAS 0x04 | |
1793 | #define ENLQOBUSFREE 0x02 | |
1794 | #define ENLQOPHACHGINPKT 0x01 | |
1795 | ||
1da177e4 LT |
1796 | #define LQOSTAT1 0x55 |
1797 | #define LQOINITSCBPERR 0x10 | |
1798 | #define LQOSTOPI2 0x08 | |
1799 | #define LQOBADQAS 0x04 | |
1800 | #define LQOBUSFREE 0x02 | |
1801 | #define LQOPHACHGINPKT 0x01 | |
1802 | ||
1803 | #define CLRLQOINT1 0x55 | |
1804 | #define CLRLQOINITSCBPERR 0x10 | |
1805 | #define CLRLQOSTOPI2 0x08 | |
1806 | #define CLRLQOBADQAS 0x04 | |
1807 | #define CLRLQOBUSFREE 0x02 | |
1808 | #define CLRLQOPHACHGINPKT 0x01 | |
1809 | ||
1da177e4 LT |
1810 | #define LQOSTAT2 0x56 |
1811 | #define LQOPKT 0xe0 | |
1812 | #define LQOWAITFIFO 0x10 | |
1813 | #define LQOPHACHGOUTPKT 0x02 | |
1814 | #define LQOSTOP0 0x01 | |
1815 | ||
1816 | #define OS_SPACE_CNT 0x56 | |
1817 | ||
1818 | #define SIMODE1 0x57 | |
1819 | #define ENSELTIMO 0x80 | |
1820 | #define ENATNTARG 0x40 | |
1821 | #define ENSCSIRST 0x20 | |
1822 | #define ENPHASEMIS 0x10 | |
1823 | #define ENBUSFREE 0x08 | |
1824 | #define ENSCSIPERR 0x04 | |
1825 | #define ENSTRB2FAST 0x02 | |
1826 | #define ENREQINIT 0x01 | |
1827 | ||
1828 | #define GSFIFO 0x58 | |
1829 | ||
1830 | #define DFFSXFRCTL 0x5a | |
1831 | #define DFFBITBUCKET 0x08 | |
1832 | #define CLRSHCNT 0x04 | |
1833 | #define CLRCHN 0x02 | |
1834 | #define RSTCHN 0x01 | |
1835 | ||
1836 | #define LQOSCSCTL 0x5a | |
1837 | #define LQOH2A_VERSION 0x80 | |
d10c2e46 HR |
1838 | #define LQOBUSETDLY 0x40 |
1839 | #define LQONOHOLDLACK 0x02 | |
1da177e4 LT |
1840 | #define LQONOCHKOVER 0x01 |
1841 | ||
1842 | #define NEXTSCB 0x5a | |
1843 | ||
1844 | #define CLRSEQINTSRC 0x5b | |
1845 | #define CLRCTXTDONE 0x40 | |
1846 | #define CLRSAVEPTRS 0x20 | |
1847 | #define CLRCFG4DATA 0x10 | |
1848 | #define CLRCFG4ISTAT 0x08 | |
1849 | #define CLRCFG4TSTAT 0x04 | |
1850 | #define CLRCFG4ICMD 0x02 | |
1851 | #define CLRCFG4TCMD 0x01 | |
1852 | ||
1853 | #define SEQINTSRC 0x5b | |
1854 | #define CTXTDONE 0x40 | |
1855 | #define SAVEPTRS 0x20 | |
1856 | #define CFG4DATA 0x10 | |
1857 | #define CFG4ISTAT 0x08 | |
1858 | #define CFG4TSTAT 0x04 | |
1859 | #define CFG4ICMD 0x02 | |
1860 | #define CFG4TCMD 0x01 | |
1861 | ||
060ae855 DV |
1862 | #define CURRSCB 0x5c |
1863 | ||
1da177e4 LT |
1864 | #define SEQIMODE 0x5c |
1865 | #define ENCTXTDONE 0x40 | |
1866 | #define ENSAVEPTRS 0x20 | |
1867 | #define ENCFG4DATA 0x10 | |
1868 | #define ENCFG4ISTAT 0x08 | |
1869 | #define ENCFG4TSTAT 0x04 | |
1870 | #define ENCFG4ICMD 0x02 | |
1871 | #define ENCFG4TCMD 0x01 | |
1872 | ||
1873 | #define MDFFSTAT 0x5d | |
1874 | #define SHCNTNEGATIVE 0x40 | |
1875 | #define SHCNTMINUS1 0x20 | |
1876 | #define LASTSDONE 0x10 | |
1877 | #define SHVALID 0x08 | |
1878 | #define DLZERO 0x04 | |
1879 | #define DATAINFIFO 0x02 | |
1880 | #define FIFOFREE 0x01 | |
1881 | ||
1882 | #define CRCCONTROL 0x5d | |
1883 | #define CRCVALCHKEN 0x40 | |
1884 | ||
1885 | #define DFFTAG 0x5e | |
1886 | ||
060ae855 DV |
1887 | #define LASTSCB 0x5e |
1888 | ||
1da177e4 LT |
1889 | #define SCSITEST 0x5e |
1890 | #define CNTRTEST 0x08 | |
1891 | #define SEL_TXPLL_DEBUG 0x04 | |
1892 | ||
1893 | #define IOPDNCTL 0x5f | |
1894 | #define DISABLE_OE 0x80 | |
1895 | #define PDN_IDIST 0x04 | |
1896 | #define PDN_DIFFSENSE 0x01 | |
1897 | ||
1898 | #define SHADDR 0x60 | |
1899 | ||
1900 | #define NEGOADDR 0x60 | |
1901 | ||
060ae855 | 1902 | #define DGRPCRCI 0x60 |
1da177e4 | 1903 | |
060ae855 | 1904 | #define NEGPERIOD 0x61 |
1da177e4 | 1905 | |
d10c2e46 HR |
1906 | #define PACKCRCI 0x62 |
1907 | ||
060ae855 DV |
1908 | #define NEGOFFSET 0x62 |
1909 | ||
1da177e4 LT |
1910 | #define NEGPPROPTS 0x63 |
1911 | #define PPROPT_PACE 0x08 | |
1912 | #define PPROPT_QAS 0x04 | |
1913 | #define PPROPT_DT 0x02 | |
1914 | #define PPROPT_IUT 0x01 | |
1915 | ||
1916 | #define NEGCONOPTS 0x64 | |
1917 | #define ENSNAPSHOT 0x40 | |
1918 | #define RTI_WRTDIS 0x20 | |
1919 | #define RTI_OVRDTRN 0x10 | |
1920 | #define ENSLOWCRC 0x08 | |
1921 | #define ENAUTOATNI 0x04 | |
1922 | #define ENAUTOATNO 0x02 | |
1923 | #define WIDEXFER 0x01 | |
1924 | ||
1925 | #define ANNEXCOL 0x65 | |
1926 | ||
11668bb6 HR |
1927 | #define ANNEXDAT 0x66 |
1928 | ||
1da177e4 | 1929 | #define SCSCHKN 0x66 |
d10c2e46 | 1930 | #define BIDICHKDIS 0x80 |
1da177e4 LT |
1931 | #define STSELSKIDDIS 0x40 |
1932 | #define CURRFIFODEF 0x20 | |
1933 | #define WIDERESEN 0x10 | |
1934 | #define SDONEMSKDIS 0x08 | |
1935 | #define DFFACTCLR 0x04 | |
1936 | #define SHVALIDSTDIS 0x02 | |
1937 | #define LSTSGCLRDIS 0x01 | |
1938 | ||
1da177e4 LT |
1939 | #define IOWNID 0x67 |
1940 | ||
1941 | #define PLL960CTL0 0x68 | |
1942 | ||
1943 | #define SHCNT 0x68 | |
1944 | ||
1945 | #define TOWNID 0x69 | |
1946 | ||
1947 | #define PLL960CTL1 0x69 | |
1948 | ||
1949 | #define PLL960CNT0 0x6a | |
1950 | ||
1951 | #define XSIG 0x6a | |
1952 | ||
1953 | #define SELOID 0x6b | |
1954 | ||
1955 | #define PLL400CTL0 0x6c | |
1956 | #define PLL_VCOSEL 0x80 | |
1957 | #define PLL_PWDN 0x40 | |
1958 | #define PLL_NS 0x30 | |
1959 | #define PLL_ENLUD 0x08 | |
1960 | #define PLL_ENLPF 0x04 | |
1961 | #define PLL_DLPF 0x02 | |
1962 | #define PLL_ENFBM 0x01 | |
1963 | ||
060ae855 DV |
1964 | #define FAIRNESS 0x6c |
1965 | ||
1da177e4 LT |
1966 | #define PLL400CTL1 0x6d |
1967 | #define PLL_CNTEN 0x80 | |
1968 | #define PLL_CNTCLR 0x40 | |
1969 | #define PLL_RST 0x01 | |
1970 | ||
1da177e4 LT |
1971 | #define UNFAIRNESS 0x6e |
1972 | ||
11668bb6 HR |
1973 | #define PLL400CNT0 0x6e |
1974 | ||
1da177e4 LT |
1975 | #define HADDR 0x70 |
1976 | ||
1977 | #define PLLDELAY 0x70 | |
1978 | #define SPLIT_DROP_REQ 0x80 | |
1979 | ||
060ae855 | 1980 | #define HODMAADR 0x70 |
1da177e4 LT |
1981 | |
1982 | #define HODMACNT 0x78 | |
1983 | ||
060ae855 | 1984 | #define HCNT 0x78 |
1da177e4 | 1985 | |
060ae855 | 1986 | #define HODMAEN 0x7a |
1da177e4 | 1987 | |
d10c2e46 | 1988 | #define SCBHADDR 0x7c |
1da177e4 | 1989 | |
060ae855 | 1990 | #define SGHADDR 0x7c |
11668bb6 | 1991 | |
d10c2e46 HR |
1992 | #define SCBHCNT 0x84 |
1993 | ||
060ae855 DV |
1994 | #define SGHCNT 0x84 |
1995 | ||
1da177e4 LT |
1996 | #define DFF_THRSH 0x88 |
1997 | #define WR_DFTHRSH 0x70 | |
1998 | #define RD_DFTHRSH 0x07 | |
1999 | #define WR_DFTHRSH_MAX 0x70 | |
2000 | #define WR_DFTHRSH_90 0x60 | |
2001 | #define WR_DFTHRSH_85 0x50 | |
2002 | #define WR_DFTHRSH_75 0x40 | |
2003 | #define WR_DFTHRSH_63 0x30 | |
2004 | #define WR_DFTHRSH_50 0x20 | |
2005 | #define WR_DFTHRSH_25 0x10 | |
2006 | #define RD_DFTHRSH_MAX 0x07 | |
2007 | #define RD_DFTHRSH_90 0x06 | |
2008 | #define RD_DFTHRSH_85 0x05 | |
2009 | #define RD_DFTHRSH_75 0x04 | |
2010 | #define RD_DFTHRSH_63 0x03 | |
2011 | #define RD_DFTHRSH_50 0x02 | |
2012 | #define RD_DFTHRSH_25 0x01 | |
1da177e4 | 2013 | #define RD_DFTHRSH_MIN 0x00 |
11668bb6 | 2014 | #define WR_DFTHRSH_MIN 0x00 |
1da177e4 LT |
2015 | |
2016 | #define ROMADDR 0x8a | |
2017 | ||
2018 | #define ROMCNTRL 0x8d | |
2019 | #define ROMOP 0xe0 | |
2020 | #define ROMSPD 0x18 | |
2021 | #define REPEAT 0x02 | |
2022 | #define RDY 0x01 | |
2023 | ||
2024 | #define ROMDATA 0x8e | |
2025 | ||
2026 | #define CMCRXMSG0 0x90 | |
2027 | ||
2028 | #define ROENABLE 0x90 | |
2029 | #define MSIROEN 0x20 | |
2030 | #define OVLYROEN 0x10 | |
2031 | #define CMCROEN 0x08 | |
2032 | #define SGROEN 0x04 | |
2033 | #define DCH1ROEN 0x02 | |
2034 | #define DCH0ROEN 0x01 | |
2035 | ||
060ae855 | 2036 | #define OVLYRXMSG0 0x90 |
1da177e4 | 2037 | |
060ae855 | 2038 | #define DCHRXMSG0 0x90 |
1da177e4 | 2039 | |
060ae855 | 2040 | #define OVLYRXMSG1 0x91 |
1da177e4 LT |
2041 | |
2042 | #define NSENABLE 0x91 | |
2043 | #define MSINSEN 0x20 | |
2044 | #define OVLYNSEN 0x10 | |
2045 | #define CMCNSEN 0x08 | |
2046 | #define SGNSEN 0x04 | |
2047 | #define DCH1NSEN 0x02 | |
2048 | #define DCH0NSEN 0x01 | |
2049 | ||
060ae855 DV |
2050 | #define CMCRXMSG1 0x91 |
2051 | ||
2052 | #define DCHRXMSG1 0x91 | |
2053 | ||
11668bb6 | 2054 | #define DCHRXMSG2 0x92 |
1da177e4 LT |
2055 | |
2056 | #define CMCRXMSG2 0x92 | |
2057 | ||
2058 | #define OST 0x92 | |
2059 | ||
11668bb6 HR |
2060 | #define OVLYRXMSG2 0x92 |
2061 | ||
1da177e4 LT |
2062 | #define DCHRXMSG3 0x93 |
2063 | ||
11668bb6 HR |
2064 | #define OVLYRXMSG3 0x93 |
2065 | ||
1da177e4 LT |
2066 | #define CMCRXMSG3 0x93 |
2067 | ||
2068 | #define PCIXCTL 0x93 | |
2069 | #define SERRPULSE 0x80 | |
2070 | #define UNEXPSCIEN 0x20 | |
2071 | #define SPLTSMADIS 0x10 | |
2072 | #define SPLTSTADIS 0x08 | |
2073 | #define SRSPDPEEN 0x04 | |
2074 | #define TSCSERREN 0x02 | |
2075 | #define CMPABCDIS 0x01 | |
2076 | ||
1da177e4 LT |
2077 | #define OVLYSEQBCNT 0x94 |
2078 | ||
1da177e4 LT |
2079 | #define DCHSEQBCNT 0x94 |
2080 | ||
060ae855 DV |
2081 | #define CMCSEQBCNT 0x94 |
2082 | ||
2083 | #define CMCSPLTSTAT0 0x96 | |
2084 | ||
1da177e4 LT |
2085 | #define DCHSPLTSTAT0 0x96 |
2086 | ||
11668bb6 | 2087 | #define OVLYSPLTSTAT0 0x96 |
1da177e4 | 2088 | |
060ae855 | 2089 | #define CMCSPLTSTAT1 0x97 |
1da177e4 LT |
2090 | |
2091 | #define OVLYSPLTSTAT1 0x97 | |
2092 | ||
11668bb6 HR |
2093 | #define DCHSPLTSTAT1 0x97 |
2094 | ||
1da177e4 LT |
2095 | #define SGRXMSG0 0x98 |
2096 | #define CDNUM 0xf8 | |
2097 | #define CFNUM 0x07 | |
2098 | ||
2099 | #define SLVSPLTOUTADR0 0x98 | |
2100 | #define LOWER_ADDR 0x7f | |
2101 | ||
2102 | #define SGRXMSG1 0x99 | |
2103 | #define CBNUM 0xff | |
2104 | ||
2105 | #define SLVSPLTOUTADR1 0x99 | |
2106 | #define REQ_DNUM 0xf8 | |
2107 | #define REQ_FNUM 0x07 | |
2108 | ||
2109 | #define SGRXMSG2 0x9a | |
2110 | #define MINDEX 0xff | |
2111 | ||
2112 | #define SLVSPLTOUTADR2 0x9a | |
2113 | #define REQ_BNUM 0xff | |
2114 | ||
2115 | #define SGRXMSG3 0x9b | |
2116 | #define MCLASS 0x0f | |
2117 | ||
2118 | #define SLVSPLTOUTADR3 0x9b | |
2119 | #define TAG_NUM 0x1f | |
2120 | #define RLXORD 0x10 | |
2121 | ||
060ae855 DV |
2122 | #define SGSEQBCNT 0x9c |
2123 | ||
1da177e4 LT |
2124 | #define SLVSPLTOUTATTR0 0x9c |
2125 | #define LOWER_BCNT 0xff | |
2126 | ||
2127 | #define SLVSPLTOUTATTR1 0x9d | |
2128 | #define CMPLT_DNUM 0xf8 | |
2129 | #define CMPLT_FNUM 0x07 | |
2130 | ||
060ae855 DV |
2131 | #define SLVSPLTOUTATTR2 0x9e |
2132 | #define CMPLT_BNUM 0xff | |
2133 | ||
1da177e4 LT |
2134 | #define SGSPLTSTAT0 0x9e |
2135 | #define STAETERM 0x80 | |
2136 | #define SCBCERR 0x40 | |
2137 | #define SCADERR 0x20 | |
2138 | #define SCDATBUCKET 0x10 | |
2139 | #define CNTNOTCMPLT 0x08 | |
2140 | #define RXOVRUN 0x04 | |
2141 | #define RXSCEMSG 0x02 | |
2142 | #define RXSPLTRSP 0x01 | |
2143 | ||
11668bb6 HR |
2144 | #define SGSPLTSTAT1 0x9f |
2145 | #define RXDATABUCKET 0x01 | |
2146 | ||
1da177e4 LT |
2147 | #define SFUNCT 0x9f |
2148 | #define TEST_GROUP 0xf0 | |
2149 | #define TEST_NUM 0x0f | |
2150 | ||
1da177e4 LT |
2151 | #define DF0PCISTAT 0xa0 |
2152 | ||
2153 | #define REG0 0xa0 | |
2154 | ||
2155 | #define DF1PCISTAT 0xa1 | |
2156 | ||
2157 | #define SGPCISTAT 0xa2 | |
2158 | ||
2159 | #define REG1 0xa2 | |
2160 | ||
2161 | #define CMCPCISTAT 0xa3 | |
2162 | ||
2163 | #define OVLYPCISTAT 0xa4 | |
2164 | #define SCAAPERR 0x08 | |
2165 | #define RDPERR 0x04 | |
2166 | ||
2167 | #define REG_ISR 0xa4 | |
2168 | ||
2169 | #define SG_STATE 0xa6 | |
2170 | #define FETCH_INPROG 0x04 | |
2171 | #define LOADING_NEEDED 0x02 | |
2172 | #define SEGS_AVAIL 0x01 | |
2173 | ||
2174 | #define MSIPCISTAT 0xa6 | |
2175 | #define RMA 0x20 | |
2176 | #define RTA 0x10 | |
2177 | #define CLRPENDMSI 0x08 | |
2178 | #define DPR 0x01 | |
2179 | ||
2180 | #define TARGPCISTAT 0xa7 | |
2181 | #define DPE 0x80 | |
2182 | #define SSE 0x40 | |
2183 | #define STA 0x08 | |
2184 | #define TWATERR 0x02 | |
2185 | ||
2186 | #define DATA_COUNT_ODD 0xa7 | |
2187 | ||
2188 | #define SCBPTR 0xa8 | |
2189 | ||
2190 | #define CCSCBACNT 0xab | |
2191 | ||
2192 | #define SCBAUTOPTR 0xab | |
2193 | #define AUSCBPTR_EN 0x80 | |
2194 | #define SCBPTR_ADDR 0x38 | |
2195 | #define SCBPTR_OFF 0x07 | |
2196 | ||
2197 | #define CCSGADDR 0xac | |
2198 | ||
d10c2e46 HR |
2199 | #define CCSCBADR_BK 0xac |
2200 | ||
060ae855 DV |
2201 | #define CCSCBADDR 0xac |
2202 | ||
1da177e4 LT |
2203 | #define CMC_RAMBIST 0xad |
2204 | #define SG_ELEMENT_SIZE 0x80 | |
2205 | #define SCBRAMBIST_FAIL 0x40 | |
2206 | #define SG_BIST_FAIL 0x20 | |
2207 | #define SG_BIST_EN 0x10 | |
2208 | #define CMC_BUFFER_BIST_FAIL 0x02 | |
2209 | #define CMC_BUFFER_BIST_EN 0x01 | |
2210 | ||
1da177e4 LT |
2211 | #define CCSCBCTL 0xad |
2212 | #define CCSCBDONE 0x80 | |
2213 | #define ARRDONE 0x40 | |
2214 | #define CCARREN 0x10 | |
2215 | #define CCSCBEN 0x08 | |
2216 | #define CCSCBDIR 0x04 | |
2217 | #define CCSCBRESET 0x01 | |
2218 | ||
11668bb6 HR |
2219 | #define CCSGCTL 0xad |
2220 | #define CCSGEN 0x0c | |
2221 | #define CCSGDONE 0x80 | |
2222 | #define SG_CACHE_AVAIL 0x10 | |
2223 | #define CCSGENACK 0x08 | |
2224 | #define SG_FETCH_REQ 0x02 | |
2225 | #define CCSGRESET 0x01 | |
2226 | ||
1da177e4 LT |
2227 | #define CCSGRAM 0xb0 |
2228 | ||
2229 | #define FLEXADR 0xb0 | |
2230 | ||
2231 | #define CCSCBRAM 0xb0 | |
2232 | ||
2233 | #define FLEXCNT 0xb3 | |
2234 | ||
2235 | #define FLEXDMASTAT 0xb5 | |
2236 | #define FLEXDMAERR 0x02 | |
2237 | #define FLEXDMADONE 0x01 | |
2238 | ||
2239 | #define FLEXDATA 0xb6 | |
2240 | ||
2241 | #define BRDDAT 0xb8 | |
2242 | ||
2243 | #define BRDCTL 0xb9 | |
2244 | #define FLXARBACK 0x80 | |
2245 | #define FLXARBREQ 0x40 | |
2246 | #define BRDADDR 0x38 | |
2247 | #define BRDEN 0x04 | |
2248 | #define BRDRW 0x02 | |
2249 | #define BRDSTB 0x01 | |
2250 | ||
2251 | #define SEEADR 0xba | |
2252 | ||
2253 | #define SEEDAT 0xbc | |
2254 | ||
2255 | #define SEECTL 0xbe | |
1da177e4 | 2256 | #define SEEOP_WALL 0x40 |
11668bb6 | 2257 | #define SEEOP_EWEN 0x40 |
060ae855 | 2258 | #define SEEOP_EWDS 0x40 |
1da177e4 LT |
2259 | #define SEEOPCODE 0x70 |
2260 | #define SEERST 0x02 | |
2261 | #define SEESTART 0x01 | |
2262 | #define SEEOP_ERASE 0x70 | |
2263 | #define SEEOP_READ 0x60 | |
2264 | #define SEEOP_WRITE 0x50 | |
2265 | #define SEEOP_ERAL 0x40 | |
2266 | ||
2267 | #define SEESTAT 0xbe | |
2268 | #define INIT_DONE 0x80 | |
2269 | #define LDALTID_L 0x08 | |
2270 | #define SEEARBACK 0x04 | |
2271 | #define SEEBUSY 0x02 | |
2272 | ||
2273 | #define SCBCNT 0xbf | |
2274 | ||
060ae855 DV |
2275 | #define DFWADDR 0xc0 |
2276 | ||
1da177e4 LT |
2277 | #define DSPFLTRCTL 0xc0 |
2278 | #define FLTRDISABLE 0x20 | |
2279 | #define EDGESENSE 0x10 | |
2280 | #define DSPFCNTSEL 0x0f | |
2281 | ||
2282 | #define DSPDATACTL 0xc1 | |
2283 | #define BYPASSENAB 0x80 | |
2284 | #define DESQDIS 0x10 | |
2285 | #define RCVROFFSTDIS 0x04 | |
2286 | #define XMITOFFSTDIS 0x02 | |
2287 | ||
060ae855 DV |
2288 | #define DFRADDR 0xc2 |
2289 | ||
1da177e4 LT |
2290 | #define DSPREQCTL 0xc2 |
2291 | #define MANREQCTL 0xc0 | |
2292 | #define MANREQDLY 0x3f | |
2293 | ||
2294 | #define DSPACKCTL 0xc3 | |
2295 | #define MANACKCTL 0xc0 | |
2296 | #define MANACKDLY 0x3f | |
2297 | ||
2298 | #define DFDAT 0xc4 | |
2299 | ||
2300 | #define DSPSELECT 0xc4 | |
2301 | #define AUTOINCEN 0x80 | |
2302 | #define DSPSEL 0x1f | |
2303 | ||
2304 | #define WRTBIASCTL 0xc5 | |
2305 | #define AUTOXBCDIS 0x80 | |
2306 | #define XMITMANVAL 0x3f | |
2307 | ||
2308 | #define RCVRBIOSCTL 0xc6 | |
2309 | #define AUTORBCDIS 0x80 | |
2310 | #define RCVRMANVAL 0x3f | |
2311 | ||
2312 | #define WRTBIASCALC 0xc7 | |
2313 | ||
d10c2e46 | 2314 | #define RCVRBIASCALC 0xc8 |
1da177e4 | 2315 | |
060ae855 | 2316 | #define DFPTRS 0xc8 |
11668bb6 | 2317 | |
d10c2e46 HR |
2318 | #define SKEWCALC 0xc9 |
2319 | ||
060ae855 DV |
2320 | #define DFBKPTR 0xc9 |
2321 | ||
1da177e4 LT |
2322 | #define DFDBCTL 0xcb |
2323 | #define DFF_CIO_WR_RDY 0x20 | |
2324 | #define DFF_CIO_RD_RDY 0x10 | |
2325 | #define DFF_DIR_ERR 0x08 | |
2326 | #define DFF_RAMBIST_FAIL 0x04 | |
2327 | #define DFF_RAMBIST_DONE 0x02 | |
2328 | #define DFF_RAMBIST_EN 0x01 | |
2329 | ||
2330 | #define DFSCNT 0xcc | |
2331 | ||
2332 | #define DFBCNT 0xce | |
2333 | ||
2334 | #define OVLYADDR 0xd4 | |
2335 | ||
2336 | #define SEQCTL0 0xd6 | |
2337 | #define PERRORDIS 0x80 | |
2338 | #define PAUSEDIS 0x40 | |
2339 | #define FAILDIS 0x20 | |
2340 | #define FASTMODE 0x10 | |
2341 | #define BRKADRINTEN 0x08 | |
2342 | #define STEP 0x04 | |
2343 | #define SEQRESET 0x02 | |
2344 | #define LOADRAM 0x01 | |
2345 | ||
2346 | #define SEQCTL1 0xd7 | |
2347 | #define OVRLAY_DATA_CHK 0x08 | |
2348 | #define RAMBIST_DONE 0x04 | |
2349 | #define RAMBIST_FAIL 0x02 | |
2350 | #define RAMBIST_EN 0x01 | |
2351 | ||
2352 | #define FLAGS 0xd8 | |
2353 | #define ZERO 0x02 | |
2354 | #define CARRY 0x01 | |
2355 | ||
2356 | #define SEQINTCTL 0xd9 | |
2357 | #define INTVEC1DSL 0x80 | |
2358 | #define INT1_CONTEXT 0x20 | |
2359 | #define SCS_SEQ_INT1M1 0x10 | |
2360 | #define SCS_SEQ_INT1M0 0x08 | |
2361 | #define INTMASK2 0x04 | |
2362 | #define INTMASK1 0x02 | |
2363 | #define IRET 0x01 | |
2364 | ||
2365 | #define SEQRAM 0xda | |
2366 | ||
2367 | #define PRGMCNT 0xde | |
2368 | ||
2369 | #define ACCUM 0xe0 | |
2370 | ||
2371 | #define SINDEX 0xe2 | |
2372 | ||
2373 | #define DINDEX 0xe4 | |
2374 | ||
11668bb6 HR |
2375 | #define BRKADDR0 0xe6 |
2376 | ||
1da177e4 LT |
2377 | #define BRKADDR1 0xe6 |
2378 | #define BRKDIS 0x80 | |
2379 | ||
1da177e4 LT |
2380 | #define ALLONES 0xe8 |
2381 | ||
2382 | #define ALLZEROS 0xea | |
2383 | ||
2384 | #define NONE 0xea | |
2385 | ||
2386 | #define SINDIR 0xec | |
2387 | ||
2388 | #define DINDIR 0xed | |
2389 | ||
2390 | #define FUNCTION1 0xf0 | |
2391 | ||
2392 | #define STACK 0xf2 | |
2393 | ||
1da177e4 LT |
2394 | #define INTVEC1_ADDR 0xf4 |
2395 | ||
11668bb6 | 2396 | #define CURADDR 0xf4 |
1da177e4 LT |
2397 | |
2398 | #define LASTADDR 0xf6 | |
2399 | ||
11668bb6 HR |
2400 | #define INTVEC2_ADDR 0xf6 |
2401 | ||
1da177e4 LT |
2402 | #define LONGJMP_ADDR 0xf8 |
2403 | ||
2404 | #define ACCUM_SAVE 0xfa | |
2405 | ||
060ae855 DV |
2406 | #define WAITING_SCB_TAILS 0x100 |
2407 | ||
1da177e4 LT |
2408 | #define AHD_PCI_CONFIG_BASE 0x100 |
2409 | ||
2410 | #define SRAM_BASE 0x100 | |
2411 | ||
2412 | #define WAITING_TID_HEAD 0x120 | |
2413 | ||
2414 | #define WAITING_TID_TAIL 0x122 | |
2415 | ||
2416 | #define NEXT_QUEUED_SCB_ADDR 0x124 | |
2417 | ||
2418 | #define COMPLETE_SCB_HEAD 0x128 | |
2419 | ||
2420 | #define COMPLETE_SCB_DMAINPROG_HEAD 0x12a | |
2421 | ||
2422 | #define COMPLETE_DMA_SCB_HEAD 0x12c | |
2423 | ||
11668bb6 HR |
2424 | #define COMPLETE_DMA_SCB_TAIL 0x12e |
2425 | ||
2426 | #define COMPLETE_ON_QFREEZE_HEAD 0x130 | |
2427 | ||
2428 | #define QFREEZE_COUNT 0x132 | |
1da177e4 | 2429 | |
11668bb6 | 2430 | #define KERNEL_QFREEZE_COUNT 0x134 |
1da177e4 | 2431 | |
11668bb6 | 2432 | #define SAVED_MODE 0x136 |
1da177e4 | 2433 | |
11668bb6 HR |
2434 | #define MSG_OUT 0x137 |
2435 | ||
2436 | #define DMAPARAMS 0x138 | |
1da177e4 LT |
2437 | #define PRELOADEN 0x80 |
2438 | #define WIDEODD 0x40 | |
2439 | #define SCSIEN 0x20 | |
d10c2e46 | 2440 | #define SDMAEN 0x10 |
060ae855 | 2441 | #define SDMAENACK 0x10 |
1da177e4 | 2442 | #define HDMAEN 0x08 |
11668bb6 | 2443 | #define HDMAENACK 0x08 |
1da177e4 LT |
2444 | #define DIRECTION 0x04 |
2445 | #define FIFOFLUSH 0x02 | |
2446 | #define FIFORESET 0x01 | |
2447 | ||
11668bb6 | 2448 | #define SEQ_FLAGS 0x139 |
1da177e4 LT |
2449 | #define NOT_IDENTIFIED 0x80 |
2450 | #define NO_CDB_SENT 0x40 | |
2451 | #define TARGET_CMD_IS_TAGGED 0x40 | |
2452 | #define DPHASE 0x20 | |
2453 | #define TARG_CMD_PENDING 0x10 | |
2454 | #define CMDPHASE_PENDING 0x08 | |
2455 | #define DPHASE_PENDING 0x04 | |
2456 | #define SPHASE_PENDING 0x02 | |
2457 | #define NO_DISCONNECT 0x01 | |
2458 | ||
11668bb6 | 2459 | #define SAVED_SCSIID 0x13a |
1da177e4 | 2460 | |
11668bb6 | 2461 | #define SAVED_LUN 0x13b |
1da177e4 | 2462 | |
11668bb6 | 2463 | #define LASTPHASE 0x13c |
1da177e4 LT |
2464 | #define PHASE_MASK 0xe0 |
2465 | #define CDI 0x80 | |
2466 | #define IOI 0x40 | |
2467 | #define MSGI 0x20 | |
2468 | #define P_BUSFREE 0x01 | |
2469 | #define P_MESGIN 0xe0 | |
2470 | #define P_STATUS 0xc0 | |
2471 | #define P_MESGOUT 0xa0 | |
2472 | #define P_COMMAND 0x80 | |
2473 | #define P_DATAIN_DT 0x60 | |
2474 | #define P_DATAIN 0x40 | |
2475 | #define P_DATAOUT_DT 0x20 | |
2476 | #define P_DATAOUT 0x00 | |
2477 | ||
11668bb6 | 2478 | #define QOUTFIFO_ENTRY_VALID_TAG 0x13d |
1da177e4 | 2479 | |
11668bb6 | 2480 | #define KERNEL_TQINPOS 0x13e |
1da177e4 | 2481 | |
11668bb6 | 2482 | #define TQINPOS 0x13f |
1da177e4 | 2483 | |
11668bb6 | 2484 | #define SHARED_DATA_ADDR 0x140 |
1da177e4 | 2485 | |
11668bb6 | 2486 | #define QOUTFIFO_NEXT_ADDR 0x144 |
1da177e4 | 2487 | |
11668bb6 HR |
2488 | #define ARG_1 0x148 |
2489 | #define RETURN_1 0x148 | |
1da177e4 LT |
2490 | #define SEND_MSG 0x80 |
2491 | #define SEND_SENSE 0x40 | |
2492 | #define SEND_REJ 0x20 | |
2493 | #define MSGOUT_PHASEMIS 0x10 | |
2494 | #define EXIT_MSG_LOOP 0x08 | |
2495 | #define CONT_MSG_LOOP_WRITE 0x04 | |
2496 | #define CONT_MSG_LOOP_READ 0x03 | |
2497 | #define CONT_MSG_LOOP_TARG 0x02 | |
2498 | ||
11668bb6 HR |
2499 | #define ARG_2 0x149 |
2500 | #define RETURN_2 0x149 | |
1da177e4 | 2501 | |
11668bb6 | 2502 | #define LAST_MSG 0x14a |
1da177e4 | 2503 | |
11668bb6 | 2504 | #define SCSISEQ_TEMPLATE 0x14b |
1da177e4 LT |
2505 | #define MANUALCTL 0x40 |
2506 | #define ENSELI 0x20 | |
2507 | #define ENRSELI 0x10 | |
2508 | #define MANUALP 0x0c | |
2509 | #define ENAUTOATNP 0x02 | |
2510 | #define ALTSTIM 0x01 | |
2511 | ||
11668bb6 | 2512 | #define INITIATOR_TAG 0x14c |
1da177e4 | 2513 | |
11668bb6 | 2514 | #define SEQ_FLAGS2 0x14d |
1da177e4 LT |
2515 | #define SELECTOUT_QFROZEN 0x04 |
2516 | #define TARGET_MSG_PENDING 0x02 | |
53467e63 | 2517 | #define PENDING_MK_MESSAGE 0x01 |
1da177e4 | 2518 | |
11668bb6 | 2519 | #define ALLOCFIFO_SCBPTR 0x14e |
1da177e4 | 2520 | |
11668bb6 | 2521 | #define INT_COALESCING_TIMER 0x150 |
1da177e4 | 2522 | |
11668bb6 | 2523 | #define INT_COALESCING_MAXCMDS 0x152 |
1da177e4 | 2524 | |
11668bb6 | 2525 | #define INT_COALESCING_MINCMDS 0x153 |
1da177e4 | 2526 | |
11668bb6 | 2527 | #define CMDS_PENDING 0x154 |
1da177e4 | 2528 | |
11668bb6 | 2529 | #define INT_COALESCING_CMDCOUNT 0x156 |
1da177e4 | 2530 | |
11668bb6 | 2531 | #define LOCAL_HS_MAILBOX 0x157 |
1da177e4 | 2532 | |
11668bb6 | 2533 | #define CMDSIZE_TABLE 0x158 |
1da177e4 | 2534 | |
53467e63 HR |
2535 | #define MK_MESSAGE_SCB 0x160 |
2536 | ||
2537 | #define MK_MESSAGE_SCSIID 0x162 | |
2538 | ||
060ae855 DV |
2539 | #define SCB_BASE 0x180 |
2540 | ||
1da177e4 LT |
2541 | #define SCB_RESIDUAL_DATACNT 0x180 |
2542 | #define SCB_CDB_STORE 0x180 | |
2543 | #define SCB_HOST_CDB_PTR 0x180 | |
2544 | ||
2545 | #define SCB_RESIDUAL_SGPTR 0x184 | |
2546 | #define SG_ADDR_MASK 0xf8 | |
2547 | #define SG_OVERRUN_RESID 0x02 | |
2548 | ||
2549 | #define SCB_SCSI_STATUS 0x188 | |
2550 | #define SCB_HOST_CDB_LEN 0x188 | |
2551 | ||
2552 | #define SCB_TARGET_PHASES 0x189 | |
2553 | ||
2554 | #define SCB_TARGET_DATA_DIR 0x18a | |
2555 | ||
2556 | #define SCB_TARGET_ITAG 0x18b | |
2557 | ||
2558 | #define SCB_SENSE_BUSADDR 0x18c | |
2559 | #define SCB_NEXT_COMPLETE 0x18c | |
2560 | ||
2561 | #define SCB_TAG 0x190 | |
2562 | #define SCB_FIFO_USE_COUNT 0x190 | |
2563 | ||
2564 | #define SCB_CONTROL 0x192 | |
2565 | #define TARGET_SCB 0x80 | |
2566 | #define DISCENB 0x40 | |
2567 | #define TAG_ENB 0x20 | |
2568 | #define MK_MESSAGE 0x10 | |
2569 | #define STATUS_RCVD 0x08 | |
2570 | #define DISCONNECTED 0x04 | |
2571 | #define SCB_TAG_TYPE 0x03 | |
2572 | ||
2573 | #define SCB_SCSIID 0x193 | |
2574 | #define TID 0xf0 | |
2575 | #define OID 0x0f | |
2576 | ||
2577 | #define SCB_LUN 0x194 | |
2578 | #define LID 0xff | |
2579 | ||
2580 | #define SCB_TASK_ATTRIBUTE 0x195 | |
2581 | #define SCB_XFERLEN_ODD 0x01 | |
2582 | ||
2583 | #define SCB_CDB_LEN 0x196 | |
2584 | #define SCB_CDB_LEN_PTR 0x80 | |
2585 | ||
2586 | #define SCB_TASK_MANAGEMENT 0x197 | |
2587 | ||
2588 | #define SCB_DATAPTR 0x198 | |
2589 | ||
2590 | #define SCB_DATACNT 0x1a0 | |
2591 | #define SG_LAST_SEG 0x80 | |
2592 | #define SG_HIGH_ADDR_BITS 0x7f | |
2593 | ||
2594 | #define SCB_SGPTR 0x1a4 | |
2595 | #define SG_STATUS_VALID 0x04 | |
2596 | #define SG_FULL_RESID 0x02 | |
2597 | #define SG_LIST_NULL 0x01 | |
2598 | ||
2599 | #define SCB_BUSADDR 0x1a8 | |
2600 | ||
2601 | #define SCB_NEXT 0x1ac | |
2602 | #define SCB_NEXT_SCB_BUSADDR 0x1ac | |
2603 | ||
2604 | #define SCB_NEXT2 0x1ae | |
2605 | ||
2606 | #define SCB_SPARE 0x1b0 | |
2607 | #define SCB_PKT_LUN 0x1b0 | |
2608 | ||
2609 | #define SCB_DISCONNECTED_LISTS 0x1b8 | |
2610 | ||
2611 | ||
11668bb6 HR |
2612 | #define AHD_TIMER_MAX_US 0x18ffe7 |
2613 | #define AHD_TIMER_MAX_TICKS 0xffff | |
2614 | #define AHD_SENSE_BUFSIZE 0x100 | |
2615 | #define BUS_8_BIT 0x00 | |
2616 | #define TARGET_CMD_CMPLT 0xfe | |
2617 | #define SEEOP_WRAL_ADDR 0x40 | |
2618 | #define AHD_AMPLITUDE_DEF 0x07 | |
2619 | #define AHD_PRECOMP_CUTBACK_37 0x07 | |
2620 | #define AHD_PRECOMP_SHIFT 0x00 | |
2621 | #define AHD_ANNEXCOL_PRECOMP_SLEW 0x04 | |
1da177e4 LT |
2622 | #define AHD_TIMER_US_PER_TICK 0x19 |
2623 | #define SCB_TRANSFER_SIZE_FULL_LUN 0x38 | |
2624 | #define STATUS_QUEUE_FULL 0x28 | |
2625 | #define STATUS_BUSY 0x08 | |
2626 | #define MAX_OFFSET_NON_PACED 0x7f | |
2627 | #define MAX_OFFSET_PACED 0xfe | |
2628 | #define BUS_32_BIT 0x02 | |
2629 | #define CCSGADDR_MAX 0x80 | |
2630 | #define TID_SHIFT 0x04 | |
2631 | #define MK_MESSAGE_BIT_OFFSET 0x04 | |
2632 | #define WRTBIASCTL_HP_DEFAULT 0x00 | |
2633 | #define SEEOP_EWDS_ADDR 0x00 | |
2634 | #define AHD_AMPLITUDE_SHIFT 0x00 | |
2635 | #define AHD_AMPLITUDE_MASK 0x07 | |
2636 | #define AHD_ANNEXCOL_AMPLITUDE 0x06 | |
2637 | #define AHD_SLEWRATE_DEF_REVA 0x08 | |
2638 | #define AHD_SLEWRATE_SHIFT 0x03 | |
2639 | #define AHD_SLEWRATE_MASK 0x78 | |
2640 | #define AHD_PRECOMP_CUTBACK_29 0x06 | |
2641 | #define AHD_NUM_PER_DEV_ANNEXCOLS 0x04 | |
2642 | #define B_CURRFIFO_0 0x02 | |
2643 | #define LUNLEN_SINGLE_LEVEL_LUN 0x0f | |
2644 | #define NVRAM_SCB_OFFSET 0x2c | |
1da177e4 | 2645 | #define STATUS_PKT_SENSE 0xff |
060ae855 | 2646 | #define CMD_GROUP_CODE_SHIFT 0x05 |
1da177e4 | 2647 | #define MAX_OFFSET_PACED_BUG 0x7f |
1da177e4 | 2648 | #define STIMESEL_BUG_ADJ 0x08 |
060ae855 DV |
2649 | #define STIMESEL_MIN 0x18 |
2650 | #define STIMESEL_SHIFT 0x03 | |
1da177e4 | 2651 | #define CCSGRAM_MAXSEGS 0x10 |
060ae855 | 2652 | #define INVALID_ADDR 0x80 |
1da177e4 | 2653 | #define SEEOP_ERAL_ADDR 0x80 |
1da177e4 | 2654 | #define AHD_SLEWRATE_DEF_REVB 0x08 |
1da177e4 | 2655 | #define AHD_PRECOMP_CUTBACK_17 0x04 |
060ae855 | 2656 | #define AHD_PRECOMP_MASK 0x07 |
1da177e4 LT |
2657 | #define SRC_MODE_SHIFT 0x00 |
2658 | #define PKT_OVERRUN_BUFSIZE 0x200 | |
2659 | #define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30 | |
060ae855 | 2660 | #define TARGET_DATA_IN 0x01 |
1da177e4 LT |
2661 | #define HOST_MSG 0xff |
2662 | #define MAX_OFFSET 0xfe | |
2663 | #define BUS_16_BIT 0x01 | |
060ae855 DV |
2664 | #define CCSCBADDR_MAX 0x80 |
2665 | #define NUMDSPS 0x14 | |
2666 | #define SEEOP_EWEN_ADDR 0xc0 | |
2667 | #define AHD_ANNEXCOL_PER_DEV0 0x04 | |
2668 | #define DST_MODE_SHIFT 0x04 | |
1da177e4 LT |
2669 | |
2670 | ||
2671 | /* Downloaded Constant Definitions */ | |
11668bb6 | 2672 | #define CACHELINE_MASK 0x07 |
1da177e4 LT |
2673 | #define SCB_TRANSFER_SIZE 0x06 |
2674 | #define PKT_OVERRUN_BUFOFFSET 0x05 | |
060ae855 | 2675 | #define SG_SIZEOF 0x04 |
1da177e4 | 2676 | #define SG_PREFETCH_ADDR_MASK 0x03 |
060ae855 DV |
2677 | #define SG_PREFETCH_ALIGN_MASK 0x02 |
2678 | #define SG_PREFETCH_CNT_LIMIT 0x01 | |
1da177e4 | 2679 | #define SG_PREFETCH_CNT 0x00 |
11668bb6 | 2680 | #define DOWNLOAD_CONST_COUNT 0x08 |
1da177e4 LT |
2681 | |
2682 | ||
2683 | /* Exported Labels */ | |
d10c2e46 | 2684 | #define LABEL_seq_isr 0x28f |
060ae855 | 2685 | #define LABEL_timer_isr 0x28b |