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[SCSI] HP XP devinfo update
[deliverable/linux.git] / drivers / scsi / aic7xxx / aic7xxx.h
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1da177e4
LT		 1/*
2 * Core definitions and data structures shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
79778a27 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#85 $
1da177e4
LT		 41 *
42 * $FreeBSD$
43 */
44
45#ifndef _AIC7XXX_H_
46#define _AIC7XXX_H_
47
48/* Register Definitions */
49#include "aic7xxx_reg.h"
50
51/************************* Forward Declarations *******************************/
52struct ahc_platform_data;
53struct scb_platform_data;
54struct seeprom_descriptor;
55
56/****************************** Useful Macros *********************************/
57#ifndef MAX
58#define MAX(a,b) (((a) > (b)) ? (a) : (b))
59#endif
60
61#ifndef MIN
62#define MIN(a,b) (((a) < (b)) ? (a) : (b))
63#endif
64
65#ifndef TRUE
66#define TRUE 1
67#endif
68#ifndef FALSE
69#define FALSE 0
70#endif
71
1da177e4
LT		 72#define ALL_CHANNELS '\0'
73#define ALL_TARGETS_MASK 0xFFFF
74#define INITIATOR_WILDCARD (~0)
75
76#define SCSIID_TARGET(ahc, scsiid) \
77 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \
78 >> TID_SHIFT)
79#define SCSIID_OUR_ID(scsiid) \
80 ((scsiid) & OID)
81#define SCSIID_CHANNEL(ahc, scsiid) \
82 ((((ahc)->features & AHC_TWIN) != 0) \
83 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \
84 : 'A')
85#define SCB_IS_SCSIBUS_B(ahc, scb) \
86 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B')
87#define SCB_GET_OUR_ID(scb) \
88 SCSIID_OUR_ID((scb)->hscb->scsiid)
89#define SCB_GET_TARGET(ahc, scb) \
90 SCSIID_TARGET((ahc), (scb)->hscb->scsiid)
91#define SCB_GET_CHANNEL(ahc, scb) \
92 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid)
93#define SCB_GET_LUN(scb) \
94 ((scb)->hscb->lun & LID)
95#define SCB_GET_TARGET_OFFSET(ahc, scb) \
96 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0))
97#define SCB_GET_TARGET_MASK(ahc, scb) \
98 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb)))
99#ifdef AHC_DEBUG
100#define SCB_IS_SILENT(scb) \
101 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \
102 && (((scb)->flags & SCB_SILENT) != 0))
103#else
104#define SCB_IS_SILENT(scb) \
105 (((scb)->flags & SCB_SILENT) != 0)
106#endif
107#define TCL_TARGET_OFFSET(tcl) \
108 ((((tcl) >> 4) & TID) >> 4)
109#define TCL_LUN(tcl) \
110 (tcl & (AHC_NUM_LUNS - 1))
111#define BUILD_TCL(scsiid, lun) \
112 ((lun) | (((scsiid) & TID) << 4))
113
114#ifndef AHC_TARGET_MODE
115#undef AHC_TMODE_ENABLE
116#define AHC_TMODE_ENABLE 0
117#endif
118
119/**************************** Driver Constants ********************************/
120/*
121 * The maximum number of supported targets.
122 */
123#define AHC_NUM_TARGETS 16
124
125/*
126 * The maximum number of supported luns.
127 * The identify message only supports 64 luns in SPI3.
128 * You can have 2^64 luns when information unit transfers are enabled,
129 * but it is doubtful this driver will ever support IUTs.
130 */
131#define AHC_NUM_LUNS 64
132
133/*
134 * The maximum transfer per S/G segment.
135 */
136#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
137
138/*
139 * The maximum amount of SCB storage in hardware on a controller.
140 * This value represents an upper bound. Controllers vary in the number
141 * they actually support.
142 */
143#define AHC_SCB_MAX 255
144
145/*
146 * The maximum number of concurrent transactions supported per driver instance.
147 * Sequencer Control Blocks (SCBs) store per-transaction information. Although
148 * the space for SCBs on the host adapter varies by model, the driver will
149 * page the SCBs between host and controller memory as needed. We are limited
150 * to 253 because:
151 * 1) The 8bit nature of the RISC engine holds us to an 8bit value.
152 * 2) We reserve one value, 255, to represent the invalid element.
153 * 3) Our input queue scheme requires one SCB to always be reserved
154 * in advance of queuing any SCBs. This takes us down to 254.
155 * 4) To handle our output queue correctly on machines that only
156 * support 32bit stores, we must clear the array 4 bytes at a
157 * time. To avoid colliding with a DMA write from the sequencer,
158 * we must be sure that 4 slots are empty when we write to clear
159 * the queue. This reduces us to 253 SCBs: 1 that just completed
160 * and the known three additional empty slots in the queue that
161 * precede it.
162 */
163#define AHC_MAX_QUEUE 253
164
165/*
166 * The maximum amount of SCB storage we allocate in host memory. This
167 * number should reflect the 1 additional SCB we require to handle our
168 * qinfifo mechanism.
169 */
170#define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1)
171
172/*
173 * Ring Buffer of incoming target commands.
174 * We allocate 256 to simplify the logic in the sequencer
175 * by using the natural wrap point of an 8bit counter.
176 */
177#define AHC_TMODE_CMDS 256
178
179/* Reset line assertion time in us */
180#define AHC_BUSRESET_DELAY 25
181
182/******************* Chip Characteristics/Operating Settings *****************/
183/*
184 * Chip Type
185 * The chip order is from least sophisticated to most sophisticated.
186 */
187typedef enum {
188 AHC_NONE = 0x0000,
189 AHC_CHIPID_MASK = 0x00FF,
190 AHC_AIC7770 = 0x0001,
191 AHC_AIC7850 = 0x0002,
192 AHC_AIC7855 = 0x0003,
193 AHC_AIC7859 = 0x0004,
194 AHC_AIC7860 = 0x0005,
195 AHC_AIC7870 = 0x0006,
196 AHC_AIC7880 = 0x0007,
197 AHC_AIC7895 = 0x0008,
198 AHC_AIC7895C = 0x0009,
199 AHC_AIC7890 = 0x000a,
200 AHC_AIC7896 = 0x000b,
201 AHC_AIC7892 = 0x000c,
202 AHC_AIC7899 = 0x000d,
203 AHC_VL = 0x0100, /* Bus type VL */
204 AHC_EISA = 0x0200, /* Bus type EISA */
205 AHC_PCI = 0x0400, /* Bus type PCI */
206 AHC_BUS_MASK = 0x0F00
207} ahc_chip;
208
209/*
210 * Features available in each chip type.
211 */
212typedef enum {
213 AHC_FENONE = 0x00000,
214 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */
215 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */
216 AHC_WIDE = 0x00004, /* Wide Channel */
217 AHC_TWIN = 0x00008, /* Twin Channel */
218 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */
219 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */
220 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */
221 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */
222 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */
223 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */
224 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */
225 AHC_DT = 0x00800, /* Double Transition transfers */
226 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */
227 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */
228 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */
229 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/
230 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */
231 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */
232 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */
233 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */
b2d8bfe1 234 AHC_HVD = 0x100000, /* HVD rather than SE */
1da177e4
LT		 235 AHC_AIC7770_FE = AHC_FENONE,
236 /*
237 * The real 7850 does not support Ultra modes, but there are
238 * several cards that use the generic 7850 PCI ID even though
239 * they are using an Ultra capable chip (7859/7860). We start
240 * out with the AHC_ULTRA feature set and then check the DEVSTATUS
241 * register to determine if the capability is really present.
242 */
243 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA,
244 AHC_AIC7860_FE = AHC_AIC7850_FE,
79778a27 245 AHC_AIC7870_FE = AHC_TARGETMODE|AHC_AUTOPAUSE,
1da177e4
LT		 246 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA,
247 /*
248 * Although we have space for both the initiator and
249 * target roles on ULTRA2 chips, we currently disable
250 * the initiator role to allow multi-scsi-id target mode
251 * configurations. We can only respond on the same SCSI
252 * ID as our initiator role if we allow initiator operation.
253 * At some point, we should add a configuration knob to
254 * allow both roles to be loaded.
255 */
256 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2
257 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID
258 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS
259 |AHC_TARGETMODE,
260 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE,
261 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE
262 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS,
263 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID,
264 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC,
265 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC
266} ahc_feature;
267
268/*
269 * Bugs in the silicon that we work around in software.
270 */
271typedef enum {
272 AHC_BUGNONE = 0x00,
273 /*
274 * On all chips prior to the U2 product line,
275 * the WIDEODD S/G segment feature does not
276 * work during scsi->HostBus transfers.
277 */
278 AHC_TMODE_WIDEODD_BUG = 0x01,
279 /*
280 * On the aic7890/91 Rev 0 chips, the autoflush
281 * feature does not work. A manual flush of
282 * the DMA FIFO is required.
283 */
284 AHC_AUTOFLUSH_BUG = 0x02,
285 /*
286 * On many chips, cacheline streaming does not work.
287 */
288 AHC_CACHETHEN_BUG = 0x04,
289 /*
290 * On the aic7896/97 chips, cacheline
291 * streaming must be enabled.
292 */
293 AHC_CACHETHEN_DIS_BUG = 0x08,
294 /*
295 * PCI 2.1 Retry failure on non-empty data fifo.
296 */
297 AHC_PCI_2_1_RETRY_BUG = 0x10,
298 /*
299 * Controller does not handle cacheline residuals
300 * properly on S/G segments if PCI MWI instructions
301 * are allowed.
302 */
303 AHC_PCI_MWI_BUG = 0x20,
304 /*
305 * An SCB upload using the SCB channel's
306 * auto array entry copy feature may
307 * corrupt data. This appears to only
308 * occur on 66MHz systems.
309 */
310 AHC_SCBCHAN_UPLOAD_BUG = 0x40
311} ahc_bug;
312
313/*
314 * Configuration specific settings.
315 * The driver determines these settings by probing the
316 * chip/controller's configuration.
317 */
318typedef enum {
319 AHC_FNONE = 0x000,
320 AHC_PRIMARY_CHANNEL = 0x003, /*
321 * The channel that should
322 * be probed first.
323 */
324 AHC_USEDEFAULTS = 0x004, /*
325 * For cards without an seeprom
326 * or a BIOS to initialize the chip's
327 * SRAM, we use the default target
328 * settings.
329 */
330 AHC_SEQUENCER_DEBUG = 0x008,
331 AHC_SHARED_SRAM = 0x010,
332 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */
333 AHC_RESET_BUS_A = 0x040,
334 AHC_RESET_BUS_B = 0x080,
335 AHC_EXTENDED_TRANS_A = 0x100,
336 AHC_EXTENDED_TRANS_B = 0x200,
337 AHC_TERM_ENB_A = 0x400,
338 AHC_TERM_ENB_B = 0x800,
339 AHC_INITIATORROLE = 0x1000, /*
340 * Allow initiator operations on
341 * this controller.
342 */
343 AHC_TARGETROLE = 0x2000, /*
344 * Allow target operations on this
345 * controller.
346 */
347 AHC_NEWEEPROM_FMT = 0x4000,
1da177e4
LT		 348 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */
349 AHC_INT50_SPEEDFLEX = 0x20000, /*
350 * Internal 50pin connector
351 * sits behind an aic3860
352 */
353 AHC_SCB_BTT = 0x40000, /*
354 * The busy targets table is
355 * stored in SCB space rather
356 * than SRAM.
357 */
358 AHC_BIOS_ENABLED = 0x80000,
359 AHC_ALL_INTERRUPTS = 0x100000,
360 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */
361 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */
362 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */
363 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */
364 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */
365 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */
366 AHC_DISABLE_PCI_PERR = 0x10000000,
367 AHC_HAS_TERM_LOGIC = 0x20000000
368} ahc_flag;
369
370/************************* Hardware SCB Definition ***************************/
371
372/*
373 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
374 * consists of a "hardware SCB" mirroring the fields available on the card
375 * and additional information the kernel stores for each transaction.
376 *
377 * To minimize space utilization, a portion of the hardware scb stores
378 * different data during different portions of a SCSI transaction.
379 * As initialized by the host driver for the initiator role, this area
380 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
381 * the cdb has been presented to the target, this area serves to store
382 * residual transfer information and the SCSI status byte.
383 * For the target role, the contents of this area do not change, but
384 * still serve a different purpose than for the initiator role. See
385 * struct target_data for details.
386 */
387
388/*
389 * Status information embedded in the shared poriton of
390 * an SCB after passing the cdb to the target. The kernel
391 * driver will only read this data for transactions that
392 * complete abnormally (non-zero status byte).
393 */
394struct status_pkt {
395 uint32_t residual_datacnt; /* Residual in the current S/G seg */
396 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
397 uint8_t scsi_status; /* Standard SCSI status byte */
398};
399
400/*
401 * Target mode version of the shared data SCB segment.
402 */
403struct target_data {
404 uint32_t residual_datacnt; /* Residual in the current S/G seg */
405 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
406 uint8_t scsi_status; /* SCSI status to give to initiator */
407 uint8_t target_phases; /* Bitmap of phases to execute */
408 uint8_t data_phase; /* Data-In or Data-Out */
409 uint8_t initiator_tag; /* Initiator's transaction tag */
410};
411
412struct hardware_scb {
413/*0*/ union {
414 /*
415 * If the cdb is 12 bytes or less, we embed it directly
416 * in the SCB. For longer cdbs, we embed the address
417 * of the cdb payload as seen by the chip and a DMA
418 * is used to pull it in.
419 */
420 uint8_t cdb[12];
421 uint32_t cdb_ptr;
422 struct status_pkt status;
423 struct target_data tdata;
424 } shared_data;
425/*
426 * A word about residuals.
427 * The scb is presented to the sequencer with the dataptr and datacnt
428 * fields initialized to the contents of the first S/G element to
429 * transfer. The sgptr field is initialized to the bus address for
430 * the S/G element that follows the first in the in core S/G array
431 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
432 * S/G entry for this transfer (single S/G element transfer with the
433 * first elements address and length preloaded in the dataptr/datacnt
434 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
435 * The SG_FULL_RESID flag ensures that the residual will be correctly
436 * noted even if no data transfers occur. Once the data phase is entered,
437 * the residual sgptr and datacnt are loaded from the sgptr and the
438 * datacnt fields. After each S/G element's dataptr and length are
439 * loaded into the hardware, the residual sgptr is advanced. After
440 * each S/G element is expired, its datacnt field is checked to see
441 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
442 * residual sg ptr and the transfer is considered complete. If the
443 * sequencer determines that there is a residual in the tranfer, it
444 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into
445 * host memory. To sumarize:
446 *
447 * Sequencer:
448 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
449 * or residual_sgptr does not have SG_LIST_NULL set.
450 *
451 * o We are transfering the last segment if residual_datacnt has
452 * the SG_LAST_SEG flag set.
453 *
454 * Host:
455 * o A residual has occurred if a completed scb has the
456 * SG_RESID_VALID flag set.
457 *
458 * o residual_sgptr and sgptr refer to the "next" sg entry
459 * and so may point beyond the last valid sg entry for the
460 * transfer.
461 */
462/*12*/ uint32_t dataptr;
463/*16*/ uint32_t datacnt; /*
464 * Byte 3 (numbered from 0) of
465 * the datacnt is really the
466 * 4th byte in that data address.
467 */
468/*20*/ uint32_t sgptr;
469#define SG_PTR_MASK 0xFFFFFFF8
470/*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */
471/*25*/ uint8_t scsiid; /* what to load in the SCSIID register */
472/*26*/ uint8_t lun;
473/*27*/ uint8_t tag; /*
474 * Index into our kernel SCB array.
475 * Also used as the tag for tagged I/O
476 */
477/*28*/ uint8_t cdb_len;
478/*29*/ uint8_t scsirate; /* Value for SCSIRATE register */
479/*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */
480/*31*/ uint8_t next; /*
481 * Used for threading SCBs in the
482 * "Waiting for Selection" and
483 * "Disconnected SCB" lists down
484 * in the sequencer.
485 */
486/*32*/ uint8_t cdb32[32]; /*
487 * CDB storage for cdbs of size
488 * 13->32. We store them here
489 * because hardware scbs are
490 * allocated from DMA safe
491 * memory so we are guaranteed
492 * the controller can access
493 * this data.
494 */
495};
496
497/************************ Kernel SCB Definitions ******************************/
498/*
499 * Some fields of the SCB are OS dependent. Here we collect the
500 * definitions for elements that all OS platforms need to include
501 * in there SCB definition.
502 */
503
504/*
505 * Definition of a scatter/gather element as transfered to the controller.
506 * The aic7xxx chips only support a 24bit length. We use the top byte of
507 * the length to store additional address bits and a flag to indicate
508 * that a given segment terminates the transfer. This gives us an
509 * addressable range of 512GB on machines with 64bit PCI or with chips
510 * that can support dual address cycles on 32bit PCI busses.
511 */
512struct ahc_dma_seg {
513 uint32_t addr;
514 uint32_t len;
515#define AHC_DMA_LAST_SEG 0x80000000
516#define AHC_SG_HIGH_ADDR_MASK 0x7F000000
517#define AHC_SG_LEN_MASK 0x00FFFFFF
518};
519
520struct sg_map_node {
521 bus_dmamap_t sg_dmamap;
522 dma_addr_t sg_physaddr;
523 struct ahc_dma_seg* sg_vaddr;
524 SLIST_ENTRY(sg_map_node) links;
525};
526
527/*
528 * The current state of this SCB.
529 */
530typedef enum {
531 SCB_FREE = 0x0000,
532 SCB_OTHERTCL_TIMEOUT = 0x0002,/*
533 * Another device was active
534 * during the first timeout for
535 * this SCB so we gave ourselves
536 * an additional timeout period
537 * in case it was hogging the
538 * bus.
539 */
540 SCB_DEVICE_RESET = 0x0004,
541 SCB_SENSE = 0x0008,
542 SCB_CDB32_PTR = 0x0010,
543 SCB_RECOVERY_SCB = 0x0020,
544 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */
545 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */
546 SCB_ABORT = 0x0100,
547 SCB_UNTAGGEDQ = 0x0200,
548 SCB_ACTIVE = 0x0400,
549 SCB_TARGET_IMMEDIATE = 0x0800,
550 SCB_TRANSMISSION_ERROR = 0x1000,/*
551 * We detected a parity or CRC
552 * error that has effected the
553 * payload of the command. This
554 * flag is checked when normal
555 * status is returned to catch
556 * the case of a target not
557 * responding to our attempt
558 * to report the error.
559 */
560 SCB_TARGET_SCB = 0x2000,
561 SCB_SILENT = 0x4000 /*
562 * Be quiet about transmission type
563 * errors. They are expected and we
564 * don't want to upset the user. This
565 * flag is typically used during DV.
566 */
567} scb_flag;
568
569struct scb {
570 struct hardware_scb *hscb;
571 union {
572 SLIST_ENTRY(scb) sle;
573 TAILQ_ENTRY(scb) tqe;
574 } links;
575 LIST_ENTRY(scb) pending_links;
576 ahc_io_ctx_t io_ctx;
577 struct ahc_softc *ahc_softc;
578 scb_flag flags;
579#ifndef __linux__
580 bus_dmamap_t dmamap;
581#endif
582 struct scb_platform_data *platform_data;
583 struct sg_map_node *sg_map;
584 struct ahc_dma_seg *sg_list;
585 dma_addr_t sg_list_phys;
586 u_int sg_count;/* How full ahc_dma_seg is */
587};
588
589struct scb_data {
590 SLIST_HEAD(, scb) free_scbs; /*
591 * Pool of SCBs ready to be assigned
592 * commands to execute.
593 */
594 struct scb *scbindex[256]; /*
595 * Mapping from tag to SCB.
596 * As tag identifiers are an
597 * 8bit value, we provide space
598 * for all possible tag values.
599 * Any lookups to entries at or
600 * above AHC_SCB_MAX_ALLOC will
601 * always fail.
602 */
603 struct hardware_scb *hscbs; /* Array of hardware SCBs */
604 struct scb *scbarray; /* Array of kernel SCBs */
605 struct scsi_sense_data *sense; /* Per SCB sense data */
606
607 /*
608 * "Bus" addresses of our data structures.
609 */
610 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */
611 bus_dmamap_t hscb_dmamap;
612 dma_addr_t hscb_busaddr;
613 bus_dma_tag_t sense_dmat;
614 bus_dmamap_t sense_dmamap;
615 dma_addr_t sense_busaddr;
616 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
617 SLIST_HEAD(, sg_map_node) sg_maps;
618 uint8_t numscbs;
619 uint8_t maxhscbs; /* Number of SCBs on the card */
620 uint8_t init_level; /*
621 * How far we've initialized
622 * this structure.
623 */
624};
625
626/************************ Target Mode Definitions *****************************/
627
628/*
629 * Connection desciptor for select-in requests in target mode.
630 */
631struct target_cmd {
632 uint8_t scsiid; /* Our ID and the initiator's ID */
633 uint8_t identify; /* Identify message */
634 uint8_t bytes[22]; /*
635 * Bytes contains any additional message
636 * bytes terminated by 0xFF. The remainder
637 * is the cdb to execute.
638 */
639 uint8_t cmd_valid; /*
640 * When a command is complete, the firmware
641 * will set cmd_valid to all bits set.
642 * After the host has seen the command,
643 * the bits are cleared. This allows us
644 * to just peek at host memory to determine
645 * if more work is complete. cmd_valid is on
646 * an 8 byte boundary to simplify setting
647 * it on aic7880 hardware which only has
648 * limited direct access to the DMA FIFO.
649 */
650 uint8_t pad[7];
651};
652
653/*
654 * Number of events we can buffer up if we run out
655 * of immediate notify ccbs.
656 */
657#define AHC_TMODE_EVENT_BUFFER_SIZE 8
658struct ahc_tmode_event {
659 uint8_t initiator_id;
660 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
661#define EVENT_TYPE_BUS_RESET 0xFF
662 uint8_t event_arg;
663};
664
665/*
666 * Per enabled lun target mode state.
667 * As this state is directly influenced by the host OS'es target mode
668 * environment, we let the OS module define it. Forward declare the
669 * structure here so we can store arrays of them, etc. in OS neutral
670 * data structures.
671 */
672#ifdef AHC_TARGET_MODE
673struct ahc_tmode_lstate {
674 struct cam_path *path;
675 struct ccb_hdr_slist accept_tios;
676 struct ccb_hdr_slist immed_notifies;
677 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE];
678 uint8_t event_r_idx;
679 uint8_t event_w_idx;
680};
681#else
682struct ahc_tmode_lstate;
683#endif
684
685/******************** Transfer Negotiation Datastructures *********************/
686#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */
687#define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
688#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */
689#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */
690
691#define AHC_WIDTH_UNKNOWN 0xFF
692#define AHC_PERIOD_UNKNOWN 0xFF
693#define AHC_OFFSET_UNKNOWN 0xFF
694#define AHC_PPR_OPTS_UNKNOWN 0xFF
695
696/*
697 * Transfer Negotiation Information.
698 */
699struct ahc_transinfo {
700 uint8_t protocol_version; /* SCSI Revision level */
701 uint8_t transport_version; /* SPI Revision level */
702 uint8_t width; /* Bus width */
703 uint8_t period; /* Sync rate factor */
704 uint8_t offset; /* Sync offset */
705 uint8_t ppr_options; /* Parallel Protocol Request options */
706};
707
708/*
709 * Per-initiator current, goal and user transfer negotiation information. */
710struct ahc_initiator_tinfo {
711 uint8_t scsirate; /* Computed value for SCSIRATE reg */
712 struct ahc_transinfo curr;
713 struct ahc_transinfo goal;
714 struct ahc_transinfo user;
715};
716
717/*
718 * Per enabled target ID state.
719 * Pointers to lun target state as well as sync/wide negotiation information
720 * for each initiator<->target mapping. For the initiator role we pretend
721 * that we are the target and the targets are the initiators since the
722 * negotiation is the same regardless of role.
723 */
724struct ahc_tmode_tstate {
725 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS];
726 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS];
727
728 /*
729 * Per initiator state bitmasks.
730 */
731 uint16_t auto_negotiate;/* Auto Negotiation Required */
732 uint16_t ultraenb; /* Using ultra sync rate */
733 uint16_t discenable; /* Disconnection allowed */
734 uint16_t tagenable; /* Tagged Queuing allowed */
735};
736
737/*
738 * Data structure for our table of allowed synchronous transfer rates.
739 */
740struct ahc_syncrate {
741 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */
742 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */
743#define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */
744#define ST_SXFR 0x010 /* Rate Single Transition Only */
745#define DT_SXFR 0x040 /* Rate Double Transition Only */
746 uint8_t period; /* Period to send to SCSI target */
747 char *rate;
748};
749
750/* Safe and valid period for async negotiations. */
751#define AHC_ASYNC_XFER_PERIOD 0x45
752#define AHC_ULTRA2_XFER_PERIOD 0x0a
753
754/*
755 * Indexes into our table of syncronous transfer rates.
756 */
757#define AHC_SYNCRATE_DT 0
758#define AHC_SYNCRATE_ULTRA2 1
759#define AHC_SYNCRATE_ULTRA 3
760#define AHC_SYNCRATE_FAST 6
761#define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT
762#define AHC_SYNCRATE_MIN 13
763
764/***************************** Lookup Tables **********************************/
765/*
766 * Phase -> name and message out response
767 * to parity errors in each phase table.
768 */
769struct ahc_phase_table_entry {
770 uint8_t phase;
771 uint8_t mesg_out; /* Message response to parity errors */
772 char *phasemsg;
773};
774
775/************************** Serial EEPROM Format ******************************/
776
777struct seeprom_config {
778/*
779 * Per SCSI ID Configuration Flags
780 */
781 uint16_t device_flags[16]; /* words 0-15 */
782#define CFXFER 0x0007 /* synchronous transfer rate */
783#define CFSYNCH 0x0008 /* enable synchronous transfer */
784#define CFDISC 0x0010 /* enable disconnection */
785#define CFWIDEB 0x0020 /* wide bus device */
786#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/
787#define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */
788#define CFSTART 0x0100 /* send start unit SCSI command */
789#define CFINCBIOS 0x0200 /* include in BIOS scan */
790#define CFRNFOUND 0x0400 /* report even if not found */
791#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
792#define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */
793#define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */
794
795/*
796 * BIOS Control Bits
797 */
798 uint16_t bios_control; /* word 16 */
799#define CFSUPREM 0x0001 /* support all removeable drives */
800#define CFSUPREMB 0x0002 /* support removeable boot drives */
801#define CFBIOSEN 0x0004 /* BIOS enabled */
802#define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */
803#define CFSM2DRV 0x0010 /* support more than two drives */
804#define CFSTPWLEVEL 0x0010 /* Termination level control */
805#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */
806#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
807#define CFTERM_MENU 0x0040 /* BIOS displays termination menu */
808#define CFEXTEND 0x0080 /* extended translation enabled */
809#define CFSCAMEN 0x0100 /* SCAM enable */
810#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
811#define CFMSG_VERBOSE 0x0000
812#define CFMSG_SILENT 0x0200
813#define CFMSG_DIAG 0x0400
814#define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */
815/* UNUSED 0xff00 */
816
817/*
818 * Host Adapter Control Bits
819 */
820 uint16_t adapter_control; /* word 17 */
821#define CFAUTOTERM 0x0001 /* Perform Auto termination */
822#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */
823#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */
824#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */
825#define CFSTERM 0x0004 /* SCSI low byte termination */
826#define CFWSTERM 0x0008 /* SCSI high byte termination */
827#define CFSPARITY 0x0010 /* SCSI parity */
828#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */
829#define CFMULTILUN 0x0020
830#define CFRESETB 0x0040 /* reset SCSI bus at boot */
831#define CFCLUSTERENB 0x0080 /* Cluster Enable */
832#define CFBOOTCHAN 0x0300 /* probe this channel first */
833#define CFBOOTCHANSHIFT 8
834#define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/
835#define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */
836#define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */
837#define CFENABLEDV 0x4000 /* Perform Domain Validation*/
838
839/*
840 * Bus Release Time, Host Adapter ID
841 */
842 uint16_t brtime_id; /* word 18 */
843#define CFSCSIID 0x000f /* host adapter SCSI ID */
844/* UNUSED 0x00f0 */
845#define CFBRTIME 0xff00 /* bus release time */
846
847/*
848 * Maximum targets
849 */
850 uint16_t max_targets; /* word 19 */
851#define CFMAXTARG 0x00ff /* maximum targets */
852#define CFBOOTLUN 0x0f00 /* Lun to boot from */
853#define CFBOOTID 0xf000 /* Target to boot from */
854 uint16_t res_1[10]; /* words 20-29 */
855 uint16_t signature; /* Signature == 0x250 */
856#define CFSIGNATURE 0x250
857#define CFSIGNATURE2 0x300
858 uint16_t checksum; /* word 31 */
859};
860
861/**************************** Message Buffer *********************************/
862typedef enum {
863 MSG_TYPE_NONE = 0x00,
864 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
865 MSG_TYPE_INITIATOR_MSGIN = 0x02,
866 MSG_TYPE_TARGET_MSGOUT = 0x03,
867 MSG_TYPE_TARGET_MSGIN = 0x04
868} ahc_msg_type;
869
870typedef enum {
871 MSGLOOP_IN_PROG,
872 MSGLOOP_MSGCOMPLETE,
873 MSGLOOP_TERMINATED
874} msg_loop_stat;
875
876/*********************** Software Configuration Structure *********************/
877TAILQ_HEAD(scb_tailq, scb);
878
879struct ahc_aic7770_softc {
880 /*
881 * Saved register state used for chip_init().
882 */
883 uint8_t busspd;
884 uint8_t bustime;
885};
886
887struct ahc_pci_softc {
888 /*
889 * Saved register state used for chip_init().
890 */
891 uint32_t devconfig;
892 uint16_t targcrccnt;
893 uint8_t command;
894 uint8_t csize_lattime;
895 uint8_t optionmode;
896 uint8_t crccontrol1;
897 uint8_t dscommand0;
898 uint8_t dspcistatus;
899 uint8_t scbbaddr;
900 uint8_t dff_thrsh;
901};
902
903union ahc_bus_softc {
904 struct ahc_aic7770_softc aic7770_softc;
905 struct ahc_pci_softc pci_softc;
906};
907
908typedef void (*ahc_bus_intr_t)(struct ahc_softc *);
909typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *);
910typedef int (*ahc_bus_suspend_t)(struct ahc_softc *);
911typedef int (*ahc_bus_resume_t)(struct ahc_softc *);
912typedef void ahc_callback_t (void *);
913
914struct ahc_softc {
915 bus_space_tag_t tag;
916 bus_space_handle_t bsh;
917#ifndef __linux__
918 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
919#endif
920 struct scb_data *scb_data;
921
922 struct scb *next_queued_scb;
923
924 /*
925 * SCBs that have been sent to the controller
926 */
927 LIST_HEAD(, scb) pending_scbs;
928
929 /*
930 * Counting lock for deferring the release of additional
931 * untagged transactions from the untagged_queues. When
932 * the lock is decremented to 0, all queues in the
933 * untagged_queues array are run.
934 */
935 u_int untagged_queue_lock;
936
937 /*
938 * Per-target queue of untagged-transactions. The
939 * transaction at the head of the queue is the
940 * currently pending untagged transaction for the
941 * target. The driver only allows a single untagged
942 * transaction per target.
943 */
944 struct scb_tailq untagged_queues[AHC_NUM_TARGETS];
945
946 /*
947 * Bus attachment specific data.
948 */
949 union ahc_bus_softc bus_softc;
950
951 /*
952 * Platform specific data.
953 */
954 struct ahc_platform_data *platform_data;
955
956 /*
957 * Platform specific device information.
958 */
959 ahc_dev_softc_t dev_softc;
960
961 /*
962 * Bus specific device information.
963 */
964 ahc_bus_intr_t bus_intr;
965
966 /*
967 * Bus specific initialization required
968 * after a chip reset.
969 */
970 ahc_bus_chip_init_t bus_chip_init;
971
972 /*
973 * Bus specific suspend routine.
974 */
975 ahc_bus_suspend_t bus_suspend;
976
977 /*
978 * Bus specific resume routine.
979 */
980 ahc_bus_resume_t bus_resume;
981
982 /*
983 * Target mode related state kept on a per enabled lun basis.
984 * Targets that are not enabled will have null entries.
985 * As an initiator, we keep one target entry for our initiator
986 * ID to store our sync/wide transfer settings.
987 */
988 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS];
989
990 /*
991 * The black hole device responsible for handling requests for
992 * disabled luns on enabled targets.
993 */
994 struct ahc_tmode_lstate *black_hole;
995
996 /*
997 * Device instance currently on the bus awaiting a continue TIO
998 * for a command that was not given the disconnect priveledge.
999 */
1000 struct ahc_tmode_lstate *pending_device;
1001
1002 /*
1003 * Card characteristics
1004 */
1005 ahc_chip chip;
1006 ahc_feature features;
1007 ahc_bug bugs;
1008 ahc_flag flags;
1009 struct seeprom_config *seep_config;
1010
1011 /* Values to store in the SEQCTL register for pause and unpause */
1012 uint8_t unpause;
1013 uint8_t pause;
1014
1015 /* Command Queues */
1016 uint8_t qoutfifonext;
1017 uint8_t qinfifonext;
1018 uint8_t *qoutfifo;
1019 uint8_t *qinfifo;
1020
1021 /* Critical Section Data */
1022 struct cs *critical_sections;
1023 u_int num_critical_sections;
1024
1da177e4
LT		 1025 /* Channel Names ('A', 'B', etc.) */
1026 char channel;
1027 char channel_b;
1028
1029 /* Initiator Bus ID */
1030 uint8_t our_id;
1031 uint8_t our_id_b;
1032
1033 /*
1034 * PCI error detection.
1035 */
1036 int unsolicited_ints;
1037
1038 /*
1039 * Target incoming command FIFO.
1040 */
1041 struct target_cmd *targetcmds;
1042 uint8_t tqinfifonext;
1043
1044 /*
1045 * Cached copy of the sequencer control register.
1046 */
1047 uint8_t seqctl;
1048
1049 /*
1050 * Incoming and outgoing message handling.
1051 */
1052 uint8_t send_msg_perror;
1053 ahc_msg_type msg_type;
1054 uint8_t msgout_buf[12];/* Message we are sending */
1055 uint8_t msgin_buf[12];/* Message we are receiving */
1056 u_int msgout_len; /* Length of message to send */
1057 u_int msgout_index; /* Current index in msgout */
1058 u_int msgin_index; /* Current index in msgin */
1059
1060 /*
1061 * Mapping information for data structures shared
1062 * between the sequencer and kernel.
1063 */
1064 bus_dma_tag_t parent_dmat;
1065 bus_dma_tag_t shared_data_dmat;
1066 bus_dmamap_t shared_data_dmamap;
1067 dma_addr_t shared_data_busaddr;
1068
1069 /*
1070 * Bus address of the one byte buffer used to
1071 * work-around a DMA bug for chips <= aic7880
1072 * in target mode.
1073 */
1074 dma_addr_t dma_bug_buf;
1075
1076 /* Number of enabled target mode device on this card */
1077 u_int enabled_luns;
1078
1079 /* Initialization level of this data structure */
1080 u_int init_level;
1081
1082 /* PCI cacheline size. */
1083 u_int pci_cachesize;
1084
1085 /*
1086 * Count of parity errors we have seen as a target.
1087 * We auto-disable parity error checking after seeing
1088 * AHC_PCI_TARGET_PERR_THRESH number of errors.
1089 */
1090 u_int pci_target_perr_count;
1091#define AHC_PCI_TARGET_PERR_THRESH 10
1092
1093 /* Maximum number of sequencer instructions supported. */
1094 u_int instruction_ram_size;
1095
1096 /* Per-Unit descriptive information */
1097 const char *description;
1098 char *name;
1099 int unit;
1100
1101 /* Selection Timer settings */
1102 int seltime;
1103 int seltime_b;
1104
1105 uint16_t user_discenable;/* Disconnection allowed */
1106 uint16_t user_tagenable;/* Tagged Queuing allowed */
1107};
1108
1da177e4
LT		 1109/************************ Active Device Information ***************************/
1110typedef enum {
1111 ROLE_UNKNOWN,
1112 ROLE_INITIATOR,
1113 ROLE_TARGET
1114} role_t;
1115
1116struct ahc_devinfo {
1117 int our_scsiid;
1118 int target_offset;
1119 uint16_t target_mask;
1120 u_int target;
1121 u_int lun;
1122 char channel;
1123 role_t role; /*
1124 * Only guaranteed to be correct if not
1125 * in the busfree state.
1126 */
1127};
1128
1129/****************************** PCI Structures ********************************/
1130typedef int (ahc_device_setup_t)(struct ahc_softc *);
1131
1132struct ahc_pci_identity {
1133 uint64_t full_id;
1134 uint64_t id_mask;
1135 char *name;
1136 ahc_device_setup_t *setup;
1137};
1138extern struct ahc_pci_identity ahc_pci_ident_table[];
1139extern const u_int ahc_num_pci_devs;
1140
1141/***************************** VL/EISA Declarations ***************************/
1142struct aic7770_identity {
1143 uint32_t full_id;
1144 uint32_t id_mask;
1145 const char *name;
1146 ahc_device_setup_t *setup;
1147};
1148extern struct aic7770_identity aic7770_ident_table[];
1149extern const int ahc_num_aic7770_devs;
1150
1151#define AHC_EISA_SLOT_OFFSET 0xc00
1152#define AHC_EISA_IOSIZE 0x100
1153
1154/*************************** Function Declarations ****************************/
1155/******************************************************************************/
1156u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl);
1157void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl);
1158void ahc_busy_tcl(struct ahc_softc *ahc,
1159 u_int tcl, u_int busyid);
1160
1161/***************************** PCI Front End *********************************/
1162struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t);
1163int ahc_pci_config(struct ahc_softc *,
1164 struct ahc_pci_identity *);
1165int ahc_pci_test_register_access(struct ahc_softc *);
1166
1167/*************************** EISA/VL Front End ********************************/
1168struct aic7770_identity *aic7770_find_device(uint32_t);
1169int aic7770_config(struct ahc_softc *ahc,
1170 struct aic7770_identity *,
1171 u_int port);
1172
1173/************************** SCB and SCB queue management **********************/
1174int ahc_probe_scbs(struct ahc_softc *);
1175void ahc_run_untagged_queues(struct ahc_softc *ahc);
1176void ahc_run_untagged_queue(struct ahc_softc *ahc,
1177 struct scb_tailq *queue);
1178void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc,
1179 struct scb *scb);
1180int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb,
1181 int target, char channel, int lun,
1182 u_int tag, role_t role);
1183
1184/****************************** Initialization ********************************/
1185struct ahc_softc *ahc_alloc(void *platform_arg, char *name);
1186int ahc_softc_init(struct ahc_softc *);
1187void ahc_controller_info(struct ahc_softc *ahc, char *buf);
1188int ahc_chip_init(struct ahc_softc *ahc);
1189int ahc_init(struct ahc_softc *ahc);
1190void ahc_intr_enable(struct ahc_softc *ahc, int enable);
1191void ahc_pause_and_flushwork(struct ahc_softc *ahc);
1192int ahc_suspend(struct ahc_softc *ahc);
1193int ahc_resume(struct ahc_softc *ahc);
1da177e4
LT		 1194void ahc_set_unit(struct ahc_softc *, int);
1195void ahc_set_name(struct ahc_softc *, char *);
1196void ahc_alloc_scbs(struct ahc_softc *ahc);
1197void ahc_free(struct ahc_softc *ahc);
1198int ahc_reset(struct ahc_softc *ahc, int reinit);
1199void ahc_shutdown(void *arg);
1200
1201/*************************** Interrupt Services *******************************/
1202void ahc_clear_intstat(struct ahc_softc *ahc);
1203void ahc_run_qoutfifo(struct ahc_softc *ahc);
1204#ifdef AHC_TARGET_MODE
1205void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused);
1206#endif
1207void ahc_handle_brkadrint(struct ahc_softc *ahc);
1208void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat);
1209void ahc_handle_scsiint(struct ahc_softc *ahc,
1210 u_int intstat);
1211void ahc_clear_critical_section(struct ahc_softc *ahc);
1212
1213/***************************** Error Recovery *********************************/
1214typedef enum {
1215 SEARCH_COMPLETE,
1216 SEARCH_COUNT,
1217 SEARCH_REMOVE
1218} ahc_search_action;
1219int ahc_search_qinfifo(struct ahc_softc *ahc, int target,
1220 char channel, int lun, u_int tag,
1221 role_t role, uint32_t status,
1222 ahc_search_action action);
1223int ahc_search_untagged_queues(struct ahc_softc *ahc,
1224 ahc_io_ctx_t ctx,
1225 int target, char channel,
1226 int lun, uint32_t status,
1227 ahc_search_action action);
1228int ahc_search_disc_list(struct ahc_softc *ahc, int target,
1229 char channel, int lun, u_int tag,
1230 int stop_on_first, int remove,
1231 int save_state);
1232void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb);
1233int ahc_reset_channel(struct ahc_softc *ahc, char channel,
1234 int initiate_reset);
1235int ahc_abort_scbs(struct ahc_softc *ahc, int target,
1236 char channel, int lun, u_int tag,
1237 role_t role, uint32_t status);
1238void ahc_restart(struct ahc_softc *ahc);
1239void ahc_calc_residual(struct ahc_softc *ahc,
1240 struct scb *scb);
1241/*************************** Utility Functions ********************************/
1242struct ahc_phase_table_entry*
1243 ahc_lookup_phase_entry(int phase);
1244void ahc_compile_devinfo(struct ahc_devinfo *devinfo,
1245 u_int our_id, u_int target,
1246 u_int lun, char channel,
1247 role_t role);
1248/************************** Transfer Negotiation ******************************/
1249struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1250 u_int *ppr_options, u_int maxsync);
1251u_int ahc_find_period(struct ahc_softc *ahc,
1252 u_int scsirate, u_int maxsync);
1253void ahc_validate_offset(struct ahc_softc *ahc,
1254 struct ahc_initiator_tinfo *tinfo,
1255 struct ahc_syncrate *syncrate,
1256 u_int *offset, int wide,
1257 role_t role);
1258void ahc_validate_width(struct ahc_softc *ahc,
1259 struct ahc_initiator_tinfo *tinfo,
1260 u_int *bus_width,
1261 role_t role);
1262/*
1263 * Negotiation types. These are used to qualify if we should renegotiate
1264 * even if our goal and current transport parameters are identical.
1265 */
1266typedef enum {
1267 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1268 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1269 AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */
1270} ahc_neg_type;
1271int ahc_update_neg_request(struct ahc_softc*,
1272 struct ahc_devinfo*,
1273 struct ahc_tmode_tstate*,
1274 struct ahc_initiator_tinfo*,
1275 ahc_neg_type);
1276void ahc_set_width(struct ahc_softc *ahc,
1277 struct ahc_devinfo *devinfo,
1278 u_int width, u_int type, int paused);
1279void ahc_set_syncrate(struct ahc_softc *ahc,
1280 struct ahc_devinfo *devinfo,
1281 struct ahc_syncrate *syncrate,
1282 u_int period, u_int offset,
1283 u_int ppr_options,
1284 u_int type, int paused);
1285typedef enum {
1286 AHC_QUEUE_NONE,
1287 AHC_QUEUE_BASIC,
1288 AHC_QUEUE_TAGGED
1289} ahc_queue_alg;
1290
1291void ahc_set_tags(struct ahc_softc *ahc,
1292 struct ahc_devinfo *devinfo,
1293 ahc_queue_alg alg);
1294
1295/**************************** Target Mode *************************************/
1296#ifdef AHC_TARGET_MODE
1297void ahc_send_lstate_events(struct ahc_softc *,
1298 struct ahc_tmode_lstate *);
1299void ahc_handle_en_lun(struct ahc_softc *ahc,
1300 struct cam_sim *sim, union ccb *ccb);
1301cam_status ahc_find_tmode_devs(struct ahc_softc *ahc,
1302 struct cam_sim *sim, union ccb *ccb,
1303 struct ahc_tmode_tstate **tstate,
1304 struct ahc_tmode_lstate **lstate,
1305 int notfound_failure);
1306#ifndef AHC_TMODE_ENABLE
1307#define AHC_TMODE_ENABLE 0
1308#endif
1309#endif
1310/******************************* Debug ***************************************/
1311#ifdef AHC_DEBUG
1312extern uint32_t ahc_debug;
1313#define AHC_SHOW_MISC 0x0001
1314#define AHC_SHOW_SENSE 0x0002
1315#define AHC_DUMP_SEEPROM 0x0004
1316#define AHC_SHOW_TERMCTL 0x0008
1317#define AHC_SHOW_MEMORY 0x0010
1318#define AHC_SHOW_MESSAGES 0x0020
1319#define AHC_SHOW_DV 0x0040
1320#define AHC_SHOW_SELTO 0x0080
1321#define AHC_SHOW_QFULL 0x0200
1322#define AHC_SHOW_QUEUE 0x0400
1323#define AHC_SHOW_TQIN 0x0800
1324#define AHC_SHOW_MASKED_ERRORS 0x1000
1325#define AHC_DEBUG_SEQUENCER 0x2000
1326#endif
1327void ahc_print_scb(struct scb *scb);
1328void ahc_print_devinfo(struct ahc_softc *ahc,
1329 struct ahc_devinfo *dev);
1330void ahc_dump_card_state(struct ahc_softc *ahc);
1331int ahc_print_register(ahc_reg_parse_entry_t *table,
1332 u_int num_entries,
1333 const char *name,
1334 u_int address,
1335 u_int value,
1336 u_int *cur_column,
1337 u_int wrap_point);
1338/******************************* SEEPROM *************************************/
1339int ahc_acquire_seeprom(struct ahc_softc *ahc,
1340 struct seeprom_descriptor *sd);
1341void ahc_release_seeprom(struct seeprom_descriptor *sd);
1342#endif /* _AIC7XXX_H_ */
Linux kernel - Deliverables
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