Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * DO NOT EDIT - This file is automatically generated | |
3 | * from the following source files: | |
4 | * | |
79778a27 JB |
5 | * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $ |
6 | * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $ | |
1da177e4 LT |
7 | */ |
8 | typedef int (ahc_reg_print_t)(u_int, u_int *, u_int); | |
9 | typedef struct ahc_reg_parse_entry { | |
10 | char *name; | |
11 | uint8_t value; | |
12 | uint8_t mask; | |
13 | } ahc_reg_parse_entry_t; | |
14 | ||
15 | #if AIC_DEBUG_REGISTERS | |
16 | ahc_reg_print_t ahc_scsiseq_print; | |
17 | #else | |
18 | #define ahc_scsiseq_print(regvalue, cur_col, wrap) \ | |
19 | ahc_print_register(NULL, 0, "SCSISEQ", 0x00, regvalue, cur_col, wrap) | |
20 | #endif | |
21 | ||
22 | #if AIC_DEBUG_REGISTERS | |
23 | ahc_reg_print_t ahc_sxfrctl0_print; | |
24 | #else | |
25 | #define ahc_sxfrctl0_print(regvalue, cur_col, wrap) \ | |
26 | ahc_print_register(NULL, 0, "SXFRCTL0", 0x01, regvalue, cur_col, wrap) | |
27 | #endif | |
28 | ||
1da177e4 LT |
29 | #if AIC_DEBUG_REGISTERS |
30 | ahc_reg_print_t ahc_scsisigi_print; | |
31 | #else | |
32 | #define ahc_scsisigi_print(regvalue, cur_col, wrap) \ | |
33 | ahc_print_register(NULL, 0, "SCSISIGI", 0x03, regvalue, cur_col, wrap) | |
34 | #endif | |
35 | ||
36 | #if AIC_DEBUG_REGISTERS | |
37 | ahc_reg_print_t ahc_scsirate_print; | |
38 | #else | |
39 | #define ahc_scsirate_print(regvalue, cur_col, wrap) \ | |
40 | ahc_print_register(NULL, 0, "SCSIRATE", 0x04, regvalue, cur_col, wrap) | |
41 | #endif | |
42 | ||
1da177e4 LT |
43 | #if AIC_DEBUG_REGISTERS |
44 | ahc_reg_print_t ahc_sstat0_print; | |
45 | #else | |
46 | #define ahc_sstat0_print(regvalue, cur_col, wrap) \ | |
47 | ahc_print_register(NULL, 0, "SSTAT0", 0x0b, regvalue, cur_col, wrap) | |
48 | #endif | |
49 | ||
1da177e4 LT |
50 | #if AIC_DEBUG_REGISTERS |
51 | ahc_reg_print_t ahc_sstat1_print; | |
52 | #else | |
53 | #define ahc_sstat1_print(regvalue, cur_col, wrap) \ | |
54 | ahc_print_register(NULL, 0, "SSTAT1", 0x0c, regvalue, cur_col, wrap) | |
55 | #endif | |
56 | ||
57 | #if AIC_DEBUG_REGISTERS | |
58 | ahc_reg_print_t ahc_sstat2_print; | |
59 | #else | |
60 | #define ahc_sstat2_print(regvalue, cur_col, wrap) \ | |
61 | ahc_print_register(NULL, 0, "SSTAT2", 0x0d, regvalue, cur_col, wrap) | |
62 | #endif | |
63 | ||
64 | #if AIC_DEBUG_REGISTERS | |
65 | ahc_reg_print_t ahc_sstat3_print; | |
66 | #else | |
67 | #define ahc_sstat3_print(regvalue, cur_col, wrap) \ | |
68 | ahc_print_register(NULL, 0, "SSTAT3", 0x0e, regvalue, cur_col, wrap) | |
69 | #endif | |
70 | ||
1da177e4 LT |
71 | #if AIC_DEBUG_REGISTERS |
72 | ahc_reg_print_t ahc_simode0_print; | |
73 | #else | |
74 | #define ahc_simode0_print(regvalue, cur_col, wrap) \ | |
75 | ahc_print_register(NULL, 0, "SIMODE0", 0x10, regvalue, cur_col, wrap) | |
76 | #endif | |
77 | ||
78 | #if AIC_DEBUG_REGISTERS | |
79 | ahc_reg_print_t ahc_simode1_print; | |
80 | #else | |
81 | #define ahc_simode1_print(regvalue, cur_col, wrap) \ | |
82 | ahc_print_register(NULL, 0, "SIMODE1", 0x11, regvalue, cur_col, wrap) | |
83 | #endif | |
84 | ||
85 | #if AIC_DEBUG_REGISTERS | |
86 | ahc_reg_print_t ahc_scsibusl_print; | |
87 | #else | |
88 | #define ahc_scsibusl_print(regvalue, cur_col, wrap) \ | |
89 | ahc_print_register(NULL, 0, "SCSIBUSL", 0x12, regvalue, cur_col, wrap) | |
90 | #endif | |
91 | ||
1da177e4 LT |
92 | #if AIC_DEBUG_REGISTERS |
93 | ahc_reg_print_t ahc_sblkctl_print; | |
94 | #else | |
95 | #define ahc_sblkctl_print(regvalue, cur_col, wrap) \ | |
96 | ahc_print_register(NULL, 0, "SBLKCTL", 0x1f, regvalue, cur_col, wrap) | |
97 | #endif | |
98 | ||
1da177e4 LT |
99 | #if AIC_DEBUG_REGISTERS |
100 | ahc_reg_print_t ahc_seq_flags_print; | |
101 | #else | |
102 | #define ahc_seq_flags_print(regvalue, cur_col, wrap) \ | |
103 | ahc_print_register(NULL, 0, "SEQ_FLAGS", 0x3c, regvalue, cur_col, wrap) | |
104 | #endif | |
105 | ||
1da177e4 LT |
106 | #if AIC_DEBUG_REGISTERS |
107 | ahc_reg_print_t ahc_lastphase_print; | |
108 | #else | |
109 | #define ahc_lastphase_print(regvalue, cur_col, wrap) \ | |
110 | ahc_print_register(NULL, 0, "LASTPHASE", 0x3f, regvalue, cur_col, wrap) | |
111 | #endif | |
112 | ||
1da177e4 LT |
113 | #if AIC_DEBUG_REGISTERS |
114 | ahc_reg_print_t ahc_seqctl_print; | |
115 | #else | |
116 | #define ahc_seqctl_print(regvalue, cur_col, wrap) \ | |
117 | ahc_print_register(NULL, 0, "SEQCTL", 0x60, regvalue, cur_col, wrap) | |
118 | #endif | |
119 | ||
1da177e4 LT |
120 | #if AIC_DEBUG_REGISTERS |
121 | ahc_reg_print_t ahc_sram_base_print; | |
122 | #else | |
123 | #define ahc_sram_base_print(regvalue, cur_col, wrap) \ | |
124 | ahc_print_register(NULL, 0, "SRAM_BASE", 0x70, regvalue, cur_col, wrap) | |
125 | #endif | |
126 | ||
1da177e4 LT |
127 | #if AIC_DEBUG_REGISTERS |
128 | ahc_reg_print_t ahc_error_print; | |
129 | #else | |
130 | #define ahc_error_print(regvalue, cur_col, wrap) \ | |
131 | ahc_print_register(NULL, 0, "ERROR", 0x92, regvalue, cur_col, wrap) | |
132 | #endif | |
133 | ||
134 | #if AIC_DEBUG_REGISTERS | |
135 | ahc_reg_print_t ahc_dfcntrl_print; | |
136 | #else | |
137 | #define ahc_dfcntrl_print(regvalue, cur_col, wrap) \ | |
138 | ahc_print_register(NULL, 0, "DFCNTRL", 0x93, regvalue, cur_col, wrap) | |
139 | #endif | |
140 | ||
141 | #if AIC_DEBUG_REGISTERS | |
142 | ahc_reg_print_t ahc_dfstatus_print; | |
143 | #else | |
144 | #define ahc_dfstatus_print(regvalue, cur_col, wrap) \ | |
145 | ahc_print_register(NULL, 0, "DFSTATUS", 0x94, regvalue, cur_col, wrap) | |
146 | #endif | |
147 | ||
1da177e4 LT |
148 | #if AIC_DEBUG_REGISTERS |
149 | ahc_reg_print_t ahc_scsiphase_print; | |
150 | #else | |
151 | #define ahc_scsiphase_print(regvalue, cur_col, wrap) \ | |
152 | ahc_print_register(NULL, 0, "SCSIPHASE", 0x9e, regvalue, cur_col, wrap) | |
153 | #endif | |
154 | ||
1da177e4 LT |
155 | #if AIC_DEBUG_REGISTERS |
156 | ahc_reg_print_t ahc_scb_base_print; | |
157 | #else | |
158 | #define ahc_scb_base_print(regvalue, cur_col, wrap) \ | |
159 | ahc_print_register(NULL, 0, "SCB_BASE", 0xa0, regvalue, cur_col, wrap) | |
160 | #endif | |
161 | ||
1da177e4 LT |
162 | #if AIC_DEBUG_REGISTERS |
163 | ahc_reg_print_t ahc_scb_control_print; | |
164 | #else | |
165 | #define ahc_scb_control_print(regvalue, cur_col, wrap) \ | |
166 | ahc_print_register(NULL, 0, "SCB_CONTROL", 0xb8, regvalue, cur_col, wrap) | |
167 | #endif | |
168 | ||
169 | #if AIC_DEBUG_REGISTERS | |
170 | ahc_reg_print_t ahc_scb_scsiid_print; | |
171 | #else | |
172 | #define ahc_scb_scsiid_print(regvalue, cur_col, wrap) \ | |
173 | ahc_print_register(NULL, 0, "SCB_SCSIID", 0xb9, regvalue, cur_col, wrap) | |
174 | #endif | |
175 | ||
176 | #if AIC_DEBUG_REGISTERS | |
177 | ahc_reg_print_t ahc_scb_lun_print; | |
178 | #else | |
179 | #define ahc_scb_lun_print(regvalue, cur_col, wrap) \ | |
180 | ahc_print_register(NULL, 0, "SCB_LUN", 0xba, regvalue, cur_col, wrap) | |
181 | #endif | |
182 | ||
183 | #if AIC_DEBUG_REGISTERS | |
184 | ahc_reg_print_t ahc_scb_tag_print; | |
185 | #else | |
186 | #define ahc_scb_tag_print(regvalue, cur_col, wrap) \ | |
187 | ahc_print_register(NULL, 0, "SCB_TAG", 0xbb, regvalue, cur_col, wrap) | |
188 | #endif | |
189 | ||
1da177e4 LT |
190 | |
191 | #define SCSISEQ 0x00 | |
192 | #define TEMODE 0x80 | |
193 | #define SCSIRSTO 0x01 | |
194 | ||
195 | #define SXFRCTL0 0x01 | |
196 | #define DFON 0x80 | |
197 | #define DFPEXP 0x40 | |
198 | #define FAST20 0x20 | |
199 | #define CLRSTCNT 0x10 | |
200 | #define SPIOEN 0x08 | |
201 | #define SCAMEN 0x04 | |
202 | #define CLRCHN 0x02 | |
203 | ||
204 | #define SXFRCTL1 0x02 | |
205 | #define STIMESEL 0x18 | |
206 | #define BITBUCKET 0x80 | |
207 | #define SWRAPEN 0x40 | |
208 | #define ENSTIMER 0x04 | |
209 | #define ACTNEGEN 0x02 | |
210 | #define STPWEN 0x01 | |
211 | ||
212 | #define SCSISIGO 0x03 | |
213 | #define CDO 0x80 | |
214 | #define IOO 0x40 | |
215 | #define MSGO 0x20 | |
216 | #define ATNO 0x10 | |
217 | #define SELO 0x08 | |
218 | #define BSYO 0x04 | |
219 | #define REQO 0x02 | |
220 | #define ACKO 0x01 | |
221 | ||
222 | #define SCSISIGI 0x03 | |
223 | #define P_DATAIN_DT 0x60 | |
224 | #define P_DATAOUT_DT 0x20 | |
225 | #define ATNI 0x10 | |
226 | #define SELI 0x08 | |
227 | #define BSYI 0x04 | |
228 | #define REQI 0x02 | |
229 | #define ACKI 0x01 | |
230 | ||
231 | #define SCSIRATE 0x04 | |
232 | #define SXFR 0x70 | |
233 | #define SOFS 0x0f | |
234 | #define SXFR_ULTRA2 0x0f | |
235 | #define WIDEXFER 0x80 | |
236 | #define ENABLE_CRC 0x40 | |
237 | #define SINGLE_EDGE 0x10 | |
238 | ||
239 | #define SCSIID 0x05 | |
240 | #define SCSIOFFSET 0x05 | |
241 | #define SOFS_ULTRA2 0x7f | |
242 | ||
243 | #define SCSIDATL 0x06 | |
244 | ||
245 | #define SCSIDATH 0x07 | |
246 | ||
247 | #define STCNT 0x08 | |
248 | ||
249 | #define OPTIONMODE 0x08 | |
250 | #define OPTIONMODE_DEFAULTS 0x03 | |
251 | #define AUTORATEEN 0x80 | |
252 | #define AUTOACKEN 0x40 | |
253 | #define ATNMGMNTEN 0x20 | |
254 | #define BUSFREEREV 0x10 | |
255 | #define EXPPHASEDIS 0x08 | |
256 | #define SCSIDATL_IMGEN 0x04 | |
257 | #define AUTO_MSGOUT_DE 0x02 | |
258 | #define DIS_MSGIN_DUALEDGE 0x01 | |
259 | ||
260 | #define TARGCRCCNT 0x0a | |
261 | ||
262 | #define CLRSINT0 0x0b | |
263 | #define CLRSELDO 0x40 | |
264 | #define CLRSELDI 0x20 | |
265 | #define CLRSELINGO 0x10 | |
266 | #define CLRIOERR 0x08 | |
267 | #define CLRSWRAP 0x08 | |
268 | #define CLRSPIORDY 0x02 | |
269 | ||
270 | #define SSTAT0 0x0b | |
271 | #define TARGET 0x80 | |
272 | #define SELDO 0x40 | |
273 | #define SELDI 0x20 | |
274 | #define SELINGO 0x10 | |
275 | #define SWRAP 0x08 | |
276 | #define IOERR 0x08 | |
277 | #define SDONE 0x04 | |
278 | #define SPIORDY 0x02 | |
279 | #define DMADONE 0x01 | |
280 | ||
281 | #define CLRSINT1 0x0c | |
282 | #define CLRSELTIMEO 0x80 | |
283 | #define CLRATNO 0x40 | |
284 | #define CLRSCSIRSTI 0x20 | |
285 | #define CLRBUSFREE 0x08 | |
286 | #define CLRSCSIPERR 0x04 | |
287 | #define CLRPHASECHG 0x02 | |
288 | #define CLRREQINIT 0x01 | |
289 | ||
290 | #define SSTAT1 0x0c | |
291 | #define SELTO 0x80 | |
292 | #define ATNTARG 0x40 | |
293 | #define SCSIRSTI 0x20 | |
294 | #define PHASEMIS 0x10 | |
295 | #define BUSFREE 0x08 | |
296 | #define SCSIPERR 0x04 | |
297 | #define PHASECHG 0x02 | |
298 | #define REQINIT 0x01 | |
299 | ||
300 | #define SSTAT2 0x0d | |
301 | #define SFCNT 0x1f | |
302 | #define OVERRUN 0x80 | |
303 | #define SHVALID 0x40 | |
304 | #define EXP_ACTIVE 0x10 | |
305 | #define CRCVALERR 0x08 | |
306 | #define CRCENDERR 0x04 | |
307 | #define CRCREQERR 0x02 | |
308 | #define DUAL_EDGE_ERR 0x01 | |
309 | ||
310 | #define SSTAT3 0x0e | |
311 | #define SCSICNT 0xf0 | |
312 | #define U2OFFCNT 0x7f | |
313 | #define OFFCNT 0x0f | |
314 | ||
315 | #define SCSIID_ULTRA2 0x0f | |
316 | ||
317 | #define SIMODE0 0x10 | |
318 | #define ENSELDO 0x40 | |
319 | #define ENSELDI 0x20 | |
320 | #define ENSELINGO 0x10 | |
321 | #define ENIOERR 0x08 | |
322 | #define ENSWRAP 0x08 | |
323 | #define ENSDONE 0x04 | |
324 | #define ENSPIORDY 0x02 | |
325 | #define ENDMADONE 0x01 | |
326 | ||
327 | #define SIMODE1 0x11 | |
328 | #define ENSELTIMO 0x80 | |
329 | #define ENATNTARG 0x40 | |
330 | #define ENSCSIRST 0x20 | |
331 | #define ENPHASEMIS 0x10 | |
332 | #define ENBUSFREE 0x08 | |
333 | #define ENSCSIPERR 0x04 | |
334 | #define ENPHASECHG 0x02 | |
335 | #define ENREQINIT 0x01 | |
336 | ||
337 | #define SCSIBUSL 0x12 | |
338 | ||
339 | #define SCSIBUSH 0x13 | |
340 | ||
341 | #define SXFRCTL2 0x13 | |
342 | #define ASYNC_SETUP 0x07 | |
343 | #define AUTORSTDIS 0x10 | |
344 | #define CMDDMAEN 0x08 | |
345 | ||
346 | #define SHADDR 0x14 | |
347 | ||
348 | #define SELTIMER 0x18 | |
349 | #define TARGIDIN 0x18 | |
350 | #define STAGE6 0x20 | |
351 | #define STAGE5 0x10 | |
352 | #define STAGE4 0x08 | |
353 | #define STAGE3 0x04 | |
354 | #define STAGE2 0x02 | |
355 | #define STAGE1 0x01 | |
356 | ||
357 | #define SELID 0x19 | |
358 | #define SELID_MASK 0xf0 | |
359 | #define ONEBIT 0x08 | |
360 | ||
361 | #define SCAMCTL 0x1a | |
362 | #define SCAMLVL 0x03 | |
363 | #define ENSCAMSELO 0x80 | |
364 | #define CLRSCAMSELID 0x40 | |
365 | #define ALTSTIM 0x20 | |
366 | #define DFLTTID 0x10 | |
367 | ||
368 | #define TARGID 0x1b | |
369 | ||
370 | #define SPIOCAP 0x1b | |
371 | #define SOFT1 0x80 | |
372 | #define SOFT0 0x40 | |
373 | #define SOFTCMDEN 0x20 | |
374 | #define EXT_BRDCTL 0x10 | |
375 | #define SEEPROM 0x08 | |
376 | #define EEPROM 0x04 | |
377 | #define ROM 0x02 | |
378 | #define SSPIOCPS 0x01 | |
379 | ||
380 | #define BRDCTL 0x1d | |
381 | #define BRDDAT7 0x80 | |
382 | #define BRDDAT6 0x40 | |
383 | #define BRDDAT5 0x20 | |
384 | #define BRDDAT4 0x10 | |
385 | #define BRDSTB 0x10 | |
386 | #define BRDDAT3 0x08 | |
387 | #define BRDCS 0x08 | |
388 | #define BRDDAT2 0x04 | |
389 | #define BRDRW 0x04 | |
390 | #define BRDRW_ULTRA2 0x02 | |
391 | #define BRDCTL1 0x02 | |
392 | #define BRDCTL0 0x01 | |
393 | #define BRDSTB_ULTRA2 0x01 | |
394 | ||
395 | #define SEECTL 0x1e | |
396 | #define EXTARBACK 0x80 | |
397 | #define EXTARBREQ 0x40 | |
398 | #define SEEMS 0x20 | |
399 | #define SEERDY 0x10 | |
400 | #define SEECS 0x08 | |
401 | #define SEECK 0x04 | |
402 | #define SEEDO 0x02 | |
403 | #define SEEDI 0x01 | |
404 | ||
405 | #define SBLKCTL 0x1f | |
406 | #define DIAGLEDEN 0x80 | |
407 | #define DIAGLEDON 0x40 | |
408 | #define AUTOFLUSHDIS 0x20 | |
409 | #define ENAB40 0x08 | |
410 | #define SELBUSB 0x08 | |
411 | #define ENAB20 0x04 | |
412 | #define SELWIDE 0x02 | |
413 | #define XCVR 0x01 | |
414 | ||
415 | #define BUSY_TARGETS 0x20 | |
416 | #define TARG_SCSIRATE 0x20 | |
417 | ||
418 | #define ULTRA_ENB 0x30 | |
419 | #define CMDSIZE_TABLE 0x30 | |
420 | ||
421 | #define DISC_DSB 0x32 | |
422 | ||
423 | #define CMDSIZE_TABLE_TAIL 0x34 | |
424 | ||
425 | #define MWI_RESIDUAL 0x38 | |
1da177e4 LT |
426 | |
427 | #define NEXT_QUEUED_SCB 0x39 | |
428 | ||
429 | #define MSG_OUT 0x3a | |
430 | ||
431 | #define DMAPARAMS 0x3b | |
432 | #define PRELOADEN 0x80 | |
433 | #define WIDEODD 0x40 | |
434 | #define SCSIEN 0x20 | |
435 | #define SDMAEN 0x10 | |
436 | #define SDMAENACK 0x10 | |
437 | #define HDMAEN 0x08 | |
438 | #define HDMAENACK 0x08 | |
439 | #define DIRECTION 0x04 | |
440 | #define FIFOFLUSH 0x02 | |
441 | #define FIFORESET 0x01 | |
442 | ||
443 | #define SEQ_FLAGS 0x3c | |
444 | #define NOT_IDENTIFIED 0x80 | |
445 | #define NO_CDB_SENT 0x40 | |
446 | #define TARGET_CMD_IS_TAGGED 0x40 | |
447 | #define DPHASE 0x20 | |
448 | #define TARG_CMD_PENDING 0x10 | |
449 | #define CMDPHASE_PENDING 0x08 | |
450 | #define DPHASE_PENDING 0x04 | |
451 | #define SPHASE_PENDING 0x02 | |
452 | #define NO_DISCONNECT 0x01 | |
453 | ||
454 | #define SAVED_SCSIID 0x3d | |
455 | ||
456 | #define SAVED_LUN 0x3e | |
457 | ||
458 | #define LASTPHASE 0x3f | |
459 | #define P_MESGIN 0xe0 | |
460 | #define PHASE_MASK 0xe0 | |
461 | #define P_STATUS 0xc0 | |
462 | #define P_MESGOUT 0xa0 | |
463 | #define P_COMMAND 0x80 | |
464 | #define P_DATAIN 0x40 | |
465 | #define P_BUSFREE 0x01 | |
466 | #define P_DATAOUT 0x00 | |
467 | #define CDI 0x80 | |
468 | #define IOI 0x40 | |
469 | #define MSGI 0x20 | |
470 | ||
471 | #define WAITING_SCBH 0x40 | |
472 | ||
473 | #define DISCONNECTED_SCBH 0x41 | |
474 | ||
475 | #define FREE_SCBH 0x42 | |
476 | ||
477 | #define COMPLETE_SCBH 0x43 | |
478 | ||
479 | #define HSCB_ADDR 0x44 | |
480 | ||
481 | #define SHARED_DATA_ADDR 0x48 | |
482 | ||
483 | #define KERNEL_QINPOS 0x4c | |
484 | ||
485 | #define QINPOS 0x4d | |
486 | ||
487 | #define QOUTPOS 0x4e | |
488 | ||
489 | #define KERNEL_TQINPOS 0x4f | |
490 | ||
491 | #define TQINPOS 0x50 | |
492 | ||
493 | #define ARG_1 0x51 | |
494 | #define RETURN_1 0x51 | |
495 | #define SEND_MSG 0x80 | |
496 | #define SEND_SENSE 0x40 | |
497 | #define SEND_REJ 0x20 | |
498 | #define MSGOUT_PHASEMIS 0x10 | |
499 | #define EXIT_MSG_LOOP 0x08 | |
500 | #define CONT_MSG_LOOP 0x04 | |
501 | #define CONT_TARG_SESSION 0x02 | |
502 | ||
503 | #define ARG_2 0x52 | |
504 | #define RETURN_2 0x52 | |
505 | ||
506 | #define LAST_MSG 0x53 | |
79778a27 | 507 | #define TARG_IMMEDIATE_SCB 0x53 |
1da177e4 LT |
508 | |
509 | #define SCSISEQ_TEMPLATE 0x54 | |
510 | #define ENSELO 0x40 | |
511 | #define ENSELI 0x20 | |
512 | #define ENRSELI 0x10 | |
513 | #define ENAUTOATNO 0x08 | |
514 | #define ENAUTOATNI 0x04 | |
515 | #define ENAUTOATNP 0x02 | |
516 | ||
517 | #define HA_274_BIOSGLOBAL 0x56 | |
518 | #define INITIATOR_TAG 0x56 | |
519 | #define HA_274_EXTENDED_TRANS 0x01 | |
520 | ||
521 | #define SEQ_FLAGS2 0x57 | |
522 | #define TARGET_MSG_PENDING 0x02 | |
523 | #define SCB_DMA 0x01 | |
524 | ||
525 | #define SCSICONF 0x5a | |
526 | #define HWSCSIID 0x0f | |
527 | #define HSCSIID 0x07 | |
528 | #define TERM_ENB 0x80 | |
529 | #define RESET_SCSI 0x40 | |
530 | #define ENSPCHK 0x20 | |
531 | ||
532 | #define INTDEF 0x5c | |
533 | #define VECTOR 0x0f | |
534 | #define EDGE_TRIG 0x80 | |
535 | ||
536 | #define HOSTCONF 0x5d | |
537 | ||
538 | #define HA_274_BIOSCTRL 0x5f | |
539 | #define BIOSDISABLED 0x30 | |
540 | #define BIOSMODE 0x30 | |
541 | #define CHANNEL_B_PRIMARY 0x08 | |
542 | ||
543 | #define SEQCTL 0x60 | |
544 | #define PERRORDIS 0x80 | |
545 | #define PAUSEDIS 0x40 | |
546 | #define FAILDIS 0x20 | |
547 | #define FASTMODE 0x10 | |
548 | #define BRKADRINTEN 0x08 | |
549 | #define STEP 0x04 | |
550 | #define SEQRESET 0x02 | |
551 | #define LOADRAM 0x01 | |
552 | ||
553 | #define SEQRAM 0x61 | |
554 | ||
555 | #define SEQADDR0 0x62 | |
556 | ||
557 | #define SEQADDR1 0x63 | |
558 | #define SEQADDR1_MASK 0x01 | |
559 | ||
560 | #define ACCUM 0x64 | |
561 | ||
562 | #define SINDEX 0x65 | |
563 | ||
564 | #define DINDEX 0x66 | |
565 | ||
566 | #define ALLONES 0x69 | |
567 | ||
568 | #define ALLZEROS 0x6a | |
569 | ||
570 | #define NONE 0x6a | |
571 | ||
572 | #define FLAGS 0x6b | |
573 | #define ZERO 0x02 | |
574 | #define CARRY 0x01 | |
575 | ||
576 | #define SINDIR 0x6c | |
577 | ||
578 | #define DINDIR 0x6d | |
579 | ||
580 | #define FUNCTION1 0x6e | |
581 | ||
582 | #define STACK 0x6f | |
583 | ||
584 | #define TARG_OFFSET 0x70 | |
585 | ||
586 | #define SRAM_BASE 0x70 | |
587 | ||
588 | #define BCTL 0x84 | |
589 | #define ACE 0x08 | |
590 | #define ENABLE 0x01 | |
591 | ||
592 | #define DSCOMMAND0 0x84 | |
593 | #define CACHETHEN 0x80 | |
594 | #define DPARCKEN 0x40 | |
595 | #define MPARCKEN 0x20 | |
596 | #define EXTREQLCK 0x10 | |
597 | #define INTSCBRAMSEL 0x08 | |
598 | #define RAMPS 0x04 | |
599 | #define USCBSIZE32 0x02 | |
600 | #define CIOPARCKEN 0x01 | |
601 | ||
602 | #define BUSTIME 0x85 | |
603 | #define BOFF 0xf0 | |
604 | #define BON 0x0f | |
605 | ||
606 | #define DSCOMMAND1 0x85 | |
607 | #define DSLATT 0xfc | |
608 | #define HADDLDSEL1 0x02 | |
609 | #define HADDLDSEL0 0x01 | |
610 | ||
611 | #define BUSSPD 0x86 | |
612 | #define DFTHRSH 0xc0 | |
613 | #define DFTHRSH_75 0x80 | |
614 | #define STBOFF 0x38 | |
615 | #define STBON 0x07 | |
616 | ||
617 | #define HS_MAILBOX 0x86 | |
618 | #define HOST_MAILBOX 0xf0 | |
619 | #define HOST_TQINPOS 0x80 | |
620 | #define SEQ_MAILBOX 0x0f | |
621 | ||
622 | #define DSPCISTATUS 0x86 | |
623 | #define DFTHRSH_100 0xc0 | |
624 | ||
625 | #define HCNTRL 0x87 | |
626 | #define POWRDN 0x40 | |
627 | #define SWINT 0x10 | |
628 | #define IRQMS 0x08 | |
629 | #define PAUSE 0x04 | |
630 | #define INTEN 0x02 | |
631 | #define CHIPRST 0x01 | |
632 | #define CHIPRSTACK 0x01 | |
633 | ||
634 | #define HADDR 0x88 | |
635 | ||
636 | #define HCNT 0x8c | |
637 | ||
638 | #define SCBPTR 0x90 | |
639 | ||
640 | #define INTSTAT 0x91 | |
641 | #define SEQINT_MASK 0xf1 | |
642 | #define OUT_OF_RANGE 0xe1 | |
643 | #define NO_FREE_SCB 0xd1 | |
644 | #define SCB_MISMATCH 0xc1 | |
645 | #define MISSED_BUSFREE 0xb1 | |
646 | #define MKMSG_FAILED 0xa1 | |
647 | #define DATA_OVERRUN 0x91 | |
648 | #define PERR_DETECTED 0x81 | |
649 | #define BAD_STATUS 0x71 | |
650 | #define HOST_MSG_LOOP 0x61 | |
651 | #define PDATA_REINIT 0x51 | |
652 | #define IGN_WIDE_RES 0x41 | |
653 | #define NO_MATCH 0x31 | |
654 | #define PROTO_VIOLATION 0x21 | |
655 | #define SEND_REJECT 0x11 | |
656 | #define INT_PEND 0x0f | |
657 | #define BAD_PHASE 0x01 | |
658 | #define BRKADRINT 0x08 | |
659 | #define SCSIINT 0x04 | |
660 | #define CMDCMPLT 0x02 | |
661 | #define SEQINT 0x01 | |
662 | ||
663 | #define CLRINT 0x92 | |
664 | #define CLRPARERR 0x10 | |
665 | #define CLRBRKADRINT 0x08 | |
666 | #define CLRSCSIINT 0x04 | |
667 | #define CLRCMDINT 0x02 | |
668 | #define CLRSEQINT 0x01 | |
669 | ||
670 | #define ERROR 0x92 | |
671 | #define CIOPARERR 0x80 | |
672 | #define PCIERRSTAT 0x40 | |
673 | #define MPARERR 0x20 | |
674 | #define DPARERR 0x10 | |
675 | #define SQPARERR 0x08 | |
676 | #define ILLOPCODE 0x04 | |
677 | #define ILLSADDR 0x02 | |
678 | #define ILLHADDR 0x01 | |
679 | ||
680 | #define DFCNTRL 0x93 | |
681 | ||
682 | #define DFSTATUS 0x94 | |
683 | #define PRELOAD_AVAIL 0x80 | |
684 | #define DFCACHETH 0x40 | |
685 | #define FIFOQWDEMP 0x20 | |
686 | #define MREQPEND 0x10 | |
687 | #define HDONE 0x08 | |
688 | #define DFTHRESH 0x04 | |
689 | #define FIFOFULL 0x02 | |
690 | #define FIFOEMP 0x01 | |
691 | ||
692 | #define DFWADDR 0x95 | |
693 | ||
694 | #define DFRADDR 0x97 | |
695 | ||
696 | #define DFDAT 0x99 | |
697 | ||
698 | #define SCBCNT 0x9a | |
699 | #define SCBCNT_MASK 0x1f | |
700 | #define SCBAUTO 0x80 | |
701 | ||
702 | #define QINFIFO 0x9b | |
703 | ||
704 | #define QINCNT 0x9c | |
705 | ||
706 | #define QOUTFIFO 0x9d | |
707 | ||
708 | #define CRCCONTROL1 0x9d | |
709 | #define CRCONSEEN 0x80 | |
710 | #define CRCVALCHKEN 0x40 | |
711 | #define CRCENDCHKEN 0x20 | |
712 | #define CRCREQCHKEN 0x10 | |
713 | #define TARGCRCENDEN 0x08 | |
714 | #define TARGCRCCNTEN 0x04 | |
715 | ||
716 | #define QOUTCNT 0x9e | |
717 | ||
718 | #define SCSIPHASE 0x9e | |
719 | #define DATA_PHASE_MASK 0x03 | |
720 | #define STATUS_PHASE 0x20 | |
721 | #define COMMAND_PHASE 0x10 | |
722 | #define MSG_IN_PHASE 0x08 | |
723 | #define MSG_OUT_PHASE 0x04 | |
724 | #define DATA_IN_PHASE 0x02 | |
725 | #define DATA_OUT_PHASE 0x01 | |
726 | ||
727 | #define SFUNCT 0x9f | |
728 | #define ALT_MODE 0x80 | |
729 | ||
730 | #define SCB_BASE 0xa0 | |
731 | ||
732 | #define SCB_CDB_PTR 0xa0 | |
733 | #define SCB_RESIDUAL_DATACNT 0xa0 | |
734 | #define SCB_CDB_STORE 0xa0 | |
735 | ||
736 | #define SCB_RESIDUAL_SGPTR 0xa4 | |
737 | ||
738 | #define SCB_SCSI_STATUS 0xa8 | |
739 | ||
740 | #define SCB_TARGET_PHASES 0xa9 | |
741 | ||
742 | #define SCB_TARGET_DATA_DIR 0xaa | |
743 | ||
744 | #define SCB_TARGET_ITAG 0xab | |
745 | ||
746 | #define SCB_DATAPTR 0xac | |
747 | ||
748 | #define SCB_DATACNT 0xb0 | |
749 | #define SG_HIGH_ADDR_BITS 0x7f | |
750 | #define SG_LAST_SEG 0x80 | |
751 | ||
752 | #define SCB_SGPTR 0xb4 | |
753 | #define SG_RESID_VALID 0x04 | |
754 | #define SG_FULL_RESID 0x02 | |
755 | #define SG_LIST_NULL 0x01 | |
756 | ||
757 | #define SCB_CONTROL 0xb8 | |
758 | #define SCB_TAG_TYPE 0x03 | |
759 | #define STATUS_RCVD 0x80 | |
760 | #define TARGET_SCB 0x80 | |
761 | #define DISCENB 0x40 | |
762 | #define TAG_ENB 0x20 | |
763 | #define MK_MESSAGE 0x10 | |
764 | #define ULTRAENB 0x08 | |
765 | #define DISCONNECTED 0x04 | |
766 | ||
767 | #define SCB_SCSIID 0xb9 | |
768 | #define TID 0xf0 | |
769 | #define TWIN_TID 0x70 | |
770 | #define OID 0x0f | |
771 | #define TWIN_CHNLB 0x80 | |
772 | ||
773 | #define SCB_LUN 0xba | |
774 | #define LID 0x3f | |
775 | #define SCB_XFERLEN_ODD 0x80 | |
776 | ||
777 | #define SCB_TAG 0xbb | |
778 | ||
779 | #define SCB_CDB_LEN 0xbc | |
780 | ||
781 | #define SCB_SCSIRATE 0xbd | |
782 | ||
783 | #define SCB_SCSIOFFSET 0xbe | |
784 | ||
785 | #define SCB_NEXT 0xbf | |
786 | ||
787 | #define SCB_64_SPARE 0xc0 | |
788 | ||
789 | #define SEECTL_2840 0xc0 | |
790 | #define CS_2840 0x04 | |
791 | #define CK_2840 0x02 | |
792 | #define DO_2840 0x01 | |
793 | ||
794 | #define STATUS_2840 0xc1 | |
795 | #define BIOS_SEL 0x60 | |
796 | #define ADSEL 0x1e | |
797 | #define EEPROM_TF 0x80 | |
798 | #define DI_2840 0x01 | |
799 | ||
800 | #define SCB_64_BTT 0xd0 | |
801 | ||
802 | #define CCHADDR 0xe0 | |
803 | ||
804 | #define CCHCNT 0xe8 | |
805 | ||
806 | #define CCSGRAM 0xe9 | |
807 | ||
808 | #define CCSGADDR 0xea | |
809 | ||
810 | #define CCSGCTL 0xeb | |
811 | #define CCSGDONE 0x80 | |
812 | #define CCSGEN 0x08 | |
813 | #define SG_FETCH_NEEDED 0x02 | |
814 | #define CCSGRESET 0x01 | |
815 | ||
816 | #define CCSCBRAM 0xec | |
817 | ||
818 | #define CCSCBADDR 0xed | |
819 | ||
820 | #define CCSCBCTL 0xee | |
821 | #define CCSCBDONE 0x80 | |
822 | #define ARRDONE 0x40 | |
823 | #define CCARREN 0x10 | |
824 | #define CCSCBEN 0x08 | |
825 | #define CCSCBDIR 0x04 | |
826 | #define CCSCBRESET 0x01 | |
827 | ||
828 | #define CCSCBCNT 0xef | |
829 | ||
830 | #define SCBBADDR 0xf0 | |
831 | ||
832 | #define CCSCBPTR 0xf1 | |
833 | ||
834 | #define HNSCB_QOFF 0xf4 | |
835 | ||
836 | #define SNSCB_QOFF 0xf6 | |
837 | ||
838 | #define SDSCB_QOFF 0xf8 | |
839 | ||
840 | #define QOFF_CTLSTA 0xfa | |
841 | #define SCB_QSIZE 0x07 | |
842 | #define SCB_QSIZE_256 0x06 | |
843 | #define SCB_AVAIL 0x40 | |
844 | #define SNSCB_ROLLOVER 0x20 | |
845 | #define SDSCB_ROLLOVER 0x10 | |
846 | ||
847 | #define DFF_THRSH 0xfb | |
848 | #define WR_DFTHRSH 0x70 | |
849 | #define WR_DFTHRSH_MAX 0x70 | |
850 | #define WR_DFTHRSH_90 0x60 | |
851 | #define WR_DFTHRSH_85 0x50 | |
852 | #define WR_DFTHRSH_75 0x40 | |
853 | #define WR_DFTHRSH_63 0x30 | |
854 | #define WR_DFTHRSH_50 0x20 | |
855 | #define WR_DFTHRSH_25 0x10 | |
856 | #define RD_DFTHRSH 0x07 | |
857 | #define RD_DFTHRSH_MAX 0x07 | |
858 | #define RD_DFTHRSH_90 0x06 | |
859 | #define RD_DFTHRSH_85 0x05 | |
860 | #define RD_DFTHRSH_75 0x04 | |
861 | #define RD_DFTHRSH_63 0x03 | |
862 | #define RD_DFTHRSH_50 0x02 | |
863 | #define RD_DFTHRSH_25 0x01 | |
864 | #define RD_DFTHRSH_MIN 0x00 | |
865 | #define WR_DFTHRSH_MIN 0x00 | |
866 | ||
867 | #define SG_CACHE_SHADOW 0xfc | |
868 | #define SG_ADDR_MASK 0xf8 | |
869 | #define LAST_SEG 0x02 | |
870 | #define LAST_SEG_DONE 0x01 | |
871 | ||
872 | #define SG_CACHE_PRE 0xfc | |
873 | ||
874 | ||
875 | #define MAX_OFFSET_ULTRA2 0x7f | |
876 | #define MAX_OFFSET_16BIT 0x08 | |
877 | #define BUS_8_BIT 0x00 | |
878 | #define TARGET_CMD_CMPLT 0xfe | |
879 | #define STATUS_QUEUE_FULL 0x28 | |
880 | #define STATUS_BUSY 0x08 | |
881 | #define MAX_OFFSET_8BIT 0x0f | |
882 | #define BUS_32_BIT 0x02 | |
883 | #define CCSGADDR_MAX 0x80 | |
884 | #define TID_SHIFT 0x04 | |
885 | #define SCB_DOWNLOAD_SIZE_64 0x30 | |
886 | #define HOST_MAILBOX_SHIFT 0x04 | |
887 | #define CMD_GROUP_CODE_SHIFT 0x05 | |
888 | #define CCSGRAM_MAXSEGS 0x10 | |
889 | #define SCB_LIST_NULL 0xff | |
890 | #define SG_SIZEOF 0x08 | |
891 | #define SCB_DOWNLOAD_SIZE 0x20 | |
892 | #define SEQ_MAILBOX_SHIFT 0x00 | |
893 | #define TARGET_DATA_IN 0x01 | |
894 | #define HOST_MSG 0xff | |
895 | #define MAX_OFFSET 0x7f | |
896 | #define BUS_16_BIT 0x01 | |
897 | #define SCB_UPLOAD_SIZE 0x20 | |
898 | #define STACK_SIZE 0x04 | |
899 | ||
900 | ||
901 | /* Downloaded Constant Definitions */ | |
902 | #define INVERTED_CACHESIZE_MASK 0x03 | |
903 | #define SG_PREFETCH_ADDR_MASK 0x06 | |
904 | #define SG_PREFETCH_ALIGN_MASK 0x05 | |
905 | #define QOUTFIFO_OFFSET 0x00 | |
906 | #define SG_PREFETCH_CNT 0x04 | |
907 | #define CACHESIZE_MASK 0x02 | |
908 | #define QINFIFO_OFFSET 0x01 | |
909 | #define DOWNLOAD_CONST_COUNT 0x07 | |
910 | ||
911 | ||
912 | /* Exported Labels */ |