[deliverable/linux.git] / drivers / scsi / am53c974.c

/*
 * AMD am53c974 driver.
 * Copyright (c) 2014 Hannes Reinecke, SUSE Linux GmbH
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/interrupt.h>

#include <scsi/scsi_host.h>

#include "esp_scsi.h"

#define DRV_MODULE_NAME "am53c974"
#define DRV_MODULE_VERSION "1.00"

static bool am53c974_debug;

#define esp_dma_log(f, a...)						\
	do {								\
		if (am53c974_debug)					\
			shost_printk(KERN_DEBUG, esp->host, f, ##a);	\
	} while (0)

#define ESP_DMA_CMD 0x10
#define ESP_DMA_STC 0x11
#define ESP_DMA_SPA 0x12
#define ESP_DMA_WBC 0x13
#define ESP_DMA_WAC 0x14
#define ESP_DMA_STATUS 0x15
#define ESP_DMA_SMDLA 0x16
#define ESP_DMA_WMAC 0x17

#define ESP_DMA_CMD_IDLE 0x00
#define ESP_DMA_CMD_BLAST 0x01
#define ESP_DMA_CMD_ABORT 0x02
#define ESP_DMA_CMD_START 0x03
#define ESP_DMA_CMD_MASK  0x03
#define ESP_DMA_CMD_DIAG 0x04
#define ESP_DMA_CMD_MDL 0x10
#define ESP_DMA_CMD_INTE_P 0x20
#define ESP_DMA_CMD_INTE_D 0x40
#define ESP_DMA_CMD_DIR 0x80

#define ESP_DMA_STAT_PWDN 0x01
#define ESP_DMA_STAT_ERROR 0x02
#define ESP_DMA_STAT_ABORT 0x04
#define ESP_DMA_STAT_DONE 0x08
#define ESP_DMA_STAT_SCSIINT 0x10
#define ESP_DMA_STAT_BCMPLT 0x20

/* EEPROM is accessed with 16-bit values */
#define DC390_EEPROM_READ 0x80
#define DC390_EEPROM_LEN 0x40

/*
 * DC390 EEPROM
 *
 * 8 * 4 bytes of per-device options
 * followed by HBA specific options
 */

/* Per-device options */
#define DC390_EE_MODE1 0x00
#define DC390_EE_SPEED 0x01

/* HBA-specific options */
#define DC390_EE_ADAPT_SCSI_ID 0x40
#define DC390_EE_MODE2 0x41
#define DC390_EE_DELAY 0x42
#define DC390_EE_TAG_CMD_NUM 0x43

#define DC390_EE_MODE1_PARITY_CHK   0x01
#define DC390_EE_MODE1_SYNC_NEGO    0x02
#define DC390_EE_MODE1_EN_DISC      0x04
#define DC390_EE_MODE1_SEND_START   0x08
#define DC390_EE_MODE1_TCQ          0x10

#define DC390_EE_MODE2_MORE_2DRV    0x01
#define DC390_EE_MODE2_GREATER_1G   0x02
#define DC390_EE_MODE2_RST_SCSI_BUS 0x04
#define DC390_EE_MODE2_ACTIVE_NEGATION 0x08
#define DC390_EE_MODE2_NO_SEEK      0x10
#define DC390_EE_MODE2_LUN_CHECK    0x20

struct pci_esp_priv {
	struct esp *esp;
	u8 dma_status;
};

static void pci_esp_dma_drain(struct esp *esp);

static inline struct pci_esp_priv *pci_esp_get_priv(struct esp *esp)
{
	struct pci_dev *pdev = esp->dev;

	return pci_get_drvdata(pdev);
}

static void pci_esp_write8(struct esp *esp, u8 val, unsigned long reg)
{
	iowrite8(val, esp->regs + (reg * 4UL));
}

static u8 pci_esp_read8(struct esp *esp, unsigned long reg)
{
	return ioread8(esp->regs + (reg * 4UL));
}

static void pci_esp_write32(struct esp *esp, u32 val, unsigned long reg)
{
	return iowrite32(val, esp->regs + (reg * 4UL));
}

static dma_addr_t pci_esp_map_single(struct esp *esp, void *buf,
				     size_t sz, int dir)
{
	return pci_map_single(esp->dev, buf, sz, dir);
}

static int pci_esp_map_sg(struct esp *esp, struct scatterlist *sg,
			  int num_sg, int dir)
{
	return pci_map_sg(esp->dev, sg, num_sg, dir);
}

static void pci_esp_unmap_single(struct esp *esp, dma_addr_t addr,
				 size_t sz, int dir)
{
	pci_unmap_single(esp->dev, addr, sz, dir);
}

static void pci_esp_unmap_sg(struct esp *esp, struct scatterlist *sg,
			     int num_sg, int dir)
{
	pci_unmap_sg(esp->dev, sg, num_sg, dir);
}

static int pci_esp_irq_pending(struct esp *esp)
{
	struct pci_esp_priv *pep = pci_esp_get_priv(esp);

	pep->dma_status = pci_esp_read8(esp, ESP_DMA_STATUS);
	esp_dma_log("dma intr dreg[%02x]\n", pep->dma_status);

	if (pep->dma_status & (ESP_DMA_STAT_ERROR |
			       ESP_DMA_STAT_ABORT |
			       ESP_DMA_STAT_DONE |
			       ESP_DMA_STAT_SCSIINT))
		return 1;

	return 0;
}

static void pci_esp_reset_dma(struct esp *esp)
{
	/* Nothing to do ? */
}

static void pci_esp_dma_drain(struct esp *esp)
{
	u8 resid;
	int lim = 1000;


	if ((esp->sreg & ESP_STAT_PMASK) == ESP_DOP ||
	    (esp->sreg & ESP_STAT_PMASK) == ESP_DIP)
		/* Data-In or Data-Out, nothing to be done */
		return;

	while (--lim > 0) {
		resid = pci_esp_read8(esp, ESP_FFLAGS) & ESP_FF_FBYTES;
		if (resid <= 1)
			break;
		cpu_relax();
	}
	if (resid > 1) {
		/* FIFO not cleared */
		shost_printk(KERN_INFO, esp->host,
			     "FIFO not cleared, %d bytes left\n",
			     resid);
	}

	/*
	 * When there is a residual BCMPLT will never be set
	 * (obviously). But we still have to issue the BLAST
	 * command, otherwise the data will not being transferred.
	 * But we'll never know when the BLAST operation is
	 * finished. So check for some time and give up eventually.
	 */
	lim = 1000;
	pci_esp_write8(esp, ESP_DMA_CMD_DIR | ESP_DMA_CMD_BLAST, ESP_DMA_CMD);
	while (pci_esp_read8(esp, ESP_DMA_STATUS) & ESP_DMA_STAT_BCMPLT) {
		if (--lim == 0)
			break;
		cpu_relax();
	}
	pci_esp_write8(esp, ESP_DMA_CMD_DIR | ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
	esp_dma_log("DMA blast done (%d tries, %d bytes left)\n", lim, resid);
	/* BLAST residual handling is currently untested */
	if (WARN_ON_ONCE(resid == 1)) {
		struct esp_cmd_entry *ent = esp->active_cmd;

		ent->flags |= ESP_CMD_FLAG_RESIDUAL;
	}
}

static void pci_esp_dma_invalidate(struct esp *esp)
{
	struct pci_esp_priv *pep = pci_esp_get_priv(esp);

	esp_dma_log("invalidate DMA\n");

	pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
	pep->dma_status = 0;
}

static int pci_esp_dma_error(struct esp *esp)
{
	struct pci_esp_priv *pep = pci_esp_get_priv(esp);

	if (pep->dma_status & ESP_DMA_STAT_ERROR) {
		u8 dma_cmd = pci_esp_read8(esp, ESP_DMA_CMD);

		if ((dma_cmd & ESP_DMA_CMD_MASK) == ESP_DMA_CMD_START)
			pci_esp_write8(esp, ESP_DMA_CMD_ABORT, ESP_DMA_CMD);

		return 1;
	}
	if (pep->dma_status & ESP_DMA_STAT_ABORT) {
		pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
		pep->dma_status = pci_esp_read8(esp, ESP_DMA_CMD);
		return 1;
	}
	return 0;
}

static void pci_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
				 u32 dma_count, int write, u8 cmd)
{
	struct pci_esp_priv *pep = pci_esp_get_priv(esp);
	u32 val = 0;

	BUG_ON(!(cmd & ESP_CMD_DMA));

	pep->dma_status = 0;

	/* Set DMA engine to IDLE */
	if (write)
		/* DMA write direction logic is inverted */
		val |= ESP_DMA_CMD_DIR;
	pci_esp_write8(esp, ESP_DMA_CMD_IDLE | val, ESP_DMA_CMD);

	pci_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
	pci_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);

	pci_esp_write32(esp, esp_count, ESP_DMA_STC);
	pci_esp_write32(esp, addr, ESP_DMA_SPA);

	esp_dma_log("start dma addr[%x] count[%d:%d]\n",
		    addr, esp_count, dma_count);

	scsi_esp_cmd(esp, cmd);
	/* Send DMA Start command */
	pci_esp_write8(esp, ESP_DMA_CMD_START | val, ESP_DMA_CMD);
}

static const struct esp_driver_ops pci_esp_ops = {
	.esp_write8	=	pci_esp_write8,
	.esp_read8	=	pci_esp_read8,
	.map_single	=	pci_esp_map_single,
	.map_sg		=	pci_esp_map_sg,
	.unmap_single	=	pci_esp_unmap_single,
	.unmap_sg	=	pci_esp_unmap_sg,
	.irq_pending	=	pci_esp_irq_pending,
	.reset_dma	=	pci_esp_reset_dma,
	.dma_drain	=	pci_esp_dma_drain,
	.dma_invalidate	=	pci_esp_dma_invalidate,
	.send_dma_cmd	=	pci_esp_send_dma_cmd,
	.dma_error	=	pci_esp_dma_error,
};

/*
 * Read DC-390 eeprom
 */
static void dc390_eeprom_prepare_read(struct pci_dev *pdev, u8 cmd)
{
	u8 carry_flag = 1, j = 0x80, bval;
	int i;

	for (i = 0; i < 9; i++) {
		if (carry_flag) {
			pci_write_config_byte(pdev, 0x80, 0x40);
			bval = 0xc0;
		} else
			bval = 0x80;

		udelay(160);
		pci_write_config_byte(pdev, 0x80, bval);
		udelay(160);
		pci_write_config_byte(pdev, 0x80, 0);
		udelay(160);

		carry_flag = (cmd & j) ? 1 : 0;
		j >>= 1;
	}
}

static u16 dc390_eeprom_get_data(struct pci_dev *pdev)
{
	int i;
	u16 wval = 0;
	u8 bval;

	for (i = 0; i < 16; i++) {
		wval <<= 1;

		pci_write_config_byte(pdev, 0x80, 0x80);
		udelay(160);
		pci_write_config_byte(pdev, 0x80, 0x40);
		udelay(160);
		pci_read_config_byte(pdev, 0x00, &bval);

		if (bval == 0x22)
			wval |= 1;
	}

	return wval;
}

static void dc390_read_eeprom(struct pci_dev *pdev, u16 *ptr)
{
	u8 cmd = DC390_EEPROM_READ, i;

	for (i = 0; i < DC390_EEPROM_LEN; i++) {
		pci_write_config_byte(pdev, 0xc0, 0);
		udelay(160);

		dc390_eeprom_prepare_read(pdev, cmd++);
		*ptr++ = dc390_eeprom_get_data(pdev);

		pci_write_config_byte(pdev, 0x80, 0);
		pci_write_config_byte(pdev, 0x80, 0);
		udelay(160);
	}
}

static void dc390_check_eeprom(struct esp *esp)
{
	u8 EEbuf[128];
	u16 *ptr = (u16 *)EEbuf, wval = 0;
	int i;

	dc390_read_eeprom((struct pci_dev *)esp->dev, ptr);

	for (i = 0; i < DC390_EEPROM_LEN; i++, ptr++)
		wval += *ptr;

	/* no Tekram EEprom found */
	if (wval != 0x1234) {
		struct pci_dev *pdev = esp->dev;
		dev_printk(KERN_INFO, &pdev->dev,
			   "No valid Tekram EEprom found\n");
		return;
	}
	esp->scsi_id = EEbuf[DC390_EE_ADAPT_SCSI_ID];
	esp->num_tags = 2 << EEbuf[DC390_EE_TAG_CMD_NUM];
	if (EEbuf[DC390_EE_MODE2] & DC390_EE_MODE2_ACTIVE_NEGATION)
		esp->config4 |= ESP_CONFIG4_RADE | ESP_CONFIG4_RAE;
}

static int pci_esp_probe_one(struct pci_dev *pdev,
			      const struct pci_device_id *id)
{
	struct scsi_host_template *hostt = &scsi_esp_template;
	int err = -ENODEV;
	struct Scsi_Host *shost;
	struct esp *esp;
	struct pci_esp_priv *pep;

	if (pci_enable_device(pdev)) {
		dev_printk(KERN_INFO, &pdev->dev, "cannot enable device\n");
		return -ENODEV;
	}

	if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
		dev_printk(KERN_INFO, &pdev->dev,
			   "failed to set 32bit DMA mask\n");
		goto fail_disable_device;
	}

	shost = scsi_host_alloc(hostt, sizeof(struct esp));
	if (!shost) {
		dev_printk(KERN_INFO, &pdev->dev,
			   "failed to allocate scsi host\n");
		err = -ENOMEM;
		goto fail_disable_device;
	}

	pep = kzalloc(sizeof(struct pci_esp_priv), GFP_KERNEL);
	if (!pep) {
		dev_printk(KERN_INFO, &pdev->dev,
			   "failed to allocate esp_priv\n");
		err = -ENOMEM;
		goto fail_host_alloc;
	}

	esp = shost_priv(shost);
	esp->host = shost;
	esp->dev = pdev;
	esp->ops = &pci_esp_ops;
	/*
	 * The am53c974 HBA has a design flaw of generating
	 * spurious DMA completion interrupts when using
	 * DMA for command submission.
	 */
	esp->flags |= ESP_FLAG_USE_FIFO;
	pep->esp = esp;

	if (pci_request_regions(pdev, DRV_MODULE_NAME)) {
		dev_printk(KERN_ERR, &pdev->dev,
			   "pci memory selection failed\n");
		goto fail_priv_alloc;
	}

	esp->regs = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
	if (!esp->regs) {
		dev_printk(KERN_ERR, &pdev->dev, "pci I/O map failed\n");
		err = -EINVAL;
		goto fail_release_regions;
	}
	esp->dma_regs = esp->regs;

	pci_set_master(pdev);

	esp->command_block = pci_alloc_consistent(pdev, 16,
						  &esp->command_block_dma);
	if (!esp->command_block) {
		dev_printk(KERN_ERR, &pdev->dev,
			   "failed to allocate command block\n");
		err = -ENOMEM;
		goto fail_unmap_regs;
	}

	err = request_irq(pdev->irq, scsi_esp_intr, IRQF_SHARED,
			  DRV_MODULE_NAME, esp);
	if (err < 0) {
		dev_printk(KERN_ERR, &pdev->dev, "failed to register IRQ\n");
		goto fail_unmap_command_block;
	}

	esp->scsi_id = 7;
	dc390_check_eeprom(esp);

	shost->this_id = esp->scsi_id;
	shost->max_id = 8;
	shost->irq = pdev->irq;
	shost->io_port = pci_resource_start(pdev, 0);
	shost->n_io_port = pci_resource_len(pdev, 0);
	shost->unique_id = shost->io_port;
	esp->scsi_id_mask = (1 << esp->scsi_id);
	/* Assume 40MHz clock */
	esp->cfreq = 40000000;

	pci_set_drvdata(pdev, pep);

	err = scsi_esp_register(esp, &pdev->dev);
	if (err)
		goto fail_free_irq;

	return 0;

fail_free_irq:
	free_irq(pdev->irq, esp);
fail_unmap_command_block:
	pci_free_consistent(pdev, 16, esp->command_block,
			    esp->command_block_dma);
fail_unmap_regs:
	pci_iounmap(pdev, esp->regs);
fail_release_regions:
	pci_release_regions(pdev);
fail_priv_alloc:
	kfree(pep);
fail_host_alloc:
	scsi_host_put(shost);
fail_disable_device:
	pci_disable_device(pdev);

	return err;
}

static void pci_esp_remove_one(struct pci_dev *pdev)
{
	struct pci_esp_priv *pep = pci_get_drvdata(pdev);
	struct esp *esp = pep->esp;

	scsi_esp_unregister(esp);
	free_irq(pdev->irq, esp);
	pci_free_consistent(pdev, 16, esp->command_block,
			    esp->command_block_dma);
	pci_iounmap(pdev, esp->regs);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	kfree(pep);

	scsi_host_put(esp->host);
}

static struct pci_device_id am53c974_pci_tbl[] = {
	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_SCSI,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ }
};
MODULE_DEVICE_TABLE(pci, am53c974_pci_tbl);

static struct pci_driver am53c974_driver = {
	.name           = DRV_MODULE_NAME,
	.id_table       = am53c974_pci_tbl,
	.probe          = pci_esp_probe_one,
	.remove         = pci_esp_remove_one,
};

static int __init am53c974_module_init(void)
{
	return pci_register_driver(&am53c974_driver);
}

static void __exit am53c974_module_exit(void)
{
	pci_unregister_driver(&am53c974_driver);
}

MODULE_DESCRIPTION("AM53C974 SCSI driver");
MODULE_AUTHOR("Hannes Reinecke <hare@suse.de>");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_MODULE_VERSION);

module_param(am53c974_debug, bool, 0644);
MODULE_PARM_DESC(am53c974_debug, "Enable debugging");

module_init(am53c974_module_init);
module_exit(am53c974_module_exit);
Commit	Line	Data
3a7e7be2 HR	1	/*
	2	* AMD am53c974 driver.
	3	* Copyright (c) 2014 Hannes Reinecke, SUSE Linux GmbH
	4	*/
	5
	6	#include <linux/kernel.h>
	7	#include <linux/module.h>
	8	#include <linux/init.h>
	9	#include <linux/delay.h>
	10	#include <linux/pci.h>
	11	#include <linux/interrupt.h>
	12
	13	#include <scsi/scsi_host.h>
	14
	15	#include "esp_scsi.h"
	16
	17	#define DRV_MODULE_NAME "am53c974"
	18	#define DRV_MODULE_VERSION "1.00"
	19
	20	static bool am53c974_debug;
	21
	22	#define esp_dma_log(f, a...) \
	23	do { \
	24	if (am53c974_debug) \
	25	shost_printk(KERN_DEBUG, esp->host, f, ##a); \
	26	} while (0)
	27
	28	#define ESP_DMA_CMD 0x10
	29	#define ESP_DMA_STC 0x11
	30	#define ESP_DMA_SPA 0x12
	31	#define ESP_DMA_WBC 0x13
	32	#define ESP_DMA_WAC 0x14
	33	#define ESP_DMA_STATUS 0x15
	34	#define ESP_DMA_SMDLA 0x16
	35	#define ESP_DMA_WMAC 0x17
	36
	37	#define ESP_DMA_CMD_IDLE 0x00
	38	#define ESP_DMA_CMD_BLAST 0x01
	39	#define ESP_DMA_CMD_ABORT 0x02
	40	#define ESP_DMA_CMD_START 0x03
	41	#define ESP_DMA_CMD_MASK 0x03
	42	#define ESP_DMA_CMD_DIAG 0x04
	43	#define ESP_DMA_CMD_MDL 0x10
	44	#define ESP_DMA_CMD_INTE_P 0x20
	45	#define ESP_DMA_CMD_INTE_D 0x40
	46	#define ESP_DMA_CMD_DIR 0x80
	47
	48	#define ESP_DMA_STAT_PWDN 0x01
	49	#define ESP_DMA_STAT_ERROR 0x02
	50	#define ESP_DMA_STAT_ABORT 0x04
	51	#define ESP_DMA_STAT_DONE 0x08
	52	#define ESP_DMA_STAT_SCSIINT 0x10
	53	#define ESP_DMA_STAT_BCMPLT 0x20
	54
	55	/* EEPROM is accessed with 16-bit values */
	56	#define DC390_EEPROM_READ 0x80
	57	#define DC390_EEPROM_LEN 0x40
	58
	59	/*
	60	* DC390 EEPROM
	61	*
	62	* 8 * 4 bytes of per-device options
	63	* followed by HBA specific options
	64	*/
65
66	/* Per-device options */
67	#define DC390_EE_MODE1 0x00
68	#define DC390_EE_SPEED 0x01
69
70	/* HBA-specific options */
71	#define DC390_EE_ADAPT_SCSI_ID 0x40
72	#define DC390_EE_MODE2 0x41
73	#define DC390_EE_DELAY 0x42
74	#define DC390_EE_TAG_CMD_NUM 0x43
75
76	#define DC390_EE_MODE1_PARITY_CHK 0x01
77	#define DC390_EE_MODE1_SYNC_NEGO 0x02
78	#define DC390_EE_MODE1_EN_DISC 0x04
79	#define DC390_EE_MODE1_SEND_START 0x08
80	#define DC390_EE_MODE1_TCQ 0x10
81
82	#define DC390_EE_MODE2_MORE_2DRV 0x01
83	#define DC390_EE_MODE2_GREATER_1G 0x02
84	#define DC390_EE_MODE2_RST_SCSI_BUS 0x04
85	#define DC390_EE_MODE2_ACTIVE_NEGATION 0x08
86	#define DC390_EE_MODE2_NO_SEEK 0x10
87	#define DC390_EE_MODE2_LUN_CHECK 0x20
88
89	struct pci_esp_priv {
90	struct esp *esp;
91	u8 dma_status;
92	};
93
94	static void pci_esp_dma_drain(struct esp *esp);
95
96	static inline struct pci_esp_priv pci_esp_get_priv(struct esp esp)
97	{
98	struct pci_dev *pdev = esp->dev;
99
100	return pci_get_drvdata(pdev);
101	}
102
103	static void pci_esp_write8(struct esp *esp, u8 val, unsigned long reg)
104	{
105	iowrite8(val, esp->regs + (reg * 4UL));
106	}
107
108	static u8 pci_esp_read8(struct esp *esp, unsigned long reg)
109	{
110	return ioread8(esp->regs + (reg * 4UL));
111	}
112
113	static void pci_esp_write32(struct esp *esp, u32 val, unsigned long reg)
114	{
115	return iowrite32(val, esp->regs + (reg * 4UL));
116	}
117
118	static dma_addr_t pci_esp_map_single(struct esp esp, void buf,
119	size_t sz, int dir)
120	{
121	return pci_map_single(esp->dev, buf, sz, dir);
122	}
123
124	static int pci_esp_map_sg(struct esp esp, struct scatterlist sg,
125	int num_sg, int dir)
126	{
127	return pci_map_sg(esp->dev, sg, num_sg, dir);
128	}
129
130	static void pci_esp_unmap_single(struct esp *esp, dma_addr_t addr,
131	size_t sz, int dir)
132	{
133	pci_unmap_single(esp->dev, addr, sz, dir);
134	}
135
136	static void pci_esp_unmap_sg(struct esp esp, struct scatterlist sg,
137	int num_sg, int dir)
138	{
139	pci_unmap_sg(esp->dev, sg, num_sg, dir);
140	}
141
142	static int pci_esp_irq_pending(struct esp *esp)
143	{
144	struct pci_esp_priv *pep = pci_esp_get_priv(esp);
145
146	pep->dma_status = pci_esp_read8(esp, ESP_DMA_STATUS);
147	esp_dma_log("dma intr dreg[%02x]\n", pep->dma_status);
148
149	if (pep->dma_status & (ESP_DMA_STAT_ERROR \|
150	ESP_DMA_STAT_ABORT \|
151	ESP_DMA_STAT_DONE \|
152	ESP_DMA_STAT_SCSIINT))
153	return 1;
154
155	return 0;
156	}
157
158	static void pci_esp_reset_dma(struct esp *esp)
159	{
160	/* Nothing to do ? */
161	}
162
163	static void pci_esp_dma_drain(struct esp *esp)
164	{
165	u8 resid;
166	int lim = 1000;
167
168
169	if ((esp->sreg & ESP_STAT_PMASK) == ESP_DOP \|\|
170	(esp->sreg & ESP_STAT_PMASK) == ESP_DIP)
171	/* Data-In or Data-Out, nothing to be done */
172	return;
173
174	while (--lim > 0) {
175	resid = pci_esp_read8(esp, ESP_FFLAGS) & ESP_FF_FBYTES;
176	if (resid <= 1)
177	break;
178	cpu_relax();
179	}
180	if (resid > 1) {
181	/* FIFO not cleared */
182	shost_printk(KERN_INFO, esp->host,
183	"FIFO not cleared, %d bytes left\n",
184	resid);
185	}
186
187	/*
188	* When there is a residual BCMPLT will never be set
189	* (obviously). But we still have to issue the BLAST
190	* command, otherwise the data will not being transferred.
191	* But we'll never know when the BLAST operation is
192	* finished. So check for some time and give up eventually.
193	*/
194	lim = 1000;
195	pci_esp_write8(esp, ESP_DMA_CMD_DIR \| ESP_DMA_CMD_BLAST, ESP_DMA_CMD);
196	while (pci_esp_read8(esp, ESP_DMA_STATUS) & ESP_DMA_STAT_BCMPLT) {
197	if (--lim == 0)
198	break;
199	cpu_relax();
200	}
201	pci_esp_write8(esp, ESP_DMA_CMD_DIR \| ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
202	esp_dma_log("DMA blast done (%d tries, %d bytes left)\n", lim, resid);
6df388f2 HR	203	/* BLAST residual handling is currently untested */
	204	if (WARN_ON_ONCE(resid == 1)) {
	205	struct esp_cmd_entry *ent = esp->active_cmd;
	206
	207	ent->flags \|= ESP_CMD_FLAG_RESIDUAL;
	208	}
3a7e7be2 HR	209	}
	210
	211	static void pci_esp_dma_invalidate(struct esp *esp)
	212	{
	213	struct pci_esp_priv *pep = pci_esp_get_priv(esp);
	214
	215	esp_dma_log("invalidate DMA\n");
	216
	217	pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
	218	pep->dma_status = 0;
	219	}
	220
	221	static int pci_esp_dma_error(struct esp *esp)
	222	{
	223	struct pci_esp_priv *pep = pci_esp_get_priv(esp);
	224
	225	if (pep->dma_status & ESP_DMA_STAT_ERROR) {
	226	u8 dma_cmd = pci_esp_read8(esp, ESP_DMA_CMD);
	227
	228	if ((dma_cmd & ESP_DMA_CMD_MASK) == ESP_DMA_CMD_START)
	229	pci_esp_write8(esp, ESP_DMA_CMD_ABORT, ESP_DMA_CMD);
	230
	231	return 1;
	232	}
	233	if (pep->dma_status & ESP_DMA_STAT_ABORT) {
	234	pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
	235	pep->dma_status = pci_esp_read8(esp, ESP_DMA_CMD);
	236	return 1;
	237	}
	238	return 0;
	239	}
	240
	241	static void pci_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
	242	u32 dma_count, int write, u8 cmd)
	243	{
	244	struct pci_esp_priv *pep = pci_esp_get_priv(esp);
	245	u32 val = 0;
	246
	247	BUG_ON(!(cmd & ESP_CMD_DMA));
	248
	249	pep->dma_status = 0;
	250
	251	/* Set DMA engine to IDLE */
	252	if (write)
	253	/* DMA write direction logic is inverted */
	254	val \|= ESP_DMA_CMD_DIR;
	255	pci_esp_write8(esp, ESP_DMA_CMD_IDLE \| val, ESP_DMA_CMD);
	256
	257	pci_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
	258	pci_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
	259
	260	pci_esp_write32(esp, esp_count, ESP_DMA_STC);
	261	pci_esp_write32(esp, addr, ESP_DMA_SPA);
	262
	263	esp_dma_log("start dma addr[%x] count[%d:%d]\n",
	264	addr, esp_count, dma_count);
	265
	266	scsi_esp_cmd(esp, cmd);
	267	/* Send DMA Start command */
	268	pci_esp_write8(esp, ESP_DMA_CMD_START \| val, ESP_DMA_CMD);
	269	}
	270
	271	static const struct esp_driver_ops pci_esp_ops = {
	272	.esp_write8 = pci_esp_write8,
273	.esp_read8 = pci_esp_read8,
274	.map_single = pci_esp_map_single,
275	.map_sg = pci_esp_map_sg,
276	.unmap_single = pci_esp_unmap_single,
277	.unmap_sg = pci_esp_unmap_sg,
278	.irq_pending = pci_esp_irq_pending,
279	.reset_dma = pci_esp_reset_dma,
280	.dma_drain = pci_esp_dma_drain,
281	.dma_invalidate = pci_esp_dma_invalidate,
282	.send_dma_cmd = pci_esp_send_dma_cmd,
283	.dma_error = pci_esp_dma_error,
284	};
285
286	/*
287	* Read DC-390 eeprom
288	*/
289	static void dc390_eeprom_prepare_read(struct pci_dev *pdev, u8 cmd)
290	{
291	u8 carry_flag = 1, j = 0x80, bval;
292	int i;
293
294	for (i = 0; i < 9; i++) {
295	if (carry_flag) {
296	pci_write_config_byte(pdev, 0x80, 0x40);
297	bval = 0xc0;
298	} else
299	bval = 0x80;
300
301	udelay(160);
302	pci_write_config_byte(pdev, 0x80, bval);
303	udelay(160);
304	pci_write_config_byte(pdev, 0x80, 0);
305	udelay(160);
306
307	carry_flag = (cmd & j) ? 1 : 0;
308	j >>= 1;
309	}
310	}
311
312	static u16 dc390_eeprom_get_data(struct pci_dev *pdev)
313	{
314	int i;
315	u16 wval = 0;
316	u8 bval;
317
318	for (i = 0; i < 16; i++) {
319	wval <<= 1;
320
321	pci_write_config_byte(pdev, 0x80, 0x80);
322	udelay(160);
323	pci_write_config_byte(pdev, 0x80, 0x40);
324	udelay(160);
325	pci_read_config_byte(pdev, 0x00, &bval);
326
327	if (bval == 0x22)
328	wval \|= 1;
329	}
330
331	return wval;
332	}
333
334	static void dc390_read_eeprom(struct pci_dev pdev, u16 ptr)
335	{
336	u8 cmd = DC390_EEPROM_READ, i;
337
338	for (i = 0; i < DC390_EEPROM_LEN; i++) {
339	pci_write_config_byte(pdev, 0xc0, 0);
340	udelay(160);
341
342	dc390_eeprom_prepare_read(pdev, cmd++);
343	*ptr++ = dc390_eeprom_get_data(pdev);
344
345	pci_write_config_byte(pdev, 0x80, 0);
346	pci_write_config_byte(pdev, 0x80, 0);
347	udelay(160);
348	}
349	}
350
351	static void dc390_check_eeprom(struct esp *esp)
352	{
353	u8 EEbuf[128];
354	u16 ptr = (u16 )EEbuf, wval = 0;
355	int i;
356
357	dc390_read_eeprom((struct pci_dev *)esp->dev, ptr);
358
359	for (i = 0; i < DC390_EEPROM_LEN; i++, ptr++)
360	wval += *ptr;
361
362	/* no Tekram EEprom found */
363	if (wval != 0x1234) {
364	struct pci_dev *pdev = esp->dev;
365	dev_printk(KERN_INFO, &pdev->dev,
366	"No valid Tekram EEprom found\n");
367	return;
368	}
369	esp->scsi_id = EEbuf[DC390_EE_ADAPT_SCSI_ID];
370	esp->num_tags = 2 << EEbuf[DC390_EE_TAG_CMD_NUM];
eeea2f9c HR	371	if (EEbuf[DC390_EE_MODE2] & DC390_EE_MODE2_ACTIVE_NEGATION)
eeea2f9c HR	372	esp->config4 \|= ESP_CONFIG4_RADE \| ESP_CONFIG4_RAE;
3a7e7be2 HR	373	}
	374
	375	static int pci_esp_probe_one(struct pci_dev *pdev,
	376	const struct pci_device_id *id)
	377	{
	378	struct scsi_host_template *hostt = &scsi_esp_template;
	379	int err = -ENODEV;
	380	struct Scsi_Host *shost;
	381	struct esp *esp;
	382	struct pci_esp_priv *pep;
	383
	384	if (pci_enable_device(pdev)) {
	385	dev_printk(KERN_INFO, &pdev->dev, "cannot enable device\n");
	386	return -ENODEV;
	387	}
	388
	389	if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
	390	dev_printk(KERN_INFO, &pdev->dev,
	391	"failed to set 32bit DMA mask\n");
	392	goto fail_disable_device;
	393	}
	394
	395	shost = scsi_host_alloc(hostt, sizeof(struct esp));
	396	if (!shost) {
	397	dev_printk(KERN_INFO, &pdev->dev,
	398	"failed to allocate scsi host\n");
	399	err = -ENOMEM;
	400	goto fail_disable_device;
	401	}
	402
	403	pep = kzalloc(sizeof(struct pci_esp_priv), GFP_KERNEL);
	404	if (!pep) {
	405	dev_printk(KERN_INFO, &pdev->dev,
	406	"failed to allocate esp_priv\n");
	407	err = -ENOMEM;
	408	goto fail_host_alloc;
	409	}
	410
	411	esp = shost_priv(shost);
	412	esp->host = shost;
	413	esp->dev = pdev;
	414	esp->ops = &pci_esp_ops;
	415	/*
	416	* The am53c974 HBA has a design flaw of generating
	417	* spurious DMA completion interrupts when using
	418	* DMA for command submission.
	419	*/
	420	esp->flags \|= ESP_FLAG_USE_FIFO;
	421	pep->esp = esp;
	422
	423	if (pci_request_regions(pdev, DRV_MODULE_NAME)) {
	424	dev_printk(KERN_ERR, &pdev->dev,
	425	"pci memory selection failed\n");
	426	goto fail_priv_alloc;
	427	}
	428
	429	esp->regs = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
	430	if (!esp->regs) {
	431	dev_printk(KERN_ERR, &pdev->dev, "pci I/O map failed\n");
	432	err = -EINVAL;
	433	goto fail_release_regions;
	434	}
	435	esp->dma_regs = esp->regs;
	436
437	pci_set_master(pdev);
438
439	esp->command_block = pci_alloc_consistent(pdev, 16,
440	&esp->command_block_dma);
441	if (!esp->command_block) {
442	dev_printk(KERN_ERR, &pdev->dev,
443	"failed to allocate command block\n");
444	err = -ENOMEM;
445	goto fail_unmap_regs;
446	}
447
448	err = request_irq(pdev->irq, scsi_esp_intr, IRQF_SHARED,
449	DRV_MODULE_NAME, esp);
450	if (err < 0) {
451	dev_printk(KERN_ERR, &pdev->dev, "failed to register IRQ\n");
452	goto fail_unmap_command_block;
453	}
454
455	esp->scsi_id = 7;
456	dc390_check_eeprom(esp);
457
458	shost->this_id = esp->scsi_id;
459	shost->max_id = 8;
460	shost->irq = pdev->irq;
461	shost->io_port = pci_resource_start(pdev, 0);
462	shost->n_io_port = pci_resource_len(pdev, 0);
463	shost->unique_id = shost->io_port;
464	esp->scsi_id_mask = (1 << esp->scsi_id);
465	/* Assume 40MHz clock */
466	esp->cfreq = 40000000;
467
468	pci_set_drvdata(pdev, pep);
469
470	err = scsi_esp_register(esp, &pdev->dev);
471	if (err)
472	goto fail_free_irq;
473
474	return 0;
475
476	fail_free_irq:
477	free_irq(pdev->irq, esp);
478	fail_unmap_command_block:
479	pci_free_consistent(pdev, 16, esp->command_block,
480	esp->command_block_dma);
481	fail_unmap_regs:
482	pci_iounmap(pdev, esp->regs);
483	fail_release_regions:
484	pci_release_regions(pdev);
485	fail_priv_alloc:
486	kfree(pep);
487	fail_host_alloc:
488	scsi_host_put(shost);
489	fail_disable_device:
490	pci_disable_device(pdev);
491
492	return err;
493	}
494
495	static void pci_esp_remove_one(struct pci_dev *pdev)
496	{
497	struct pci_esp_priv *pep = pci_get_drvdata(pdev);
498	struct esp *esp = pep->esp;
499
500	scsi_esp_unregister(esp);
501	free_irq(pdev->irq, esp);
502	pci_free_consistent(pdev, 16, esp->command_block,
503	esp->command_block_dma);
504	pci_iounmap(pdev, esp->regs);
505	pci_release_regions(pdev);
506	pci_disable_device(pdev);
507	kfree(pep);
508
509	scsi_host_put(esp->host);
510	}
511
512	static struct pci_device_id am53c974_pci_tbl[] = {
513	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_SCSI,
514	PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
515	{ }
516	};
517	MODULE_DEVICE_TABLE(pci, am53c974_pci_tbl);
518
519	static struct pci_driver am53c974_driver = {
520	.name = DRV_MODULE_NAME,
521	.id_table = am53c974_pci_tbl,
522	.probe = pci_esp_probe_one,
523	.remove = pci_esp_remove_one,
524	};
525
526	static int __init am53c974_module_init(void)
527	{
528	return pci_register_driver(&am53c974_driver);
529	}
530
531	static void __exit am53c974_module_exit(void)
532	{
533	pci_unregister_driver(&am53c974_driver);
534	}
535
536	MODULE_DESCRIPTION("AM53C974 SCSI driver");
537	MODULE_AUTHOR("Hannes Reinecke <hare@suse.de>");
538	MODULE_LICENSE("GPL");
539	MODULE_VERSION(DRV_MODULE_VERSION);
540
541	module_param(am53c974_debug, bool, 0644);
542	MODULE_PARM_DESC(am53c974_debug, "Enable debugging");
543
544	module_init(am53c974_module_init);
545	module_exit(am53c974_module_exit);