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1c57e86d EC |
1 | /* |
2 | ******************************************************************************* | |
3 | ** O.S : Linux | |
4 | ** FILE NAME : arcmsr.h | |
5 | ** BY : Erich Chen | |
6 | ** Description: SCSI RAID Device Driver for | |
7 | ** ARECA RAID Host adapter | |
8 | ******************************************************************************* | |
9 | ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved. | |
10 | ** | |
11 | ** Web site: www.areca.com.tw | |
1a4f550a | 12 | ** E-mail: support@areca.com.tw |
1c57e86d EC |
13 | ** |
14 | ** This program is free software; you can redistribute it and/or modify | |
15 | ** it under the terms of the GNU General Public License version 2 as | |
16 | ** published by the Free Software Foundation. | |
17 | ** This program is distributed in the hope that it will be useful, | |
18 | ** but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | ** GNU General Public License for more details. | |
21 | ******************************************************************************* | |
22 | ** Redistribution and use in source and binary forms, with or without | |
23 | ** modification, are permitted provided that the following conditions | |
24 | ** are met: | |
25 | ** 1. Redistributions of source code must retain the above copyright | |
26 | ** notice, this list of conditions and the following disclaimer. | |
27 | ** 2. Redistributions in binary form must reproduce the above copyright | |
28 | ** notice, this list of conditions and the following disclaimer in the | |
29 | ** documentation and/or other materials provided with the distribution. | |
30 | ** 3. The name of the author may not be used to endorse or promote products | |
31 | ** derived from this software without specific prior written permission. | |
32 | ** | |
33 | ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR | |
34 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | |
35 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. | |
36 | ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
37 | ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT | |
38 | ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
39 | ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY | |
40 | ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
41 | **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF | |
42 | ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
43 | ******************************************************************************* | |
44 | */ | |
45 | #include <linux/interrupt.h> | |
46 | ||
ee959b00 | 47 | struct device_attribute; |
1a4f550a NC |
48 | /*The limit of outstanding scsi command that firmware can handle*/ |
49 | #define ARCMSR_MAX_OUTSTANDING_CMD 256 | |
50 | #define ARCMSR_MAX_FREECCB_NUM 320 | |
ba1cb461 | 51 | #define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.15 2008/02/27" |
1c57e86d EC |
52 | #define ARCMSR_SCSI_INITIATOR_ID 255 |
53 | #define ARCMSR_MAX_XFER_SECTORS 512 | |
1a4f550a NC |
54 | #define ARCMSR_MAX_XFER_SECTORS_B 4096 |
55 | #define ARCMSR_MAX_TARGETID 17 | |
56 | #define ARCMSR_MAX_TARGETLUN 8 | |
57 | #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD | |
58 | #define ARCMSR_MAX_QBUFFER 4096 | |
59 | #define ARCMSR_MAX_SG_ENTRIES 38 | |
60 | #define ARCMSR_MAX_HBB_POSTQUEUE 264 | |
61 | /* | |
62 | ********************************************************************************** | |
63 | ** | |
64 | ********************************************************************************** | |
65 | */ | |
66 | #define ARC_SUCCESS 0 | |
67 | #define ARC_FAILURE 1 | |
1c57e86d EC |
68 | /* |
69 | ******************************************************************************* | |
70 | ** split 64bits dma addressing | |
71 | ******************************************************************************* | |
72 | */ | |
73 | #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16) | |
74 | #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff) | |
75 | /* | |
76 | ******************************************************************************* | |
77 | ** MESSAGE CONTROL CODE | |
78 | ******************************************************************************* | |
79 | */ | |
80 | struct CMD_MESSAGE | |
81 | { | |
82 | uint32_t HeaderLength; | |
83 | uint8_t Signature[8]; | |
84 | uint32_t Timeout; | |
85 | uint32_t ControlCode; | |
86 | uint32_t ReturnCode; | |
87 | uint32_t Length; | |
88 | }; | |
89 | /* | |
90 | ******************************************************************************* | |
91 | ** IOP Message Transfer Data for user space | |
92 | ******************************************************************************* | |
93 | */ | |
94 | struct CMD_MESSAGE_FIELD | |
95 | { | |
96 | struct CMD_MESSAGE cmdmessage; | |
97 | uint8_t messagedatabuffer[1032]; | |
98 | }; | |
99 | /* IOP message transfer */ | |
1a4f550a | 100 | #define ARCMSR_MESSAGE_FAIL 0x0001 |
1c57e86d EC |
101 | /* DeviceType */ |
102 | #define ARECA_SATA_RAID 0x90000000 | |
103 | /* FunctionCode */ | |
104 | #define FUNCTION_READ_RQBUFFER 0x0801 | |
105 | #define FUNCTION_WRITE_WQBUFFER 0x0802 | |
106 | #define FUNCTION_CLEAR_RQBUFFER 0x0803 | |
107 | #define FUNCTION_CLEAR_WQBUFFER 0x0804 | |
108 | #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 | |
109 | #define FUNCTION_RETURN_CODE_3F 0x0806 | |
110 | #define FUNCTION_SAY_HELLO 0x0807 | |
111 | #define FUNCTION_SAY_GOODBYE 0x0808 | |
112 | #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 | |
113 | /* ARECA IO CONTROL CODE*/ | |
114 | #define ARCMSR_MESSAGE_READ_RQBUFFER \ | |
115 | ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER | |
116 | #define ARCMSR_MESSAGE_WRITE_WQBUFFER \ | |
117 | ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER | |
118 | #define ARCMSR_MESSAGE_CLEAR_RQBUFFER \ | |
119 | ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER | |
120 | #define ARCMSR_MESSAGE_CLEAR_WQBUFFER \ | |
121 | ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER | |
122 | #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \ | |
123 | ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER | |
124 | #define ARCMSR_MESSAGE_RETURN_CODE_3F \ | |
125 | ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F | |
126 | #define ARCMSR_MESSAGE_SAY_HELLO \ | |
127 | ARECA_SATA_RAID | FUNCTION_SAY_HELLO | |
128 | #define ARCMSR_MESSAGE_SAY_GOODBYE \ | |
129 | ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE | |
130 | #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \ | |
131 | ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE | |
132 | /* ARECA IOCTL ReturnCode */ | |
133 | #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 | |
134 | #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 | |
135 | #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F | |
136 | /* | |
137 | ************************************************************* | |
138 | ** structure for holding DMA address data | |
139 | ************************************************************* | |
140 | */ | |
141 | #define IS_SG64_ADDR 0x01000000 /* bit24 */ | |
142 | struct SG32ENTRY | |
143 | { | |
80da1adb AV |
144 | __le32 length; |
145 | __le32 address; | |
1c57e86d EC |
146 | }; |
147 | struct SG64ENTRY | |
148 | { | |
80da1adb AV |
149 | __le32 length; |
150 | __le32 address; | |
151 | __le32 addresshigh; | |
1c57e86d EC |
152 | }; |
153 | struct SGENTRY_UNION | |
154 | { | |
155 | union | |
156 | { | |
157 | struct SG32ENTRY sg32entry; | |
158 | struct SG64ENTRY sg64entry; | |
159 | }u; | |
160 | }; | |
161 | /* | |
162 | ******************************************************************** | |
163 | ** Q Buffer of IOP Message Transfer | |
164 | ******************************************************************** | |
165 | */ | |
166 | struct QBUFFER | |
167 | { | |
168 | uint32_t data_len; | |
169 | uint8_t data[124]; | |
170 | }; | |
171 | /* | |
172 | ******************************************************************************* | |
1a4f550a | 173 | ** FIRMWARE INFO for Intel IOP R 80331 processor (Type A) |
1c57e86d EC |
174 | ******************************************************************************* |
175 | */ | |
176 | struct FIRMWARE_INFO | |
177 | { | |
1a4f550a NC |
178 | uint32_t signature; /*0, 00-03*/ |
179 | uint32_t request_len; /*1, 04-07*/ | |
180 | uint32_t numbers_queue; /*2, 08-11*/ | |
1c57e86d | 181 | uint32_t sdram_size; /*3, 12-15*/ |
1a4f550a NC |
182 | uint32_t ide_channels; /*4, 16-19*/ |
183 | char vendor[40]; /*5, 20-59*/ | |
184 | char model[8]; /*15, 60-67*/ | |
185 | char firmware_ver[16]; /*17, 68-83*/ | |
186 | char device_map[16]; /*21, 84-99*/ | |
1c57e86d EC |
187 | }; |
188 | /* signature of set and get firmware config */ | |
1a4f550a NC |
189 | #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 |
190 | #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 | |
1c57e86d | 191 | /* message code of inbound message register */ |
1a4f550a NC |
192 | #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 |
193 | #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 | |
1c57e86d EC |
194 | #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 |
195 | #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 | |
196 | #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 | |
197 | #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 | |
198 | #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 | |
199 | #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 | |
200 | #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 | |
201 | /* doorbell interrupt generator */ | |
202 | #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 | |
203 | #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 | |
204 | #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 | |
205 | #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 | |
206 | /* ccb areca cdb flag */ | |
207 | #define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000 | |
208 | #define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000 | |
209 | #define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000 | |
210 | #define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000 | |
211 | /* outbound firmware ok */ | |
212 | #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 | |
1a4f550a NC |
213 | |
214 | /* | |
215 | ************************************************************************ | |
216 | ** SPEC. for Areca Type B adapter | |
217 | ************************************************************************ | |
218 | */ | |
219 | /* ARECA HBB COMMAND for its FIRMWARE */ | |
220 | /* window of "instruction flags" from driver to iop */ | |
221 | #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 | |
222 | #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 | |
223 | /* window of "instruction flags" from iop to driver */ | |
224 | #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 | |
225 | #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C | |
226 | /* ARECA FLAG LANGUAGE */ | |
227 | /* ioctl transfer */ | |
228 | #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 | |
229 | /* ioctl transfer */ | |
230 | #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 | |
231 | #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 | |
232 | #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 | |
233 | ||
234 | #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F | |
235 | #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 | |
236 | #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 | |
237 | /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ | |
238 | #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 | |
239 | /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ | |
240 | #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 | |
241 | /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ | |
242 | #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 | |
243 | /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ | |
244 | #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 | |
245 | /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ | |
246 | #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 | |
247 | /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ | |
248 | #define ARCMSR_MESSAGE_START_BGRB 0x00060008 | |
249 | #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 | |
250 | #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 | |
76d78300 | 251 | #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 |
1a4f550a NC |
252 | /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ |
253 | #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 | |
254 | /* ioctl transfer */ | |
255 | #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 | |
256 | /* ioctl transfer */ | |
257 | #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 | |
258 | #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 | |
259 | #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 | |
76d78300 | 260 | #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 |
1a4f550a NC |
261 | |
262 | /* data tunnel buffer between user space program and its firmware */ | |
263 | /* user space data to iop 128bytes */ | |
264 | #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 | |
265 | /* iop data to user space 128bytes */ | |
266 | #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 | |
267 | /* iop message_rwbuffer for message command */ | |
268 | #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 | |
1c57e86d EC |
269 | /* |
270 | ******************************************************************************* | |
271 | ** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504) | |
272 | ******************************************************************************* | |
273 | */ | |
274 | struct ARCMSR_CDB | |
275 | { | |
276 | uint8_t Bus; | |
277 | uint8_t TargetID; | |
278 | uint8_t LUN; | |
279 | uint8_t Function; | |
1c57e86d EC |
280 | uint8_t CdbLength; |
281 | uint8_t sgcount; | |
282 | uint8_t Flags; | |
283 | #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 | |
284 | #define ARCMSR_CDB_FLAG_BIOS 0x02 | |
285 | #define ARCMSR_CDB_FLAG_WRITE 0x04 | |
286 | #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 | |
287 | #define ARCMSR_CDB_FLAG_HEADQ 0x08 | |
288 | #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 | |
1c57e86d | 289 | |
1a4f550a | 290 | uint8_t Reserved1; |
1c57e86d EC |
291 | uint32_t Context; |
292 | uint32_t DataLength; | |
1c57e86d | 293 | uint8_t Cdb[16]; |
1c57e86d | 294 | uint8_t DeviceStatus; |
1a4f550a NC |
295 | #define ARCMSR_DEV_CHECK_CONDITION 0x02 |
296 | #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 | |
297 | #define ARCMSR_DEV_ABORTED 0xF1 | |
298 | #define ARCMSR_DEV_INIT_FAIL 0xF2 | |
1c57e86d | 299 | |
1a4f550a | 300 | uint8_t SenseData[15]; |
1c57e86d EC |
301 | union |
302 | { | |
303 | struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; | |
304 | struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; | |
305 | } u; | |
306 | }; | |
307 | /* | |
308 | ******************************************************************************* | |
1a4f550a | 309 | ** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor |
1c57e86d EC |
310 | ******************************************************************************* |
311 | */ | |
1a4f550a | 312 | struct MessageUnit_A |
1c57e86d EC |
313 | { |
314 | uint32_t resrved0[4]; /*0000 000F*/ | |
315 | uint32_t inbound_msgaddr0; /*0010 0013*/ | |
316 | uint32_t inbound_msgaddr1; /*0014 0017*/ | |
317 | uint32_t outbound_msgaddr0; /*0018 001B*/ | |
318 | uint32_t outbound_msgaddr1; /*001C 001F*/ | |
319 | uint32_t inbound_doorbell; /*0020 0023*/ | |
320 | uint32_t inbound_intstatus; /*0024 0027*/ | |
321 | uint32_t inbound_intmask; /*0028 002B*/ | |
322 | uint32_t outbound_doorbell; /*002C 002F*/ | |
323 | uint32_t outbound_intstatus; /*0030 0033*/ | |
324 | uint32_t outbound_intmask; /*0034 0037*/ | |
325 | uint32_t reserved1[2]; /*0038 003F*/ | |
326 | uint32_t inbound_queueport; /*0040 0043*/ | |
327 | uint32_t outbound_queueport; /*0044 0047*/ | |
328 | uint32_t reserved2[2]; /*0048 004F*/ | |
329 | uint32_t reserved3[492]; /*0050 07FF 492*/ | |
330 | uint32_t reserved4[128]; /*0800 09FF 128*/ | |
331 | uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/ | |
332 | uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/ | |
333 | uint32_t reserved5[32]; /*0E80 0EFF 32*/ | |
334 | uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/ | |
335 | uint32_t reserved6[32]; /*0F80 0FFF 32*/ | |
336 | }; | |
1a4f550a NC |
337 | |
338 | struct MessageUnit_B | |
339 | { | |
340 | uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; | |
341 | uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; | |
342 | uint32_t postq_index; | |
343 | uint32_t doneq_index; | |
4d3995b1 | 344 | void __iomem *drv2iop_doorbell_reg; |
345 | void __iomem *drv2iop_doorbell_mask_reg; | |
346 | void __iomem *iop2drv_doorbell_reg; | |
347 | void __iomem *iop2drv_doorbell_mask_reg; | |
348 | void __iomem *msgcode_rwbuffer_reg; | |
349 | void __iomem *ioctl_wbuffer_reg; | |
350 | void __iomem *ioctl_rbuffer_reg; | |
1a4f550a NC |
351 | }; |
352 | ||
1c57e86d EC |
353 | /* |
354 | ******************************************************************************* | |
355 | ** Adapter Control Block | |
356 | ******************************************************************************* | |
357 | */ | |
358 | struct AdapterControlBlock | |
359 | { | |
1a4f550a NC |
360 | uint32_t adapter_type; /* adapter A,B..... */ |
361 | #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */ | |
362 | #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */ | |
363 | #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc P IOP */ | |
364 | #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */ | |
1c57e86d EC |
365 | struct pci_dev * pdev; |
366 | struct Scsi_Host * host; | |
367 | unsigned long vir2phy_offset; | |
368 | /* Offset is used in making arc cdb physical to virtual calculations */ | |
369 | uint32_t outbound_int_enable; | |
370 | ||
80da1adb | 371 | union { |
80da1adb AV |
372 | struct MessageUnit_A __iomem * pmuA; |
373 | struct MessageUnit_B * pmuB; | |
374 | }; | |
1c57e86d EC |
375 | /* message unit ATU inbound base address0 */ |
376 | ||
377 | uint32_t acb_flags; | |
1a4f550a NC |
378 | #define ACB_F_SCSISTOPADAPTER 0x0001 |
379 | #define ACB_F_MSG_STOP_BGRB 0x0002 | |
1c57e86d | 380 | /* stop RAID background rebuild */ |
1a4f550a | 381 | #define ACB_F_MSG_START_BGRB 0x0004 |
1c57e86d | 382 | /* stop RAID background rebuild */ |
1a4f550a | 383 | #define ACB_F_IOPDATA_OVERFLOW 0x0008 |
1c57e86d | 384 | /* iop message data rqbuffer overflow */ |
1a4f550a | 385 | #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 |
1c57e86d | 386 | /* message clear wqbuffer */ |
1a4f550a | 387 | #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 |
1c57e86d | 388 | /* message clear rqbuffer */ |
1a4f550a NC |
389 | #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040 |
390 | #define ACB_F_BUS_RESET 0x0080 | |
391 | #define ACB_F_IOP_INITED 0x0100 | |
1c57e86d EC |
392 | /* iop init */ |
393 | ||
394 | struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM]; | |
395 | /* used for memory free */ | |
396 | struct list_head ccb_free_list; | |
397 | /* head of free ccb list */ | |
1a4f550a | 398 | |
1c57e86d | 399 | atomic_t ccboutstandingcount; |
1a4f550a NC |
400 | /*The present outstanding command number that in the IOP that |
401 | waiting for being handled by FW*/ | |
1c57e86d EC |
402 | |
403 | void * dma_coherent; | |
404 | /* dma_coherent used for memory free */ | |
405 | dma_addr_t dma_coherent_handle; | |
406 | /* dma_coherent_handle used for memory free */ | |
407 | ||
408 | uint8_t rqbuffer[ARCMSR_MAX_QBUFFER]; | |
409 | /* data collection buffer for read from 80331 */ | |
410 | int32_t rqbuf_firstindex; | |
411 | /* first of read buffer */ | |
412 | int32_t rqbuf_lastindex; | |
413 | /* last of read buffer */ | |
414 | uint8_t wqbuffer[ARCMSR_MAX_QBUFFER]; | |
415 | /* data collection buffer for write to 80331 */ | |
416 | int32_t wqbuf_firstindex; | |
417 | /* first of write buffer */ | |
418 | int32_t wqbuf_lastindex; | |
419 | /* last of write buffer */ | |
420 | uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; | |
421 | /* id0 ..... id15, lun0...lun7 */ | |
422 | #define ARECA_RAID_GONE 0x55 | |
423 | #define ARECA_RAID_GOOD 0xaa | |
424 | uint32_t num_resets; | |
425 | uint32_t num_aborts; | |
426 | uint32_t firm_request_len; | |
427 | uint32_t firm_numbers_queue; | |
428 | uint32_t firm_sdram_size; | |
429 | uint32_t firm_hd_channels; | |
430 | char firm_model[12]; | |
431 | char firm_version[20]; | |
432 | };/* HW_DEVICE_EXTENSION */ | |
433 | /* | |
434 | ******************************************************************************* | |
435 | ** Command Control Block | |
436 | ** this CCB length must be 32 bytes boundary | |
437 | ******************************************************************************* | |
438 | */ | |
439 | struct CommandControlBlock | |
440 | { | |
441 | struct ARCMSR_CDB arcmsr_cdb; | |
442 | /* | |
1a4f550a | 443 | ** 0-503 (size of CDB = 504): |
1c57e86d EC |
444 | ** arcmsr messenger scsi command descriptor size 504 bytes |
445 | */ | |
446 | uint32_t cdb_shifted_phyaddr; | |
447 | /* 504-507 */ | |
448 | uint32_t reserved1; | |
449 | /* 508-511 */ | |
450 | #if BITS_PER_LONG == 64 | |
451 | /* ======================512+64 bytes======================== */ | |
452 | struct list_head list; | |
453 | /* 512-527 16 bytes next/prev ptrs for ccb lists */ | |
454 | struct scsi_cmnd * pcmd; | |
455 | /* 528-535 8 bytes pointer of linux scsi command */ | |
456 | struct AdapterControlBlock * acb; | |
457 | /* 536-543 8 bytes pointer of acb */ | |
458 | ||
459 | uint16_t ccb_flags; | |
460 | /* 544-545 */ | |
461 | #define CCB_FLAG_READ 0x0000 | |
462 | #define CCB_FLAG_WRITE 0x0001 | |
463 | #define CCB_FLAG_ERROR 0x0002 | |
464 | #define CCB_FLAG_FLUSHCACHE 0x0004 | |
465 | #define CCB_FLAG_MASTER_ABORTED 0x0008 | |
466 | uint16_t startdone; | |
467 | /* 546-547 */ | |
468 | #define ARCMSR_CCB_DONE 0x0000 | |
469 | #define ARCMSR_CCB_START 0x55AA | |
470 | #define ARCMSR_CCB_ABORTED 0xAA55 | |
471 | #define ARCMSR_CCB_ILLEGAL 0xFFFF | |
472 | uint32_t reserved2[7]; | |
473 | /* 548-551 552-555 556-559 560-563 564-567 568-571 572-575 */ | |
474 | #else | |
475 | /* ======================512+32 bytes======================== */ | |
476 | struct list_head list; | |
477 | /* 512-519 8 bytes next/prev ptrs for ccb lists */ | |
478 | struct scsi_cmnd * pcmd; | |
479 | /* 520-523 4 bytes pointer of linux scsi command */ | |
480 | struct AdapterControlBlock * acb; | |
481 | /* 524-527 4 bytes pointer of acb */ | |
482 | ||
483 | uint16_t ccb_flags; | |
484 | /* 528-529 */ | |
485 | #define CCB_FLAG_READ 0x0000 | |
486 | #define CCB_FLAG_WRITE 0x0001 | |
487 | #define CCB_FLAG_ERROR 0x0002 | |
488 | #define CCB_FLAG_FLUSHCACHE 0x0004 | |
489 | #define CCB_FLAG_MASTER_ABORTED 0x0008 | |
490 | uint16_t startdone; | |
491 | /* 530-531 */ | |
492 | #define ARCMSR_CCB_DONE 0x0000 | |
493 | #define ARCMSR_CCB_START 0x55AA | |
494 | #define ARCMSR_CCB_ABORTED 0xAA55 | |
495 | #define ARCMSR_CCB_ILLEGAL 0xFFFF | |
496 | uint32_t reserved2[3]; | |
497 | /* 532-535 536-539 540-543 */ | |
498 | #endif | |
499 | /* ========================================================== */ | |
500 | }; | |
501 | /* | |
502 | ******************************************************************************* | |
503 | ** ARECA SCSI sense data | |
504 | ******************************************************************************* | |
505 | */ | |
506 | struct SENSE_DATA | |
507 | { | |
508 | uint8_t ErrorCode:7; | |
509 | #define SCSI_SENSE_CURRENT_ERRORS 0x70 | |
510 | #define SCSI_SENSE_DEFERRED_ERRORS 0x71 | |
511 | uint8_t Valid:1; | |
512 | uint8_t SegmentNumber; | |
513 | uint8_t SenseKey:4; | |
514 | uint8_t Reserved:1; | |
515 | uint8_t IncorrectLength:1; | |
516 | uint8_t EndOfMedia:1; | |
517 | uint8_t FileMark:1; | |
518 | uint8_t Information[4]; | |
519 | uint8_t AdditionalSenseLength; | |
520 | uint8_t CommandSpecificInformation[4]; | |
521 | uint8_t AdditionalSenseCode; | |
522 | uint8_t AdditionalSenseCodeQualifier; | |
523 | uint8_t FieldReplaceableUnitCode; | |
524 | uint8_t SenseKeySpecific[3]; | |
525 | }; | |
526 | /* | |
527 | ******************************************************************************* | |
528 | ** Outbound Interrupt Status Register - OISR | |
529 | ******************************************************************************* | |
530 | */ | |
531 | #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 | |
532 | #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 | |
533 | #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 | |
534 | #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 | |
535 | #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 | |
536 | #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 | |
537 | #define ARCMSR_MU_OUTBOUND_HANDLE_INT \ | |
538 | (ARCMSR_MU_OUTBOUND_MESSAGE0_INT \ | |
539 | |ARCMSR_MU_OUTBOUND_MESSAGE1_INT \ | |
540 | |ARCMSR_MU_OUTBOUND_DOORBELL_INT \ | |
541 | |ARCMSR_MU_OUTBOUND_POSTQUEUE_INT \ | |
542 | |ARCMSR_MU_OUTBOUND_PCI_INT) | |
543 | /* | |
544 | ******************************************************************************* | |
545 | ** Outbound Interrupt Mask Register - OIMR | |
546 | ******************************************************************************* | |
547 | */ | |
548 | #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 | |
549 | #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 | |
550 | #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 | |
551 | #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 | |
552 | #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 | |
553 | #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 | |
554 | #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F | |
555 | ||
1a4f550a NC |
556 | extern void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *); |
557 | extern void arcmsr_iop_message_read(struct AdapterControlBlock *); | |
80da1adb | 558 | extern struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *); |
ee959b00 | 559 | extern struct device_attribute *arcmsr_host_attrs[]; |
1a4f550a | 560 | extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *); |
1c57e86d | 561 | void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb); |