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1da177e4 LT |
1 | /* |
2 | * linux/drivers/acorn/scsi/acornscsi.h | |
3 | * | |
4 | * Copyright (C) 1997 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Acorn SCSI driver | |
11 | */ | |
12 | #ifndef ACORNSCSI_H | |
13 | #define ACORNSCSI_H | |
14 | ||
15 | /* SBIC registers */ | |
16 | #define SBIC_OWNID 0 | |
17 | #define OWNID_FS1 (1<<7) | |
18 | #define OWNID_FS2 (1<<6) | |
19 | #define OWNID_EHP (1<<4) | |
20 | #define OWNID_EAF (1<<3) | |
21 | ||
22 | #define SBIC_CTRL 1 | |
23 | #define CTRL_DMAMODE (1<<7) | |
24 | #define CTRL_DMADBAMODE (1<<6) | |
25 | #define CTRL_DMABURST (1<<5) | |
26 | #define CTRL_DMAPOLLED 0 | |
27 | #define CTRL_HHP (1<<4) | |
28 | #define CTRL_EDI (1<<3) | |
29 | #define CTRL_IDI (1<<2) | |
30 | #define CTRL_HA (1<<1) | |
31 | #define CTRL_HSP (1<<0) | |
32 | ||
33 | #define SBIC_TIMEOUT 2 | |
34 | #define SBIC_TOTSECTS 3 | |
35 | #define SBIC_TOTHEADS 4 | |
36 | #define SBIC_TOTCYLH 5 | |
37 | #define SBIC_TOTCYLL 6 | |
38 | #define SBIC_LOGADDRH 7 | |
39 | #define SBIC_LOGADDRM2 8 | |
40 | #define SBIC_LOGADDRM1 9 | |
41 | #define SBIC_LOGADDRL 10 | |
42 | #define SBIC_SECTORNUM 11 | |
43 | #define SBIC_HEADNUM 12 | |
44 | #define SBIC_CYLH 13 | |
45 | #define SBIC_CYLL 14 | |
46 | #define SBIC_TARGETLUN 15 | |
47 | #define TARGETLUN_TLV (1<<7) | |
48 | #define TARGETLUN_DOK (1<<6) | |
49 | ||
50 | #define SBIC_CMNDPHASE 16 | |
51 | #define SBIC_SYNCHTRANSFER 17 | |
52 | #define SYNCHTRANSFER_OF0 0x00 | |
53 | #define SYNCHTRANSFER_OF1 0x01 | |
54 | #define SYNCHTRANSFER_OF2 0x02 | |
55 | #define SYNCHTRANSFER_OF3 0x03 | |
56 | #define SYNCHTRANSFER_OF4 0x04 | |
57 | #define SYNCHTRANSFER_OF5 0x05 | |
58 | #define SYNCHTRANSFER_OF6 0x06 | |
59 | #define SYNCHTRANSFER_OF7 0x07 | |
60 | #define SYNCHTRANSFER_OF8 0x08 | |
61 | #define SYNCHTRANSFER_OF9 0x09 | |
62 | #define SYNCHTRANSFER_OF10 0x0A | |
63 | #define SYNCHTRANSFER_OF11 0x0B | |
64 | #define SYNCHTRANSFER_OF12 0x0C | |
65 | #define SYNCHTRANSFER_8DBA 0x00 | |
66 | #define SYNCHTRANSFER_2DBA 0x20 | |
67 | #define SYNCHTRANSFER_3DBA 0x30 | |
68 | #define SYNCHTRANSFER_4DBA 0x40 | |
69 | #define SYNCHTRANSFER_5DBA 0x50 | |
70 | #define SYNCHTRANSFER_6DBA 0x60 | |
71 | #define SYNCHTRANSFER_7DBA 0x70 | |
72 | ||
73 | #define SBIC_TRANSCNTH 18 | |
74 | #define SBIC_TRANSCNTM 19 | |
75 | #define SBIC_TRANSCNTL 20 | |
76 | #define SBIC_DESTID 21 | |
77 | #define DESTID_SCC (1<<7) | |
78 | #define DESTID_DPD (1<<6) | |
79 | ||
80 | #define SBIC_SOURCEID 22 | |
81 | #define SOURCEID_ER (1<<7) | |
82 | #define SOURCEID_ES (1<<6) | |
83 | #define SOURCEID_DSP (1<<5) | |
84 | #define SOURCEID_SIV (1<<4) | |
85 | ||
86 | #define SBIC_SSR 23 | |
87 | #define SBIC_CMND 24 | |
88 | #define CMND_RESET 0x00 | |
89 | #define CMND_ABORT 0x01 | |
90 | #define CMND_ASSERTATN 0x02 | |
91 | #define CMND_NEGATEACK 0x03 | |
92 | #define CMND_DISCONNECT 0x04 | |
93 | #define CMND_RESELECT 0x05 | |
94 | #define CMND_SELWITHATN 0x06 | |
95 | #define CMND_SELECT 0x07 | |
96 | #define CMND_SELECTATNTRANSFER 0x08 | |
97 | #define CMND_SELECTTRANSFER 0x09 | |
98 | #define CMND_RESELECTRXDATA 0x0A | |
99 | #define CMND_RESELECTTXDATA 0x0B | |
100 | #define CMND_WAITFORSELRECV 0x0C | |
101 | #define CMND_SENDSTATCMD 0x0D | |
102 | #define CMND_SENDDISCONNECT 0x0E | |
103 | #define CMND_SETIDI 0x0F | |
104 | #define CMND_RECEIVECMD 0x10 | |
105 | #define CMND_RECEIVEDTA 0x11 | |
106 | #define CMND_RECEIVEMSG 0x12 | |
107 | #define CMND_RECEIVEUSP 0x13 | |
108 | #define CMND_SENDCMD 0x14 | |
109 | #define CMND_SENDDATA 0x15 | |
110 | #define CMND_SENDMSG 0x16 | |
111 | #define CMND_SENDUSP 0x17 | |
112 | #define CMND_TRANSLATEADDR 0x18 | |
113 | #define CMND_XFERINFO 0x20 | |
114 | #define CMND_SBT (1<<7) | |
115 | ||
116 | #define SBIC_DATA 25 | |
117 | #define SBIC_ASR 26 | |
118 | #define ASR_INT (1<<7) | |
119 | #define ASR_LCI (1<<6) | |
120 | #define ASR_BSY (1<<5) | |
121 | #define ASR_CIP (1<<4) | |
122 | #define ASR_PE (1<<1) | |
123 | #define ASR_DBR (1<<0) | |
124 | ||
125 | /* DMAC registers */ | |
126 | #define DMAC_INIT 0x00 | |
127 | #define INIT_8BIT (1) | |
128 | ||
129 | #define DMAC_CHANNEL 0x80 | |
130 | #define CHANNEL_0 0x00 | |
131 | #define CHANNEL_1 0x01 | |
132 | #define CHANNEL_2 0x02 | |
133 | #define CHANNEL_3 0x03 | |
134 | ||
135 | #define DMAC_TXCNTLO 0x01 | |
136 | #define DMAC_TXCNTHI 0x81 | |
137 | #define DMAC_TXADRLO 0x02 | |
138 | #define DMAC_TXADRMD 0x82 | |
139 | #define DMAC_TXADRHI 0x03 | |
140 | ||
141 | #define DMAC_DEVCON0 0x04 | |
142 | #define DEVCON0_AKL (1<<7) | |
143 | #define DEVCON0_RQL (1<<6) | |
144 | #define DEVCON0_EXW (1<<5) | |
145 | #define DEVCON0_ROT (1<<4) | |
146 | #define DEVCON0_CMP (1<<3) | |
147 | #define DEVCON0_DDMA (1<<2) | |
148 | #define DEVCON0_AHLD (1<<1) | |
149 | #define DEVCON0_MTM (1<<0) | |
150 | ||
151 | #define DMAC_DEVCON1 0x84 | |
152 | #define DEVCON1_WEV (1<<1) | |
153 | #define DEVCON1_BHLD (1<<0) | |
154 | ||
155 | #define DMAC_MODECON 0x05 | |
156 | #define MODECON_WOED 0x01 | |
157 | #define MODECON_VERIFY 0x00 | |
158 | #define MODECON_READ 0x04 | |
159 | #define MODECON_WRITE 0x08 | |
160 | #define MODECON_AUTOINIT 0x10 | |
161 | #define MODECON_ADDRDIR 0x20 | |
162 | #define MODECON_DEMAND 0x00 | |
163 | #define MODECON_SINGLE 0x40 | |
164 | #define MODECON_BLOCK 0x80 | |
165 | #define MODECON_CASCADE 0xC0 | |
166 | ||
167 | #define DMAC_STATUS 0x85 | |
168 | #define STATUS_TC0 (1<<0) | |
169 | #define STATUS_RQ0 (1<<4) | |
170 | ||
171 | #define DMAC_TEMPLO 0x06 | |
172 | #define DMAC_TEMPHI 0x86 | |
173 | #define DMAC_REQREG 0x07 | |
174 | #define DMAC_MASKREG 0x87 | |
175 | #define MASKREG_M0 0x01 | |
176 | #define MASKREG_M1 0x02 | |
177 | #define MASKREG_M2 0x04 | |
178 | #define MASKREG_M3 0x08 | |
179 | ||
180 | /* miscellaneous internal variables */ | |
181 | ||
1da177e4 LT |
182 | #define MASK_ON (MASKREG_M3|MASKREG_M2|MASKREG_M1|MASKREG_M0) |
183 | #define MASK_OFF (MASKREG_M3|MASKREG_M2|MASKREG_M1) | |
184 | ||
185 | /* | |
186 | * SCSI driver phases | |
187 | */ | |
188 | typedef enum { | |
189 | PHASE_IDLE, /* we're not planning on doing anything */ | |
190 | PHASE_CONNECTING, /* connecting to a target */ | |
191 | PHASE_CONNECTED, /* connected to a target */ | |
192 | PHASE_MSGOUT, /* message out to device */ | |
193 | PHASE_RECONNECTED, /* reconnected */ | |
194 | PHASE_COMMANDPAUSED, /* command partly sent */ | |
195 | PHASE_COMMAND, /* command all sent */ | |
196 | PHASE_DATAOUT, /* data out to device */ | |
197 | PHASE_DATAIN, /* data in from device */ | |
198 | PHASE_STATUSIN, /* status in from device */ | |
199 | PHASE_MSGIN, /* message in from device */ | |
200 | PHASE_DONE, /* finished */ | |
201 | PHASE_ABORTED, /* aborted */ | |
202 | PHASE_DISCONNECT, /* disconnecting */ | |
203 | } phase_t; | |
204 | ||
205 | /* | |
206 | * After interrupt, what to do now | |
207 | */ | |
208 | typedef enum { | |
209 | INTR_IDLE, /* not expecting another IRQ */ | |
210 | INTR_NEXT_COMMAND, /* start next command */ | |
211 | INTR_PROCESSING, /* interrupt routine still processing */ | |
212 | } intr_ret_t; | |
213 | ||
214 | /* | |
215 | * DMA direction | |
216 | */ | |
217 | typedef enum { | |
218 | DMA_OUT, /* DMA from memory to chip */ | |
219 | DMA_IN /* DMA from chip to memory */ | |
220 | } dmadir_t; | |
221 | ||
222 | /* | |
223 | * Synchronous transfer state | |
224 | */ | |
225 | typedef enum { /* Synchronous transfer state */ | |
25985edc LDM |
226 | SYNC_ASYNCHRONOUS, /* don't negotiate synchronous transfers*/ |
227 | SYNC_NEGOCIATE, /* start negotiation */ | |
1da177e4 LT |
228 | SYNC_SENT_REQUEST, /* sent SDTR message */ |
229 | SYNC_COMPLETED, /* received SDTR reply */ | |
230 | } syncxfer_t; | |
231 | ||
232 | /* | |
233 | * Command type | |
234 | */ | |
235 | typedef enum { /* command type */ | |
236 | CMD_READ, /* READ_6, READ_10, READ_12 */ | |
237 | CMD_WRITE, /* WRITE_6, WRITE_10, WRITE_12 */ | |
238 | CMD_MISC, /* Others */ | |
239 | } cmdtype_t; | |
240 | ||
241 | /* | |
242 | * Data phase direction | |
243 | */ | |
244 | typedef enum { /* Data direction */ | |
245 | DATADIR_IN, /* Data in phase expected */ | |
246 | DATADIR_OUT /* Data out phase expected */ | |
247 | } datadir_t; | |
248 | ||
249 | #include "queue.h" | |
250 | #include "msgqueue.h" | |
251 | ||
252 | #define STATUS_BUFFER_SIZE 32 | |
253 | /* | |
254 | * This is used to dump the previous states of the SBIC | |
255 | */ | |
256 | struct status_entry { | |
257 | unsigned long when; | |
258 | unsigned char ssr; | |
259 | unsigned char ph; | |
260 | unsigned char irq; | |
261 | unsigned char unused; | |
262 | }; | |
263 | ||
264 | #define ADD_STATUS(_q,_ssr,_ph,_irq) \ | |
265 | ({ \ | |
266 | host->status[(_q)][host->status_ptr[(_q)]].when = jiffies; \ | |
267 | host->status[(_q)][host->status_ptr[(_q)]].ssr = (_ssr); \ | |
268 | host->status[(_q)][host->status_ptr[(_q)]].ph = (_ph); \ | |
269 | host->status[(_q)][host->status_ptr[(_q)]].irq = (_irq); \ | |
270 | host->status_ptr[(_q)] = (host->status_ptr[(_q)] + 1) & (STATUS_BUFFER_SIZE - 1); \ | |
271 | }) | |
272 | ||
273 | /* | |
274 | * AcornSCSI host specific data | |
275 | */ | |
276 | typedef struct acornscsi_hostdata { | |
277 | /* miscellaneous */ | |
278 | struct Scsi_Host *host; /* host */ | |
ee0ca6ba H |
279 | struct scsi_cmnd *SCpnt; /* currently processing command */ |
280 | struct scsi_cmnd *origSCpnt; /* original connecting command */ | |
e95a1b65 RK |
281 | void __iomem *base; /* memc base address */ |
282 | void __iomem *fast; /* fast ioc base address */ | |
1da177e4 LT |
283 | |
284 | /* driver information */ | |
285 | struct { | |
1da177e4 LT |
286 | unsigned int irq; /* interrupt */ |
287 | phase_t phase; /* current phase */ | |
288 | ||
289 | struct { | |
290 | unsigned char target; /* reconnected target */ | |
291 | unsigned char lun; /* reconnected lun */ | |
292 | unsigned char tag; /* reconnected tag */ | |
293 | } reconnected; | |
294 | ||
0a04137e | 295 | struct scsi_pointer SCp; /* current commands data pointer */ |
1da177e4 LT |
296 | |
297 | MsgQueue_t msgs; | |
298 | ||
299 | unsigned short last_message; /* last message to be sent */ | |
300 | unsigned char disconnectable:1; /* this command can be disconnected */ | |
301 | } scsi; | |
302 | ||
303 | /* statistics information */ | |
304 | struct { | |
305 | unsigned int queues; | |
306 | unsigned int removes; | |
307 | unsigned int fins; | |
308 | unsigned int reads; | |
309 | unsigned int writes; | |
310 | unsigned int miscs; | |
311 | unsigned int disconnects; | |
312 | unsigned int aborts; | |
313 | unsigned int resets; | |
314 | } stats; | |
315 | ||
316 | /* queue handling */ | |
317 | struct { | |
318 | Queue_t issue; /* issue queue */ | |
319 | Queue_t disconnected; /* disconnected command queue */ | |
320 | } queues; | |
321 | ||
322 | /* per-device info */ | |
323 | struct { | |
324 | unsigned char sync_xfer; /* synchronous transfer (SBIC value) */ | |
25985edc | 325 | syncxfer_t sync_state; /* sync xfer negotiation state */ |
1da177e4 LT |
326 | unsigned char disconnect_ok:1; /* device can disconnect */ |
327 | } device[8]; | |
328 | unsigned long busyluns[64 / sizeof(unsigned long)];/* array of bits indicating LUNs busy */ | |
329 | ||
330 | /* DMA info */ | |
331 | struct { | |
1da177e4 LT |
332 | unsigned int free_addr; /* next free address */ |
333 | unsigned int start_addr; /* start address of current transfer */ | |
334 | dmadir_t direction; /* dma direction */ | |
335 | unsigned int transferred; /* number of bytes transferred */ | |
336 | unsigned int xfer_start; /* scheduled DMA transfer start */ | |
337 | unsigned int xfer_length; /* scheduled DMA transfer length */ | |
338 | char *xfer_ptr; /* pointer to area */ | |
339 | unsigned char xfer_required:1; /* set if we need to transfer something */ | |
340 | unsigned char xfer_setup:1; /* set if DMA is setup */ | |
341 | unsigned char xfer_done:1; /* set if DMA reached end of BH list */ | |
342 | } dma; | |
343 | ||
344 | /* card info */ | |
345 | struct { | |
1da177e4 LT |
346 | unsigned char page_reg; /* current setting of page reg */ |
347 | } card; | |
348 | ||
349 | unsigned char status_ptr[9]; | |
350 | struct status_entry status[9][STATUS_BUFFER_SIZE]; | |
351 | } AS_Host; | |
352 | ||
353 | #endif /* ACORNSCSI_H */ |