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1da177e4 | 1 | /* |
af36d7f0 JG |
2 | * ata_piix.c - Intel PATA/SATA controllers |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * | |
9 | * Copyright 2003-2005 Red Hat Inc | |
10 | * Copyright 2003-2005 Jeff Garzik | |
11 | * | |
12 | * | |
13 | * Copyright header from piix.c: | |
14 | * | |
15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
17 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
18 | * | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2, or (at your option) | |
23 | * any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; see the file COPYING. If not, write to | |
32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
33 | * | |
34 | * | |
35 | * libata documentation is available via 'make {ps|pdf}docs', | |
36 | * as Documentation/DocBook/libata.* | |
37 | * | |
38 | * Hardware documentation available at http://developer.intel.com/ | |
39 | * | |
d96212ed AC |
40 | * Documentation |
41 | * Publically available from Intel web site. Errata documentation | |
42 | * is also publically available. As an aide to anyone hacking on this | |
43 | * driver the list of errata that are relevant is below.going back to | |
44 | * PIIX4. Older device documentation is now a bit tricky to find. | |
45 | * | |
46 | * The chipsets all follow very much the same design. The orginal Triton | |
47 | * series chipsets do _not_ support independant device timings, but this | |
48 | * is fixed in Triton II. With the odd mobile exception the chips then | |
49 | * change little except in gaining more modes until SATA arrives. This | |
50 | * driver supports only the chips with independant timing (that is those | |
51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix | |
52 | * for the early chip drivers. | |
53 | * | |
54 | * Errata of note: | |
55 | * | |
56 | * Unfixable | |
57 | * PIIX4 errata #9 - Only on ultra obscure hw | |
58 | * ICH3 errata #13 - Not observed to affect real hw | |
59 | * by Intel | |
60 | * | |
61 | * Things we must deal with | |
62 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
63 | * (must stop/start dma to recover) | |
64 | * 440MX errata #15 - As PIIX4 errata #10 | |
65 | * PIIX4 errata #15 - Must not read control registers | |
66 | * during a PIO transfer | |
67 | * 440MX errata #13 - As PIIX4 errata #15 | |
68 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
69 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
70 | * ICH2 spec c #9 - Extra operations needed to handle | |
71 | * drive hotswap [NOT YET SUPPORTED] | |
72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
73 | * and must be dword aligned | |
74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
75 | * | |
76 | * Should have been BIOS fixed: | |
77 | * 450NX: errata #19 - DMA hangs on old 450NX | |
78 | * 450NX: errata #20 - DMA hangs on old 450NX | |
79 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
80 | * ICH3 errata #15 - IDE deadlock under high load | |
81 | * (BIOS must set dev 31 fn 0 bit 23) | |
82 | * ICH3 errata #18 - Don't use native mode | |
1da177e4 LT |
83 | */ |
84 | ||
85 | #include <linux/kernel.h> | |
86 | #include <linux/module.h> | |
87 | #include <linux/pci.h> | |
88 | #include <linux/init.h> | |
89 | #include <linux/blkdev.h> | |
90 | #include <linux/delay.h> | |
6248e647 | 91 | #include <linux/device.h> |
1da177e4 LT |
92 | #include <scsi/scsi_host.h> |
93 | #include <linux/libata.h> | |
94 | ||
95 | #define DRV_NAME "ata_piix" | |
7bdd7208 | 96 | #define DRV_VERSION "1.05" |
1da177e4 LT |
97 | |
98 | enum { | |
99 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ | |
100 | ICH5_PMR = 0x90, /* port mapping register */ | |
101 | ICH5_PCS = 0x92, /* port control and status */ | |
7b6dbd68 | 102 | PIIX_SCC = 0x0A, /* sub-class code register */ |
1da177e4 LT |
103 | |
104 | PIIX_FLAG_AHCI = (1 << 28), /* AHCI possible */ | |
105 | PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */ | |
106 | PIIX_FLAG_COMBINED = (1 << 30), /* combined mode possible */ | |
107 | ||
108 | /* combined mode. if set, PATA is channel 0. | |
109 | * if clear, PATA is channel 1. | |
110 | */ | |
111 | PIIX_COMB_PATA_P0 = (1 << 1), | |
112 | PIIX_COMB = (1 << 2), /* combined mode enabled? */ | |
113 | ||
6a690df5 HR |
114 | PIIX_PORT_ENABLED = (1 << 0), |
115 | PIIX_PORT_PRESENT = (1 << 4), | |
1da177e4 LT |
116 | |
117 | PIIX_80C_PRI = (1 << 5) | (1 << 4), | |
118 | PIIX_80C_SEC = (1 << 7) | (1 << 6), | |
119 | ||
120 | ich5_pata = 0, | |
121 | ich5_sata = 1, | |
122 | piix4_pata = 2, | |
123 | ich6_sata = 3, | |
1c24a412 | 124 | ich6_sata_ahci = 4, |
7b6dbd68 GF |
125 | |
126 | PIIX_AHCI_DEVICE = 6, | |
1da177e4 LT |
127 | }; |
128 | ||
129 | static int piix_init_one (struct pci_dev *pdev, | |
130 | const struct pci_device_id *ent); | |
131 | ||
132 | static void piix_pata_phy_reset(struct ata_port *ap); | |
133 | static void piix_sata_phy_reset(struct ata_port *ap); | |
134 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev); | |
135 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev); | |
136 | ||
137 | static unsigned int in_module_init = 1; | |
138 | ||
3b7d697d | 139 | static const struct pci_device_id piix_pci_tbl[] = { |
1da177e4 LT |
140 | #ifdef ATA_ENABLE_PATA |
141 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata }, | |
142 | { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata }, | |
143 | { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata }, | |
144 | #endif | |
145 | ||
146 | /* NOTE: The following PCI ids must be kept in sync with the | |
147 | * list in drivers/pci/quirks.c. | |
148 | */ | |
149 | ||
150 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, | |
151 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, | |
152 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, | |
153 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, | |
154 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, | |
1c24a412 JG |
155 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
156 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, | |
157 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, | |
158 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, | |
159 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, | |
1da177e4 LT |
160 | |
161 | { } /* terminate list */ | |
162 | }; | |
163 | ||
164 | static struct pci_driver piix_pci_driver = { | |
165 | .name = DRV_NAME, | |
166 | .id_table = piix_pci_tbl, | |
167 | .probe = piix_init_one, | |
168 | .remove = ata_pci_remove_one, | |
169 | }; | |
170 | ||
193515d5 | 171 | static struct scsi_host_template piix_sht = { |
1da177e4 LT |
172 | .module = THIS_MODULE, |
173 | .name = DRV_NAME, | |
174 | .ioctl = ata_scsi_ioctl, | |
175 | .queuecommand = ata_scsi_queuecmd, | |
176 | .eh_strategy_handler = ata_scsi_error, | |
177 | .can_queue = ATA_DEF_QUEUE, | |
178 | .this_id = ATA_SHT_THIS_ID, | |
179 | .sg_tablesize = LIBATA_MAX_PRD, | |
180 | .max_sectors = ATA_MAX_SECTORS, | |
181 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
182 | .emulated = ATA_SHT_EMULATED, | |
183 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
184 | .proc_name = DRV_NAME, | |
185 | .dma_boundary = ATA_DMA_BOUNDARY, | |
186 | .slave_configure = ata_scsi_slave_config, | |
187 | .bios_param = ata_std_bios_param, | |
188 | .ordered_flush = 1, | |
189 | }; | |
190 | ||
057ace5e | 191 | static const struct ata_port_operations piix_pata_ops = { |
1da177e4 LT |
192 | .port_disable = ata_port_disable, |
193 | .set_piomode = piix_set_piomode, | |
194 | .set_dmamode = piix_set_dmamode, | |
195 | ||
196 | .tf_load = ata_tf_load, | |
197 | .tf_read = ata_tf_read, | |
198 | .check_status = ata_check_status, | |
199 | .exec_command = ata_exec_command, | |
200 | .dev_select = ata_std_dev_select, | |
201 | ||
202 | .phy_reset = piix_pata_phy_reset, | |
203 | ||
204 | .bmdma_setup = ata_bmdma_setup, | |
205 | .bmdma_start = ata_bmdma_start, | |
206 | .bmdma_stop = ata_bmdma_stop, | |
207 | .bmdma_status = ata_bmdma_status, | |
208 | .qc_prep = ata_qc_prep, | |
209 | .qc_issue = ata_qc_issue_prot, | |
210 | ||
211 | .eng_timeout = ata_eng_timeout, | |
212 | ||
213 | .irq_handler = ata_interrupt, | |
214 | .irq_clear = ata_bmdma_irq_clear, | |
215 | ||
216 | .port_start = ata_port_start, | |
217 | .port_stop = ata_port_stop, | |
aa8f0dc6 | 218 | .host_stop = ata_host_stop, |
1da177e4 LT |
219 | }; |
220 | ||
057ace5e | 221 | static const struct ata_port_operations piix_sata_ops = { |
1da177e4 LT |
222 | .port_disable = ata_port_disable, |
223 | ||
224 | .tf_load = ata_tf_load, | |
225 | .tf_read = ata_tf_read, | |
226 | .check_status = ata_check_status, | |
227 | .exec_command = ata_exec_command, | |
228 | .dev_select = ata_std_dev_select, | |
229 | ||
230 | .phy_reset = piix_sata_phy_reset, | |
231 | ||
232 | .bmdma_setup = ata_bmdma_setup, | |
233 | .bmdma_start = ata_bmdma_start, | |
234 | .bmdma_stop = ata_bmdma_stop, | |
235 | .bmdma_status = ata_bmdma_status, | |
236 | .qc_prep = ata_qc_prep, | |
237 | .qc_issue = ata_qc_issue_prot, | |
238 | ||
239 | .eng_timeout = ata_eng_timeout, | |
240 | ||
241 | .irq_handler = ata_interrupt, | |
242 | .irq_clear = ata_bmdma_irq_clear, | |
243 | ||
244 | .port_start = ata_port_start, | |
245 | .port_stop = ata_port_stop, | |
aa8f0dc6 | 246 | .host_stop = ata_host_stop, |
1da177e4 LT |
247 | }; |
248 | ||
249 | static struct ata_port_info piix_port_info[] = { | |
250 | /* ich5_pata */ | |
251 | { | |
252 | .sht = &piix_sht, | |
253 | .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | | |
254 | PIIX_FLAG_CHECKINTR, | |
255 | .pio_mask = 0x1f, /* pio0-4 */ | |
256 | #if 0 | |
257 | .mwdma_mask = 0x06, /* mwdma1-2 */ | |
258 | #else | |
259 | .mwdma_mask = 0x00, /* mwdma broken */ | |
260 | #endif | |
261 | .udma_mask = 0x3f, /* udma0-5 */ | |
262 | .port_ops = &piix_pata_ops, | |
263 | }, | |
264 | ||
265 | /* ich5_sata */ | |
266 | { | |
267 | .sht = &piix_sht, | |
268 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST | | |
269 | PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR, | |
270 | .pio_mask = 0x1f, /* pio0-4 */ | |
271 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
272 | .udma_mask = 0x7f, /* udma0-6 */ | |
273 | .port_ops = &piix_sata_ops, | |
274 | }, | |
275 | ||
276 | /* piix4_pata */ | |
277 | { | |
278 | .sht = &piix_sht, | |
279 | .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
280 | .pio_mask = 0x1f, /* pio0-4 */ | |
281 | #if 0 | |
282 | .mwdma_mask = 0x06, /* mwdma1-2 */ | |
283 | #else | |
284 | .mwdma_mask = 0x00, /* mwdma broken */ | |
285 | #endif | |
286 | .udma_mask = ATA_UDMA_MASK_40C, | |
287 | .port_ops = &piix_pata_ops, | |
288 | }, | |
289 | ||
290 | /* ich6_sata */ | |
291 | { | |
292 | .sht = &piix_sht, | |
293 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST | | |
294 | PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR | | |
295 | ATA_FLAG_SLAVE_POSS, | |
296 | .pio_mask = 0x1f, /* pio0-4 */ | |
297 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
298 | .udma_mask = 0x7f, /* udma0-6 */ | |
299 | .port_ops = &piix_sata_ops, | |
300 | }, | |
301 | ||
1c24a412 | 302 | /* ich6_sata_ahci */ |
c368ca4e JG |
303 | { |
304 | .sht = &piix_sht, | |
305 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST | | |
306 | PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR | | |
307 | ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI, | |
308 | .pio_mask = 0x1f, /* pio0-4 */ | |
309 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
310 | .udma_mask = 0x7f, /* udma0-6 */ | |
311 | .port_ops = &piix_sata_ops, | |
312 | }, | |
1da177e4 LT |
313 | }; |
314 | ||
315 | static struct pci_bits piix_enable_bits[] = { | |
316 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ | |
317 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ | |
318 | }; | |
319 | ||
320 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); | |
321 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); | |
322 | MODULE_LICENSE("GPL"); | |
323 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
324 | MODULE_VERSION(DRV_VERSION); | |
325 | ||
326 | /** | |
327 | * piix_pata_cbl_detect - Probe host controller cable detect info | |
328 | * @ap: Port for which cable detect info is desired | |
329 | * | |
330 | * Read 80c cable indicator from ATA PCI device's PCI config | |
331 | * register. This register is normally set by firmware (BIOS). | |
332 | * | |
333 | * LOCKING: | |
334 | * None (inherited from caller). | |
335 | */ | |
336 | static void piix_pata_cbl_detect(struct ata_port *ap) | |
337 | { | |
338 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | |
339 | u8 tmp, mask; | |
340 | ||
341 | /* no 80c support in host controller? */ | |
342 | if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0) | |
343 | goto cbl40; | |
344 | ||
345 | /* check BIOS cable detect results */ | |
346 | mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; | |
347 | pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); | |
348 | if ((tmp & mask) == 0) | |
349 | goto cbl40; | |
350 | ||
351 | ap->cbl = ATA_CBL_PATA80; | |
352 | return; | |
353 | ||
354 | cbl40: | |
355 | ap->cbl = ATA_CBL_PATA40; | |
356 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
357 | } | |
358 | ||
359 | /** | |
360 | * piix_pata_phy_reset - Probe specified port on PATA host controller | |
361 | * @ap: Port to probe | |
362 | * | |
363 | * Probe PATA phy. | |
364 | * | |
365 | * LOCKING: | |
366 | * None (inherited from caller). | |
367 | */ | |
368 | ||
369 | static void piix_pata_phy_reset(struct ata_port *ap) | |
370 | { | |
371 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | |
372 | ||
373 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) { | |
374 | ata_port_disable(ap); | |
375 | printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id); | |
376 | return; | |
377 | } | |
378 | ||
379 | piix_pata_cbl_detect(ap); | |
380 | ||
381 | ata_port_probe(ap); | |
382 | ||
383 | ata_bus_reset(ap); | |
384 | } | |
385 | ||
386 | /** | |
387 | * piix_sata_probe - Probe PCI device for present SATA devices | |
388 | * @ap: Port associated with the PCI device we wish to probe | |
389 | * | |
390 | * Reads SATA PCI device's PCI config register Port Configuration | |
391 | * and Status (PCS) to determine port and device availability. | |
392 | * | |
393 | * LOCKING: | |
394 | * None (inherited from caller). | |
395 | * | |
396 | * RETURNS: | |
6a690df5 HR |
397 | * Non-zero if port is enabled, it may or may not have a device |
398 | * attached in that case (PRESENT bit would only be set if BIOS probe | |
399 | * was done). Zero is returned if port is disabled. | |
1da177e4 LT |
400 | */ |
401 | static int piix_sata_probe (struct ata_port *ap) | |
402 | { | |
403 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | |
404 | int combined = (ap->flags & ATA_FLAG_SLAVE_POSS); | |
405 | int orig_mask, mask, i; | |
406 | u8 pcs; | |
407 | ||
408 | mask = (PIIX_PORT_PRESENT << ap->hard_port_no) | | |
409 | (PIIX_PORT_ENABLED << ap->hard_port_no); | |
410 | ||
411 | pci_read_config_byte(pdev, ICH5_PCS, &pcs); | |
412 | orig_mask = (int) pcs & 0xff; | |
413 | ||
414 | /* TODO: this is vaguely wrong for ICH6 combined mode, | |
415 | * where only two of the four SATA ports are mapped | |
416 | * onto a single ATA channel. It is also vaguely inaccurate | |
417 | * for ICH5, which has only two ports. However, this is ok, | |
418 | * as further device presence detection code will handle | |
419 | * any false positives produced here. | |
420 | */ | |
421 | ||
422 | for (i = 0; i < 4; i++) { | |
6a690df5 | 423 | mask = (PIIX_PORT_ENABLED << i); |
1da177e4 LT |
424 | |
425 | if ((orig_mask & mask) == mask) | |
426 | if (combined || (i == ap->hard_port_no)) | |
427 | return 1; | |
428 | } | |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
433 | /** | |
434 | * piix_sata_phy_reset - Probe specified port on SATA host controller | |
435 | * @ap: Port to probe | |
436 | * | |
437 | * Probe SATA phy. | |
438 | * | |
439 | * LOCKING: | |
440 | * None (inherited from caller). | |
441 | */ | |
442 | ||
443 | static void piix_sata_phy_reset(struct ata_port *ap) | |
444 | { | |
445 | if (!piix_sata_probe(ap)) { | |
446 | ata_port_disable(ap); | |
447 | printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id); | |
448 | return; | |
449 | } | |
450 | ||
451 | ap->cbl = ATA_CBL_SATA; | |
452 | ||
453 | ata_port_probe(ap); | |
454 | ||
455 | ata_bus_reset(ap); | |
456 | } | |
457 | ||
458 | /** | |
459 | * piix_set_piomode - Initialize host controller PATA PIO timings | |
460 | * @ap: Port whose timings we are configuring | |
461 | * @adev: um | |
1da177e4 LT |
462 | * |
463 | * Set PIO mode for device, in host controller PCI config space. | |
464 | * | |
465 | * LOCKING: | |
466 | * None (inherited from caller). | |
467 | */ | |
468 | ||
469 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
470 | { | |
471 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
472 | struct pci_dev *dev = to_pci_dev(ap->host_set->dev); | |
473 | unsigned int is_slave = (adev->devno != 0); | |
474 | unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40; | |
475 | unsigned int slave_port = 0x44; | |
476 | u16 master_data; | |
477 | u8 slave_data; | |
478 | ||
479 | static const /* ISP RTC */ | |
480 | u8 timings[][2] = { { 0, 0 }, | |
481 | { 0, 0 }, | |
482 | { 1, 0 }, | |
483 | { 2, 1 }, | |
484 | { 2, 3 }, }; | |
485 | ||
486 | pci_read_config_word(dev, master_port, &master_data); | |
487 | if (is_slave) { | |
488 | master_data |= 0x4000; | |
489 | /* enable PPE, IE and TIME */ | |
490 | master_data |= 0x0070; | |
491 | pci_read_config_byte(dev, slave_port, &slave_data); | |
492 | slave_data &= (ap->hard_port_no ? 0x0f : 0xf0); | |
493 | slave_data |= | |
494 | (timings[pio][0] << 2) | | |
495 | (timings[pio][1] << (ap->hard_port_no ? 4 : 0)); | |
496 | } else { | |
497 | master_data &= 0xccf8; | |
498 | /* enable PPE, IE and TIME */ | |
499 | master_data |= 0x0007; | |
500 | master_data |= | |
501 | (timings[pio][0] << 12) | | |
502 | (timings[pio][1] << 8); | |
503 | } | |
504 | pci_write_config_word(dev, master_port, master_data); | |
505 | if (is_slave) | |
506 | pci_write_config_byte(dev, slave_port, slave_data); | |
507 | } | |
508 | ||
509 | /** | |
510 | * piix_set_dmamode - Initialize host controller PATA PIO timings | |
511 | * @ap: Port whose timings we are configuring | |
512 | * @adev: um | |
513 | * @udma: udma mode, 0 - 6 | |
514 | * | |
515 | * Set UDMA mode for device, in host controller PCI config space. | |
516 | * | |
517 | * LOCKING: | |
518 | * None (inherited from caller). | |
519 | */ | |
520 | ||
521 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
522 | { | |
523 | unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */ | |
524 | struct pci_dev *dev = to_pci_dev(ap->host_set->dev); | |
525 | u8 maslave = ap->hard_port_no ? 0x42 : 0x40; | |
526 | u8 speed = udma; | |
527 | unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno; | |
528 | int a_speed = 3 << (drive_dn * 4); | |
529 | int u_flag = 1 << drive_dn; | |
530 | int v_flag = 0x01 << drive_dn; | |
531 | int w_flag = 0x10 << drive_dn; | |
532 | int u_speed = 0; | |
533 | int sitre; | |
534 | u16 reg4042, reg4a; | |
535 | u8 reg48, reg54, reg55; | |
536 | ||
537 | pci_read_config_word(dev, maslave, ®4042); | |
538 | DPRINTK("reg4042 = 0x%04x\n", reg4042); | |
539 | sitre = (reg4042 & 0x4000) ? 1 : 0; | |
540 | pci_read_config_byte(dev, 0x48, ®48); | |
541 | pci_read_config_word(dev, 0x4a, ®4a); | |
542 | pci_read_config_byte(dev, 0x54, ®54); | |
543 | pci_read_config_byte(dev, 0x55, ®55); | |
544 | ||
545 | switch(speed) { | |
546 | case XFER_UDMA_4: | |
547 | case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break; | |
548 | case XFER_UDMA_6: | |
549 | case XFER_UDMA_5: | |
550 | case XFER_UDMA_3: | |
551 | case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break; | |
552 | case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break; | |
553 | case XFER_MW_DMA_2: | |
554 | case XFER_MW_DMA_1: break; | |
555 | default: | |
556 | BUG(); | |
557 | return; | |
558 | } | |
559 | ||
560 | if (speed >= XFER_UDMA_0) { | |
561 | if (!(reg48 & u_flag)) | |
562 | pci_write_config_byte(dev, 0x48, reg48 | u_flag); | |
563 | if (speed == XFER_UDMA_5) { | |
564 | pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag); | |
565 | } else { | |
566 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
567 | } | |
568 | if ((reg4a & a_speed) != u_speed) | |
569 | pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed); | |
570 | if (speed > XFER_UDMA_2) { | |
571 | if (!(reg54 & v_flag)) | |
572 | pci_write_config_byte(dev, 0x54, reg54 | v_flag); | |
573 | } else | |
574 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
575 | } else { | |
576 | if (reg48 & u_flag) | |
577 | pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); | |
578 | if (reg4a & a_speed) | |
579 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
580 | if (reg54 & v_flag) | |
581 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
582 | if (reg55 & w_flag) | |
583 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
584 | } | |
585 | } | |
586 | ||
1da177e4 LT |
587 | #define AHCI_PCI_BAR 5 |
588 | #define AHCI_GLOBAL_CTL 0x04 | |
589 | #define AHCI_ENABLE (1 << 31) | |
590 | static int piix_disable_ahci(struct pci_dev *pdev) | |
591 | { | |
ea6ba10b | 592 | void __iomem *mmio; |
1da177e4 LT |
593 | u32 tmp; |
594 | int rc = 0; | |
595 | ||
596 | /* BUG: pci_enable_device has not yet been called. This | |
597 | * works because this device is usually set up by BIOS. | |
598 | */ | |
599 | ||
374b1873 JG |
600 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
601 | !pci_resource_len(pdev, AHCI_PCI_BAR)) | |
1da177e4 | 602 | return 0; |
7b6dbd68 | 603 | |
374b1873 | 604 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
1da177e4 LT |
605 | if (!mmio) |
606 | return -ENOMEM; | |
7b6dbd68 | 607 | |
1da177e4 LT |
608 | tmp = readl(mmio + AHCI_GLOBAL_CTL); |
609 | if (tmp & AHCI_ENABLE) { | |
610 | tmp &= ~AHCI_ENABLE; | |
611 | writel(tmp, mmio + AHCI_GLOBAL_CTL); | |
612 | ||
613 | tmp = readl(mmio + AHCI_GLOBAL_CTL); | |
614 | if (tmp & AHCI_ENABLE) | |
615 | rc = -EIO; | |
616 | } | |
7b6dbd68 | 617 | |
374b1873 | 618 | pci_iounmap(pdev, mmio); |
1da177e4 LT |
619 | return rc; |
620 | } | |
621 | ||
622 | /** | |
623 | * piix_init_one - Register PIIX ATA PCI device with kernel services | |
624 | * @pdev: PCI device to register | |
625 | * @ent: Entry in piix_pci_tbl matching with @pdev | |
626 | * | |
627 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
628 | * and then hand over control to libata, for it to do the rest. | |
629 | * | |
630 | * LOCKING: | |
631 | * Inherited from PCI layer (may sleep). | |
632 | * | |
633 | * RETURNS: | |
634 | * Zero on success, or -ERRNO value. | |
635 | */ | |
636 | ||
637 | static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
638 | { | |
639 | static int printed_version; | |
640 | struct ata_port_info *port_info[2]; | |
fbf30fba | 641 | unsigned int combined = 0; |
1da177e4 LT |
642 | unsigned int pata_chan = 0, sata_chan = 0; |
643 | ||
644 | if (!printed_version++) | |
6248e647 JG |
645 | dev_printk(KERN_DEBUG, &pdev->dev, |
646 | "version " DRV_VERSION "\n"); | |
1da177e4 LT |
647 | |
648 | /* no hotplugging support (FIXME) */ | |
649 | if (!in_module_init) | |
650 | return -ENODEV; | |
651 | ||
652 | port_info[0] = &piix_port_info[ent->driver_data]; | |
fbf30fba | 653 | port_info[1] = &piix_port_info[ent->driver_data]; |
1da177e4 LT |
654 | |
655 | if (port_info[0]->host_flags & PIIX_FLAG_AHCI) { | |
8a60a071 JG |
656 | u8 tmp; |
657 | pci_read_config_byte(pdev, PIIX_SCC, &tmp); | |
658 | if (tmp == PIIX_AHCI_DEVICE) { | |
659 | int rc = piix_disable_ahci(pdev); | |
660 | if (rc) | |
661 | return rc; | |
662 | } | |
1da177e4 LT |
663 | } |
664 | ||
665 | if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) { | |
666 | u8 tmp; | |
667 | pci_read_config_byte(pdev, ICH5_PMR, &tmp); | |
668 | ||
669 | if (tmp & PIIX_COMB) { | |
670 | combined = 1; | |
671 | if (tmp & PIIX_COMB_PATA_P0) | |
672 | sata_chan = 1; | |
673 | else | |
674 | pata_chan = 1; | |
675 | } | |
676 | } | |
677 | ||
678 | /* On ICH5, some BIOSen disable the interrupt using the | |
679 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. | |
680 | * On ICH6, this bit has the same effect, but only when | |
681 | * MSI is disabled (and it is disabled, as we don't use | |
682 | * message-signalled interrupts currently). | |
683 | */ | |
684 | if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR) | |
a04ce0ff | 685 | pci_intx(pdev, 1); |
1da177e4 LT |
686 | |
687 | if (combined) { | |
688 | port_info[sata_chan] = &piix_port_info[ent->driver_data]; | |
689 | port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS; | |
690 | port_info[pata_chan] = &piix_port_info[ich5_pata]; | |
1da177e4 | 691 | |
6248e647 JG |
692 | dev_printk(KERN_WARNING, &pdev->dev, |
693 | "combined mode detected (p=%u, s=%u)\n", | |
694 | pata_chan, sata_chan); | |
1da177e4 LT |
695 | } |
696 | ||
fbf30fba | 697 | return ata_pci_init_one(pdev, port_info, 2); |
1da177e4 LT |
698 | } |
699 | ||
1da177e4 LT |
700 | static int __init piix_init(void) |
701 | { | |
702 | int rc; | |
703 | ||
704 | DPRINTK("pci_module_init\n"); | |
705 | rc = pci_module_init(&piix_pci_driver); | |
706 | if (rc) | |
707 | return rc; | |
708 | ||
709 | in_module_init = 0; | |
710 | ||
711 | DPRINTK("done\n"); | |
712 | return 0; | |
713 | } | |
714 | ||
1da177e4 LT |
715 | static void __exit piix_exit(void) |
716 | { | |
717 | pci_unregister_driver(&piix_pci_driver); | |
718 | } | |
719 | ||
720 | module_init(piix_init); | |
721 | module_exit(piix_exit); | |
722 |