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[PATCH] ata_piix: add a couple of flags
[deliverable/linux.git] / drivers / scsi / ata_piix.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
94
95#define DRV_NAME "ata_piix"
7bdd7208 96#define DRV_VERSION "1.05"
1da177e4
LT		 97
98enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 102 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 103
d4358048
TH		 104 PIIX_FLAG_IGN_PRESENT = (1 << 25), /* ignore PCS present bits */
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108 PIIX_FLAG_COMBINED = (1 << 29), /* combined mode possible */
109 /* ICH6/7 use different scheme for map value */
110 PIIX_FLAG_COMBINED_ICH6 = PIIX_FLAG_COMBINED | (1 << 30),
1da177e4
LT		 111
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
115 PIIX_COMB_PATA_P0 = (1 << 1),
116 PIIX_COMB = (1 << 2), /* combined mode enabled? */
117
6a690df5
HR		 118 PIIX_PORT_ENABLED = (1 << 0),
119 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 120
121 PIIX_80C_PRI = (1 << 5) | (1 << 4),
122 PIIX_80C_SEC = (1 << 7) | (1 << 6),
123
1d076e5b
TH		 124 /* controller IDs */
125 piix4_pata = 0,
126 ich5_pata = 1,
127 ich5_sata = 2,
128 esb_sata = 3,
129 ich6_sata = 4,
130 ich6_sata_ahci = 5,
131 ich6m_sata_ahci = 6,
7b6dbd68
GF		 132
133 PIIX_AHCI_DEVICE = 6,
1da177e4
LT		 134};
135
136static int piix_init_one (struct pci_dev *pdev,
137 const struct pci_device_id *ent);
138
573db6b8 139static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes);
ccbe6d5e 140static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes);
1da177e4
LT		 141static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
142static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
143
144static unsigned int in_module_init = 1;
145
3b7d697d 146static const struct pci_device_id piix_pci_tbl[] = {
1da177e4
LT		 147#ifdef ATA_ENABLE_PATA
148 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
149 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
150 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
151#endif
152
153 /* NOTE: The following PCI ids must be kept in sync with the
154 * list in drivers/pci/quirks.c.
155 */
156
1d076e5b 157 /* 82801EB (ICH5) */
1da177e4 158 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 159 /* 82801EB (ICH5) */
1da177e4 160 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b
TH		 161 /* 6300ESB (ICH5 variant with broken PCS present bits) */
162 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
163 /* 6300ESB pretending RAID */
164 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
165 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 166 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 167 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 168 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 169 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
170 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
171 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 172 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 173 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
174 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
175 /* Enterprise Southbridge 2 (where's the datasheet?) */
1c24a412 176 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 177 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
012b265f 178 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 179 /* SATA Controller 2 IDE (ICH8, ditto) */
012b265f 180 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 181 /* Mobile SATA Controller IDE (ICH8M, ditto) */
182 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
1da177e4
LT		 183
184 { } /* terminate list */
185};
186
187static struct pci_driver piix_pci_driver = {
188 .name = DRV_NAME,
189 .id_table = piix_pci_tbl,
190 .probe = piix_init_one,
191 .remove = ata_pci_remove_one,
9b847548
JA		 192 .suspend = ata_pci_device_suspend,
193 .resume = ata_pci_device_resume,
1da177e4
LT		 194};
195
193515d5 196static struct scsi_host_template piix_sht = {
1da177e4
LT		 197 .module = THIS_MODULE,
198 .name = DRV_NAME,
199 .ioctl = ata_scsi_ioctl,
200 .queuecommand = ata_scsi_queuecmd,
35daeb8f 201 .eh_timed_out = ata_scsi_timed_out,
1da177e4
LT		 202 .eh_strategy_handler = ata_scsi_error,
203 .can_queue = ATA_DEF_QUEUE,
204 .this_id = ATA_SHT_THIS_ID,
205 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 206 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
207 .emulated = ATA_SHT_EMULATED,
208 .use_clustering = ATA_SHT_USE_CLUSTERING,
209 .proc_name = DRV_NAME,
210 .dma_boundary = ATA_DMA_BOUNDARY,
211 .slave_configure = ata_scsi_slave_config,
212 .bios_param = ata_std_bios_param,
9b847548
JA		 213 .resume = ata_scsi_device_resume,
214 .suspend = ata_scsi_device_suspend,
1da177e4
LT		 215};
216
057ace5e 217static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 218 .port_disable = ata_port_disable,
219 .set_piomode = piix_set_piomode,
220 .set_dmamode = piix_set_dmamode,
221
222 .tf_load = ata_tf_load,
223 .tf_read = ata_tf_read,
224 .check_status = ata_check_status,
225 .exec_command = ata_exec_command,
226 .dev_select = ata_std_dev_select,
227
573db6b8 228 .probe_reset = piix_pata_probe_reset,
1da177e4
LT		 229
230 .bmdma_setup = ata_bmdma_setup,
231 .bmdma_start = ata_bmdma_start,
232 .bmdma_stop = ata_bmdma_stop,
233 .bmdma_status = ata_bmdma_status,
234 .qc_prep = ata_qc_prep,
235 .qc_issue = ata_qc_issue_prot,
236
237 .eng_timeout = ata_eng_timeout,
238
239 .irq_handler = ata_interrupt,
240 .irq_clear = ata_bmdma_irq_clear,
241
242 .port_start = ata_port_start,
243 .port_stop = ata_port_stop,
aa8f0dc6 244 .host_stop = ata_host_stop,
1da177e4
LT		 245};
246
057ace5e 247static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 248 .port_disable = ata_port_disable,
249
250 .tf_load = ata_tf_load,
251 .tf_read = ata_tf_read,
252 .check_status = ata_check_status,
253 .exec_command = ata_exec_command,
254 .dev_select = ata_std_dev_select,
255
ccbe6d5e 256 .probe_reset = piix_sata_probe_reset,
1da177e4
LT		 257
258 .bmdma_setup = ata_bmdma_setup,
259 .bmdma_start = ata_bmdma_start,
260 .bmdma_stop = ata_bmdma_stop,
261 .bmdma_status = ata_bmdma_status,
262 .qc_prep = ata_qc_prep,
263 .qc_issue = ata_qc_issue_prot,
264
265 .eng_timeout = ata_eng_timeout,
266
267 .irq_handler = ata_interrupt,
268 .irq_clear = ata_bmdma_irq_clear,
269
270 .port_start = ata_port_start,
271 .port_stop = ata_port_stop,
aa8f0dc6 272 .host_stop = ata_host_stop,
1da177e4
LT		 273};
274
275static struct ata_port_info piix_port_info[] = {
1d076e5b
TH		 276 /* piix4_pata */
277 {
278 .sht = &piix_sht,
279 .host_flags = ATA_FLAG_SLAVE_POSS,
280 .pio_mask = 0x1f, /* pio0-4 */
281#if 0
282 .mwdma_mask = 0x06, /* mwdma1-2 */
283#else
284 .mwdma_mask = 0x00, /* mwdma broken */
285#endif
286 .udma_mask = ATA_UDMA_MASK_40C,
287 .port_ops = &piix_pata_ops,
288 },
289
1da177e4
LT		 290 /* ich5_pata */
291 {
292 .sht = &piix_sht,
573db6b8 293 .host_flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
1da177e4
LT		 294 .pio_mask = 0x1f, /* pio0-4 */
295#if 0
296 .mwdma_mask = 0x06, /* mwdma1-2 */
297#else
298 .mwdma_mask = 0x00, /* mwdma broken */
299#endif
300 .udma_mask = 0x3f, /* udma0-5 */
301 .port_ops = &piix_pata_ops,
302 },
303
304 /* ich5_sata */
305 {
306 .sht = &piix_sht,
ccbe6d5e
TH		 307 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
308 PIIX_FLAG_CHECKINTR,
1da177e4
LT		 309 .pio_mask = 0x1f, /* pio0-4 */
310 .mwdma_mask = 0x07, /* mwdma0-2 */
311 .udma_mask = 0x7f, /* udma0-6 */
312 .port_ops = &piix_sata_ops,
313 },
314
1d076e5b 315 /* i6300esb_sata */
1da177e4
LT		 316 {
317 .sht = &piix_sht,
1d076e5b 318 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
d4358048 319 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGN_PRESENT,
1da177e4 320 .pio_mask = 0x1f, /* pio0-4 */
1d076e5b
TH		 321 .mwdma_mask = 0x07, /* mwdma0-2 */
322 .udma_mask = 0x7f, /* udma0-6 */
323 .port_ops = &piix_sata_ops,
1da177e4
LT		 324 },
325
326 /* ich6_sata */
327 {
328 .sht = &piix_sht,
ccbe6d5e 329 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
d4358048
TH		 330 PIIX_FLAG_CHECKINTR | ATA_FLAG_SLAVE_POSS |
331 PIIX_FLAG_SCR,
1da177e4
LT		 332 .pio_mask = 0x1f, /* pio0-4 */
333 .mwdma_mask = 0x07, /* mwdma0-2 */
334 .udma_mask = 0x7f, /* udma0-6 */
335 .port_ops = &piix_sata_ops,
336 },
337
1c24a412 338 /* ich6_sata_ahci */
c368ca4e
JG		 339 {
340 .sht = &piix_sht,
ccbe6d5e 341 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
ff0fc146 342 PIIX_FLAG_CHECKINTR | ATA_FLAG_SLAVE_POSS |
d4358048 343 PIIX_FLAG_SCR | PIIX_FLAG_AHCI,
c368ca4e
JG		 344 .pio_mask = 0x1f, /* pio0-4 */
345 .mwdma_mask = 0x07, /* mwdma0-2 */
346 .udma_mask = 0x7f, /* udma0-6 */
347 .port_ops = &piix_sata_ops,
348 },
1d076e5b
TH		 349
350 /* ich6m_sata_ahci */
351 {
352 .sht = &piix_sht,
353 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
354 PIIX_FLAG_CHECKINTR | ATA_FLAG_SLAVE_POSS |
d4358048 355 PIIX_FLAG_SCR | PIIX_FLAG_AHCI,
1d076e5b
TH		 356 .pio_mask = 0x1f, /* pio0-4 */
357 .mwdma_mask = 0x07, /* mwdma0-2 */
358 .udma_mask = 0x7f, /* udma0-6 */
359 .port_ops = &piix_sata_ops,
360 },
1da177e4
LT		 361};
362
363static struct pci_bits piix_enable_bits[] = {
364 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
365 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
366};
367
368MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
369MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
370MODULE_LICENSE("GPL");
371MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
372MODULE_VERSION(DRV_VERSION);
373
374/**
375 * piix_pata_cbl_detect - Probe host controller cable detect info
376 * @ap: Port for which cable detect info is desired
377 *
378 * Read 80c cable indicator from ATA PCI device's PCI config
379 * register. This register is normally set by firmware (BIOS).
380 *
381 * LOCKING:
382 * None (inherited from caller).
383 */
384static void piix_pata_cbl_detect(struct ata_port *ap)
385{
386 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
387 u8 tmp, mask;
388
389 /* no 80c support in host controller? */
390 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
391 goto cbl40;
392
393 /* check BIOS cable detect results */
394 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
395 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
396 if ((tmp & mask) == 0)
397 goto cbl40;
398
399 ap->cbl = ATA_CBL_PATA80;
400 return;
401
402cbl40:
403 ap->cbl = ATA_CBL_PATA40;
404 ap->udma_mask &= ATA_UDMA_MASK_40C;
405}
406
407/**
573db6b8
TH		 408 * piix_pata_probeinit - probeinit for PATA host controller
409 * @ap: Target port
1da177e4 410 *
573db6b8 411 * Probeinit including cable detection.
1da177e4
LT		 412 *
413 * LOCKING:
414 * None (inherited from caller).
415 */
573db6b8
TH		 416static void piix_pata_probeinit(struct ata_port *ap)
417{
418 piix_pata_cbl_detect(ap);
419 ata_std_probeinit(ap);
420}
1da177e4 421
573db6b8
TH		 422/**
423 * piix_pata_probe_reset - Perform reset on PATA port and classify
424 * @ap: Port to reset
425 * @classes: Resulting classes of attached devices
426 *
427 * Reset PATA phy and classify attached devices.
428 *
429 * LOCKING:
430 * None (inherited from caller).
431 */
432static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes)
1da177e4
LT		 433{
434 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
435
436 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
1da177e4 437 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
573db6b8 438 return 0;
1da177e4
LT		 439 }
440
573db6b8
TH		 441 return ata_drive_probe_reset(ap, piix_pata_probeinit,
442 ata_std_softreset, NULL,
443 ata_std_postreset, classes);
1da177e4
LT		 444}
445
446/**
447 * piix_sata_probe - Probe PCI device for present SATA devices
448 * @ap: Port associated with the PCI device we wish to probe
449 *
450 * Reads SATA PCI device's PCI config register Port Configuration
451 * and Status (PCS) to determine port and device availability.
452 *
453 * LOCKING:
454 * None (inherited from caller).
455 *
456 * RETURNS:
6a690df5
HR		 457 * Non-zero if port is enabled, it may or may not have a device
458 * attached in that case (PRESENT bit would only be set if BIOS probe
459 * was done). Zero is returned if port is disabled.
1da177e4
LT		 460 */
461static int piix_sata_probe (struct ata_port *ap)
462{
463 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
464 int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
465 int orig_mask, mask, i;
466 u8 pcs;
467
1da177e4
LT		 468 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
469 orig_mask = (int) pcs & 0xff;
470
471 /* TODO: this is vaguely wrong for ICH6 combined mode,
472 * where only two of the four SATA ports are mapped
473 * onto a single ATA channel. It is also vaguely inaccurate
474 * for ICH5, which has only two ports. However, this is ok,
475 * as further device presence detection code will handle
476 * any false positives produced here.
477 */
478
479 for (i = 0; i < 4; i++) {
6a690df5 480 mask = (PIIX_PORT_ENABLED << i);
1da177e4
LT		 481
482 if ((orig_mask & mask) == mask)
483 if (combined || (i == ap->hard_port_no))
484 return 1;
485 }
486
487 return 0;
488}
489
490/**
ccbe6d5e
TH		 491 * piix_sata_probe_reset - Perform reset on SATA port and classify
492 * @ap: Port to reset
493 * @classes: Resulting classes of attached devices
1da177e4 494 *
ccbe6d5e 495 * Reset SATA phy and classify attached devices.
1da177e4
LT		 496 *
497 * LOCKING:
498 * None (inherited from caller).
499 */
ccbe6d5e 500static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes)
1da177e4
LT		 501{
502 if (!piix_sata_probe(ap)) {
1da177e4 503 printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
ccbe6d5e 504 return 0;
1da177e4
LT		 505 }
506
ccbe6d5e
TH		 507 return ata_drive_probe_reset(ap, ata_std_probeinit,
508 ata_std_softreset, NULL,
509 ata_std_postreset, classes);
1da177e4
LT		 510}
511
512/**
513 * piix_set_piomode - Initialize host controller PATA PIO timings
514 * @ap: Port whose timings we are configuring
515 * @adev: um
1da177e4
LT		 516 *
517 * Set PIO mode for device, in host controller PCI config space.
518 *
519 * LOCKING:
520 * None (inherited from caller).
521 */
522
523static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
524{
525 unsigned int pio = adev->pio_mode - XFER_PIO_0;
526 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
527 unsigned int is_slave = (adev->devno != 0);
528 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
529 unsigned int slave_port = 0x44;
530 u16 master_data;
531 u8 slave_data;
532
533 static const /* ISP RTC */
534 u8 timings[][2] = { { 0, 0 },
535 { 0, 0 },
536 { 1, 0 },
537 { 2, 1 },
538 { 2, 3 }, };
539
540 pci_read_config_word(dev, master_port, &master_data);
541 if (is_slave) {
542 master_data |= 0x4000;
543 /* enable PPE, IE and TIME */
544 master_data |= 0x0070;
545 pci_read_config_byte(dev, slave_port, &slave_data);
546 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
547 slave_data |=
548 (timings[pio][0] << 2) |
549 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
550 } else {
551 master_data &= 0xccf8;
552 /* enable PPE, IE and TIME */
553 master_data |= 0x0007;
554 master_data |=
555 (timings[pio][0] << 12) |
556 (timings[pio][1] << 8);
557 }
558 pci_write_config_word(dev, master_port, master_data);
559 if (is_slave)
560 pci_write_config_byte(dev, slave_port, slave_data);
561}
562
563/**
564 * piix_set_dmamode - Initialize host controller PATA PIO timings
565 * @ap: Port whose timings we are configuring
566 * @adev: um
567 * @udma: udma mode, 0 - 6
568 *
569 * Set UDMA mode for device, in host controller PCI config space.
570 *
571 * LOCKING:
572 * None (inherited from caller).
573 */
574
575static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
576{
577 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
578 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
579 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
580 u8 speed = udma;
581 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
582 int a_speed = 3 << (drive_dn * 4);
583 int u_flag = 1 << drive_dn;
584 int v_flag = 0x01 << drive_dn;
585 int w_flag = 0x10 << drive_dn;
586 int u_speed = 0;
587 int sitre;
588 u16 reg4042, reg4a;
589 u8 reg48, reg54, reg55;
590
591 pci_read_config_word(dev, maslave, &reg4042);
592 DPRINTK("reg4042 = 0x%04x\n", reg4042);
593 sitre = (reg4042 & 0x4000) ? 1 : 0;
594 pci_read_config_byte(dev, 0x48, &reg48);
595 pci_read_config_word(dev, 0x4a, &reg4a);
596 pci_read_config_byte(dev, 0x54, &reg54);
597 pci_read_config_byte(dev, 0x55, &reg55);
598
599 switch(speed) {
600 case XFER_UDMA_4:
601 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
602 case XFER_UDMA_6:
603 case XFER_UDMA_5:
604 case XFER_UDMA_3:
605 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
606 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
607 case XFER_MW_DMA_2:
608 case XFER_MW_DMA_1: break;
609 default:
610 BUG();
611 return;
612 }
613
614 if (speed >= XFER_UDMA_0) {
615 if (!(reg48 & u_flag))
616 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
617 if (speed == XFER_UDMA_5) {
618 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
619 } else {
620 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
621 }
622 if ((reg4a & a_speed) != u_speed)
623 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
624 if (speed > XFER_UDMA_2) {
625 if (!(reg54 & v_flag))
626 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
627 } else
628 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
629 } else {
630 if (reg48 & u_flag)
631 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
632 if (reg4a & a_speed)
633 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
634 if (reg54 & v_flag)
635 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
636 if (reg55 & w_flag)
637 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
638 }
639}
640
1da177e4
LT		 641#define AHCI_PCI_BAR 5
642#define AHCI_GLOBAL_CTL 0x04
643#define AHCI_ENABLE (1 << 31)
644static int piix_disable_ahci(struct pci_dev *pdev)
645{
ea6ba10b 646 void __iomem *mmio;
1da177e4
LT		 647 u32 tmp;
648 int rc = 0;
649
650 /* BUG: pci_enable_device has not yet been called. This
651 * works because this device is usually set up by BIOS.
652 */
653
374b1873
JG		 654 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
655 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 656 return 0;
7b6dbd68 657
374b1873 658 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 659 if (!mmio)
660 return -ENOMEM;
7b6dbd68 661
1da177e4
LT		 662 tmp = readl(mmio + AHCI_GLOBAL_CTL);
663 if (tmp & AHCI_ENABLE) {
664 tmp &= ~AHCI_ENABLE;
665 writel(tmp, mmio + AHCI_GLOBAL_CTL);
666
667 tmp = readl(mmio + AHCI_GLOBAL_CTL);
668 if (tmp & AHCI_ENABLE)
669 rc = -EIO;
670 }
7b6dbd68 671
374b1873 672 pci_iounmap(pdev, mmio);
1da177e4
LT		 673 return rc;
674}
675
c621b140
AC		 676/**
677 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 678 * @ata_dev: the PCI device to check
c621b140
AC		 679 *
680 * Check for the present of 450NX errata #19 and errata #25. If
681 * they are found return an error code so we can turn off DMA
682 */
683
684static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
685{
686 struct pci_dev *pdev = NULL;
687 u16 cfg;
688 u8 rev;
689 int no_piix_dma = 0;
690
691 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
692 {
693 /* Look for 450NX PXB. Check for problem configurations
694 A PCI quirk checks bit 6 already */
695 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
696 pci_read_config_word(pdev, 0x41, &cfg);
697 /* Only on the original revision: IDE DMA can hang */
698 if(rev == 0x00)
699 no_piix_dma = 1;
700 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
701 else if(cfg & (1<<14) && rev < 5)
702 no_piix_dma = 2;
703 }
704 if(no_piix_dma)
705 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
706 if(no_piix_dma == 2)
707 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
708 return no_piix_dma;
709}
710
1da177e4
LT		 711/**
712 * piix_init_one - Register PIIX ATA PCI device with kernel services
713 * @pdev: PCI device to register
714 * @ent: Entry in piix_pci_tbl matching with @pdev
715 *
716 * Called from kernel PCI layer. We probe for combined mode (sigh),
717 * and then hand over control to libata, for it to do the rest.
718 *
719 * LOCKING:
720 * Inherited from PCI layer (may sleep).
721 *
722 * RETURNS:
723 * Zero on success, or -ERRNO value.
724 */
725
726static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
727{
728 static int printed_version;
729 struct ata_port_info *port_info[2];
fbf30fba 730 unsigned int combined = 0;
1da177e4 731 unsigned int pata_chan = 0, sata_chan = 0;
ff0fc146 732 unsigned long host_flags;
1da177e4
LT		 733
734 if (!printed_version++)
6248e647
JG		 735 dev_printk(KERN_DEBUG, &pdev->dev,
736 "version " DRV_VERSION "\n");
1da177e4
LT		 737
738 /* no hotplugging support (FIXME) */
739 if (!in_module_init)
740 return -ENODEV;
741
742 port_info[0] = &piix_port_info[ent->driver_data];
fbf30fba 743 port_info[1] = &piix_port_info[ent->driver_data];
1da177e4 744
ff0fc146
TH		 745 host_flags = port_info[0]->host_flags;
746
747 if (host_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 748 u8 tmp;
749 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
750 if (tmp == PIIX_AHCI_DEVICE) {
751 int rc = piix_disable_ahci(pdev);
752 if (rc)
753 return rc;
754 }
1da177e4
LT		 755 }
756
ff0fc146 757 if (host_flags & PIIX_FLAG_COMBINED) {
1da177e4
LT		 758 u8 tmp;
759 pci_read_config_byte(pdev, ICH5_PMR, &tmp);
760
ff0fc146 761 if (host_flags & PIIX_FLAG_COMBINED_ICH6) {
b376bc1f 762 switch (tmp & 0x3) {
ff0fc146
TH		 763 case 0:
764 break;
765 case 1:
766 combined = 1;
1da177e4 767 sata_chan = 1;
ff0fc146
TH		 768 break;
769 case 2:
770 combined = 1;
1da177e4 771 pata_chan = 1;
ff0fc146
TH		 772 break;
773 case 3:
774 dev_printk(KERN_WARNING, &pdev->dev,
775 "invalid MAP value %u\n", tmp);
776 break;
777 }
778 } else {
779 if (tmp & PIIX_COMB) {
780 combined = 1;
781 if (tmp & PIIX_COMB_PATA_P0)
782 sata_chan = 1;
783 else
784 pata_chan = 1;
785 }
1da177e4
LT		 786 }
787 }
788
789 /* On ICH5, some BIOSen disable the interrupt using the
790 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
791 * On ICH6, this bit has the same effect, but only when
792 * MSI is disabled (and it is disabled, as we don't use
793 * message-signalled interrupts currently).
794 */
ff0fc146 795 if (host_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 796 pci_intx(pdev, 1);
1da177e4
LT		 797
798 if (combined) {
799 port_info[sata_chan] = &piix_port_info[ent->driver_data];
800 port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS;
801 port_info[pata_chan] = &piix_port_info[ich5_pata];
1da177e4 802
6248e647
JG		 803 dev_printk(KERN_WARNING, &pdev->dev,
804 "combined mode detected (p=%u, s=%u)\n",
805 pata_chan, sata_chan);
1da177e4 806 }
c621b140
AC		 807 if (piix_check_450nx_errata(pdev)) {
808 /* This writes into the master table but it does not
809 really matter for this errata as we will apply it to
810 all the PIIX devices on the board */
811 port_info[0]->mwdma_mask = 0;
812 port_info[0]->udma_mask = 0;
813 port_info[1]->mwdma_mask = 0;
814 port_info[1]->udma_mask = 0;
815 }
fbf30fba 816 return ata_pci_init_one(pdev, port_info, 2);
1da177e4
LT		 817}
818
1da177e4
LT		 819static int __init piix_init(void)
820{
821 int rc;
822
823 DPRINTK("pci_module_init\n");
824 rc = pci_module_init(&piix_pci_driver);
825 if (rc)
826 return rc;
827
828 in_module_init = 0;
829
830 DPRINTK("done\n");
831 return 0;
832}
833
1da177e4
LT		 834static void __exit piix_exit(void)
835{
836 pci_unregister_driver(&piix_pci_driver);
837}
838
839module_init(piix_init);
840module_exit(piix_exit);
841
Linux kernel - Deliverables
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