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[PATCH] ata_piix: add host_set private structure
[deliverable/linux.git] / drivers / scsi / ata_piix.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
94
95#define DRV_NAME "ata_piix"
8676ce07 96#define DRV_VERSION "2.00"
1da177e4
LT		 97
98enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 102 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 103
219e6214 104 PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */
d4358048 105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108 PIIX_FLAG_COMBINED = (1 << 29), /* combined mode possible */
109 /* ICH6/7 use different scheme for map value */
110 PIIX_FLAG_COMBINED_ICH6 = PIIX_FLAG_COMBINED | (1 << 30),
1da177e4
LT		 111
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
6a690df5
HR		 115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
1d076e5b
TH		 121 /* controller IDs */
122 piix4_pata = 0,
123 ich5_pata = 1,
124 ich5_sata = 2,
125 esb_sata = 3,
126 ich6_sata = 4,
127 ich6_sata_ahci = 5,
128 ich6m_sata_ahci = 6,
7b6dbd68 129
d33f58b8
TH		 130 /* constants for mapping table */
131 P0 = 0, /* port 0 */
132 P1 = 1, /* port 1 */
133 P2 = 2, /* port 2 */
134 P3 = 3, /* port 3 */
135 IDE = -1, /* IDE */
136 NA = -2, /* not avaliable */
137 RV = -3, /* reserved */
138
7b6dbd68 139 PIIX_AHCI_DEVICE = 6,
1da177e4
LT		 140};
141
d33f58b8
TH		 142struct piix_map_db {
143 const u32 mask;
144 const int map[][4];
145};
146
d96715c1
TH		 147struct piix_host_priv {
148 const int *map;
149};
150
1da177e4
LT		 151static int piix_init_one (struct pci_dev *pdev,
152 const struct pci_device_id *ent);
d96715c1 153static void piix_host_stop(struct ata_host_set *host_set);
1da177e4
LT		 154static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
155static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
ccc4672a
TH		 156static void piix_pata_error_handler(struct ata_port *ap);
157static void piix_sata_error_handler(struct ata_port *ap);
1da177e4
LT		 158
159static unsigned int in_module_init = 1;
160
3b7d697d 161static const struct pci_device_id piix_pci_tbl[] = {
1da177e4
LT		 162#ifdef ATA_ENABLE_PATA
163 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
164 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
165 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
b74ba22f 166 { 0x8086, 0x27df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
1da177e4
LT		 167#endif
168
169 /* NOTE: The following PCI ids must be kept in sync with the
170 * list in drivers/pci/quirks.c.
171 */
172
1d076e5b 173 /* 82801EB (ICH5) */
1da177e4 174 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 175 /* 82801EB (ICH5) */
1da177e4 176 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b
TH		 177 /* 6300ESB (ICH5 variant with broken PCS present bits) */
178 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
179 /* 6300ESB pretending RAID */
180 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
181 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 182 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 183 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 184 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 185 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
186 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
187 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 188 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 189 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
190 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
191 /* Enterprise Southbridge 2 (where's the datasheet?) */
1c24a412 192 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 193 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
012b265f 194 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 195 /* SATA Controller 2 IDE (ICH8, ditto) */
012b265f 196 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 197 /* Mobile SATA Controller IDE (ICH8M, ditto) */
198 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
1da177e4
LT		 199
200 { } /* terminate list */
201};
202
203static struct pci_driver piix_pci_driver = {
204 .name = DRV_NAME,
205 .id_table = piix_pci_tbl,
206 .probe = piix_init_one,
207 .remove = ata_pci_remove_one,
9b847548
JA		 208 .suspend = ata_pci_device_suspend,
209 .resume = ata_pci_device_resume,
1da177e4
LT		 210};
211
193515d5 212static struct scsi_host_template piix_sht = {
1da177e4
LT		 213 .module = THIS_MODULE,
214 .name = DRV_NAME,
215 .ioctl = ata_scsi_ioctl,
216 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 217 .can_queue = ATA_DEF_QUEUE,
218 .this_id = ATA_SHT_THIS_ID,
219 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 220 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
221 .emulated = ATA_SHT_EMULATED,
222 .use_clustering = ATA_SHT_USE_CLUSTERING,
223 .proc_name = DRV_NAME,
224 .dma_boundary = ATA_DMA_BOUNDARY,
225 .slave_configure = ata_scsi_slave_config,
ccf68c34 226 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 227 .bios_param = ata_std_bios_param,
9b847548
JA		 228 .resume = ata_scsi_device_resume,
229 .suspend = ata_scsi_device_suspend,
1da177e4
LT		 230};
231
057ace5e 232static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 233 .port_disable = ata_port_disable,
234 .set_piomode = piix_set_piomode,
235 .set_dmamode = piix_set_dmamode,
89bad589 236 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 237
238 .tf_load = ata_tf_load,
239 .tf_read = ata_tf_read,
240 .check_status = ata_check_status,
241 .exec_command = ata_exec_command,
242 .dev_select = ata_std_dev_select,
243
1da177e4
LT		 244 .bmdma_setup = ata_bmdma_setup,
245 .bmdma_start = ata_bmdma_start,
246 .bmdma_stop = ata_bmdma_stop,
247 .bmdma_status = ata_bmdma_status,
248 .qc_prep = ata_qc_prep,
249 .qc_issue = ata_qc_issue_prot,
89bad589 250 .data_xfer = ata_pio_data_xfer,
1da177e4 251
3f037db0
TH		 252 .freeze = ata_bmdma_freeze,
253 .thaw = ata_bmdma_thaw,
ccc4672a 254 .error_handler = piix_pata_error_handler,
3f037db0 255 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 256
257 .irq_handler = ata_interrupt,
258 .irq_clear = ata_bmdma_irq_clear,
259
260 .port_start = ata_port_start,
261 .port_stop = ata_port_stop,
d96715c1 262 .host_stop = piix_host_stop,
1da177e4
LT		 263};
264
057ace5e 265static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 266 .port_disable = ata_port_disable,
267
268 .tf_load = ata_tf_load,
269 .tf_read = ata_tf_read,
270 .check_status = ata_check_status,
271 .exec_command = ata_exec_command,
272 .dev_select = ata_std_dev_select,
273
1da177e4
LT		 274 .bmdma_setup = ata_bmdma_setup,
275 .bmdma_start = ata_bmdma_start,
276 .bmdma_stop = ata_bmdma_stop,
277 .bmdma_status = ata_bmdma_status,
278 .qc_prep = ata_qc_prep,
279 .qc_issue = ata_qc_issue_prot,
89bad589 280 .data_xfer = ata_pio_data_xfer,
1da177e4 281
3f037db0
TH		 282 .freeze = ata_bmdma_freeze,
283 .thaw = ata_bmdma_thaw,
ccc4672a 284 .error_handler = piix_sata_error_handler,
3f037db0 285 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 286
287 .irq_handler = ata_interrupt,
288 .irq_clear = ata_bmdma_irq_clear,
289
290 .port_start = ata_port_start,
291 .port_stop = ata_port_stop,
d96715c1 292 .host_stop = piix_host_stop,
1da177e4
LT		 293};
294
d96715c1 295static const struct piix_map_db ich5_map_db = {
d33f58b8
TH		 296 .mask = 0x7,
297 .map = {
298 /* PM PS SM SS MAP */
299 { P0, NA, P1, NA }, /* 000b */
300 { P1, NA, P0, NA }, /* 001b */
301 { RV, RV, RV, RV },
302 { RV, RV, RV, RV },
303 { P0, P1, IDE, IDE }, /* 100b */
304 { P1, P0, IDE, IDE }, /* 101b */
305 { IDE, IDE, P0, P1 }, /* 110b */
306 { IDE, IDE, P1, P0 }, /* 111b */
307 },
308};
309
d96715c1 310static const struct piix_map_db ich6_map_db = {
d33f58b8
TH		 311 .mask = 0x3,
312 .map = {
313 /* PM PS SM SS MAP */
79ea24e7 314 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 315 { IDE, IDE, P1, P3 }, /* 01b */
316 { P0, P2, IDE, IDE }, /* 10b */
317 { RV, RV, RV, RV },
318 },
319};
320
d96715c1 321static const struct piix_map_db ich6m_map_db = {
d33f58b8
TH		 322 .mask = 0x3,
323 .map = {
324 /* PM PS SM SS MAP */
79ea24e7 325 { P0, P2, RV, RV }, /* 00b */
d33f58b8
TH		 326 { RV, RV, RV, RV },
327 { P0, P2, IDE, IDE }, /* 10b */
328 { RV, RV, RV, RV },
329 },
330};
331
d96715c1
TH		 332static const struct piix_map_db *piix_map_db_table[] = {
333 [ich5_sata] = &ich5_map_db,
334 [esb_sata] = &ich5_map_db,
335 [ich6_sata] = &ich6_map_db,
336 [ich6_sata_ahci] = &ich6_map_db,
337 [ich6m_sata_ahci] = &ich6m_map_db,
338};
339
1da177e4 340static struct ata_port_info piix_port_info[] = {
1d076e5b
TH		 341 /* piix4_pata */
342 {
343 .sht = &piix_sht,
344 .host_flags = ATA_FLAG_SLAVE_POSS,
345 .pio_mask = 0x1f, /* pio0-4 */
346#if 0
347 .mwdma_mask = 0x06, /* mwdma1-2 */
348#else
349 .mwdma_mask = 0x00, /* mwdma broken */
350#endif
351 .udma_mask = ATA_UDMA_MASK_40C,
352 .port_ops = &piix_pata_ops,
353 },
354
1da177e4
LT		 355 /* ich5_pata */
356 {
357 .sht = &piix_sht,
573db6b8 358 .host_flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
1da177e4
LT		 359 .pio_mask = 0x1f, /* pio0-4 */
360#if 0
361 .mwdma_mask = 0x06, /* mwdma1-2 */
362#else
363 .mwdma_mask = 0x00, /* mwdma broken */
364#endif
365 .udma_mask = 0x3f, /* udma0-5 */
366 .port_ops = &piix_pata_ops,
367 },
368
369 /* ich5_sata */
370 {
371 .sht = &piix_sht,
ccbe6d5e
TH		 372 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
373 PIIX_FLAG_CHECKINTR,
1da177e4
LT		 374 .pio_mask = 0x1f, /* pio0-4 */
375 .mwdma_mask = 0x07, /* mwdma0-2 */
376 .udma_mask = 0x7f, /* udma0-6 */
377 .port_ops = &piix_sata_ops,
378 },
379
1d076e5b 380 /* i6300esb_sata */
1da177e4
LT		 381 {
382 .sht = &piix_sht,
1d076e5b 383 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
219e6214 384 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS,
1da177e4 385 .pio_mask = 0x1f, /* pio0-4 */
1d076e5b
TH		 386 .mwdma_mask = 0x07, /* mwdma0-2 */
387 .udma_mask = 0x7f, /* udma0-6 */
388 .port_ops = &piix_sata_ops,
1da177e4
LT		 389 },
390
391 /* ich6_sata */
392 {
393 .sht = &piix_sht,
ccbe6d5e 394 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
d33f58b8 395 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR,
1da177e4
LT		 396 .pio_mask = 0x1f, /* pio0-4 */
397 .mwdma_mask = 0x07, /* mwdma0-2 */
398 .udma_mask = 0x7f, /* udma0-6 */
399 .port_ops = &piix_sata_ops,
400 },
401
1c24a412 402 /* ich6_sata_ahci */
c368ca4e
JG		 403 {
404 .sht = &piix_sht,
ccbe6d5e 405 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
d33f58b8
TH		 406 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
407 PIIX_FLAG_AHCI,
c368ca4e
JG		 408 .pio_mask = 0x1f, /* pio0-4 */
409 .mwdma_mask = 0x07, /* mwdma0-2 */
410 .udma_mask = 0x7f, /* udma0-6 */
411 .port_ops = &piix_sata_ops,
412 },
1d076e5b
TH		 413
414 /* ich6m_sata_ahci */
415 {
416 .sht = &piix_sht,
417 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
d33f58b8
TH		 418 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
419 PIIX_FLAG_AHCI,
1d076e5b
TH		 420 .pio_mask = 0x1f, /* pio0-4 */
421 .mwdma_mask = 0x07, /* mwdma0-2 */
422 .udma_mask = 0x7f, /* udma0-6 */
423 .port_ops = &piix_sata_ops,
424 },
1da177e4
LT		 425};
426
427static struct pci_bits piix_enable_bits[] = {
428 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
429 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
430};
431
432MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
433MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
434MODULE_LICENSE("GPL");
435MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
436MODULE_VERSION(DRV_VERSION);
437
438/**
439 * piix_pata_cbl_detect - Probe host controller cable detect info
440 * @ap: Port for which cable detect info is desired
441 *
442 * Read 80c cable indicator from ATA PCI device's PCI config
443 * register. This register is normally set by firmware (BIOS).
444 *
445 * LOCKING:
446 * None (inherited from caller).
447 */
448static void piix_pata_cbl_detect(struct ata_port *ap)
449{
450 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
451 u8 tmp, mask;
452
453 /* no 80c support in host controller? */
454 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
455 goto cbl40;
456
457 /* check BIOS cable detect results */
458 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
459 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
460 if ((tmp & mask) == 0)
461 goto cbl40;
462
463 ap->cbl = ATA_CBL_PATA80;
464 return;
465
466cbl40:
467 ap->cbl = ATA_CBL_PATA40;
468 ap->udma_mask &= ATA_UDMA_MASK_40C;
469}
470
471/**
ccc4672a 472 * piix_pata_prereset - prereset for PATA host controller
573db6b8 473 * @ap: Target port
1da177e4 474 *
ccc4672a 475 * Prereset including cable detection.
573db6b8
TH		 476 *
477 * LOCKING:
478 * None (inherited from caller).
479 */
ccc4672a 480static int piix_pata_prereset(struct ata_port *ap)
1da177e4
LT		 481{
482 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
483
484 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
f15a1daf 485 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
ccc4672a 486 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
573db6b8 487 return 0;
1da177e4
LT		 488 }
489
ccc4672a
TH		 490 piix_pata_cbl_detect(ap);
491
492 return ata_std_prereset(ap);
493}
494
495static void piix_pata_error_handler(struct ata_port *ap)
496{
497 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
498 ata_std_postreset);
1da177e4
LT		 499}
500
501/**
ccc4672a
TH		 502 * piix_sata_prereset - prereset for SATA host controller
503 * @ap: Target port
1da177e4 504 *
d133ecab
TH		 505 * Reads and configures SATA PCI device's PCI config register
506 * Port Configuration and Status (PCS) to determine port and
ccc4672a
TH		 507 * device availability. Return -ENODEV to skip reset if no
508 * device is present.
1da177e4
LT		 509 *
510 * LOCKING:
511 * None (inherited from caller).
512 *
513 * RETURNS:
ccc4672a 514 * 0 if device is present, -ENODEV otherwise.
1da177e4 515 */
ccc4672a 516static int piix_sata_prereset(struct ata_port *ap)
1da177e4
LT		 517{
518 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
d96715c1
TH		 519 struct piix_host_priv *hpriv = ap->host_set->private_data;
520 const unsigned int *map = hpriv->map;
d133ecab
TH		 521 int base = 2 * ap->hard_port_no;
522 unsigned int present_mask = 0;
523 int port, i;
1da177e4
LT		 524 u8 pcs;
525
1da177e4 526 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
d133ecab
TH		 527 DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base);
528
529 /* enable all ports on this ap and wait for them to settle */
530 for (i = 0; i < 2; i++) {
531 port = map[base + i];
532 if (port >= 0)
533 pcs |= 1 << port;
534 }
1da177e4 535
d133ecab
TH		 536 pci_write_config_byte(pdev, ICH5_PCS, pcs);
537 msleep(100);
1da177e4 538
d133ecab
TH		 539 /* let's see which devices are present */
540 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
541
542 for (i = 0; i < 2; i++) {
543 port = map[base + i];
544 if (port < 0)
545 continue;
219e6214 546 if (ap->flags & PIIX_FLAG_IGNORE_PCS || pcs & 1 << (4 + port))
d133ecab
TH		 547 present_mask |= 1 << i;
548 else
549 pcs &= ~(1 << port);
1da177e4
LT		 550 }
551
d133ecab
TH		 552 /* disable offline ports on non-AHCI controllers */
553 if (!(ap->flags & PIIX_FLAG_AHCI))
554 pci_write_config_byte(pdev, ICH5_PCS, pcs);
555
556 DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n",
557 ap->id, pcs, present_mask);
558
ccc4672a 559 if (!present_mask) {
f15a1daf 560 ata_port_printk(ap, KERN_INFO, "SATA port has no device.\n");
ccc4672a 561 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
ccbe6d5e 562 return 0;
1da177e4
LT		 563 }
564
ccc4672a
TH		 565 return ata_std_prereset(ap);
566}
567
568static void piix_sata_error_handler(struct ata_port *ap)
569{
570 ata_bmdma_drive_eh(ap, piix_sata_prereset, ata_std_softreset, NULL,
571 ata_std_postreset);
1da177e4
LT		 572}
573
574/**
575 * piix_set_piomode - Initialize host controller PATA PIO timings
576 * @ap: Port whose timings we are configuring
577 * @adev: um
1da177e4
LT		 578 *
579 * Set PIO mode for device, in host controller PCI config space.
580 *
581 * LOCKING:
582 * None (inherited from caller).
583 */
584
585static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
586{
587 unsigned int pio = adev->pio_mode - XFER_PIO_0;
588 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
589 unsigned int is_slave = (adev->devno != 0);
590 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
591 unsigned int slave_port = 0x44;
592 u16 master_data;
593 u8 slave_data;
594
595 static const /* ISP RTC */
596 u8 timings[][2] = { { 0, 0 },
597 { 0, 0 },
598 { 1, 0 },
599 { 2, 1 },
600 { 2, 3 }, };
601
602 pci_read_config_word(dev, master_port, &master_data);
603 if (is_slave) {
604 master_data |= 0x4000;
605 /* enable PPE, IE and TIME */
606 master_data |= 0x0070;
607 pci_read_config_byte(dev, slave_port, &slave_data);
608 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
609 slave_data |=
610 (timings[pio][0] << 2) |
611 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
612 } else {
613 master_data &= 0xccf8;
614 /* enable PPE, IE and TIME */
615 master_data |= 0x0007;
616 master_data |=
617 (timings[pio][0] << 12) |
618 (timings[pio][1] << 8);
619 }
620 pci_write_config_word(dev, master_port, master_data);
621 if (is_slave)
622 pci_write_config_byte(dev, slave_port, slave_data);
623}
624
625/**
626 * piix_set_dmamode - Initialize host controller PATA PIO timings
627 * @ap: Port whose timings we are configuring
628 * @adev: um
629 * @udma: udma mode, 0 - 6
630 *
631 * Set UDMA mode for device, in host controller PCI config space.
632 *
633 * LOCKING:
634 * None (inherited from caller).
635 */
636
637static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
638{
639 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
640 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
641 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
642 u8 speed = udma;
643 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
644 int a_speed = 3 << (drive_dn * 4);
645 int u_flag = 1 << drive_dn;
646 int v_flag = 0x01 << drive_dn;
647 int w_flag = 0x10 << drive_dn;
648 int u_speed = 0;
649 int sitre;
650 u16 reg4042, reg4a;
651 u8 reg48, reg54, reg55;
652
653 pci_read_config_word(dev, maslave, &reg4042);
654 DPRINTK("reg4042 = 0x%04x\n", reg4042);
655 sitre = (reg4042 & 0x4000) ? 1 : 0;
656 pci_read_config_byte(dev, 0x48, &reg48);
657 pci_read_config_word(dev, 0x4a, &reg4a);
658 pci_read_config_byte(dev, 0x54, &reg54);
659 pci_read_config_byte(dev, 0x55, &reg55);
660
661 switch(speed) {
662 case XFER_UDMA_4:
663 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
664 case XFER_UDMA_6:
665 case XFER_UDMA_5:
666 case XFER_UDMA_3:
667 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
668 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
669 case XFER_MW_DMA_2:
670 case XFER_MW_DMA_1: break;
671 default:
672 BUG();
673 return;
674 }
675
676 if (speed >= XFER_UDMA_0) {
677 if (!(reg48 & u_flag))
678 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
679 if (speed == XFER_UDMA_5) {
680 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
681 } else {
682 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
683 }
684 if ((reg4a & a_speed) != u_speed)
685 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
686 if (speed > XFER_UDMA_2) {
687 if (!(reg54 & v_flag))
688 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
689 } else
690 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
691 } else {
692 if (reg48 & u_flag)
693 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
694 if (reg4a & a_speed)
695 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
696 if (reg54 & v_flag)
697 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
698 if (reg55 & w_flag)
699 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
700 }
701}
702
1da177e4
LT		 703#define AHCI_PCI_BAR 5
704#define AHCI_GLOBAL_CTL 0x04
705#define AHCI_ENABLE (1 << 31)
706static int piix_disable_ahci(struct pci_dev *pdev)
707{
ea6ba10b 708 void __iomem *mmio;
1da177e4
LT		 709 u32 tmp;
710 int rc = 0;
711
712 /* BUG: pci_enable_device has not yet been called. This
713 * works because this device is usually set up by BIOS.
714 */
715
374b1873
JG		 716 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
717 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 718 return 0;
7b6dbd68 719
374b1873 720 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 721 if (!mmio)
722 return -ENOMEM;
7b6dbd68 723
1da177e4
LT		 724 tmp = readl(mmio + AHCI_GLOBAL_CTL);
725 if (tmp & AHCI_ENABLE) {
726 tmp &= ~AHCI_ENABLE;
727 writel(tmp, mmio + AHCI_GLOBAL_CTL);
728
729 tmp = readl(mmio + AHCI_GLOBAL_CTL);
730 if (tmp & AHCI_ENABLE)
731 rc = -EIO;
732 }
7b6dbd68 733
374b1873 734 pci_iounmap(pdev, mmio);
1da177e4
LT		 735 return rc;
736}
737
c621b140
AC		 738/**
739 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 740 * @ata_dev: the PCI device to check
2e9edbf8 741 *
c621b140
AC		 742 * Check for the present of 450NX errata #19 and errata #25. If
743 * they are found return an error code so we can turn off DMA
744 */
745
746static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
747{
748 struct pci_dev *pdev = NULL;
749 u16 cfg;
750 u8 rev;
751 int no_piix_dma = 0;
2e9edbf8 752
c621b140
AC		 753 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
754 {
755 /* Look for 450NX PXB. Check for problem configurations
756 A PCI quirk checks bit 6 already */
757 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
758 pci_read_config_word(pdev, 0x41, &cfg);
759 /* Only on the original revision: IDE DMA can hang */
31a34fe7 760 if (rev == 0x00)
c621b140
AC		 761 no_piix_dma = 1;
762 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
31a34fe7 763 else if (cfg & (1<<14) && rev < 5)
c621b140
AC		 764 no_piix_dma = 2;
765 }
31a34fe7 766 if (no_piix_dma)
c621b140 767 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
31a34fe7 768 if (no_piix_dma == 2)
c621b140
AC		 769 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
770 return no_piix_dma;
2e9edbf8 771}
c621b140 772
d33f58b8 773static void __devinit piix_init_sata_map(struct pci_dev *pdev,
d96715c1
TH		 774 struct ata_port_info *pinfo,
775 const struct piix_map_db *map_db)
d33f58b8 776{
d96715c1 777 struct piix_host_priv *hpriv = pinfo[0].private_data;
d33f58b8
TH		 778 const unsigned int *map;
779 int i, invalid_map = 0;
780 u8 map_value;
781
782 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
783
784 map = map_db->map[map_value & map_db->mask];
785
786 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
787 for (i = 0; i < 4; i++) {
788 switch (map[i]) {
789 case RV:
790 invalid_map = 1;
791 printk(" XX");
792 break;
793
794 case NA:
795 printk(" --");
796 break;
797
798 case IDE:
799 WARN_ON((i & 1) || map[i + 1] != IDE);
800 pinfo[i / 2] = piix_port_info[ich5_pata];
801 i++;
802 printk(" IDE IDE");
803 break;
804
805 default:
806 printk(" P%d", map[i]);
807 if (i & 1)
808 pinfo[i / 2].host_flags |= ATA_FLAG_SLAVE_POSS;
809 break;
810 }
811 }
812 printk(" ]\n");
813
814 if (invalid_map)
815 dev_printk(KERN_ERR, &pdev->dev,
816 "invalid MAP value %u\n", map_value);
817
d96715c1 818 hpriv->map = map;
d33f58b8
TH		 819}
820
1da177e4
LT		 821/**
822 * piix_init_one - Register PIIX ATA PCI device with kernel services
823 * @pdev: PCI device to register
824 * @ent: Entry in piix_pci_tbl matching with @pdev
825 *
826 * Called from kernel PCI layer. We probe for combined mode (sigh),
827 * and then hand over control to libata, for it to do the rest.
828 *
829 * LOCKING:
830 * Inherited from PCI layer (may sleep).
831 *
832 * RETURNS:
833 * Zero on success, or -ERRNO value.
834 */
835
836static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
837{
838 static int printed_version;
d33f58b8
TH		 839 struct ata_port_info port_info[2];
840 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
d96715c1 841 struct piix_host_priv *hpriv;
ff0fc146 842 unsigned long host_flags;
1da177e4
LT		 843
844 if (!printed_version++)
6248e647
JG		 845 dev_printk(KERN_DEBUG, &pdev->dev,
846 "version " DRV_VERSION "\n");
1da177e4
LT		 847
848 /* no hotplugging support (FIXME) */
849 if (!in_module_init)
850 return -ENODEV;
851
d96715c1
TH		 852 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
853 if (!hpriv)
854 return -ENOMEM;
855
d33f58b8
TH		 856 port_info[0] = piix_port_info[ent->driver_data];
857 port_info[1] = piix_port_info[ent->driver_data];
d96715c1
TH		 858 port_info[0].private_data = hpriv;
859 port_info[1].private_data = hpriv;
1da177e4 860
d33f58b8 861 host_flags = port_info[0].host_flags;
ff0fc146
TH		 862
863 if (host_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 864 u8 tmp;
865 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
866 if (tmp == PIIX_AHCI_DEVICE) {
867 int rc = piix_disable_ahci(pdev);
868 if (rc)
869 return rc;
870 }
1da177e4
LT		 871 }
872
d33f58b8
TH		 873 /* Initialize SATA map */
874 if (host_flags & ATA_FLAG_SATA)
d96715c1
TH		 875 piix_init_sata_map(pdev, port_info,
876 piix_map_db_table[ent->driver_data]);
1da177e4
LT		 877
878 /* On ICH5, some BIOSen disable the interrupt using the
879 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
880 * On ICH6, this bit has the same effect, but only when
881 * MSI is disabled (and it is disabled, as we don't use
882 * message-signalled interrupts currently).
883 */
ff0fc146 884 if (host_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 885 pci_intx(pdev, 1);
1da177e4 886
c621b140
AC		 887 if (piix_check_450nx_errata(pdev)) {
888 /* This writes into the master table but it does not
889 really matter for this errata as we will apply it to
890 all the PIIX devices on the board */
d33f58b8
TH		 891 port_info[0].mwdma_mask = 0;
892 port_info[0].udma_mask = 0;
893 port_info[1].mwdma_mask = 0;
894 port_info[1].udma_mask = 0;
c621b140 895 }
d33f58b8 896 return ata_pci_init_one(pdev, ppinfo, 2);
1da177e4
LT		 897}
898
d96715c1
TH		 899static void piix_host_stop(struct ata_host_set *host_set)
900{
901 if (host_set->next == NULL)
902 kfree(host_set->private_data);
903 ata_host_stop(host_set);
904}
905
1da177e4
LT		 906static int __init piix_init(void)
907{
908 int rc;
909
910 DPRINTK("pci_module_init\n");
911 rc = pci_module_init(&piix_pci_driver);
912 if (rc)
913 return rc;
914
915 in_module_init = 0;
916
917 DPRINTK("done\n");
918 return 0;
919}
920
1da177e4
LT		 921static void __exit piix_exit(void)
922{
923 pci_unregister_driver(&piix_pci_driver);
924}
925
926module_init(piix_init);
927module_exit(piix_exit);
928
Linux kernel - Deliverables
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