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[PATCH] sata_mv: endian annotations
[deliverable/linux.git] / drivers / scsi / ata_piix.c
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1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
94
95#define DRV_NAME "ata_piix"
af64371a 96#define DRV_VERSION "1.10"
1da177e4
LT		 97
98enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 102 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 103
219e6214 104 PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */
d4358048 105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108 PIIX_FLAG_COMBINED = (1 << 29), /* combined mode possible */
109 /* ICH6/7 use different scheme for map value */
110 PIIX_FLAG_COMBINED_ICH6 = PIIX_FLAG_COMBINED | (1 << 30),
1da177e4
LT		 111
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
6a690df5
HR		 115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
1d076e5b
TH		 121 /* controller IDs */
122 piix4_pata = 0,
123 ich5_pata = 1,
124 ich5_sata = 2,
125 esb_sata = 3,
126 ich6_sata = 4,
127 ich6_sata_ahci = 5,
128 ich6m_sata_ahci = 6,
7b6dbd68 129
d33f58b8
TH		 130 /* constants for mapping table */
131 P0 = 0, /* port 0 */
132 P1 = 1, /* port 1 */
133 P2 = 2, /* port 2 */
134 P3 = 3, /* port 3 */
135 IDE = -1, /* IDE */
136 NA = -2, /* not avaliable */
137 RV = -3, /* reserved */
138
7b6dbd68 139 PIIX_AHCI_DEVICE = 6,
1da177e4
LT		 140};
141
d33f58b8
TH		 142struct piix_map_db {
143 const u32 mask;
144 const int map[][4];
145};
146
1da177e4
LT		 147static int piix_init_one (struct pci_dev *pdev,
148 const struct pci_device_id *ent);
149
573db6b8 150static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes);
ccbe6d5e 151static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes);
1da177e4
LT		 152static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
153static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
154
155static unsigned int in_module_init = 1;
156
3b7d697d 157static const struct pci_device_id piix_pci_tbl[] = {
1da177e4
LT		 158#ifdef ATA_ENABLE_PATA
159 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
160 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
161 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
b74ba22f 162 { 0x8086, 0x27df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
1da177e4
LT		 163#endif
164
165 /* NOTE: The following PCI ids must be kept in sync with the
166 * list in drivers/pci/quirks.c.
167 */
168
1d076e5b 169 /* 82801EB (ICH5) */
1da177e4 170 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 171 /* 82801EB (ICH5) */
1da177e4 172 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b
TH		 173 /* 6300ESB (ICH5 variant with broken PCS present bits) */
174 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
175 /* 6300ESB pretending RAID */
176 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
177 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 178 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 179 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 180 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 181 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
182 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
183 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 184 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 185 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
186 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
187 /* Enterprise Southbridge 2 (where's the datasheet?) */
1c24a412 188 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 189 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
012b265f 190 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 191 /* SATA Controller 2 IDE (ICH8, ditto) */
012b265f 192 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 193 /* Mobile SATA Controller IDE (ICH8M, ditto) */
194 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
1da177e4
LT		 195
196 { } /* terminate list */
197};
198
199static struct pci_driver piix_pci_driver = {
200 .name = DRV_NAME,
201 .id_table = piix_pci_tbl,
202 .probe = piix_init_one,
203 .remove = ata_pci_remove_one,
9b847548
JA		 204 .suspend = ata_pci_device_suspend,
205 .resume = ata_pci_device_resume,
1da177e4
LT		 206};
207
193515d5 208static struct scsi_host_template piix_sht = {
1da177e4
LT		 209 .module = THIS_MODULE,
210 .name = DRV_NAME,
211 .ioctl = ata_scsi_ioctl,
212 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 213 .can_queue = ATA_DEF_QUEUE,
214 .this_id = ATA_SHT_THIS_ID,
215 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 216 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
217 .emulated = ATA_SHT_EMULATED,
218 .use_clustering = ATA_SHT_USE_CLUSTERING,
219 .proc_name = DRV_NAME,
220 .dma_boundary = ATA_DMA_BOUNDARY,
221 .slave_configure = ata_scsi_slave_config,
222 .bios_param = ata_std_bios_param,
9b847548
JA		 223 .resume = ata_scsi_device_resume,
224 .suspend = ata_scsi_device_suspend,
1da177e4
LT		 225};
226
057ace5e 227static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 228 .port_disable = ata_port_disable,
229 .set_piomode = piix_set_piomode,
230 .set_dmamode = piix_set_dmamode,
231
232 .tf_load = ata_tf_load,
233 .tf_read = ata_tf_read,
234 .check_status = ata_check_status,
235 .exec_command = ata_exec_command,
236 .dev_select = ata_std_dev_select,
237
573db6b8 238 .probe_reset = piix_pata_probe_reset,
1da177e4
LT		 239
240 .bmdma_setup = ata_bmdma_setup,
241 .bmdma_start = ata_bmdma_start,
242 .bmdma_stop = ata_bmdma_stop,
243 .bmdma_status = ata_bmdma_status,
244 .qc_prep = ata_qc_prep,
245 .qc_issue = ata_qc_issue_prot,
246
3f037db0
TH		 247 .freeze = ata_bmdma_freeze,
248 .thaw = ata_bmdma_thaw,
249 .error_handler = ata_bmdma_error_handler,
250 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 251
252 .irq_handler = ata_interrupt,
253 .irq_clear = ata_bmdma_irq_clear,
254
255 .port_start = ata_port_start,
256 .port_stop = ata_port_stop,
aa8f0dc6 257 .host_stop = ata_host_stop,
1da177e4
LT		 258};
259
057ace5e 260static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 261 .port_disable = ata_port_disable,
262
263 .tf_load = ata_tf_load,
264 .tf_read = ata_tf_read,
265 .check_status = ata_check_status,
266 .exec_command = ata_exec_command,
267 .dev_select = ata_std_dev_select,
268
ccbe6d5e 269 .probe_reset = piix_sata_probe_reset,
1da177e4
LT		 270
271 .bmdma_setup = ata_bmdma_setup,
272 .bmdma_start = ata_bmdma_start,
273 .bmdma_stop = ata_bmdma_stop,
274 .bmdma_status = ata_bmdma_status,
275 .qc_prep = ata_qc_prep,
276 .qc_issue = ata_qc_issue_prot,
277
3f037db0
TH		 278 .freeze = ata_bmdma_freeze,
279 .thaw = ata_bmdma_thaw,
280 .error_handler = ata_bmdma_error_handler,
281 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 282
283 .irq_handler = ata_interrupt,
284 .irq_clear = ata_bmdma_irq_clear,
285
286 .port_start = ata_port_start,
287 .port_stop = ata_port_stop,
aa8f0dc6 288 .host_stop = ata_host_stop,
1da177e4
LT		 289};
290
d33f58b8
TH		 291static struct piix_map_db ich5_map_db = {
292 .mask = 0x7,
293 .map = {
294 /* PM PS SM SS MAP */
295 { P0, NA, P1, NA }, /* 000b */
296 { P1, NA, P0, NA }, /* 001b */
297 { RV, RV, RV, RV },
298 { RV, RV, RV, RV },
299 { P0, P1, IDE, IDE }, /* 100b */
300 { P1, P0, IDE, IDE }, /* 101b */
301 { IDE, IDE, P0, P1 }, /* 110b */
302 { IDE, IDE, P1, P0 }, /* 111b */
303 },
304};
305
306static struct piix_map_db ich6_map_db = {
307 .mask = 0x3,
308 .map = {
309 /* PM PS SM SS MAP */
79ea24e7 310 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 311 { IDE, IDE, P1, P3 }, /* 01b */
312 { P0, P2, IDE, IDE }, /* 10b */
313 { RV, RV, RV, RV },
314 },
315};
316
317static struct piix_map_db ich6m_map_db = {
318 .mask = 0x3,
319 .map = {
320 /* PM PS SM SS MAP */
79ea24e7 321 { P0, P2, RV, RV }, /* 00b */
d33f58b8
TH		 322 { RV, RV, RV, RV },
323 { P0, P2, IDE, IDE }, /* 10b */
324 { RV, RV, RV, RV },
325 },
326};
327
1da177e4 328static struct ata_port_info piix_port_info[] = {
1d076e5b
TH		 329 /* piix4_pata */
330 {
331 .sht = &piix_sht,
332 .host_flags = ATA_FLAG_SLAVE_POSS,
333 .pio_mask = 0x1f, /* pio0-4 */
334#if 0
335 .mwdma_mask = 0x06, /* mwdma1-2 */
336#else
337 .mwdma_mask = 0x00, /* mwdma broken */
338#endif
339 .udma_mask = ATA_UDMA_MASK_40C,
340 .port_ops = &piix_pata_ops,
341 },
342
1da177e4
LT		 343 /* ich5_pata */
344 {
345 .sht = &piix_sht,
573db6b8 346 .host_flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
1da177e4
LT		 347 .pio_mask = 0x1f, /* pio0-4 */
348#if 0
349 .mwdma_mask = 0x06, /* mwdma1-2 */
350#else
351 .mwdma_mask = 0x00, /* mwdma broken */
352#endif
353 .udma_mask = 0x3f, /* udma0-5 */
354 .port_ops = &piix_pata_ops,
355 },
356
357 /* ich5_sata */
358 {
359 .sht = &piix_sht,
ccbe6d5e
TH		 360 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
361 PIIX_FLAG_CHECKINTR,
1da177e4
LT		 362 .pio_mask = 0x1f, /* pio0-4 */
363 .mwdma_mask = 0x07, /* mwdma0-2 */
364 .udma_mask = 0x7f, /* udma0-6 */
365 .port_ops = &piix_sata_ops,
d33f58b8 366 .private_data = &ich5_map_db,
1da177e4
LT		 367 },
368
1d076e5b 369 /* i6300esb_sata */
1da177e4
LT		 370 {
371 .sht = &piix_sht,
1d076e5b 372 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
219e6214 373 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS,
1da177e4 374 .pio_mask = 0x1f, /* pio0-4 */
1d076e5b
TH		 375 .mwdma_mask = 0x07, /* mwdma0-2 */
376 .udma_mask = 0x7f, /* udma0-6 */
377 .port_ops = &piix_sata_ops,
d33f58b8 378 .private_data = &ich5_map_db,
1da177e4
LT		 379 },
380
381 /* ich6_sata */
382 {
383 .sht = &piix_sht,
ccbe6d5e 384 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
d33f58b8 385 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR,
1da177e4
LT		 386 .pio_mask = 0x1f, /* pio0-4 */
387 .mwdma_mask = 0x07, /* mwdma0-2 */
388 .udma_mask = 0x7f, /* udma0-6 */
389 .port_ops = &piix_sata_ops,
d33f58b8 390 .private_data = &ich6_map_db,
1da177e4
LT		 391 },
392
1c24a412 393 /* ich6_sata_ahci */
c368ca4e
JG		 394 {
395 .sht = &piix_sht,
ccbe6d5e 396 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
d33f58b8
TH		 397 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
398 PIIX_FLAG_AHCI,
c368ca4e
JG		 399 .pio_mask = 0x1f, /* pio0-4 */
400 .mwdma_mask = 0x07, /* mwdma0-2 */
401 .udma_mask = 0x7f, /* udma0-6 */
402 .port_ops = &piix_sata_ops,
d33f58b8 403 .private_data = &ich6_map_db,
c368ca4e 404 },
1d076e5b
TH		 405
406 /* ich6m_sata_ahci */
407 {
408 .sht = &piix_sht,
409 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
d33f58b8
TH		 410 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
411 PIIX_FLAG_AHCI,
1d076e5b
TH		 412 .pio_mask = 0x1f, /* pio0-4 */
413 .mwdma_mask = 0x07, /* mwdma0-2 */
414 .udma_mask = 0x7f, /* udma0-6 */
415 .port_ops = &piix_sata_ops,
d33f58b8 416 .private_data = &ich6m_map_db,
1d076e5b 417 },
1da177e4
LT		 418};
419
420static struct pci_bits piix_enable_bits[] = {
421 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
422 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
423};
424
425MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
426MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
427MODULE_LICENSE("GPL");
428MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
429MODULE_VERSION(DRV_VERSION);
430
431/**
432 * piix_pata_cbl_detect - Probe host controller cable detect info
433 * @ap: Port for which cable detect info is desired
434 *
435 * Read 80c cable indicator from ATA PCI device's PCI config
436 * register. This register is normally set by firmware (BIOS).
437 *
438 * LOCKING:
439 * None (inherited from caller).
440 */
441static void piix_pata_cbl_detect(struct ata_port *ap)
442{
443 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
444 u8 tmp, mask;
445
446 /* no 80c support in host controller? */
447 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
448 goto cbl40;
449
450 /* check BIOS cable detect results */
451 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
452 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
453 if ((tmp & mask) == 0)
454 goto cbl40;
455
456 ap->cbl = ATA_CBL_PATA80;
457 return;
458
459cbl40:
460 ap->cbl = ATA_CBL_PATA40;
461 ap->udma_mask &= ATA_UDMA_MASK_40C;
462}
463
464/**
573db6b8
TH		 465 * piix_pata_probeinit - probeinit for PATA host controller
466 * @ap: Target port
1da177e4 467 *
573db6b8 468 * Probeinit including cable detection.
1da177e4
LT		 469 *
470 * LOCKING:
471 * None (inherited from caller).
472 */
573db6b8
TH		 473static void piix_pata_probeinit(struct ata_port *ap)
474{
475 piix_pata_cbl_detect(ap);
476 ata_std_probeinit(ap);
477}
1da177e4 478
573db6b8
TH		 479/**
480 * piix_pata_probe_reset - Perform reset on PATA port and classify
481 * @ap: Port to reset
482 * @classes: Resulting classes of attached devices
483 *
484 * Reset PATA phy and classify attached devices.
485 *
486 * LOCKING:
487 * None (inherited from caller).
488 */
489static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes)
1da177e4
LT		 490{
491 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
492
493 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
f15a1daf 494 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
573db6b8 495 return 0;
1da177e4
LT		 496 }
497
573db6b8
TH		 498 return ata_drive_probe_reset(ap, piix_pata_probeinit,
499 ata_std_softreset, NULL,
500 ata_std_postreset, classes);
1da177e4
LT		 501}
502
503/**
504 * piix_sata_probe - Probe PCI device for present SATA devices
505 * @ap: Port associated with the PCI device we wish to probe
506 *
d133ecab
TH		 507 * Reads and configures SATA PCI device's PCI config register
508 * Port Configuration and Status (PCS) to determine port and
509 * device availability.
1da177e4
LT		 510 *
511 * LOCKING:
512 * None (inherited from caller).
513 *
514 * RETURNS:
d133ecab 515 * Mask of avaliable devices on the port.
1da177e4 516 */
d133ecab 517static unsigned int piix_sata_probe (struct ata_port *ap)
1da177e4
LT		 518{
519 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
d133ecab
TH		 520 const unsigned int *map = ap->host_set->private_data;
521 int base = 2 * ap->hard_port_no;
522 unsigned int present_mask = 0;
523 int port, i;
1da177e4
LT		 524 u8 pcs;
525
1da177e4 526 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
d133ecab
TH		 527 DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base);
528
529 /* enable all ports on this ap and wait for them to settle */
530 for (i = 0; i < 2; i++) {
531 port = map[base + i];
532 if (port >= 0)
533 pcs |= 1 << port;
534 }
1da177e4 535
d133ecab
TH		 536 pci_write_config_byte(pdev, ICH5_PCS, pcs);
537 msleep(100);
1da177e4 538
d133ecab
TH		 539 /* let's see which devices are present */
540 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
541
542 for (i = 0; i < 2; i++) {
543 port = map[base + i];
544 if (port < 0)
545 continue;
219e6214 546 if (ap->flags & PIIX_FLAG_IGNORE_PCS || pcs & 1 << (4 + port))
d133ecab
TH		 547 present_mask |= 1 << i;
548 else
549 pcs &= ~(1 << port);
1da177e4
LT		 550 }
551
d133ecab
TH		 552 /* disable offline ports on non-AHCI controllers */
553 if (!(ap->flags & PIIX_FLAG_AHCI))
554 pci_write_config_byte(pdev, ICH5_PCS, pcs);
555
556 DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n",
557 ap->id, pcs, present_mask);
558
559 return present_mask;
1da177e4
LT		 560}
561
562/**
ccbe6d5e
TH		 563 * piix_sata_probe_reset - Perform reset on SATA port and classify
564 * @ap: Port to reset
565 * @classes: Resulting classes of attached devices
1da177e4 566 *
ccbe6d5e 567 * Reset SATA phy and classify attached devices.
1da177e4
LT		 568 *
569 * LOCKING:
570 * None (inherited from caller).
571 */
ccbe6d5e 572static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes)
1da177e4
LT		 573{
574 if (!piix_sata_probe(ap)) {
f15a1daf 575 ata_port_printk(ap, KERN_INFO, "SATA port has no device.\n");
ccbe6d5e 576 return 0;
1da177e4
LT		 577 }
578
ccbe6d5e
TH		 579 return ata_drive_probe_reset(ap, ata_std_probeinit,
580 ata_std_softreset, NULL,
581 ata_std_postreset, classes);
1da177e4
LT		 582}
583
584/**
585 * piix_set_piomode - Initialize host controller PATA PIO timings
586 * @ap: Port whose timings we are configuring
587 * @adev: um
1da177e4
LT		 588 *
589 * Set PIO mode for device, in host controller PCI config space.
590 *
591 * LOCKING:
592 * None (inherited from caller).
593 */
594
595static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
596{
597 unsigned int pio = adev->pio_mode - XFER_PIO_0;
598 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
599 unsigned int is_slave = (adev->devno != 0);
600 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
601 unsigned int slave_port = 0x44;
602 u16 master_data;
603 u8 slave_data;
604
605 static const /* ISP RTC */
606 u8 timings[][2] = { { 0, 0 },
607 { 0, 0 },
608 { 1, 0 },
609 { 2, 1 },
610 { 2, 3 }, };
611
612 pci_read_config_word(dev, master_port, &master_data);
613 if (is_slave) {
614 master_data |= 0x4000;
615 /* enable PPE, IE and TIME */
616 master_data |= 0x0070;
617 pci_read_config_byte(dev, slave_port, &slave_data);
618 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
619 slave_data |=
620 (timings[pio][0] << 2) |
621 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
622 } else {
623 master_data &= 0xccf8;
624 /* enable PPE, IE and TIME */
625 master_data |= 0x0007;
626 master_data |=
627 (timings[pio][0] << 12) |
628 (timings[pio][1] << 8);
629 }
630 pci_write_config_word(dev, master_port, master_data);
631 if (is_slave)
632 pci_write_config_byte(dev, slave_port, slave_data);
633}
634
635/**
636 * piix_set_dmamode - Initialize host controller PATA PIO timings
637 * @ap: Port whose timings we are configuring
638 * @adev: um
639 * @udma: udma mode, 0 - 6
640 *
641 * Set UDMA mode for device, in host controller PCI config space.
642 *
643 * LOCKING:
644 * None (inherited from caller).
645 */
646
647static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
648{
649 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
650 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
651 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
652 u8 speed = udma;
653 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
654 int a_speed = 3 << (drive_dn * 4);
655 int u_flag = 1 << drive_dn;
656 int v_flag = 0x01 << drive_dn;
657 int w_flag = 0x10 << drive_dn;
658 int u_speed = 0;
659 int sitre;
660 u16 reg4042, reg4a;
661 u8 reg48, reg54, reg55;
662
663 pci_read_config_word(dev, maslave, &reg4042);
664 DPRINTK("reg4042 = 0x%04x\n", reg4042);
665 sitre = (reg4042 & 0x4000) ? 1 : 0;
666 pci_read_config_byte(dev, 0x48, &reg48);
667 pci_read_config_word(dev, 0x4a, &reg4a);
668 pci_read_config_byte(dev, 0x54, &reg54);
669 pci_read_config_byte(dev, 0x55, &reg55);
670
671 switch(speed) {
672 case XFER_UDMA_4:
673 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
674 case XFER_UDMA_6:
675 case XFER_UDMA_5:
676 case XFER_UDMA_3:
677 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
678 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
679 case XFER_MW_DMA_2:
680 case XFER_MW_DMA_1: break;
681 default:
682 BUG();
683 return;
684 }
685
686 if (speed >= XFER_UDMA_0) {
687 if (!(reg48 & u_flag))
688 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
689 if (speed == XFER_UDMA_5) {
690 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
691 } else {
692 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
693 }
694 if ((reg4a & a_speed) != u_speed)
695 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
696 if (speed > XFER_UDMA_2) {
697 if (!(reg54 & v_flag))
698 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
699 } else
700 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
701 } else {
702 if (reg48 & u_flag)
703 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
704 if (reg4a & a_speed)
705 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
706 if (reg54 & v_flag)
707 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
708 if (reg55 & w_flag)
709 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
710 }
711}
712
1da177e4
LT		 713#define AHCI_PCI_BAR 5
714#define AHCI_GLOBAL_CTL 0x04
715#define AHCI_ENABLE (1 << 31)
716static int piix_disable_ahci(struct pci_dev *pdev)
717{
ea6ba10b 718 void __iomem *mmio;
1da177e4
LT		 719 u32 tmp;
720 int rc = 0;
721
722 /* BUG: pci_enable_device has not yet been called. This
723 * works because this device is usually set up by BIOS.
724 */
725
374b1873
JG		 726 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
727 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 728 return 0;
7b6dbd68 729
374b1873 730 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 731 if (!mmio)
732 return -ENOMEM;
7b6dbd68 733
1da177e4
LT		 734 tmp = readl(mmio + AHCI_GLOBAL_CTL);
735 if (tmp & AHCI_ENABLE) {
736 tmp &= ~AHCI_ENABLE;
737 writel(tmp, mmio + AHCI_GLOBAL_CTL);
738
739 tmp = readl(mmio + AHCI_GLOBAL_CTL);
740 if (tmp & AHCI_ENABLE)
741 rc = -EIO;
742 }
7b6dbd68 743
374b1873 744 pci_iounmap(pdev, mmio);
1da177e4
LT		 745 return rc;
746}
747
c621b140
AC		 748/**
749 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 750 * @ata_dev: the PCI device to check
2e9edbf8 751 *
c621b140
AC		 752 * Check for the present of 450NX errata #19 and errata #25. If
753 * they are found return an error code so we can turn off DMA
754 */
755
756static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
757{
758 struct pci_dev *pdev = NULL;
759 u16 cfg;
760 u8 rev;
761 int no_piix_dma = 0;
2e9edbf8 762
c621b140
AC		 763 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
764 {
765 /* Look for 450NX PXB. Check for problem configurations
766 A PCI quirk checks bit 6 already */
767 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
768 pci_read_config_word(pdev, 0x41, &cfg);
769 /* Only on the original revision: IDE DMA can hang */
770 if(rev == 0x00)
771 no_piix_dma = 1;
772 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
773 else if(cfg & (1<<14) && rev < 5)
774 no_piix_dma = 2;
775 }
776 if(no_piix_dma)
777 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
778 if(no_piix_dma == 2)
779 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
780 return no_piix_dma;
2e9edbf8 781}
c621b140 782
d33f58b8
TH		 783static void __devinit piix_init_sata_map(struct pci_dev *pdev,
784 struct ata_port_info *pinfo)
785{
786 struct piix_map_db *map_db = pinfo[0].private_data;
787 const unsigned int *map;
788 int i, invalid_map = 0;
789 u8 map_value;
790
791 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
792
793 map = map_db->map[map_value & map_db->mask];
794
795 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
796 for (i = 0; i < 4; i++) {
797 switch (map[i]) {
798 case RV:
799 invalid_map = 1;
800 printk(" XX");
801 break;
802
803 case NA:
804 printk(" --");
805 break;
806
807 case IDE:
808 WARN_ON((i & 1) || map[i + 1] != IDE);
809 pinfo[i / 2] = piix_port_info[ich5_pata];
810 i++;
811 printk(" IDE IDE");
812 break;
813
814 default:
815 printk(" P%d", map[i]);
816 if (i & 1)
817 pinfo[i / 2].host_flags |= ATA_FLAG_SLAVE_POSS;
818 break;
819 }
820 }
821 printk(" ]\n");
822
823 if (invalid_map)
824 dev_printk(KERN_ERR, &pdev->dev,
825 "invalid MAP value %u\n", map_value);
826
827 pinfo[0].private_data = (void *)map;
828 pinfo[1].private_data = (void *)map;
829}
830
1da177e4
LT		 831/**
832 * piix_init_one - Register PIIX ATA PCI device with kernel services
833 * @pdev: PCI device to register
834 * @ent: Entry in piix_pci_tbl matching with @pdev
835 *
836 * Called from kernel PCI layer. We probe for combined mode (sigh),
837 * and then hand over control to libata, for it to do the rest.
838 *
839 * LOCKING:
840 * Inherited from PCI layer (may sleep).
841 *
842 * RETURNS:
843 * Zero on success, or -ERRNO value.
844 */
845
846static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
847{
848 static int printed_version;
d33f58b8
TH		 849 struct ata_port_info port_info[2];
850 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
ff0fc146 851 unsigned long host_flags;
1da177e4
LT		 852
853 if (!printed_version++)
6248e647
JG		 854 dev_printk(KERN_DEBUG, &pdev->dev,
855 "version " DRV_VERSION "\n");
1da177e4
LT		 856
857 /* no hotplugging support (FIXME) */
858 if (!in_module_init)
859 return -ENODEV;
860
d33f58b8
TH		 861 port_info[0] = piix_port_info[ent->driver_data];
862 port_info[1] = piix_port_info[ent->driver_data];
1da177e4 863
d33f58b8 864 host_flags = port_info[0].host_flags;
ff0fc146
TH		 865
866 if (host_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 867 u8 tmp;
868 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
869 if (tmp == PIIX_AHCI_DEVICE) {
870 int rc = piix_disable_ahci(pdev);
871 if (rc)
872 return rc;
873 }
1da177e4
LT		 874 }
875
d33f58b8
TH		 876 /* Initialize SATA map */
877 if (host_flags & ATA_FLAG_SATA)
878 piix_init_sata_map(pdev, port_info);
1da177e4
LT		 879
880 /* On ICH5, some BIOSen disable the interrupt using the
881 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
882 * On ICH6, this bit has the same effect, but only when
883 * MSI is disabled (and it is disabled, as we don't use
884 * message-signalled interrupts currently).
885 */
ff0fc146 886 if (host_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 887 pci_intx(pdev, 1);
1da177e4 888
c621b140
AC		 889 if (piix_check_450nx_errata(pdev)) {
890 /* This writes into the master table but it does not
891 really matter for this errata as we will apply it to
892 all the PIIX devices on the board */
d33f58b8
TH		 893 port_info[0].mwdma_mask = 0;
894 port_info[0].udma_mask = 0;
895 port_info[1].mwdma_mask = 0;
896 port_info[1].udma_mask = 0;
c621b140 897 }
d33f58b8 898 return ata_pci_init_one(pdev, ppinfo, 2);
1da177e4
LT		 899}
900
1da177e4
LT		 901static int __init piix_init(void)
902{
903 int rc;
904
905 DPRINTK("pci_module_init\n");
906 rc = pci_module_init(&piix_pci_driver);
907 if (rc)
908 return rc;
909
910 in_module_init = 0;
911
912 DPRINTK("done\n");
913 return 0;
914}
915
1da177e4
LT		 916static void __exit piix_exit(void)
917{
918 pci_unregister_driver(&piix_pci_driver);
919}
920
921module_init(piix_init);
922module_exit(piix_exit);
923
Linux kernel - Deliverables
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