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atp870u: Convert is880() to use wrappers
[deliverable/linux.git] / drivers / scsi / atp870u.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (C) 1997 Wu Ching Chen
3 * 2.1.x update (C) 1998 Krzysztof G. Baranowski
fa195afe
AC		 4 * 2.5.x update (C) 2002 Red Hat
5 * 2.6.x update (C) 2004 Red Hat
1da177e4
LT		 6 *
7 * Marcelo Tosatti <marcelo@conectiva.com.br> : SMP fixes
8 *
9 * Wu Ching Chen : NULL pointer fixes 2000/06/02
10 * support atp876 chip
11 * enable 32 bit fifo transfer
12 * support cdrom & remove device run ultra speed
13 * fix disconnect bug 2000/12/21
14 * support atp880 chip lvd u160 2001/05/15
15 * fix prd table bug 2001/09/12 (7.1)
16 *
17 * atp885 support add by ACARD Hao Ping Lian 2005/01/05
18 */
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/string.h>
25#include <linux/ioport.h>
26#include <linux/delay.h>
27#include <linux/proc_fs.h>
28#include <linux/spinlock.h>
29#include <linux/pci.h>
30#include <linux/blkdev.h>
910638ae 31#include <linux/dma-mapping.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include <asm/io.h>
34
35#include <scsi/scsi.h>
36#include <scsi/scsi_cmnd.h>
37#include <scsi/scsi_device.h>
38#include <scsi/scsi_host.h>
39
40#include "atp870u.h"
41
42static struct scsi_host_template atp870u_template;
43static void send_s870(struct atp_unit *dev,unsigned char c);
44static void is885(struct atp_unit *dev, unsigned int wkport,unsigned char c);
45static void tscam_885(void);
46
6a3cebb6
OZ		 47static inline void atp_writeb_base(struct atp_unit *atp, u8 reg, u8 val)
48{
49 outb(val, atp->baseport + reg);
50}
51
52static inline void atp_writeb_io(struct atp_unit *atp, u8 channel, u8 reg, u8 val)
53{
54 outb(val, atp->ioport[channel] + reg);
55}
56
57static inline void atp_writew_io(struct atp_unit *atp, u8 channel, u8 reg, u16 val)
58{
59 outw(val, atp->ioport[channel] + reg);
60}
61
62static inline void atp_writeb_pci(struct atp_unit *atp, u8 channel, u8 reg, u8 val)
63{
64 outb(val, atp->pciport[channel] + reg);
65}
66
67static inline void atp_writel_pci(struct atp_unit *atp, u8 channel, u8 reg, u32 val)
68{
69 outl(val, atp->pciport[channel] + reg);
70}
71
72static inline u8 atp_readb_base(struct atp_unit *atp, u8 reg)
73{
74 return inb(atp->baseport + reg);
75}
76
77static inline u8 atp_readb_io(struct atp_unit *atp, u8 channel, u8 reg)
78{
79 return inb(atp->ioport[channel] + reg);
80}
81
82static inline u16 atp_readw_io(struct atp_unit *atp, u8 channel, u8 reg)
83{
84 return inw(atp->ioport[channel] + reg);
85}
86
87static inline u8 atp_readb_pci(struct atp_unit *atp, u8 channel, u8 reg)
88{
89 return inb(atp->pciport[channel] + reg);
90}
91
7d12e780 92static irqreturn_t atp870u_intr_handle(int irq, void *dev_id)
1da177e4
LT		 93{
94 unsigned long flags;
bc0fe4c9 95 unsigned short int id;
1da177e4
LT		 96 unsigned char i, j, c, target_id, lun,cmdp;
97 unsigned char *prd;
98 struct scsi_cmnd *workreq;
1da177e4
LT		 99 unsigned long adrcnt, k;
100#ifdef ED_DBGP
101 unsigned long l;
102#endif
1da177e4
LT		 103 struct Scsi_Host *host = dev_id;
104 struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
105
106 for (c = 0; c < 2; c++) {
6a3cebb6 107 j = atp_readb_io(dev, c, 0x1f);
1da177e4 108 if ((j & 0x80) != 0)
78614ecd 109 break;
1da177e4
LT		 110 dev->in_int[c] = 0;
111 }
78614ecd
OZ		 112 if ((j & 0x80) == 0)
113 return IRQ_NONE;
1da177e4
LT		 114#ifdef ED_DBGP
115 printk("atp870u_intr_handle enter\n");
116#endif
117 dev->in_int[c] = 1;
6a3cebb6 118 cmdp = atp_readb_io(dev, c, 0x10);
1da177e4
LT		 119 if (dev->working[c] != 0) {
120 if (dev->dev_id == ATP885_DEVID) {
6a3cebb6
OZ		 121 if ((atp_readb_io(dev, c, 0x16) & 0x80) == 0)
122 atp_writeb_io(dev, c, 0x16, (atp_readb_io(dev, c, 0x16) | 0x80));
1da177e4 123 }
6a3cebb6 124 if ((atp_readb_pci(dev, c, 0x00) & 0x08) != 0)
1da177e4 125 {
1da177e4 126 for (k=0; k < 1000; k++) {
6a3cebb6 127 if ((atp_readb_pci(dev, c, 2) & 0x08) == 0)
78614ecd 128 break;
6a3cebb6 129 if ((atp_readb_pci(dev, c, 2) & 0x01) == 0)
78614ecd 130 break;
1da177e4
LT		 131 }
132 }
6a3cebb6 133 atp_writeb_pci(dev, c, 0, 0x00);
1da177e4 134
6a3cebb6 135 i = atp_readb_io(dev, c, 0x17);
1da177e4 136
bc0fe4c9 137 if (dev->dev_id == ATP885_DEVID)
6a3cebb6 138 atp_writeb_pci(dev, c, 2, 0x06);
1da177e4 139
6a3cebb6 140 target_id = atp_readb_io(dev, c, 0x15);
1da177e4
LT		 141
142 /*
143 * Remap wide devices onto id numbers
144 */
145
146 if ((target_id & 0x40) != 0) {
147 target_id = (target_id & 0x07) | 0x08;
148 } else {
149 target_id &= 0x07;
150 }
151
152 if ((j & 0x40) != 0) {
153 if (dev->last_cmd[c] == 0xff) {
154 dev->last_cmd[c] = target_id;
155 }
156 dev->last_cmd[c] |= 0x40;
157 }
158 if (dev->dev_id == ATP885_DEVID)
159 dev->r1f[c][target_id] |= j;
160#ifdef ED_DBGP
161 printk("atp870u_intr_handle status = %x\n",i);
162#endif
163 if (i == 0x85) {
164 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
165 dev->last_cmd[c] = 0xff;
166 }
167 if (dev->dev_id == ATP885_DEVID) {
1da177e4 168 adrcnt = 0;
6a3cebb6
OZ		 169 ((unsigned char *) &adrcnt)[2] = atp_readb_io(dev, c, 0x12);
170 ((unsigned char *) &adrcnt)[1] = atp_readb_io(dev, c, 0x13);
171 ((unsigned char *) &adrcnt)[0] = atp_readb_io(dev, c, 0x14);
1da177e4
LT		 172 if (dev->id[c][target_id].last_len != adrcnt)
173 {
174 k = dev->id[c][target_id].last_len;
175 k -= adrcnt;
176 dev->id[c][target_id].tran_len = k;
177 dev->id[c][target_id].last_len = adrcnt;
178 }
179#ifdef ED_DBGP
3a38e53e 180 printk("dev->id[c][target_id].last_len = %d dev->id[c][target_id].tran_len = %d\n",dev->id[c][target_id].last_len,dev->id[c][target_id].tran_len);
1da177e4
LT		 181#endif
182 }
183
184 /*
185 * Flip wide
186 */
187 if (dev->wide_id[c] != 0) {
6a3cebb6
OZ		 188 atp_writeb_io(dev, c, 0x1b, 0x01);
189 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != 0x01)
190 atp_writeb_io(dev, c, 0x1b, 0x01);
1da177e4
LT		 191 }
192 /*
193 * Issue more commands
194 */
195 spin_lock_irqsave(dev->host->host_lock, flags);
196 if (((dev->quhd[c] != dev->quend[c]) || (dev->last_cmd[c] != 0xff)) &&
197 (dev->in_snd[c] == 0)) {
198#ifdef ED_DBGP
199 printk("Call sent_s870\n");
200#endif
201 send_s870(dev,c);
202 }
203 spin_unlock_irqrestore(dev->host->host_lock, flags);
204 /*
205 * Done
206 */
207 dev->in_int[c] = 0;
208#ifdef ED_DBGP
209 printk("Status 0x85 return\n");
210#endif
78614ecd 211 return IRQ_HANDLED;
1da177e4
LT		 212 }
213
214 if (i == 0x40) {
215 dev->last_cmd[c] |= 0x40;
216 dev->in_int[c] = 0;
78614ecd 217 return IRQ_HANDLED;
1da177e4
LT		 218 }
219
220 if (i == 0x21) {
221 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
222 dev->last_cmd[c] = 0xff;
223 }
1da177e4 224 adrcnt = 0;
6a3cebb6
OZ		 225 ((unsigned char *) &adrcnt)[2] = atp_readb_io(dev, c, 0x12);
226 ((unsigned char *) &adrcnt)[1] = atp_readb_io(dev, c, 0x13);
227 ((unsigned char *) &adrcnt)[0] = atp_readb_io(dev, c, 0x14);
1da177e4
LT		 228 k = dev->id[c][target_id].last_len;
229 k -= adrcnt;
230 dev->id[c][target_id].tran_len = k;
231 dev->id[c][target_id].last_len = adrcnt;
6a3cebb6
OZ		 232 atp_writeb_io(dev, c, 0x10, 0x41);
233 atp_writeb_io(dev, c, 0x18, 0x08);
1da177e4 234 dev->in_int[c] = 0;
78614ecd 235 return IRQ_HANDLED;
1da177e4
LT		 236 }
237
238 if (dev->dev_id == ATP885_DEVID) {
239 if ((i == 0x4c) || (i == 0x4d) || (i == 0x8c) || (i == 0x8d)) {
240 if ((i == 0x4c) || (i == 0x8c))
241 i=0x48;
242 else
243 i=0x49;
244 }
245
246 }
247 if ((i == 0x80) || (i == 0x8f)) {
248#ifdef ED_DBGP
249 printk(KERN_DEBUG "Device reselect\n");
250#endif
251 lun = 0;
6a3cebb6
OZ		 252 if (cmdp == 0x44 || i == 0x80)
253 lun = atp_readb_io(dev, c, 0x1d) & 0x07;
254 else {
1da177e4
LT		 255 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
256 dev->last_cmd[c] = 0xff;
257 }
258 if (cmdp == 0x41) {
259#ifdef ED_DBGP
260 printk("cmdp = 0x41\n");
261#endif
1da177e4 262 adrcnt = 0;
6a3cebb6
OZ		 263 ((unsigned char *) &adrcnt)[2] = atp_readb_io(dev, c, 0x12);
264 ((unsigned char *) &adrcnt)[1] = atp_readb_io(dev, c, 0x13);
265 ((unsigned char *) &adrcnt)[0] = atp_readb_io(dev, c, 0x14);
1da177e4
LT		 266 k = dev->id[c][target_id].last_len;
267 k -= adrcnt;
268 dev->id[c][target_id].tran_len = k;
269 dev->id[c][target_id].last_len = adrcnt;
6a3cebb6 270 atp_writeb_io(dev, c, 0x18, 0x08);
1da177e4 271 dev->in_int[c] = 0;
78614ecd 272 return IRQ_HANDLED;
1da177e4
LT		 273 } else {
274#ifdef ED_DBGP
275 printk("cmdp != 0x41\n");
276#endif
6a3cebb6 277 atp_writeb_io(dev, c, 0x10, 0x46);
1da177e4 278 dev->id[c][target_id].dirct = 0x00;
6a3cebb6
OZ		 279 atp_writeb_io(dev, c, 0x12, 0x00);
280 atp_writeb_io(dev, c, 0x13, 0x00);
281 atp_writeb_io(dev, c, 0x14, 0x00);
282 atp_writeb_io(dev, c, 0x18, 0x08);
1da177e4 283 dev->in_int[c] = 0;
78614ecd 284 return IRQ_HANDLED;
1da177e4
LT		 285 }
286 }
287 if (dev->last_cmd[c] != 0xff) {
288 dev->last_cmd[c] |= 0x40;
289 }
290 if (dev->dev_id == ATP885_DEVID) {
6a3cebb6
OZ		 291 j = atp_readb_base(dev, 0x29) & 0xfe;
292 atp_writeb_base(dev, 0x29, j);
3a38e53e 293 } else
6a3cebb6 294 atp_writeb_io(dev, c, 0x10, 0x45);
3a38e53e 295
6a3cebb6 296 target_id = atp_readb_io(dev, c, 0x16);
1da177e4
LT		 297 /*
298 * Remap wide identifiers
299 */
300 if ((target_id & 0x10) != 0) {
301 target_id = (target_id & 0x07) | 0x08;
302 } else {
303 target_id &= 0x07;
304 }
3a38e53e 305 if (dev->dev_id == ATP885_DEVID)
6a3cebb6 306 atp_writeb_io(dev, c, 0x10, 0x45);
1da177e4
LT		 307 workreq = dev->id[c][target_id].curr_req;
308#ifdef ED_DBGP
017560fc
JG		 309 scmd_printk(KERN_DEBUG, workreq, "CDB");
310 for (l = 0; l < workreq->cmd_len; l++)
1da177e4 311 printk(KERN_DEBUG " %x",workreq->cmnd[l]);
017560fc 312 printk("\n");
1da177e4
LT		 313#endif
314
6a3cebb6
OZ		 315 atp_writeb_io(dev, c, 0x0f, lun);
316 atp_writeb_io(dev, c, 0x11, dev->id[c][target_id].devsp);
1da177e4
LT		 317 adrcnt = dev->id[c][target_id].tran_len;
318 k = dev->id[c][target_id].last_len;
319
6a3cebb6
OZ		 320 atp_writeb_io(dev, c, 0x12, ((unsigned char *) &k)[2]);
321 atp_writeb_io(dev, c, 0x13, ((unsigned char *) &k)[1]);
322 atp_writeb_io(dev, c, 0x14, ((unsigned char *) &k)[0]);
1da177e4 323#ifdef ED_DBGP
6a3cebb6 324 printk("k %x, k[0] 0x%x k[1] 0x%x k[2] 0x%x\n", k, atp_readb_io(dev, c, 0x14), atp_readb_io(dev, c, 0x13), atp_readb_io(dev, c, 0x12));
1da177e4
LT		 325#endif
326 /* Remap wide */
327 j = target_id;
328 if (target_id > 7) {
329 j = (j & 0x07) | 0x40;
330 }
331 /* Add direction */
332 j |= dev->id[c][target_id].dirct;
6a3cebb6
OZ		 333 atp_writeb_io(dev, c, 0x15, j);
334 atp_writeb_io(dev, c, 0x16, 0x80);
1da177e4
LT		 335
336 /* enable 32 bit fifo transfer */
337 if (dev->dev_id == ATP885_DEVID) {
6a3cebb6 338 i = atp_readb_pci(dev, c, 1) & 0xf3;
1da177e4
LT		 339 //j=workreq->cmnd[0];
340 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
341 i |= 0x0c;
342 }
6a3cebb6 343 atp_writeb_pci(dev, c, 1, i);
1da177e4
LT		 344 } else if ((dev->dev_id == ATP880_DEVID1) ||
345 (dev->dev_id == ATP880_DEVID2) ) {
6a3cebb6
OZ		 346 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a))
347 atp_writeb_base(dev, 0x3b, (atp_readb_base(dev, 0x3b) & 0x3f) | 0xc0);
348 else
349 atp_writeb_base(dev, 0x3b, atp_readb_base(dev, 0x3b) & 0x3f);
1da177e4 350 } else {
6a3cebb6
OZ		 351 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a))
352 atp_writeb_io(dev, c, 0x3a, (atp_readb_io(dev, c, 0x3a) & 0xf3) | 0x08);
353 else
354 atp_writeb_io(dev, c, 0x3a, atp_readb_io(dev, c, 0x3a) & 0xf3);
1da177e4 355 }
1da177e4
LT		 356 j = 0;
357 id = 1;
358 id = id << target_id;
359 /*
360 * Is this a wide device
361 */
362 if ((id & dev->wide_id[c]) != 0) {
363 j |= 0x01;
364 }
6a3cebb6
OZ		 365 atp_writeb_io(dev, c, 0x1b, j);
366 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != j)
367 atp_writeb_io(dev, c, 0x1b, j);
1da177e4 368 if (dev->id[c][target_id].last_len == 0) {
6a3cebb6 369 atp_writeb_io(dev, c, 0x18, 0x08);
1da177e4
LT		 370 dev->in_int[c] = 0;
371#ifdef ED_DBGP
372 printk("dev->id[c][target_id].last_len = 0\n");
373#endif
78614ecd 374 return IRQ_HANDLED;
1da177e4
LT		 375 }
376#ifdef ED_DBGP
377 printk("target_id = %d adrcnt = %d\n",target_id,adrcnt);
378#endif
379 prd = dev->id[c][target_id].prd_pos;
380 while (adrcnt != 0) {
381 id = ((unsigned short int *)prd)[2];
382 if (id == 0) {
383 k = 0x10000;
384 } else {
385 k = id;
386 }
387 if (k > adrcnt) {
388 ((unsigned short int *)prd)[2] = (unsigned short int)
389 (k - adrcnt);
390 ((unsigned long *)prd)[0] += adrcnt;
391 adrcnt = 0;
392 dev->id[c][target_id].prd_pos = prd;
393 } else {
394 adrcnt -= k;
395 dev->id[c][target_id].prdaddr += 0x08;
396 prd += 0x08;
397 if (adrcnt == 0) {
398 dev->id[c][target_id].prd_pos = prd;
399 }
400 }
401 }
6a3cebb6 402 atp_writel_pci(dev, c, 0x04, dev->id[c][target_id].prdaddr);
1da177e4
LT		 403#ifdef ED_DBGP
404 printk("dev->id[%d][%d].prdaddr 0x%8x\n", c, target_id, dev->id[c][target_id].prdaddr);
405#endif
bc0fe4c9 406 if (dev->dev_id != ATP885_DEVID) {
6a3cebb6
OZ		 407 atp_writeb_pci(dev, c, 2, 0x06);
408 atp_writeb_pci(dev, c, 2, 0x00);
1da177e4 409 }
1da177e4
LT		 410 /*
411 * Check transfer direction
412 */
413 if (dev->id[c][target_id].dirct != 0) {
6a3cebb6
OZ		 414 atp_writeb_io(dev, c, 0x18, 0x08);
415 atp_writeb_pci(dev, c, 0, 0x01);
1da177e4
LT		 416 dev->in_int[c] = 0;
417#ifdef ED_DBGP
418 printk("status 0x80 return dirct != 0\n");
419#endif
78614ecd 420 return IRQ_HANDLED;
1da177e4 421 }
6a3cebb6
OZ		 422 atp_writeb_io(dev, c, 0x18, 0x08);
423 atp_writeb_pci(dev, c, 0, 0x09);
1da177e4
LT		 424 dev->in_int[c] = 0;
425#ifdef ED_DBGP
426 printk("status 0x80 return dirct = 0\n");
427#endif
78614ecd 428 return IRQ_HANDLED;
1da177e4
LT		 429 }
430
431 /*
432 * Current scsi request on this target
433 */
434
435 workreq = dev->id[c][target_id].curr_req;
436
78614ecd 437 if (i == 0x42 || i == 0x16) {
1da177e4
LT		 438 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
439 dev->last_cmd[c] = 0xff;
440 }
78614ecd 441 if (i == 0x16) {
6a3cebb6 442 workreq->result = atp_readb_io(dev, c, 0x0f);
78614ecd
OZ		 443 if (((dev->r1f[c][target_id] & 0x10) != 0)&&(dev->dev_id==ATP885_DEVID)) {
444 printk(KERN_WARNING "AEC67162 CRC ERROR !\n");
445 workreq->result = 0x02;
446 }
447 } else
448 workreq->result = 0x02;
449
1da177e4 450 if (dev->dev_id == ATP885_DEVID) {
6a3cebb6
OZ		 451 j = atp_readb_base(dev, 0x29) | 0x01;
452 atp_writeb_base(dev, 0x29, j);
1da177e4
LT		 453 }
454 /*
455 * Complete the command
456 */
fe7ed98f
BH		 457 scsi_dma_unmap(workreq);
458
1da177e4
LT		 459 spin_lock_irqsave(dev->host->host_lock, flags);
460 (*workreq->scsi_done) (workreq);
461#ifdef ED_DBGP
462 printk("workreq->scsi_done\n");
463#endif
464 /*
465 * Clear it off the queue
466 */
467 dev->id[c][target_id].curr_req = NULL;
468 dev->working[c]--;
469 spin_unlock_irqrestore(dev->host->host_lock, flags);
470 /*
471 * Take it back wide
472 */
473 if (dev->wide_id[c] != 0) {
6a3cebb6
OZ		 474 atp_writeb_io(dev, c, 0x1b, 0x01);
475 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != 0x01)
476 atp_writeb_io(dev, c, 0x1b, 0x01);
1da177e4
LT		 477 }
478 /*
479 * If there is stuff to send and nothing going then send it
480 */
481 spin_lock_irqsave(dev->host->host_lock, flags);
482 if (((dev->last_cmd[c] != 0xff) || (dev->quhd[c] != dev->quend[c])) &&
483 (dev->in_snd[c] == 0)) {
484#ifdef ED_DBGP
485 printk("Call sent_s870(scsi_done)\n");
486#endif
487 send_s870(dev,c);
488 }
489 spin_unlock_irqrestore(dev->host->host_lock, flags);
490 dev->in_int[c] = 0;
78614ecd 491 return IRQ_HANDLED;
1da177e4
LT		 492 }
493 if ((dev->last_cmd[c] & 0xf0) != 0x40) {
494 dev->last_cmd[c] = 0xff;
495 }
496 if (i == 0x4f) {
497 i = 0x89;
498 }
499 i &= 0x0f;
500 if (i == 0x09) {
6a3cebb6
OZ		 501 atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr);
502 atp_writeb_pci(dev, c, 2, 0x06);
503 atp_writeb_pci(dev, c, 2, 0x00);
504 atp_writeb_io(dev, c, 0x10, 0x41);
1da177e4 505 if (dev->dev_id == ATP885_DEVID) {
1da177e4 506 k = dev->id[c][target_id].last_len;
6a3cebb6
OZ		 507 atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&k))[2]);
508 atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&k))[1]);
509 atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&k))[0]);
1da177e4 510 dev->id[c][target_id].dirct = 0x00;
1da177e4
LT		 511 } else {
512 dev->id[c][target_id].dirct = 0x00;
1da177e4 513 }
6a3cebb6
OZ		 514 atp_writeb_io(dev, c, 0x18, 0x08);
515 atp_writeb_pci(dev, c, 0, 0x09);
1da177e4 516 dev->in_int[c] = 0;
78614ecd 517 return IRQ_HANDLED;
1da177e4
LT		 518 }
519 if (i == 0x08) {
6a3cebb6
OZ		 520 atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr);
521 atp_writeb_pci(dev, c, 2, 0x06);
522 atp_writeb_pci(dev, c, 2, 0x00);
523 atp_writeb_io(dev, c, 0x10, 0x41);
1da177e4 524 if (dev->dev_id == ATP885_DEVID) {
1da177e4 525 k = dev->id[c][target_id].last_len;
6a3cebb6
OZ		 526 atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&k))[2]);
527 atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&k))[1]);
528 atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&k))[0]);
1da177e4 529 }
6a3cebb6 530 atp_writeb_io(dev, c, 0x15, atp_readb_io(dev, c, 0x15) | 0x20);
1da177e4 531 dev->id[c][target_id].dirct = 0x20;
6a3cebb6
OZ		 532 atp_writeb_io(dev, c, 0x18, 0x08);
533 atp_writeb_pci(dev, c, 0, 0x01);
1da177e4 534 dev->in_int[c] = 0;
78614ecd 535 return IRQ_HANDLED;
1da177e4 536 }
6a3cebb6
OZ		 537 if (i == 0x0a)
538 atp_writeb_io(dev, c, 0x10, 0x30);
539 else
540 atp_writeb_io(dev, c, 0x10, 0x46);
1da177e4 541 dev->id[c][target_id].dirct = 0x00;
6a3cebb6
OZ		 542 atp_writeb_io(dev, c, 0x12, 0x00);
543 atp_writeb_io(dev, c, 0x13, 0x00);
544 atp_writeb_io(dev, c, 0x14, 0x00);
545 atp_writeb_io(dev, c, 0x18, 0x08);
1da177e4 546 }
78614ecd
OZ		 547 dev->in_int[c] = 0;
548
1da177e4
LT		 549 return IRQ_HANDLED;
550}
551/**
552 * atp870u_queuecommand - Queue SCSI command
553 * @req_p: request block
554 * @done: completion function
555 *
556 * Queue a command to the ATP queue. Called with the host lock held.
557 */
f281233d 558static int atp870u_queuecommand_lck(struct scsi_cmnd *req_p,
1da177e4
LT		 559 void (*done) (struct scsi_cmnd *))
560{
561 unsigned char c;
3b836464 562 unsigned int m;
1da177e4
LT		 563 struct atp_unit *dev;
564 struct Scsi_Host *host;
565
422c0d61 566 c = scmd_channel(req_p);
1da177e4 567 req_p->sense_buffer[0]=0;
fe7ed98f 568 scsi_set_resid(req_p, 0);
422c0d61 569 if (scmd_channel(req_p) > 1) {
1da177e4
LT		 570 req_p->result = 0x00040000;
571 done(req_p);
572#ifdef ED_DBGP
573 printk("atp870u_queuecommand : req_p->device->channel > 1\n");
574#endif
575 return 0;
576 }
577
578 host = req_p->device->host;
579 dev = (struct atp_unit *)&host->hostdata;
580
581
582
583 m = 1;
422c0d61 584 m = m << scmd_id(req_p);
1da177e4
LT		 585
586 /*
587 * Fake a timeout for missing targets
588 */
589
590 if ((m & dev->active_id[c]) == 0) {
591 req_p->result = 0x00040000;
592 done(req_p);
593 return 0;
594 }
595
596 if (done) {
597 req_p->scsi_done = done;
598 } else {
599#ifdef ED_DBGP
600 printk( "atp870u_queuecommand: done can't be NULL\n");
601#endif
602 req_p->result = 0;
603 done(req_p);
604 return 0;
605 }
606
607 /*
608 * Count new command
609 */
610 dev->quend[c]++;
611 if (dev->quend[c] >= qcnt) {
612 dev->quend[c] = 0;
613 }
614
615 /*
616 * Check queue state
617 */
618 if (dev->quhd[c] == dev->quend[c]) {
619 if (dev->quend[c] == 0) {
620 dev->quend[c] = qcnt;
621 }
622#ifdef ED_DBGP
623 printk("atp870u_queuecommand : dev->quhd[c] == dev->quend[c]\n");
624#endif
625 dev->quend[c]--;
626 req_p->result = 0x00020000;
627 done(req_p);
628 return 0;
629 }
630 dev->quereq[c][dev->quend[c]] = req_p;
1da177e4 631#ifdef ED_DBGP
6a3cebb6 632 printk("dev->ioport[c] = %x atp_readb_io(dev, c, 0x1c) = %x dev->in_int[%d] = %d dev->in_snd[%d] = %d\n",dev->ioport[c],atp_readb_io(dev, c, 0x1c),c,dev->in_int[c],c,dev->in_snd[c]);
1da177e4 633#endif
6a3cebb6 634 if ((atp_readb_io(dev, c, 0x1c) == 0) && (dev->in_int[c] == 0) && (dev->in_snd[c] == 0)) {
1da177e4
LT		 635#ifdef ED_DBGP
636 printk("Call sent_s870(atp870u_queuecommand)\n");
637#endif
638 send_s870(dev,c);
639 }
640#ifdef ED_DBGP
641 printk("atp870u_queuecommand : exit\n");
642#endif
643 return 0;
644}
645
f281233d
JG		 646static DEF_SCSI_QCMD(atp870u_queuecommand)
647
1da177e4
LT		 648/**
649 * send_s870 - send a command to the controller
650 * @host: host
651 *
652 * On entry there is work queued to be done. We move some of that work to the
653 * controller itself.
654 *
655 * Caller holds the host lock.
656 */
657static void send_s870(struct atp_unit *dev,unsigned char c)
658{
468b8968 659 struct scsi_cmnd *workreq = NULL;
1da177e4
LT		 660 unsigned int i;//,k;
661 unsigned char j, target_id;
662 unsigned char *prd;
c2bab403 663 unsigned short int w;
1da177e4 664 unsigned long l, bttl = 0;
1da177e4
LT		 665 unsigned long sg_count;
666
667 if (dev->in_snd[c] != 0) {
668#ifdef ED_DBGP
669 printk("cmnd in_snd\n");
670#endif
671 return;
672 }
673#ifdef ED_DBGP
674 printk("Sent_s870 enter\n");
675#endif
676 dev->in_snd[c] = 1;
677 if ((dev->last_cmd[c] != 0xff) && ((dev->last_cmd[c] & 0x40) != 0)) {
678 dev->last_cmd[c] &= 0x0f;
679 workreq = dev->id[c][dev->last_cmd[c]].curr_req;
468b8968
OZ		 680 if (!workreq) {
681 dev->last_cmd[c] = 0xff;
682 if (dev->quhd[c] == dev->quend[c]) {
683 dev->in_snd[c] = 0;
684 return;
685 }
1da177e4
LT		 686 }
687 }
468b8968
OZ		 688 if (!workreq) {
689 if ((dev->last_cmd[c] != 0xff) && (dev->working[c] != 0)) {
690 dev->in_snd[c] = 0;
691 return;
692 }
693 dev->working[c]++;
694 j = dev->quhd[c];
695 dev->quhd[c]++;
696 if (dev->quhd[c] >= qcnt)
697 dev->quhd[c] = 0;
698 workreq = dev->quereq[c][dev->quhd[c]];
699 if (dev->id[c][scmd_id(workreq)].curr_req != NULL) {
700 dev->quhd[c] = j;
701 dev->working[c]--;
702 dev->in_snd[c] = 0;
703 return;
704 }
422c0d61
JG		 705 dev->id[c][scmd_id(workreq)].curr_req = workreq;
706 dev->last_cmd[c] = scmd_id(workreq);
1da177e4 707 }
6a3cebb6 708 if ((atp_readb_io(dev, c, 0x1f) & 0xb0) != 0 || atp_readb_io(dev, c, 0x1c) != 0) {
1da177e4 709#ifdef ED_DBGP
468b8968 710 printk("Abort to Send\n");
1da177e4 711#endif
468b8968
OZ		 712 dev->last_cmd[c] |= 0x40;
713 dev->in_snd[c] = 0;
714 return;
715 }
1da177e4
LT		 716#ifdef ED_DBGP
717 printk("OK to Send\n");
422c0d61 718 scmd_printk(KERN_DEBUG, workreq, "CDB");
1da177e4
LT		 719 for(i=0;i<workreq->cmd_len;i++) {
720 printk(" %x",workreq->cmnd[i]);
721 }
422c0d61 722 printk("\n");
1da177e4 723#endif
fe7ed98f
BH		 724 l = scsi_bufflen(workreq);
725
1da177e4 726 if (dev->dev_id == ATP885_DEVID) {
6a3cebb6
OZ		 727 j = atp_readb_base(dev, 0x29) & 0xfe;
728 atp_writeb_base(dev, 0x29, j);
422c0d61 729 dev->r1f[c][scmd_id(workreq)] = 0;
1da177e4
LT		 730 }
731
732 if (workreq->cmnd[0] == READ_CAPACITY) {
fe7ed98f
BH		 733 if (l > 8)
734 l = 8;
1da177e4
LT		 735 }
736 if (workreq->cmnd[0] == 0x00) {
fe7ed98f 737 l = 0;
1da177e4
LT		 738 }
739
1da177e4 740 j = 0;
422c0d61 741 target_id = scmd_id(workreq);
1da177e4
LT		 742
743 /*
744 * Wide ?
745 */
746 w = 1;
747 w = w << target_id;
748 if ((w & dev->wide_id[c]) != 0) {
749 j |= 0x01;
750 }
6a3cebb6
OZ		 751 atp_writeb_io(dev, c, 0x1b, j);
752 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != j) {
753 atp_writeb_pci(dev, c, 0x1b, j);
1da177e4
LT		 754#ifdef ED_DBGP
755 printk("send_s870 while loop 1\n");
756#endif
757 }
758 /*
759 * Write the command
760 */
761
6a3cebb6
OZ		 762 atp_writeb_io(dev, c, 0x00, workreq->cmd_len);
763 atp_writeb_io(dev, c, 0x01, 0x2c);
764 if (dev->dev_id == ATP885_DEVID)
765 atp_writeb_io(dev, c, 0x02, 0x7f);
766 else
767 atp_writeb_io(dev, c, 0x02, 0xcf);
768 for (i = 0; i < workreq->cmd_len; i++)
769 atp_writeb_io(dev, c, 0x03 + i, workreq->cmnd[i]);
770 atp_writeb_io(dev, c, 0x0f, workreq->device->lun);
1da177e4
LT		 771 /*
772 * Write the target
773 */
6a3cebb6 774 atp_writeb_io(dev, c, 0x11, dev->id[c][target_id].devsp);
1da177e4
LT		 775#ifdef ED_DBGP
776 printk("dev->id[%d][%d].devsp = %2x\n",c,target_id,dev->id[c][target_id].devsp);
777#endif
fe7ed98f
BH		 778
779 sg_count = scsi_dma_map(workreq);
1da177e4
LT		 780 /*
781 * Write transfer size
782 */
6a3cebb6
OZ		 783 atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&l))[2]);
784 atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&l))[1]);
785 atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&l))[0]);
1da177e4
LT		 786 j = target_id;
787 dev->id[c][j].last_len = l;
788 dev->id[c][j].tran_len = 0;
789#ifdef ED_DBGP
790 printk("dev->id[%2d][%2d].last_len = %d\n",c,j,dev->id[c][j].last_len);
791#endif
792 /*
793 * Flip the wide bits
794 */
795 if ((j & 0x08) != 0) {
796 j = (j & 0x07) | 0x40;
797 }
798 /*
799 * Check transfer direction
800 */
6a3cebb6
OZ		 801 if (workreq->sc_data_direction == DMA_TO_DEVICE)
802 atp_writeb_io(dev, c, 0x15, j | 0x20);
803 else
804 atp_writeb_io(dev, c, 0x15, j);
805 atp_writeb_io(dev, c, 0x16, atp_readb_io(dev, c, 0x16) | 0x80);
806 atp_writeb_io(dev, c, 0x16, 0x80);
1da177e4
LT		 807 dev->id[c][target_id].dirct = 0;
808 if (l == 0) {
6a3cebb6 809 if (atp_readb_io(dev, c, 0x1c) == 0) {
1da177e4
LT		 810#ifdef ED_DBGP
811 printk("change SCSI_CMD_REG 0x08\n");
812#endif
6a3cebb6
OZ		 813 atp_writeb_io(dev, c, 0x18, 0x08);
814 } else
1da177e4 815 dev->last_cmd[c] |= 0x40;
1da177e4
LT		 816 dev->in_snd[c] = 0;
817 return;
818 }
1da177e4
LT		 819 prd = dev->id[c][target_id].prd_table;
820 dev->id[c][target_id].prd_pos = prd;
821
822 /*
823 * Now write the request list. Either as scatter/gather or as
824 * a linear chain.
825 */
826
fe7ed98f
BH		 827 if (l) {
828 struct scatterlist *sgpnt;
1da177e4 829 i = 0;
fe7ed98f
BH		 830 scsi_for_each_sg(workreq, sgpnt, sg_count, j) {
831 bttl = sg_dma_address(sgpnt);
832 l=sg_dma_len(sgpnt);
1da177e4 833#ifdef ED_DBGP
fe7ed98f 834 printk("1. bttl %x, l %x\n",bttl, l);
1da177e4 835#endif
fe7ed98f 836 while (l > 0x10000) {
1da177e4
LT		 837 (((u16 *) (prd))[i + 3]) = 0x0000;
838 (((u16 *) (prd))[i + 2]) = 0x0000;
839 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
840 l -= 0x10000;
841 bttl += 0x10000;
842 i += 0x04;
843 }
844 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl);
845 (((u16 *) (prd))[i + 2]) = cpu_to_le16(l);
846 (((u16 *) (prd))[i + 3]) = 0;
847 i += 0x04;
848 }
849 (((u16 *) (prd))[i - 1]) = cpu_to_le16(0x8000);
850#ifdef ED_DBGP
851 printk("prd %4x %4x %4x %4x\n",(((unsigned short int *)prd)[0]),(((unsigned short int *)prd)[1]),(((unsigned short int *)prd)[2]),(((unsigned short int *)prd)[3]));
852 printk("2. bttl %x, l %x\n",bttl, l);
853#endif
1da177e4 854 }
1da177e4 855#ifdef ED_DBGP
c2bab403 856 printk("send_s870: prdaddr_2 0x%8x target_id %d\n", dev->id[c][target_id].prdaddr,target_id);
1da177e4 857#endif
b5683557 858 dev->id[c][target_id].prdaddr = dev->id[c][target_id].prd_bus;
6a3cebb6
OZ		 859 atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr);
860 atp_writeb_pci(dev, c, 2, 0x06);
861 atp_writeb_pci(dev, c, 2, 0x00);
1da177e4 862 if (dev->dev_id == ATP885_DEVID) {
6a3cebb6 863 j = atp_readb_pci(dev, c, 1) & 0xf3;
1da177e4
LT		 864 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) ||
865 (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) {
866 j |= 0x0c;
867 }
6a3cebb6 868 atp_writeb_pci(dev, c, 1, j);
1da177e4
LT		 869 } else if ((dev->dev_id == ATP880_DEVID1) ||
870 (dev->dev_id == ATP880_DEVID2)) {
6a3cebb6
OZ		 871 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a))
872 atp_writeb_base(dev, 0x3b, (atp_readb_base(dev, 0x3b) & 0x3f) | 0xc0);
873 else
874 atp_writeb_base(dev, 0x3b, atp_readb_base(dev, 0x3b) & 0x3f);
1da177e4 875 } else {
6a3cebb6
OZ		 876 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a))
877 atp_writeb_io(dev, c, 0x3a, (atp_readb_io(dev, c, 0x3a) & 0xf3) | 0x08);
878 else
879 atp_writeb_io(dev, c, 0x3a, atp_readb_io(dev, c, 0x3a) & 0xf3);
1da177e4 880 }
1da177e4
LT		 881
882 if(workreq->sc_data_direction == DMA_TO_DEVICE) {
883 dev->id[c][target_id].dirct = 0x20;
6a3cebb6
OZ		 884 if (atp_readb_io(dev, c, 0x1c) == 0) {
885 atp_writeb_io(dev, c, 0x18, 0x08);
886 atp_writeb_pci(dev, c, 0, 0x01);
1da177e4
LT		 887#ifdef ED_DBGP
888 printk( "start DMA(to target)\n");
889#endif
890 } else {
891 dev->last_cmd[c] |= 0x40;
892 }
893 dev->in_snd[c] = 0;
894 return;
895 }
6a3cebb6
OZ		 896 if (atp_readb_io(dev, c, 0x1c) == 0) {
897 atp_writeb_io(dev, c, 0x18, 0x08);
898 atp_writeb_pci(dev, c, 0, 0x09);
1da177e4
LT		 899#ifdef ED_DBGP
900 printk( "start DMA(to host)\n");
901#endif
902 } else {
903 dev->last_cmd[c] |= 0x40;
904 }
905 dev->in_snd[c] = 0;
906 return;
907
908}
909
910static unsigned char fun_scam(struct atp_unit *dev, unsigned short int *val)
911{
1da177e4
LT		 912 unsigned short int i, k;
913 unsigned char j;
914
6a3cebb6 915 atp_writew_io(dev, 0, 0x1c, *val);
1da177e4 916 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
6a3cebb6 917 k = atp_readw_io(dev, 0, 0x1c);
1da177e4 918 j = (unsigned char) (k >> 8);
832e9ac6
OZ		 919 if ((k & 0x8000) != 0) /* DB7 all release? */
920 i = 0;
1da177e4
LT		 921 }
922 *val |= 0x4000; /* assert DB6 */
6a3cebb6 923 atp_writew_io(dev, 0, 0x1c, *val);
1da177e4 924 *val &= 0xdfff; /* assert DB5 */
6a3cebb6 925 atp_writew_io(dev, 0, 0x1c, *val);
1da177e4 926 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
6a3cebb6 927 if ((atp_readw_io(dev, 0, 0x1c) & 0x2000) != 0) /* DB5 all release? */
832e9ac6 928 i = 0;
1da177e4
LT		 929 }
930 *val |= 0x8000; /* no DB4-0, assert DB7 */
931 *val &= 0xe0ff;
6a3cebb6 932 atp_writew_io(dev, 0, 0x1c, *val);
1da177e4 933 *val &= 0xbfff; /* release DB6 */
6a3cebb6 934 atp_writew_io(dev, 0, 0x1c, *val);
1da177e4 935 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */
6a3cebb6 936 if ((atp_readw_io(dev, 0, 0x1c) & 0x4000) != 0) /* DB6 all release? */
832e9ac6 937 i = 0;
1da177e4
LT		 938 }
939
940 return j;
941}
942
943static void tscam(struct Scsi_Host *host)
944{
945
1da177e4
LT		 946 unsigned char i, j, k;
947 unsigned long n;
948 unsigned short int m, assignid_map, val;
949 unsigned char mbuf[33], quintet[2];
950 struct atp_unit *dev = (struct atp_unit *)&host->hostdata;
951 static unsigned char g2q_tab[8] = {
952 0x38, 0x31, 0x32, 0x2b, 0x34, 0x2d, 0x2e, 0x27
953 };
954
955/* I can't believe we need this before we've even done anything. Remove it
956 * and see if anyone bitches.
957 for (i = 0; i < 0x10; i++) {
958 udelay(0xffff);
959 }
960 */
961
6a3cebb6
OZ		 962 atp_writeb_io(dev, 0, 1, 0x08);
963 atp_writeb_io(dev, 0, 2, 0x7f);
964 atp_writeb_io(dev, 0, 0x11, 0x20);
1da177e4
LT		 965
966 if ((dev->scam_on & 0x40) == 0) {
967 return;
968 }
969 m = 1;
970 m <<= dev->host_id[0];
971 j = 16;
972 if (dev->chip_ver < 4) {
973 m |= 0xff00;
974 j = 8;
975 }
976 assignid_map = m;
6a3cebb6
OZ		 977 atp_writeb_io(dev, 0, 0x02, 0x02); /* 2*2=4ms,3EH 2/32*3E=3.9ms */
978 atp_writeb_io(dev, 0, 0x03, 0);
979 atp_writeb_io(dev, 0, 0x04, 0);
980 atp_writeb_io(dev, 0, 0x05, 0);
981 atp_writeb_io(dev, 0, 0x06, 0);
982 atp_writeb_io(dev, 0, 0x07, 0);
983 atp_writeb_io(dev, 0, 0x08, 0);
1da177e4
LT		 984
985 for (i = 0; i < j; i++) {
986 m = 1;
987 m = m << i;
988 if ((m & assignid_map) != 0) {
989 continue;
990 }
6a3cebb6
OZ		 991 atp_writeb_io(dev, 0, 0x0f, 0);
992 atp_writeb_io(dev, 0, 0x12, 0);
993 atp_writeb_io(dev, 0, 0x13, 0);
994 atp_writeb_io(dev, 0, 0x14, 0);
1da177e4
LT		 995 if (i > 7) {
996 k = (i & 0x07) | 0x40;
997 } else {
998 k = i;
999 }
6a3cebb6
OZ		 1000 atp_writeb_io(dev, 0, 0x15, k);
1001 if (dev->chip_ver == 4)
1002 atp_writeb_io(dev, 0, 0x1b, 0x01);
1003 else
1004 atp_writeb_io(dev, 0, 0x1b, 0x00);
58c4d046 1005 do {
6a3cebb6 1006 atp_writeb_io(dev, 0, 0x18, 0x09);
1da177e4 1007
6a3cebb6 1008 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
58c4d046 1009 cpu_relax();
6a3cebb6 1010 k = atp_readb_io(dev, 0, 0x17);
58c4d046
OZ		 1011 if ((k == 0x85) || (k == 0x42))
1012 break;
1013 if (k != 0x16)
6a3cebb6 1014 atp_writeb_io(dev, 0, 0x10, 0x41);
58c4d046
OZ		 1015 } while (k != 0x16);
1016 if ((k == 0x85) || (k == 0x42))
1017 continue;
1da177e4
LT		 1018 assignid_map |= m;
1019
1020 }
6a3cebb6
OZ		 1021 atp_writeb_io(dev, 0, 0x02, 0x7f);
1022 atp_writeb_io(dev, 0, 0x1b, 0x02);
1da177e4
LT		 1023
1024 outb(0, 0x80);
1025
1026 val = 0x0080; /* bsy */
6a3cebb6 1027 atp_writew_io(dev, 0, 0x1c, val);
1da177e4 1028 val |= 0x0040; /* sel */
6a3cebb6 1029 atp_writew_io(dev, 0, 0x1c, val);
1da177e4 1030 val |= 0x0004; /* msg */
6a3cebb6 1031 atp_writew_io(dev, 0, 0x1c, val);
1da177e4
LT		 1032 inb(0x80); /* 2 deskew delay(45ns*2=90ns) */
1033 val &= 0x007f; /* no bsy */
6a3cebb6 1034 atp_writew_io(dev, 0, 0x1c, val);
1da177e4
LT		 1035 mdelay(128);
1036 val &= 0x00fb; /* after 1ms no msg */
6a3cebb6
OZ		 1037 atp_writew_io(dev, 0, 0x1c, val);
1038 while ((atp_readb_io(dev, 0, 0x1c) & 0x04) != 0)
58c4d046 1039 ;
1da177e4
LT		 1040 outb(1, 0x80);
1041 udelay(100);
c7fcc089 1042 for (n = 0; n < 0x30000; n++)
6a3cebb6 1043 if ((atp_readb_io(dev, 0, 0x1c) & 0x80) != 0) /* bsy ? */
c7fcc089
OZ		 1044 break;
1045 if (n < 0x30000)
1046 for (n = 0; n < 0x30000; n++)
6a3cebb6 1047 if ((atp_readb_io(dev, 0, 0x1c) & 0x81) == 0x0081) {
c7fcc089
OZ		 1048 inb(0x80);
1049 val |= 0x8003; /* io,cd,db7 */
6a3cebb6 1050 atp_writew_io(dev, 0, 0x1c, val);
c7fcc089
OZ		 1051 inb(0x80);
1052 val &= 0x00bf; /* no sel */
6a3cebb6 1053 atp_writew_io(dev, 0, 0x1c, val);
c7fcc089
OZ		 1054 outb(2, 0x80);
1055 break;
1056 }
1057 while (1) {
0f6d93aa
MM		 1058 /*
1059 * The funny division into multiple delays is to accomodate
1060 * arches like ARM where udelay() multiplies its argument by
1061 * a large number to initialize a loop counter. To avoid
1062 * overflow, the maximum supported udelay is 2000 microseconds.
1063 *
1064 * XXX it would be more polite to find a way to use msleep()
1065 */
1066 mdelay(2);
1067 udelay(48);
6a3cebb6
OZ		 1068 if ((atp_readb_io(dev, 0, 0x1c) & 0x80) == 0x00) { /* bsy ? */
1069 atp_writew_io(dev, 0, 0x1c, 0);
1070 atp_writeb_io(dev, 0, 0x1b, 0);
1071 atp_writeb_io(dev, 0, 0x15, 0);
1072 atp_writeb_io(dev, 0, 0x18, 0x09);
1073 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0)
1da177e4 1074 cpu_relax();
6a3cebb6 1075 atp_readb_io(dev, 0, 0x17);
1da177e4
LT		 1076 return;
1077 }
1078 val &= 0x00ff; /* synchronization */
1079 val |= 0x3f00;
1080 fun_scam(dev, &val);
1081 outb(3, 0x80);
1082 val &= 0x00ff; /* isolation */
1083 val |= 0x2000;
1084 fun_scam(dev, &val);
1085 outb(4, 0x80);
1086 i = 8;
1087 j = 0;
c7fcc089
OZ		 1088
1089 while (1) {
6a3cebb6 1090 if ((atp_readw_io(dev, 0, 0x1c) & 0x2000) == 0)
c7fcc089
OZ		 1091 continue;
1092 outb(5, 0x80);
1093 val &= 0x00ff; /* get ID_STRING */
1094 val |= 0x2000;
1095 k = fun_scam(dev, &val);
1096 if ((k & 0x03) == 0)
1097 break;
1098 mbuf[j] <<= 0x01;
1099 mbuf[j] &= 0xfe;
1100 if ((k & 0x02) != 0)
1101 mbuf[j] |= 0x01;
1102 i--;
1103 if (i > 0)
1104 continue;
1105 j++;
1106 i = 8;
1da177e4 1107 }
1da177e4 1108
c7fcc089 1109 /* isolation complete.. */
1da177e4
LT		 1110/* mbuf[32]=0;
1111 printk(" \n%x %x %x %s\n ",assignid_map,mbuf[0],mbuf[1],&mbuf[2]); */
1112 i = 15;
1113 j = mbuf[0];
25985edc 1114 if ((j & 0x20) != 0) { /* bit5=1:ID up to 7 */
1da177e4
LT		 1115 i = 7;
1116 }
c7fcc089
OZ		 1117 if ((j & 0x06) != 0) { /* IDvalid? */
1118 k = mbuf[1];
1119 while (1) {
1120 m = 1;
1121 m <<= k;
1122 if ((m & assignid_map) == 0)
1123 break;
1124 if (k > 0)
1125 k--;
1126 else
1127 break;
1128 }
1da177e4 1129 }
c7fcc089
OZ		 1130 if ((m & assignid_map) != 0) { /* srch from max acceptable ID# */
1131 k = i; /* max acceptable ID# */
1132 while (1) {
1133 m = 1;
1134 m <<= k;
1135 if ((m & assignid_map) == 0)
1136 break;
1137 if (k > 0)
1138 k--;
1139 else
1140 break;
1141 }
1da177e4 1142 }
c7fcc089 1143 /* k=binID#, */
1da177e4
LT		 1144 assignid_map |= m;
1145 if (k < 8) {
1146 quintet[0] = 0x38; /* 1st dft ID<8 */
1147 } else {
1148 quintet[0] = 0x31; /* 1st ID>=8 */
1149 }
1150 k &= 0x07;
1151 quintet[1] = g2q_tab[k];
1152
1153 val &= 0x00ff; /* AssignID 1stQuintet,AH=001xxxxx */
1154 m = quintet[0] << 8;
1155 val |= m;
1156 fun_scam(dev, &val);
1157 val &= 0x00ff; /* AssignID 2ndQuintet,AH=001xxxxx */
1158 m = quintet[1] << 8;
1159 val |= m;
1160 fun_scam(dev, &val);
1161
c7fcc089 1162 }
1da177e4
LT		 1163}
1164
152c3ac5 1165static void is870(struct atp_unit *dev)
1da177e4 1166{
1da177e4
LT		 1167 unsigned char i, j, k, rmb, n;
1168 unsigned short int m;
1169 static unsigned char mbuf[512];
1170 static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 };
1171 static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 };
1172 static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1173 static unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0c, 0x0e };
1174 static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x0c, 0x07 };
1175 static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 };
1176
152c3ac5 1177 atp_writeb_io(dev, 0, 0x3a, atp_readb_io(dev, 0, 0x3a) | 0x10);
1da177e4
LT		 1178
1179 for (i = 0; i < 16; i++) {
1180 if ((dev->chip_ver != 4) && (i > 7)) {
1181 break;
1182 }
1183 m = 1;
1184 m = m << i;
1185 if ((m & dev->active_id[0]) != 0) {
1186 continue;
1187 }
1188 if (i == dev->host_id[0]) {
1189 printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[0]);
1190 continue;
1191 }
1da177e4 1192 if (dev->chip_ver == 4) {
152c3ac5 1193 atp_writeb_io(dev, 0, 0x1b, 0x01);
1da177e4 1194 } else {
152c3ac5
OZ		 1195 atp_writeb_io(dev, 0, 0x1b, 0x00);
1196 }
1197 atp_writeb_io(dev, 0, 1, 0x08);
1198 atp_writeb_io(dev, 0, 2, 0x7f);
1199 atp_writeb_io(dev, 0, 3, satn[0]);
1200 atp_writeb_io(dev, 0, 4, satn[1]);
1201 atp_writeb_io(dev, 0, 5, satn[2]);
1202 atp_writeb_io(dev, 0, 6, satn[3]);
1203 atp_writeb_io(dev, 0, 7, satn[4]);
1204 atp_writeb_io(dev, 0, 8, satn[5]);
1205 atp_writeb_io(dev, 0, 0x0f, 0);
1206 atp_writeb_io(dev, 0, 0x11, dev->id[0][i].devsp);
1207 atp_writeb_io(dev, 0, 0x12, 0);
1208 atp_writeb_io(dev, 0, 0x13, satn[6]);
1209 atp_writeb_io(dev, 0, 0x14, satn[7]);
1da177e4
LT		 1210 j = i;
1211 if ((j & 0x08) != 0) {
1212 j = (j & 0x07) | 0x40;
1213 }
152c3ac5
OZ		 1214 atp_writeb_io(dev, 0, 0x15, j);
1215 atp_writeb_io(dev, 0, 0x18, satn[8]);
1da177e4 1216
152c3ac5 1217 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1218 cpu_relax();
1219
152c3ac5 1220 if (atp_readb_io(dev, 0, 0x17) != 0x11 && atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1221 continue;
1222
152c3ac5 1223 while (atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1224 cpu_relax();
1225
1226 dev->active_id[0] |= m;
1227
152c3ac5
OZ		 1228 atp_writeb_io(dev, 0, 0x10, 0x30);
1229 atp_writeb_io(dev, 0, 0x04, 0x00);
1da177e4
LT		 1230
1231phase_cmd:
152c3ac5
OZ		 1232 atp_writeb_io(dev, 0, 0x18, 0x08);
1233 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4 1234 cpu_relax();
152c3ac5 1235 j = atp_readb_io(dev, 0, 0x17);
1da177e4 1236 if (j != 0x16) {
152c3ac5 1237 atp_writeb_io(dev, 0, 0x10, 0x41);
1da177e4
LT		 1238 goto phase_cmd;
1239 }
1240sel_ok:
152c3ac5
OZ		 1241 atp_writeb_io(dev, 0, 3, inqd[0]);
1242 atp_writeb_io(dev, 0, 4, inqd[1]);
1243 atp_writeb_io(dev, 0, 5, inqd[2]);
1244 atp_writeb_io(dev, 0, 6, inqd[3]);
1245 atp_writeb_io(dev, 0, 7, inqd[4]);
1246 atp_writeb_io(dev, 0, 8, inqd[5]);
1247 atp_writeb_io(dev, 0, 0x0f, 0);
1248 atp_writeb_io(dev, 0, 0x11, dev->id[0][i].devsp);
1249 atp_writeb_io(dev, 0, 0x12, 0);
1250 atp_writeb_io(dev, 0, 0x13, inqd[6]);
1251 atp_writeb_io(dev, 0, 0x14, inqd[7]);
1252 atp_writeb_io(dev, 0, 0x18, inqd[8]);
1253
1254 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1255 cpu_relax();
1256
152c3ac5 1257 if (atp_readb_io(dev, 0, 0x17) != 0x11 && atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1258 continue;
1259
152c3ac5 1260 while (atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1261 cpu_relax();
1262
1da177e4 1263 if (dev->chip_ver == 4)
152c3ac5 1264 atp_writeb_io(dev, 0, 0x1b, 0x00);
1da177e4 1265
152c3ac5 1266 atp_writeb_io(dev, 0, 0x18, 0x08);
1da177e4
LT		 1267 j = 0;
1268rd_inq_data:
152c3ac5 1269 k = atp_readb_io(dev, 0, 0x1f);
1da177e4 1270 if ((k & 0x01) != 0) {
152c3ac5 1271 mbuf[j++] = atp_readb_io(dev, 0, 0x19);
1da177e4
LT		 1272 goto rd_inq_data;
1273 }
1274 if ((k & 0x80) == 0) {
1275 goto rd_inq_data;
1276 }
152c3ac5 1277 j = atp_readb_io(dev, 0, 0x17);
1da177e4
LT		 1278 if (j == 0x16) {
1279 goto inq_ok;
1280 }
152c3ac5
OZ		 1281 atp_writeb_io(dev, 0, 0x10, 0x46);
1282 atp_writeb_io(dev, 0, 0x12, 0);
1283 atp_writeb_io(dev, 0, 0x13, 0);
1284 atp_writeb_io(dev, 0, 0x14, 0);
1285 atp_writeb_io(dev, 0, 0x18, 0x08);
ea41ed60 1286
152c3ac5 1287 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1288 cpu_relax();
1289
152c3ac5 1290 if (atp_readb_io(dev, 0, 0x17) != 0x16) {
1da177e4
LT		 1291 goto sel_ok;
1292 }
1293inq_ok:
1294 mbuf[36] = 0;
1295 printk(KERN_INFO " ID: %2d %s\n", i, &mbuf[8]);
1296 dev->id[0][i].devtype = mbuf[0];
1297 rmb = mbuf[1];
1298 n = mbuf[7];
1299 if (dev->chip_ver != 4) {
1300 goto not_wide;
1301 }
1302 if ((mbuf[7] & 0x60) == 0) {
1303 goto not_wide;
1304 }
1305 if ((dev->global_map[0] & 0x20) == 0) {
1306 goto not_wide;
1307 }
152c3ac5
OZ		 1308 atp_writeb_io(dev, 0, 0x1b, 0x01);
1309 atp_writeb_io(dev, 0, 3, satn[0]);
1310 atp_writeb_io(dev, 0, 4, satn[1]);
1311 atp_writeb_io(dev, 0, 5, satn[2]);
1312 atp_writeb_io(dev, 0, 6, satn[3]);
1313 atp_writeb_io(dev, 0, 7, satn[4]);
1314 atp_writeb_io(dev, 0, 8, satn[5]);
1315 atp_writeb_io(dev, 0, 0x0f, 0);
1316 atp_writeb_io(dev, 0, 0x11, dev->id[0][i].devsp);
1317 atp_writeb_io(dev, 0, 0x12, 0);
1318 atp_writeb_io(dev, 0, 0x13, satn[6]);
1319 atp_writeb_io(dev, 0, 0x14, satn[7]);
1320 atp_writeb_io(dev, 0, 0x18, satn[8]);
1321
1322 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1323 cpu_relax();
1324
152c3ac5 1325 if (atp_readb_io(dev, 0, 0x17) != 0x11 && atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1326 continue;
1327
152c3ac5 1328 while (atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1329 cpu_relax();
1330
1331try_wide:
1332 j = 0;
152c3ac5
OZ		 1333 atp_writeb_io(dev, 0, 0x14, 0x05);
1334 atp_writeb_io(dev, 0, 0x18, 0x20);
ea41ed60 1335
152c3ac5
OZ		 1336 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0) {
1337 if ((atp_readb_io(dev, 0, 0x1f) & 0x01) != 0)
1338 atp_writeb_io(dev, 0, 0x19, wide[j++]);
1da177e4 1339 }
1da177e4 1340
152c3ac5 1341 while ((atp_readb_io(dev, 0, 0x17) & 0x80) == 0x00)
1da177e4
LT		 1342 cpu_relax();
1343
152c3ac5 1344 j = atp_readb_io(dev, 0, 0x17) & 0x0f;
1da177e4
LT		 1345 if (j == 0x0f) {
1346 goto widep_in;
1347 }
1348 if (j == 0x0a) {
1349 goto widep_cmd;
1350 }
1351 if (j == 0x0e) {
1352 goto try_wide;
1353 }
1354 continue;
1355widep_out:
152c3ac5
OZ		 1356 atp_writeb_io(dev, 0, 0x18, 0x20);
1357 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0) {
1358 if ((atp_readb_io(dev, 0, 0x1f) & 0x01) != 0)
1359 atp_writeb_io(dev, 0, 0x19, 0);
1da177e4 1360 }
152c3ac5 1361 j = atp_readb_io(dev, 0, 0x17) & 0x0f;
1da177e4
LT		 1362 if (j == 0x0f) {
1363 goto widep_in;
1364 }
1365 if (j == 0x0a) {
1366 goto widep_cmd;
1367 }
1368 if (j == 0x0e) {
1369 goto widep_out;
1370 }
1371 continue;
1372widep_in:
152c3ac5
OZ		 1373 atp_writeb_io(dev, 0, 0x14, 0xff);
1374 atp_writeb_io(dev, 0, 0x18, 0x20);
1da177e4
LT		 1375 k = 0;
1376widep_in1:
152c3ac5 1377 j = atp_readb_io(dev, 0, 0x1f);
1da177e4 1378 if ((j & 0x01) != 0) {
152c3ac5 1379 mbuf[k++] = atp_readb_io(dev, 0, 0x19);
1da177e4
LT		 1380 goto widep_in1;
1381 }
1382 if ((j & 0x80) == 0x00) {
1383 goto widep_in1;
1384 }
152c3ac5 1385 j = atp_readb_io(dev, 0, 0x17) & 0x0f;
1da177e4
LT		 1386 if (j == 0x0f) {
1387 goto widep_in;
1388 }
1389 if (j == 0x0a) {
1390 goto widep_cmd;
1391 }
1392 if (j == 0x0e) {
1393 goto widep_out;
1394 }
1395 continue;
1396widep_cmd:
152c3ac5
OZ		 1397 atp_writeb_io(dev, 0, 0x10, 0x30);
1398 atp_writeb_io(dev, 0, 0x14, 0x00);
1399 atp_writeb_io(dev, 0, 0x18, 0x08);
1400
1401 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1402 cpu_relax();
1403
152c3ac5 1404 j = atp_readb_io(dev, 0, 0x17);
1da177e4
LT		 1405 if (j != 0x16) {
1406 if (j == 0x4e) {
1407 goto widep_out;
1408 }
1409 continue;
1410 }
1411 if (mbuf[0] != 0x01) {
1412 goto not_wide;
1413 }
1414 if (mbuf[1] != 0x02) {
1415 goto not_wide;
1416 }
1417 if (mbuf[2] != 0x03) {
1418 goto not_wide;
1419 }
1420 if (mbuf[3] != 0x01) {
1421 goto not_wide;
1422 }
1423 m = 1;
1424 m = m << i;
1425 dev->wide_id[0] |= m;
1426not_wide:
1427 if ((dev->id[0][i].devtype == 0x00) || (dev->id[0][i].devtype == 0x07) || ((dev->id[0][i].devtype == 0x05) && ((n & 0x10) != 0))) {
1428 goto set_sync;
1429 }
1430 continue;
1431set_sync:
1da177e4
LT		 1432 j = 0;
1433 if ((m & dev->wide_id[0]) != 0) {
1434 j |= 0x01;
1435 }
152c3ac5
OZ		 1436 atp_writeb_io(dev, 0, 0x1b, j);
1437 atp_writeb_io(dev, 0, 3, satn[0]);
1438 atp_writeb_io(dev, 0, 4, satn[1]);
1439 atp_writeb_io(dev, 0, 5, satn[2]);
1440 atp_writeb_io(dev, 0, 6, satn[3]);
1441 atp_writeb_io(dev, 0, 7, satn[4]);
1442 atp_writeb_io(dev, 0, 8, satn[5]);
1443 atp_writeb_io(dev, 0, 0x0f, 0);
1444 atp_writeb_io(dev, 0, 0x11, dev->id[0][i].devsp);
1445 atp_writeb_io(dev, 0, 0x12, 0);
1446 atp_writeb_io(dev, 0, 0x13, satn[6]);
1447 atp_writeb_io(dev, 0, 0x14, satn[7]);
1448 atp_writeb_io(dev, 0, 0x18, satn[8]);
1449
1450 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1451 cpu_relax();
1452
152c3ac5 1453 if (atp_readb_io(dev, 0, 0x17) != 0x11 && atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1454 continue;
1455
152c3ac5 1456 while (atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1457 cpu_relax();
1458
1459try_sync:
1460 j = 0;
152c3ac5
OZ		 1461 atp_writeb_io(dev, 0, 0x14, 0x06);
1462 atp_writeb_io(dev, 0, 0x18, 0x20);
ea41ed60 1463
152c3ac5
OZ		 1464 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0) {
1465 if ((atp_readb_io(dev, 0, 0x1f) & 0x01) != 0) {
1da177e4 1466 if ((m & dev->wide_id[0]) != 0) {
152c3ac5 1467 atp_writeb_io(dev, 0, 0x19, synw[j++]);
1da177e4
LT		 1468 } else {
1469 if ((m & dev->ultra_map[0]) != 0) {
152c3ac5 1470 atp_writeb_io(dev, 0, 0x19, synu[j++]);
1da177e4 1471 } else {
152c3ac5 1472 atp_writeb_io(dev, 0, 0x19, synn[j++]);
1da177e4
LT		 1473 }
1474 }
1da177e4
LT		 1475 }
1476 }
1da177e4 1477
152c3ac5 1478 while ((atp_readb_io(dev, 0, 0x17) & 0x80) == 0x00)
1da177e4
LT		 1479 cpu_relax();
1480
152c3ac5 1481 j = atp_readb_io(dev, 0, 0x17) & 0x0f;
1da177e4
LT		 1482 if (j == 0x0f) {
1483 goto phase_ins;
1484 }
1485 if (j == 0x0a) {
1486 goto phase_cmds;
1487 }
1488 if (j == 0x0e) {
1489 goto try_sync;
1490 }
1491 continue;
1492phase_outs:
152c3ac5
OZ		 1493 atp_writeb_io(dev, 0, 0x18, 0x20);
1494 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00) {
1495 if ((atp_readb_io(dev, 0, 0x1f) & 0x01) != 0x00)
1496 atp_writeb_io(dev, 0, 0x19, 0x00);
1da177e4 1497 }
152c3ac5 1498 j = atp_readb_io(dev, 0, 0x17);
1da177e4
LT		 1499 if (j == 0x85) {
1500 goto tar_dcons;
1501 }
1502 j &= 0x0f;
1503 if (j == 0x0f) {
1504 goto phase_ins;
1505 }
1506 if (j == 0x0a) {
1507 goto phase_cmds;
1508 }
1509 if (j == 0x0e) {
1510 goto phase_outs;
1511 }
1512 continue;
1513phase_ins:
152c3ac5
OZ		 1514 atp_writeb_io(dev, 0, 0x14, 0xff);
1515 atp_writeb_io(dev, 0, 0x18, 0x20);
1da177e4
LT		 1516 k = 0;
1517phase_ins1:
152c3ac5 1518 j = atp_readb_io(dev, 0, 0x1f);
1da177e4 1519 if ((j & 0x01) != 0x00) {
152c3ac5 1520 mbuf[k++] = atp_readb_io(dev, 0, 0x19);
1da177e4
LT		 1521 goto phase_ins1;
1522 }
1523 if ((j & 0x80) == 0x00) {
1524 goto phase_ins1;
1525 }
1da177e4 1526
152c3ac5 1527 while ((atp_readb_io(dev, 0, 0x17) & 0x80) == 0x00)
1da177e4
LT		 1528 cpu_relax();
1529
152c3ac5 1530 j = atp_readb_io(dev, 0, 0x17);
1da177e4
LT		 1531 if (j == 0x85) {
1532 goto tar_dcons;
1533 }
1534 j &= 0x0f;
1535 if (j == 0x0f) {
1536 goto phase_ins;
1537 }
1538 if (j == 0x0a) {
1539 goto phase_cmds;
1540 }
1541 if (j == 0x0e) {
1542 goto phase_outs;
1543 }
1544 continue;
1545phase_cmds:
152c3ac5 1546 atp_writeb_io(dev, 0, 0x10, 0x30);
1da177e4 1547tar_dcons:
152c3ac5
OZ		 1548 atp_writeb_io(dev, 0, 0x14, 0x00);
1549 atp_writeb_io(dev, 0, 0x18, 0x08);
1da177e4 1550
152c3ac5 1551 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1552 cpu_relax();
1553
152c3ac5 1554 j = atp_readb_io(dev, 0, 0x17);
1da177e4
LT		 1555 if (j != 0x16) {
1556 continue;
1557 }
1558 if (mbuf[0] != 0x01) {
1559 continue;
1560 }
1561 if (mbuf[1] != 0x03) {
1562 continue;
1563 }
1564 if (mbuf[4] == 0x00) {
1565 continue;
1566 }
1567 if (mbuf[3] > 0x64) {
1568 continue;
1569 }
1570 if (mbuf[4] > 0x0c) {
1571 mbuf[4] = 0x0c;
1572 }
1573 dev->id[0][i].devsp = mbuf[4];
1574 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
1575 j = 0xa0;
1576 goto set_syn_ok;
1577 }
1578 if (mbuf[3] < 0x1a) {
1579 j = 0x20;
1580 goto set_syn_ok;
1581 }
1582 if (mbuf[3] < 0x33) {
1583 j = 0x40;
1584 goto set_syn_ok;
1585 }
1586 if (mbuf[3] < 0x4c) {
1587 j = 0x50;
1588 goto set_syn_ok;
1589 }
1590 j = 0x60;
1591set_syn_ok:
1592 dev->id[0][i].devsp = (dev->id[0][i].devsp & 0x0f) | j;
1593 }
152c3ac5 1594 atp_writeb_io(dev, 0, 0x3a, atp_readb_io(dev, 0, 0x3a) & 0xef);
1da177e4
LT		 1595}
1596
48502560 1597static void is880(struct atp_unit *dev)
1da177e4 1598{
1da177e4
LT		 1599 unsigned char i, j, k, rmb, n, lvdmode;
1600 unsigned short int m;
1601 static unsigned char mbuf[512];
1602 static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 };
1603 static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 };
1604 static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1605 unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
1606 static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x19, 0x0e };
1607 unsigned char synuw[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e };
1608 static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 };
1609 static unsigned char u3[9] = { 0x80, 1, 6, 4, 0x09, 00, 0x0e, 0x01, 0x02 };
1610
48502560 1611 lvdmode = atp_readb_base(dev, 0x3f) & 0x40;
1da177e4
LT		 1612
1613 for (i = 0; i < 16; i++) {
1614 m = 1;
1615 m = m << i;
1616 if ((m & dev->active_id[0]) != 0) {
1617 continue;
1618 }
1619 if (i == dev->host_id[0]) {
1620 printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[0]);
1621 continue;
1622 }
48502560
OZ		 1623 atp_writeb_io(dev, 0, 0x1b, 0x01);
1624 atp_writeb_io(dev, 0, 1, 0x08);
1625 atp_writeb_io(dev, 0, 2, 0x7f);
1626 atp_writeb_io(dev, 0, 3, satn[0]);
1627 atp_writeb_io(dev, 0, 4, satn[1]);
1628 atp_writeb_io(dev, 0, 5, satn[2]);
1629 atp_writeb_io(dev, 0, 6, satn[3]);
1630 atp_writeb_io(dev, 0, 7, satn[4]);
1631 atp_writeb_io(dev, 0, 8, satn[5]);
1632 atp_writeb_io(dev, 0, 0x0f, 0);
1633 atp_writeb_io(dev, 0, 0x11, dev->id[0][i].devsp);
1634 atp_writeb_io(dev, 0, 0x12, 0);
1635 atp_writeb_io(dev, 0, 0x13, satn[6]);
1636 atp_writeb_io(dev, 0, 0x14, satn[7]);
1da177e4
LT		 1637 j = i;
1638 if ((j & 0x08) != 0) {
1639 j = (j & 0x07) | 0x40;
1640 }
48502560
OZ		 1641 atp_writeb_io(dev, 0, 0x15, j);
1642 atp_writeb_io(dev, 0, 0x18, satn[8]);
1da177e4 1643
48502560 1644 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1645 cpu_relax();
1646
48502560 1647 if (atp_readb_io(dev, 0, 0x17) != 0x11 && atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1648 continue;
1649
48502560 1650 while (atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1651 cpu_relax();
1652
1653 dev->active_id[0] |= m;
1654
48502560
OZ		 1655 atp_writeb_io(dev, 0, 0x10, 0x30);
1656 atp_writeb_io(dev, 0, 0x14, 0x00);
1da177e4
LT		 1657
1658phase_cmd:
48502560 1659 atp_writeb_io(dev, 0, 0x18, 0x08);
1da177e4 1660
48502560 1661 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1662 cpu_relax();
1663
48502560 1664 j = atp_readb_io(dev, 0, 0x17);
1da177e4 1665 if (j != 0x16) {
48502560 1666 atp_writeb_io(dev, 0, 0x10, 0x41);
1da177e4
LT		 1667 goto phase_cmd;
1668 }
1669sel_ok:
48502560
OZ		 1670 atp_writeb_io(dev, 0, 3, inqd[0]);
1671 atp_writeb_io(dev, 0, 4, inqd[1]);
1672 atp_writeb_io(dev, 0, 5, inqd[2]);
1673 atp_writeb_io(dev, 0, 6, inqd[3]);
1674 atp_writeb_io(dev, 0, 7, inqd[4]);
1675 atp_writeb_io(dev, 0, 8, inqd[5]);
1676 atp_writeb_io(dev, 0, 0x0f, 0);
1677 atp_writeb_io(dev, 0, 0x11, dev->id[0][i].devsp);
1678 atp_writeb_io(dev, 0, 0x12, 0);
1679 atp_writeb_io(dev, 0, 0x13, inqd[6]);
1680 atp_writeb_io(dev, 0, 0x14, inqd[7]);
1681 atp_writeb_io(dev, 0, 0x18, inqd[8]);
1da177e4 1682
48502560 1683 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1684 cpu_relax();
1685
48502560 1686 if (atp_readb_io(dev, 0, 0x17) != 0x11 && atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1687 continue;
1688
48502560 1689 while (atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1690 cpu_relax();
1691
48502560
OZ		 1692 atp_writeb_io(dev, 0, 0x1b, 0x00);
1693 atp_writeb_io(dev, 0, 0x18, 0x08);
1da177e4
LT		 1694 j = 0;
1695rd_inq_data:
48502560 1696 k = atp_readb_io(dev, 0, 0x1f);
1da177e4 1697 if ((k & 0x01) != 0) {
48502560 1698 mbuf[j++] = atp_readb_io(dev, 0, 0x19);
1da177e4
LT		 1699 goto rd_inq_data;
1700 }
1701 if ((k & 0x80) == 0) {
1702 goto rd_inq_data;
1703 }
48502560 1704 j = atp_readb_io(dev, 0, 0x17);
1da177e4
LT		 1705 if (j == 0x16) {
1706 goto inq_ok;
1707 }
48502560
OZ		 1708 atp_writeb_io(dev, 0, 0x10, 0x46);
1709 atp_writeb_io(dev, 0, 0x12, 0);
1710 atp_writeb_io(dev, 0, 0x13, 0);
1711 atp_writeb_io(dev, 0, 0x14, 0);
1712 atp_writeb_io(dev, 0, 0x18, 0x08);
1713 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1714 cpu_relax();
1715
48502560 1716 if (atp_readb_io(dev, 0, 0x17) != 0x16)
1da177e4
LT		 1717 goto sel_ok;
1718
1719inq_ok:
1720 mbuf[36] = 0;
1721 printk(KERN_INFO " ID: %2d %s\n", i, &mbuf[8]);
1722 dev->id[0][i].devtype = mbuf[0];
1723 rmb = mbuf[1];
1724 n = mbuf[7];
1725 if ((mbuf[7] & 0x60) == 0) {
1726 goto not_wide;
1727 }
1728 if ((i < 8) && ((dev->global_map[0] & 0x20) == 0)) {
1729 goto not_wide;
1730 }
1731 if (lvdmode == 0) {
1732 goto chg_wide;
1733 }
1734 if (dev->sp[0][i] != 0x04) // force u2
1735 {
1736 goto chg_wide;
1737 }
1738
48502560
OZ		 1739 atp_writeb_io(dev, 0, 0x1b, 0x01);
1740 atp_writeb_io(dev, 0, 3, satn[0]);
1741 atp_writeb_io(dev, 0, 4, satn[1]);
1742 atp_writeb_io(dev, 0, 5, satn[2]);
1743 atp_writeb_io(dev, 0, 6, satn[3]);
1744 atp_writeb_io(dev, 0, 7, satn[4]);
1745 atp_writeb_io(dev, 0, 8, satn[5]);
1746 atp_writeb_io(dev, 0, 0x0f, 0);
1747 atp_writeb_io(dev, 0, 0x11, dev->id[0][i].devsp);
1748 atp_writeb_io(dev, 0, 0x12, 0);
1749 atp_writeb_io(dev, 0, 0x13, satn[6]);
1750 atp_writeb_io(dev, 0, 0x14, satn[7]);
1751 atp_writeb_io(dev, 0, 0x18, satn[8]);
1752
1753 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1754 cpu_relax();
1755
48502560 1756 if (atp_readb_io(dev, 0, 0x17) != 0x11 && atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1757 continue;
1758
48502560 1759 while (atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1760 cpu_relax();
1761
1762try_u3:
1763 j = 0;
48502560
OZ		 1764 atp_writeb_io(dev, 0, 0x14, 0x09);
1765 atp_writeb_io(dev, 0, 0x18, 0x20);
3b30acf6 1766
48502560
OZ		 1767 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0) {
1768 if ((atp_readb_io(dev, 0, 0x1f) & 0x01) != 0)
1769 atp_writeb_io(dev, 0, 0x19, u3[j++]);
1da177e4 1770 }
1da177e4 1771
48502560 1772 while ((atp_readb_io(dev, 0, 0x17) & 0x80) == 0x00)
1da177e4
LT		 1773 cpu_relax();
1774
48502560 1775 j = atp_readb_io(dev, 0, 0x17) & 0x0f;
1da177e4
LT		 1776 if (j == 0x0f) {
1777 goto u3p_in;
1778 }
1779 if (j == 0x0a) {
1780 goto u3p_cmd;
1781 }
1782 if (j == 0x0e) {
1783 goto try_u3;
1784 }
1785 continue;
1786u3p_out:
48502560
OZ		 1787 atp_writeb_io(dev, 0, 0x18, 0x20);
1788 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0) {
1789 if ((atp_readb_io(dev, 0, 0x1f) & 0x01) != 0)
1790 atp_writeb_io(dev, 0, 0x19, 0);
1da177e4 1791 }
48502560 1792 j = atp_readb_io(dev, 0, 0x17) & 0x0f;
1da177e4
LT		 1793 if (j == 0x0f) {
1794 goto u3p_in;
1795 }
1796 if (j == 0x0a) {
1797 goto u3p_cmd;
1798 }
1799 if (j == 0x0e) {
1800 goto u3p_out;
1801 }
1802 continue;
1803u3p_in:
48502560
OZ		 1804 atp_writeb_io(dev, 0, 0x14, 0x09);
1805 atp_writeb_io(dev, 0, 0x18, 0x20);
1da177e4
LT		 1806 k = 0;
1807u3p_in1:
48502560 1808 j = atp_readb_io(dev, 0, 0x1f);
1da177e4 1809 if ((j & 0x01) != 0) {
48502560 1810 mbuf[k++] = atp_readb_io(dev, 0, 0x19);
1da177e4
LT		 1811 goto u3p_in1;
1812 }
1813 if ((j & 0x80) == 0x00) {
1814 goto u3p_in1;
1815 }
48502560 1816 j = atp_readb_io(dev, 0, 0x17) & 0x0f;
1da177e4
LT		 1817 if (j == 0x0f) {
1818 goto u3p_in;
1819 }
1820 if (j == 0x0a) {
1821 goto u3p_cmd;
1822 }
1823 if (j == 0x0e) {
1824 goto u3p_out;
1825 }
1826 continue;
1827u3p_cmd:
48502560
OZ		 1828 atp_writeb_io(dev, 0, 0x10, 0x30);
1829 atp_writeb_io(dev, 0, 0x14, 0x00);
1830 atp_writeb_io(dev, 0, 0x18, 0x08);
1da177e4 1831
48502560 1832 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1833 cpu_relax();
1834
48502560 1835 j = atp_readb_io(dev, 0, 0x17);
1da177e4
LT		 1836 if (j != 0x16) {
1837 if (j == 0x4e) {
1838 goto u3p_out;
1839 }
1840 continue;
1841 }
1842 if (mbuf[0] != 0x01) {
1843 goto chg_wide;
1844 }
1845 if (mbuf[1] != 0x06) {
1846 goto chg_wide;
1847 }
1848 if (mbuf[2] != 0x04) {
1849 goto chg_wide;
1850 }
1851 if (mbuf[3] == 0x09) {
1852 m = 1;
1853 m = m << i;
1854 dev->wide_id[0] |= m;
1855 dev->id[0][i].devsp = 0xce;
1856 continue;
1857 }
1858chg_wide:
48502560
OZ		 1859 atp_writeb_io(dev, 0, 0x1b, 0x01);
1860 atp_writeb_io(dev, 0, 3, satn[0]);
1861 atp_writeb_io(dev, 0, 4, satn[1]);
1862 atp_writeb_io(dev, 0, 5, satn[2]);
1863 atp_writeb_io(dev, 0, 6, satn[3]);
1864 atp_writeb_io(dev, 0, 7, satn[4]);
1865 atp_writeb_io(dev, 0, 8, satn[5]);
1866 atp_writeb_io(dev, 0, 0x0f, 0);
1867 atp_writeb_io(dev, 0, 0x11, dev->id[0][i].devsp);
1868 atp_writeb_io(dev, 0, 0x12, 0);
1869 atp_writeb_io(dev, 0, 0x13, satn[6]);
1870 atp_writeb_io(dev, 0, 0x14, satn[7]);
1871 atp_writeb_io(dev, 0, 0x18, satn[8]);
1872
1873 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1874 cpu_relax();
1875
48502560 1876 if (atp_readb_io(dev, 0, 0x17) != 0x11 && atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1877 continue;
1878
48502560 1879 while (atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 1880 cpu_relax();
1881
1882try_wide:
1883 j = 0;
48502560
OZ		 1884 atp_writeb_io(dev, 0, 0x14, 0x05);
1885 atp_writeb_io(dev, 0, 0x18, 0x20);
3b30acf6 1886
48502560
OZ		 1887 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0) {
1888 if ((atp_readb_io(dev, 0, 0x1f) & 0x01) != 0)
1889 atp_writeb_io(dev, 0, 0x19, wide[j++]);
1da177e4 1890 }
48502560 1891 while ((atp_readb_io(dev, 0, 0x17) & 0x80) == 0x00)
1da177e4
LT		 1892 cpu_relax();
1893
48502560 1894 j = atp_readb_io(dev, 0, 0x17) & 0x0f;
1da177e4
LT		 1895 if (j == 0x0f) {
1896 goto widep_in;
1897 }
1898 if (j == 0x0a) {
1899 goto widep_cmd;
1900 }
1901 if (j == 0x0e) {
1902 goto try_wide;
1903 }
1904 continue;
1905widep_out:
48502560
OZ		 1906 atp_writeb_io(dev, 0, 0x18, 0x20);
1907 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0) {
1908 if ((atp_readb_io(dev, 0, 0x1f) & 0x01) != 0)
1909 atp_writeb_io(dev, 0, 0x19, 0);
1da177e4 1910 }
48502560 1911 j = atp_readb_io(dev, 0, 0x17) & 0x0f;
1da177e4
LT		 1912 if (j == 0x0f) {
1913 goto widep_in;
1914 }
1915 if (j == 0x0a) {
1916 goto widep_cmd;
1917 }
1918 if (j == 0x0e) {
1919 goto widep_out;
1920 }
1921 continue;
1922widep_in:
48502560
OZ		 1923 atp_writeb_io(dev, 0, 0x14, 0xff);
1924 atp_writeb_io(dev, 0, 0x18, 0x20);
1da177e4
LT		 1925 k = 0;
1926widep_in1:
48502560 1927 j = atp_readb_io(dev, 0, 0x1f);
1da177e4 1928 if ((j & 0x01) != 0) {
48502560 1929 mbuf[k++] = atp_readb_io(dev, 0, 0x19);
1da177e4
LT		 1930 goto widep_in1;
1931 }
1932 if ((j & 0x80) == 0x00) {
1933 goto widep_in1;
1934 }
48502560 1935 j = atp_readb_io(dev, 0, 0x17) & 0x0f;
1da177e4
LT		 1936 if (j == 0x0f) {
1937 goto widep_in;
1938 }
1939 if (j == 0x0a) {
1940 goto widep_cmd;
1941 }
1942 if (j == 0x0e) {
1943 goto widep_out;
1944 }
1945 continue;
1946widep_cmd:
48502560
OZ		 1947 atp_writeb_io(dev, 0, 0x10, 0x30);
1948 atp_writeb_io(dev, 0, 0x14, 0x00);
1949 atp_writeb_io(dev, 0, 0x18, 0x08);
3b30acf6 1950
48502560 1951 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 1952 cpu_relax();
1953
48502560 1954 j = atp_readb_io(dev, 0, 0x17);
1da177e4
LT		 1955 if (j != 0x16) {
1956 if (j == 0x4e) {
1957 goto widep_out;
1958 }
1959 continue;
1960 }
1961 if (mbuf[0] != 0x01) {
1962 goto not_wide;
1963 }
1964 if (mbuf[1] != 0x02) {
1965 goto not_wide;
1966 }
1967 if (mbuf[2] != 0x03) {
1968 goto not_wide;
1969 }
1970 if (mbuf[3] != 0x01) {
1971 goto not_wide;
1972 }
1973 m = 1;
1974 m = m << i;
1975 dev->wide_id[0] |= m;
1976not_wide:
1977 if ((dev->id[0][i].devtype == 0x00) || (dev->id[0][i].devtype == 0x07) || ((dev->id[0][i].devtype == 0x05) && ((n & 0x10) != 0))) {
1978 m = 1;
1979 m = m << i;
1980 if ((dev->async[0] & m) != 0) {
1981 goto set_sync;
1982 }
1983 }
1984 continue;
1985set_sync:
1986 if (dev->sp[0][i] == 0x02) {
1987 synu[4] = 0x0c;
1988 synuw[4] = 0x0c;
1989 } else {
1990 if (dev->sp[0][i] >= 0x03) {
1991 synu[4] = 0x0a;
1992 synuw[4] = 0x0a;
1993 }
1994 }
1da177e4
LT		 1995 j = 0;
1996 if ((m & dev->wide_id[0]) != 0) {
1997 j |= 0x01;
1998 }
48502560
OZ		 1999 atp_writeb_io(dev, 0, 0x1b, j);
2000 atp_writeb_io(dev, 0, 3, satn[0]);
2001 atp_writeb_io(dev, 0, 4, satn[1]);
2002 atp_writeb_io(dev, 0, 5, satn[2]);
2003 atp_writeb_io(dev, 0, 6, satn[3]);
2004 atp_writeb_io(dev, 0, 7, satn[4]);
2005 atp_writeb_io(dev, 0, 8, satn[5]);
2006 atp_writeb_io(dev, 0, 0x0f, 0);
2007 atp_writeb_io(dev, 0, 0x11, dev->id[0][i].devsp);
2008 atp_writeb_io(dev, 0, 0x12, 0);
2009 atp_writeb_io(dev, 0, 0x13, satn[6]);
2010 atp_writeb_io(dev, 0, 0x14, satn[7]);
2011 atp_writeb_io(dev, 0, 0x18, satn[8]);
2012
2013 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 2014 cpu_relax();
2015
48502560 2016 if (atp_readb_io(dev, 0, 0x17) != 0x11 && atp_readb_io(dev, 0, 0x17) != 0x8e) {
1da177e4
LT		 2017 continue;
2018 }
48502560 2019 while (atp_readb_io(dev, 0, 0x17) != 0x8e)
1da177e4
LT		 2020 cpu_relax();
2021
2022try_sync:
2023 j = 0;
48502560
OZ		 2024 atp_writeb_io(dev, 0, 0x14, 0x06);
2025 atp_writeb_io(dev, 0, 0x18, 0x20);
3b30acf6 2026
48502560
OZ		 2027 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0) {
2028 if ((atp_readb_io(dev, 0, 0x1f) & 0x01) != 0) {
1da177e4
LT		 2029 if ((m & dev->wide_id[0]) != 0) {
2030 if ((m & dev->ultra_map[0]) != 0) {
48502560 2031 atp_writeb_io(dev, 0, 0x19, synuw[j++]);
1da177e4 2032 } else {
48502560 2033 atp_writeb_io(dev, 0, 0x19, synw[j++]);
1da177e4
LT		 2034 }
2035 } else {
2036 if ((m & dev->ultra_map[0]) != 0) {
48502560 2037 atp_writeb_io(dev, 0, 0x19, synu[j++]);
1da177e4 2038 } else {
48502560 2039 atp_writeb_io(dev, 0, 0x19, synn[j++]);
1da177e4
LT		 2040 }
2041 }
1da177e4
LT		 2042 }
2043 }
1da177e4 2044
48502560 2045 while ((atp_readb_io(dev, 0, 0x17) & 0x80) == 0x00)
1da177e4
LT		 2046 cpu_relax();
2047
48502560 2048 j = atp_readb_io(dev, 0, 0x17) & 0x0f;
1da177e4
LT		 2049 if (j == 0x0f) {
2050 goto phase_ins;
2051 }
2052 if (j == 0x0a) {
2053 goto phase_cmds;
2054 }
2055 if (j == 0x0e) {
2056 goto try_sync;
2057 }
2058 continue;
2059phase_outs:
48502560
OZ		 2060 atp_writeb_io(dev, 0, 0x18, 0x20);
2061 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00) {
2062 if ((atp_readb_io(dev, 0, 0x1f) & 0x01) != 0x00)
2063 atp_writeb_io(dev, 0, 0x19, 0x00);
1da177e4 2064 }
48502560 2065 j = atp_readb_io(dev, 0, 0x17);
1da177e4
LT		 2066 if (j == 0x85) {
2067 goto tar_dcons;
2068 }
2069 j &= 0x0f;
2070 if (j == 0x0f) {
2071 goto phase_ins;
2072 }
2073 if (j == 0x0a) {
2074 goto phase_cmds;
2075 }
2076 if (j == 0x0e) {
2077 goto phase_outs;
2078 }
2079 continue;
2080phase_ins:
48502560
OZ		 2081 atp_writeb_io(dev, 0, 0x14, 0x06);
2082 atp_writeb_io(dev, 0, 0x18, 0x20);
1da177e4
LT		 2083 k = 0;
2084phase_ins1:
48502560 2085 j = atp_readb_io(dev, 0, 0x1f);
1da177e4 2086 if ((j & 0x01) != 0x00) {
48502560 2087 mbuf[k++] = atp_readb_io(dev, 0, 0x19);
1da177e4
LT		 2088 goto phase_ins1;
2089 }
2090 if ((j & 0x80) == 0x00) {
2091 goto phase_ins1;
2092 }
1da177e4 2093
48502560 2094 while ((atp_readb_io(dev, 0, 0x17) & 0x80) == 0x00)
1da177e4
LT		 2095 cpu_relax();
2096
48502560 2097 j = atp_readb_io(dev, 0, 0x17);
1da177e4
LT		 2098 if (j == 0x85) {
2099 goto tar_dcons;
2100 }
2101 j &= 0x0f;
2102 if (j == 0x0f) {
2103 goto phase_ins;
2104 }
2105 if (j == 0x0a) {
2106 goto phase_cmds;
2107 }
2108 if (j == 0x0e) {
2109 goto phase_outs;
2110 }
2111 continue;
2112phase_cmds:
48502560 2113 atp_writeb_io(dev, 0, 0x10, 0x30);
1da177e4 2114tar_dcons:
48502560
OZ		 2115 atp_writeb_io(dev, 0, 0x14, 0x00);
2116 atp_writeb_io(dev, 0, 0x18, 0x08);
1da177e4 2117
48502560 2118 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00)
1da177e4
LT		 2119 cpu_relax();
2120
48502560 2121 j = atp_readb_io(dev, 0, 0x17);
1da177e4
LT		 2122 if (j != 0x16) {
2123 continue;
2124 }
2125 if (mbuf[0] != 0x01) {
2126 continue;
2127 }
2128 if (mbuf[1] != 0x03) {
2129 continue;
2130 }
2131 if (mbuf[4] == 0x00) {
2132 continue;
2133 }
2134 if (mbuf[3] > 0x64) {
2135 continue;
2136 }
2137 if (mbuf[4] > 0x0e) {
2138 mbuf[4] = 0x0e;
2139 }
2140 dev->id[0][i].devsp = mbuf[4];
2141 if (mbuf[3] < 0x0c) {
2142 j = 0xb0;
2143 goto set_syn_ok;
2144 }
2145 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
2146 j = 0xa0;
2147 goto set_syn_ok;
2148 }
2149 if (mbuf[3] < 0x1a) {
2150 j = 0x20;
2151 goto set_syn_ok;
2152 }
2153 if (mbuf[3] < 0x33) {
2154 j = 0x40;
2155 goto set_syn_ok;
2156 }
2157 if (mbuf[3] < 0x4c) {
2158 j = 0x50;
2159 goto set_syn_ok;
2160 }
2161 j = 0x60;
2162set_syn_ok:
2163 dev->id[0][i].devsp = (dev->id[0][i].devsp & 0x0f) | j;
2164 }
2165}
2166
2167static void atp870u_free_tables(struct Scsi_Host *host)
2168{
2169 struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
2170 int j, k;
2171 for (j=0; j < 2; j++) {
2172 for (k = 0; k < 16; k++) {
2173 if (!atp_dev->id[j][k].prd_table)
2174 continue;
b5683557 2175 pci_free_consistent(atp_dev->pdev, 1024, atp_dev->id[j][k].prd_table, atp_dev->id[j][k].prd_bus);
1da177e4
LT		 2176 atp_dev->id[j][k].prd_table = NULL;
2177 }
2178 }
2179}
2180
2181static int atp870u_init_tables(struct Scsi_Host *host)
2182{
2183 struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata;
2184 int c,k;
2185 for(c=0;c < 2;c++) {
2186 for(k=0;k<16;k++) {
b5683557 2187 atp_dev->id[c][k].prd_table = pci_alloc_consistent(atp_dev->pdev, 1024, &(atp_dev->id[c][k].prd_bus));
1da177e4
LT		 2188 if (!atp_dev->id[c][k].prd_table) {
2189 printk("atp870u_init_tables fail\n");
2190 atp870u_free_tables(host);
2191 return -ENOMEM;
2192 }
b5683557 2193 atp_dev->id[c][k].prdaddr = atp_dev->id[c][k].prd_bus;
1da177e4
LT		 2194 atp_dev->id[c][k].devsp=0x20;
2195 atp_dev->id[c][k].devtype = 0x7f;
2196 atp_dev->id[c][k].curr_req = NULL;
2197 }
2198
2199 atp_dev->active_id[c] = 0;
2200 atp_dev->wide_id[c] = 0;
2201 atp_dev->host_id[c] = 0x07;
2202 atp_dev->quhd[c] = 0;
2203 atp_dev->quend[c] = 0;
2204 atp_dev->last_cmd[c] = 0xff;
2205 atp_dev->in_snd[c] = 0;
2206 atp_dev->in_int[c] = 0;
2207
2208 for (k = 0; k < qcnt; k++) {
2209 atp_dev->quereq[c][k] = NULL;
2210 }
2211 for (k = 0; k < 16; k++) {
2212 atp_dev->id[c][k].curr_req = NULL;
2213 atp_dev->sp[c][k] = 0x04;
2214 }
2215 }
2216 return 0;
2217}
2218
2219/* return non-zero on detection */
2220static int atp870u_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2221{
2222 unsigned char k, m, c;
2223 unsigned long flags;
493c5201 2224 unsigned int base_io, error,n;
1da177e4
LT		 2225 unsigned char host_id;
2226 struct Scsi_Host *shpnt = NULL;
dc6a78f1 2227 struct atp_unit *atpdev, *p;
1da177e4
LT		 2228 unsigned char setupdata[2][16];
2229 int count = 0;
dc6a78f1
RD		 2230
2231 atpdev = kzalloc(sizeof(*atpdev), GFP_KERNEL);
2232 if (!atpdev)
2233 return -ENOMEM;
2234
1da177e4 2235 if (pci_enable_device(pdev))
dc6a78f1 2236 goto err_eio;
1da177e4 2237
284901a9 2238 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1da177e4
LT		 2239 printk(KERN_INFO "atp870u: use 32bit DMA mask.\n");
2240 } else {
2241 printk(KERN_ERR "atp870u: DMA mask required but not available.\n");
dc6a78f1 2242 goto err_eio;
1da177e4
LT		 2243 }
2244
1da177e4
LT		 2245 /*
2246 * It's probably easier to weed out some revisions like
2247 * this than via the PCI device table
2248 */
2249 if (ent->device == PCI_DEVICE_ID_ARTOP_AEC7610) {
7d7311c4 2250 atpdev->chip_ver = pdev->revision;
dc6a78f1
RD		 2251 if (atpdev->chip_ver < 2)
2252 goto err_eio;
1da177e4
LT		 2253 }
2254
2255 switch (ent->device) {
2256 case PCI_DEVICE_ID_ARTOP_AEC7612UW:
2257 case PCI_DEVICE_ID_ARTOP_AEC7612SUW:
2258 case ATP880_DEVID1:
2259 case ATP880_DEVID2:
2260 case ATP885_DEVID:
dc6a78f1 2261 atpdev->chip_ver = 0x04;
1da177e4
LT		 2262 default:
2263 break;
2264 }
2265 base_io = pci_resource_start(pdev, 0);
2266 base_io &= 0xfffffff8;
6a3cebb6 2267 atpdev->baseport = base_io;
dc6a78f1 2268
1da177e4 2269 if ((ent->device == ATP880_DEVID1)||(ent->device == ATP880_DEVID2)) {
7d7311c4 2270 atpdev->chip_ver = pdev->revision;
1da177e4
LT		 2271 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);//JCC082803
2272
2273 host_id = inb(base_io + 0x39);
2274 host_id >>= 0x04;
2275
2276 printk(KERN_INFO " ACARD AEC-67160 PCI Ultra3 LVD Host Adapter: %d"
2277 " IO:%x, IRQ:%d.\n", count, base_io, pdev->irq);
dc6a78f1
RD		 2278 atpdev->ioport[0] = base_io + 0x40;
2279 atpdev->pciport[0] = base_io + 0x28;
2280 atpdev->dev_id = ent->device;
2281 atpdev->host_id[0] = host_id;
1da177e4 2282
493c5201
OZ		 2283 atpdev->scam_on = inb(base_io + 0x22);
2284 atpdev->global_map[0] = inb(base_io + 0x35);
2285 atpdev->ultra_map[0] = inw(base_io + 0x3c);
1da177e4
LT		 2286
2287 n = 0x3f09;
2288next_fblk_880:
2289 if (n >= 0x4000)
2290 goto flash_ok_880;
2291
2292 m = 0;
2293 outw(n, base_io + 0x34);
2294 n += 0x0002;
2295 if (inb(base_io + 0x30) == 0xff)
2296 goto flash_ok_880;
2297
dc6a78f1
RD		 2298 atpdev->sp[0][m++] = inb(base_io + 0x30);
2299 atpdev->sp[0][m++] = inb(base_io + 0x31);
2300 atpdev->sp[0][m++] = inb(base_io + 0x32);
2301 atpdev->sp[0][m++] = inb(base_io + 0x33);
1da177e4
LT		 2302 outw(n, base_io + 0x34);
2303 n += 0x0002;
dc6a78f1
RD		 2304 atpdev->sp[0][m++] = inb(base_io + 0x30);
2305 atpdev->sp[0][m++] = inb(base_io + 0x31);
2306 atpdev->sp[0][m++] = inb(base_io + 0x32);
2307 atpdev->sp[0][m++] = inb(base_io + 0x33);
1da177e4
LT		 2308 outw(n, base_io + 0x34);
2309 n += 0x0002;
dc6a78f1
RD		 2310 atpdev->sp[0][m++] = inb(base_io + 0x30);
2311 atpdev->sp[0][m++] = inb(base_io + 0x31);
2312 atpdev->sp[0][m++] = inb(base_io + 0x32);
2313 atpdev->sp[0][m++] = inb(base_io + 0x33);
1da177e4
LT		 2314 outw(n, base_io + 0x34);
2315 n += 0x0002;
dc6a78f1
RD		 2316 atpdev->sp[0][m++] = inb(base_io + 0x30);
2317 atpdev->sp[0][m++] = inb(base_io + 0x31);
2318 atpdev->sp[0][m++] = inb(base_io + 0x32);
2319 atpdev->sp[0][m++] = inb(base_io + 0x33);
1da177e4
LT		 2320 n += 0x0018;
2321 goto next_fblk_880;
2322flash_ok_880:
2323 outw(0, base_io + 0x34);
dc6a78f1
RD		 2324 atpdev->ultra_map[0] = 0;
2325 atpdev->async[0] = 0;
1da177e4
LT		 2326 for (k = 0; k < 16; k++) {
2327 n = 1;
2328 n = n << k;
dc6a78f1
RD		 2329 if (atpdev->sp[0][k] > 1) {
2330 atpdev->ultra_map[0] |= n;
1da177e4 2331 } else {
dc6a78f1
RD		 2332 if (atpdev->sp[0][k] == 0)
2333 atpdev->async[0] |= n;
1da177e4
LT		 2334 }
2335 }
dc6a78f1
RD		 2336 atpdev->async[0] = ~(atpdev->async[0]);
2337 outb(atpdev->global_map[0], base_io + 0x35);
1da177e4
LT		 2338
2339 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2340 if (!shpnt)
dc6a78f1 2341 goto err_nomem;
1da177e4
LT		 2342
2343 p = (struct atp_unit *)&shpnt->hostdata;
2344
dc6a78f1
RD		 2345 atpdev->host = shpnt;
2346 atpdev->pdev = pdev;
1da177e4 2347 pci_set_drvdata(pdev, p);
dc6a78f1 2348 memcpy(p, atpdev, sizeof(*atpdev));
1da177e4
LT		 2349 if (atp870u_init_tables(shpnt) < 0) {
2350 printk(KERN_ERR "Unable to allocate tables for Acard controller\n");
2351 goto unregister;
2352 }
2353
1d6f359a 2354 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp880i", shpnt)) {
1da177e4
LT		 2355 printk(KERN_ERR "Unable to allocate IRQ%d for Acard controller.\n", pdev->irq);
2356 goto free_tables;
2357 }
2358
2359 spin_lock_irqsave(shpnt->host_lock, flags);
493c5201
OZ		 2360 k = inb(base_io + 0x38) & 0x80;
2361 outb(k, base_io + 0x38);
2362 outb(0x20, base_io + 0x3b);
1da177e4 2363 mdelay(32);
493c5201 2364 outb(0, base_io + 0x3b);
1da177e4 2365 mdelay(32);
493c5201
OZ		 2366 inb(base_io + 0x5b);
2367 inb(base_io + 0x57);
2368 outb((host_id | 0x08), base_io + 0x40);
2369 outb(0, base_io + 0x58);
2370 while ((inb(base_io + 0x5f) & 0x80) == 0)
1da177e4 2371 mdelay(1);
493c5201
OZ		 2372 inb(base_io + 0x57);
2373 outb(8, base_io + 0x41);
2374 outb(0x7f, base_io + 0x42);
2375 outb(0x20, base_io + 0x51);
1da177e4
LT		 2376
2377 tscam(shpnt);
48502560 2378 is880(p);
493c5201 2379 outb(0xb0, base_io + 0x38);
1da177e4
LT		 2380 shpnt->max_id = 16;
2381 shpnt->this_id = host_id;
2382 shpnt->unique_id = base_io;
2383 shpnt->io_port = base_io;
2384 shpnt->n_io_port = 0x60; /* Number of bytes of I/O space used */
2385 shpnt->irq = pdev->irq;
2386 } else if (ent->device == ATP885_DEVID) {
2387 printk(KERN_INFO " ACARD AEC-67162 PCI Ultra3 LVD Host Adapter: IO:%x, IRQ:%d.\n"
2388 , base_io, pdev->irq);
2389
dc6a78f1
RD		 2390 atpdev->pdev = pdev;
2391 atpdev->dev_id = ent->device;
dc6a78f1
RD		 2392 atpdev->ioport[0] = base_io + 0x80;
2393 atpdev->ioport[1] = base_io + 0xc0;
2394 atpdev->pciport[0] = base_io + 0x40;
2395 atpdev->pciport[1] = base_io + 0x50;
1da177e4
LT		 2396
2397 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2398 if (!shpnt)
dc6a78f1 2399 goto err_nomem;
1da177e4
LT		 2400
2401 p = (struct atp_unit *)&shpnt->hostdata;
2402
dc6a78f1
RD		 2403 atpdev->host = shpnt;
2404 atpdev->pdev = pdev;
1da177e4 2405 pci_set_drvdata(pdev, p);
dc6a78f1 2406 memcpy(p, atpdev, sizeof(struct atp_unit));
1da177e4
LT		 2407 if (atp870u_init_tables(shpnt) < 0)
2408 goto unregister;
2409
2410#ifdef ED_DBGP
2411 printk("request_irq() shpnt %p hostdata %p\n", shpnt, p);
2412#endif
1d6f359a 2413 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp870u", shpnt)) {
1da177e4
LT		 2414 printk(KERN_ERR "Unable to allocate IRQ for Acard controller.\n");
2415 goto free_tables;
2416 }
2417
2418 spin_lock_irqsave(shpnt->host_lock, flags);
2419
2420 c=inb(base_io + 0x29);
2421 outb((c | 0x04),base_io + 0x29);
2422
2423 n=0x1f80;
2424next_fblk_885:
2425 if (n >= 0x2000) {
2426 goto flash_ok_885;
2427 }
2428 outw(n,base_io + 0x3c);
2429 if (inl(base_io + 0x38) == 0xffffffff) {
2430 goto flash_ok_885;
2431 }
2432 for (m=0; m < 2; m++) {
2433 p->global_map[m]= 0;
2434 for (k=0; k < 4; k++) {
2435 outw(n++,base_io + 0x3c);
2436 ((unsigned long *)&setupdata[m][0])[k]=inl(base_io + 0x38);
2437 }
2438 for (k=0; k < 4; k++) {
2439 outw(n++,base_io + 0x3c);
2440 ((unsigned long *)&p->sp[m][0])[k]=inl(base_io + 0x38);
2441 }
2442 n += 8;
2443 }
2444 goto next_fblk_885;
2445flash_ok_885:
2446#ifdef ED_DBGP
2447 printk( "Flash Read OK\n");
2448#endif
2449 c=inb(base_io + 0x29);
2450 outb((c & 0xfb),base_io + 0x29);
2451 for (c=0;c < 2;c++) {
2452 p->ultra_map[c]=0;
2453 p->async[c] = 0;
2454 for (k=0; k < 16; k++) {
2455 n=1;
2456 n = n << k;
2457 if (p->sp[c][k] > 1) {
2458 p->ultra_map[c] |= n;
2459 } else {
2460 if (p->sp[c][k] == 0) {
2461 p->async[c] |= n;
2462 }
2463 }
2464 }
2465 p->async[c] = ~(p->async[c]);
2466
2467 if (p->global_map[c] == 0) {
2468 k=setupdata[c][1];
2469 if ((k & 0x40) != 0)
2470 p->global_map[c] |= 0x20;
2471 k &= 0x07;
2472 p->global_map[c] |= k;
2473 if ((setupdata[c][2] & 0x04) != 0)
2474 p->global_map[c] |= 0x08;
2475 p->host_id[c] = setupdata[c][0] & 0x07;
2476 }
2477 }
2478
2479 k = inb(base_io + 0x28) & 0x8f;
2480 k |= 0x10;
2481 outb(k, base_io + 0x28);
2482 outb(0x80, base_io + 0x41);
2483 outb(0x80, base_io + 0x51);
2484 mdelay(100);
2485 outb(0, base_io + 0x41);
2486 outb(0, base_io + 0x51);
2487 mdelay(1000);
2488 inb(base_io + 0x9b);
2489 inb(base_io + 0x97);
2490 inb(base_io + 0xdb);
2491 inb(base_io + 0xd7);
1da177e4
LT		 2492 k=p->host_id[0];
2493 if (k > 7)
2494 k = (k & 0x07) | 0x40;
2495 k |= 0x08;
493c5201
OZ		 2496 outb(k, base_io + 0x80);
2497 outb(0, base_io + 0x98);
1da177e4 2498
493c5201 2499 while ((inb(base_io + 0x9f) & 0x80) == 0)
1da177e4
LT		 2500 cpu_relax();
2501
493c5201
OZ		 2502 inb(base_io + 0x97);
2503 outb(8, base_io + 0x81);
2504 outb(0x7f, base_io + 0x82);
2505 outb(0x20, base_io + 0x91);
2506
1da177e4
LT		 2507 k=p->host_id[1];
2508 if (k > 7)
2509 k = (k & 0x07) | 0x40;
2510 k |= 0x08;
493c5201
OZ		 2511 outb(k, base_io + 0xc0);
2512 outb(0, base_io + 0xd8);
1da177e4 2513
493c5201 2514 while ((inb(base_io + 0xdf) & 0x80) == 0)
1da177e4
LT		 2515 cpu_relax();
2516
493c5201
OZ		 2517 inb(base_io + 0xd7);
2518 outb(8, base_io + 0xc1);
2519 outb(0x7f, base_io + 0xc2);
2520 outb(0x20, base_io + 0xd1);
1da177e4
LT		 2521
2522 tscam_885();
2523 printk(KERN_INFO " Scanning Channel A SCSI Device ...\n");
2524 is885(p, base_io + 0x80, 0);
2525 printk(KERN_INFO " Scanning Channel B SCSI Device ...\n");
2526 is885(p, base_io + 0xc0, 1);
2527
2528 k = inb(base_io + 0x28) & 0xcf;
2529 k |= 0xc0;
2530 outb(k, base_io + 0x28);
2531 k = inb(base_io + 0x1f) | 0x80;
2532 outb(k, base_io + 0x1f);
2533 k = inb(base_io + 0x29) | 0x01;
2534 outb(k, base_io + 0x29);
2535#ifdef ED_DBGP
2536 //printk("atp885: atp_host[0] 0x%p\n", atp_host[0]);
2537#endif
2538 shpnt->max_id = 16;
2539 shpnt->max_lun = (p->global_map[0] & 0x07) + 1;
2540 shpnt->max_channel = 1;
2541 shpnt->this_id = p->host_id[0];
2542 shpnt->unique_id = base_io;
2543 shpnt->io_port = base_io;
2544 shpnt->n_io_port = 0xff; /* Number of bytes of I/O space used */
2545 shpnt->irq = pdev->irq;
2546
2547 } else {
2548 error = pci_read_config_byte(pdev, 0x49, &host_id);
2549
2550 printk(KERN_INFO " ACARD AEC-671X PCI Ultra/W SCSI-2/3 Host Adapter: %d "
2551 "IO:%x, IRQ:%d.\n", count, base_io, pdev->irq);
2552
dc6a78f1
RD		 2553 atpdev->ioport[0] = base_io;
2554 atpdev->pciport[0] = base_io + 0x20;
2555 atpdev->dev_id = ent->device;
1da177e4 2556 host_id &= 0x07;
dc6a78f1 2557 atpdev->host_id[0] = host_id;
493c5201
OZ		 2558 atpdev->scam_on = inb(base_io + 0x22);
2559 atpdev->global_map[0] = inb(base_io + 0x2d);
2560 atpdev->ultra_map[0] = inw(base_io + 0x2e);
1da177e4 2561
dc6a78f1
RD		 2562 if (atpdev->ultra_map[0] == 0) {
2563 atpdev->scam_on = 0x00;
2564 atpdev->global_map[0] = 0x20;
2565 atpdev->ultra_map[0] = 0xffff;
1da177e4
LT		 2566 }
2567
2568 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit));
2569 if (!shpnt)
dc6a78f1 2570 goto err_nomem;
1da177e4
LT		 2571
2572 p = (struct atp_unit *)&shpnt->hostdata;
2573
dc6a78f1
RD		 2574 atpdev->host = shpnt;
2575 atpdev->pdev = pdev;
1da177e4 2576 pci_set_drvdata(pdev, p);
dc6a78f1 2577 memcpy(p, atpdev, sizeof(*atpdev));
1da177e4
LT		 2578 if (atp870u_init_tables(shpnt) < 0)
2579 goto unregister;
2580
1d6f359a 2581 if (request_irq(pdev->irq, atp870u_intr_handle, IRQF_SHARED, "atp870i", shpnt)) {
1da177e4
LT		 2582 printk(KERN_ERR "Unable to allocate IRQ%d for Acard controller.\n", pdev->irq);
2583 goto free_tables;
2584 }
2585
2586 spin_lock_irqsave(shpnt->host_lock, flags);
dc6a78f1 2587 if (atpdev->chip_ver > 0x07) { /* check if atp876 chip then enable terminator */
493c5201 2588 outb(0x00, base_io + 0x3e);
1da177e4
LT		 2589 }
2590
493c5201
OZ		 2591 k = (inb(base_io + 0x3a) & 0xf3) | 0x10;
2592 outb(k, base_io + 0x3a);
2593 outb((k & 0xdf), base_io + 0x3a);
1da177e4 2594 mdelay(32);
493c5201 2595 outb(k, base_io + 0x3a);
1da177e4 2596 mdelay(32);
493c5201
OZ		 2597 outb((host_id | 0x08), base_io + 0);
2598 outb(0, base_io + 0x18);
2599 while ((inb(base_io + 0x1f) & 0x80) == 0)
1da177e4
LT		 2600 mdelay(1);
2601
493c5201
OZ		 2602 inb(base_io + 0x17);
2603 outb(8, base_io + 1);
2604 outb(0x7f, base_io + 2);
2605 outb(0x20, base_io + 0x11);
1da177e4
LT		 2606
2607 tscam(shpnt);
152c3ac5 2608 is870(p);
493c5201
OZ		 2609 outb((inb(base_io + 0x3a) & 0xef), base_io + 0x3a);
2610 outb((inb(base_io + 0x3b) | 0x20), base_io + 0x3b);
dc6a78f1 2611 if (atpdev->chip_ver == 4)
1da177e4
LT		 2612 shpnt->max_id = 16;
2613 else
2b89dad0 2614 shpnt->max_id = 8;
1da177e4
LT		 2615 shpnt->this_id = host_id;
2616 shpnt->unique_id = base_io;
2617 shpnt->io_port = base_io;
2618 shpnt->n_io_port = 0x40; /* Number of bytes of I/O space used */
2619 shpnt->irq = pdev->irq;
2620 }
2621 spin_unlock_irqrestore(shpnt->host_lock, flags);
2622 if(ent->device==ATP885_DEVID) {
2623 if(!request_region(base_io, 0xff, "atp870u")) /* Register the IO ports that we use */
2624 goto request_io_fail;
2625 } else if((ent->device==ATP880_DEVID1)||(ent->device==ATP880_DEVID2)) {
2626 if(!request_region(base_io, 0x60, "atp870u")) /* Register the IO ports that we use */
2627 goto request_io_fail;
2628 } else {
2629 if(!request_region(base_io, 0x40, "atp870u")) /* Register the IO ports that we use */
2630 goto request_io_fail;
2631 }
2632 count++;
2633 if (scsi_add_host(shpnt, &pdev->dev))
2634 goto scsi_add_fail;
2635 scsi_scan_host(shpnt);
2636#ifdef ED_DBGP
2637 printk("atp870u_prob : exit\n");
2638#endif
2639 return 0;
2640
2641scsi_add_fail:
2642 printk("atp870u_prob:scsi_add_fail\n");
2643 if(ent->device==ATP885_DEVID) {
2644 release_region(base_io, 0xff);
2645 } else if((ent->device==ATP880_DEVID1)||(ent->device==ATP880_DEVID2)) {
2646 release_region(base_io, 0x60);
2647 } else {
2648 release_region(base_io, 0x40);
2649 }
2650request_io_fail:
2651 printk("atp870u_prob:request_io_fail\n");
2652 free_irq(pdev->irq, shpnt);
2653free_tables:
2654 printk("atp870u_prob:free_table\n");
2655 atp870u_free_tables(shpnt);
2656unregister:
2657 printk("atp870u_prob:unregister\n");
2658 scsi_host_put(shpnt);
2659 return -1;
dc6a78f1
RD		 2660err_eio:
2661 kfree(atpdev);
2662 return -EIO;
2663err_nomem:
2664 kfree(atpdev);
2665 return -ENOMEM;
1da177e4
LT		 2666}
2667
2668/* The abort command does not leave the device in a clean state where
2669 it is available to be used again. Until this gets worked out, we will
2670 leave it commented out. */
2671
2672static int atp870u_abort(struct scsi_cmnd * SCpnt)
2673{
2674 unsigned char j, k, c;
2675 struct scsi_cmnd *workrequ;
1da177e4
LT		 2676 struct atp_unit *dev;
2677 struct Scsi_Host *host;
2678 host = SCpnt->device->host;
2679
2680 dev = (struct atp_unit *)&host->hostdata;
422c0d61 2681 c = scmd_channel(SCpnt);
1da177e4
LT		 2682 printk(" atp870u: abort Channel = %x \n", c);
2683 printk("working=%x last_cmd=%x ", dev->working[c], dev->last_cmd[c]);
2684 printk(" quhdu=%x quendu=%x ", dev->quhd[c], dev->quend[c]);
1da177e4 2685 for (j = 0; j < 0x18; j++) {
6a3cebb6 2686 printk(" r%2x=%2x", j, atp_readb_io(dev, c, j));
1da177e4 2687 }
6a3cebb6
OZ		 2688 printk(" r1c=%2x", atp_readb_io(dev, c, 0x1c));
2689 printk(" r1f=%2x in_snd=%2x ", atp_readb_io(dev, c, 0x1f), dev->in_snd[c]);
2690 printk(" d00=%2x", atp_readb_pci(dev, c, 0x00));
2691 printk(" d02=%2x", atp_readb_pci(dev, c, 0x02));
1da177e4
LT		 2692 for(j=0;j<16;j++) {
2693 if (dev->id[c][j].curr_req != NULL) {
2694 workrequ = dev->id[c][j].curr_req;
2695 printk("\n que cdb= ");
2696 for (k=0; k < workrequ->cmd_len; k++) {
2697 printk(" %2x ",workrequ->cmnd[k]);
2698 }
2699 printk(" last_lenu= %x ",(unsigned int)dev->id[c][j].last_len);
2700 }
2701 }
2702 return SUCCESS;
2703}
2704
2705static const char *atp870u_info(struct Scsi_Host *notused)
2706{
2707 static char buffer[128];
2708
2709 strcpy(buffer, "ACARD AEC-6710/6712/67160 PCI Ultra/W/LVD SCSI-3 Adapter Driver V2.6+ac ");
2710
2711 return buffer;
2712}
2713
d773e422 2714static int atp870u_show_info(struct seq_file *m, struct Scsi_Host *HBAptr)
1da177e4 2715{
3d30079c
RV		 2716 seq_puts(m, "ACARD AEC-671X Driver Version: 2.6+ac\n\n"
2717 "Adapter Configuration:\n");
d773e422
AV		 2718 seq_printf(m, " Base IO: %#.4lx\n", HBAptr->io_port);
2719 seq_printf(m, " IRQ: %d\n", HBAptr->irq);
2720 return 0;
1da177e4
LT		 2721}
2722
2723
2724static int atp870u_biosparam(struct scsi_device *disk, struct block_device *dev,
2725 sector_t capacity, int *ip)
2726{
2727 int heads, sectors, cylinders;
2728
2729 heads = 64;
2730 sectors = 32;
2731 cylinders = (unsigned long)capacity / (heads * sectors);
2732 if (cylinders > 1024) {
2733 heads = 255;
2734 sectors = 63;
2735 cylinders = (unsigned long)capacity / (heads * sectors);
2736 }
2737 ip[0] = heads;
2738 ip[1] = sectors;
2739 ip[2] = cylinders;
2740
2741 return 0;
2742}
2743
2744static void atp870u_remove (struct pci_dev *pdev)
2745{
2746 struct atp_unit *devext = pci_get_drvdata(pdev);
2747 struct Scsi_Host *pshost = devext->host;
2748
2749
2750 scsi_remove_host(pshost);
2751 printk(KERN_INFO "free_irq : %d\n",pshost->irq);
2752 free_irq(pshost->irq, pshost);
2753 release_region(pshost->io_port, pshost->n_io_port);
2754 printk(KERN_INFO "atp870u_free_tables : %p\n",pshost);
2755 atp870u_free_tables(pshost);
2756 printk(KERN_INFO "scsi_host_put : %p\n",pshost);
2757 scsi_host_put(pshost);
1da177e4
LT		 2758}
2759MODULE_LICENSE("GPL");
2760
2761static struct scsi_host_template atp870u_template = {
2762 .module = THIS_MODULE,
2763 .name = "atp870u" /* name */,
2764 .proc_name = "atp870u",
d773e422 2765 .show_info = atp870u_show_info,
1da177e4
LT		 2766 .info = atp870u_info /* info */,
2767 .queuecommand = atp870u_queuecommand /* queuecommand */,
2768 .eh_abort_handler = atp870u_abort /* abort */,
2769 .bios_param = atp870u_biosparam /* biosparm */,
2770 .can_queue = qcnt /* can_queue */,
2771 .this_id = 7 /* SCSI ID */,
2772 .sg_tablesize = ATP870U_SCATTER /*SG_ALL*/ /*SG_NONE*/,
1da177e4
LT		 2773 .use_clustering = ENABLE_CLUSTERING,
2774 .max_sectors = ATP870U_MAX_SECTORS,
2775};
2776
2777static struct pci_device_id atp870u_id_table[] = {
2778 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP885_DEVID) },
2779 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID1) },
2780 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID2) },
2781 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7610) },
2782 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612UW) },
2783 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612U) },
2784 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612S) },
2785 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612D) },
2786 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612SUW) },
2787 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_8060) },
2788 { 0, },
2789};
2790
2791MODULE_DEVICE_TABLE(pci, atp870u_id_table);
2792
2793static struct pci_driver atp870u_driver = {
2794 .id_table = atp870u_id_table,
2795 .name = "atp870u",
2796 .probe = atp870u_probe,
6f039790 2797 .remove = atp870u_remove,
1da177e4
LT		 2798};
2799
2800static int __init atp870u_init(void)
2801{
2802#ifdef ED_DBGP
2803 printk("atp870u_init: Entry\n");
2804#endif
2805 return pci_register_driver(&atp870u_driver);
2806}
2807
2808static void __exit atp870u_exit(void)
2809{
2810#ifdef ED_DBGP
2811 printk("atp870u_exit: Entry\n");
2812#endif
2813 pci_unregister_driver(&atp870u_driver);
2814}
2815
2816static void tscam_885(void)
2817{
2818 unsigned char i;
2819
2820 for (i = 0; i < 0x2; i++) {
2821 mdelay(300);
2822 }
2823 return;
2824}
2825
2826
2827
2828static void is885(struct atp_unit *dev, unsigned int wkport,unsigned char c)
2829{
1da177e4
LT		 2830 unsigned char i, j, k, rmb, n, lvdmode;
2831 unsigned short int m;
2832 static unsigned char mbuf[512];
2833 static unsigned char satn[9] = {0, 0, 0, 0, 0, 0, 0, 6, 6};
2834 static unsigned char inqd[9] = {0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6};
2835 static unsigned char synn[6] = {0x80, 1, 3, 1, 0x19, 0x0e};
2836 unsigned char synu[6] = {0x80, 1, 3, 1, 0x0a, 0x0e};
2837 static unsigned char synw[6] = {0x80, 1, 3, 1, 0x19, 0x0e};
2838 unsigned char synuw[6] = {0x80, 1, 3, 1, 0x0a, 0x0e};
2839 static unsigned char wide[6] = {0x80, 1, 2, 3, 1, 0};
2840 static unsigned char u3[9] = { 0x80,1,6,4,0x09,00,0x0e,0x01,0x02 };
2841
2842 lvdmode=inb(wkport + 0x1b) >> 7;
2843
2844 for (i = 0; i < 16; i++) {
2845 m = 1;
2846 m = m << i;
2847 if ((m & dev->active_id[c]) != 0) {
2848 continue;
2849 }
2850 if (i == dev->host_id[c]) {
2851 printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[c]);
2852 continue;
2853 }
e2c22b45
OZ		 2854 outb(0x01, wkport + 0x1b);
2855 outb(0x08, wkport + 0x01);
2856 outb(0x7f, wkport + 0x02);
2857 outb(satn[0], wkport + 0x03);
2858 outb(satn[1], wkport + 0x04);
2859 outb(satn[2], wkport + 0x05);
2860 outb(satn[3], wkport + 0x06);
2861 outb(satn[4], wkport + 0x07);
2862 outb(satn[5], wkport + 0x08);
2863 outb(0, wkport + 0x0f);
2864 outb(dev->id[c][i].devsp, wkport + 0x11);
1da177e4 2865
e2c22b45
OZ		 2866 outb(0, wkport + 0x12);
2867 outb(satn[6], wkport + 0x13);
2868 outb(satn[7], wkport + 0x14);
1da177e4
LT		 2869 j = i;
2870 if ((j & 0x08) != 0) {
2871 j = (j & 0x07) | 0x40;
2872 }
e2c22b45
OZ		 2873 outb(j, wkport + 0x15);
2874 outb(satn[8], wkport + 0x18);
1da177e4 2875
e2c22b45 2876 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 2877 cpu_relax();
e2c22b45 2878 if ((inb(wkport + 0x17) != 0x11) && (inb(wkport + 0x17) != 0x8e)) {
1da177e4
LT		 2879 continue;
2880 }
e2c22b45 2881 while (inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 2882 cpu_relax();
2883 dev->active_id[c] |= m;
2884
e2c22b45
OZ		 2885 outb(0x30, wkport + 0x10);
2886 outb(0x00, wkport + 0x14);
1da177e4
LT		 2887
2888phase_cmd:
e2c22b45
OZ		 2889 outb(0x08, wkport + 0x18);
2890 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 2891 cpu_relax();
e2c22b45 2892 j = inb(wkport + 0x17);
1da177e4 2893 if (j != 0x16) {
e2c22b45 2894 outb(0x41, wkport + 0x10);
1da177e4
LT		 2895 goto phase_cmd;
2896 }
2897sel_ok:
e2c22b45
OZ		 2898 outb(inqd[0], wkport + 0x03);
2899 outb(inqd[1], wkport + 0x04);
2900 outb(inqd[2], wkport + 0x05);
2901 outb(inqd[3], wkport + 0x06);
2902 outb(inqd[4], wkport + 0x07);
2903 outb(inqd[5], wkport + 0x08);
2904 outb(0, wkport + 0x0f);
2905 outb(dev->id[c][i].devsp, wkport + 0x11);
2906 outb(0, wkport + 0x12);
2907 outb(inqd[6], wkport + 0x13);
2908 outb(inqd[7], wkport + 0x14);
2909 outb(inqd[8], wkport + 0x18);
2910 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 2911 cpu_relax();
e2c22b45 2912 if ((inb(wkport + 0x17) != 0x11) && (inb(wkport + 0x17) != 0x8e)) {
1da177e4
LT		 2913 continue;
2914 }
e2c22b45 2915 while (inb(wkport + 0x17) != 0x8e)
1da177e4 2916 cpu_relax();
e2c22b45
OZ		 2917 outb(0x00, wkport + 0x1b);
2918 outb(0x08, wkport + 0x18);
1da177e4
LT		 2919 j = 0;
2920rd_inq_data:
e2c22b45 2921 k = inb(wkport + 0x1f);
1da177e4 2922 if ((k & 0x01) != 0) {
e2c22b45 2923 mbuf[j++] = inb(wkport + 0x19);
1da177e4
LT		 2924 goto rd_inq_data;
2925 }
2926 if ((k & 0x80) == 0) {
2927 goto rd_inq_data;
2928 }
e2c22b45 2929 j = inb(wkport + 0x17);
1da177e4
LT		 2930 if (j == 0x16) {
2931 goto inq_ok;
2932 }
e2c22b45
OZ		 2933 outb(0x46, wkport + 0x10);
2934 outb(0, wkport + 0x12);
2935 outb(0, wkport + 0x13);
2936 outb(0, wkport + 0x14);
2937 outb(0x08, wkport + 0x18);
2938 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 2939 cpu_relax();
e2c22b45 2940 if (inb(wkport + 0x17) != 0x16) {
1da177e4
LT		 2941 goto sel_ok;
2942 }
2943inq_ok:
2944 mbuf[36] = 0;
2945 printk( KERN_INFO" ID: %2d %s\n", i, &mbuf[8]);
2946 dev->id[c][i].devtype = mbuf[0];
2947 rmb = mbuf[1];
2948 n = mbuf[7];
2949 if ((mbuf[7] & 0x60) == 0) {
2950 goto not_wide;
2951 }
2952 if ((i < 8) && ((dev->global_map[c] & 0x20) == 0)) {
2953 goto not_wide;
2954 }
2955 if (lvdmode == 0) {
2956 goto chg_wide;
2957 }
2958 if (dev->sp[c][i] != 0x04) { // force u2
2959 goto chg_wide;
2960 }
2961
e2c22b45
OZ		 2962 outb(0x01, wkport + 0x1b);
2963 outb(satn[0], wkport + 0x03);
2964 outb(satn[1], wkport + 0x04);
2965 outb(satn[2], wkport + 0x05);
2966 outb(satn[3], wkport + 0x06);
2967 outb(satn[4], wkport + 0x07);
2968 outb(satn[5], wkport + 0x08);
2969 outb(0, wkport + 0x0f);
2970 outb(dev->id[c][i].devsp, wkport + 0x11);
2971 outb(0, wkport + 0x12);
2972 outb(satn[6], wkport + 0x13);
2973 outb(satn[7], wkport + 0x14);
2974 outb(satn[8], wkport + 0x18);
2975
2976 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 2977 cpu_relax();
e2c22b45 2978 if ((inb(wkport + 0x17) != 0x11) && (inb(wkport + 0x17) != 0x8e)) {
1da177e4
LT		 2979 continue;
2980 }
e2c22b45 2981 while (inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 2982 cpu_relax();
2983try_u3:
2984 j = 0;
e2c22b45
OZ		 2985 outb(0x09, wkport + 0x14);
2986 outb(0x20, wkport + 0x18);
2987
2988 while ((inb(wkport + 0x1f) & 0x80) == 0) {
2989 if ((inb(wkport + 0x1f) & 0x01) != 0)
2990 outb(u3[j++], wkport + 0x19);
1da177e4
LT		 2991 cpu_relax();
2992 }
e2c22b45 2993 while ((inb(wkport + 0x17) & 0x80) == 0x00)
1da177e4 2994 cpu_relax();
e2c22b45 2995 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 2996 if (j == 0x0f) {
2997 goto u3p_in;
2998 }
2999 if (j == 0x0a) {
3000 goto u3p_cmd;
3001 }
3002 if (j == 0x0e) {
3003 goto try_u3;
3004 }
3005 continue;
3006u3p_out:
e2c22b45
OZ		 3007 outb(0x20, wkport + 0x18);
3008 while ((inb(wkport + 0x1f) & 0x80) == 0) {
3009 if ((inb(wkport + 0x1f) & 0x01) != 0)
3010 outb(0, wkport + 0x19);
1da177e4
LT		 3011 cpu_relax();
3012 }
e2c22b45 3013 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 3014 if (j == 0x0f) {
3015 goto u3p_in;
3016 }
3017 if (j == 0x0a) {
3018 goto u3p_cmd;
3019 }
3020 if (j == 0x0e) {
3021 goto u3p_out;
3022 }
3023 continue;
3024u3p_in:
e2c22b45
OZ		 3025 outb(0x09, wkport + 0x14);
3026 outb(0x20, wkport + 0x18);
1da177e4
LT		 3027 k = 0;
3028u3p_in1:
e2c22b45 3029 j = inb(wkport + 0x1f);
1da177e4 3030 if ((j & 0x01) != 0) {
e2c22b45 3031 mbuf[k++] = inb(wkport + 0x19);
1da177e4
LT		 3032 goto u3p_in1;
3033 }
3034 if ((j & 0x80) == 0x00) {
3035 goto u3p_in1;
3036 }
e2c22b45 3037 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 3038 if (j == 0x0f) {
3039 goto u3p_in;
3040 }
3041 if (j == 0x0a) {
3042 goto u3p_cmd;
3043 }
3044 if (j == 0x0e) {
3045 goto u3p_out;
3046 }
3047 continue;
3048u3p_cmd:
e2c22b45
OZ		 3049 outb(0x30, wkport + 0x10);
3050 outb(0x00, wkport + 0x14);
3051 outb(0x08, wkport + 0x18);
3052 while ((inb(wkport + 0x1f) & 0x80) == 0x00);
3053 j = inb(wkport + 0x17);
1da177e4
LT		 3054 if (j != 0x16) {
3055 if (j == 0x4e) {
3056 goto u3p_out;
3057 }
3058 continue;
3059 }
3060 if (mbuf[0] != 0x01) {
3061 goto chg_wide;
3062 }
3063 if (mbuf[1] != 0x06) {
3064 goto chg_wide;
3065 }
3066 if (mbuf[2] != 0x04) {
3067 goto chg_wide;
3068 }
3069 if (mbuf[3] == 0x09) {
3070 m = 1;
3071 m = m << i;
3072 dev->wide_id[c] |= m;
3073 dev->id[c][i].devsp = 0xce;
3074#ifdef ED_DBGP
3075 printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp);
3076#endif
3077 continue;
3078 }
3079chg_wide:
e2c22b45
OZ		 3080 outb(0x01, wkport + 0x1b);
3081 outb(satn[0], wkport + 0x03);
3082 outb(satn[1], wkport + 0x04);
3083 outb(satn[2], wkport + 0x05);
3084 outb(satn[3], wkport + 0x06);
3085 outb(satn[4], wkport + 0x07);
3086 outb(satn[5], wkport + 0x08);
3087 outb(0, wkport + 0x0f);
3088 outb(dev->id[c][i].devsp, wkport + 0x11);
3089 outb(0, wkport + 0x12);
3090 outb(satn[6], wkport + 0x13);
3091 outb(satn[7], wkport + 0x14);
3092 outb(satn[8], wkport + 0x18);
3093
3094 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 3095 cpu_relax();
e2c22b45 3096 if ((inb(wkport + 0x17) != 0x11) && (inb(wkport + 0x17) != 0x8e)) {
1da177e4
LT		 3097 continue;
3098 }
e2c22b45 3099 while (inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 3100 cpu_relax();
3101try_wide:
3102 j = 0;
e2c22b45
OZ		 3103 outb(0x05, wkport + 0x14);
3104 outb(0x20, wkport + 0x18);
3105
3106 while ((inb(wkport + 0x1f) & 0x80) == 0) {
3107 if ((inb(wkport + 0x1f) & 0x01) != 0)
3108 outb(wide[j++], wkport + 0x19);
1da177e4
LT		 3109 cpu_relax();
3110 }
e2c22b45 3111 while ((inb(wkport + 0x17) & 0x80) == 0x00)
1da177e4 3112 cpu_relax();
e2c22b45 3113 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 3114 if (j == 0x0f) {
3115 goto widep_in;
3116 }
3117 if (j == 0x0a) {
3118 goto widep_cmd;
3119 }
3120 if (j == 0x0e) {
3121 goto try_wide;
3122 }
3123 continue;
3124widep_out:
e2c22b45
OZ		 3125 outb(0x20, wkport + 0x18);
3126 while ((inb(wkport + 0x1f) & 0x80) == 0) {
3127 if ((inb(wkport + 0x1f) & 0x01) != 0)
3128 outb(0, wkport + 0x19);
1da177e4
LT		 3129 cpu_relax();
3130 }
e2c22b45 3131 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 3132 if (j == 0x0f) {
3133 goto widep_in;
3134 }
3135 if (j == 0x0a) {
3136 goto widep_cmd;
3137 }
3138 if (j == 0x0e) {
3139 goto widep_out;
3140 }
3141 continue;
3142widep_in:
e2c22b45
OZ		 3143 outb(0xff, wkport + 0x14);
3144 outb(0x20, wkport + 0x18);
1da177e4
LT		 3145 k = 0;
3146widep_in1:
e2c22b45 3147 j = inb(wkport + 0x1f);
1da177e4 3148 if ((j & 0x01) != 0) {
e2c22b45 3149 mbuf[k++] = inb(wkport + 0x19);
1da177e4
LT		 3150 goto widep_in1;
3151 }
3152 if ((j & 0x80) == 0x00) {
3153 goto widep_in1;
3154 }
e2c22b45 3155 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 3156 if (j == 0x0f) {
3157 goto widep_in;
3158 }
3159 if (j == 0x0a) {
3160 goto widep_cmd;
3161 }
3162 if (j == 0x0e) {
3163 goto widep_out;
3164 }
3165 continue;
3166widep_cmd:
e2c22b45
OZ		 3167 outb(0x30, wkport + 0x10);
3168 outb(0x00, wkport + 0x14);
3169 outb(0x08, wkport + 0x18);
3170 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 3171 cpu_relax();
e2c22b45 3172 j = inb(wkport + 0x17);
1da177e4
LT		 3173 if (j != 0x16) {
3174 if (j == 0x4e) {
3175 goto widep_out;
3176 }
3177 continue;
3178 }
3179 if (mbuf[0] != 0x01) {
3180 goto not_wide;
3181 }
3182 if (mbuf[1] != 0x02) {
3183 goto not_wide;
3184 }
3185 if (mbuf[2] != 0x03) {
3186 goto not_wide;
3187 }
3188 if (mbuf[3] != 0x01) {
3189 goto not_wide;
3190 }
3191 m = 1;
3192 m = m << i;
3193 dev->wide_id[c] |= m;
3194not_wide:
3195 if ((dev->id[c][i].devtype == 0x00) || (dev->id[c][i].devtype == 0x07) ||
3196 ((dev->id[c][i].devtype == 0x05) && ((n & 0x10) != 0))) {
3197 m = 1;
3198 m = m << i;
3199 if ((dev->async[c] & m) != 0) {
3200 goto set_sync;
3201 }
3202 }
3203 continue;
3204set_sync:
3205 if (dev->sp[c][i] == 0x02) {
3206 synu[4]=0x0c;
3207 synuw[4]=0x0c;
3208 } else {
3209 if (dev->sp[c][i] >= 0x03) {
3210 synu[4]=0x0a;
3211 synuw[4]=0x0a;
3212 }
3213 }
1da177e4
LT		 3214 j = 0;
3215 if ((m & dev->wide_id[c]) != 0) {
3216 j |= 0x01;
3217 }
e2c22b45
OZ		 3218 outb(j, wkport + 0x1b);
3219 outb(satn[0], wkport + 0x03);
3220 outb(satn[1], wkport + 0x04);
3221 outb(satn[2], wkport + 0x05);
3222 outb(satn[3], wkport + 0x06);
3223 outb(satn[4], wkport + 0x07);
3224 outb(satn[5], wkport + 0x08);
3225 outb(0, wkport + 0x0f);
3226 outb(dev->id[c][i].devsp, wkport + 0x11);
3227 outb(0, wkport + 0x12);
3228 outb(satn[6], wkport + 0x13);
3229 outb(satn[7], wkport + 0x14);
3230 outb(satn[8], wkport + 0x18);
3231
3232 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 3233 cpu_relax();
e2c22b45 3234 if ((inb(wkport + 0x17) != 0x11) && (inb(wkport + 0x17) != 0x8e)) {
1da177e4
LT		 3235 continue;
3236 }
e2c22b45 3237 while (inb(wkport + 0x17) != 0x8e)
1da177e4
LT		 3238 cpu_relax();
3239try_sync:
3240 j = 0;
e2c22b45
OZ		 3241 outb(0x06, wkport + 0x14);
3242 outb(0x20, wkport + 0x18);
3243
3244 while ((inb(wkport + 0x1f) & 0x80) == 0) {
3245 if ((inb(wkport + 0x1f) & 0x01) != 0) {
1da177e4
LT		 3246 if ((m & dev->wide_id[c]) != 0) {
3247 if ((m & dev->ultra_map[c]) != 0) {
e2c22b45 3248 outb(synuw[j++], wkport + 0x19);
1da177e4 3249 } else {
e2c22b45 3250 outb(synw[j++], wkport + 0x19);
1da177e4
LT		 3251 }
3252 } else {
3253 if ((m & dev->ultra_map[c]) != 0) {
e2c22b45 3254 outb(synu[j++], wkport + 0x19);
1da177e4 3255 } else {
e2c22b45 3256 outb(synn[j++], wkport + 0x19);
1da177e4
LT		 3257 }
3258 }
1da177e4
LT		 3259 }
3260 }
e2c22b45 3261 while ((inb(wkport + 0x17) & 0x80) == 0x00)
1da177e4 3262 cpu_relax();
e2c22b45 3263 j = inb(wkport + 0x17) & 0x0f;
1da177e4
LT		 3264 if (j == 0x0f) {
3265 goto phase_ins;
3266 }
3267 if (j == 0x0a) {
3268 goto phase_cmds;
3269 }
3270 if (j == 0x0e) {
3271 goto try_sync;
3272 }
3273 continue;
3274phase_outs:
e2c22b45
OZ		 3275 outb(0x20, wkport + 0x18);
3276 while ((inb(wkport + 0x1f) & 0x80) == 0x00) {
3277 if ((inb(wkport + 0x1f) & 0x01) != 0x00)
3278 outb(0x00, wkport + 0x19);
1da177e4
LT		 3279 cpu_relax();
3280 }
e2c22b45 3281 j = inb(wkport + 0x17);
1da177e4
LT		 3282 if (j == 0x85) {
3283 goto tar_dcons;
3284 }
3285 j &= 0x0f;
3286 if (j == 0x0f) {
3287 goto phase_ins;
3288 }
3289 if (j == 0x0a) {
3290 goto phase_cmds;
3291 }
3292 if (j == 0x0e) {
3293 goto phase_outs;
3294 }
3295 continue;
3296phase_ins:
e2c22b45
OZ		 3297 outb(0x06, wkport + 0x14);
3298 outb(0x20, wkport + 0x18);
1da177e4
LT		 3299 k = 0;
3300phase_ins1:
e2c22b45 3301 j = inb(wkport + 0x1f);
1da177e4 3302 if ((j & 0x01) != 0x00) {
e2c22b45 3303 mbuf[k++] = inb(wkport + 0x19);
1da177e4
LT		 3304 goto phase_ins1;
3305 }
3306 if ((j & 0x80) == 0x00) {
3307 goto phase_ins1;
3308 }
e2c22b45
OZ		 3309 while ((inb(wkport + 0x17) & 0x80) == 0x00);
3310 j = inb(wkport + 0x17);
1da177e4
LT		 3311 if (j == 0x85) {
3312 goto tar_dcons;
3313 }
3314 j &= 0x0f;
3315 if (j == 0x0f) {
3316 goto phase_ins;
3317 }
3318 if (j == 0x0a) {
3319 goto phase_cmds;
3320 }
3321 if (j == 0x0e) {
3322 goto phase_outs;
3323 }
3324 continue;
3325phase_cmds:
e2c22b45 3326 outb(0x30, wkport + 0x10);
1da177e4 3327tar_dcons:
e2c22b45
OZ		 3328 outb(0x00, wkport + 0x14);
3329 outb(0x08, wkport + 0x18);
3330 while ((inb(wkport + 0x1f) & 0x80) == 0x00)
1da177e4 3331 cpu_relax();
e2c22b45 3332 j = inb(wkport + 0x17);
1da177e4
LT		 3333 if (j != 0x16) {
3334 continue;
3335 }
3336 if (mbuf[0] != 0x01) {
3337 continue;
3338 }
3339 if (mbuf[1] != 0x03) {
3340 continue;
3341 }
3342 if (mbuf[4] == 0x00) {
3343 continue;
3344 }
3345 if (mbuf[3] > 0x64) {
3346 continue;
3347 }
3348 if (mbuf[4] > 0x0e) {
3349 mbuf[4] = 0x0e;
3350 }
3351 dev->id[c][i].devsp = mbuf[4];
3352 if (mbuf[3] < 0x0c){
3353 j = 0xb0;
3354 goto set_syn_ok;
3355 }
3356 if ((mbuf[3] < 0x0d) && (rmb == 0)) {
3357 j = 0xa0;
3358 goto set_syn_ok;
3359 }
3360 if (mbuf[3] < 0x1a) {
3361 j = 0x20;
3362 goto set_syn_ok;
3363 }
3364 if (mbuf[3] < 0x33) {
3365 j = 0x40;
3366 goto set_syn_ok;
3367 }
3368 if (mbuf[3] < 0x4c) {
3369 j = 0x50;
3370 goto set_syn_ok;
3371 }
3372 j = 0x60;
3373 set_syn_ok:
3374 dev->id[c][i].devsp = (dev->id[c][i].devsp & 0x0f) | j;
3375#ifdef ED_DBGP
3376 printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp);
3377#endif
3378 }
e2c22b45 3379 outb(0x80, wkport + 0x16);
1da177e4
LT		 3380}
3381
3382module_init(atp870u_init);
3383module_exit(atp870u_exit);
3384
Linux kernel - Deliverables
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