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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / scsi / be2iscsi / be_cmds.c
CommitLineData
6733b39a 1/**
255fa9a3 2 * Copyright (C) 2005 - 2011 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
255fa9a3 11 * linux-drivers@emulex.com
6733b39a 12 *
255fa9a3
JK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6733b39a
JK		 16 */
17
2177199d
JSJ		 18#include <scsi/iscsi_proto.h>
19
6733b39a
JK		 20#include "be.h"
21#include "be_mgmt.h"
22#include "be_main.h"
23
e9b91193
JK		 24int beiscsi_pci_soft_reset(struct beiscsi_hba *phba)
25{
26 u32 sreset;
27 u8 *pci_reset_offset = 0;
28 u8 *pci_online0_offset = 0;
29 u8 *pci_online1_offset = 0;
30 u32 pconline0 = 0;
31 u32 pconline1 = 0;
32 u32 i;
33
34 pci_reset_offset = (u8 *)phba->pci_va + BE2_SOFT_RESET;
35 pci_online0_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE0;
36 pci_online1_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE1;
37 sreset = readl((void *)pci_reset_offset);
38 sreset |= BE2_SET_RESET;
39 writel(sreset, (void *)pci_reset_offset);
40
41 i = 0;
42 while (sreset & BE2_SET_RESET) {
43 if (i > 64)
44 break;
45 msleep(100);
46 sreset = readl((void *)pci_reset_offset);
47 i++;
48 }
49
50 if (sreset & BE2_SET_RESET) {
51 printk(KERN_ERR "Soft Reset did not deassert\n");
52 return -EIO;
53 }
54 pconline1 = BE2_MPU_IRAM_ONLINE;
55 writel(pconline0, (void *)pci_online0_offset);
56 writel(pconline1, (void *)pci_online1_offset);
57
58 sreset = BE2_SET_RESET;
59 writel(sreset, (void *)pci_reset_offset);
60
61 i = 0;
62 while (sreset & BE2_SET_RESET) {
63 if (i > 64)
64 break;
65 msleep(1);
66 sreset = readl((void *)pci_reset_offset);
67 i++;
68 }
69 if (sreset & BE2_SET_RESET) {
70 printk(KERN_ERR "MPU Online Soft Reset did not deassert\n");
71 return -EIO;
72 }
73 return 0;
74}
75
76int be_chk_reset_complete(struct beiscsi_hba *phba)
77{
78 unsigned int num_loop;
79 u8 *mpu_sem = 0;
80 u32 status;
81
82 num_loop = 1000;
83 mpu_sem = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
84 msleep(5000);
85
86 while (num_loop) {
87 status = readl((void *)mpu_sem);
88
89 if ((status & 0x80000000) || (status & 0x0000FFFF) == 0xC000)
90 break;
91 msleep(60);
92 num_loop--;
93 }
94
95 if ((status & 0x80000000) || (!num_loop)) {
96 printk(KERN_ERR "Failed in be_chk_reset_complete"
97 "status = 0x%x\n", status);
98 return -EIO;
99 }
100
101 return 0;
102}
103
756d29c8 104void be_mcc_notify(struct beiscsi_hba *phba)
bfead3b2
JK		 105{
106 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
107 u32 val = 0;
108
109 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
110 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
111 iowrite32(val, phba->db_va + DB_MCCQ_OFFSET);
112}
113
756d29c8
JK		 114unsigned int alloc_mcc_tag(struct beiscsi_hba *phba)
115{
116 unsigned int tag = 0;
756d29c8 117
756d29c8
JK		 118 if (phba->ctrl.mcc_tag_available) {
119 tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index];
120 phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0;
121 phba->ctrl.mcc_numtag[tag] = 0;
756d29c8
JK		 122 }
123 if (tag) {
124 phba->ctrl.mcc_tag_available--;
125 if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1))
126 phba->ctrl.mcc_alloc_index = 0;
127 else
128 phba->ctrl.mcc_alloc_index++;
129 }
130 return tag;
131}
132
133void free_mcc_tag(struct be_ctrl_info *ctrl, unsigned int tag)
134{
135 spin_lock(&ctrl->mbox_lock);
136 tag = tag & 0x000000FF;
137 ctrl->mcc_tag[ctrl->mcc_free_index] = tag;
138 if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1))
139 ctrl->mcc_free_index = 0;
140 else
141 ctrl->mcc_free_index++;
142 ctrl->mcc_tag_available++;
143 spin_unlock(&ctrl->mbox_lock);
144}
145
146bool is_link_state_evt(u32 trailer)
147{
148 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
149 ASYNC_TRAILER_EVENT_CODE_MASK) ==
150 ASYNC_EVENT_CODE_LINK_STATE);
151}
152
6733b39a
JK		 153static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
154{
155 if (compl->flags != 0) {
156 compl->flags = le32_to_cpu(compl->flags);
157 WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
158 return true;
159 } else
160 return false;
161}
162
163static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
164{
165 compl->flags = 0;
166}
167
168static int be_mcc_compl_process(struct be_ctrl_info *ctrl,
169 struct be_mcc_compl *compl)
170{
171 u16 compl_status, extd_status;
172
173 be_dws_le_to_cpu(compl, 4);
174
175 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
176 CQE_STATUS_COMPL_MASK;
177 if (compl_status != MCC_STATUS_SUCCESS) {
178 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
179 CQE_STATUS_EXTD_MASK;
180 dev_err(&ctrl->pdev->dev,
181 "error in cmd completion: status(compl/extd)=%d/%d\n",
182 compl_status, extd_status);
d3ad2bb3 183 return -EBUSY;
6733b39a
JK		 184 }
185 return 0;
186}
187
756d29c8
JK		 188int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl,
189 struct be_mcc_compl *compl)
6733b39a 190{
756d29c8
JK		 191 u16 compl_status, extd_status;
192 unsigned short tag;
193
194 be_dws_le_to_cpu(compl, 4);
195
196 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
197 CQE_STATUS_COMPL_MASK;
198 /* The ctrl.mcc_numtag[tag] is filled with
199 * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status,
200 * [7:0] = compl_status
201 */
202 tag = (compl->tag0 & 0x000000FF);
203 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
204 CQE_STATUS_EXTD_MASK;
205
206 ctrl->mcc_numtag[tag] = 0x80000000;
207 ctrl->mcc_numtag[tag] |= (compl->tag0 & 0x00FF0000);
208 ctrl->mcc_numtag[tag] |= (extd_status & 0x000000FF) << 8;
209 ctrl->mcc_numtag[tag] |= (compl_status & 0x000000FF);
210 wake_up_interruptible(&ctrl->mcc_wait[tag]);
211 return 0;
bfead3b2
JK		 212}
213
214static struct be_mcc_compl *be_mcc_compl_get(struct beiscsi_hba *phba)
215{
216 struct be_queue_info *mcc_cq = &phba->ctrl.mcc_obj.cq;
217 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
218
219 if (be_mcc_compl_is_new(compl)) {
220 queue_tail_inc(mcc_cq);
221 return compl;
222 }
223 return NULL;
224}
225
226static void be2iscsi_fail_session(struct iscsi_cls_session *cls_session)
227{
228 iscsi_session_failure(cls_session->dd_data, ISCSI_ERR_CONN_FAILED);
229}
230
756d29c8 231void beiscsi_async_link_state_process(struct beiscsi_hba *phba,
bfead3b2
JK		 232 struct be_async_event_link_state *evt)
233{
234 switch (evt->port_link_status) {
235 case ASYNC_EVENT_LINK_DOWN:
457ff3b7
JK		 236 SE_DEBUG(DBG_LVL_1, "Link Down on Physical Port %d\n",
237 evt->physical_port);
bfead3b2 238 phba->state |= BE_ADAPTER_LINK_DOWN;
da7408c8
JK		 239 iscsi_host_for_each_session(phba->shost,
240 be2iscsi_fail_session);
bfead3b2
JK		 241 break;
242 case ASYNC_EVENT_LINK_UP:
243 phba->state = BE_ADAPTER_UP;
457ff3b7 244 SE_DEBUG(DBG_LVL_1, "Link UP on Physical Port %d\n",
bfead3b2 245 evt->physical_port);
bfead3b2
JK		 246 break;
247 default:
248 SE_DEBUG(DBG_LVL_1, "Unexpected Async Notification %d on"
457ff3b7 249 "Physical Port %d\n",
bfead3b2
JK		 250 evt->port_link_status,
251 evt->physical_port);
252 }
6733b39a
JK		 253}
254
bfead3b2 255static void beiscsi_cq_notify(struct beiscsi_hba *phba, u16 qid, bool arm,
6733b39a
JK		 256 u16 num_popped)
257{
258 u32 val = 0;
259 val |= qid & DB_CQ_RING_ID_MASK;
260 if (arm)
261 val |= 1 << DB_CQ_REARM_SHIFT;
262 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
bfead3b2
JK		 263 iowrite32(val, phba->db_va + DB_CQ_OFFSET);
264}
265
266
35e66019 267int beiscsi_process_mcc(struct beiscsi_hba *phba)
bfead3b2
JK		 268{
269 struct be_mcc_compl *compl;
270 int num = 0, status = 0;
271 struct be_ctrl_info *ctrl = &phba->ctrl;
272
273 spin_lock_bh(&phba->ctrl.mcc_cq_lock);
274 while ((compl = be_mcc_compl_get(phba))) {
275 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
276 /* Interpret flags as an async trailer */
78b9fb6d
JK		 277 if (is_link_state_evt(compl->flags))
278 /* Interpret compl as a async link evt */
279 beiscsi_async_link_state_process(phba,
280 (struct be_async_event_link_state *) compl);
281 else
282 SE_DEBUG(DBG_LVL_1,
283 " Unsupported Async Event, flags"
457ff3b7 284 " = 0x%08x\n", compl->flags);
bfead3b2 285
bfead3b2
JK		 286 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
287 status = be_mcc_compl_process(ctrl, compl);
288 atomic_dec(&phba->ctrl.mcc_obj.q.used);
289 }
290 be_mcc_compl_use(compl);
291 num++;
292 }
293
294 if (num)
295 beiscsi_cq_notify(phba, phba->ctrl.mcc_obj.cq.id, true, num);
296
297 spin_unlock_bh(&phba->ctrl.mcc_cq_lock);
298 return status;
299}
300
301/* Wait till no more pending mcc requests are present */
302static int be_mcc_wait_compl(struct beiscsi_hba *phba)
303{
bfead3b2
JK		 304 int i, status;
305 for (i = 0; i < mcc_timeout; i++) {
35e66019 306 status = beiscsi_process_mcc(phba);
bfead3b2
JK		 307 if (status)
308 return status;
309
310 if (atomic_read(&phba->ctrl.mcc_obj.q.used) == 0)
311 break;
312 udelay(100);
313 }
314 if (i == mcc_timeout) {
315 dev_err(&phba->pcidev->dev, "mccq poll timed out\n");
d3ad2bb3 316 return -EBUSY;
bfead3b2
JK		 317 }
318 return 0;
319}
320
321/* Notify MCC requests and wait for completion */
322int be_mcc_notify_wait(struct beiscsi_hba *phba)
323{
324 be_mcc_notify(phba);
325 return be_mcc_wait_compl(phba);
6733b39a
JK		 326}
327
328static int be_mbox_db_ready_wait(struct be_ctrl_info *ctrl)
329{
330#define long_delay 2000
331 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
332 int cnt = 0, wait = 5; /* in usecs */
333 u32 ready;
334
335 do {
336 ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK;
337 if (ready)
338 break;
339
91446f06 340 if (cnt > 12000000) {
6733b39a 341 dev_err(&ctrl->pdev->dev, "mbox_db poll timed out\n");
d3ad2bb3 342 return -EBUSY;
6733b39a
JK		 343 }
344
345 if (cnt > 50) {
346 wait = long_delay;
347 mdelay(long_delay / 1000);
348 } else
349 udelay(wait);
350 cnt += wait;
351 } while (true);
352 return 0;
353}
354
355int be_mbox_notify(struct be_ctrl_info *ctrl)
356{
357 int status;
358 u32 val = 0;
359 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
360 struct be_dma_mem *mbox_mem = &ctrl->mbox_mem;
361 struct be_mcc_mailbox *mbox = mbox_mem->va;
362 struct be_mcc_compl *compl = &mbox->compl;
363
364 val &= ~MPU_MAILBOX_DB_RDY_MASK;
365 val |= MPU_MAILBOX_DB_HI_MASK;
366 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
367 iowrite32(val, db);
368
369 status = be_mbox_db_ready_wait(ctrl);
370 if (status != 0) {
457ff3b7 371 SE_DEBUG(DBG_LVL_1, " be_mbox_db_ready_wait failed\n");
6733b39a
JK		 372 return status;
373 }
374 val = 0;
375 val &= ~MPU_MAILBOX_DB_RDY_MASK;
376 val &= ~MPU_MAILBOX_DB_HI_MASK;
377 val |= (u32) (mbox_mem->dma >> 4) << 2;
378 iowrite32(val, db);
379
380 status = be_mbox_db_ready_wait(ctrl);
381 if (status != 0) {
457ff3b7 382 SE_DEBUG(DBG_LVL_1, " be_mbox_db_ready_wait failed\n");
6733b39a
JK		 383 return status;
384 }
385 if (be_mcc_compl_is_new(compl)) {
386 status = be_mcc_compl_process(ctrl, &mbox->compl);
387 be_mcc_compl_use(compl);
388 if (status) {
457ff3b7 389 SE_DEBUG(DBG_LVL_1, "After be_mcc_compl_process\n");
6733b39a
JK		 390 return status;
391 }
392 } else {
393 dev_err(&ctrl->pdev->dev, "invalid mailbox completion\n");
d3ad2bb3 394 return -EBUSY;
6733b39a
JK		 395 }
396 return 0;
397}
398
bfead3b2
JK		 399/*
400 * Insert the mailbox address into the doorbell in two steps
401 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
402 */
403static int be_mbox_notify_wait(struct beiscsi_hba *phba)
404{
405 int status;
406 u32 val = 0;
407 void __iomem *db = phba->ctrl.db + MPU_MAILBOX_DB_OFFSET;
408 struct be_dma_mem *mbox_mem = &phba->ctrl.mbox_mem;
409 struct be_mcc_mailbox *mbox = mbox_mem->va;
410 struct be_mcc_compl *compl = &mbox->compl;
411 struct be_ctrl_info *ctrl = &phba->ctrl;
412
413 val |= MPU_MAILBOX_DB_HI_MASK;
414 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
415 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
416 iowrite32(val, db);
417
418 /* wait for ready to be set */
419 status = be_mbox_db_ready_wait(ctrl);
420 if (status != 0)
421 return status;
422
423 val = 0;
424 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
425 val |= (u32)(mbox_mem->dma >> 4) << 2;
426 iowrite32(val, db);
427
428 status = be_mbox_db_ready_wait(ctrl);
429 if (status != 0)
430 return status;
431
432 /* A cq entry has been made now */
433 if (be_mcc_compl_is_new(compl)) {
434 status = be_mcc_compl_process(ctrl, &mbox->compl);
435 be_mcc_compl_use(compl);
436 if (status)
437 return status;
438 } else {
439 dev_err(&phba->pcidev->dev, "invalid mailbox completion\n");
d3ad2bb3 440 return -EBUSY;
bfead3b2
JK		 441 }
442 return 0;
443}
444
6733b39a
JK		 445void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
446 bool embedded, u8 sge_cnt)
447{
448 if (embedded)
449 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
450 else
451 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
452 MCC_WRB_SGE_CNT_SHIFT;
453 wrb->payload_length = payload_len;
454 be_dws_cpu_to_le(wrb, 8);
455}
456
457void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
458 u8 subsystem, u8 opcode, int cmd_len)
459{
460 req_hdr->opcode = opcode;
461 req_hdr->subsystem = subsystem;
462 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
91eefa89 463 req_hdr->timeout = 120;
6733b39a
JK		 464}
465
466static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
467 struct be_dma_mem *mem)
468{
469 int i, buf_pages;
470 u64 dma = (u64) mem->dma;
471
472 buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
473 for (i = 0; i < buf_pages; i++) {
474 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
475 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
476 dma += PAGE_SIZE_4K;
477 }
478}
479
480static u32 eq_delay_to_mult(u32 usec_delay)
481{
482#define MAX_INTR_RATE 651042
483 const u32 round = 10;
484 u32 multiplier;
485
486 if (usec_delay == 0)
487 multiplier = 0;
488 else {
489 u32 interrupt_rate = 1000000 / usec_delay;
490 if (interrupt_rate == 0)
491 multiplier = 1023;
492 else {
493 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
494 multiplier /= interrupt_rate;
495 multiplier = (multiplier + round / 2) / round;
496 multiplier = min(multiplier, (u32) 1023);
497 }
498 }
499 return multiplier;
500}
501
502struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
503{
504 return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
505}
506
bfead3b2
JK		 507struct be_mcc_wrb *wrb_from_mccq(struct beiscsi_hba *phba)
508{
509 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
510 struct be_mcc_wrb *wrb;
511
512 BUG_ON(atomic_read(&mccq->used) >= mccq->len);
513 wrb = queue_head_node(mccq);
756d29c8
JK		 514 memset(wrb, 0, sizeof(*wrb));
515 wrb->tag0 = (mccq->head & 0x000000FF) << 16;
bfead3b2
JK		 516 queue_head_inc(mccq);
517 atomic_inc(&mccq->used);
bfead3b2
JK		 518 return wrb;
519}
520
521
6733b39a
JK		 522int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
523 struct be_queue_info *eq, int eq_delay)
524{
525 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
526 struct be_cmd_req_eq_create *req = embedded_payload(wrb);
527 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
528 struct be_dma_mem *q_mem = &eq->dma_mem;
529 int status;
530
bfead3b2 531 SE_DEBUG(DBG_LVL_8, "In beiscsi_cmd_eq_create\n");
6733b39a
JK		 532 spin_lock(&ctrl->mbox_lock);
533 memset(wrb, 0, sizeof(*wrb));
534
535 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
536
537 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
538 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
539
540 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
541
542 AMAP_SET_BITS(struct amap_eq_context, func, req->context,
543 PCI_FUNC(ctrl->pdev->devfn));
544 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
545 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
546 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
547 __ilog2_u32(eq->len / 256));
548 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
549 eq_delay_to_mult(eq_delay));
550 be_dws_cpu_to_le(req->context, sizeof(req->context));
551
552 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
553
554 status = be_mbox_notify(ctrl);
555 if (!status) {
556 eq->id = le16_to_cpu(resp->eq_id);
557 eq->created = true;
558 }
559 spin_unlock(&ctrl->mbox_lock);
560 return status;
561}
562
563int be_cmd_fw_initialize(struct be_ctrl_info *ctrl)
564{
565 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
566 int status;
567 u8 *endian_check;
568
bfead3b2 569 SE_DEBUG(DBG_LVL_8, "In be_cmd_fw_initialize\n");
6733b39a
JK		 570 spin_lock(&ctrl->mbox_lock);
571 memset(wrb, 0, sizeof(*wrb));
572
573 endian_check = (u8 *) wrb;
574 *endian_check++ = 0xFF;
575 *endian_check++ = 0x12;
576 *endian_check++ = 0x34;
577 *endian_check++ = 0xFF;
578 *endian_check++ = 0xFF;
579 *endian_check++ = 0x56;
580 *endian_check++ = 0x78;
581 *endian_check++ = 0xFF;
582 be_dws_cpu_to_le(wrb, sizeof(*wrb));
583
584 status = be_mbox_notify(ctrl);
585 if (status)
457ff3b7 586 SE_DEBUG(DBG_LVL_1, "be_cmd_fw_initialize Failed\n");
6733b39a
JK		 587
588 spin_unlock(&ctrl->mbox_lock);
589 return status;
590}
591
592int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
593 struct be_queue_info *cq, struct be_queue_info *eq,
594 bool sol_evts, bool no_delay, int coalesce_wm)
595{
596 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
597 struct be_cmd_req_cq_create *req = embedded_payload(wrb);
598 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
599 struct be_dma_mem *q_mem = &cq->dma_mem;
600 void *ctxt = &req->context;
601 int status;
602
457ff3b7 603 SE_DEBUG(DBG_LVL_8, "In beiscsi_cmd_cq_create\n");
6733b39a
JK		 604 spin_lock(&ctrl->mbox_lock);
605 memset(wrb, 0, sizeof(*wrb));
606
607 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
608
609 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
610 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
6733b39a
JK		 611 if (!q_mem->va)
612 SE_DEBUG(DBG_LVL_1, "uninitialized q_mem->va\n");
613
614 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
615
616 AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
617 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
618 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
619 __ilog2_u32(cq->len / 256));
620 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
621 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
622 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
623 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
624 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
625 AMAP_SET_BITS(struct amap_cq_context, func, ctxt,
626 PCI_FUNC(ctrl->pdev->devfn));
627 be_dws_cpu_to_le(ctxt, sizeof(req->context));
628
629 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
630
631 status = be_mbox_notify(ctrl);
632 if (!status) {
633 cq->id = le16_to_cpu(resp->cq_id);
634 cq->created = true;
635 } else
457ff3b7 636 SE_DEBUG(DBG_LVL_1, "In be_cmd_cq_create, status=ox%08x\n",
6733b39a
JK		 637 status);
638 spin_unlock(&ctrl->mbox_lock);
639
640 return status;
641}
642
643static u32 be_encoded_q_len(int q_len)
644{
645 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
646 if (len_encoded == 16)
647 len_encoded = 0;
648 return len_encoded;
649}
bfead3b2 650
35e66019 651int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba,
bfead3b2
JK		 652 struct be_queue_info *mccq,
653 struct be_queue_info *cq)
654{
655 struct be_mcc_wrb *wrb;
656 struct be_cmd_req_mcc_create *req;
657 struct be_dma_mem *q_mem = &mccq->dma_mem;
658 struct be_ctrl_info *ctrl;
659 void *ctxt;
660 int status;
661
662 spin_lock(&phba->ctrl.mbox_lock);
663 ctrl = &phba->ctrl;
664 wrb = wrb_from_mbox(&ctrl->mbox_mem);
37609766 665 memset(wrb, 0, sizeof(*wrb));
bfead3b2
JK		 666 req = embedded_payload(wrb);
667 ctxt = &req->context;
668
669 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
670
671 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
672 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
673
674 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
675
676 AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt,
677 PCI_FUNC(phba->pcidev->devfn));
678 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
679 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
680 be_encoded_q_len(mccq->len));
681 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
682
683 be_dws_cpu_to_le(ctxt, sizeof(req->context));
684
685 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
686
687 status = be_mbox_notify_wait(phba);
688 if (!status) {
689 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
690 mccq->id = le16_to_cpu(resp->id);
691 mccq->created = true;
692 }
693 spin_unlock(&phba->ctrl.mbox_lock);
694
695 return status;
696}
697
6733b39a
JK		 698int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
699 int queue_type)
700{
701 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
702 struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
703 u8 subsys = 0, opcode = 0;
704 int status;
705
457ff3b7 706 SE_DEBUG(DBG_LVL_8, "In beiscsi_cmd_q_destroy\n");
6733b39a
JK		 707 spin_lock(&ctrl->mbox_lock);
708 memset(wrb, 0, sizeof(*wrb));
709 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
710
711 switch (queue_type) {
712 case QTYPE_EQ:
713 subsys = CMD_SUBSYSTEM_COMMON;
714 opcode = OPCODE_COMMON_EQ_DESTROY;
715 break;
716 case QTYPE_CQ:
717 subsys = CMD_SUBSYSTEM_COMMON;
718 opcode = OPCODE_COMMON_CQ_DESTROY;
719 break;
bfead3b2
JK		 720 case QTYPE_MCCQ:
721 subsys = CMD_SUBSYSTEM_COMMON;
722 opcode = OPCODE_COMMON_MCC_DESTROY;
723 break;
6733b39a
JK		 724 case QTYPE_WRBQ:
725 subsys = CMD_SUBSYSTEM_ISCSI;
726 opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY;
727 break;
728 case QTYPE_DPDUQ:
729 subsys = CMD_SUBSYSTEM_ISCSI;
730 opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY;
731 break;
732 case QTYPE_SGL:
733 subsys = CMD_SUBSYSTEM_ISCSI;
734 opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES;
735 break;
736 default:
737 spin_unlock(&ctrl->mbox_lock);
738 BUG();
d3ad2bb3 739 return -ENXIO;
6733b39a
JK		 740 }
741 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
742 if (queue_type != QTYPE_SGL)
743 req->id = cpu_to_le16(q->id);
744
745 status = be_mbox_notify(ctrl);
746
747 spin_unlock(&ctrl->mbox_lock);
748 return status;
749}
750
6733b39a
JK		 751int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl,
752 struct be_queue_info *cq,
753 struct be_queue_info *dq, int length,
754 int entry_size)
755{
756 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
757 struct be_defq_create_req *req = embedded_payload(wrb);
758 struct be_dma_mem *q_mem = &dq->dma_mem;
759 void *ctxt = &req->context;
760 int status;
761
bfead3b2 762 SE_DEBUG(DBG_LVL_8, "In be_cmd_create_default_pdu_queue\n");
6733b39a
JK		 763 spin_lock(&ctrl->mbox_lock);
764 memset(wrb, 0, sizeof(*wrb));
765
766 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
767
768 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
769 OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req));
770
771 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
772 AMAP_SET_BITS(struct amap_be_default_pdu_context, rx_pdid, ctxt, 0);
773 AMAP_SET_BITS(struct amap_be_default_pdu_context, rx_pdid_valid, ctxt,
774 1);
775 AMAP_SET_BITS(struct amap_be_default_pdu_context, pci_func_id, ctxt,
776 PCI_FUNC(ctrl->pdev->devfn));
777 AMAP_SET_BITS(struct amap_be_default_pdu_context, ring_size, ctxt,
778 be_encoded_q_len(length / sizeof(struct phys_addr)));
779 AMAP_SET_BITS(struct amap_be_default_pdu_context, default_buffer_size,
780 ctxt, entry_size);
781 AMAP_SET_BITS(struct amap_be_default_pdu_context, cq_id_recv, ctxt,
782 cq->id);
783
784 be_dws_cpu_to_le(ctxt, sizeof(req->context));
785
786 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
787
788 status = be_mbox_notify(ctrl);
789 if (!status) {
790 struct be_defq_create_resp *resp = embedded_payload(wrb);
791
792 dq->id = le16_to_cpu(resp->id);
793 dq->created = true;
794 }
795 spin_unlock(&ctrl->mbox_lock);
796
797 return status;
798}
799
800int be_cmd_wrbq_create(struct be_ctrl_info *ctrl, struct be_dma_mem *q_mem,
801 struct be_queue_info *wrbq)
802{
803 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
804 struct be_wrbq_create_req *req = embedded_payload(wrb);
805 struct be_wrbq_create_resp *resp = embedded_payload(wrb);
806 int status;
807
808 spin_lock(&ctrl->mbox_lock);
809 memset(wrb, 0, sizeof(*wrb));
810
811 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
812
813 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
814 OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req));
815 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
816 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
817
818 status = be_mbox_notify(ctrl);
bfead3b2 819 if (!status) {
6733b39a 820 wrbq->id = le16_to_cpu(resp->cid);
bfead3b2
JK		 821 wrbq->created = true;
822 }
6733b39a
JK		 823 spin_unlock(&ctrl->mbox_lock);
824 return status;
825}
826
827int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl,
828 struct be_dma_mem *q_mem,
829 u32 page_offset, u32 num_pages)
830{
831 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
832 struct be_post_sgl_pages_req *req = embedded_payload(wrb);
833 int status;
834 unsigned int curr_pages;
835 u32 internal_page_offset = 0;
836 u32 temp_num_pages = num_pages;
837
838 if (num_pages == 0xff)
839 num_pages = 1;
840
841 spin_lock(&ctrl->mbox_lock);
842 do {
843 memset(wrb, 0, sizeof(*wrb));
844 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
845 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
846 OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES,
847 sizeof(*req));
848 curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req,
849 pages);
850 req->num_pages = min(num_pages, curr_pages);
851 req->page_offset = page_offset;
852 be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem);
853 q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE);
854 internal_page_offset += req->num_pages;
855 page_offset += req->num_pages;
856 num_pages -= req->num_pages;
857
858 if (temp_num_pages == 0xff)
859 req->num_pages = temp_num_pages;
860
861 status = be_mbox_notify(ctrl);
862 if (status) {
863 SE_DEBUG(DBG_LVL_1,
864 "FW CMD to map iscsi frags failed.\n");
865 goto error;
866 }
867 } while (num_pages > 0);
868error:
869 spin_unlock(&ctrl->mbox_lock);
870 if (status != 0)
871 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
872 return status;
873}
e5285860
JK		 874
875int beiscsi_cmd_reset_function(struct beiscsi_hba *phba)
876{
877 struct be_ctrl_info *ctrl = &phba->ctrl;
878 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
879 struct be_post_sgl_pages_req *req = embedded_payload(wrb);
880 int status;
881
882 spin_lock(&ctrl->mbox_lock);
883
884 req = embedded_payload(wrb);
885 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
886 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
887 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
888 status = be_mbox_notify_wait(phba);
889
890 spin_unlock(&ctrl->mbox_lock);
891 return status;
892}
Linux kernel - Deliverables
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