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6733b39a | 1 | /** |
4627de93 | 2 | * Copyright (C) 2005 - 2015 Avago Technologies |
6733b39a JK |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
4627de93 | 10 | * Written by: Jayamohan Kallickal (jayamohan.kallickal@avagotech.com) |
6733b39a JK |
11 | * |
12 | * Contact Information: | |
4627de93 | 13 | * linux-drivers@avagotech.com |
6733b39a | 14 | * |
4627de93 | 15 | * Avago Technologies |
255fa9a3 JK |
16 | * 3333 Susan Street |
17 | * Costa Mesa, CA 92626 | |
6733b39a JK |
18 | */ |
19 | ||
20 | #ifndef _BEISCSI_MAIN_ | |
21 | #define _BEISCSI_MAIN_ | |
22 | ||
6733b39a JK |
23 | #include <linux/kernel.h> |
24 | #include <linux/pci.h> | |
82c57028 | 25 | #include <linux/if_ether.h> |
6733b39a | 26 | #include <linux/in.h> |
99bc5d55 JSJ |
27 | #include <linux/ctype.h> |
28 | #include <linux/module.h> | |
3567f36a | 29 | #include <linux/aer.h> |
6733b39a JK |
30 | #include <scsi/scsi.h> |
31 | #include <scsi/scsi_cmnd.h> | |
32 | #include <scsi/scsi_device.h> | |
33 | #include <scsi/scsi_host.h> | |
34 | #include <scsi/iscsi_proto.h> | |
35 | #include <scsi/libiscsi.h> | |
36 | #include <scsi/scsi_transport_iscsi.h> | |
37 | ||
6733b39a | 38 | #define DRV_NAME "be2iscsi" |
d56dfb41 | 39 | #define BUILD_STR "10.6.0.0" |
4627de93 | 40 | #define BE_NAME "Avago Technologies OneConnect" \ |
2f635883 | 41 | "Open-iSCSI Driver version" BUILD_STR |
6733b39a JK |
42 | #define DRV_DESC BE_NAME " " "Driver" |
43 | ||
457ff3b7 | 44 | #define BE_VENDOR_ID 0x19A2 |
139a1b1e | 45 | #define ELX_VENDOR_ID 0x10DF |
f98c96b0 | 46 | /* DEVICE ID's for BE2 */ |
6733b39a JK |
47 | #define BE_DEVICE_ID1 0x212 |
48 | #define OC_DEVICE_ID1 0x702 | |
49 | #define OC_DEVICE_ID2 0x703 | |
f98c96b0 JK |
50 | |
51 | /* DEVICE ID's for BE3 */ | |
52 | #define BE_DEVICE_ID2 0x222 | |
bfead3b2 | 53 | #define OC_DEVICE_ID3 0x712 |
6733b39a | 54 | |
139a1b1e JSJ |
55 | /* DEVICE ID for SKH */ |
56 | #define OC_SKH_ID1 0x722 | |
57 | ||
7da50879 JK |
58 | #define BE2_IO_DEPTH 1024 |
59 | #define BE2_MAX_SESSIONS 256 | |
6733b39a | 60 | #define BE2_CMDS_PER_CXN 128 |
6733b39a JK |
61 | #define BE2_TMFS 16 |
62 | #define BE2_NOPOUT_REQ 16 | |
6733b39a JK |
63 | #define BE2_SGE 32 |
64 | #define BE2_DEFPDU_HDR_SZ 64 | |
65 | #define BE2_DEFPDU_DATA_SZ 8192 | |
6733b39a | 66 | |
22abeef0 JSJ |
67 | #define MAX_CPUS 64 |
68 | #define BEISCSI_MAX_NUM_CPUS 7 | |
22abeef0 | 69 | |
22661e25 | 70 | #define BEISCSI_VER_STRLEN 32 |
22abeef0 | 71 | |
aa359032 | 72 | #define BEISCSI_SGLIST_ELEMENTS 30 |
6733b39a | 73 | |
73af08e1 JK |
74 | #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */ |
75 | #define BEISCSI_MAX_SECTORS 1024 /* scsi_host->max_sectors */ | |
15a90fe0 | 76 | #define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */ |
6733b39a JK |
77 | |
78 | #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */ | |
79 | #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */ | |
80 | #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01 | |
81 | #define BEISCSI_MAX_FRAGS_INIT 192 | |
457ff3b7 | 82 | #define BE_NUM_MSIX_ENTRIES 1 |
e9b91193 JK |
83 | |
84 | #define MPU_EP_CONTROL 0 | |
85 | #define MPU_EP_SEMAPHORE 0xac | |
86 | #define BE2_SOFT_RESET 0x5c | |
87 | #define BE2_PCI_ONLINE0 0xb0 | |
88 | #define BE2_PCI_ONLINE1 0xb4 | |
89 | #define BE2_SET_RESET 0x80 | |
90 | #define BE2_MPU_IRAM_ONLINE 0x00000080 | |
6733b39a JK |
91 | |
92 | #define BE_SENSE_INFO_SIZE 258 | |
93 | #define BE_ISCSI_PDU_HEADER_SIZE 64 | |
94 | #define BE_MIN_MEM_SIZE 16384 | |
bfead3b2 | 95 | #define MAX_CMD_SZ 65536 |
6733b39a JK |
96 | #define IIOC_SCSI_DATA 0x05 /* Write Operation */ |
97 | ||
9aef4200 | 98 | #define INVALID_SESS_HANDLE 0xFFFFFFFF |
6733b39a | 99 | |
9343be74 JK |
100 | /** |
101 | * Adapter States | |
102 | **/ | |
3567f36a JK |
103 | #define BE_ADAPTER_LINK_UP 0x001 |
104 | #define BE_ADAPTER_LINK_DOWN 0x002 | |
105 | #define BE_ADAPTER_PCI_ERR 0x004 | |
9343be74 | 106 | #define BE_ADAPTER_STATE_SHUTDOWN 0x008 |
a3d313ea | 107 | #define BE_ADAPTER_CHECK_BOOT 0x010 |
9343be74 | 108 | |
3567f36a JK |
109 | |
110 | #define BEISCSI_CLEAN_UNLOAD 0x01 | |
111 | #define BEISCSI_EEH_UNLOAD 0x02 | |
3efde862 JSJ |
112 | |
113 | #define BE_GET_BOOT_RETRIES 45 | |
114 | #define BE_GET_BOOT_TO 20 | |
6733b39a JK |
115 | /** |
116 | * hardware needs the async PDU buffers to be posted in multiples of 8 | |
117 | * So have atleast 8 of them by default | |
118 | */ | |
119 | ||
8a86e833 JK |
120 | #define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num) \ |
121 | (phwi->phwi_ctxt->pasync_ctx[ulp_num]) | |
6733b39a JK |
122 | |
123 | /********* Memory BAR register ************/ | |
457ff3b7 | 124 | #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc |
6733b39a JK |
125 | /** |
126 | * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt | |
127 | * Disable" may still globally block interrupts in addition to individual | |
128 | * interrupt masks; a mechanism for the device driver to block all interrupts | |
129 | * atomically without having to arbitrate for the PCI Interrupt Disable bit | |
130 | * with the OS. | |
131 | */ | |
132 | #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */ | |
133 | ||
134 | /********* ISR0 Register offset **********/ | |
457ff3b7 | 135 | #define CEV_ISR0_OFFSET 0xC18 |
6733b39a JK |
136 | #define CEV_ISR_SIZE 4 |
137 | ||
138 | /** | |
139 | * Macros for reading/writing a protection domain or CSR registers | |
140 | * in BladeEngine. | |
141 | */ | |
142 | ||
143 | #define DB_TXULP0_OFFSET 0x40 | |
144 | #define DB_RXULP0_OFFSET 0xA0 | |
145 | /********* Event Q door bell *************/ | |
146 | #define DB_EQ_OFFSET DB_CQ_OFFSET | |
e08b3c8b | 147 | #define DB_EQ_RING_ID_LOW_MASK 0x1FF /* bits 0 - 8 */ |
6733b39a JK |
148 | /* Clear the interrupt for this eq */ |
149 | #define DB_EQ_CLR_SHIFT (9) /* bit 9 */ | |
150 | /* Must be 1 */ | |
151 | #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */ | |
e08b3c8b JK |
152 | /* Higher Order EQ_ID bit */ |
153 | #define DB_EQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */ | |
154 | #define DB_EQ_HIGH_SET_SHIFT 11 | |
155 | #define DB_EQ_HIGH_FEILD_SHIFT 9 | |
6733b39a JK |
156 | /* Number of event entries processed */ |
157 | #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ | |
158 | /* Rearm bit */ | |
159 | #define DB_EQ_REARM_SHIFT (29) /* bit 29 */ | |
160 | ||
161 | /********* Compl Q door bell *************/ | |
457ff3b7 | 162 | #define DB_CQ_OFFSET 0x120 |
e08b3c8b JK |
163 | #define DB_CQ_RING_ID_LOW_MASK 0x3FF /* bits 0 - 9 */ |
164 | /* Higher Order CQ_ID bit */ | |
165 | #define DB_CQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */ | |
166 | #define DB_CQ_HIGH_SET_SHIFT 11 | |
167 | #define DB_CQ_HIGH_FEILD_SHIFT 10 | |
168 | ||
6733b39a | 169 | /* Number of event entries processed */ |
457ff3b7 | 170 | #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ |
6733b39a | 171 | /* Rearm bit */ |
457ff3b7 | 172 | #define DB_CQ_REARM_SHIFT (29) /* bit 29 */ |
6733b39a JK |
173 | |
174 | #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr) | |
8a86e833 JK |
175 | #define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\ |
176 | (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id) | |
177 | #define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\ | |
178 | (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id) | |
6733b39a JK |
179 | |
180 | #define PAGES_REQUIRED(x) \ | |
181 | ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE)) | |
182 | ||
8fcfb210 JK |
183 | #define BEISCSI_MSI_NAME 20 /* size of msi_name string */ |
184 | ||
a129d92f | 185 | #define MEM_DESCR_OFFSET 8 |
8a86e833 JK |
186 | #define BEISCSI_DEFQ_HDR 1 |
187 | #define BEISCSI_DEFQ_DATA 0 | |
6733b39a JK |
188 | enum be_mem_enum { |
189 | HWI_MEM_ADDN_CONTEXT, | |
6733b39a JK |
190 | HWI_MEM_WRB, |
191 | HWI_MEM_WRBH, | |
bfead3b2 | 192 | HWI_MEM_SGLH, |
6733b39a | 193 | HWI_MEM_SGE, |
a129d92f JK |
194 | HWI_MEM_TEMPLATE_HDR_ULP0, |
195 | HWI_MEM_ASYNC_HEADER_BUF_ULP0, /* 6 */ | |
8a86e833 JK |
196 | HWI_MEM_ASYNC_DATA_BUF_ULP0, |
197 | HWI_MEM_ASYNC_HEADER_RING_ULP0, | |
198 | HWI_MEM_ASYNC_DATA_RING_ULP0, | |
199 | HWI_MEM_ASYNC_HEADER_HANDLE_ULP0, | |
a129d92f | 200 | HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */ |
8a86e833 | 201 | HWI_MEM_ASYNC_PDU_CONTEXT_ULP0, |
a129d92f JK |
202 | HWI_MEM_TEMPLATE_HDR_ULP1, |
203 | HWI_MEM_ASYNC_HEADER_BUF_ULP1, /* 14 */ | |
8a86e833 JK |
204 | HWI_MEM_ASYNC_DATA_BUF_ULP1, |
205 | HWI_MEM_ASYNC_HEADER_RING_ULP1, | |
206 | HWI_MEM_ASYNC_DATA_RING_ULP1, | |
207 | HWI_MEM_ASYNC_HEADER_HANDLE_ULP1, | |
a129d92f | 208 | HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */ |
8a86e833 | 209 | HWI_MEM_ASYNC_PDU_CONTEXT_ULP1, |
6733b39a | 210 | ISCSI_MEM_GLOBAL_HEADER, |
bfead3b2 | 211 | SE_MEM_MAX |
6733b39a JK |
212 | }; |
213 | ||
214 | struct be_bus_address32 { | |
215 | unsigned int address_lo; | |
216 | unsigned int address_hi; | |
217 | }; | |
218 | ||
219 | struct be_bus_address64 { | |
220 | unsigned long long address; | |
221 | }; | |
222 | ||
223 | struct be_bus_address { | |
224 | union { | |
225 | struct be_bus_address32 a32; | |
226 | struct be_bus_address64 a64; | |
227 | } u; | |
228 | }; | |
229 | ||
230 | struct mem_array { | |
231 | struct be_bus_address bus_address; /* Bus address of location */ | |
232 | void *virtual_address; /* virtual address to the location */ | |
233 | unsigned int size; /* Size required by memory block */ | |
234 | }; | |
235 | ||
236 | struct be_mem_descriptor { | |
237 | unsigned int index; /* Index of this memory parameter */ | |
238 | unsigned int category; /* type indicates cached/non-cached */ | |
239 | unsigned int num_elements; /* number of elements in this | |
240 | * descriptor | |
241 | */ | |
242 | unsigned int alignment_mask; /* Alignment mask for this block */ | |
243 | unsigned int size_in_bytes; /* Size required by memory block */ | |
244 | struct mem_array *mem_array; | |
245 | }; | |
246 | ||
247 | struct sgl_handle { | |
248 | unsigned int sgl_index; | |
bfead3b2 JK |
249 | unsigned int type; |
250 | unsigned int cid; | |
251 | struct iscsi_task *task; | |
6733b39a JK |
252 | struct iscsi_sge *pfrag; |
253 | }; | |
254 | ||
255 | struct hba_parameters { | |
256 | unsigned int ios_per_ctrl; | |
257 | unsigned int cxns_per_ctrl; | |
258 | unsigned int asyncpdus_per_ctrl; | |
259 | unsigned int icds_per_ctrl; | |
260 | unsigned int num_sge_per_io; | |
261 | unsigned int defpdu_hdr_sz; | |
262 | unsigned int defpdu_data_sz; | |
263 | unsigned int num_cq_entries; | |
264 | unsigned int num_eq_entries; | |
265 | unsigned int wrbs_per_cxn; | |
266 | unsigned int crashmode; | |
267 | unsigned int hba_num; | |
268 | ||
269 | unsigned int mgmt_ws_sz; | |
270 | unsigned int hwi_ws_sz; | |
271 | ||
272 | unsigned int eto; | |
273 | unsigned int ldto; | |
274 | ||
275 | unsigned int dbg_flags; | |
276 | unsigned int num_cxn; | |
277 | ||
278 | unsigned int eq_timer; | |
279 | /** | |
280 | * These are calculated from other params. They're here | |
281 | * for debug purposes | |
282 | */ | |
283 | unsigned int num_mcc_pages; | |
284 | unsigned int num_mcc_cq_pages; | |
285 | unsigned int num_cq_pages; | |
286 | unsigned int num_eq_pages; | |
287 | ||
288 | unsigned int num_async_pdu_buf_pages; | |
289 | unsigned int num_async_pdu_buf_sgl_pages; | |
290 | unsigned int num_async_pdu_buf_cq_pages; | |
291 | ||
292 | unsigned int num_async_pdu_hdr_pages; | |
293 | unsigned int num_async_pdu_hdr_sgl_pages; | |
294 | unsigned int num_async_pdu_hdr_cq_pages; | |
295 | ||
296 | unsigned int num_sge; | |
297 | }; | |
298 | ||
4183122d JK |
299 | struct invalidate_command_table { |
300 | unsigned short icd; | |
301 | unsigned short cid; | |
302 | } __packed; | |
303 | ||
4eea99d5 JK |
304 | #define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \ |
305 | (phwi_ctrlr->wrb_context[cri].ulp_num) | |
306 | struct hwi_wrb_context { | |
307 | struct list_head wrb_handle_list; | |
308 | struct list_head wrb_handle_drvr_list; | |
309 | struct wrb_handle **pwrb_handle_base; | |
310 | struct wrb_handle **pwrb_handle_basestd; | |
311 | struct iscsi_wrb *plast_wrb; | |
312 | unsigned short alloc_index; | |
313 | unsigned short free_index; | |
314 | unsigned short wrb_handles_available; | |
315 | unsigned short cid; | |
316 | uint8_t ulp_num; /* ULP to which CID binded */ | |
317 | uint16_t register_set; | |
318 | uint16_t doorbell_format; | |
319 | uint32_t doorbell_offset; | |
320 | }; | |
321 | ||
0a3db7c0 JK |
322 | struct ulp_cid_info { |
323 | unsigned short *cid_array; | |
324 | unsigned short avlbl_cids; | |
325 | unsigned short cid_alloc; | |
326 | unsigned short cid_free; | |
327 | }; | |
328 | ||
4eea99d5 | 329 | #include "be.h" |
2c9dfd36 JK |
330 | #define chip_be2(phba) (phba->generation == BE_GEN2) |
331 | #define chip_be3_r(phba) (phba->generation == BE_GEN3) | |
332 | #define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba))) | |
843ae752 JK |
333 | |
334 | #define BEISCSI_ULP0 0 | |
335 | #define BEISCSI_ULP1 1 | |
336 | #define BEISCSI_ULP_COUNT 2 | |
337 | #define BEISCSI_ULP0_LOADED 0x01 | |
338 | #define BEISCSI_ULP1_LOADED 0x02 | |
0a3db7c0 JK |
339 | |
340 | #define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \ | |
341 | (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids) | |
342 | #define BEISCSI_ULP0_AVLBL_CID(phba) \ | |
343 | BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0) | |
344 | #define BEISCSI_ULP1_AVLBL_CID(phba) \ | |
345 | BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1) | |
346 | ||
6733b39a JK |
347 | struct beiscsi_hba { |
348 | struct hba_parameters params; | |
349 | struct hwi_controller *phwi_ctrlr; | |
350 | unsigned int mem_req[SE_MEM_MAX]; | |
351 | /* PCI BAR mapped addresses */ | |
352 | u8 __iomem *csr_va; /* CSR */ | |
353 | u8 __iomem *db_va; /* Door Bell */ | |
354 | u8 __iomem *pci_va; /* PCI Config */ | |
355 | struct be_bus_address csr_pa; /* CSR */ | |
356 | struct be_bus_address db_pa; /* CSR */ | |
357 | struct be_bus_address pci_pa; /* CSR */ | |
358 | /* PCI representation of our HBA */ | |
359 | struct pci_dev *pcidev; | |
6733b39a | 360 | unsigned short asic_revision; |
bfead3b2 JK |
361 | unsigned int num_cpus; |
362 | unsigned int nxt_cqid; | |
22abeef0 JSJ |
363 | struct msix_entry msix_entries[MAX_CPUS]; |
364 | char *msi_name[MAX_CPUS]; | |
bfead3b2 | 365 | bool msix_enabled; |
6733b39a JK |
366 | struct be_mem_descriptor *init_mem; |
367 | ||
368 | unsigned short io_sgl_alloc_index; | |
369 | unsigned short io_sgl_free_index; | |
370 | unsigned short io_sgl_hndl_avbl; | |
371 | struct sgl_handle **io_sgl_hndl_base; | |
bfead3b2 | 372 | struct sgl_handle **sgl_hndl_array; |
6733b39a JK |
373 | |
374 | unsigned short eh_sgl_alloc_index; | |
375 | unsigned short eh_sgl_free_index; | |
376 | unsigned short eh_sgl_hndl_avbl; | |
377 | struct sgl_handle **eh_sgl_hndl_base; | |
378 | spinlock_t io_sgl_lock; | |
379 | spinlock_t mgmt_sgl_lock; | |
380 | spinlock_t isr_lock; | |
8f09a3b9 | 381 | spinlock_t async_pdu_lock; |
6733b39a | 382 | unsigned int age; |
6733b39a | 383 | struct list_head hba_queue; |
a7909b39 JK |
384 | #define BE_MAX_SESSION 2048 |
385 | #define BE_SET_CID_TO_CRI(cri_index, cid) \ | |
386 | (phba->cid_to_cri_map[cid] = cri_index) | |
387 | #define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid]) | |
388 | unsigned short cid_to_cri_map[BE_MAX_SESSION]; | |
0a3db7c0 | 389 | struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT]; |
6733b39a | 390 | struct iscsi_endpoint **ep_array; |
a7909b39 | 391 | struct beiscsi_conn **conn_table; |
c7acc5b8 | 392 | struct iscsi_boot_kset *boot_kset; |
6733b39a | 393 | struct Scsi_Host *shost; |
0e43895e MC |
394 | struct iscsi_iface *ipv4_iface; |
395 | struct iscsi_iface *ipv6_iface; | |
6733b39a JK |
396 | struct { |
397 | /** | |
398 | * group together since they are used most frequently | |
399 | * for cid to cri conversion | |
400 | */ | |
6733b39a | 401 | unsigned int phys_port; |
68c26a3a JK |
402 | unsigned int eqid_count; |
403 | unsigned int cqid_count; | |
843ae752 JK |
404 | unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT]; |
405 | #define BEISCSI_GET_CID_COUNT(phba, ulp_num) \ | |
8a86e833 | 406 | (phba->fw_config.iscsi_cid_count[ulp_num]) |
843ae752 JK |
407 | unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT]; |
408 | unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT]; | |
409 | unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT]; | |
410 | unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT]; | |
411 | unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT]; | |
6733b39a | 412 | |
bfead3b2 | 413 | unsigned short iscsi_features; |
843ae752 JK |
414 | uint16_t dual_ulp_aware; |
415 | unsigned long ulp_supported; | |
6733b39a JK |
416 | } fw_config; |
417 | ||
e175defe | 418 | unsigned int state; |
3efde862 | 419 | int get_boot; |
e175defe JSJ |
420 | bool fw_timeout; |
421 | bool ue_detected; | |
422 | struct delayed_work beiscsi_hw_check_task; | |
423 | ||
6c83185a | 424 | bool mac_addr_set; |
6733b39a | 425 | u8 mac_address[ETH_ALEN]; |
22661e25 | 426 | char fw_ver_str[BEISCSI_VER_STRLEN]; |
6733b39a JK |
427 | char wq_name[20]; |
428 | struct workqueue_struct *wq; /* The actuak work queue */ | |
6733b39a | 429 | struct be_ctrl_info ctrl; |
f98c96b0 | 430 | unsigned int generation; |
0e43895e | 431 | unsigned int interface_handle; |
c7acc5b8 | 432 | struct mgmt_session_info boot_sess; |
4183122d JK |
433 | struct invalidate_command_table inv_tbl[128]; |
434 | ||
73af08e1 | 435 | struct be_aic_obj aic_obj[MAX_CPUS]; |
99bc5d55 | 436 | unsigned int attr_log_enable; |
09a1093a JSJ |
437 | int (*iotask_fn)(struct iscsi_task *, |
438 | struct scatterlist *sg, | |
439 | uint32_t num_sg, uint32_t xferlen, | |
440 | uint32_t writedir); | |
6733b39a JK |
441 | }; |
442 | ||
b8b9e1b8 JK |
443 | struct beiscsi_session { |
444 | struct pci_pool *bhs_pool; | |
445 | }; | |
446 | ||
6733b39a JK |
447 | /** |
448 | * struct beiscsi_conn - iscsi connection structure | |
449 | */ | |
450 | struct beiscsi_conn { | |
451 | struct iscsi_conn *conn; | |
452 | struct beiscsi_hba *phba; | |
453 | u32 exp_statsn; | |
1e4be6ff | 454 | u32 doorbell_offset; |
6733b39a JK |
455 | u32 beiscsi_conn_cid; |
456 | struct beiscsi_endpoint *ep; | |
457 | unsigned short login_in_progress; | |
d2cecf0d | 458 | struct wrb_handle *plogin_wrb_handle; |
6733b39a | 459 | struct sgl_handle *plogin_sgl_handle; |
b8b9e1b8 | 460 | struct beiscsi_session *beiscsi_sess; |
bfead3b2 | 461 | struct iscsi_task *task; |
6733b39a JK |
462 | }; |
463 | ||
464 | /* This structure is used by the chip */ | |
465 | struct pdu_data_out { | |
466 | u32 dw[12]; | |
467 | }; | |
468 | /** | |
469 | * Pseudo amap definition in which each bit of the actual structure is defined | |
470 | * as a byte: used to calculate offset/shift/mask of each field | |
471 | */ | |
472 | struct amap_pdu_data_out { | |
473 | u8 opcode[6]; /* opcode */ | |
474 | u8 rsvd0[2]; /* should be 0 */ | |
475 | u8 rsvd1[7]; | |
476 | u8 final_bit; /* F bit */ | |
477 | u8 rsvd2[16]; | |
478 | u8 ahs_length[8]; /* no AHS */ | |
479 | u8 data_len_hi[8]; | |
480 | u8 data_len_lo[16]; /* DataSegmentLength */ | |
481 | u8 lun[64]; | |
482 | u8 itt[32]; /* ITT; initiator task tag */ | |
483 | u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */ | |
484 | u8 rsvd3[32]; | |
485 | u8 exp_stat_sn[32]; | |
486 | u8 rsvd4[32]; | |
487 | u8 data_sn[32]; | |
488 | u8 buffer_offset[32]; | |
489 | u8 rsvd5[32]; | |
490 | }; | |
491 | ||
492 | struct be_cmd_bhs { | |
12352183 | 493 | struct iscsi_scsi_req iscsi_hdr; |
6733b39a JK |
494 | unsigned char pad1[16]; |
495 | struct pdu_data_out iscsi_data_pdu; | |
496 | unsigned char pad2[BE_SENSE_INFO_SIZE - | |
497 | sizeof(struct pdu_data_out)]; | |
498 | }; | |
499 | ||
500 | struct beiscsi_io_task { | |
501 | struct wrb_handle *pwrb_handle; | |
502 | struct sgl_handle *psgl_handle; | |
503 | struct beiscsi_conn *conn; | |
504 | struct scsi_cmnd *scsi_cmnd; | |
505 | unsigned int cmd_sn; | |
506 | unsigned int flags; | |
507 | unsigned short cid; | |
508 | unsigned short header_len; | |
bfead3b2 | 509 | itt_t libiscsi_itt; |
6733b39a JK |
510 | struct be_cmd_bhs *cmd_bhs; |
511 | struct be_bus_address bhs_pa; | |
512 | unsigned short bhs_len; | |
d629c471 JSJ |
513 | dma_addr_t mtask_addr; |
514 | uint32_t mtask_data_count; | |
09a1093a | 515 | uint8_t wrb_type; |
6733b39a JK |
516 | }; |
517 | ||
518 | struct be_nonio_bhs { | |
519 | struct iscsi_hdr iscsi_hdr; | |
520 | unsigned char pad1[16]; | |
521 | struct pdu_data_out iscsi_data_pdu; | |
522 | unsigned char pad2[BE_SENSE_INFO_SIZE - | |
523 | sizeof(struct pdu_data_out)]; | |
524 | }; | |
525 | ||
526 | struct be_status_bhs { | |
12352183 | 527 | struct iscsi_scsi_req iscsi_hdr; |
6733b39a JK |
528 | unsigned char pad1[16]; |
529 | /** | |
530 | * The plus 2 below is to hold the sense info length that gets | |
531 | * DMA'ed by RxULP | |
532 | */ | |
533 | unsigned char sense_info[BE_SENSE_INFO_SIZE]; | |
534 | }; | |
535 | ||
536 | struct iscsi_sge { | |
537 | u32 dw[4]; | |
538 | }; | |
539 | ||
540 | /** | |
541 | * Pseudo amap definition in which each bit of the actual structure is defined | |
542 | * as a byte: used to calculate offset/shift/mask of each field | |
543 | */ | |
544 | struct amap_iscsi_sge { | |
545 | u8 addr_hi[32]; | |
546 | u8 addr_lo[32]; | |
547 | u8 sge_offset[22]; /* DWORD 2 */ | |
548 | u8 rsvd0[9]; /* DWORD 2 */ | |
549 | u8 last_sge; /* DWORD 2 */ | |
550 | u8 len[17]; /* DWORD 3 */ | |
551 | u8 rsvd1[15]; /* DWORD 3 */ | |
552 | }; | |
553 | ||
554 | struct beiscsi_offload_params { | |
7331613e | 555 | u32 dw[6]; |
6733b39a JK |
556 | }; |
557 | ||
558 | #define OFFLD_PARAMS_ERL 0x00000003 | |
559 | #define OFFLD_PARAMS_DDE 0x00000004 | |
560 | #define OFFLD_PARAMS_HDE 0x00000008 | |
561 | #define OFFLD_PARAMS_IR2T 0x00000010 | |
562 | #define OFFLD_PARAMS_IMD 0x00000020 | |
acb9693c JSJ |
563 | #define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040 |
564 | #define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080 | |
565 | #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00 | |
6733b39a JK |
566 | |
567 | /** | |
568 | * Pseudo amap definition in which each bit of the actual structure is defined | |
569 | * as a byte: used to calculate offset/shift/mask of each field | |
570 | */ | |
571 | struct amap_beiscsi_offload_params { | |
572 | u8 max_burst_length[32]; | |
573 | u8 max_send_data_segment_length[32]; | |
574 | u8 first_burst_length[32]; | |
575 | u8 erl[2]; | |
576 | u8 dde[1]; | |
577 | u8 hde[1]; | |
578 | u8 ir2t[1]; | |
579 | u8 imd[1]; | |
acb9693c JSJ |
580 | u8 data_seq_inorder[1]; |
581 | u8 pdu_seq_inorder[1]; | |
582 | u8 max_r2t[16]; | |
583 | u8 pad[8]; | |
6733b39a | 584 | u8 exp_statsn[32]; |
7331613e | 585 | u8 max_recv_data_segment_length[32]; |
6733b39a JK |
586 | }; |
587 | ||
588 | /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn, | |
589 | struct beiscsi_hba *phba, struct sol_cqe *psol);*/ | |
590 | ||
591 | struct async_pdu_handle { | |
592 | struct list_head link; | |
593 | struct be_bus_address pa; | |
594 | void *pbuffer; | |
595 | unsigned int consumed; | |
596 | unsigned char index; | |
597 | unsigned char is_header; | |
598 | unsigned short cri; | |
599 | unsigned long buffer_len; | |
600 | }; | |
601 | ||
602 | struct hwi_async_entry { | |
603 | struct { | |
604 | unsigned char hdr_received; | |
605 | unsigned char hdr_len; | |
606 | unsigned short bytes_received; | |
607 | unsigned int bytes_needed; | |
608 | struct list_head list; | |
609 | } wait_queue; | |
610 | ||
611 | struct list_head header_busy_list; | |
612 | struct list_head data_busy_list; | |
613 | }; | |
614 | ||
6733b39a JK |
615 | struct hwi_async_pdu_context { |
616 | struct { | |
617 | struct be_bus_address pa_base; | |
618 | void *va_base; | |
619 | void *ring_base; | |
620 | struct async_pdu_handle *handle_base; | |
621 | ||
622 | unsigned int host_write_ptr; | |
623 | unsigned int ep_read_ptr; | |
624 | unsigned int writables; | |
625 | ||
626 | unsigned int free_entries; | |
627 | unsigned int busy_entries; | |
6733b39a JK |
628 | |
629 | struct list_head free_list; | |
630 | } async_header; | |
631 | ||
632 | struct { | |
633 | struct be_bus_address pa_base; | |
634 | void *va_base; | |
635 | void *ring_base; | |
636 | struct async_pdu_handle *handle_base; | |
637 | ||
638 | unsigned int host_write_ptr; | |
639 | unsigned int ep_read_ptr; | |
640 | unsigned int writables; | |
641 | ||
642 | unsigned int free_entries; | |
643 | unsigned int busy_entries; | |
6733b39a | 644 | struct list_head free_list; |
6733b39a JK |
645 | } async_data; |
646 | ||
dc63aac6 JK |
647 | unsigned int buffer_size; |
648 | unsigned int num_entries; | |
8a86e833 JK |
649 | #define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid]) |
650 | unsigned short cid_to_async_cri_map[BE_MAX_SESSION]; | |
6733b39a JK |
651 | /** |
652 | * This is a varying size list! Do not add anything | |
653 | * after this entry!! | |
654 | */ | |
a7909b39 | 655 | struct hwi_async_entry *async_entry; |
6733b39a JK |
656 | }; |
657 | ||
658 | #define PDUCQE_CODE_MASK 0x0000003F | |
659 | #define PDUCQE_DPL_MASK 0xFFFF0000 | |
660 | #define PDUCQE_INDEX_MASK 0x0000FFFF | |
661 | ||
662 | struct i_t_dpdu_cqe { | |
663 | u32 dw[4]; | |
664 | } __packed; | |
665 | ||
666 | /** | |
667 | * Pseudo amap definition in which each bit of the actual structure is defined | |
668 | * as a byte: used to calculate offset/shift/mask of each field | |
669 | */ | |
670 | struct amap_i_t_dpdu_cqe { | |
671 | u8 db_addr_hi[32]; | |
672 | u8 db_addr_lo[32]; | |
673 | u8 code[6]; | |
674 | u8 cid[10]; | |
675 | u8 dpl[16]; | |
676 | u8 index[16]; | |
677 | u8 num_cons[10]; | |
678 | u8 rsvd0[4]; | |
679 | u8 final; | |
680 | u8 valid; | |
681 | } __packed; | |
682 | ||
73133261 JSJ |
683 | struct amap_i_t_dpdu_cqe_v2 { |
684 | u8 db_addr_hi[32]; /* DWORD 0 */ | |
685 | u8 db_addr_lo[32]; /* DWORD 1 */ | |
686 | u8 code[6]; /* DWORD 2 */ | |
687 | u8 num_cons; /* DWORD 2*/ | |
688 | u8 rsvd0[8]; /* DWORD 2 */ | |
689 | u8 dpl[17]; /* DWORD 2 */ | |
690 | u8 index[16]; /* DWORD 3 */ | |
691 | u8 cid[13]; /* DWORD 3 */ | |
692 | u8 rsvd1; /* DWORD 3 */ | |
693 | u8 final; /* DWORD 3 */ | |
694 | u8 valid; /* DWORD 3 */ | |
695 | } __packed; | |
696 | ||
6733b39a JK |
697 | #define CQE_VALID_MASK 0x80000000 |
698 | #define CQE_CODE_MASK 0x0000003F | |
699 | #define CQE_CID_MASK 0x0000FFC0 | |
700 | ||
701 | #define EQE_VALID_MASK 0x00000001 | |
702 | #define EQE_MAJORCODE_MASK 0x0000000E | |
703 | #define EQE_RESID_MASK 0xFFFF0000 | |
704 | ||
705 | struct be_eq_entry { | |
706 | u32 dw[1]; | |
707 | } __packed; | |
708 | ||
709 | /** | |
710 | * Pseudo amap definition in which each bit of the actual structure is defined | |
711 | * as a byte: used to calculate offset/shift/mask of each field | |
712 | */ | |
713 | struct amap_eq_entry { | |
714 | u8 valid; /* DWORD 0 */ | |
715 | u8 major_code[3]; /* DWORD 0 */ | |
716 | u8 minor_code[12]; /* DWORD 0 */ | |
717 | u8 resource_id[16]; /* DWORD 0 */ | |
718 | ||
719 | } __packed; | |
720 | ||
721 | struct cq_db { | |
722 | u32 dw[1]; | |
723 | } __packed; | |
724 | ||
725 | /** | |
726 | * Pseudo amap definition in which each bit of the actual structure is defined | |
727 | * as a byte: used to calculate offset/shift/mask of each field | |
728 | */ | |
729 | struct amap_cq_db { | |
730 | u8 qid[10]; | |
731 | u8 event[1]; | |
732 | u8 rsvd0[5]; | |
733 | u8 num_popped[13]; | |
734 | u8 rearm[1]; | |
735 | u8 rsvd1[2]; | |
736 | } __packed; | |
737 | ||
738 | void beiscsi_process_eq(struct beiscsi_hba *phba); | |
739 | ||
6733b39a JK |
740 | struct iscsi_wrb { |
741 | u32 dw[16]; | |
742 | } __packed; | |
743 | ||
744 | #define WRB_TYPE_MASK 0xF0000000 | |
09a1093a JSJ |
745 | #define SKH_WRB_TYPE_OFFSET 27 |
746 | #define BE_WRB_TYPE_OFFSET 28 | |
747 | ||
748 | #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \ | |
749 | (pwrb->dw[0] |= (wrb_type << type_offset)) | |
6733b39a JK |
750 | |
751 | /** | |
752 | * Pseudo amap definition in which each bit of the actual structure is defined | |
753 | * as a byte: used to calculate offset/shift/mask of each field | |
754 | */ | |
755 | struct amap_iscsi_wrb { | |
756 | u8 lun[14]; /* DWORD 0 */ | |
757 | u8 lt; /* DWORD 0 */ | |
758 | u8 invld; /* DWORD 0 */ | |
759 | u8 wrb_idx[8]; /* DWORD 0 */ | |
760 | u8 dsp; /* DWORD 0 */ | |
761 | u8 dmsg; /* DWORD 0 */ | |
762 | u8 undr_run; /* DWORD 0 */ | |
763 | u8 over_run; /* DWORD 0 */ | |
764 | u8 type[4]; /* DWORD 0 */ | |
765 | u8 ptr2nextwrb[8]; /* DWORD 1 */ | |
766 | u8 r2t_exp_dtl[24]; /* DWORD 1 */ | |
767 | u8 sgl_icd_idx[12]; /* DWORD 2 */ | |
768 | u8 rsvd0[20]; /* DWORD 2 */ | |
769 | u8 exp_data_sn[32]; /* DWORD 3 */ | |
770 | u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */ | |
771 | u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */ | |
772 | u8 cmdsn_itt[32]; /* DWORD 6 */ | |
773 | u8 dif_ref_tag[32]; /* DWORD 7 */ | |
774 | u8 sge0_addr_hi[32]; /* DWORD 8 */ | |
775 | u8 sge0_addr_lo[32]; /* DWORD 9 */ | |
776 | u8 sge0_offset[22]; /* DWORD 10 */ | |
777 | u8 pbs; /* DWORD 10 */ | |
778 | u8 dif_mode[2]; /* DWORD 10 */ | |
779 | u8 rsvd1[6]; /* DWORD 10 */ | |
780 | u8 sge0_last; /* DWORD 10 */ | |
781 | u8 sge0_len[17]; /* DWORD 11 */ | |
782 | u8 dif_meta_tag[14]; /* DWORD 11 */ | |
783 | u8 sge0_in_ddr; /* DWORD 11 */ | |
784 | u8 sge1_addr_hi[32]; /* DWORD 12 */ | |
785 | u8 sge1_addr_lo[32]; /* DWORD 13 */ | |
786 | u8 sge1_r2t_offset[22]; /* DWORD 14 */ | |
787 | u8 rsvd2[9]; /* DWORD 14 */ | |
788 | u8 sge1_last; /* DWORD 14 */ | |
789 | u8 sge1_len[17]; /* DWORD 15 */ | |
790 | u8 ref_sgl_icd_idx[12]; /* DWORD 15 */ | |
791 | u8 rsvd3[2]; /* DWORD 15 */ | |
792 | u8 sge1_in_ddr; /* DWORD 15 */ | |
793 | ||
794 | } __packed; | |
795 | ||
09a1093a JSJ |
796 | struct amap_iscsi_wrb_v2 { |
797 | u8 r2t_exp_dtl[25]; /* DWORD 0 */ | |
798 | u8 rsvd0[2]; /* DWORD 0*/ | |
799 | u8 type[5]; /* DWORD 0 */ | |
800 | u8 ptr2nextwrb[8]; /* DWORD 1 */ | |
801 | u8 wrb_idx[8]; /* DWORD 1 */ | |
802 | u8 lun[16]; /* DWORD 1 */ | |
803 | u8 sgl_idx[16]; /* DWORD 2 */ | |
804 | u8 ref_sgl_icd_idx[16]; /* DWORD 2 */ | |
805 | u8 exp_data_sn[32]; /* DWORD 3 */ | |
806 | u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */ | |
807 | u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */ | |
808 | u8 cq_id[16]; /* DWORD 6 */ | |
809 | u8 rsvd1[16]; /* DWORD 6 */ | |
810 | u8 cmdsn_itt[32]; /* DWORD 7 */ | |
811 | u8 sge0_addr_hi[32]; /* DWORD 8 */ | |
812 | u8 sge0_addr_lo[32]; /* DWORD 9 */ | |
813 | u8 sge0_offset[24]; /* DWORD 10 */ | |
814 | u8 rsvd2[7]; /* DWORD 10 */ | |
815 | u8 sge0_last; /* DWORD 10 */ | |
816 | u8 sge0_len[17]; /* DWORD 11 */ | |
817 | u8 rsvd3[7]; /* DWORD 11 */ | |
818 | u8 diff_enbl; /* DWORD 11 */ | |
819 | u8 u_run; /* DWORD 11 */ | |
820 | u8 o_run; /* DWORD 11 */ | |
821 | u8 invalid; /* DWORD 11 */ | |
822 | u8 dsp; /* DWORD 11 */ | |
823 | u8 dmsg; /* DWORD 11 */ | |
824 | u8 rsvd4; /* DWORD 11 */ | |
825 | u8 lt; /* DWORD 11 */ | |
826 | u8 sge1_addr_hi[32]; /* DWORD 12 */ | |
827 | u8 sge1_addr_lo[32]; /* DWORD 13 */ | |
828 | u8 sge1_r2t_offset[24]; /* DWORD 14 */ | |
829 | u8 rsvd5[7]; /* DWORD 14 */ | |
830 | u8 sge1_last; /* DWORD 14 */ | |
831 | u8 sge1_len[17]; /* DWORD 15 */ | |
832 | u8 rsvd6[15]; /* DWORD 15 */ | |
833 | } __packed; | |
834 | ||
835 | ||
d5431488 | 836 | struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid); |
6733b39a JK |
837 | void |
838 | free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle); | |
839 | ||
756d29c8 | 840 | void beiscsi_process_all_cqs(struct work_struct *work); |
4a4a11b9 JK |
841 | void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn, |
842 | struct iscsi_task *task); | |
756d29c8 | 843 | |
e08b3c8b JK |
844 | void hwi_ring_cq_db(struct beiscsi_hba *phba, |
845 | unsigned int id, unsigned int num_processed, | |
846 | unsigned char rearm, unsigned char event); | |
b7ab35b1 JK |
847 | |
848 | unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq); | |
849 | ||
7a158003 JSJ |
850 | static inline bool beiscsi_error(struct beiscsi_hba *phba) |
851 | { | |
852 | return phba->ue_detected || phba->fw_timeout; | |
853 | } | |
854 | ||
6733b39a JK |
855 | struct pdu_nop_out { |
856 | u32 dw[12]; | |
857 | }; | |
858 | ||
859 | /** | |
860 | * Pseudo amap definition in which each bit of the actual structure is defined | |
861 | * as a byte: used to calculate offset/shift/mask of each field | |
862 | */ | |
863 | struct amap_pdu_nop_out { | |
864 | u8 opcode[6]; /* opcode 0x00 */ | |
865 | u8 i_bit; /* I Bit */ | |
866 | u8 x_bit; /* reserved; should be 0 */ | |
867 | u8 fp_bit_filler1[7]; | |
868 | u8 f_bit; /* always 1 */ | |
869 | u8 reserved1[16]; | |
870 | u8 ahs_length[8]; /* no AHS */ | |
871 | u8 data_len_hi[8]; | |
872 | u8 data_len_lo[16]; /* DataSegmentLength */ | |
873 | u8 lun[64]; | |
874 | u8 itt[32]; /* initiator id for ping or 0xffffffff */ | |
875 | u8 ttt[32]; /* target id for ping or 0xffffffff */ | |
876 | u8 cmd_sn[32]; | |
877 | u8 exp_stat_sn[32]; | |
878 | u8 reserved5[128]; | |
879 | }; | |
880 | ||
881 | #define PDUBASE_OPCODE_MASK 0x0000003F | |
882 | #define PDUBASE_DATALENHI_MASK 0x0000FF00 | |
883 | #define PDUBASE_DATALENLO_MASK 0xFFFF0000 | |
884 | ||
885 | struct pdu_base { | |
886 | u32 dw[16]; | |
887 | } __packed; | |
888 | ||
889 | /** | |
890 | * Pseudo amap definition in which each bit of the actual structure is defined | |
891 | * as a byte: used to calculate offset/shift/mask of each field | |
892 | */ | |
893 | struct amap_pdu_base { | |
894 | u8 opcode[6]; | |
895 | u8 i_bit; /* immediate bit */ | |
896 | u8 x_bit; /* reserved, always 0 */ | |
897 | u8 reserved1[24]; /* opcode-specific fields */ | |
898 | u8 ahs_length[8]; /* length units is 4 byte words */ | |
899 | u8 data_len_hi[8]; | |
900 | u8 data_len_lo[16]; /* DatasegmentLength */ | |
901 | u8 lun[64]; /* lun or opcode-specific fields */ | |
902 | u8 itt[32]; /* initiator task tag */ | |
903 | u8 reserved4[224]; | |
904 | }; | |
905 | ||
906 | struct iscsi_target_context_update_wrb { | |
907 | u32 dw[16]; | |
908 | } __packed; | |
909 | ||
910 | /** | |
911 | * Pseudo amap definition in which each bit of the actual structure is defined | |
912 | * as a byte: used to calculate offset/shift/mask of each field | |
913 | */ | |
acb9693c | 914 | #define BE_TGT_CTX_UPDT_CMD 0x07 |
6733b39a JK |
915 | struct amap_iscsi_target_context_update_wrb { |
916 | u8 lun[14]; /* DWORD 0 */ | |
917 | u8 lt; /* DWORD 0 */ | |
918 | u8 invld; /* DWORD 0 */ | |
919 | u8 wrb_idx[8]; /* DWORD 0 */ | |
920 | u8 dsp; /* DWORD 0 */ | |
921 | u8 dmsg; /* DWORD 0 */ | |
922 | u8 undr_run; /* DWORD 0 */ | |
923 | u8 over_run; /* DWORD 0 */ | |
924 | u8 type[4]; /* DWORD 0 */ | |
925 | u8 ptr2nextwrb[8]; /* DWORD 1 */ | |
926 | u8 max_burst_length[19]; /* DWORD 1 */ | |
927 | u8 rsvd0[5]; /* DWORD 1 */ | |
928 | u8 rsvd1[15]; /* DWORD 2 */ | |
929 | u8 max_send_data_segment_length[17]; /* DWORD 2 */ | |
930 | u8 first_burst_length[14]; /* DWORD 3 */ | |
931 | u8 rsvd2[2]; /* DWORD 3 */ | |
932 | u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */ | |
933 | u8 rsvd3[5]; /* DWORD 3 */ | |
934 | u8 session_state[3]; /* DWORD 3 */ | |
935 | u8 rsvd4[16]; /* DWORD 4 */ | |
936 | u8 tx_jumbo; /* DWORD 4 */ | |
937 | u8 hde; /* DWORD 4 */ | |
938 | u8 dde; /* DWORD 4 */ | |
939 | u8 erl[2]; /* DWORD 4 */ | |
940 | u8 domain_id[5]; /* DWORD 4 */ | |
941 | u8 mode; /* DWORD 4 */ | |
942 | u8 imd; /* DWORD 4 */ | |
943 | u8 ir2t; /* DWORD 4 */ | |
944 | u8 notpredblq[2]; /* DWORD 4 */ | |
945 | u8 compltonack; /* DWORD 4 */ | |
946 | u8 stat_sn[32]; /* DWORD 5 */ | |
947 | u8 pad_buffer_addr_hi[32]; /* DWORD 6 */ | |
948 | u8 pad_buffer_addr_lo[32]; /* DWORD 7 */ | |
949 | u8 pad_addr_hi[32]; /* DWORD 8 */ | |
950 | u8 pad_addr_lo[32]; /* DWORD 9 */ | |
951 | u8 rsvd5[32]; /* DWORD 10 */ | |
952 | u8 rsvd6[32]; /* DWORD 11 */ | |
953 | u8 rsvd7[32]; /* DWORD 12 */ | |
954 | u8 rsvd8[32]; /* DWORD 13 */ | |
955 | u8 rsvd9[32]; /* DWORD 14 */ | |
956 | u8 rsvd10[32]; /* DWORD 15 */ | |
957 | ||
958 | } __packed; | |
959 | ||
acb9693c JSJ |
960 | #define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024) |
961 | #define BEISCSI_MAX_CXNS 1 | |
962 | struct amap_iscsi_target_context_update_wrb_v2 { | |
963 | u8 max_burst_length[24]; /* DWORD 0 */ | |
964 | u8 rsvd0[3]; /* DWORD 0 */ | |
965 | u8 type[5]; /* DWORD 0 */ | |
966 | u8 ptr2nextwrb[8]; /* DWORD 1 */ | |
967 | u8 wrb_idx[8]; /* DWORD 1 */ | |
968 | u8 rsvd1[16]; /* DWORD 1 */ | |
969 | u8 max_send_data_segment_length[24]; /* DWORD 2 */ | |
970 | u8 rsvd2[8]; /* DWORD 2 */ | |
971 | u8 first_burst_length[24]; /* DWORD 3 */ | |
972 | u8 rsvd3[8]; /* DOWRD 3 */ | |
973 | u8 max_r2t[16]; /* DWORD 4 */ | |
7331613e | 974 | u8 rsvd4; /* DWORD 4 */ |
acb9693c JSJ |
975 | u8 hde; /* DWORD 4 */ |
976 | u8 dde; /* DWORD 4 */ | |
977 | u8 erl[2]; /* DWORD 4 */ | |
7331613e | 978 | u8 rsvd5[6]; /* DWORD 4 */ |
acb9693c JSJ |
979 | u8 imd; /* DWORD 4 */ |
980 | u8 ir2t; /* DWORD 4 */ | |
7331613e | 981 | u8 rsvd6[3]; /* DWORD 4 */ |
acb9693c | 982 | u8 stat_sn[32]; /* DWORD 5 */ |
7331613e JK |
983 | u8 rsvd7[32]; /* DWORD 6 */ |
984 | u8 rsvd8[32]; /* DWORD 7 */ | |
acb9693c | 985 | u8 max_recv_dataseg_len[24]; /* DWORD 8 */ |
7331613e JK |
986 | u8 rsvd9[8]; /* DWORD 8 */ |
987 | u8 rsvd10[32]; /* DWORD 9 */ | |
988 | u8 rsvd11[32]; /* DWORD 10 */ | |
acb9693c | 989 | u8 max_cxns[16]; /* DWORD 11 */ |
7331613e | 990 | u8 rsvd12[11]; /* DWORD 11*/ |
acb9693c | 991 | u8 invld; /* DWORD 11 */ |
7331613e | 992 | u8 rsvd13;/* DWORD 11*/ |
acb9693c JSJ |
993 | u8 dmsg; /* DWORD 11 */ |
994 | u8 data_seq_inorder; /* DWORD 11 */ | |
995 | u8 pdu_seq_inorder; /* DWORD 11 */ | |
7331613e JK |
996 | u8 rsvd14[32]; /*DWORD 12 */ |
997 | u8 rsvd15[32]; /* DWORD 13 */ | |
998 | u8 rsvd16[32]; /* DWORD 14 */ | |
999 | u8 rsvd17[32]; /* DWORD 15 */ | |
acb9693c JSJ |
1000 | } __packed; |
1001 | ||
1002 | ||
6733b39a JK |
1003 | struct be_ring { |
1004 | u32 pages; /* queue size in pages */ | |
1005 | u32 id; /* queue id assigned by beklib */ | |
1006 | u32 num; /* number of elements in queue */ | |
1007 | u32 cidx; /* consumer index */ | |
1008 | u32 pidx; /* producer index -- not used by most rings */ | |
1009 | u32 item_size; /* size in bytes of one object */ | |
8a86e833 JK |
1010 | u8 ulp_num; /* ULP to which CID binded */ |
1011 | u16 register_set; | |
1012 | u16 doorbell_format; | |
1013 | u32 doorbell_offset; | |
6733b39a JK |
1014 | |
1015 | void *va; /* The virtual address of the ring. This | |
1016 | * should be last to allow 32 & 64 bit debugger | |
1017 | * extensions to work. | |
1018 | */ | |
1019 | }; | |
1020 | ||
6733b39a JK |
1021 | struct hwi_controller { |
1022 | struct list_head io_sgl_list; | |
1023 | struct list_head eh_sgl_list; | |
1024 | struct sgl_handle *psgl_handle_base; | |
1025 | unsigned int wrb_mem_index; | |
1026 | ||
a7909b39 | 1027 | struct hwi_wrb_context *wrb_context; |
6733b39a | 1028 | struct mcc_wrb *pmcc_wrb_base; |
8a86e833 JK |
1029 | struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT]; |
1030 | struct be_ring default_pdu_data[BEISCSI_ULP_COUNT]; | |
6733b39a | 1031 | struct hwi_context_memory *phwi_ctxt; |
6733b39a JK |
1032 | }; |
1033 | ||
1034 | enum hwh_type_enum { | |
1035 | HWH_TYPE_IO = 1, | |
1036 | HWH_TYPE_LOGOUT = 2, | |
1037 | HWH_TYPE_TMF = 3, | |
1038 | HWH_TYPE_NOP = 4, | |
1039 | HWH_TYPE_IO_RD = 5, | |
1040 | HWH_TYPE_LOGIN = 11, | |
1041 | HWH_TYPE_INVALID = 0xFFFFFFFF | |
1042 | }; | |
1043 | ||
1044 | struct wrb_handle { | |
1045 | enum hwh_type_enum type; | |
1046 | unsigned short wrb_index; | |
1047 | unsigned short nxt_wrb_index; | |
1048 | ||
1049 | struct iscsi_task *pio_handle; | |
1050 | struct iscsi_wrb *pwrb; | |
1051 | }; | |
1052 | ||
1053 | struct hwi_context_memory { | |
bfead3b2 JK |
1054 | /* Adaptive interrupt coalescing (AIC) info */ |
1055 | u16 min_eqd; /* in usecs */ | |
1056 | u16 max_eqd; /* in usecs */ | |
1057 | u16 cur_eqd; /* in usecs */ | |
1058 | struct be_eq_obj be_eq[MAX_CPUS]; | |
22abeef0 | 1059 | struct be_queue_info be_cq[MAX_CPUS - 1]; |
6733b39a | 1060 | |
a7909b39 | 1061 | struct be_queue_info *be_wrbq; |
8a86e833 JK |
1062 | struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT]; |
1063 | struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT]; | |
1064 | struct hwi_async_pdu_context *pasync_ctx[BEISCSI_ULP_COUNT]; | |
6733b39a JK |
1065 | }; |
1066 | ||
99bc5d55 JSJ |
1067 | /* Logging related definitions */ |
1068 | #define BEISCSI_LOG_INIT 0x0001 /* Initialization events */ | |
1069 | #define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */ | |
1070 | #define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */ | |
1071 | #define BEISCSI_LOG_EH 0x0008 /* Error Handler */ | |
1072 | #define BEISCSI_LOG_IO 0x0010 /* IO Code Path */ | |
1073 | #define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */ | |
afb96058 | 1074 | #define BEISCSI_LOG_ISCSI 0x0040 /* SCSI/iSCSI Protocol related Logs */ |
99bc5d55 JSJ |
1075 | |
1076 | #define beiscsi_log(phba, level, mask, fmt, arg...) \ | |
1077 | do { \ | |
1078 | uint32_t log_value = phba->attr_log_enable; \ | |
1079 | if (((mask) & log_value) || (level[1] <= '3')) \ | |
1080 | shost_printk(level, phba->shost, \ | |
1081 | fmt, __LINE__, ##arg); \ | |
1082 | } while (0) | |
1083 | ||
6733b39a | 1084 | #endif |