Commit | Line | Data |
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7725ccfd | 1 | /* |
a36c61f9 | 2 | * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. |
7725ccfd JH |
3 | * All rights reserved |
4 | * www.brocade.com | |
5 | * | |
6 | * Linux driver for Brocade Fibre Channel Host Bus Adapter. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License (GPL) Version 2 as | |
10 | * published by the Free Software Foundation | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | */ | |
17 | ||
f16a1750 | 18 | #include "bfad_drv.h" |
a36c61f9 | 19 | #include "bfa_modules.h" |
11189208 | 20 | #include "bfi_reg.h" |
7725ccfd JH |
21 | |
22 | BFA_TRC_FILE(HAL, IOCFC_CT); | |
23 | ||
5fbe25c7 | 24 | /* |
7725ccfd JH |
25 | * Dummy interrupt handler for handling spurious interrupt during chip-reinit. |
26 | */ | |
27 | static void | |
28 | bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec) | |
29 | { | |
30 | } | |
31 | ||
32 | void | |
33 | bfa_hwct_reginit(struct bfa_s *bfa) | |
34 | { | |
35 | struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs; | |
53440260 | 36 | void __iomem *kva = bfa_ioc_bar0(&bfa->ioc); |
11189208 | 37 | int fn = bfa_ioc_pcifn(&bfa->ioc); |
7725ccfd JH |
38 | |
39 | if (fn == 0) { | |
40 | bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS); | |
41 | bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK); | |
42 | } else { | |
43 | bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS); | |
44 | bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK); | |
45 | } | |
11189208 | 46 | } |
7725ccfd | 47 | |
11189208 KG |
48 | void |
49 | bfa_hwct2_reginit(struct bfa_s *bfa) | |
50 | { | |
51 | struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs; | |
52 | void __iomem *kva = bfa_ioc_bar0(&bfa->ioc); | |
53 | ||
54 | bfa_regs->intr_status = (kva + CT2_HOSTFN_INT_STATUS); | |
55 | bfa_regs->intr_mask = (kva + CT2_HOSTFN_INTR_MASK); | |
7725ccfd JH |
56 | } |
57 | ||
f5713c5d KG |
58 | void |
59 | bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq) | |
60 | { | |
a36c61f9 | 61 | u32 r32; |
f5713c5d | 62 | |
53440260 JH |
63 | r32 = readl(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]); |
64 | writel(r32, bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]); | |
f5713c5d KG |
65 | } |
66 | ||
ca6e0ea7 KG |
67 | /* |
68 | * Actions to respond RME Interrupt for Catapult ASIC: | |
69 | * - Write 1 to Interrupt Status register (INTx only - done in bfa_intx()) | |
70 | * - Acknowledge by writing to RME Queue Control register | |
71 | * - Update CI | |
72 | */ | |
7725ccfd | 73 | void |
ca6e0ea7 | 74 | bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci) |
7725ccfd JH |
75 | { |
76 | u32 r32; | |
77 | ||
53440260 JH |
78 | r32 = readl(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]); |
79 | writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]); | |
ca6e0ea7 KG |
80 | |
81 | bfa_rspq_ci(bfa, rspq) = ci; | |
82 | writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]); | |
83 | mmiowb(); | |
84 | } | |
85 | ||
86 | /* | |
87 | * Actions to respond RME Interrupt for Catapult2 ASIC: | |
88 | * - Write 1 to Interrupt Status register (INTx only - done in bfa_intx()) | |
89 | * - Update CI | |
90 | */ | |
91 | void | |
92 | bfa_hwct2_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci) | |
93 | { | |
94 | bfa_rspq_ci(bfa, rspq) = ci; | |
95 | writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]); | |
96 | mmiowb(); | |
7725ccfd JH |
97 | } |
98 | ||
99 | void | |
100 | bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap, | |
101 | u32 *num_vecs, u32 *max_vec_bit) | |
102 | { | |
11189208 KG |
103 | *msix_vecs_bmap = (1 << BFI_MSIX_CT_MAX) - 1; |
104 | *max_vec_bit = (1 << (BFI_MSIX_CT_MAX - 1)); | |
105 | *num_vecs = BFI_MSIX_CT_MAX; | |
7725ccfd JH |
106 | } |
107 | ||
5fbe25c7 | 108 | /* |
7725ccfd JH |
109 | * Setup MSI-X vector for catapult |
110 | */ | |
111 | void | |
112 | bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs) | |
113 | { | |
11189208 | 114 | WARN_ON((nvecs != 1) && (nvecs != BFI_MSIX_CT_MAX)); |
7725ccfd JH |
115 | bfa_trc(bfa, nvecs); |
116 | ||
117 | bfa->msix.nvecs = nvecs; | |
118 | bfa_hwct_msix_uninstall(bfa); | |
119 | } | |
120 | ||
121 | void | |
775c7742 KG |
122 | bfa_hwct_msix_ctrl_install(struct bfa_s *bfa) |
123 | { | |
124 | if (bfa->msix.nvecs == 0) | |
125 | return; | |
126 | ||
127 | if (bfa->msix.nvecs == 1) | |
128 | bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_all; | |
129 | else | |
130 | bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_lpu_err; | |
131 | } | |
132 | ||
133 | void | |
134 | bfa_hwct_msix_queue_install(struct bfa_s *bfa) | |
7725ccfd JH |
135 | { |
136 | int i; | |
137 | ||
138 | if (bfa->msix.nvecs == 0) | |
139 | return; | |
140 | ||
141 | if (bfa->msix.nvecs == 1) { | |
775c7742 | 142 | for (i = BFI_MSIX_CPE_QMIN_CT; i < BFI_MSIX_CT_MAX; i++) |
7725ccfd JH |
143 | bfa->msix.handler[i] = bfa_msix_all; |
144 | return; | |
145 | } | |
146 | ||
11189208 | 147 | for (i = BFI_MSIX_CPE_QMIN_CT; i <= BFI_MSIX_CPE_QMAX_CT; i++) |
7725ccfd JH |
148 | bfa->msix.handler[i] = bfa_msix_reqq; |
149 | ||
11189208 | 150 | for (i = BFI_MSIX_RME_QMIN_CT; i <= BFI_MSIX_RME_QMAX_CT; i++) |
7725ccfd | 151 | bfa->msix.handler[i] = bfa_msix_rspq; |
7725ccfd JH |
152 | } |
153 | ||
154 | void | |
155 | bfa_hwct_msix_uninstall(struct bfa_s *bfa) | |
156 | { | |
157 | int i; | |
158 | ||
11189208 | 159 | for (i = 0; i < BFI_MSIX_CT_MAX; i++) |
7725ccfd JH |
160 | bfa->msix.handler[i] = bfa_hwct_msix_dummy; |
161 | } | |
162 | ||
5fbe25c7 | 163 | /* |
7725ccfd JH |
164 | * Enable MSI-X vectors |
165 | */ | |
166 | void | |
167 | bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix) | |
168 | { | |
169 | bfa_trc(bfa, 0); | |
7725ccfd JH |
170 | bfa_ioc_isr_mode_set(&bfa->ioc, msix); |
171 | } | |
172 | ||
36d345a7 JH |
173 | void |
174 | bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end) | |
175 | { | |
11189208 KG |
176 | *start = BFI_MSIX_RME_QMIN_CT; |
177 | *end = BFI_MSIX_RME_QMAX_CT; | |
36d345a7 | 178 | } |