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0a20de44 | 1 | /* |
a36c61f9 | 2 | * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. |
0a20de44 KG |
3 | * All rights reserved |
4 | * www.brocade.com | |
5 | * | |
6 | * Linux driver for Brocade Fibre Channel Host Bus Adapter. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License (GPL) Version 2 as | |
10 | * published by the Free Software Foundation | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | */ | |
17 | ||
f16a1750 | 18 | #include "bfad_drv.h" |
a36c61f9 | 19 | #include "bfa_ioc.h" |
11189208 | 20 | #include "bfi_reg.h" |
a36c61f9 | 21 | #include "bfa_defs.h" |
0a20de44 KG |
22 | |
23 | BFA_TRC_FILE(CNA, IOC_CB); | |
24 | ||
c679b599 VMG |
25 | #define bfa_ioc_cb_join_pos(__ioc) ((u32) (1 << BFA_IOC_CB_JOIN_SH)) |
26 | ||
0a20de44 KG |
27 | /* |
28 | * forward declarations | |
29 | */ | |
0a20de44 KG |
30 | static bfa_boolean_t bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc); |
31 | static void bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc); | |
0a20de44 KG |
32 | static void bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc); |
33 | static void bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc); | |
34 | static void bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix); | |
f1d584d7 | 35 | static void bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc); |
0a20de44 | 36 | static void bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc); |
45d7f0cc | 37 | static bfa_boolean_t bfa_ioc_cb_sync_start(struct bfa_ioc_s *ioc); |
f1d584d7 KG |
38 | static void bfa_ioc_cb_sync_join(struct bfa_ioc_s *ioc); |
39 | static void bfa_ioc_cb_sync_leave(struct bfa_ioc_s *ioc); | |
40 | static void bfa_ioc_cb_sync_ack(struct bfa_ioc_s *ioc); | |
41 | static bfa_boolean_t bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc); | |
c679b599 VMG |
42 | static void bfa_ioc_cb_set_cur_ioc_fwstate( |
43 | struct bfa_ioc_s *ioc, enum bfi_ioc_state fwstate); | |
44 | static enum bfi_ioc_state bfa_ioc_cb_get_cur_ioc_fwstate(struct bfa_ioc_s *ioc); | |
45 | static void bfa_ioc_cb_set_alt_ioc_fwstate( | |
46 | struct bfa_ioc_s *ioc, enum bfi_ioc_state fwstate); | |
47 | static enum bfi_ioc_state bfa_ioc_cb_get_alt_ioc_fwstate(struct bfa_ioc_s *ioc); | |
0a20de44 | 48 | |
52f94b6f | 49 | static struct bfa_ioc_hwif_s hwif_cb; |
0a20de44 | 50 | |
5fbe25c7 | 51 | /* |
0a20de44 KG |
52 | * Called from bfa_ioc_attach() to map asic specific calls. |
53 | */ | |
54 | void | |
55 | bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc) | |
56 | { | |
293f82d5 JH |
57 | hwif_cb.ioc_pll_init = bfa_ioc_cb_pll_init; |
58 | hwif_cb.ioc_firmware_lock = bfa_ioc_cb_firmware_lock; | |
59 | hwif_cb.ioc_firmware_unlock = bfa_ioc_cb_firmware_unlock; | |
60 | hwif_cb.ioc_reg_init = bfa_ioc_cb_reg_init; | |
61 | hwif_cb.ioc_map_port = bfa_ioc_cb_map_port; | |
62 | hwif_cb.ioc_isr_mode_set = bfa_ioc_cb_isr_mode_set; | |
f1d584d7 | 63 | hwif_cb.ioc_notify_fail = bfa_ioc_cb_notify_fail; |
293f82d5 | 64 | hwif_cb.ioc_ownership_reset = bfa_ioc_cb_ownership_reset; |
45d7f0cc | 65 | hwif_cb.ioc_sync_start = bfa_ioc_cb_sync_start; |
f1d584d7 KG |
66 | hwif_cb.ioc_sync_join = bfa_ioc_cb_sync_join; |
67 | hwif_cb.ioc_sync_leave = bfa_ioc_cb_sync_leave; | |
68 | hwif_cb.ioc_sync_ack = bfa_ioc_cb_sync_ack; | |
69 | hwif_cb.ioc_sync_complete = bfa_ioc_cb_sync_complete; | |
c679b599 VMG |
70 | hwif_cb.ioc_set_fwstate = bfa_ioc_cb_set_cur_ioc_fwstate; |
71 | hwif_cb.ioc_get_fwstate = bfa_ioc_cb_get_cur_ioc_fwstate; | |
72 | hwif_cb.ioc_set_alt_fwstate = bfa_ioc_cb_set_alt_ioc_fwstate; | |
73 | hwif_cb.ioc_get_alt_fwstate = bfa_ioc_cb_get_alt_ioc_fwstate; | |
0a20de44 | 74 | |
293f82d5 | 75 | ioc->ioc_hwif = &hwif_cb; |
0a20de44 KG |
76 | } |
77 | ||
8f4bfadd | 78 | /* |
0a20de44 KG |
79 | * Return true if firmware of current driver matches the running firmware. |
80 | */ | |
81 | static bfa_boolean_t | |
82 | bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc) | |
83 | { | |
28d358d0 VMG |
84 | enum bfi_ioc_state alt_fwstate, cur_fwstate; |
85 | struct bfi_ioc_image_hdr_s fwhdr; | |
86 | ||
87 | cur_fwstate = bfa_ioc_cb_get_cur_ioc_fwstate(ioc); | |
88 | bfa_trc(ioc, cur_fwstate); | |
89 | alt_fwstate = bfa_ioc_cb_get_alt_ioc_fwstate(ioc); | |
90 | bfa_trc(ioc, alt_fwstate); | |
91 | ||
92 | /* | |
93 | * Uninit implies this is the only driver as of now. | |
94 | */ | |
95 | if (cur_fwstate == BFI_IOC_UNINIT) | |
96 | return BFA_TRUE; | |
97 | /* | |
98 | * Check if another driver with a different firmware is active | |
99 | */ | |
100 | bfa_ioc_fwver_get(ioc, &fwhdr); | |
101 | if (!bfa_ioc_fwver_cmp(ioc, &fwhdr) && | |
102 | alt_fwstate != BFI_IOC_DISABLED) { | |
103 | bfa_trc(ioc, alt_fwstate); | |
104 | return BFA_FALSE; | |
105 | } | |
106 | ||
0a20de44 KG |
107 | return BFA_TRUE; |
108 | } | |
109 | ||
110 | static void | |
111 | bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc) | |
112 | { | |
113 | } | |
114 | ||
5fbe25c7 | 115 | /* |
0a20de44 KG |
116 | * Notify other functions on HB failure. |
117 | */ | |
118 | static void | |
f1d584d7 | 119 | bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc) |
0a20de44 | 120 | { |
11189208 | 121 | writel(~0U, ioc->ioc_regs.err_set); |
53440260 | 122 | readl(ioc->ioc_regs.err_set); |
0a20de44 KG |
123 | } |
124 | ||
5fbe25c7 | 125 | /* |
0a20de44 KG |
126 | * Host to LPU mailbox message addresses |
127 | */ | |
d1c61f8e | 128 | static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = { |
0a20de44 KG |
129 | { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 }, |
130 | { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 } | |
131 | }; | |
132 | ||
5fbe25c7 | 133 | /* |
0a20de44 KG |
134 | * Host <-> LPU mailbox command/status registers |
135 | */ | |
d1c61f8e | 136 | static struct { u32 hfn, lpu; } iocreg_mbcmd[] = { |
a36c61f9 | 137 | |
0a20de44 KG |
138 | { HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT }, |
139 | { HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT } | |
140 | }; | |
141 | ||
142 | static void | |
143 | bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc) | |
144 | { | |
53440260 | 145 | void __iomem *rb; |
0a20de44 KG |
146 | int pcifn = bfa_ioc_pcifn(ioc); |
147 | ||
148 | rb = bfa_ioc_bar0(ioc); | |
149 | ||
150 | ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox; | |
151 | ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox; | |
152 | ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn; | |
153 | ||
154 | if (ioc->port_id == 0) { | |
155 | ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG; | |
156 | ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG; | |
f1d584d7 | 157 | ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG; |
0a20de44 KG |
158 | } else { |
159 | ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG); | |
160 | ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG); | |
f1d584d7 | 161 | ioc->ioc_regs.alt_ioc_fwstate = (rb + BFA_IOC0_STATE_REG); |
0a20de44 KG |
162 | } |
163 | ||
5fbe25c7 | 164 | /* |
0a20de44 KG |
165 | * Host <-> LPU mailbox command/status registers |
166 | */ | |
167 | ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd[pcifn].hfn; | |
168 | ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd[pcifn].lpu; | |
169 | ||
170 | /* | |
171 | * PSS control registers | |
172 | */ | |
173 | ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); | |
8b651b42 | 174 | ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG); |
11189208 KG |
175 | ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG); |
176 | ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG); | |
0a20de44 KG |
177 | |
178 | /* | |
179 | * IOC semaphore registers and serialization | |
180 | */ | |
181 | ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG); | |
182 | ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG); | |
183 | ||
5fbe25c7 | 184 | /* |
0a20de44 KG |
185 | * sram memory access |
186 | */ | |
187 | ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START); | |
188 | ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CB; | |
189 | ||
190 | /* | |
191 | * err set reg : for notification of hb failure | |
192 | */ | |
193 | ioc->ioc_regs.err_set = (rb + ERR_SET_REG); | |
194 | } | |
195 | ||
5fbe25c7 | 196 | /* |
0a20de44 KG |
197 | * Initialize IOC to port mapping. |
198 | */ | |
a36c61f9 | 199 | |
0a20de44 KG |
200 | static void |
201 | bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc) | |
202 | { | |
5fbe25c7 | 203 | /* |
0a20de44 KG |
204 | * For crossbow, port id is same as pci function. |
205 | */ | |
206 | ioc->port_id = bfa_ioc_pcifn(ioc); | |
a36c61f9 | 207 | |
0a20de44 KG |
208 | bfa_trc(ioc, ioc->port_id); |
209 | } | |
210 | ||
5fbe25c7 | 211 | /* |
0a20de44 KG |
212 | * Set interrupt mode for a function: INTX or MSIX |
213 | */ | |
214 | static void | |
215 | bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix) | |
216 | { | |
217 | } | |
218 | ||
45d7f0cc JH |
219 | /* |
220 | * Synchronized IOC failure processing routines | |
221 | */ | |
222 | static bfa_boolean_t | |
223 | bfa_ioc_cb_sync_start(struct bfa_ioc_s *ioc) | |
224 | { | |
c679b599 VMG |
225 | u32 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate); |
226 | ||
227 | /** | |
228 | * Driver load time. If the join bit is set, | |
229 | * it is due to an unclean exit by the driver for this | |
230 | * PCI fn in the previous incarnation. Whoever comes here first | |
231 | * should clean it up, no matter which PCI fn. | |
232 | */ | |
233 | if (ioc_fwstate & BFA_IOC_CB_JOIN_MASK) { | |
234 | writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate); | |
235 | writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate); | |
236 | return BFA_TRUE; | |
237 | } | |
238 | ||
45d7f0cc JH |
239 | return bfa_ioc_cb_sync_complete(ioc); |
240 | } | |
241 | ||
5fbe25c7 | 242 | /* |
a36c61f9 KG |
243 | * Cleanup hw semaphore and usecnt registers |
244 | */ | |
245 | static void | |
246 | bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc) | |
0a20de44 | 247 | { |
0a20de44 KG |
248 | |
249 | /* | |
a36c61f9 KG |
250 | * Read the hw sem reg to make sure that it is locked |
251 | * before we clear it. If it is not locked, writing 1 | |
252 | * will lock it instead of clearing it. | |
0a20de44 | 253 | */ |
53440260 | 254 | readl(ioc->ioc_regs.ioc_sem_reg); |
f7f73812 | 255 | writel(1, ioc->ioc_regs.ioc_sem_reg); |
a36c61f9 KG |
256 | } |
257 | ||
8f4bfadd | 258 | /* |
f1d584d7 KG |
259 | * Synchronized IOC failure processing routines |
260 | */ | |
261 | static void | |
262 | bfa_ioc_cb_sync_join(struct bfa_ioc_s *ioc) | |
263 | { | |
c679b599 VMG |
264 | u32 r32 = readl(ioc->ioc_regs.ioc_fwstate); |
265 | u32 join_pos = bfa_ioc_cb_join_pos(ioc); | |
266 | ||
267 | writel((r32 | join_pos), ioc->ioc_regs.ioc_fwstate); | |
f1d584d7 KG |
268 | } |
269 | ||
270 | static void | |
271 | bfa_ioc_cb_sync_leave(struct bfa_ioc_s *ioc) | |
272 | { | |
c679b599 VMG |
273 | u32 r32 = readl(ioc->ioc_regs.ioc_fwstate); |
274 | u32 join_pos = bfa_ioc_cb_join_pos(ioc); | |
275 | ||
276 | writel((r32 & ~join_pos), ioc->ioc_regs.ioc_fwstate); | |
277 | } | |
278 | ||
279 | static void | |
280 | bfa_ioc_cb_set_cur_ioc_fwstate(struct bfa_ioc_s *ioc, | |
281 | enum bfi_ioc_state fwstate) | |
282 | { | |
283 | u32 r32 = readl(ioc->ioc_regs.ioc_fwstate); | |
284 | ||
285 | writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), | |
286 | ioc->ioc_regs.ioc_fwstate); | |
287 | } | |
288 | ||
289 | static enum bfi_ioc_state | |
290 | bfa_ioc_cb_get_cur_ioc_fwstate(struct bfa_ioc_s *ioc) | |
291 | { | |
292 | return (enum bfi_ioc_state)(readl(ioc->ioc_regs.ioc_fwstate) & | |
293 | BFA_IOC_CB_FWSTATE_MASK); | |
294 | } | |
295 | ||
296 | static void | |
297 | bfa_ioc_cb_set_alt_ioc_fwstate(struct bfa_ioc_s *ioc, | |
298 | enum bfi_ioc_state fwstate) | |
299 | { | |
300 | u32 r32 = readl(ioc->ioc_regs.alt_ioc_fwstate); | |
301 | ||
302 | writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), | |
303 | ioc->ioc_regs.alt_ioc_fwstate); | |
304 | } | |
305 | ||
306 | static enum bfi_ioc_state | |
307 | bfa_ioc_cb_get_alt_ioc_fwstate(struct bfa_ioc_s *ioc) | |
308 | { | |
309 | return (enum bfi_ioc_state)(readl(ioc->ioc_regs.alt_ioc_fwstate) & | |
310 | BFA_IOC_CB_FWSTATE_MASK); | |
f1d584d7 KG |
311 | } |
312 | ||
313 | static void | |
314 | bfa_ioc_cb_sync_ack(struct bfa_ioc_s *ioc) | |
315 | { | |
c679b599 | 316 | bfa_ioc_cb_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL); |
f1d584d7 KG |
317 | } |
318 | ||
319 | static bfa_boolean_t | |
320 | bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc) | |
321 | { | |
c679b599 VMG |
322 | u32 fwstate, alt_fwstate; |
323 | fwstate = bfa_ioc_cb_get_cur_ioc_fwstate(ioc); | |
a36c61f9 | 324 | |
8f4bfadd | 325 | /* |
f1d584d7 KG |
326 | * At this point, this IOC is hoding the hw sem in the |
327 | * start path (fwcheck) OR in the disable/enable path | |
328 | * OR to check if the other IOC has acknowledged failure. | |
329 | * | |
330 | * So, this IOC can be in UNINIT, INITING, DISABLED, FAIL | |
331 | * or in MEMTEST states. In a normal scenario, this IOC | |
332 | * can not be in OP state when this function is called. | |
333 | * | |
334 | * However, this IOC could still be in OP state when | |
335 | * the OS driver is starting up, if the OptROM code has | |
336 | * left it in that state. | |
337 | * | |
338 | * If we had marked this IOC's fwstate as BFI_IOC_FAIL | |
339 | * in the failure case and now, if the fwstate is not | |
340 | * BFI_IOC_FAIL it implies that the other PCI fn have | |
341 | * reinitialized the ASIC or this IOC got disabled, so | |
342 | * return TRUE. | |
343 | */ | |
344 | if (fwstate == BFI_IOC_UNINIT || | |
345 | fwstate == BFI_IOC_INITING || | |
346 | fwstate == BFI_IOC_DISABLED || | |
347 | fwstate == BFI_IOC_MEMTEST || | |
348 | fwstate == BFI_IOC_OP) | |
349 | return BFA_TRUE; | |
350 | else { | |
c679b599 | 351 | alt_fwstate = bfa_ioc_cb_get_alt_ioc_fwstate(ioc); |
f1d584d7 KG |
352 | if (alt_fwstate == BFI_IOC_FAIL || |
353 | alt_fwstate == BFI_IOC_DISABLED || | |
354 | alt_fwstate == BFI_IOC_UNINIT || | |
355 | alt_fwstate == BFI_IOC_INITING || | |
356 | alt_fwstate == BFI_IOC_MEMTEST) | |
357 | return BFA_TRUE; | |
358 | else | |
359 | return BFA_FALSE; | |
360 | } | |
361 | } | |
a36c61f9 KG |
362 | |
363 | bfa_status_t | |
11189208 | 364 | bfa_ioc_cb_pll_init(void __iomem *rb, enum bfi_asic_mode fcmode) |
a36c61f9 | 365 | { |
c679b599 | 366 | u32 pll_sclk, pll_fclk, join_bits; |
0a20de44 | 367 | |
11189208 KG |
368 | pll_sclk = __APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN | |
369 | __APP_PLL_SCLK_P0_1(3U) | | |
370 | __APP_PLL_SCLK_JITLMT0_1(3U) | | |
371 | __APP_PLL_SCLK_CNTLMT0_1(3U); | |
372 | pll_fclk = __APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN | | |
373 | __APP_PLL_LCLK_RSEL200500 | __APP_PLL_LCLK_P0_1(3U) | | |
374 | __APP_PLL_LCLK_JITLMT0_1(3U) | | |
375 | __APP_PLL_LCLK_CNTLMT0_1(3U); | |
c679b599 VMG |
376 | join_bits = readl(rb + BFA_IOC0_STATE_REG) & |
377 | BFA_IOC_CB_JOIN_MASK; | |
378 | writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC0_STATE_REG)); | |
379 | join_bits = readl(rb + BFA_IOC1_STATE_REG) & | |
380 | BFA_IOC_CB_JOIN_MASK; | |
381 | writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC1_STATE_REG)); | |
53440260 JH |
382 | writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); |
383 | writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); | |
384 | writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); | |
385 | writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); | |
386 | writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); | |
387 | writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); | |
11189208 KG |
388 | writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG); |
389 | writel(__APP_PLL_SCLK_BYPASS | __APP_PLL_SCLK_LOGIC_SOFT_RESET, | |
390 | rb + APP_PLL_SCLK_CTL_REG); | |
391 | writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG); | |
392 | writel(__APP_PLL_LCLK_BYPASS | __APP_PLL_LCLK_LOGIC_SOFT_RESET, | |
393 | rb + APP_PLL_LCLK_CTL_REG); | |
6a18b167 | 394 | udelay(2); |
11189208 KG |
395 | writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG); |
396 | writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG); | |
397 | writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET, | |
398 | rb + APP_PLL_SCLK_CTL_REG); | |
399 | writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET, | |
400 | rb + APP_PLL_LCLK_CTL_REG); | |
6a18b167 | 401 | udelay(2000); |
53440260 JH |
402 | writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); |
403 | writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); | |
11189208 KG |
404 | writel(pll_sclk, (rb + APP_PLL_SCLK_CTL_REG)); |
405 | writel(pll_fclk, (rb + APP_PLL_LCLK_CTL_REG)); | |
0a20de44 KG |
406 | |
407 | return BFA_STATUS_OK; | |
408 | } |