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Merge branch 'mlx4-next'
[deliverable/linux.git] / drivers / scsi / csiostor / csio_hw.c
CommitLineData
a3667aae
NKI		 1/*
2 * This file is part of the Chelsio FCoE driver for Linux.
3 *
4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/pci.h>
36#include <linux/pci_regs.h>
37#include <linux/firmware.h>
38#include <linux/stddef.h>
39#include <linux/delay.h>
40#include <linux/string.h>
41#include <linux/compiler.h>
42#include <linux/jiffies.h>
43#include <linux/kernel.h>
44#include <linux/log2.h>
45
46#include "csio_hw.h"
47#include "csio_lnode.h"
48#include "csio_rnode.h"
49
a3667aae
NKI		 50int csio_dbg_level = 0xFEFF;
51unsigned int csio_port_mask = 0xf;
52
53/* Default FW event queue entries. */
54static uint32_t csio_evtq_sz = CSIO_EVTQ_SIZE;
55
56/* Default MSI param level */
57int csio_msi = 2;
58
59/* FCoE function instances */
60static int dev_num;
61
62/* FCoE Adapter types & its description */
7cc16380
AB		 63static const struct csio_adap_desc csio_t5_fcoe_adapters[] = {
64 {"T580-Dbg 10G", "Chelsio T580-Dbg 10G [FCoE]"},
65 {"T520-CR 10G", "Chelsio T520-CR 10G [FCoE]"},
3fb4c22e 66 {"T522-CR 10G/1G", "Chelsio T522-CR 10G/1G [FCoE]"},
7cc16380
AB		 67 {"T540-CR 10G", "Chelsio T540-CR 10G [FCoE]"},
68 {"T520-BCH 10G", "Chelsio T520-BCH 10G [FCoE]"},
69 {"T540-BCH 10G", "Chelsio T540-BCH 10G [FCoE]"},
70 {"T540-CH 10G", "Chelsio T540-CH 10G [FCoE]"},
71 {"T520-SO 10G", "Chelsio T520-SO 10G [FCoE]"},
72 {"T520-CX4 10G", "Chelsio T520-CX4 10G [FCoE]"},
73 {"T520-BT 10G", "Chelsio T520-BT 10G [FCoE]"},
74 {"T504-BT 1G", "Chelsio T504-BT 1G [FCoE]"},
75 {"B520-SR 10G", "Chelsio B520-SR 10G [FCoE]"},
76 {"B504-BT 1G", "Chelsio B504-BT 1G [FCoE]"},
77 {"T580-CR 10G", "Chelsio T580-CR 10G [FCoE]"},
78 {"T540-LP-CR 10G", "Chelsio T540-LP-CR 10G [FCoE]"},
79 {"AMSTERDAM 10G", "Chelsio AMSTERDAM 10G [FCoE]"},
80 {"T580-LP-CR 40G", "Chelsio T580-LP-CR 40G [FCoE]"},
81 {"T520-LL-CR 10G", "Chelsio T520-LL-CR 10G [FCoE]"},
82 {"T560-CR 40G", "Chelsio T560-CR 40G [FCoE]"},
3fb4c22e
PM		 83 {"T580-CR 40G", "Chelsio T580-CR 40G [FCoE]"},
84 {"T580-SO 40G", "Chelsio T580-SO 40G [FCoE]"},
85 {"T502-BT 1G", "Chelsio T502-BT 1G [FCoE]"}
a3667aae
NKI		 86};
87
88static void csio_mgmtm_cleanup(struct csio_mgmtm *);
89static void csio_hw_mbm_cleanup(struct csio_hw *);
90
91/* State machine forward declarations */
92static void csio_hws_uninit(struct csio_hw *, enum csio_hw_ev);
93static void csio_hws_configuring(struct csio_hw *, enum csio_hw_ev);
94static void csio_hws_initializing(struct csio_hw *, enum csio_hw_ev);
95static void csio_hws_ready(struct csio_hw *, enum csio_hw_ev);
96static void csio_hws_quiescing(struct csio_hw *, enum csio_hw_ev);
97static void csio_hws_quiesced(struct csio_hw *, enum csio_hw_ev);
98static void csio_hws_resetting(struct csio_hw *, enum csio_hw_ev);
99static void csio_hws_removing(struct csio_hw *, enum csio_hw_ev);
100static void csio_hws_pcierr(struct csio_hw *, enum csio_hw_ev);
101
102static void csio_hw_initialize(struct csio_hw *hw);
103static void csio_evtq_stop(struct csio_hw *hw);
104static void csio_evtq_start(struct csio_hw *hw);
105
106int csio_is_hw_ready(struct csio_hw *hw)
107{
108 return csio_match_state(hw, csio_hws_ready);
109}
110
111int csio_is_hw_removing(struct csio_hw *hw)
112{
113 return csio_match_state(hw, csio_hws_removing);
114}
115
116
117/*
118 * csio_hw_wait_op_done_val - wait until an operation is completed
119 * @hw: the HW module
120 * @reg: the register to check for completion
121 * @mask: a single-bit field within @reg that indicates completion
122 * @polarity: the value of the field when the operation is completed
123 * @attempts: number of check iterations
124 * @delay: delay in usecs between iterations
125 * @valp: where to store the value of the register at completion time
126 *
127 * Wait until an operation is completed by checking a bit in a register
128 * up to @attempts times. If @valp is not NULL the value of the register
129 * at the time it indicated completion is stored there. Returns 0 if the
130 * operation completes and -EAGAIN otherwise.
131 */
7cc16380 132int
a3667aae
NKI		 133csio_hw_wait_op_done_val(struct csio_hw *hw, int reg, uint32_t mask,
134 int polarity, int attempts, int delay, uint32_t *valp)
135{
136 uint32_t val;
137 while (1) {
138 val = csio_rd_reg32(hw, reg);
139
140 if (!!(val & mask) == polarity) {
141 if (valp)
142 *valp = val;
143 return 0;
144 }
145
146 if (--attempts == 0)
147 return -EAGAIN;
148 if (delay)
149 udelay(delay);
150 }
151}
152
7cc16380
AB		 153/*
154 * csio_hw_tp_wr_bits_indirect - set/clear bits in an indirect TP register
155 * @hw: the adapter
156 * @addr: the indirect TP register address
157 * @mask: specifies the field within the register to modify
158 * @val: new value for the field
159 *
160 * Sets a field of an indirect TP register to the given value.
161 */
162void
163csio_hw_tp_wr_bits_indirect(struct csio_hw *hw, unsigned int addr,
164 unsigned int mask, unsigned int val)
165{
837e4a42
HS		 166 csio_wr_reg32(hw, addr, TP_PIO_ADDR_A);
167 val |= csio_rd_reg32(hw, TP_PIO_DATA_A) & ~mask;
168 csio_wr_reg32(hw, val, TP_PIO_DATA_A);
7cc16380
AB		 169}
170
a3667aae
NKI		 171void
172csio_set_reg_field(struct csio_hw *hw, uint32_t reg, uint32_t mask,
173 uint32_t value)
174{
175 uint32_t val = csio_rd_reg32(hw, reg) & ~mask;
176
177 csio_wr_reg32(hw, val | value, reg);
178 /* Flush */
179 csio_rd_reg32(hw, reg);
180
181}
182
a3667aae 183static int
5036f0a0 184csio_memory_write(struct csio_hw *hw, int mtype, u32 addr, u32 len, u32 *buf)
a3667aae 185{
7cc16380
AB		 186 return hw->chip_ops->chip_memory_rw(hw, MEMWIN_CSIOSTOR, mtype,
187 addr, len, buf, 0);
a3667aae
NKI		 188}
189
190/*
191 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
192 */
7cc16380
AB		 193#define EEPROM_MAX_RD_POLL 40
194#define EEPROM_MAX_WR_POLL 6
195#define EEPROM_STAT_ADDR 0x7bfc
196#define VPD_BASE 0x400
197#define VPD_BASE_OLD 0
198#define VPD_LEN 1024
a3667aae
NKI		 199#define VPD_INFO_FLD_HDR_SIZE 3
200
201/*
202 * csio_hw_seeprom_read - read a serial EEPROM location
203 * @hw: hw to read
204 * @addr: EEPROM virtual address
205 * @data: where to store the read data
206 *
207 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
208 * VPD capability. Note that this function must be called with a virtual
209 * address.
210 */
211static int
212csio_hw_seeprom_read(struct csio_hw *hw, uint32_t addr, uint32_t *data)
213{
214 uint16_t val = 0;
215 int attempts = EEPROM_MAX_RD_POLL;
216 uint32_t base = hw->params.pci.vpd_cap_addr;
217
218 if (addr >= EEPROMVSIZE || (addr & 3))
219 return -EINVAL;
220
221 pci_write_config_word(hw->pdev, base + PCI_VPD_ADDR, (uint16_t)addr);
222
223 do {
224 udelay(10);
225 pci_read_config_word(hw->pdev, base + PCI_VPD_ADDR, &val);
226 } while (!(val & PCI_VPD_ADDR_F) && --attempts);
227
228 if (!(val & PCI_VPD_ADDR_F)) {
229 csio_err(hw, "reading EEPROM address 0x%x failed\n", addr);
230 return -EINVAL;
231 }
232
233 pci_read_config_dword(hw->pdev, base + PCI_VPD_DATA, data);
78890ed7 234 *data = le32_to_cpu(*(__le32 *)data);
5036f0a0 235
a3667aae
NKI		 236 return 0;
237}
238
239/*
240 * Partial EEPROM Vital Product Data structure. Includes only the ID and
241 * VPD-R sections.
242 */
243struct t4_vpd_hdr {
244 u8 id_tag;
245 u8 id_len[2];
246 u8 id_data[ID_LEN];
247 u8 vpdr_tag;
248 u8 vpdr_len[2];
249};
250
251/*
252 * csio_hw_get_vpd_keyword_val - Locates an information field keyword in
253 * the VPD
254 * @v: Pointer to buffered vpd data structure
255 * @kw: The keyword to search for
256 *
257 * Returns the value of the information field keyword or
258 * -EINVAL otherwise.
259 */
260static int
261csio_hw_get_vpd_keyword_val(const struct t4_vpd_hdr *v, const char *kw)
262{
263 int32_t i;
264 int32_t offset , len;
265 const uint8_t *buf = &v->id_tag;
266 const uint8_t *vpdr_len = &v->vpdr_tag;
267 offset = sizeof(struct t4_vpd_hdr);
268 len = (uint16_t)vpdr_len[1] + ((uint16_t)vpdr_len[2] << 8);
269
270 if (len + sizeof(struct t4_vpd_hdr) > VPD_LEN)
271 return -EINVAL;
272
273 for (i = offset; (i + VPD_INFO_FLD_HDR_SIZE) <= (offset + len);) {
274 if (memcmp(buf + i , kw, 2) == 0) {
275 i += VPD_INFO_FLD_HDR_SIZE;
276 return i;
277 }
278
279 i += VPD_INFO_FLD_HDR_SIZE + buf[i+2];
280 }
281
282 return -EINVAL;
283}
284
285static int
286csio_pci_capability(struct pci_dev *pdev, int cap, int *pos)
287{
288 *pos = pci_find_capability(pdev, cap);
289 if (*pos)
290 return 0;
291
292 return -1;
293}
294
295/*
296 * csio_hw_get_vpd_params - read VPD parameters from VPD EEPROM
297 * @hw: HW module
298 * @p: where to store the parameters
299 *
300 * Reads card parameters stored in VPD EEPROM.
301 */
302static int
303csio_hw_get_vpd_params(struct csio_hw *hw, struct csio_vpd *p)
304{
305 int i, ret, ec, sn, addr;
306 uint8_t *vpd, csum;
307 const struct t4_vpd_hdr *v;
308 /* To get around compilation warning from strstrip */
309 char *s;
310
311 if (csio_is_valid_vpd(hw))
312 return 0;
313
314 ret = csio_pci_capability(hw->pdev, PCI_CAP_ID_VPD,
315 &hw->params.pci.vpd_cap_addr);
316 if (ret)
317 return -EINVAL;
318
319 vpd = kzalloc(VPD_LEN, GFP_ATOMIC);
320 if (vpd == NULL)
321 return -ENOMEM;
322
323 /*
324 * Card information normally starts at VPD_BASE but early cards had
325 * it at 0.
326 */
327 ret = csio_hw_seeprom_read(hw, VPD_BASE, (uint32_t *)(vpd));
328 addr = *vpd == 0x82 ? VPD_BASE : VPD_BASE_OLD;
329
330 for (i = 0; i < VPD_LEN; i += 4) {
331 ret = csio_hw_seeprom_read(hw, addr + i, (uint32_t *)(vpd + i));
332 if (ret) {
333 kfree(vpd);
334 return ret;
335 }
336 }
337
338 /* Reset the VPD flag! */
339 hw->flags &= (~CSIO_HWF_VPD_VALID);
340
341 v = (const struct t4_vpd_hdr *)vpd;
342
343#define FIND_VPD_KW(var, name) do { \
344 var = csio_hw_get_vpd_keyword_val(v, name); \
345 if (var < 0) { \
346 csio_err(hw, "missing VPD keyword " name "\n"); \
347 kfree(vpd); \
348 return -EINVAL; \
349 } \
350} while (0)
351
352 FIND_VPD_KW(i, "RV");
353 for (csum = 0; i >= 0; i--)
354 csum += vpd[i];
355
356 if (csum) {
357 csio_err(hw, "corrupted VPD EEPROM, actual csum %u\n", csum);
358 kfree(vpd);
359 return -EINVAL;
360 }
361 FIND_VPD_KW(ec, "EC");
362 FIND_VPD_KW(sn, "SN");
363#undef FIND_VPD_KW
364
365 memcpy(p->id, v->id_data, ID_LEN);
366 s = strstrip(p->id);
367 memcpy(p->ec, vpd + ec, EC_LEN);
368 s = strstrip(p->ec);
369 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2];
370 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
371 s = strstrip(p->sn);
372
373 csio_valid_vpd_copied(hw);
374
375 kfree(vpd);
376 return 0;
377}
378
379/*
380 * csio_hw_sf1_read - read data from the serial flash
381 * @hw: the HW module
382 * @byte_cnt: number of bytes to read
383 * @cont: whether another operation will be chained
384 * @lock: whether to lock SF for PL access only
385 * @valp: where to store the read data
386 *
387 * Reads up to 4 bytes of data from the serial flash. The location of
388 * the read needs to be specified prior to calling this by issuing the
389 * appropriate commands to the serial flash.
390 */
391static int
392csio_hw_sf1_read(struct csio_hw *hw, uint32_t byte_cnt, int32_t cont,
393 int32_t lock, uint32_t *valp)
394{
395 int ret;
396
397 if (!byte_cnt || byte_cnt > 4)
398 return -EINVAL;
0d804338 399 if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F)
a3667aae
NKI		 400 return -EBUSY;
401
0d804338
HS		 402 csio_wr_reg32(hw, SF_LOCK_V(lock) | SF_CONT_V(cont) |
403 BYTECNT_V(byte_cnt - 1), SF_OP_A);
404 ret = csio_hw_wait_op_done_val(hw, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS,
405 10, NULL);
a3667aae 406 if (!ret)
0d804338 407 *valp = csio_rd_reg32(hw, SF_DATA_A);
a3667aae
NKI		 408 return ret;
409}
410
411/*
412 * csio_hw_sf1_write - write data to the serial flash
413 * @hw: the HW module
414 * @byte_cnt: number of bytes to write
415 * @cont: whether another operation will be chained
416 * @lock: whether to lock SF for PL access only
417 * @val: value to write
418 *
419 * Writes up to 4 bytes of data to the serial flash. The location of
420 * the write needs to be specified prior to calling this by issuing the
421 * appropriate commands to the serial flash.
422 */
423static int
424csio_hw_sf1_write(struct csio_hw *hw, uint32_t byte_cnt, uint32_t cont,
425 int32_t lock, uint32_t val)
426{
427 if (!byte_cnt || byte_cnt > 4)
428 return -EINVAL;
0d804338 429 if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F)
a3667aae
NKI		 430 return -EBUSY;
431
0d804338
HS		 432 csio_wr_reg32(hw, val, SF_DATA_A);
433 csio_wr_reg32(hw, SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) |
434 OP_V(1) | SF_LOCK_V(lock), SF_OP_A);
a3667aae 435
0d804338 436 return csio_hw_wait_op_done_val(hw, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS,
a3667aae
NKI		 437 10, NULL);
438}
439
440/*
441 * csio_hw_flash_wait_op - wait for a flash operation to complete
442 * @hw: the HW module
443 * @attempts: max number of polls of the status register
444 * @delay: delay between polls in ms
445 *
446 * Wait for a flash operation to complete by polling the status register.
447 */
448static int
449csio_hw_flash_wait_op(struct csio_hw *hw, int32_t attempts, int32_t delay)
450{
451 int ret;
452 uint32_t status;
453
454 while (1) {
455 ret = csio_hw_sf1_write(hw, 1, 1, 1, SF_RD_STATUS);
456 if (ret != 0)
457 return ret;
458
459 ret = csio_hw_sf1_read(hw, 1, 0, 1, &status);
460 if (ret != 0)
461 return ret;
462
463 if (!(status & 1))
464 return 0;
465 if (--attempts == 0)
466 return -EAGAIN;
467 if (delay)
468 msleep(delay);
469 }
470}
471
472/*
473 * csio_hw_read_flash - read words from serial flash
474 * @hw: the HW module
475 * @addr: the start address for the read
476 * @nwords: how many 32-bit words to read
477 * @data: where to store the read data
478 * @byte_oriented: whether to store data as bytes or as words
479 *
480 * Read the specified number of 32-bit words from the serial flash.
481 * If @byte_oriented is set the read data is stored as a byte array
482 * (i.e., big-endian), otherwise as 32-bit words in the platform's
483 * natural endianess.
484 */
485static int
486csio_hw_read_flash(struct csio_hw *hw, uint32_t addr, uint32_t nwords,
487 uint32_t *data, int32_t byte_oriented)
488{
489 int ret;
490
491 if (addr + nwords * sizeof(uint32_t) > hw->params.sf_size || (addr & 3))
492 return -EINVAL;
493
494 addr = swab32(addr) | SF_RD_DATA_FAST;
495
496 ret = csio_hw_sf1_write(hw, 4, 1, 0, addr);
497 if (ret != 0)
498 return ret;
499
500 ret = csio_hw_sf1_read(hw, 1, 1, 0, data);
501 if (ret != 0)
502 return ret;
503
504 for ( ; nwords; nwords--, data++) {
505 ret = csio_hw_sf1_read(hw, 4, nwords > 1, nwords == 1, data);
506 if (nwords == 1)
0d804338 507 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
a3667aae
NKI		 508 if (ret)
509 return ret;
510 if (byte_oriented)
78890ed7 511 *data = (__force __u32) htonl(*data);
a3667aae
NKI		 512 }
513 return 0;
514}
515
516/*
517 * csio_hw_write_flash - write up to a page of data to the serial flash
518 * @hw: the hw
519 * @addr: the start address to write
520 * @n: length of data to write in bytes
521 * @data: the data to write
522 *
523 * Writes up to a page of data (256 bytes) to the serial flash starting
524 * at the given address. All the data must be written to the same page.
525 */
526static int
527csio_hw_write_flash(struct csio_hw *hw, uint32_t addr,
528 uint32_t n, const uint8_t *data)
529{
530 int ret = -EINVAL;
531 uint32_t buf[64];
532 uint32_t i, c, left, val, offset = addr & 0xff;
533
534 if (addr >= hw->params.sf_size || offset + n > SF_PAGE_SIZE)
535 return -EINVAL;
536
537 val = swab32(addr) | SF_PROG_PAGE;
538
539 ret = csio_hw_sf1_write(hw, 1, 0, 1, SF_WR_ENABLE);
540 if (ret != 0)
541 goto unlock;
542
543 ret = csio_hw_sf1_write(hw, 4, 1, 1, val);
544 if (ret != 0)
545 goto unlock;
546
547 for (left = n; left; left -= c) {
548 c = min(left, 4U);
549 for (val = 0, i = 0; i < c; ++i)
550 val = (val << 8) + *data++;
551
552 ret = csio_hw_sf1_write(hw, c, c != left, 1, val);
553 if (ret)
554 goto unlock;
555 }
556 ret = csio_hw_flash_wait_op(hw, 8, 1);
557 if (ret)
558 goto unlock;
559
0d804338 560 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
a3667aae
NKI		 561
562 /* Read the page to verify the write succeeded */
563 ret = csio_hw_read_flash(hw, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
564 if (ret)
565 return ret;
566
567 if (memcmp(data - n, (uint8_t *)buf + offset, n)) {
568 csio_err(hw,
569 "failed to correctly write the flash page at %#x\n",
570 addr);
571 return -EINVAL;
572 }
573
574 return 0;
575
576unlock:
0d804338 577 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
a3667aae
NKI		 578 return ret;
579}
580
581/*
582 * csio_hw_flash_erase_sectors - erase a range of flash sectors
583 * @hw: the HW module
584 * @start: the first sector to erase
585 * @end: the last sector to erase
586 *
587 * Erases the sectors in the given inclusive range.
588 */
589static int
590csio_hw_flash_erase_sectors(struct csio_hw *hw, int32_t start, int32_t end)
591{
592 int ret = 0;
593
594 while (start <= end) {
595
596 ret = csio_hw_sf1_write(hw, 1, 0, 1, SF_WR_ENABLE);
597 if (ret != 0)
598 goto out;
599
600 ret = csio_hw_sf1_write(hw, 4, 0, 1,
601 SF_ERASE_SECTOR | (start << 8));
602 if (ret != 0)
603 goto out;
604
605 ret = csio_hw_flash_wait_op(hw, 14, 500);
606 if (ret != 0)
607 goto out;
608
609 start++;
610 }
611out:
612 if (ret)
613 csio_err(hw, "erase of flash sector %d failed, error %d\n",
614 start, ret);
0d804338 615 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
a3667aae
NKI		 616 return 0;
617}
618
a3667aae
NKI		 619static void
620csio_hw_print_fw_version(struct csio_hw *hw, char *str)
621{
622 csio_info(hw, "%s: %u.%u.%u.%u\n", str,
b2e1a3f0
HS		 623 FW_HDR_FW_VER_MAJOR_G(hw->fwrev),
624 FW_HDR_FW_VER_MINOR_G(hw->fwrev),
625 FW_HDR_FW_VER_MICRO_G(hw->fwrev),
626 FW_HDR_FW_VER_BUILD_G(hw->fwrev));
a3667aae
NKI		 627}
628
629/*
630 * csio_hw_get_fw_version - read the firmware version
631 * @hw: HW module
632 * @vers: where to place the version
633 *
634 * Reads the FW version from flash.
635 */
636static int
637csio_hw_get_fw_version(struct csio_hw *hw, uint32_t *vers)
638{
639 return csio_hw_read_flash(hw, FW_IMG_START +
640 offsetof(struct fw_hdr, fw_ver), 1,
641 vers, 0);
642}
643
644/*
645 * csio_hw_get_tp_version - read the TP microcode version
646 * @hw: HW module
647 * @vers: where to place the version
648 *
649 * Reads the TP microcode version from flash.
650 */
651static int
652csio_hw_get_tp_version(struct csio_hw *hw, u32 *vers)
653{
654 return csio_hw_read_flash(hw, FLASH_FW_START +
655 offsetof(struct fw_hdr, tp_microcode_ver), 1,
656 vers, 0);
657}
658
a3667aae
NKI		 659/*
660 * csio_hw_fw_dload - download firmware.
661 * @hw: HW module
662 * @fw_data: firmware image to write.
663 * @size: image size
664 *
665 * Write the supplied firmware image to the card's serial flash.
666 */
667static int
668csio_hw_fw_dload(struct csio_hw *hw, uint8_t *fw_data, uint32_t size)
669{
670 uint32_t csum;
671 int32_t addr;
672 int ret;
673 uint32_t i;
674 uint8_t first_page[SF_PAGE_SIZE];
5036f0a0 675 const __be32 *p = (const __be32 *)fw_data;
a3667aae
NKI		 676 struct fw_hdr *hdr = (struct fw_hdr *)fw_data;
677 uint32_t sf_sec_size;
678
679 if ((!hw->params.sf_size) || (!hw->params.sf_nsec)) {
680 csio_err(hw, "Serial Flash data invalid\n");
681 return -EINVAL;
682 }
683
684 if (!size) {
685 csio_err(hw, "FW image has no data\n");
686 return -EINVAL;
687 }
688
689 if (size & 511) {
690 csio_err(hw, "FW image size not multiple of 512 bytes\n");
691 return -EINVAL;
692 }
693
694 if (ntohs(hdr->len512) * 512 != size) {
695 csio_err(hw, "FW image size differs from size in FW header\n");
696 return -EINVAL;
697 }
698
699 if (size > FW_MAX_SIZE) {
700 csio_err(hw, "FW image too large, max is %u bytes\n",
701 FW_MAX_SIZE);
702 return -EINVAL;
703 }
704
705 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
706 csum += ntohl(p[i]);
707
708 if (csum != 0xffffffff) {
709 csio_err(hw, "corrupted firmware image, checksum %#x\n", csum);
710 return -EINVAL;
711 }
712
713 sf_sec_size = hw->params.sf_size / hw->params.sf_nsec;
714 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
715
716 csio_dbg(hw, "Erasing sectors... start:%d end:%d\n",
717 FW_START_SEC, FW_START_SEC + i - 1);
718
719 ret = csio_hw_flash_erase_sectors(hw, FW_START_SEC,
720 FW_START_SEC + i - 1);
721 if (ret) {
722 csio_err(hw, "Flash Erase failed\n");
723 goto out;
724 }
725
726 /*
727 * We write the correct version at the end so the driver can see a bad
728 * version if the FW write fails. Start by writing a copy of the
729 * first page with a bad version.
730 */
731 memcpy(first_page, fw_data, SF_PAGE_SIZE);
732 ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff);
733 ret = csio_hw_write_flash(hw, FW_IMG_START, SF_PAGE_SIZE, first_page);
734 if (ret)
735 goto out;
736
737 csio_dbg(hw, "Writing Flash .. start:%d end:%d\n",
738 FW_IMG_START, FW_IMG_START + size);
739
740 addr = FW_IMG_START;
741 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
742 addr += SF_PAGE_SIZE;
743 fw_data += SF_PAGE_SIZE;
744 ret = csio_hw_write_flash(hw, addr, SF_PAGE_SIZE, fw_data);
745 if (ret)
746 goto out;
747 }
748
749 ret = csio_hw_write_flash(hw,
750 FW_IMG_START +
751 offsetof(struct fw_hdr, fw_ver),
752 sizeof(hdr->fw_ver),
753 (const uint8_t *)&hdr->fw_ver);
754
755out:
756 if (ret)
757 csio_err(hw, "firmware download failed, error %d\n", ret);
758 return ret;
759}
760
761static int
762csio_hw_get_flash_params(struct csio_hw *hw)
763{
764 int ret;
765 uint32_t info = 0;
766
767 ret = csio_hw_sf1_write(hw, 1, 1, 0, SF_RD_ID);
768 if (!ret)
769 ret = csio_hw_sf1_read(hw, 3, 0, 1, &info);
0d804338 770 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
a3667aae
NKI		 771 if (ret != 0)
772 return ret;
773
774 if ((info & 0xff) != 0x20) /* not a Numonix flash */
775 return -EINVAL;
776 info >>= 16; /* log2 of size */
777 if (info >= 0x14 && info < 0x18)
778 hw->params.sf_nsec = 1 << (info - 16);
779 else if (info == 0x18)
780 hw->params.sf_nsec = 64;
781 else
782 return -EINVAL;
783 hw->params.sf_size = 1 << info;
784
785 return 0;
786}
787
a3667aae
NKI		 788/*****************************************************************************/
789/* HW State machine assists */
790/*****************************************************************************/
791
792static int
793csio_hw_dev_ready(struct csio_hw *hw)
794{
795 uint32_t reg;
796 int cnt = 6;
797
0d804338
HS		 798 while (((reg = csio_rd_reg32(hw, PL_WHOAMI_A)) == 0xFFFFFFFF) &&
799 (--cnt != 0))
a3667aae
NKI		 800 mdelay(100);
801
0d804338
HS		 802 if ((cnt == 0) && (((int32_t)(SOURCEPF_G(reg)) < 0) ||
803 (SOURCEPF_G(reg) >= CSIO_MAX_PFN))) {
a3667aae
NKI		 804 csio_err(hw, "PL_WHOAMI returned 0x%x, cnt:%d\n", reg, cnt);
805 return -EIO;
806 }
807
0d804338 808 hw->pfn = SOURCEPF_G(reg);
a3667aae
NKI		 809
810 return 0;
811}
812
813/*
814 * csio_do_hello - Perform the HELLO FW Mailbox command and process response.
815 * @hw: HW module
816 * @state: Device state
817 *
818 * FW_HELLO_CMD has to be polled for completion.
819 */
820static int
821csio_do_hello(struct csio_hw *hw, enum csio_dev_state *state)
822{
823 struct csio_mb *mbp;
824 int rv = 0;
a3667aae
NKI		 825 enum fw_retval retval;
826 uint8_t mpfn;
827 char state_str[16];
828 int retries = FW_CMD_HELLO_RETRIES;
829
830 memset(state_str, 0, sizeof(state_str));
831
832 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
833 if (!mbp) {
834 rv = -ENOMEM;
835 CSIO_INC_STATS(hw, n_err_nomem);
836 goto out;
837 }
838
a3667aae
NKI		 839retry:
840 csio_mb_hello(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn,
666224d4 841 hw->pfn, CSIO_MASTER_MAY, NULL);
a3667aae
NKI		 842
843 rv = csio_mb_issue(hw, mbp);
844 if (rv) {
845 csio_err(hw, "failed to issue HELLO cmd. ret:%d.\n", rv);
846 goto out_free_mb;
847 }
848
849 csio_mb_process_hello_rsp(hw, mbp, &retval, state, &mpfn);
850 if (retval != FW_SUCCESS) {
851 csio_err(hw, "HELLO cmd failed with ret: %d\n", retval);
852 rv = -EINVAL;
853 goto out_free_mb;
854 }
855
856 /* Firmware has designated us to be master */
857 if (hw->pfn == mpfn) {
858 hw->flags |= CSIO_HWF_MASTER;
859 } else if (*state == CSIO_DEV_STATE_UNINIT) {
860 /*
861 * If we're not the Master PF then we need to wait around for
862 * the Master PF Driver to finish setting up the adapter.
863 *
864 * Note that we also do this wait if we're a non-Master-capable
865 * PF and there is no current Master PF; a Master PF may show up
866 * momentarily and we wouldn't want to fail pointlessly. (This
867 * can happen when an OS loads lots of different drivers rapidly
868 * at the same time). In this case, the Master PF returned by
869 * the firmware will be PCIE_FW_MASTER_MASK so the test below
870 * will work ...
871 */
872
873 int waiting = FW_CMD_HELLO_TIMEOUT;
874
875 /*
876 * Wait for the firmware to either indicate an error or
877 * initialized state. If we see either of these we bail out
878 * and report the issue to the caller. If we exhaust the
879 * "hello timeout" and we haven't exhausted our retries, try
880 * again. Otherwise bail with a timeout error.
881 */
882 for (;;) {
883 uint32_t pcie_fw;
884
7cc16380 885 spin_unlock_irq(&hw->lock);
a3667aae 886 msleep(50);
7cc16380 887 spin_lock_irq(&hw->lock);
a3667aae
NKI		 888 waiting -= 50;
889
890 /*
891 * If neither Error nor Initialialized are indicated
892 * by the firmware keep waiting till we exaust our
893 * timeout ... and then retry if we haven't exhausted
894 * our retries ...
895 */
f061de42
HS		 896 pcie_fw = csio_rd_reg32(hw, PCIE_FW_A);
897 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
a3667aae
NKI		 898 if (waiting <= 0) {
899 if (retries-- > 0)
900 goto retry;
901
902 rv = -ETIMEDOUT;
903 break;
904 }
905 continue;
906 }
907
908 /*
909 * We either have an Error or Initialized condition
910 * report errors preferentially.
911 */
912 if (state) {
f061de42 913 if (pcie_fw & PCIE_FW_ERR_F) {
a3667aae
NKI		 914 *state = CSIO_DEV_STATE_ERR;
915 rv = -ETIMEDOUT;
f061de42 916 } else if (pcie_fw & PCIE_FW_INIT_F)
a3667aae
NKI		 917 *state = CSIO_DEV_STATE_INIT;
918 }
919
920 /*
921 * If we arrived before a Master PF was selected and
922 * there's not a valid Master PF, grab its identity
923 * for our caller.
924 */
f061de42
HS		 925 if (mpfn == PCIE_FW_MASTER_M &&
926 (pcie_fw & PCIE_FW_MASTER_VLD_F))
927 mpfn = PCIE_FW_MASTER_G(pcie_fw);
a3667aae
NKI		 928 break;
929 }
930 hw->flags &= ~CSIO_HWF_MASTER;
931 }
932
933 switch (*state) {
934 case CSIO_DEV_STATE_UNINIT:
935 strcpy(state_str, "Initializing");
936 break;
937 case CSIO_DEV_STATE_INIT:
938 strcpy(state_str, "Initialized");
939 break;
940 case CSIO_DEV_STATE_ERR:
941 strcpy(state_str, "Error");
942 break;
943 default:
944 strcpy(state_str, "Unknown");
945 break;
946 }
947
948 if (hw->pfn == mpfn)
949 csio_info(hw, "PF: %d, Coming up as MASTER, HW state: %s\n",
950 hw->pfn, state_str);
951 else
952 csio_info(hw,
953 "PF: %d, Coming up as SLAVE, Master PF: %d, HW state: %s\n",
954 hw->pfn, mpfn, state_str);
955
956out_free_mb:
957 mempool_free(mbp, hw->mb_mempool);
958out:
959 return rv;
960}
961
962/*
963 * csio_do_bye - Perform the BYE FW Mailbox command and process response.
964 * @hw: HW module
965 *
966 */
967static int
968csio_do_bye(struct csio_hw *hw)
969{
970 struct csio_mb *mbp;
971 enum fw_retval retval;
972
973 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
974 if (!mbp) {
975 CSIO_INC_STATS(hw, n_err_nomem);
976 return -ENOMEM;
977 }
978
979 csio_mb_bye(hw, mbp, CSIO_MB_DEFAULT_TMO, NULL);
980
981 if (csio_mb_issue(hw, mbp)) {
982 csio_err(hw, "Issue of BYE command failed\n");
983 mempool_free(mbp, hw->mb_mempool);
984 return -EINVAL;
985 }
986
987 retval = csio_mb_fw_retval(mbp);
988 if (retval != FW_SUCCESS) {
989 mempool_free(mbp, hw->mb_mempool);
990 return -EINVAL;
991 }
992
993 mempool_free(mbp, hw->mb_mempool);
994
995 return 0;
996}
997
998/*
999 * csio_do_reset- Perform the device reset.
1000 * @hw: HW module
1001 * @fw_rst: FW reset
1002 *
1003 * If fw_rst is set, issues FW reset mbox cmd otherwise
1004 * does PIO reset.
1005 * Performs reset of the function.
1006 */
1007static int
1008csio_do_reset(struct csio_hw *hw, bool fw_rst)
1009{
1010 struct csio_mb *mbp;
1011 enum fw_retval retval;
1012
1013 if (!fw_rst) {
1014 /* PIO reset */
0d804338 1015 csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A);
a3667aae
NKI		 1016 mdelay(2000);
1017 return 0;
1018 }
1019
1020 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1021 if (!mbp) {
1022 CSIO_INC_STATS(hw, n_err_nomem);
1023 return -ENOMEM;
1024 }
1025
1026 csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO,
0d804338 1027 PIORSTMODE_F | PIORST_F, 0, NULL);
a3667aae
NKI		 1028
1029 if (csio_mb_issue(hw, mbp)) {
1030 csio_err(hw, "Issue of RESET command failed.n");
1031 mempool_free(mbp, hw->mb_mempool);
1032 return -EINVAL;
1033 }
1034
1035 retval = csio_mb_fw_retval(mbp);
1036 if (retval != FW_SUCCESS) {
1037 csio_err(hw, "RESET cmd failed with ret:0x%x.\n", retval);
1038 mempool_free(mbp, hw->mb_mempool);
1039 return -EINVAL;
1040 }
1041
1042 mempool_free(mbp, hw->mb_mempool);
1043
1044 return 0;
1045}
1046
1047static int
1048csio_hw_validate_caps(struct csio_hw *hw, struct csio_mb *mbp)
1049{
1050 struct fw_caps_config_cmd *rsp = (struct fw_caps_config_cmd *)mbp->mb;
1051 uint16_t caps;
1052
1053 caps = ntohs(rsp->fcoecaps);
1054
1055 if (!(caps & FW_CAPS_CONFIG_FCOE_INITIATOR)) {
1056 csio_err(hw, "No FCoE Initiator capability in the firmware.\n");
1057 return -EINVAL;
1058 }
1059
1060 if (!(caps & FW_CAPS_CONFIG_FCOE_CTRL_OFLD)) {
1061 csio_err(hw, "No FCoE Control Offload capability\n");
1062 return -EINVAL;
1063 }
1064
1065 return 0;
1066}
1067
1068/*
1069 * csio_hw_fw_halt - issue a reset/halt to FW and put uP into RESET
1070 * @hw: the HW module
1071 * @mbox: mailbox to use for the FW RESET command (if desired)
1072 * @force: force uP into RESET even if FW RESET command fails
1073 *
1074 * Issues a RESET command to firmware (if desired) with a HALT indication
1075 * and then puts the microprocessor into RESET state. The RESET command
1076 * will only be issued if a legitimate mailbox is provided (mbox <=
1077 * PCIE_FW_MASTER_MASK).
1078 *
1079 * This is generally used in order for the host to safely manipulate the
1080 * adapter without fear of conflicting with whatever the firmware might
1081 * be doing. The only way out of this state is to RESTART the firmware
1082 * ...
1083 */
1084static int
1085csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force)
1086{
1087 enum fw_retval retval = 0;
1088
1089 /*
1090 * If a legitimate mailbox is provided, issue a RESET command
1091 * with a HALT indication.
1092 */
f061de42 1093 if (mbox <= PCIE_FW_MASTER_M) {
a3667aae
NKI		 1094 struct csio_mb *mbp;
1095
1096 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1097 if (!mbp) {
1098 CSIO_INC_STATS(hw, n_err_nomem);
1099 return -ENOMEM;
1100 }
1101
1102 csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO,
0d804338 1103 PIORSTMODE_F | PIORST_F, FW_RESET_CMD_HALT_F,
a3667aae
NKI		 1104 NULL);
1105
1106 if (csio_mb_issue(hw, mbp)) {
1107 csio_err(hw, "Issue of RESET command failed!\n");
1108 mempool_free(mbp, hw->mb_mempool);
1109 return -EINVAL;
1110 }
1111
1112 retval = csio_mb_fw_retval(mbp);
1113 mempool_free(mbp, hw->mb_mempool);
1114 }
1115
1116 /*
1117 * Normally we won't complete the operation if the firmware RESET
1118 * command fails but if our caller insists we'll go ahead and put the
1119 * uP into RESET. This can be useful if the firmware is hung or even
1120 * missing ... We'll have to take the risk of putting the uP into
1121 * RESET without the cooperation of firmware in that case.
1122 *
1123 * We also force the firmware's HALT flag to be on in case we bypassed
1124 * the firmware RESET command above or we're dealing with old firmware
1125 * which doesn't have the HALT capability. This will serve as a flag
1126 * for the incoming firmware to know that it's coming out of a HALT
1127 * rather than a RESET ... if it's new enough to understand that ...
1128 */
1129 if (retval == 0 || force) {
89c3a86c 1130 csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
f061de42
HS		 1131 csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F,
1132 PCIE_FW_HALT_F);
a3667aae
NKI		 1133 }
1134
1135 /*
1136 * And we always return the result of the firmware RESET command
1137 * even when we force the uP into RESET ...
1138 */
1139 return retval ? -EINVAL : 0;
1140}
1141
1142/*
1143 * csio_hw_fw_restart - restart the firmware by taking the uP out of RESET
1144 * @hw: the HW module
1145 * @reset: if we want to do a RESET to restart things
1146 *
1147 * Restart firmware previously halted by csio_hw_fw_halt(). On successful
1148 * return the previous PF Master remains as the new PF Master and there
1149 * is no need to issue a new HELLO command, etc.
1150 *
1151 * We do this in two ways:
1152 *
1153 * 1. If we're dealing with newer firmware we'll simply want to take
1154 * the chip's microprocessor out of RESET. This will cause the
1155 * firmware to start up from its start vector. And then we'll loop
1156 * until the firmware indicates it's started again (PCIE_FW.HALT
1157 * reset to 0) or we timeout.
1158 *
1159 * 2. If we're dealing with older firmware then we'll need to RESET
1160 * the chip since older firmware won't recognize the PCIE_FW.HALT
1161 * flag and automatically RESET itself on startup.
1162 */
1163static int
1164csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset)
1165{
1166 if (reset) {
1167 /*
1168 * Since we're directing the RESET instead of the firmware
1169 * doing it automatically, we need to clear the PCIE_FW.HALT
1170 * bit.
1171 */
f061de42 1172 csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F, 0);
a3667aae
NKI		 1173
1174 /*
1175 * If we've been given a valid mailbox, first try to get the
1176 * firmware to do the RESET. If that works, great and we can
1177 * return success. Otherwise, if we haven't been given a
1178 * valid mailbox or the RESET command failed, fall back to
1179 * hitting the chip with a hammer.
1180 */
f061de42 1181 if (mbox <= PCIE_FW_MASTER_M) {
89c3a86c 1182 csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, 0);
a3667aae
NKI		 1183 msleep(100);
1184 if (csio_do_reset(hw, true) == 0)
1185 return 0;
1186 }
1187
0d804338 1188 csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A);
a3667aae
NKI		 1189 msleep(2000);
1190 } else {
1191 int ms;
1192
89c3a86c 1193 csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, 0);
a3667aae 1194 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
f061de42 1195 if (!(csio_rd_reg32(hw, PCIE_FW_A) & PCIE_FW_HALT_F))
a3667aae
NKI		 1196 return 0;
1197 msleep(100);
1198 ms += 100;
1199 }
1200 return -ETIMEDOUT;
1201 }
1202 return 0;
1203}
1204
1205/*
1206 * csio_hw_fw_upgrade - perform all of the steps necessary to upgrade FW
1207 * @hw: the HW module
1208 * @mbox: mailbox to use for the FW RESET command (if desired)
1209 * @fw_data: the firmware image to write
1210 * @size: image size
1211 * @force: force upgrade even if firmware doesn't cooperate
1212 *
1213 * Perform all of the steps necessary for upgrading an adapter's
1214 * firmware image. Normally this requires the cooperation of the
1215 * existing firmware in order to halt all existing activities
1216 * but if an invalid mailbox token is passed in we skip that step
1217 * (though we'll still put the adapter microprocessor into RESET in
1218 * that case).
1219 *
1220 * On successful return the new firmware will have been loaded and
1221 * the adapter will have been fully RESET losing all previous setup
1222 * state. On unsuccessful return the adapter may be completely hosed ...
1223 * positive errno indicates that the adapter is ~probably~ intact, a
1224 * negative errno indicates that things are looking bad ...
1225 */
1226static int
1227csio_hw_fw_upgrade(struct csio_hw *hw, uint32_t mbox,
1228 const u8 *fw_data, uint32_t size, int32_t force)
1229{
1230 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
1231 int reset, ret;
1232
1233 ret = csio_hw_fw_halt(hw, mbox, force);
1234 if (ret != 0 && !force)
1235 return ret;
1236
1237 ret = csio_hw_fw_dload(hw, (uint8_t *) fw_data, size);
1238 if (ret != 0)
1239 return ret;
1240
1241 /*
1242 * Older versions of the firmware don't understand the new
1243 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
1244 * restart. So for newly loaded older firmware we'll have to do the
1245 * RESET for it so it starts up on a clean slate. We can tell if
1246 * the newly loaded firmware will handle this right by checking
1247 * its header flags to see if it advertises the capability.
1248 */
1249 reset = ((ntohl(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
1250 return csio_hw_fw_restart(hw, mbox, reset);
1251}
1252
1253
1254/*
1255 * csio_hw_fw_config_file - setup an adapter via a Configuration File
1256 * @hw: the HW module
1257 * @mbox: mailbox to use for the FW command
1258 * @mtype: the memory type where the Configuration File is located
1259 * @maddr: the memory address where the Configuration File is located
1260 * @finiver: return value for CF [fini] version
1261 * @finicsum: return value for CF [fini] checksum
1262 * @cfcsum: return value for CF computed checksum
1263 *
1264 * Issue a command to get the firmware to process the Configuration
1265 * File located at the specified mtype/maddress. If the Configuration
1266 * File is processed successfully and return value pointers are
1267 * provided, the Configuration File "[fini] section version and
1268 * checksum values will be returned along with the computed checksum.
1269 * It's up to the caller to decide how it wants to respond to the
1270 * checksums not matching but it recommended that a prominant warning
1271 * be emitted in order to help people rapidly identify changed or
1272 * corrupted Configuration Files.
1273 *
1274 * Also note that it's possible to modify things like "niccaps",
1275 * "toecaps",etc. between processing the Configuration File and telling
1276 * the firmware to use the new configuration. Callers which want to
1277 * do this will need to "hand-roll" their own CAPS_CONFIGS commands for
1278 * Configuration Files if they want to do this.
1279 */
1280static int
1281csio_hw_fw_config_file(struct csio_hw *hw,
1282 unsigned int mtype, unsigned int maddr,
1283 uint32_t *finiver, uint32_t *finicsum, uint32_t *cfcsum)
1284{
1285 struct csio_mb *mbp;
1286 struct fw_caps_config_cmd *caps_cmd;
1287 int rv = -EINVAL;
1288 enum fw_retval ret;
1289
1290 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1291 if (!mbp) {
1292 CSIO_INC_STATS(hw, n_err_nomem);
1293 return -ENOMEM;
1294 }
1295 /*
1296 * Tell the firmware to process the indicated Configuration File.
1297 * If there are no errors and the caller has provided return value
1298 * pointers for the [fini] section version, checksum and computed
1299 * checksum, pass those back to the caller.
1300 */
1301 caps_cmd = (struct fw_caps_config_cmd *)(mbp->mb);
1302 CSIO_INIT_MBP(mbp, caps_cmd, CSIO_MB_DEFAULT_TMO, hw, NULL, 1);
1303 caps_cmd->op_to_write =
e2ac9628
HS		 1304 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
1305 FW_CMD_REQUEST_F |
1306 FW_CMD_READ_F);
a3667aae 1307 caps_cmd->cfvalid_to_len16 =
5167865a
HS		 1308 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
1309 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
1310 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
a3667aae
NKI		 1311 FW_LEN16(*caps_cmd));
1312
1313 if (csio_mb_issue(hw, mbp)) {
1314 csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD failed!\n");
1315 goto out;
1316 }
1317
1318 ret = csio_mb_fw_retval(mbp);
1319 if (ret != FW_SUCCESS) {
1320 csio_dbg(hw, "FW_CAPS_CONFIG_CMD returned %d!\n", rv);
1321 goto out;
1322 }
1323
1324 if (finiver)
1325 *finiver = ntohl(caps_cmd->finiver);
1326 if (finicsum)
1327 *finicsum = ntohl(caps_cmd->finicsum);
1328 if (cfcsum)
1329 *cfcsum = ntohl(caps_cmd->cfcsum);
1330
1331 /* Validate device capabilities */
1332 if (csio_hw_validate_caps(hw, mbp)) {
1333 rv = -ENOENT;
1334 goto out;
1335 }
1336
1337 /*
1338 * And now tell the firmware to use the configuration we just loaded.
1339 */
1340 caps_cmd->op_to_write =
e2ac9628
HS		 1341 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
1342 FW_CMD_REQUEST_F |
1343 FW_CMD_WRITE_F);
a3667aae
NKI		 1344 caps_cmd->cfvalid_to_len16 = htonl(FW_LEN16(*caps_cmd));
1345
1346 if (csio_mb_issue(hw, mbp)) {
1347 csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD failed!\n");
1348 goto out;
1349 }
1350
1351 ret = csio_mb_fw_retval(mbp);
1352 if (ret != FW_SUCCESS) {
1353 csio_dbg(hw, "FW_CAPS_CONFIG_CMD returned %d!\n", rv);
1354 goto out;
1355 }
1356
1357 rv = 0;
1358out:
1359 mempool_free(mbp, hw->mb_mempool);
1360 return rv;
1361}
1362
1363/*
1364 * csio_get_device_params - Get device parameters.
1365 * @hw: HW module
1366 *
1367 */
1368static int
1369csio_get_device_params(struct csio_hw *hw)
1370{
1371 struct csio_wrm *wrm = csio_hw_to_wrm(hw);
1372 struct csio_mb *mbp;
1373 enum fw_retval retval;
1374 u32 param[6];
1375 int i, j = 0;
1376
1377 /* Initialize portids to -1 */
1378 for (i = 0; i < CSIO_MAX_PPORTS; i++)
1379 hw->pport[i].portid = -1;
1380
1381 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1382 if (!mbp) {
1383 CSIO_INC_STATS(hw, n_err_nomem);
1384 return -ENOMEM;
1385 }
1386
1387 /* Get port vec information. */
1388 param[0] = FW_PARAM_DEV(PORTVEC);
1389
1390 /* Get Core clock. */
1391 param[1] = FW_PARAM_DEV(CCLK);
1392
1393 /* Get EQ id start and end. */
1394 param[2] = FW_PARAM_PFVF(EQ_START);
1395 param[3] = FW_PARAM_PFVF(EQ_END);
1396
1397 /* Get IQ id start and end. */
1398 param[4] = FW_PARAM_PFVF(IQFLINT_START);
1399 param[5] = FW_PARAM_PFVF(IQFLINT_END);
1400
1401 csio_mb_params(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, 0,
1402 ARRAY_SIZE(param), param, NULL, false, NULL);
1403 if (csio_mb_issue(hw, mbp)) {
1404 csio_err(hw, "Issue of FW_PARAMS_CMD(read) failed!\n");
1405 mempool_free(mbp, hw->mb_mempool);
1406 return -EINVAL;
1407 }
1408
1409 csio_mb_process_read_params_rsp(hw, mbp, &retval,
1410 ARRAY_SIZE(param), param);
1411 if (retval != FW_SUCCESS) {
1412 csio_err(hw, "FW_PARAMS_CMD(read) failed with ret:0x%x!\n",
1413 retval);
1414 mempool_free(mbp, hw->mb_mempool);
1415 return -EINVAL;
1416 }
1417
1418 /* cache the information. */
1419 hw->port_vec = param[0];
1420 hw->vpd.cclk = param[1];
1421 wrm->fw_eq_start = param[2];
1422 wrm->fw_iq_start = param[4];
1423
1424 /* Using FW configured max iqs & eqs */
1425 if ((hw->flags & CSIO_HWF_USING_SOFT_PARAMS) ||
1426 !csio_is_hw_master(hw)) {
1427 hw->cfg_niq = param[5] - param[4] + 1;
1428 hw->cfg_neq = param[3] - param[2] + 1;
1429 csio_dbg(hw, "Using fwconfig max niqs %d neqs %d\n",
1430 hw->cfg_niq, hw->cfg_neq);
1431 }
1432
1433 hw->port_vec &= csio_port_mask;
1434
1435 hw->num_pports = hweight32(hw->port_vec);
1436
1437 csio_dbg(hw, "Port vector: 0x%x, #ports: %d\n",
1438 hw->port_vec, hw->num_pports);
1439
1440 for (i = 0; i < hw->num_pports; i++) {
1441 while ((hw->port_vec & (1 << j)) == 0)
1442 j++;
1443 hw->pport[i].portid = j++;
1444 csio_dbg(hw, "Found Port:%d\n", hw->pport[i].portid);
1445 }
1446 mempool_free(mbp, hw->mb_mempool);
1447
1448 return 0;
1449}
1450
1451
1452/*
1453 * csio_config_device_caps - Get and set device capabilities.
1454 * @hw: HW module
1455 *
1456 */
1457static int
1458csio_config_device_caps(struct csio_hw *hw)
1459{
1460 struct csio_mb *mbp;
1461 enum fw_retval retval;
1462 int rv = -EINVAL;
1463
1464 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1465 if (!mbp) {
1466 CSIO_INC_STATS(hw, n_err_nomem);
1467 return -ENOMEM;
1468 }
1469
1470 /* Get device capabilities */
1471 csio_mb_caps_config(hw, mbp, CSIO_MB_DEFAULT_TMO, 0, 0, 0, 0, NULL);
1472
1473 if (csio_mb_issue(hw, mbp)) {
1474 csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD(r) failed!\n");
1475 goto out;
1476 }
1477
1478 retval = csio_mb_fw_retval(mbp);
1479 if (retval != FW_SUCCESS) {
1480 csio_err(hw, "FW_CAPS_CONFIG_CMD(r) returned %d!\n", retval);
1481 goto out;
1482 }
1483
1484 /* Validate device capabilities */
1485 if (csio_hw_validate_caps(hw, mbp))
1486 goto out;
1487
1488 /* Don't config device capabilities if already configured */
1489 if (hw->fw_state == CSIO_DEV_STATE_INIT) {
1490 rv = 0;
1491 goto out;
1492 }
1493
1494 /* Write back desired device capabilities */
1495 csio_mb_caps_config(hw, mbp, CSIO_MB_DEFAULT_TMO, true, true,
1496 false, true, NULL);
1497
1498 if (csio_mb_issue(hw, mbp)) {
1499 csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD(w) failed!\n");
1500 goto out;
1501 }
1502
1503 retval = csio_mb_fw_retval(mbp);
1504 if (retval != FW_SUCCESS) {
1505 csio_err(hw, "FW_CAPS_CONFIG_CMD(w) returned %d!\n", retval);
1506 goto out;
1507 }
1508
1509 rv = 0;
1510out:
1511 mempool_free(mbp, hw->mb_mempool);
1512 return rv;
1513}
1514
a3667aae
NKI		 1515/*
1516 * csio_enable_ports - Bring up all available ports.
1517 * @hw: HW module.
1518 *
1519 */
1520static int
1521csio_enable_ports(struct csio_hw *hw)
1522{
1523 struct csio_mb *mbp;
1524 enum fw_retval retval;
1525 uint8_t portid;
1526 int i;
1527
1528 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1529 if (!mbp) {
1530 CSIO_INC_STATS(hw, n_err_nomem);
1531 return -ENOMEM;
1532 }
1533
1534 for (i = 0; i < hw->num_pports; i++) {
1535 portid = hw->pport[i].portid;
1536
1537 /* Read PORT information */
1538 csio_mb_port(hw, mbp, CSIO_MB_DEFAULT_TMO, portid,
1539 false, 0, 0, NULL);
1540
1541 if (csio_mb_issue(hw, mbp)) {
1542 csio_err(hw, "failed to issue FW_PORT_CMD(r) port:%d\n",
1543 portid);
1544 mempool_free(mbp, hw->mb_mempool);
1545 return -EINVAL;
1546 }
1547
1548 csio_mb_process_read_port_rsp(hw, mbp, &retval,
1549 &hw->pport[i].pcap);
1550 if (retval != FW_SUCCESS) {
1551 csio_err(hw, "FW_PORT_CMD(r) port:%d failed: 0x%x\n",
1552 portid, retval);
1553 mempool_free(mbp, hw->mb_mempool);
1554 return -EINVAL;
1555 }
1556
1557 /* Write back PORT information */
1558 csio_mb_port(hw, mbp, CSIO_MB_DEFAULT_TMO, portid, true,
1559 (PAUSE_RX | PAUSE_TX), hw->pport[i].pcap, NULL);
1560
1561 if (csio_mb_issue(hw, mbp)) {
1562 csio_err(hw, "failed to issue FW_PORT_CMD(w) port:%d\n",
1563 portid);
1564 mempool_free(mbp, hw->mb_mempool);
1565 return -EINVAL;
1566 }
1567
1568 retval = csio_mb_fw_retval(mbp);
1569 if (retval != FW_SUCCESS) {
1570 csio_err(hw, "FW_PORT_CMD(w) port:%d failed :0x%x\n",
1571 portid, retval);
1572 mempool_free(mbp, hw->mb_mempool);
1573 return -EINVAL;
1574 }
1575
1576 } /* For all ports */
1577
1578 mempool_free(mbp, hw->mb_mempool);
1579
1580 return 0;
1581}
1582
1583/*
1584 * csio_get_fcoe_resinfo - Read fcoe fw resource info.
1585 * @hw: HW module
1586 * Issued with lock held.
1587 */
1588static int
1589csio_get_fcoe_resinfo(struct csio_hw *hw)
1590{
1591 struct csio_fcoe_res_info *res_info = &hw->fres_info;
1592 struct fw_fcoe_res_info_cmd *rsp;
1593 struct csio_mb *mbp;
1594 enum fw_retval retval;
1595
1596 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1597 if (!mbp) {
1598 CSIO_INC_STATS(hw, n_err_nomem);
1599 return -ENOMEM;
1600 }
1601
1602 /* Get FCoE FW resource information */
1603 csio_fcoe_read_res_info_init_mb(hw, mbp, CSIO_MB_DEFAULT_TMO, NULL);
1604
1605 if (csio_mb_issue(hw, mbp)) {
1606 csio_err(hw, "failed to issue FW_FCOE_RES_INFO_CMD\n");
1607 mempool_free(mbp, hw->mb_mempool);
1608 return -EINVAL;
1609 }
1610
1611 rsp = (struct fw_fcoe_res_info_cmd *)(mbp->mb);
e2ac9628 1612 retval = FW_CMD_RETVAL_G(ntohl(rsp->retval_len16));
a3667aae
NKI		 1613 if (retval != FW_SUCCESS) {
1614 csio_err(hw, "FW_FCOE_RES_INFO_CMD failed with ret x%x\n",
1615 retval);
1616 mempool_free(mbp, hw->mb_mempool);
1617 return -EINVAL;
1618 }
1619
1620 res_info->e_d_tov = ntohs(rsp->e_d_tov);
1621 res_info->r_a_tov_seq = ntohs(rsp->r_a_tov_seq);
1622 res_info->r_a_tov_els = ntohs(rsp->r_a_tov_els);
1623 res_info->r_r_tov = ntohs(rsp->r_r_tov);
1624 res_info->max_xchgs = ntohl(rsp->max_xchgs);
1625 res_info->max_ssns = ntohl(rsp->max_ssns);
1626 res_info->used_xchgs = ntohl(rsp->used_xchgs);
1627 res_info->used_ssns = ntohl(rsp->used_ssns);
1628 res_info->max_fcfs = ntohl(rsp->max_fcfs);
1629 res_info->max_vnps = ntohl(rsp->max_vnps);
1630 res_info->used_fcfs = ntohl(rsp->used_fcfs);
1631 res_info->used_vnps = ntohl(rsp->used_vnps);
1632
1633 csio_dbg(hw, "max ssns:%d max xchgs:%d\n", res_info->max_ssns,
1634 res_info->max_xchgs);
1635 mempool_free(mbp, hw->mb_mempool);
1636
1637 return 0;
1638}
1639
1640static int
1641csio_hw_check_fwconfig(struct csio_hw *hw, u32 *param)
1642{
1643 struct csio_mb *mbp;
1644 enum fw_retval retval;
1645 u32 _param[1];
1646
1647 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1648 if (!mbp) {
1649 CSIO_INC_STATS(hw, n_err_nomem);
1650 return -ENOMEM;
1651 }
1652
1653 /*
1654 * Find out whether we're dealing with a version of
1655 * the firmware which has configuration file support.
1656 */
5167865a
HS		 1657 _param[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
1658 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
a3667aae
NKI		 1659
1660 csio_mb_params(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, 0,
1661 ARRAY_SIZE(_param), _param, NULL, false, NULL);
1662 if (csio_mb_issue(hw, mbp)) {
1663 csio_err(hw, "Issue of FW_PARAMS_CMD(read) failed!\n");
1664 mempool_free(mbp, hw->mb_mempool);
1665 return -EINVAL;
1666 }
1667
1668 csio_mb_process_read_params_rsp(hw, mbp, &retval,
1669 ARRAY_SIZE(_param), _param);
1670 if (retval != FW_SUCCESS) {
1671 csio_err(hw, "FW_PARAMS_CMD(read) failed with ret:0x%x!\n",
1672 retval);
1673 mempool_free(mbp, hw->mb_mempool);
1674 return -EINVAL;
1675 }
1676
1677 mempool_free(mbp, hw->mb_mempool);
1678 *param = _param[0];
1679
1680 return 0;
1681}
1682
1683static int
1684csio_hw_flash_config(struct csio_hw *hw, u32 *fw_cfg_param, char *path)
1685{
1686 int ret = 0;
1687 const struct firmware *cf;
1688 struct pci_dev *pci_dev = hw->pdev;
1689 struct device *dev = &pci_dev->dev;
a3667aae
NKI		 1690 unsigned int mtype = 0, maddr = 0;
1691 uint32_t *cfg_data;
1692 int value_to_add = 0;
1693
3fb4c22e 1694 if (request_firmware(&cf, FW_CFG_NAME_T5, dev) < 0) {
7cc16380 1695 csio_err(hw, "could not find config file %s, err: %d\n",
3fb4c22e 1696 FW_CFG_NAME_T5, ret);
a3667aae
NKI		 1697 return -ENOENT;
1698 }
1699
1700 if (cf->size%4 != 0)
1701 value_to_add = 4 - (cf->size % 4);
1702
1703 cfg_data = kzalloc(cf->size+value_to_add, GFP_KERNEL);
02db3db5
JJ		 1704 if (cfg_data == NULL) {
1705 ret = -ENOMEM;
1706 goto leave;
1707 }
a3667aae
NKI		 1708
1709 memcpy((void *)cfg_data, (const void *)cf->data, cf->size);
02db3db5
JJ		 1710 if (csio_hw_check_fwconfig(hw, fw_cfg_param) != 0) {
1711 ret = -EINVAL;
1712 goto leave;
1713 }
a3667aae 1714
5167865a
HS		 1715 mtype = FW_PARAMS_PARAM_Y_G(*fw_cfg_param);
1716 maddr = FW_PARAMS_PARAM_Z_G(*fw_cfg_param) << 16;
a3667aae
NKI		 1717
1718 ret = csio_memory_write(hw, mtype, maddr,
1719 cf->size + value_to_add, cfg_data);
7cc16380
AB		 1720
1721 if ((ret == 0) && (value_to_add != 0)) {
1722 union {
1723 u32 word;
1724 char buf[4];
1725 } last;
1726 size_t size = cf->size & ~0x3;
1727 int i;
1728
1729 last.word = cfg_data[size >> 2];
1730 for (i = value_to_add; i < 4; i++)
1731 last.buf[i] = 0;
1732 ret = csio_memory_write(hw, mtype, maddr + size, 4, &last.word);
1733 }
a3667aae 1734 if (ret == 0) {
7cc16380 1735 csio_info(hw, "config file upgraded to %s\n",
3fb4c22e
PM		 1736 FW_CFG_NAME_T5);
1737 snprintf(path, 64, "%s%s", "/lib/firmware/", FW_CFG_NAME_T5);
a3667aae
NKI		 1738 }
1739
02db3db5 1740leave:
a3667aae
NKI		 1741 kfree(cfg_data);
1742 release_firmware(cf);
a3667aae
NKI		 1743 return ret;
1744}
1745
1746/*
1747 * HW initialization: contact FW, obtain config, perform basic init.
1748 *
1749 * If the firmware we're dealing with has Configuration File support, then
1750 * we use that to perform all configuration -- either using the configuration
1751 * file stored in flash on the adapter or using a filesystem-local file
1752 * if available.
1753 *
1754 * If we don't have configuration file support in the firmware, then we'll
1755 * have to set things up the old fashioned way with hard-coded register
1756 * writes and firmware commands ...
1757 */
1758
1759/*
1760 * Attempt to initialize the HW via a Firmware Configuration File.
1761 */
1762static int
1763csio_hw_use_fwconfig(struct csio_hw *hw, int reset, u32 *fw_cfg_param)
1764{
1765 unsigned int mtype, maddr;
1766 int rv;
7cc16380 1767 uint32_t finiver = 0, finicsum = 0, cfcsum = 0;
a3667aae
NKI		 1768 int using_flash;
1769 char path[64];
1770
1771 /*
1772 * Reset device if necessary
1773 */
1774 if (reset) {
1775 rv = csio_do_reset(hw, true);
1776 if (rv != 0)
1777 goto bye;
1778 }
1779
1780 /*
1781 * If we have a configuration file in host ,
1782 * then use that. Otherwise, use the configuration file stored
1783 * in the HW flash ...
1784 */
1785 spin_unlock_irq(&hw->lock);
1786 rv = csio_hw_flash_config(hw, fw_cfg_param, path);
1787 spin_lock_irq(&hw->lock);
1788 if (rv != 0) {
1789 if (rv == -ENOENT) {
1790 /*
1791 * config file was not found. Use default
1792 * config file from flash.
1793 */
1794 mtype = FW_MEMTYPE_CF_FLASH;
7cc16380 1795 maddr = hw->chip_ops->chip_flash_cfg_addr(hw);
a3667aae
NKI		 1796 using_flash = 1;
1797 } else {
1798 /*
1799 * we revert back to the hardwired config if
1800 * flashing failed.
1801 */
1802 goto bye;
1803 }
1804 } else {
5167865a
HS		 1805 mtype = FW_PARAMS_PARAM_Y_G(*fw_cfg_param);
1806 maddr = FW_PARAMS_PARAM_Z_G(*fw_cfg_param) << 16;
a3667aae
NKI		 1807 using_flash = 0;
1808 }
1809
1810 hw->cfg_store = (uint8_t)mtype;
1811
1812 /*
1813 * Issue a Capability Configuration command to the firmware to get it
1814 * to parse the Configuration File.
1815 */
1816 rv = csio_hw_fw_config_file(hw, mtype, maddr, &finiver,
1817 &finicsum, &cfcsum);
1818 if (rv != 0)
1819 goto bye;
1820
1821 hw->cfg_finiver = finiver;
1822 hw->cfg_finicsum = finicsum;
1823 hw->cfg_cfcsum = cfcsum;
1824 hw->cfg_csum_status = true;
1825
1826 if (finicsum != cfcsum) {
1827 csio_warn(hw,
1828 "Config File checksum mismatch: csum=%#x, computed=%#x\n",
1829 finicsum, cfcsum);
1830
1831 hw->cfg_csum_status = false;
1832 }
1833
1834 /*
1835 * Note that we're operating with parameters
1836 * not supplied by the driver, rather than from hard-wired
1837 * initialization constants buried in the driver.
1838 */
1839 hw->flags |= CSIO_HWF_USING_SOFT_PARAMS;
1840
1841 /* device parameters */
1842 rv = csio_get_device_params(hw);
1843 if (rv != 0)
1844 goto bye;
1845
1846 /* Configure SGE */
1847 csio_wr_sge_init(hw);
1848
1849 /*
1850 * And finally tell the firmware to initialize itself using the
1851 * parameters from the Configuration File.
1852 */
1853 /* Post event to notify completion of configuration */
1854 csio_post_event(&hw->sm, CSIO_HWE_INIT);
1855
1856 csio_info(hw,
1857 "Firmware Configuration File %s, version %#x, computed checksum %#x\n",
1858 (using_flash ? "in device FLASH" : path), finiver, cfcsum);
1859
1860 return 0;
1861
1862 /*
1863 * Something bad happened. Return the error ...
1864 */
1865bye:
1866 hw->flags &= ~CSIO_HWF_USING_SOFT_PARAMS;
1867 csio_dbg(hw, "Configuration file error %d\n", rv);
1868 return rv;
1869}
1870
1871/*
1872 * Attempt to initialize the adapter via hard-coded, driver supplied
1873 * parameters ...
1874 */
1875static int
1876csio_hw_no_fwconfig(struct csio_hw *hw, int reset)
1877{
1878 int rv;
1879 /*
1880 * Reset device if necessary
1881 */
1882 if (reset) {
1883 rv = csio_do_reset(hw, true);
1884 if (rv != 0)
1885 goto out;
1886 }
1887
1888 /* Get and set device capabilities */
1889 rv = csio_config_device_caps(hw);
1890 if (rv != 0)
1891 goto out;
1892
a3667aae
NKI		 1893 /* device parameters */
1894 rv = csio_get_device_params(hw);
1895 if (rv != 0)
1896 goto out;
1897
1898 /* Configure SGE */
1899 csio_wr_sge_init(hw);
1900
1901 /* Post event to notify completion of configuration */
1902 csio_post_event(&hw->sm, CSIO_HWE_INIT);
1903
1904out:
1905 return rv;
1906}
1907
f40e74ff
PM		 1908/* Is the given firmware API compatible with the one the driver was compiled
1909 * with?
1910 */
1911static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
1912{
1913
1914 /* short circuit if it's the exact same firmware version */
1915 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
1916 return 1;
1917
1918#define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
1919 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
1920 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
1921 return 1;
1922#undef SAME_INTF
1923
1924 return 0;
1925}
1926
1927/* The firmware in the filesystem is usable, but should it be installed?
1928 * This routine explains itself in detail if it indicates the filesystem
1929 * firmware should be installed.
1930 */
1931static int csio_should_install_fs_fw(struct csio_hw *hw, int card_fw_usable,
1932 int k, int c)
1933{
1934 const char *reason;
1935
1936 if (!card_fw_usable) {
1937 reason = "incompatible or unusable";
1938 goto install;
1939 }
1940
1941 if (k > c) {
1942 reason = "older than the version supported with this driver";
1943 goto install;
1944 }
1945
1946 return 0;
1947
1948install:
1949 csio_err(hw, "firmware on card (%u.%u.%u.%u) is %s, "
1950 "installing firmware %u.%u.%u.%u on card.\n",
1951 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
1952 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
1953 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
1954 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
1955
1956 return 1;
1957}
1958
1959static struct fw_info fw_info_array[] = {
1960 {
1961 .chip = CHELSIO_T5,
1962 .fs_name = FW_CFG_NAME_T5,
1963 .fw_mod_name = FW_FNAME_T5,
1964 .fw_hdr = {
1965 .chip = FW_HDR_CHIP_T5,
1966 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
1967 .intfver_nic = FW_INTFVER(T5, NIC),
1968 .intfver_vnic = FW_INTFVER(T5, VNIC),
1969 .intfver_ri = FW_INTFVER(T5, RI),
1970 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
1971 .intfver_fcoe = FW_INTFVER(T5, FCOE),
1972 },
1973 }
1974};
1975
1976static struct fw_info *find_fw_info(int chip)
1977{
1978 int i;
1979
1980 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
1981 if (fw_info_array[i].chip == chip)
1982 return &fw_info_array[i];
1983 }
1984 return NULL;
1985}
1986
78890ed7 1987static int csio_hw_prep_fw(struct csio_hw *hw, struct fw_info *fw_info,
f40e74ff
PM		 1988 const u8 *fw_data, unsigned int fw_size,
1989 struct fw_hdr *card_fw, enum csio_dev_state state,
1990 int *reset)
1991{
1992 int ret, card_fw_usable, fs_fw_usable;
1993 const struct fw_hdr *fs_fw;
1994 const struct fw_hdr *drv_fw;
1995
1996 drv_fw = &fw_info->fw_hdr;
1997
1998 /* Read the header of the firmware on the card */
1999 ret = csio_hw_read_flash(hw, FLASH_FW_START,
2000 sizeof(*card_fw) / sizeof(uint32_t),
2001 (uint32_t *)card_fw, 1);
2002 if (ret == 0) {
2003 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
2004 } else {
2005 csio_err(hw,
2006 "Unable to read card's firmware header: %d\n", ret);
2007 card_fw_usable = 0;
2008 }
2009
2010 if (fw_data != NULL) {
2011 fs_fw = (const void *)fw_data;
2012 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
2013 } else {
2014 fs_fw = NULL;
2015 fs_fw_usable = 0;
2016 }
2017
2018 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
2019 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
2020 /* Common case: the firmware on the card is an exact match and
2021 * the filesystem one is an exact match too, or the filesystem
2022 * one is absent/incompatible.
2023 */
2024 } else if (fs_fw_usable && state == CSIO_DEV_STATE_UNINIT &&
2025 csio_should_install_fs_fw(hw, card_fw_usable,
2026 be32_to_cpu(fs_fw->fw_ver),
2027 be32_to_cpu(card_fw->fw_ver))) {
2028 ret = csio_hw_fw_upgrade(hw, hw->pfn, fw_data,
2029 fw_size, 0);
2030 if (ret != 0) {
2031 csio_err(hw,
2032 "failed to install firmware: %d\n", ret);
2033 goto bye;
2034 }
2035
2036 /* Installed successfully, update the cached header too. */
2037 memcpy(card_fw, fs_fw, sizeof(*card_fw));
2038 card_fw_usable = 1;
2039 *reset = 0; /* already reset as part of load_fw */
2040 }
2041
2042 if (!card_fw_usable) {
2043 uint32_t d, c, k;
2044
2045 d = be32_to_cpu(drv_fw->fw_ver);
2046 c = be32_to_cpu(card_fw->fw_ver);
2047 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
2048
2049 csio_err(hw, "Cannot find a usable firmware: "
2050 "chip state %d, "
2051 "driver compiled with %d.%d.%d.%d, "
2052 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
2053 state,
2054 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
2055 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
2056 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
2057 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
2058 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
2059 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
2060 ret = EINVAL;
2061 goto bye;
2062 }
2063
2064 /* We're using whatever's on the card and it's known to be good. */
2065 hw->fwrev = be32_to_cpu(card_fw->fw_ver);
2066 hw->tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
2067
2068bye:
2069 return ret;
2070}
2071
a3667aae
NKI		 2072/*
2073 * Returns -EINVAL if attempts to flash the firmware failed
2074 * else returns 0,
2075 * if flashing was not attempted because the card had the
2076 * latest firmware ECANCELED is returned
2077 */
2078static int
f40e74ff 2079csio_hw_flash_fw(struct csio_hw *hw, int *reset)
a3667aae
NKI		 2080{
2081 int ret = -ECANCELED;
2082 const struct firmware *fw;
f40e74ff
PM		 2083 struct fw_info *fw_info;
2084 struct fw_hdr *card_fw;
a3667aae
NKI		 2085 struct pci_dev *pci_dev = hw->pdev;
2086 struct device *dev = &pci_dev->dev ;
f40e74ff
PM		 2087 const u8 *fw_data = NULL;
2088 unsigned int fw_size = 0;
2089
2090 /* This is the firmware whose headers the driver was compiled
2091 * against
2092 */
2093 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(hw->chip_id));
2094 if (fw_info == NULL) {
2095 csio_err(hw,
2096 "unable to get firmware info for chip %d.\n",
2097 CHELSIO_CHIP_VERSION(hw->chip_id));
2098 return -EINVAL;
2099 }
a3667aae 2100
3fb4c22e 2101 if (request_firmware(&fw, FW_FNAME_T5, dev) < 0) {
7cc16380 2102 csio_err(hw, "could not find firmware image %s, err: %d\n",
3fb4c22e 2103 FW_FNAME_T5, ret);
a3667aae
NKI		 2104 return -EINVAL;
2105 }
2106
f40e74ff
PM		 2107 /* allocate memory to read the header of the firmware on the
2108 * card
a3667aae 2109 */
f40e74ff
PM		 2110 card_fw = kmalloc(sizeof(*card_fw), GFP_KERNEL);
2111
2112 fw_data = fw->data;
2113 fw_size = fw->size;
a3667aae 2114
f40e74ff
PM		 2115 /* upgrade FW logic */
2116 ret = csio_hw_prep_fw(hw, fw_info, fw_data, fw_size, card_fw,
2117 hw->fw_state, reset);
a3667aae 2118
f40e74ff
PM		 2119 /* Cleaning up */
2120 if (fw != NULL)
2121 release_firmware(fw);
2122 kfree(card_fw);
a3667aae
NKI		 2123 return ret;
2124}
2125
a3667aae
NKI		 2126/*
2127 * csio_hw_configure - Configure HW
2128 * @hw - HW module
2129 *
2130 */
2131static void
2132csio_hw_configure(struct csio_hw *hw)
2133{
2134 int reset = 1;
2135 int rv;
2136 u32 param[1];
2137
2138 rv = csio_hw_dev_ready(hw);
2139 if (rv != 0) {
2140 CSIO_INC_STATS(hw, n_err_fatal);
2141 csio_post_event(&hw->sm, CSIO_HWE_FATAL);
2142 goto out;
2143 }
2144
2145 /* HW version */
0d804338 2146 hw->chip_ver = (char)csio_rd_reg32(hw, PL_REV_A);
a3667aae
NKI		 2147
2148 /* Needed for FW download */
2149 rv = csio_hw_get_flash_params(hw);
2150 if (rv != 0) {
2151 csio_err(hw, "Failed to get serial flash params rv:%d\n", rv);
2152 csio_post_event(&hw->sm, CSIO_HWE_FATAL);
2153 goto out;
2154 }
2155
ad4d35f8
YW		 2156 /* Set PCIe completion timeout to 4 seconds */
2157 if (pci_is_pcie(hw->pdev))
2158 pcie_capability_clear_and_set_word(hw->pdev, PCI_EXP_DEVCTL2,
2159 PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
a3667aae 2160
7cc16380 2161 hw->chip_ops->chip_set_mem_win(hw, MEMWIN_CSIOSTOR);
a3667aae
NKI		 2162
2163 rv = csio_hw_get_fw_version(hw, &hw->fwrev);
2164 if (rv != 0)
2165 goto out;
2166
2167 csio_hw_print_fw_version(hw, "Firmware revision");
2168
2169 rv = csio_do_hello(hw, &hw->fw_state);
2170 if (rv != 0) {
2171 CSIO_INC_STATS(hw, n_err_fatal);
2172 csio_post_event(&hw->sm, CSIO_HWE_FATAL);
2173 goto out;
2174 }
2175
2176 /* Read vpd */
2177 rv = csio_hw_get_vpd_params(hw, &hw->vpd);
2178 if (rv != 0)
2179 goto out;
2180
f40e74ff
PM		 2181 csio_hw_get_fw_version(hw, &hw->fwrev);
2182 csio_hw_get_tp_version(hw, &hw->tp_vers);
a3667aae 2183 if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) {
a3667aae
NKI		 2184
2185 /* Do firmware update */
f40e74ff
PM		 2186 spin_unlock_irq(&hw->lock);
2187 rv = csio_hw_flash_fw(hw, &reset);
2188 spin_lock_irq(&hw->lock);
2189
2190 if (rv != 0)
2191 goto out;
a3667aae 2192
a3667aae
NKI		 2193 /*
2194 * If the firmware doesn't support Configuration
2195 * Files, use the old Driver-based, hard-wired
2196 * initialization. Otherwise, try using the
2197 * Configuration File support and fall back to the
2198 * Driver-based initialization if there's no
2199 * Configuration File found.
2200 */
2201 if (csio_hw_check_fwconfig(hw, param) == 0) {
2202 rv = csio_hw_use_fwconfig(hw, reset, param);
2203 if (rv == -ENOENT)
2204 goto out;
2205 if (rv != 0) {
2206 csio_info(hw,
2207 "No Configuration File present "
2208 "on adapter. Using hard-wired "
2209 "configuration parameters.\n");
2210 rv = csio_hw_no_fwconfig(hw, reset);
2211 }
2212 } else {
2213 rv = csio_hw_no_fwconfig(hw, reset);
2214 }
2215
2216 if (rv != 0)
2217 goto out;
2218
2219 } else {
2220 if (hw->fw_state == CSIO_DEV_STATE_INIT) {
2221
7cc16380
AB		 2222 hw->flags |= CSIO_HWF_USING_SOFT_PARAMS;
2223
a3667aae
NKI		 2224 /* device parameters */
2225 rv = csio_get_device_params(hw);
2226 if (rv != 0)
2227 goto out;
2228
2229 /* Get device capabilities */
2230 rv = csio_config_device_caps(hw);
2231 if (rv != 0)
2232 goto out;
2233
2234 /* Configure SGE */
2235 csio_wr_sge_init(hw);
2236
2237 /* Post event to notify completion of configuration */
2238 csio_post_event(&hw->sm, CSIO_HWE_INIT);
2239 goto out;
2240 }
2241 } /* if not master */
2242
2243out:
2244 return;
2245}
2246
2247/*
2248 * csio_hw_initialize - Initialize HW
2249 * @hw - HW module
2250 *
2251 */
2252static void
2253csio_hw_initialize(struct csio_hw *hw)
2254{
2255 struct csio_mb *mbp;
2256 enum fw_retval retval;
2257 int rv;
2258 int i;
2259
2260 if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) {
2261 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
2262 if (!mbp)
2263 goto out;
2264
2265 csio_mb_initialize(hw, mbp, CSIO_MB_DEFAULT_TMO, NULL);
2266
2267 if (csio_mb_issue(hw, mbp)) {
2268 csio_err(hw, "Issue of FW_INITIALIZE_CMD failed!\n");
2269 goto free_and_out;
2270 }
2271
2272 retval = csio_mb_fw_retval(mbp);
2273 if (retval != FW_SUCCESS) {
2274 csio_err(hw, "FW_INITIALIZE_CMD returned 0x%x!\n",
2275 retval);
2276 goto free_and_out;
2277 }
2278
2279 mempool_free(mbp, hw->mb_mempool);
2280 }
2281
2282 rv = csio_get_fcoe_resinfo(hw);
2283 if (rv != 0) {
2284 csio_err(hw, "Failed to read fcoe resource info: %d\n", rv);
2285 goto out;
2286 }
2287
2288 spin_unlock_irq(&hw->lock);
2289 rv = csio_config_queues(hw);
2290 spin_lock_irq(&hw->lock);
2291
2292 if (rv != 0) {
2293 csio_err(hw, "Config of queues failed!: %d\n", rv);
2294 goto out;
2295 }
2296
2297 for (i = 0; i < hw->num_pports; i++)
2298 hw->pport[i].mod_type = FW_PORT_MOD_TYPE_NA;
2299
2300 if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) {
2301 rv = csio_enable_ports(hw);
2302 if (rv != 0) {
2303 csio_err(hw, "Failed to enable ports: %d\n", rv);
2304 goto out;
2305 }
2306 }
2307
2308 csio_post_event(&hw->sm, CSIO_HWE_INIT_DONE);
2309 return;
2310
2311free_and_out:
2312 mempool_free(mbp, hw->mb_mempool);
2313out:
2314 return;
2315}
2316
0d804338 2317#define PF_INTR_MASK (PFSW_F | PFCIM_F)
a3667aae
NKI		 2318
2319/*
2320 * csio_hw_intr_enable - Enable HW interrupts
2321 * @hw: Pointer to HW module.
2322 *
2323 * Enable interrupts in HW registers.
2324 */
2325static void
2326csio_hw_intr_enable(struct csio_hw *hw)
2327{
2328 uint16_t vec = (uint16_t)csio_get_mb_intr_idx(csio_hw_to_mbm(hw));
0d804338
HS		 2329 uint32_t pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
2330 uint32_t pl = csio_rd_reg32(hw, PL_INT_ENABLE_A);
a3667aae
NKI		 2331
2332 /*
2333 * Set aivec for MSI/MSIX. PCIE_PF_CFG.INTXType is set up
2334 * by FW, so do nothing for INTX.
2335 */
2336 if (hw->intr_mode == CSIO_IM_MSIX)
f061de42
HS		 2337 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A),
2338 AIVEC_V(AIVEC_M), vec);
a3667aae 2339 else if (hw->intr_mode == CSIO_IM_MSI)
f061de42
HS		 2340 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A),
2341 AIVEC_V(AIVEC_M), 0);
a3667aae 2342
0d804338 2343 csio_wr_reg32(hw, PF_INTR_MASK, MYPF_REG(PL_PF_INT_ENABLE_A));
a3667aae
NKI		 2344
2345 /* Turn on MB interrupts - this will internally flush PIO as well */
2346 csio_mb_intr_enable(hw);
2347
2348 /* These are common registers - only a master can modify them */
2349 if (csio_is_hw_master(hw)) {
2350 /*
2351 * Disable the Serial FLASH interrupt, if enabled!
2352 */
0d804338
HS		 2353 pl &= (~SF_F);
2354 csio_wr_reg32(hw, pl, PL_INT_ENABLE_A);
a3667aae 2355
f612b815
HS		 2356 csio_wr_reg32(hw, ERR_CPL_EXCEED_IQE_SIZE_F |
2357 EGRESS_SIZE_ERR_F | ERR_INVALID_CIDX_INC_F |
2358 ERR_CPL_OPCODE_0_F | ERR_DROPPED_DB_F |
2359 ERR_DATA_CPL_ON_HIGH_QID1_F |
2360 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
2361 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
2362 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
2363 ERR_EGR_CTXT_PRIO_F | INGRESS_SIZE_ERR_F,
2364 SGE_INT_ENABLE3_A);
0d804338 2365 csio_set_reg_field(hw, PL_INT_MAP0_A, 0, 1 << pf);
a3667aae
NKI		 2366 }
2367
2368 hw->flags |= CSIO_HWF_HW_INTR_ENABLED;
2369
2370}
2371
2372/*
2373 * csio_hw_intr_disable - Disable HW interrupts
2374 * @hw: Pointer to HW module.
2375 *
2376 * Turn off Mailbox and PCI_PF_CFG interrupts.
2377 */
2378void
2379csio_hw_intr_disable(struct csio_hw *hw)
2380{
0d804338 2381 uint32_t pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
a3667aae
NKI		 2382
2383 if (!(hw->flags & CSIO_HWF_HW_INTR_ENABLED))
2384 return;
2385
2386 hw->flags &= ~CSIO_HWF_HW_INTR_ENABLED;
2387
0d804338 2388 csio_wr_reg32(hw, 0, MYPF_REG(PL_PF_INT_ENABLE_A));
a3667aae 2389 if (csio_is_hw_master(hw))
0d804338 2390 csio_set_reg_field(hw, PL_INT_MAP0_A, 1 << pf, 0);
a3667aae
NKI		 2391
2392 /* Turn off MB interrupts */
2393 csio_mb_intr_disable(hw);
2394
2395}
2396
7cc16380 2397void
a3667aae
NKI		 2398csio_hw_fatal_err(struct csio_hw *hw)
2399{
f612b815 2400 csio_set_reg_field(hw, SGE_CONTROL_A, GLOBALENABLE_F, 0);
a3667aae
NKI		 2401 csio_hw_intr_disable(hw);
2402
2403 /* Do not reset HW, we may need FW state for debugging */
2404 csio_fatal(hw, "HW Fatal error encountered!\n");
2405}
2406
2407/*****************************************************************************/
2408/* START: HW SM */
2409/*****************************************************************************/
2410/*
2411 * csio_hws_uninit - Uninit state
2412 * @hw - HW module
2413 * @evt - Event
2414 *
2415 */
2416static void
2417csio_hws_uninit(struct csio_hw *hw, enum csio_hw_ev evt)
2418{
2419 hw->prev_evt = hw->cur_evt;
2420 hw->cur_evt = evt;
2421 CSIO_INC_STATS(hw, n_evt_sm[evt]);
2422
2423 switch (evt) {
2424 case CSIO_HWE_CFG:
2425 csio_set_state(&hw->sm, csio_hws_configuring);
2426 csio_hw_configure(hw);
2427 break;
2428
2429 default:
2430 CSIO_INC_STATS(hw, n_evt_unexp);
2431 break;
2432 }
2433}
2434
2435/*
2436 * csio_hws_configuring - Configuring state
2437 * @hw - HW module
2438 * @evt - Event
2439 *
2440 */
2441static void
2442csio_hws_configuring(struct csio_hw *hw, enum csio_hw_ev evt)
2443{
2444 hw->prev_evt = hw->cur_evt;
2445 hw->cur_evt = evt;
2446 CSIO_INC_STATS(hw, n_evt_sm[evt]);
2447
2448 switch (evt) {
2449 case CSIO_HWE_INIT:
2450 csio_set_state(&hw->sm, csio_hws_initializing);
2451 csio_hw_initialize(hw);
2452 break;
2453
2454 case CSIO_HWE_INIT_DONE:
2455 csio_set_state(&hw->sm, csio_hws_ready);
2456 /* Fan out event to all lnode SMs */
2457 csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWREADY);
2458 break;
2459
2460 case CSIO_HWE_FATAL:
2461 csio_set_state(&hw->sm, csio_hws_uninit);
2462 break;
2463
2464 case CSIO_HWE_PCI_REMOVE:
2465 csio_do_bye(hw);
2466 break;
2467 default:
2468 CSIO_INC_STATS(hw, n_evt_unexp);
2469 break;
2470 }
2471}
2472
2473/*
2474 * csio_hws_initializing - Initialiazing state
2475 * @hw - HW module
2476 * @evt - Event
2477 *
2478 */
2479static void
2480csio_hws_initializing(struct csio_hw *hw, enum csio_hw_ev evt)
2481{
2482 hw->prev_evt = hw->cur_evt;
2483 hw->cur_evt = evt;
2484 CSIO_INC_STATS(hw, n_evt_sm[evt]);
2485
2486 switch (evt) {
2487 case CSIO_HWE_INIT_DONE:
2488 csio_set_state(&hw->sm, csio_hws_ready);
2489
2490 /* Fan out event to all lnode SMs */
2491 csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWREADY);
2492
2493 /* Enable interrupts */
2494 csio_hw_intr_enable(hw);
2495 break;
2496
2497 case CSIO_HWE_FATAL:
2498 csio_set_state(&hw->sm, csio_hws_uninit);
2499 break;
2500
2501 case CSIO_HWE_PCI_REMOVE:
2502 csio_do_bye(hw);
2503 break;
2504
2505 default:
2506 CSIO_INC_STATS(hw, n_evt_unexp);
2507 break;
2508 }
2509}
2510
2511/*
2512 * csio_hws_ready - Ready state
2513 * @hw - HW module
2514 * @evt - Event
2515 *
2516 */
2517static void
2518csio_hws_ready(struct csio_hw *hw, enum csio_hw_ev evt)
2519{
2520 /* Remember the event */
2521 hw->evtflag = evt;
2522
2523 hw->prev_evt = hw->cur_evt;
2524 hw->cur_evt = evt;
2525 CSIO_INC_STATS(hw, n_evt_sm[evt]);
2526
2527 switch (evt) {
2528 case CSIO_HWE_HBA_RESET:
2529 case CSIO_HWE_FW_DLOAD:
2530 case CSIO_HWE_SUSPEND:
2531 case CSIO_HWE_PCI_REMOVE:
2532 case CSIO_HWE_PCIERR_DETECTED:
2533 csio_set_state(&hw->sm, csio_hws_quiescing);
2534 /* cleanup all outstanding cmds */
2535 if (evt == CSIO_HWE_HBA_RESET ||
2536 evt == CSIO_HWE_PCIERR_DETECTED)
2537 csio_scsim_cleanup_io(csio_hw_to_scsim(hw), false);
2538 else
2539 csio_scsim_cleanup_io(csio_hw_to_scsim(hw), true);
2540
2541 csio_hw_intr_disable(hw);
2542 csio_hw_mbm_cleanup(hw);
2543 csio_evtq_stop(hw);
2544 csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWSTOP);
2545 csio_evtq_flush(hw);
2546 csio_mgmtm_cleanup(csio_hw_to_mgmtm(hw));
2547 csio_post_event(&hw->sm, CSIO_HWE_QUIESCED);
2548 break;
2549
2550 case CSIO_HWE_FATAL:
2551 csio_set_state(&hw->sm, csio_hws_uninit);
2552 break;
2553
2554 default:
2555 CSIO_INC_STATS(hw, n_evt_unexp);
2556 break;
2557 }
2558}
2559
2560/*
2561 * csio_hws_quiescing - Quiescing state
2562 * @hw - HW module
2563 * @evt - Event
2564 *
2565 */
2566static void
2567csio_hws_quiescing(struct csio_hw *hw, enum csio_hw_ev evt)
2568{
2569 hw->prev_evt = hw->cur_evt;
2570 hw->cur_evt = evt;
2571 CSIO_INC_STATS(hw, n_evt_sm[evt]);
2572
2573 switch (evt) {
2574 case CSIO_HWE_QUIESCED:
2575 switch (hw->evtflag) {
2576 case CSIO_HWE_FW_DLOAD:
2577 csio_set_state(&hw->sm, csio_hws_resetting);
2578 /* Download firmware */
2579 /* Fall through */
2580
2581 case CSIO_HWE_HBA_RESET:
2582 csio_set_state(&hw->sm, csio_hws_resetting);
2583 /* Start reset of the HBA */
2584 csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWRESET);
2585 csio_wr_destroy_queues(hw, false);
2586 csio_do_reset(hw, false);
2587 csio_post_event(&hw->sm, CSIO_HWE_HBA_RESET_DONE);
2588 break;
2589
2590 case CSIO_HWE_PCI_REMOVE:
2591 csio_set_state(&hw->sm, csio_hws_removing);
2592 csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWREMOVE);
2593 csio_wr_destroy_queues(hw, true);
2594 /* Now send the bye command */
2595 csio_do_bye(hw);
2596 break;
2597
2598 case CSIO_HWE_SUSPEND:
2599 csio_set_state(&hw->sm, csio_hws_quiesced);
2600 break;
2601
2602 case CSIO_HWE_PCIERR_DETECTED:
2603 csio_set_state(&hw->sm, csio_hws_pcierr);
2604 csio_wr_destroy_queues(hw, false);
2605 break;
2606
2607 default:
2608 CSIO_INC_STATS(hw, n_evt_unexp);
2609 break;
2610
2611 }
2612 break;
2613
2614 default:
2615 CSIO_INC_STATS(hw, n_evt_unexp);
2616 break;
2617 }
2618}
2619
2620/*
2621 * csio_hws_quiesced - Quiesced state
2622 * @hw - HW module
2623 * @evt - Event
2624 *
2625 */
2626static void
2627csio_hws_quiesced(struct csio_hw *hw, enum csio_hw_ev evt)
2628{
2629 hw->prev_evt = hw->cur_evt;
2630 hw->cur_evt = evt;
2631 CSIO_INC_STATS(hw, n_evt_sm[evt]);
2632
2633 switch (evt) {
2634 case CSIO_HWE_RESUME:
2635 csio_set_state(&hw->sm, csio_hws_configuring);
2636 csio_hw_configure(hw);
2637 break;
2638
2639 default:
2640 CSIO_INC_STATS(hw, n_evt_unexp);
2641 break;
2642 }
2643}
2644
2645/*
2646 * csio_hws_resetting - HW Resetting state
2647 * @hw - HW module
2648 * @evt - Event
2649 *
2650 */
2651static void
2652csio_hws_resetting(struct csio_hw *hw, enum csio_hw_ev evt)
2653{
2654 hw->prev_evt = hw->cur_evt;
2655 hw->cur_evt = evt;
2656 CSIO_INC_STATS(hw, n_evt_sm[evt]);
2657
2658 switch (evt) {
2659 case CSIO_HWE_HBA_RESET_DONE:
2660 csio_evtq_start(hw);
2661 csio_set_state(&hw->sm, csio_hws_configuring);
2662 csio_hw_configure(hw);
2663 break;
2664
2665 default:
2666 CSIO_INC_STATS(hw, n_evt_unexp);
2667 break;
2668 }
2669}
2670
2671/*
2672 * csio_hws_removing - PCI Hotplug removing state
2673 * @hw - HW module
2674 * @evt - Event
2675 *
2676 */
2677static void
2678csio_hws_removing(struct csio_hw *hw, enum csio_hw_ev evt)
2679{
2680 hw->prev_evt = hw->cur_evt;
2681 hw->cur_evt = evt;
2682 CSIO_INC_STATS(hw, n_evt_sm[evt]);
2683
2684 switch (evt) {
2685 case CSIO_HWE_HBA_RESET:
2686 if (!csio_is_hw_master(hw))
2687 break;
2688 /*
2689 * The BYE should have alerady been issued, so we cant
2690 * use the mailbox interface. Hence we use the PL_RST
2691 * register directly.
2692 */
2693 csio_err(hw, "Resetting HW and waiting 2 seconds...\n");
0d804338 2694 csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A);
a3667aae
NKI		 2695 mdelay(2000);
2696 break;
2697
2698 /* Should never receive any new events */
2699 default:
2700 CSIO_INC_STATS(hw, n_evt_unexp);
2701 break;
2702
2703 }
2704}
2705
2706/*
2707 * csio_hws_pcierr - PCI Error state
2708 * @hw - HW module
2709 * @evt - Event
2710 *
2711 */
2712static void
2713csio_hws_pcierr(struct csio_hw *hw, enum csio_hw_ev evt)
2714{
2715 hw->prev_evt = hw->cur_evt;
2716 hw->cur_evt = evt;
2717 CSIO_INC_STATS(hw, n_evt_sm[evt]);
2718
2719 switch (evt) {
2720 case CSIO_HWE_PCIERR_SLOT_RESET:
2721 csio_evtq_start(hw);
2722 csio_set_state(&hw->sm, csio_hws_configuring);
2723 csio_hw_configure(hw);
2724 break;
2725
2726 default:
2727 CSIO_INC_STATS(hw, n_evt_unexp);
2728 break;
2729 }
2730}
2731
2732/*****************************************************************************/
2733/* END: HW SM */
2734/*****************************************************************************/
2735
a3667aae
NKI		 2736/*
2737 * csio_handle_intr_status - table driven interrupt handler
2738 * @hw: HW instance
2739 * @reg: the interrupt status register to process
2740 * @acts: table of interrupt actions
2741 *
2742 * A table driven interrupt handler that applies a set of masks to an
2743 * interrupt status word and performs the corresponding actions if the
2744 * interrupts described by the mask have occured. The actions include
2745 * optionally emitting a warning or alert message. The table is terminated
2746 * by an entry specifying mask 0. Returns the number of fatal interrupt
2747 * conditions.
2748 */
7cc16380 2749int
a3667aae
NKI		 2750csio_handle_intr_status(struct csio_hw *hw, unsigned int reg,
2751 const struct intr_info *acts)
2752{
2753 int fatal = 0;
2754 unsigned int mask = 0;
2755 unsigned int status = csio_rd_reg32(hw, reg);
2756
2757 for ( ; acts->mask; ++acts) {
2758 if (!(status & acts->mask))
2759 continue;
2760 if (acts->fatal) {
2761 fatal++;
2762 csio_fatal(hw, "Fatal %s (0x%x)\n",
2763 acts->msg, status & acts->mask);
2764 } else if (acts->msg)
2765 csio_info(hw, "%s (0x%x)\n",
2766 acts->msg, status & acts->mask);
2767 mask |= acts->mask;
2768 }
2769 status &= mask;
2770 if (status) /* clear processed interrupts */
2771 csio_wr_reg32(hw, status, reg);
2772 return fatal;
2773}
2774
a3667aae
NKI		 2775/*
2776 * TP interrupt handler.
2777 */
2778static void csio_tp_intr_handler(struct csio_hw *hw)
2779{
2780 static struct intr_info tp_intr_info[] = {
2781 { 0x3fffffff, "TP parity error", -1, 1 },
837e4a42 2782 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
a3667aae
NKI		 2783 { 0, NULL, 0, 0 }
2784 };
2785
837e4a42 2786 if (csio_handle_intr_status(hw, TP_INT_CAUSE_A, tp_intr_info))
a3667aae
NKI		 2787 csio_hw_fatal_err(hw);
2788}
2789
2790/*
2791 * SGE interrupt handler.
2792 */
2793static void csio_sge_intr_handler(struct csio_hw *hw)
2794{
2795 uint64_t v;
2796
2797 static struct intr_info sge_intr_info[] = {
f612b815 2798 { ERR_CPL_EXCEED_IQE_SIZE_F,
a3667aae 2799 "SGE received CPL exceeding IQE size", -1, 1 },
f612b815 2800 { ERR_INVALID_CIDX_INC_F,
a3667aae 2801 "SGE GTS CIDX increment too large", -1, 0 },
f612b815
HS		 2802 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
2803 { ERR_DROPPED_DB_F, "SGE doorbell dropped", -1, 0 },
2804 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
a3667aae 2805 "SGE IQID > 1023 received CPL for FL", -1, 0 },
f612b815 2806 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
a3667aae 2807 0 },
f612b815 2808 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
a3667aae 2809 0 },
f612b815 2810 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
a3667aae 2811 0 },
f612b815 2812 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
a3667aae 2813 0 },
f612b815 2814 { ERR_ING_CTXT_PRIO_F,
a3667aae 2815 "SGE too many priority ingress contexts", -1, 0 },
f612b815 2816 { ERR_EGR_CTXT_PRIO_F,
a3667aae 2817 "SGE too many priority egress contexts", -1, 0 },
f612b815
HS		 2818 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
2819 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
a3667aae
NKI		 2820 { 0, NULL, 0, 0 }
2821 };
2822
f612b815
HS		 2823 v = (uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE1_A) |
2824 ((uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE2_A) << 32);
a3667aae
NKI		 2825 if (v) {
2826 csio_fatal(hw, "SGE parity error (%#llx)\n",
2827 (unsigned long long)v);
2828 csio_wr_reg32(hw, (uint32_t)(v & 0xFFFFFFFF),
f612b815
HS		 2829 SGE_INT_CAUSE1_A);
2830 csio_wr_reg32(hw, (uint32_t)(v >> 32), SGE_INT_CAUSE2_A);
a3667aae
NKI		 2831 }
2832
f612b815 2833 v |= csio_handle_intr_status(hw, SGE_INT_CAUSE3_A, sge_intr_info);
a3667aae 2834
f612b815 2835 if (csio_handle_intr_status(hw, SGE_INT_CAUSE3_A, sge_intr_info) ||
a3667aae
NKI		 2836 v != 0)
2837 csio_hw_fatal_err(hw);
2838}
2839
89c3a86c
HS		 2840#define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
2841 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
2842#define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
2843 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
a3667aae
NKI		 2844
2845/*
2846 * CIM interrupt handler.
2847 */
2848static void csio_cim_intr_handler(struct csio_hw *hw)
2849{
2850 static struct intr_info cim_intr_info[] = {
89c3a86c 2851 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
a3667aae
NKI		 2852 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
2853 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
89c3a86c
HS		 2854 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
2855 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
2856 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
2857 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
a3667aae
NKI		 2858 { 0, NULL, 0, 0 }
2859 };
2860 static struct intr_info cim_upintr_info[] = {
89c3a86c
HS		 2861 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
2862 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
2863 { ILLWRINT_F, "CIM illegal write", -1, 1 },
2864 { ILLRDINT_F, "CIM illegal read", -1, 1 },
2865 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
2866 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
2867 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
2868 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
2869 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
2870 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
2871 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
2872 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
2873 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
2874 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
2875 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
2876 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
2877 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
2878 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
2879 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
2880 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
2881 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
2882 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
2883 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
2884 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
2885 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
2886 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
2887 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
2888 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
a3667aae
NKI		 2889 { 0, NULL, 0, 0 }
2890 };
2891
2892 int fat;
2893
89c3a86c
HS		 2894 fat = csio_handle_intr_status(hw, CIM_HOST_INT_CAUSE_A,
2895 cim_intr_info) +
2896 csio_handle_intr_status(hw, CIM_HOST_UPACC_INT_CAUSE_A,
2897 cim_upintr_info);
a3667aae
NKI		 2898 if (fat)
2899 csio_hw_fatal_err(hw);
2900}
2901
2902/*
2903 * ULP RX interrupt handler.
2904 */
2905static void csio_ulprx_intr_handler(struct csio_hw *hw)
2906{
2907 static struct intr_info ulprx_intr_info[] = {
2908 { 0x1800000, "ULPRX context error", -1, 1 },
2909 { 0x7fffff, "ULPRX parity error", -1, 1 },
2910 { 0, NULL, 0, 0 }
2911 };
2912
0d804338 2913 if (csio_handle_intr_status(hw, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
a3667aae
NKI		 2914 csio_hw_fatal_err(hw);
2915}
2916
2917/*
2918 * ULP TX interrupt handler.
2919 */
2920static void csio_ulptx_intr_handler(struct csio_hw *hw)
2921{
2922 static struct intr_info ulptx_intr_info[] = {
837e4a42 2923 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
a3667aae 2924 0 },
837e4a42 2925 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
a3667aae 2926 0 },
837e4a42 2927 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
a3667aae 2928 0 },
837e4a42 2929 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
a3667aae
NKI		 2930 0 },
2931 { 0xfffffff, "ULPTX parity error", -1, 1 },
2932 { 0, NULL, 0, 0 }
2933 };
2934
837e4a42 2935 if (csio_handle_intr_status(hw, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
a3667aae
NKI		 2936 csio_hw_fatal_err(hw);
2937}
2938
2939/*
2940 * PM TX interrupt handler.
2941 */
2942static void csio_pmtx_intr_handler(struct csio_hw *hw)
2943{
2944 static struct intr_info pmtx_intr_info[] = {
837e4a42
HS		 2945 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
2946 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
2947 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
2948 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
a3667aae 2949 { 0xffffff0, "PMTX framing error", -1, 1 },
837e4a42
HS		 2950 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
2951 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error", -1,
a3667aae 2952 1 },
837e4a42
HS		 2953 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
2954 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
a3667aae
NKI		 2955 { 0, NULL, 0, 0 }
2956 };
2957
837e4a42 2958 if (csio_handle_intr_status(hw, PM_TX_INT_CAUSE_A, pmtx_intr_info))
a3667aae
NKI		 2959 csio_hw_fatal_err(hw);
2960}
2961
2962/*
2963 * PM RX interrupt handler.
2964 */
2965static void csio_pmrx_intr_handler(struct csio_hw *hw)
2966{
2967 static struct intr_info pmrx_intr_info[] = {
837e4a42 2968 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
a3667aae 2969 { 0x3ffff0, "PMRX framing error", -1, 1 },
837e4a42
HS		 2970 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
2971 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error", -1,
a3667aae 2972 1 },
837e4a42
HS		 2973 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
2974 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
a3667aae
NKI		 2975 { 0, NULL, 0, 0 }
2976 };
2977
837e4a42 2978 if (csio_handle_intr_status(hw, PM_RX_INT_CAUSE_A, pmrx_intr_info))
a3667aae
NKI		 2979 csio_hw_fatal_err(hw);
2980}
2981
2982/*
2983 * CPL switch interrupt handler.
2984 */
2985static void csio_cplsw_intr_handler(struct csio_hw *hw)
2986{
2987 static struct intr_info cplsw_intr_info[] = {
0d804338
HS		 2988 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
2989 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
2990 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
2991 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
2992 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
2993 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
a3667aae
NKI		 2994 { 0, NULL, 0, 0 }
2995 };
2996
0d804338 2997 if (csio_handle_intr_status(hw, CPL_INTR_CAUSE_A, cplsw_intr_info))
a3667aae
NKI		 2998 csio_hw_fatal_err(hw);
2999}
3000
3001/*
3002 * LE interrupt handler.
3003 */
3004static void csio_le_intr_handler(struct csio_hw *hw)
3005{
3006 static struct intr_info le_intr_info[] = {
0d804338
HS		 3007 { LIPMISS_F, "LE LIP miss", -1, 0 },
3008 { LIP0_F, "LE 0 LIP error", -1, 0 },
3009 { PARITYERR_F, "LE parity error", -1, 1 },
3010 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
3011 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
a3667aae
NKI		 3012 { 0, NULL, 0, 0 }
3013 };
3014
0d804338 3015 if (csio_handle_intr_status(hw, LE_DB_INT_CAUSE_A, le_intr_info))
a3667aae
NKI		 3016 csio_hw_fatal_err(hw);
3017}
3018
3019/*
3020 * MPS interrupt handler.
3021 */
3022static void csio_mps_intr_handler(struct csio_hw *hw)
3023{
3024 static struct intr_info mps_rx_intr_info[] = {
3025 { 0xffffff, "MPS Rx parity error", -1, 1 },
3026 { 0, NULL, 0, 0 }
3027 };
3028 static struct intr_info mps_tx_intr_info[] = {
837e4a42
HS		 3029 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
3030 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
3031 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
3032 -1, 1 },
3033 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
3034 -1, 1 },
3035 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
3036 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
3037 { FRMERR_F, "MPS Tx framing error", -1, 1 },
a3667aae
NKI		 3038 { 0, NULL, 0, 0 }
3039 };
3040 static struct intr_info mps_trc_intr_info[] = {
837e4a42
HS		 3041 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
3042 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
3043 -1, 1 },
3044 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
a3667aae
NKI		 3045 { 0, NULL, 0, 0 }
3046 };
3047 static struct intr_info mps_stat_sram_intr_info[] = {
3048 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
3049 { 0, NULL, 0, 0 }
3050 };
3051 static struct intr_info mps_stat_tx_intr_info[] = {
3052 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
3053 { 0, NULL, 0, 0 }
3054 };
3055 static struct intr_info mps_stat_rx_intr_info[] = {
3056 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
3057 { 0, NULL, 0, 0 }
3058 };
3059 static struct intr_info mps_cls_intr_info[] = {
837e4a42
HS		 3060 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
3061 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
3062 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
a3667aae
NKI		 3063 { 0, NULL, 0, 0 }
3064 };
3065
3066 int fat;
3067
837e4a42
HS		 3068 fat = csio_handle_intr_status(hw, MPS_RX_PERR_INT_CAUSE_A,
3069 mps_rx_intr_info) +
3070 csio_handle_intr_status(hw, MPS_TX_INT_CAUSE_A,
3071 mps_tx_intr_info) +
3072 csio_handle_intr_status(hw, MPS_TRC_INT_CAUSE_A,
3073 mps_trc_intr_info) +
3074 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
3075 mps_stat_sram_intr_info) +
3076 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
3077 mps_stat_tx_intr_info) +
3078 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
3079 mps_stat_rx_intr_info) +
3080 csio_handle_intr_status(hw, MPS_CLS_INT_CAUSE_A,
3081 mps_cls_intr_info);
3082
3083 csio_wr_reg32(hw, 0, MPS_INT_CAUSE_A);
3084 csio_rd_reg32(hw, MPS_INT_CAUSE_A); /* flush */
a3667aae
NKI		 3085 if (fat)
3086 csio_hw_fatal_err(hw);
3087}
3088
89c3a86c
HS		 3089#define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
3090 ECC_UE_INT_CAUSE_F)
a3667aae
NKI		 3091
3092/*
3093 * EDC/MC interrupt handler.
3094 */
3095static void csio_mem_intr_handler(struct csio_hw *hw, int idx)
3096{
3097 static const char name[3][5] = { "EDC0", "EDC1", "MC" };
3098
3099 unsigned int addr, cnt_addr, v;
3100
3101 if (idx <= MEM_EDC1) {
89c3a86c
HS		 3102 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
3103 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
a3667aae 3104 } else {
89c3a86c
HS		 3105 addr = MC_INT_CAUSE_A;
3106 cnt_addr = MC_ECC_STATUS_A;
a3667aae
NKI		 3107 }
3108
3109 v = csio_rd_reg32(hw, addr) & MEM_INT_MASK;
89c3a86c 3110 if (v & PERR_INT_CAUSE_F)
a3667aae 3111 csio_fatal(hw, "%s FIFO parity error\n", name[idx]);
89c3a86c
HS		 3112 if (v & ECC_CE_INT_CAUSE_F) {
3113 uint32_t cnt = ECC_CECNT_G(csio_rd_reg32(hw, cnt_addr));
a3667aae 3114
89c3a86c 3115 csio_wr_reg32(hw, ECC_CECNT_V(ECC_CECNT_M), cnt_addr);
a3667aae
NKI		 3116 csio_warn(hw, "%u %s correctable ECC data error%s\n",
3117 cnt, name[idx], cnt > 1 ? "s" : "");
3118 }
89c3a86c 3119 if (v & ECC_UE_INT_CAUSE_F)
a3667aae
NKI		 3120 csio_fatal(hw, "%s uncorrectable ECC data error\n", name[idx]);
3121
3122 csio_wr_reg32(hw, v, addr);
89c3a86c 3123 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
a3667aae
NKI		 3124 csio_hw_fatal_err(hw);
3125}
3126
3127/*
3128 * MA interrupt handler.
3129 */
3130static void csio_ma_intr_handler(struct csio_hw *hw)
3131{
89c3a86c 3132 uint32_t v, status = csio_rd_reg32(hw, MA_INT_CAUSE_A);
a3667aae 3133
89c3a86c 3134 if (status & MEM_PERR_INT_CAUSE_F)
a3667aae 3135 csio_fatal(hw, "MA parity error, parity status %#x\n",
89c3a86c
HS		 3136 csio_rd_reg32(hw, MA_PARITY_ERROR_STATUS_A));
3137 if (status & MEM_WRAP_INT_CAUSE_F) {
3138 v = csio_rd_reg32(hw, MA_INT_WRAP_STATUS_A);
a3667aae
NKI		 3139 csio_fatal(hw,
3140 "MA address wrap-around error by client %u to address %#x\n",
89c3a86c 3141 MEM_WRAP_CLIENT_NUM_G(v), MEM_WRAP_ADDRESS_G(v) << 4);
a3667aae 3142 }
89c3a86c 3143 csio_wr_reg32(hw, status, MA_INT_CAUSE_A);
a3667aae
NKI		 3144 csio_hw_fatal_err(hw);
3145}
3146
3147/*
3148 * SMB interrupt handler.
3149 */
3150static void csio_smb_intr_handler(struct csio_hw *hw)
3151{
3152 static struct intr_info smb_intr_info[] = {
0d804338
HS		 3153 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
3154 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
3155 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
a3667aae
NKI		 3156 { 0, NULL, 0, 0 }
3157 };
3158
0d804338 3159 if (csio_handle_intr_status(hw, SMB_INT_CAUSE_A, smb_intr_info))
a3667aae
NKI		 3160 csio_hw_fatal_err(hw);
3161}
3162
3163/*
3164 * NC-SI interrupt handler.
3165 */
3166static void csio_ncsi_intr_handler(struct csio_hw *hw)
3167{
3168 static struct intr_info ncsi_intr_info[] = {
0d804338
HS		 3169 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
3170 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
3171 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
3172 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
a3667aae
NKI		 3173 { 0, NULL, 0, 0 }
3174 };
3175
0d804338 3176 if (csio_handle_intr_status(hw, NCSI_INT_CAUSE_A, ncsi_intr_info))
a3667aae
NKI		 3177 csio_hw_fatal_err(hw);
3178}
3179
3180/*
3181 * XGMAC interrupt handler.
3182 */
3183static void csio_xgmac_intr_handler(struct csio_hw *hw, int port)
3184{
3fb4c22e 3185 uint32_t v = csio_rd_reg32(hw, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A));
a3667aae 3186
0d804338 3187 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
a3667aae
NKI		 3188 if (!v)
3189 return;
3190
0d804338 3191 if (v & TXFIFO_PRTY_ERR_F)
a3667aae 3192 csio_fatal(hw, "XGMAC %d Tx FIFO parity error\n", port);
0d804338 3193 if (v & RXFIFO_PRTY_ERR_F)
a3667aae 3194 csio_fatal(hw, "XGMAC %d Rx FIFO parity error\n", port);
3fb4c22e 3195 csio_wr_reg32(hw, v, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A));
a3667aae
NKI		 3196 csio_hw_fatal_err(hw);
3197}
3198
3199/*
3200 * PL interrupt handler.
3201 */
3202static void csio_pl_intr_handler(struct csio_hw *hw)
3203{
3204 static struct intr_info pl_intr_info[] = {
0d804338
HS		 3205 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
3206 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
a3667aae
NKI		 3207 { 0, NULL, 0, 0 }
3208 };
3209
0d804338 3210 if (csio_handle_intr_status(hw, PL_PL_INT_CAUSE_A, pl_intr_info))
a3667aae
NKI		 3211 csio_hw_fatal_err(hw);
3212}
3213
3214/*
3215 * csio_hw_slow_intr_handler - control path interrupt handler
3216 * @hw: HW module
3217 *
3218 * Interrupt handler for non-data global interrupt events, e.g., errors.
3219 * The designation 'slow' is because it involves register reads, while
3220 * data interrupts typically don't involve any MMIOs.
3221 */
3222int
3223csio_hw_slow_intr_handler(struct csio_hw *hw)
3224{
0d804338 3225 uint32_t cause = csio_rd_reg32(hw, PL_INT_CAUSE_A);
a3667aae
NKI		 3226
3227 if (!(cause & CSIO_GLBL_INTR_MASK)) {
3228 CSIO_INC_STATS(hw, n_plint_unexp);
3229 return 0;
3230 }
3231
3232 csio_dbg(hw, "Slow interrupt! cause: 0x%x\n", cause);
3233
3234 CSIO_INC_STATS(hw, n_plint_cnt);
3235
0d804338 3236 if (cause & CIM_F)
a3667aae
NKI		 3237 csio_cim_intr_handler(hw);
3238
0d804338 3239 if (cause & MPS_F)
a3667aae
NKI		 3240 csio_mps_intr_handler(hw);
3241
0d804338 3242 if (cause & NCSI_F)
a3667aae
NKI		 3243 csio_ncsi_intr_handler(hw);
3244
0d804338 3245 if (cause & PL_F)
a3667aae
NKI		 3246 csio_pl_intr_handler(hw);
3247
0d804338 3248 if (cause & SMB_F)
a3667aae
NKI		 3249 csio_smb_intr_handler(hw);
3250
0d804338 3251 if (cause & XGMAC0_F)
a3667aae
NKI		 3252 csio_xgmac_intr_handler(hw, 0);
3253
0d804338 3254 if (cause & XGMAC1_F)
a3667aae
NKI		 3255 csio_xgmac_intr_handler(hw, 1);
3256
0d804338 3257 if (cause & XGMAC_KR0_F)
a3667aae
NKI		 3258 csio_xgmac_intr_handler(hw, 2);
3259
0d804338 3260 if (cause & XGMAC_KR1_F)
a3667aae
NKI		 3261 csio_xgmac_intr_handler(hw, 3);
3262
0d804338 3263 if (cause & PCIE_F)
7cc16380 3264 hw->chip_ops->chip_pcie_intr_handler(hw);
a3667aae 3265
0d804338 3266 if (cause & MC_F)
a3667aae
NKI		 3267 csio_mem_intr_handler(hw, MEM_MC);
3268
0d804338 3269 if (cause & EDC0_F)
a3667aae
NKI		 3270 csio_mem_intr_handler(hw, MEM_EDC0);
3271
0d804338 3272 if (cause & EDC1_F)
a3667aae
NKI		 3273 csio_mem_intr_handler(hw, MEM_EDC1);
3274
0d804338 3275 if (cause & LE_F)
a3667aae
NKI		 3276 csio_le_intr_handler(hw);
3277
0d804338 3278 if (cause & TP_F)
a3667aae
NKI		 3279 csio_tp_intr_handler(hw);
3280
0d804338 3281 if (cause & MA_F)
a3667aae
NKI		 3282 csio_ma_intr_handler(hw);
3283
0d804338 3284 if (cause & PM_TX_F)
a3667aae
NKI		 3285 csio_pmtx_intr_handler(hw);
3286
0d804338 3287 if (cause & PM_RX_F)
a3667aae
NKI		 3288 csio_pmrx_intr_handler(hw);
3289
0d804338 3290 if (cause & ULP_RX_F)
a3667aae
NKI		 3291 csio_ulprx_intr_handler(hw);
3292
0d804338 3293 if (cause & CPL_SWITCH_F)
a3667aae
NKI		 3294 csio_cplsw_intr_handler(hw);
3295
0d804338 3296 if (cause & SGE_F)
a3667aae
NKI		 3297 csio_sge_intr_handler(hw);
3298
0d804338 3299 if (cause & ULP_TX_F)
a3667aae
NKI		 3300 csio_ulptx_intr_handler(hw);
3301
3302 /* Clear the interrupts just processed for which we are the master. */
0d804338
HS		 3303 csio_wr_reg32(hw, cause & CSIO_GLBL_INTR_MASK, PL_INT_CAUSE_A);
3304 csio_rd_reg32(hw, PL_INT_CAUSE_A); /* flush */
a3667aae
NKI		 3305
3306 return 1;
3307}
3308
3309/*****************************************************************************
3310 * HW <--> mailbox interfacing routines.
3311 ****************************************************************************/
3312/*
3313 * csio_mberr_worker - Worker thread (dpc) for mailbox/error completions
3314 *
3315 * @data: Private data pointer.
3316 *
3317 * Called from worker thread context.
3318 */
3319static void
3320csio_mberr_worker(void *data)
3321{
3322 struct csio_hw *hw = (struct csio_hw *)data;
3323 struct csio_mbm *mbm = &hw->mbm;
3324 LIST_HEAD(cbfn_q);
3325 struct csio_mb *mbp_next;
3326 int rv;
3327
3328 del_timer_sync(&mbm->timer);
3329
3330 spin_lock_irq(&hw->lock);
3331 if (list_empty(&mbm->cbfn_q)) {
3332 spin_unlock_irq(&hw->lock);
3333 return;
3334 }
3335
3336 list_splice_tail_init(&mbm->cbfn_q, &cbfn_q);
3337 mbm->stats.n_cbfnq = 0;
3338
3339 /* Try to start waiting mailboxes */
3340 if (!list_empty(&mbm->req_q)) {
3341 mbp_next = list_first_entry(&mbm->req_q, struct csio_mb, list);
3342 list_del_init(&mbp_next->list);
3343
3344 rv = csio_mb_issue(hw, mbp_next);
3345 if (rv != 0)
3346 list_add_tail(&mbp_next->list, &mbm->req_q);
3347 else
3348 CSIO_DEC_STATS(mbm, n_activeq);
3349 }
3350 spin_unlock_irq(&hw->lock);
3351
3352 /* Now callback completions */
3353 csio_mb_completions(hw, &cbfn_q);
3354}
3355
3356/*
3357 * csio_hw_mb_timer - Top-level Mailbox timeout handler.
3358 *
3359 * @data: private data pointer
3360 *
3361 **/
3362static void
3363csio_hw_mb_timer(uintptr_t data)
3364{
3365 struct csio_hw *hw = (struct csio_hw *)data;
3366 struct csio_mb *mbp = NULL;
3367
3368 spin_lock_irq(&hw->lock);
3369 mbp = csio_mb_tmo_handler(hw);
3370 spin_unlock_irq(&hw->lock);
3371
3372 /* Call back the function for the timed-out Mailbox */
3373 if (mbp)
3374 mbp->mb_cbfn(hw, mbp);
3375
3376}
3377
3378/*
3379 * csio_hw_mbm_cleanup - Cleanup Mailbox module.
3380 * @hw: HW module
3381 *
3382 * Called with lock held, should exit with lock held.
3383 * Cancels outstanding mailboxes (waiting, in-flight) and gathers them
3384 * into a local queue. Drops lock and calls the completions. Holds
3385 * lock and returns.
3386 */
3387static void
3388csio_hw_mbm_cleanup(struct csio_hw *hw)
3389{
3390 LIST_HEAD(cbfn_q);
3391
3392 csio_mb_cancel_all(hw, &cbfn_q);
3393
3394 spin_unlock_irq(&hw->lock);
3395 csio_mb_completions(hw, &cbfn_q);
3396 spin_lock_irq(&hw->lock);
3397}
3398
3399/*****************************************************************************
3400 * Event handling
3401 ****************************************************************************/
3402int
3403csio_enqueue_evt(struct csio_hw *hw, enum csio_evt type, void *evt_msg,
3404 uint16_t len)
3405{
3406 struct csio_evt_msg *evt_entry = NULL;
3407
3408 if (type >= CSIO_EVT_MAX)
3409 return -EINVAL;
3410
3411 if (len > CSIO_EVT_MSG_SIZE)
3412 return -EINVAL;
3413
3414 if (hw->flags & CSIO_HWF_FWEVT_STOP)
3415 return -EINVAL;
3416
3417 if (list_empty(&hw->evt_free_q)) {
3418 csio_err(hw, "Failed to alloc evt entry, msg type %d len %d\n",
3419 type, len);
3420 return -ENOMEM;
3421 }
3422
3423 evt_entry = list_first_entry(&hw->evt_free_q,
3424 struct csio_evt_msg, list);
3425 list_del_init(&evt_entry->list);
3426
3427 /* copy event msg and queue the event */
3428 evt_entry->type = type;
3429 memcpy((void *)evt_entry->data, evt_msg, len);
3430 list_add_tail(&evt_entry->list, &hw->evt_active_q);
3431
3432 CSIO_DEC_STATS(hw, n_evt_freeq);
3433 CSIO_INC_STATS(hw, n_evt_activeq);
3434
3435 return 0;
3436}
3437
3438static int
3439csio_enqueue_evt_lock(struct csio_hw *hw, enum csio_evt type, void *evt_msg,
3440 uint16_t len, bool msg_sg)
3441{
3442 struct csio_evt_msg *evt_entry = NULL;
3443 struct csio_fl_dma_buf *fl_sg;
3444 uint32_t off = 0;
3445 unsigned long flags;
3446 int n, ret = 0;
3447
3448 if (type >= CSIO_EVT_MAX)
3449 return -EINVAL;
3450
3451 if (len > CSIO_EVT_MSG_SIZE)
3452 return -EINVAL;
3453
3454 spin_lock_irqsave(&hw->lock, flags);
3455 if (hw->flags & CSIO_HWF_FWEVT_STOP) {
3456 ret = -EINVAL;
3457 goto out;
3458 }
3459
3460 if (list_empty(&hw->evt_free_q)) {
3461 csio_err(hw, "Failed to alloc evt entry, msg type %d len %d\n",
3462 type, len);
3463 ret = -ENOMEM;
3464 goto out;
3465 }
3466
3467 evt_entry = list_first_entry(&hw->evt_free_q,
3468 struct csio_evt_msg, list);
3469 list_del_init(&evt_entry->list);
3470
3471 /* copy event msg and queue the event */
3472 evt_entry->type = type;
3473
3474 /* If Payload in SG list*/
3475 if (msg_sg) {
3476 fl_sg = (struct csio_fl_dma_buf *) evt_msg;
3477 for (n = 0; (n < CSIO_MAX_FLBUF_PER_IQWR && off < len); n++) {
3478 memcpy((void *)((uintptr_t)evt_entry->data + off),
3479 fl_sg->flbufs[n].vaddr,
3480 fl_sg->flbufs[n].len);
3481 off += fl_sg->flbufs[n].len;
3482 }
3483 } else
3484 memcpy((void *)evt_entry->data, evt_msg, len);
3485
3486 list_add_tail(&evt_entry->list, &hw->evt_active_q);
3487 CSIO_DEC_STATS(hw, n_evt_freeq);
3488 CSIO_INC_STATS(hw, n_evt_activeq);
3489out:
3490 spin_unlock_irqrestore(&hw->lock, flags);
3491 return ret;
3492}
3493
3494static void
3495csio_free_evt(struct csio_hw *hw, struct csio_evt_msg *evt_entry)
3496{
3497 if (evt_entry) {
3498 spin_lock_irq(&hw->lock);
3499 list_del_init(&evt_entry->list);
3500 list_add_tail(&evt_entry->list, &hw->evt_free_q);
3501 CSIO_DEC_STATS(hw, n_evt_activeq);
3502 CSIO_INC_STATS(hw, n_evt_freeq);
3503 spin_unlock_irq(&hw->lock);
3504 }
3505}
3506
3507void
3508csio_evtq_flush(struct csio_hw *hw)
3509{
3510 uint32_t count;
3511 count = 30;
3512 while (hw->flags & CSIO_HWF_FWEVT_PENDING && count--) {
3513 spin_unlock_irq(&hw->lock);
3514 msleep(2000);
3515 spin_lock_irq(&hw->lock);
3516 }
3517
3518 CSIO_DB_ASSERT(!(hw->flags & CSIO_HWF_FWEVT_PENDING));
3519}
3520
3521static void
3522csio_evtq_stop(struct csio_hw *hw)
3523{
3524 hw->flags |= CSIO_HWF_FWEVT_STOP;
3525}
3526
3527static void
3528csio_evtq_start(struct csio_hw *hw)
3529{
3530 hw->flags &= ~CSIO_HWF_FWEVT_STOP;
3531}
3532
3533static void
3534csio_evtq_cleanup(struct csio_hw *hw)
3535{
3536 struct list_head *evt_entry, *next_entry;
3537
3538 /* Release outstanding events from activeq to freeq*/
3539 if (!list_empty(&hw->evt_active_q))
3540 list_splice_tail_init(&hw->evt_active_q, &hw->evt_free_q);
3541
3542 hw->stats.n_evt_activeq = 0;
3543 hw->flags &= ~CSIO_HWF_FWEVT_PENDING;
3544
3545 /* Freeup event entry */
3546 list_for_each_safe(evt_entry, next_entry, &hw->evt_free_q) {
3547 kfree(evt_entry);
3548 CSIO_DEC_STATS(hw, n_evt_freeq);
3549 }
3550
3551 hw->stats.n_evt_freeq = 0;
3552}
3553
3554
3555static void
3556csio_process_fwevtq_entry(struct csio_hw *hw, void *wr, uint32_t len,
3557 struct csio_fl_dma_buf *flb, void *priv)
3558{
3559 __u8 op;
a3667aae
NKI		 3560 void *msg = NULL;
3561 uint32_t msg_len = 0;
3562 bool msg_sg = 0;
3563
3564 op = ((struct rss_header *) wr)->opcode;
3565 if (op == CPL_FW6_PLD) {
3566 CSIO_INC_STATS(hw, n_cpl_fw6_pld);
3567 if (!flb || !flb->totlen) {
3568 CSIO_INC_STATS(hw, n_cpl_unexp);
3569 return;
3570 }
3571
3572 msg = (void *) flb;
3573 msg_len = flb->totlen;
3574 msg_sg = 1;
a3667aae
NKI		 3575 } else if (op == CPL_FW6_MSG || op == CPL_FW4_MSG) {
3576
3577 CSIO_INC_STATS(hw, n_cpl_fw6_msg);
3578 /* skip RSS header */
3579 msg = (void *)((uintptr_t)wr + sizeof(__be64));
3580 msg_len = (op == CPL_FW6_MSG) ? sizeof(struct cpl_fw6_msg) :
3581 sizeof(struct cpl_fw4_msg);
a3667aae
NKI		 3582 } else {
3583 csio_warn(hw, "unexpected CPL %#x on FW event queue\n", op);
3584 CSIO_INC_STATS(hw, n_cpl_unexp);
3585 return;
3586 }
3587
3588 /*
3589 * Enqueue event to EventQ. Events processing happens
3590 * in Event worker thread context
3591 */
3592 if (csio_enqueue_evt_lock(hw, CSIO_EVT_FW, msg,
3593 (uint16_t)msg_len, msg_sg))
3594 CSIO_INC_STATS(hw, n_evt_drop);
3595}
3596
3597void
3598csio_evtq_worker(struct work_struct *work)
3599{
3600 struct csio_hw *hw = container_of(work, struct csio_hw, evtq_work);
3601 struct list_head *evt_entry, *next_entry;
3602 LIST_HEAD(evt_q);
3603 struct csio_evt_msg *evt_msg;
3604 struct cpl_fw6_msg *msg;
3605 struct csio_rnode *rn;
3606 int rv = 0;
3607 uint8_t evtq_stop = 0;
3608
3609 csio_dbg(hw, "event worker thread active evts#%d\n",
3610 hw->stats.n_evt_activeq);
3611
3612 spin_lock_irq(&hw->lock);
3613 while (!list_empty(&hw->evt_active_q)) {
3614 list_splice_tail_init(&hw->evt_active_q, &evt_q);
3615 spin_unlock_irq(&hw->lock);
3616
3617 list_for_each_safe(evt_entry, next_entry, &evt_q) {
3618 evt_msg = (struct csio_evt_msg *) evt_entry;
3619
3620 /* Drop events if queue is STOPPED */
3621 spin_lock_irq(&hw->lock);
3622 if (hw->flags & CSIO_HWF_FWEVT_STOP)
3623 evtq_stop = 1;
3624 spin_unlock_irq(&hw->lock);
3625 if (evtq_stop) {
3626 CSIO_INC_STATS(hw, n_evt_drop);
3627 goto free_evt;
3628 }
3629
3630 switch (evt_msg->type) {
3631 case CSIO_EVT_FW:
3632 msg = (struct cpl_fw6_msg *)(evt_msg->data);
3633
3634 if ((msg->opcode == CPL_FW6_MSG ||
3635 msg->opcode == CPL_FW4_MSG) &&
3636 !msg->type) {
3637 rv = csio_mb_fwevt_handler(hw,
3638 msg->data);
3639 if (!rv)
3640 break;
3641 /* Handle any remaining fw events */
3642 csio_fcoe_fwevt_handler(hw,
3643 msg->opcode, msg->data);
3644 } else if (msg->opcode == CPL_FW6_PLD) {
3645
3646 csio_fcoe_fwevt_handler(hw,
3647 msg->opcode, msg->data);
3648 } else {
3649 csio_warn(hw,
3650 "Unhandled FW msg op %x type %x\n",
3651 msg->opcode, msg->type);
3652 CSIO_INC_STATS(hw, n_evt_drop);
3653 }
3654 break;
3655
3656 case CSIO_EVT_MBX:
3657 csio_mberr_worker(hw);
3658 break;
3659
3660 case CSIO_EVT_DEV_LOSS:
3661 memcpy(&rn, evt_msg->data, sizeof(rn));
3662 csio_rnode_devloss_handler(rn);
3663 break;
3664
3665 default:
3666 csio_warn(hw, "Unhandled event %x on evtq\n",
3667 evt_msg->type);
3668 CSIO_INC_STATS(hw, n_evt_unexp);
3669 break;
3670 }
3671free_evt:
3672 csio_free_evt(hw, evt_msg);
3673 }
3674
3675 spin_lock_irq(&hw->lock);
3676 }
3677 hw->flags &= ~CSIO_HWF_FWEVT_PENDING;
3678 spin_unlock_irq(&hw->lock);
3679}
3680
3681int
3682csio_fwevtq_handler(struct csio_hw *hw)
3683{
3684 int rv;
3685
3686 if (csio_q_iqid(hw, hw->fwevt_iq_idx) == CSIO_MAX_QID) {
3687 CSIO_INC_STATS(hw, n_int_stray);
3688 return -EINVAL;
3689 }
3690
3691 rv = csio_wr_process_iq_idx(hw, hw->fwevt_iq_idx,
3692 csio_process_fwevtq_entry, NULL);
3693 return rv;
3694}
3695
3696/****************************************************************************
3697 * Entry points
3698 ****************************************************************************/
3699
3700/* Management module */
3701/*
3702 * csio_mgmt_req_lookup - Lookup the given IO req exist in Active Q.
3703 * mgmt - mgmt module
3704 * @io_req - io request
3705 *
3706 * Return - 0:if given IO Req exists in active Q.
3707 * -EINVAL :if lookup fails.
3708 */
3709int
3710csio_mgmt_req_lookup(struct csio_mgmtm *mgmtm, struct csio_ioreq *io_req)
3711{
3712 struct list_head *tmp;
3713
3714 /* Lookup ioreq in the ACTIVEQ */
3715 list_for_each(tmp, &mgmtm->active_q) {
3716 if (io_req == (struct csio_ioreq *)tmp)
3717 return 0;
3718 }
3719 return -EINVAL;
3720}
3721
3722#define ECM_MIN_TMO 1000 /* Minimum timeout value for req */
3723
3724/*
3725 * csio_mgmts_tmo_handler - MGMT IO Timeout handler.
3726 * @data - Event data.
3727 *
3728 * Return - none.
3729 */
3730static void
3731csio_mgmt_tmo_handler(uintptr_t data)
3732{
3733 struct csio_mgmtm *mgmtm = (struct csio_mgmtm *) data;
3734 struct list_head *tmp;
3735 struct csio_ioreq *io_req;
3736
3737 csio_dbg(mgmtm->hw, "Mgmt timer invoked!\n");
3738
3739 spin_lock_irq(&mgmtm->hw->lock);
3740
3741 list_for_each(tmp, &mgmtm->active_q) {
3742 io_req = (struct csio_ioreq *) tmp;
3743 io_req->tmo -= min_t(uint32_t, io_req->tmo, ECM_MIN_TMO);
3744
3745 if (!io_req->tmo) {
3746 /* Dequeue the request from retry Q. */
3747 tmp = csio_list_prev(tmp);
3748 list_del_init(&io_req->sm.sm_list);
3749 if (io_req->io_cbfn) {
3750 /* io_req will be freed by completion handler */
3751 io_req->wr_status = -ETIMEDOUT;
3752 io_req->io_cbfn(mgmtm->hw, io_req);
3753 } else {
3754 CSIO_DB_ASSERT(0);
3755 }
3756 }
3757 }
3758
3759 /* If retry queue is not empty, re-arm timer */
3760 if (!list_empty(&mgmtm->active_q))
3761 mod_timer(&mgmtm->mgmt_timer,
3762 jiffies + msecs_to_jiffies(ECM_MIN_TMO));
3763 spin_unlock_irq(&mgmtm->hw->lock);
3764}
3765
3766static void
3767csio_mgmtm_cleanup(struct csio_mgmtm *mgmtm)
3768{
3769 struct csio_hw *hw = mgmtm->hw;
3770 struct csio_ioreq *io_req;
3771 struct list_head *tmp;
3772 uint32_t count;
3773
3774 count = 30;
3775 /* Wait for all outstanding req to complete gracefully */
3776 while ((!list_empty(&mgmtm->active_q)) && count--) {
3777 spin_unlock_irq(&hw->lock);
3778 msleep(2000);
3779 spin_lock_irq(&hw->lock);
3780 }
3781
3782 /* release outstanding req from ACTIVEQ */
3783 list_for_each(tmp, &mgmtm->active_q) {
3784 io_req = (struct csio_ioreq *) tmp;
3785 tmp = csio_list_prev(tmp);
3786 list_del_init(&io_req->sm.sm_list);
3787 mgmtm->stats.n_active--;
3788 if (io_req->io_cbfn) {
3789 /* io_req will be freed by completion handler */
3790 io_req->wr_status = -ETIMEDOUT;
3791 io_req->io_cbfn(mgmtm->hw, io_req);
3792 }
3793 }
3794}
3795
3796/*
3797 * csio_mgmt_init - Mgmt module init entry point
3798 * @mgmtsm - mgmt module
3799 * @hw - HW module
3800 *
3801 * Initialize mgmt timer, resource wait queue, active queue,
3802 * completion q. Allocate Egress and Ingress
3803 * WR queues and save off the queue index returned by the WR
3804 * module for future use. Allocate and save off mgmt reqs in the
3805 * mgmt_req_freelist for future use. Make sure their SM is initialized
3806 * to uninit state.
3807 * Returns: 0 - on success
3808 * -ENOMEM - on error.
3809 */
3810static int
3811csio_mgmtm_init(struct csio_mgmtm *mgmtm, struct csio_hw *hw)
3812{
3813 struct timer_list *timer = &mgmtm->mgmt_timer;
3814
3815 init_timer(timer);
3816 timer->function = csio_mgmt_tmo_handler;
3817 timer->data = (unsigned long)mgmtm;
3818
3819 INIT_LIST_HEAD(&mgmtm->active_q);
3820 INIT_LIST_HEAD(&mgmtm->cbfn_q);
3821
3822 mgmtm->hw = hw;
3823 /*mgmtm->iq_idx = hw->fwevt_iq_idx;*/
3824
3825 return 0;
3826}
3827
3828/*
3829 * csio_mgmtm_exit - MGMT module exit entry point
3830 * @mgmtsm - mgmt module
3831 *
3832 * This function called during MGMT module uninit.
3833 * Stop timers, free ioreqs allocated.
3834 * Returns: None
3835 *
3836 */
3837static void
3838csio_mgmtm_exit(struct csio_mgmtm *mgmtm)
3839{
3840 del_timer_sync(&mgmtm->mgmt_timer);
3841}
3842
3843
3844/**
3845 * csio_hw_start - Kicks off the HW State machine
3846 * @hw: Pointer to HW module.
3847 *
3848 * It is assumed that the initialization is a synchronous operation.
3849 * So when we return afer posting the event, the HW SM should be in
3850 * the ready state, if there were no errors during init.
3851 */
3852int
3853csio_hw_start(struct csio_hw *hw)
3854{
3855 spin_lock_irq(&hw->lock);
3856 csio_post_event(&hw->sm, CSIO_HWE_CFG);
3857 spin_unlock_irq(&hw->lock);
3858
3859 if (csio_is_hw_ready(hw))
3860 return 0;
3861 else
3862 return -EINVAL;
3863}
3864
3865int
3866csio_hw_stop(struct csio_hw *hw)
3867{
3868 csio_post_event(&hw->sm, CSIO_HWE_PCI_REMOVE);
3869
3870 if (csio_is_hw_removing(hw))
3871 return 0;
3872 else
3873 return -EINVAL;
3874}
3875
3876/* Max reset retries */
3877#define CSIO_MAX_RESET_RETRIES 3
3878
3879/**
3880 * csio_hw_reset - Reset the hardware
3881 * @hw: HW module.
3882 *
3883 * Caller should hold lock across this function.
3884 */
3885int
3886csio_hw_reset(struct csio_hw *hw)
3887{
3888 if (!csio_is_hw_master(hw))
3889 return -EPERM;
3890
3891 if (hw->rst_retries >= CSIO_MAX_RESET_RETRIES) {
3892 csio_dbg(hw, "Max hw reset attempts reached..");
3893 return -EINVAL;
3894 }
3895
3896 hw->rst_retries++;
3897 csio_post_event(&hw->sm, CSIO_HWE_HBA_RESET);
3898
3899 if (csio_is_hw_ready(hw)) {
3900 hw->rst_retries = 0;
3901 hw->stats.n_reset_start = jiffies_to_msecs(jiffies);
3902 return 0;
3903 } else
3904 return -EINVAL;
3905}
3906
3907/*
3908 * csio_hw_get_device_id - Caches the Adapter's vendor & device id.
3909 * @hw: HW module.
3910 */
3911static void
3912csio_hw_get_device_id(struct csio_hw *hw)
3913{
3914 /* Is the adapter device id cached already ?*/
3915 if (csio_is_dev_id_cached(hw))
3916 return;
3917
3918 /* Get the PCI vendor & device id */
3919 pci_read_config_word(hw->pdev, PCI_VENDOR_ID,
3920 &hw->params.pci.vendor_id);
3921 pci_read_config_word(hw->pdev, PCI_DEVICE_ID,
3922 &hw->params.pci.device_id);
3923
3924 csio_dev_id_cached(hw);
7cc16380 3925 hw->chip_id = (hw->params.pci.device_id & CSIO_HW_CHIP_MASK);
a3667aae
NKI		 3926
3927} /* csio_hw_get_device_id */
3928
3929/*
3930 * csio_hw_set_description - Set the model, description of the hw.
3931 * @hw: HW module.
3932 * @ven_id: PCI Vendor ID
3933 * @dev_id: PCI Device ID
3934 */
3935static void
3936csio_hw_set_description(struct csio_hw *hw, uint16_t ven_id, uint16_t dev_id)
3937{
3938 uint32_t adap_type, prot_type;
3939
3940 if (ven_id == CSIO_VENDOR_ID) {
3941 prot_type = (dev_id & CSIO_ASIC_DEVID_PROTO_MASK);
3942 adap_type = (dev_id & CSIO_ASIC_DEVID_TYPE_MASK);
3943
3fb4c22e 3944 if (prot_type == CSIO_T5_FCOE_ASIC) {
a3667aae 3945 memcpy(hw->hw_ver,
7cc16380 3946 csio_t5_fcoe_adapters[adap_type].model_no, 16);
a3667aae 3947 memcpy(hw->model_desc,
7cc16380
AB		 3948 csio_t5_fcoe_adapters[adap_type].description,
3949 32);
a3667aae
NKI		 3950 } else {
3951 char tempName[32] = "Chelsio FCoE Controller";
3952 memcpy(hw->model_desc, tempName, 32);
a3667aae
NKI		 3953 }
3954 }
3955} /* csio_hw_set_description */
3956
3957/**
3958 * csio_hw_init - Initialize HW module.
3959 * @hw: Pointer to HW module.
3960 *
3961 * Initialize the members of the HW module.
3962 */
3963int
3964csio_hw_init(struct csio_hw *hw)
3965{
3966 int rv = -EINVAL;
3967 uint32_t i;
3968 uint16_t ven_id, dev_id;
3969 struct csio_evt_msg *evt_entry;
3970
3971 INIT_LIST_HEAD(&hw->sm.sm_list);
3972 csio_init_state(&hw->sm, csio_hws_uninit);
3973 spin_lock_init(&hw->lock);
3974 INIT_LIST_HEAD(&hw->sln_head);
3975
3976 /* Get the PCI vendor & device id */
3977 csio_hw_get_device_id(hw);
3978
3979 strcpy(hw->name, CSIO_HW_NAME);
3980
3fb4c22e
PM		 3981 /* Initialize the HW chip ops T5 specific ops */
3982 hw->chip_ops = &t5_ops;
7cc16380 3983
a3667aae
NKI		 3984 /* Set the model & its description */
3985
3986 ven_id = hw->params.pci.vendor_id;
3987 dev_id = hw->params.pci.device_id;
3988
3989 csio_hw_set_description(hw, ven_id, dev_id);
3990
3991 /* Initialize default log level */
3992 hw->params.log_level = (uint32_t) csio_dbg_level;
3993
3994 csio_set_fwevt_intr_idx(hw, -1);
3995 csio_set_nondata_intr_idx(hw, -1);
3996
3997 /* Init all the modules: Mailbox, WorkRequest and Transport */
3998 if (csio_mbm_init(csio_hw_to_mbm(hw), hw, csio_hw_mb_timer))
3999 goto err;
4000
4001 rv = csio_wrm_init(csio_hw_to_wrm(hw), hw);
4002 if (rv)
4003 goto err_mbm_exit;
4004
4005 rv = csio_scsim_init(csio_hw_to_scsim(hw), hw);
4006 if (rv)
4007 goto err_wrm_exit;
4008
4009 rv = csio_mgmtm_init(csio_hw_to_mgmtm(hw), hw);
4010 if (rv)
4011 goto err_scsim_exit;
4012 /* Pre-allocate evtq and initialize them */
4013 INIT_LIST_HEAD(&hw->evt_active_q);
4014 INIT_LIST_HEAD(&hw->evt_free_q);
4015 for (i = 0; i < csio_evtq_sz; i++) {
4016
4017 evt_entry = kzalloc(sizeof(struct csio_evt_msg), GFP_KERNEL);
4018 if (!evt_entry) {
4019 csio_err(hw, "Failed to initialize eventq");
4020 goto err_evtq_cleanup;
4021 }
4022
4023 list_add_tail(&evt_entry->list, &hw->evt_free_q);
4024 CSIO_INC_STATS(hw, n_evt_freeq);
4025 }
4026
4027 hw->dev_num = dev_num;
4028 dev_num++;
4029
4030 return 0;
4031
4032err_evtq_cleanup:
4033 csio_evtq_cleanup(hw);
4034 csio_mgmtm_exit(csio_hw_to_mgmtm(hw));
4035err_scsim_exit:
4036 csio_scsim_exit(csio_hw_to_scsim(hw));
4037err_wrm_exit:
4038 csio_wrm_exit(csio_hw_to_wrm(hw), hw);
4039err_mbm_exit:
4040 csio_mbm_exit(csio_hw_to_mbm(hw));
4041err:
4042 return rv;
4043}
4044
4045/**
4046 * csio_hw_exit - Un-initialize HW module.
4047 * @hw: Pointer to HW module.
4048 *
4049 */
4050void
4051csio_hw_exit(struct csio_hw *hw)
4052{
4053 csio_evtq_cleanup(hw);
4054 csio_mgmtm_exit(csio_hw_to_mgmtm(hw));
4055 csio_scsim_exit(csio_hw_to_scsim(hw));
4056 csio_wrm_exit(csio_hw_to_wrm(hw), hw);
4057 csio_mbm_exit(csio_hw_to_mbm(hw));
4058}
Linux kernel - Deliverables
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