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[SCSI] gdth: split out isa probing
[deliverable/linux.git] / drivers / scsi / gdth.c
CommitLineData
1da177e4
LT		 1/************************************************************************
2 * Linux driver for *
3 * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
4 * Intel Corporation: Storage RAID Controllers *
5 * *
6 * gdth.c *
cbd5f69b 7 * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
1da177e4 8 * Copyright (C) 2002-04 Intel Corporation *
cbd5f69b 9 * Copyright (C) 2003-06 Adaptec Inc. *
1da177e4
LT		 10 * <achim_leubner@adaptec.com> *
11 * *
12 * Additions/Fixes: *
13 * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
14 * Johannes Dinner <johannes_dinner@adaptec.com> *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published *
18 * by the Free Software Foundation; either version 2 of the License, *
19 * or (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this kernel; if not, write to the Free Software *
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
29 * *
cbd5f69b 30 * Linux kernel 2.4.x, 2.6.x supported *
1da177e4
LT		 31 * *
32 * $Log: gdth.c,v $
cbd5f69b
LA		 33 * Revision 1.74 2006/04/10 13:44:47 achim
34 * Community changes for 2.6.x
35 * Kernel 2.2.x no longer supported
36 * scsi_request interface removed, thanks to Christoph Hellwig
37 *
1da177e4
LT		 38 * Revision 1.73 2004/03/31 13:33:03 achim
39 * Special command 0xfd implemented to detect 64-bit DMA support
40 *
41 * Revision 1.72 2004/03/17 08:56:04 achim
42 * 64-bit DMA only enabled if FW >= x.43
43 *
44 * Revision 1.71 2004/03/05 15:51:29 achim
45 * Screen service: separate message buffer, bugfixes
46 *
47 * Revision 1.70 2004/02/27 12:19:07 achim
48 * Bugfix: Reset bit in config (0xfe) call removed
49 *
50 * Revision 1.69 2004/02/20 09:50:24 achim
51 * Compatibility changes for kernels < 2.4.20
52 * Bugfix screen service command size
53 * pci_set_dma_mask() error handling added
54 *
55 * Revision 1.68 2004/02/19 15:46:54 achim
56 * 64-bit DMA bugfixes
57 * Drive size bugfix for drives > 1TB
58 *
59 * Revision 1.67 2004/01/14 13:11:57 achim
60 * Tool access over /proc no longer supported
61 * Bugfixes IOCTLs
62 *
63 * Revision 1.66 2003/12/19 15:04:06 achim
64 * Bugfixes support for drives > 2TB
65 *
66 * Revision 1.65 2003/12/15 11:21:56 achim
67 * 64-bit DMA support added
68 * Support for drives > 2 TB implemented
69 * Kernels 2.2.x, 2.4.x, 2.6.x supported
70 *
71 * Revision 1.64 2003/09/17 08:30:26 achim
72 * EISA/ISA controller scan disabled
73 * Command line switch probe_eisa_isa added
74 *
75 * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <bellucda@tiscali.it>
76 * Minor cleanups in gdth_ioctl.
77 *
78 * Revision 1.62 2003/02/27 15:01:59 achim
79 * Dynamic DMA mapping implemented
80 * New (character device) IOCTL interface added
81 * Other controller related changes made
82 *
83 * Revision 1.61 2002/11/08 13:09:52 boji
84 * Added support for XSCALE based RAID Controllers
85 * Fixed SCREENSERVICE initialization in SMP cases
86 * Added checks for gdth_polling before GDTH_HA_LOCK
87 *
88 * Revision 1.60 2002/02/05 09:35:22 achim
89 * MODULE_LICENSE only if kernel >= 2.4.11
90 *
91 * Revision 1.59 2002/01/30 09:46:33 achim
92 * Small changes
93 *
94 * Revision 1.58 2002/01/29 15:30:02 achim
95 * Set default value of shared_access to Y
96 * New status S_CACHE_RESERV for clustering added
97 *
98 * Revision 1.57 2001/08/21 11:16:35 achim
99 * Bugfix free_irq()
100 *
101 * Revision 1.56 2001/08/09 11:19:39 achim
cbd5f69b 102 * Scsi_Host_Template changes
1da177e4
LT		 103 *
104 * Revision 1.55 2001/08/09 10:11:28 achim
105 * Command HOST_UNFREEZE_IO before cache service init.
106 *
107 * Revision 1.54 2001/07/20 13:48:12 achim
108 * Expand: gdth_analyse_hdrive() removed
109 *
110 * Revision 1.53 2001/07/17 09:52:49 achim
111 * Small OEM related change
112 *
113 * Revision 1.52 2001/06/19 15:06:20 achim
114 * New host command GDT_UNFREEZE_IO added
115 *
116 * Revision 1.51 2001/05/22 06:42:37 achim
117 * PCI: Subdevice ID added
118 *
119 * Revision 1.50 2001/05/17 13:42:16 achim
120 * Support for Intel Storage RAID Controllers added
121 *
122 * Revision 1.50 2001/05/17 12:12:34 achim
123 * Support for Intel Storage RAID Controllers added
124 *
125 * Revision 1.49 2001/03/15 15:07:17 achim
126 * New __setup interface for boot command line options added
127 *
128 * Revision 1.48 2001/02/06 12:36:28 achim
129 * Bugfix Cluster protocol
130 *
131 * Revision 1.47 2001/01/10 14:42:06 achim
132 * New switch shared_access added
133 *
134 * Revision 1.46 2001/01/09 08:11:35 achim
135 * gdth_command() removed
136 * meaning of Scsi_Pointer members changed
137 *
138 * Revision 1.45 2000/11/16 12:02:24 achim
139 * Changes for kernel 2.4
140 *
141 * Revision 1.44 2000/10/11 08:44:10 achim
142 * Clustering changes: New flag media_changed added
143 *
144 * Revision 1.43 2000/09/20 12:59:01 achim
145 * DPMEM remap functions for all PCI controller types implemented
146 * Small changes for ia64 platform
147 *
148 * Revision 1.42 2000/07/20 09:04:50 achim
149 * Small changes for kernel 2.4
150 *
151 * Revision 1.41 2000/07/04 14:11:11 achim
152 * gdth_analyse_hdrive() added to rescan drives after online expansion
153 *
154 * Revision 1.40 2000/06/27 11:24:16 achim
155 * Changes Clustering, Screenservice
156 *
157 * Revision 1.39 2000/06/15 13:09:04 achim
158 * Changes for gdth_do_cmd()
159 *
160 * Revision 1.38 2000/06/15 12:08:43 achim
161 * Bugfix gdth_sync_event(), service SCREENSERVICE
162 * Data direction for command 0xc2 changed to DOU
163 *
164 * Revision 1.37 2000/05/25 13:50:10 achim
165 * New driver parameter virt_ctr added
166 *
167 * Revision 1.36 2000/05/04 08:50:46 achim
168 * Event buffer now in gdth_ha_str
169 *
170 * Revision 1.35 2000/03/03 10:44:08 achim
171 * New event_string only valid for the RP controller family
172 *
173 * Revision 1.34 2000/03/02 14:55:29 achim
174 * New mechanism for async. event handling implemented
175 *
176 * Revision 1.33 2000/02/21 15:37:37 achim
177 * Bugfix Alpha platform + DPMEM above 4GB
178 *
179 * Revision 1.32 2000/02/14 16:17:37 achim
180 * Bugfix sense_buffer[] + raw devices
181 *
182 * Revision 1.31 2000/02/10 10:29:00 achim
183 * Delete sense_buffer[0], if command OK
184 *
185 * Revision 1.30 1999/11/02 13:42:39 achim
186 * ARRAY_DRV_LIST2 implemented
187 * Now 255 log. and 100 host drives supported
188 *
189 * Revision 1.29 1999/10/05 13:28:47 achim
190 * GDT_CLUST_RESET added
191 *
192 * Revision 1.28 1999/08/12 13:44:54 achim
193 * MOUNTALL removed
194 * Cluster drives -> removeable drives
195 *
196 * Revision 1.27 1999/06/22 07:22:38 achim
197 * Small changes
198 *
199 * Revision 1.26 1999/06/10 16:09:12 achim
200 * Cluster Host Drive support: Bugfixes
201 *
202 * Revision 1.25 1999/06/01 16:03:56 achim
203 * gdth_init_pci(): Manipulate config. space to start RP controller
204 *
205 * Revision 1.24 1999/05/26 11:53:06 achim
206 * Cluster Host Drive support added
207 *
208 * Revision 1.23 1999/03/26 09:12:31 achim
209 * Default value for hdr_channel set to 0
210 *
211 * Revision 1.22 1999/03/22 16:27:16 achim
212 * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA()
213 *
214 * Revision 1.21 1999/03/16 13:40:34 achim
215 * Problems with reserved drives solved
216 * gdth_eh_bus_reset() implemented
217 *
218 * Revision 1.20 1999/03/10 09:08:13 achim
219 * Bugfix: Corrections in gdth_direction_tab[] made
220 * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq()
221 *
222 * Revision 1.19 1999/03/05 14:38:16 achim
223 * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong
224 * -> gdth_eval_mapping() implemented, changes in gdth_bios_param()
225 * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers
226 * with BIOS disabled and memory test set to Intensive
227 * Enhanced /proc support
228 *
229 * Revision 1.18 1999/02/24 09:54:33 achim
230 * Command line parameter hdr_channel implemented
231 * Bugfix for EISA controllers + Linux 2.2.x
232 *
233 * Revision 1.17 1998/12/17 15:58:11 achim
234 * Command line parameters implemented
235 * Changes for Alpha platforms
236 * PCI controller scan changed
237 * SMP support improved (spin_lock_irqsave(),...)
238 * New async. events, new scan/reserve commands included
239 *
240 * Revision 1.16 1998/09/28 16:08:46 achim
241 * GDT_PCIMPR: DPMEM remapping, if required
242 * mdelay() added
243 *
244 * Revision 1.15 1998/06/03 14:54:06 achim
245 * gdth_delay(), gdth_flush() implemented
246 * Bugfix: gdth_release() changed
247 *
248 * Revision 1.14 1998/05/22 10:01:17 achim
249 * mj: pcibios_strerror() removed
250 * Improved SMP support (if version >= 2.1.95)
251 * gdth_halt(): halt_called flag added (if version < 2.1)
252 *
253 * Revision 1.13 1998/04/16 09:14:57 achim
254 * Reserve drives (for raw service) implemented
255 * New error handling code enabled
256 * Get controller name from board_info() IOCTL
257 * Final round of PCI device driver patches by Martin Mares
258 *
259 * Revision 1.12 1998/03/03 09:32:37 achim
260 * Fibre channel controller support added
261 *
262 * Revision 1.11 1998/01/27 16:19:14 achim
263 * SA_SHIRQ added
264 * add_timer()/del_timer() instead of GDTH_TIMER
265 * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER
266 * New error handling included
267 *
268 * Revision 1.10 1997/10/31 12:29:57 achim
269 * Read heads/sectors from host drive
270 *
271 * Revision 1.9 1997/09/04 10:07:25 achim
272 * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ...
273 * register_reboot_notifier() to get a notify on shutown used
274 *
275 * Revision 1.8 1997/04/02 12:14:30 achim
276 * Version 1.00 (see gdth.h), tested with kernel 2.0.29
277 *
278 * Revision 1.7 1997/03/12 13:33:37 achim
279 * gdth_reset() changed, new async. events
280 *
281 * Revision 1.6 1997/03/04 14:01:11 achim
282 * Shutdown routine gdth_halt() implemented
283 *
284 * Revision 1.5 1997/02/21 09:08:36 achim
285 * New controller included (RP, RP1, RP2 series)
286 * IOCTL interface implemented
287 *
288 * Revision 1.4 1996/07/05 12:48:55 achim
289 * Function gdth_bios_param() implemented
290 * New constant GDTH_MAXC_P_L inserted
291 * GDT_WRITE_THR, GDT_EXT_INFO implemented
292 * Function gdth_reset() changed
293 *
294 * Revision 1.3 1996/05/10 09:04:41 achim
295 * Small changes for Linux 1.2.13
296 *
297 * Revision 1.2 1996/05/09 12:45:27 achim
298 * Loadable module support implemented
299 * /proc support corrections made
300 *
301 * Revision 1.1 1996/04/11 07:35:57 achim
302 * Initial revision
303 *
304 ************************************************************************/
305
306/* All GDT Disk Array Controllers are fully supported by this driver.
307 * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
308 * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
309 * list of all controller types.
310 *
311 * If you have one or more GDT3000/3020 EISA controllers with
312 * controller BIOS disabled, you have to set the IRQ values with the
313 * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
314 * the IRQ values for the EISA controllers.
315 *
316 * After the optional list of IRQ values, other possible
317 * command line options are:
318 * disable:Y disable driver
319 * disable:N enable driver
320 * reserve_mode:0 reserve no drives for the raw service
321 * reserve_mode:1 reserve all not init., removable drives
322 * reserve_mode:2 reserve all not init. drives
323 * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
324 * h- controller no., b- channel no.,
325 * t- target ID, l- LUN
326 * reverse_scan:Y reverse scan order for PCI controllers
327 * reverse_scan:N scan PCI controllers like BIOS
328 * max_ids:x x - target ID count per channel (1..MAXID)
329 * rescan:Y rescan all channels/IDs
330 * rescan:N use all devices found until now
331 * virt_ctr:Y map every channel to a virtual controller
332 * virt_ctr:N use multi channel support
333 * hdr_channel:x x - number of virtual bus for host drives
334 * shared_access:Y disable driver reserve/release protocol to
335 * access a shared resource from several nodes,
575c9687 336 * appropriate controller firmware required
1da177e4
LT		 337 * shared_access:N enable driver reserve/release protocol
338 * probe_eisa_isa:Y scan for EISA/ISA controllers
339 * probe_eisa_isa:N do not scan for EISA/ISA controllers
340 * force_dma32:Y use only 32 bit DMA mode
341 * force_dma32:N use 64 bit DMA mode, if supported
342 *
343 * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
344 * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
345 * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
346 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
347 *
348 * When loading the gdth driver as a module, the same options are available.
349 * You can set the IRQs with "IRQ=...". However, the syntax to specify the
350 * options changes slightly. You must replace all ',' between options
351 * with ' ' and all ':' with '=' and you must use
352 * '1' in place of 'Y' and '0' in place of 'N'.
353 *
354 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
355 * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
356 * probe_eisa_isa=0 force_dma32=0"
357 * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
358 */
359
360/* The meaning of the Scsi_Pointer members in this driver is as follows:
361 * ptr: Chaining
362 * this_residual: Command priority
363 * buffer: phys. DMA sense buffer
364 * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
365 * buffers_residual: Timeout value
366 * Status: Command status (gdth_do_cmd()), DMA mem. mappings
367 * Message: Additional info (gdth_do_cmd()), DMA direction
368 * have_data_in: Flag for gdth_wait_completion()
369 * sent_command: Opcode special command
370 * phase: Service/parameter/return code special command
371 */
372
373
374/* interrupt coalescing */
375/* #define INT_COAL */
376
377/* statistics */
378#define GDTH_STATISTICS
379
380#include <linux/module.h>
381
382#include <linux/version.h>
383#include <linux/kernel.h>
384#include <linux/types.h>
385#include <linux/pci.h>
386#include <linux/string.h>
387#include <linux/ctype.h>
388#include <linux/ioport.h>
389#include <linux/delay.h>
1da177e4
LT		 390#include <linux/interrupt.h>
391#include <linux/in.h>
392#include <linux/proc_fs.h>
393#include <linux/time.h>
394#include <linux/timer.h>
cbd5f69b 395#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,6)
910638ae 396#include <linux/dma-mapping.h>
cbd5f69b
LA		 397#else
398#define DMA_32BIT_MASK 0x00000000ffffffffULL
399#define DMA_64BIT_MASK 0xffffffffffffffffULL
400#endif
401
1da177e4
LT		 402#ifdef GDTH_RTC
403#include <linux/mc146818rtc.h>
404#endif
405#include <linux/reboot.h>
406
407#include <asm/dma.h>
408#include <asm/system.h>
409#include <asm/io.h>
410#include <asm/uaccess.h>
411#include <linux/spinlock.h>
412#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
413#include <linux/blkdev.h>
414#else
415#include <linux/blk.h>
416#include "sd.h"
417#endif
418
419#include "scsi.h"
420#include <scsi/scsi_host.h>
1da177e4 421#include "gdth_kcompat.h"
cbd5f69b 422#include "gdth.h"
1da177e4
LT		 423
424static void gdth_delay(int milliseconds);
425static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
7d12e780 426static irqreturn_t gdth_interrupt(int irq, void *dev_id);
1da177e4
LT		 427static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
428static int gdth_async_event(int hanum);
429static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
430
431static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
432static void gdth_next(int hanum);
433static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
434static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
435static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
436 ushort idx, gdth_evt_data *evt);
437static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
438static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
439 gdth_evt_str *estr);
440static void gdth_clear_events(void);
441
442static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
443 char *buffer,ushort count);
444static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
445static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
446
447static int gdth_search_eisa(ushort eisa_adr);
1da177e4
LT		 448static int gdth_search_pci(gdth_pci_str *pcistr);
449static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
450 ushort vendor, ushort dev);
451static void gdth_sort_pci(gdth_pci_str *pcistr, int cnt);
452static int gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha);
1da177e4
LT		 453static int gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha);
454
455static void gdth_enable_int(int hanum);
456static int gdth_get_status(unchar *pIStatus,int irq);
457static int gdth_test_busy(int hanum);
458static int gdth_get_cmd_index(int hanum);
459static void gdth_release_event(int hanum);
460static int gdth_wait(int hanum,int index,ulong32 time);
461static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
462 ulong64 p2,ulong64 p3);
463static int gdth_search_drives(int hanum);
464static int gdth_analyse_hdrive(int hanum, ushort hdrive);
465
466static const char *gdth_ctr_name(int hanum);
467
468static int gdth_open(struct inode *inode, struct file *filep);
469static int gdth_close(struct inode *inode, struct file *filep);
470static int gdth_ioctl(struct inode *inode, struct file *filep,
471 unsigned int cmd, unsigned long arg);
472
473static void gdth_flush(int hanum);
474static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
cbd5f69b
LA		 475static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
476static void gdth_scsi_done(struct scsi_cmnd *scp);
aed91cb5
CH		 477#ifdef CONFIG_ISA
478static int gdth_isa_probe_one(struct scsi_host_template *, ulong32);
479#endif
1da177e4
LT		 480
481#ifdef DEBUG_GDTH
482static unchar DebugState = DEBUG_GDTH;
483
484#ifdef __SERIAL__
485#define MAX_SERBUF 160
486static void ser_init(void);
487static void ser_puts(char *str);
488static void ser_putc(char c);
489static int ser_printk(const char *fmt, ...);
490static char strbuf[MAX_SERBUF+1];
491#ifdef __COM2__
492#define COM_BASE 0x2f8
493#else
494#define COM_BASE 0x3f8
495#endif
496static void ser_init()
497{
498 unsigned port=COM_BASE;
499
500 outb(0x80,port+3);
501 outb(0,port+1);
502 /* 19200 Baud, if 9600: outb(12,port) */
503 outb(6, port);
504 outb(3,port+3);
505 outb(0,port+1);
506 /*
507 ser_putc('I');
508 ser_putc(' ');
509 */
510}
511
512static void ser_puts(char *str)
513{
514 char *ptr;
515
516 ser_init();
517 for (ptr=str;*ptr;++ptr)
518 ser_putc(*ptr);
519}
520
521static void ser_putc(char c)
522{
523 unsigned port=COM_BASE;
524
525 while ((inb(port+5) & 0x20)==0);
526 outb(c,port);
527 if (c==0x0a)
528 {
529 while ((inb(port+5) & 0x20)==0);
530 outb(0x0d,port);
531 }
532}
533
534static int ser_printk(const char *fmt, ...)
535{
536 va_list args;
537 int i;
538
539 va_start(args,fmt);
540 i = vsprintf(strbuf,fmt,args);
541 ser_puts(strbuf);
542 va_end(args);
543 return i;
544}
545
546#define TRACE(a) {if (DebugState==1) {ser_printk a;}}
547#define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
548#define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
549
550#else /* !__SERIAL__ */
551#define TRACE(a) {if (DebugState==1) {printk a;}}
552#define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
553#define TRACE3(a) {if (DebugState!=0) {printk a;}}
554#endif
555
556#else /* !DEBUG */
557#define TRACE(a)
558#define TRACE2(a)
559#define TRACE3(a)
560#endif
561
562#ifdef GDTH_STATISTICS
563static ulong32 max_rq=0, max_index=0, max_sg=0;
564#ifdef INT_COAL
565static ulong32 max_int_coal=0;
566#endif
567static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
568static struct timer_list gdth_timer;
569#endif
570
571#define PTR2USHORT(a) (ushort)(ulong)(a)
6391a113
TK		 572#define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
573#define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
1da177e4
LT		 574
575#define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
576#define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
577#define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
578
579#define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
580
581#define gdth_readb(addr) readb(addr)
582#define gdth_readw(addr) readw(addr)
583#define gdth_readl(addr) readl(addr)
584#define gdth_writeb(b,addr) writeb((b),(addr))
585#define gdth_writew(b,addr) writew((b),(addr))
586#define gdth_writel(b,addr) writel((b),(addr))
587
aed91cb5 588#ifdef CONFIG_ISA
1da177e4 589static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
aed91cb5
CH		 590#endif
591
1da177e4
LT		 592static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
593static unchar gdth_polling; /* polling if TRUE */
594static unchar gdth_from_wait = FALSE; /* gdth_wait() */
595static int wait_index,wait_hanum; /* gdth_wait() */
596static int gdth_ctr_count = 0; /* controller count */
597static int gdth_ctr_vcount = 0; /* virt. ctr. count */
598static int gdth_ctr_released = 0; /* gdth_release() */
599static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
600static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
601static unchar gdth_write_through = FALSE; /* write through */
602static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
603static int elastidx;
604static int eoldidx;
605static int major;
606
607#define DIN 1 /* IN data direction */
608#define DOU 2 /* OUT data direction */
609#define DNO DIN /* no data transfer */
610#define DUN DIN /* unknown data direction */
611static unchar gdth_direction_tab[0x100] = {
612 DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
613 DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
614 DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
615 DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
616 DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
617 DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
618 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
619 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
620 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
621 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
622 DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
623 DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
624 DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
625 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
626 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
627 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
628};
629
630/* LILO and modprobe/insmod parameters */
631/* IRQ list for GDT3000/3020 EISA controllers */
632static int irq[MAXHA] __initdata =
633{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
634 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
635/* disable driver flag */
636static int disable __initdata = 0;
637/* reserve flag */
638static int reserve_mode = 1;
639/* reserve list */
640static int reserve_list[MAX_RES_ARGS] =
641{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
642 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
643 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
644/* scan order for PCI controllers */
645static int reverse_scan = 0;
646/* virtual channel for the host drives */
647static int hdr_channel = 0;
648/* max. IDs per channel */
649static int max_ids = MAXID;
650/* rescan all IDs */
651static int rescan = 0;
652/* map channels to virtual controllers */
653static int virt_ctr = 0;
654/* shared access */
655static int shared_access = 1;
656/* enable support for EISA and ISA controllers */
657static int probe_eisa_isa = 0;
658/* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
659static int force_dma32 = 0;
660
661/* parameters for modprobe/insmod */
cbd5f69b 662#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
1da177e4
LT		 663module_param_array(irq, int, NULL, 0);
664module_param(disable, int, 0);
665module_param(reserve_mode, int, 0);
666module_param_array(reserve_list, int, NULL, 0);
667module_param(reverse_scan, int, 0);
668module_param(hdr_channel, int, 0);
669module_param(max_ids, int, 0);
670module_param(rescan, int, 0);
671module_param(virt_ctr, int, 0);
672module_param(shared_access, int, 0);
673module_param(probe_eisa_isa, int, 0);
674module_param(force_dma32, int, 0);
cbd5f69b
LA		 675#else
676MODULE_PARM(irq, "i");
677MODULE_PARM(disable, "i");
678MODULE_PARM(reserve_mode, "i");
679MODULE_PARM(reserve_list, "4-" __MODULE_STRING(MAX_RES_ARGS) "i");
680MODULE_PARM(reverse_scan, "i");
681MODULE_PARM(hdr_channel, "i");
682MODULE_PARM(max_ids, "i");
683MODULE_PARM(rescan, "i");
684MODULE_PARM(virt_ctr, "i");
685MODULE_PARM(shared_access, "i");
686MODULE_PARM(probe_eisa_isa, "i");
687MODULE_PARM(force_dma32, "i");
688#endif
1da177e4
LT		 689MODULE_AUTHOR("Achim Leubner");
690MODULE_LICENSE("GPL");
691
692/* ioctl interface */
00977a59 693static const struct file_operations gdth_fops = {
1da177e4
LT		 694 .ioctl = gdth_ioctl,
695 .open = gdth_open,
696 .release = gdth_close,
697};
698
687d2bc4
MW		 699#define GDTH_MAGIC 0xc2e7c389 /* I got it from /dev/urandom */
700#define IS_GDTH_INTERNAL_CMD(scp) (scp->underflow == GDTH_MAGIC)
701
1da177e4
LT		 702#include "gdth_proc.h"
703#include "gdth_proc.c"
704
705/* notifier block to get a notify on system shutdown/halt/reboot */
706static struct notifier_block gdth_notifier = {
707 gdth_halt, NULL, 0
708};
e041c683 709static int notifier_disabled = 0;
1da177e4
LT		 710
711static void gdth_delay(int milliseconds)
712{
713 if (milliseconds == 0) {
714 udelay(1);
715 } else {
716 mdelay(milliseconds);
717 }
718}
719
cbd5f69b
LA		 720#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
721static void gdth_scsi_done(struct scsi_cmnd *scp)
722{
b8bff2ae 723 TRACE2(("gdth_scsi_done()\n"));
cbd5f69b 724
b8bff2ae
MW		 725 if (IS_GDTH_INTERNAL_CMD(scp))
726 complete((struct completion *)scp->request);
727 else
728 scp->scsi_done(scp);
cbd5f69b
LA		 729}
730
731int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
732 int timeout, u32 *info)
733{
734 Scsi_Cmnd *scp;
6e9a4738 735 DECLARE_COMPLETION_ONSTACK(wait);
cbd5f69b
LA		 736 int rval;
737
bbfbbbc1 738 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
cbd5f69b
LA		 739 if (!scp)
740 return -ENOMEM;
bbfbbbc1 741
cbd5f69b 742 scp->device = sdev;
beb40487
CH		 743 /* use request field to save the ptr. to completion struct. */
744 scp->request = (struct request *)&wait;
cbd5f69b
LA		 745 scp->timeout_per_command = timeout*HZ;
746 scp->request_buffer = gdtcmd;
747 scp->cmd_len = 12;
748 memcpy(scp->cmnd, cmnd, 12);
749 scp->SCp.this_residual = IOCTL_PRI; /* priority */
687d2bc4 750 scp->underflow = GDTH_MAGIC;
b8bff2ae 751 gdth_queuecommand(scp, NULL);
cbd5f69b
LA		 752 wait_for_completion(&wait);
753
754 rval = scp->SCp.Status;
755 if (info)
756 *info = scp->SCp.Message;
757 kfree(scp);
758 return rval;
759}
760#else
761static void gdth_scsi_done(Scsi_Cmnd *scp)
762{
763 TRACE2(("gdth_scsi_done()\n"));
764
765 scp->request.rq_status = RQ_SCSI_DONE;
766 if (scp->request.waiting)
767 complete(scp->request.waiting);
768}
769
770int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
771 int timeout, u32 *info)
772{
773 Scsi_Cmnd *scp = scsi_allocate_device(sdev, 1, FALSE);
774 unsigned bufflen = gdtcmd ? sizeof(gdth_cmd_str) : 0;
6e9a4738 775 DECLARE_COMPLETION_ONSTACK(wait);
cbd5f69b
LA		 776 int rval;
777
778 if (!scp)
779 return -ENOMEM;
780 scp->cmd_len = 12;
781 scp->use_sg = 0;
782 scp->SCp.this_residual = IOCTL_PRI; /* priority */
783 scp->request.rq_status = RQ_SCSI_BUSY;
784 scp->request.waiting = &wait;
785 scsi_do_cmd(scp, cmnd, gdtcmd, bufflen, gdth_scsi_done, timeout*HZ, 1);
786 wait_for_completion(&wait);
787
788 rval = scp->SCp.Status;
789 if (info)
790 *info = scp->SCp.Message;
791
792 scsi_release_command(scp);
793 return rval;
794}
795#endif
796
797int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
798 int timeout, u32 *info)
799{
800 struct scsi_device *sdev = scsi_get_host_dev(shost);
801 int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
802
803 scsi_free_host_dev(sdev);
804 return rval;
805}
806
1da177e4
LT		 807static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
808{
809 *cyls = size /HEADS/SECS;
810 if (*cyls <= MAXCYLS) {
811 *heads = HEADS;
812 *secs = SECS;
813 } else { /* too high for 64*32 */
814 *cyls = size /MEDHEADS/MEDSECS;
815 if (*cyls <= MAXCYLS) {
816 *heads = MEDHEADS;
817 *secs = MEDSECS;
818 } else { /* too high for 127*63 */
819 *cyls = size /BIGHEADS/BIGSECS;
820 *heads = BIGHEADS;
821 *secs = BIGSECS;
822 }
823 }
824}
825
826/* controller search and initialization functions */
827
828static int __init gdth_search_eisa(ushort eisa_adr)
829{
830 ulong32 id;
831
832 TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
833 id = inl(eisa_adr+ID0REG);
834 if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
835 if ((inb(eisa_adr+EISAREG) & 8) == 0)
836 return 0; /* not EISA configured */
837 return 1;
838 }
839 if (id == GDT3_ID) /* GDT3000 */
840 return 1;
841
842 return 0;
843}
844
aed91cb5 845#ifdef CONFIG_ISA
1da177e4
LT		 846static int __init gdth_search_isa(ulong32 bios_adr)
847{
848 void __iomem *addr;
849 ulong32 id;
850
851 TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
852 if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
853 id = gdth_readl(addr);
854 iounmap(addr);
855 if (id == GDT2_ID) /* GDT2000 */
856 return 1;
857 }
858 return 0;
859}
aed91cb5 860#endif /* CONFIG_ISA */
1da177e4
LT		 861
862static int __init gdth_search_pci(gdth_pci_str *pcistr)
863{
864 ushort device, cnt;
865
866 TRACE(("gdth_search_pci()\n"));
867
868 cnt = 0;
869 for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
870 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
871 for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
872 device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
873 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
874 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
875 PCI_DEVICE_ID_VORTEX_GDTNEWRX);
876 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
877 PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
878 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
879 PCI_DEVICE_ID_INTEL_SRC);
880 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
881 PCI_DEVICE_ID_INTEL_SRC_XSCALE);
882 return cnt;
883}
884
885/* Vortex only makes RAID controllers.
886 * We do not really want to specify all 550 ids here, so wildcard match.
887 */
6c4b7e4f 888static struct pci_device_id gdthtable[] __maybe_unused = {
1da177e4
LT		 889 {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
890 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
891 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
892 {0}
893};
894MODULE_DEVICE_TABLE(pci,gdthtable);
895
896static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
cbd5f69b 897 ushort vendor, ushort device)
1da177e4
LT		 898{
899 ulong base0, base1, base2;
900 struct pci_dev *pdev;
901
902 TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
903 *cnt, vendor, device));
904
905 pdev = NULL;
906 while ((pdev = pci_find_device(vendor, device, pdev))
907 != NULL) {
908 if (pci_enable_device(pdev))
909 continue;
910 if (*cnt >= MAXHA)
911 return;
912 /* GDT PCI controller found, resources are already in pdev */
913 pcistr[*cnt].pdev = pdev;
1da177e4
LT		 914 pcistr[*cnt].irq = pdev->irq;
915 base0 = pci_resource_flags(pdev, 0);
916 base1 = pci_resource_flags(pdev, 1);
917 base2 = pci_resource_flags(pdev, 2);
918 if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
919 device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
920 if (!(base0 & IORESOURCE_MEM))
921 continue;
922 pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
923 } else { /* GDT6110, GDT6120, .. */
924 if (!(base0 & IORESOURCE_MEM) ||
925 !(base2 & IORESOURCE_MEM) ||
926 !(base1 & IORESOURCE_IO))
927 continue;
928 pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
929 pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
930 pcistr[*cnt].io = pci_resource_start(pdev, 1);
931 }
932 TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
8e9a8a0d
JG		 933 pcistr[*cnt].pdev->bus->number,
934 PCI_SLOT(pcistr[*cnt].pdev->devfn),
1da177e4
LT		 935 pcistr[*cnt].irq, pcistr[*cnt].dpmem));
936 (*cnt)++;
937 }
938}
939
940
941static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
942{
943 gdth_pci_str temp;
944 int i, changed;
945
946 TRACE(("gdth_sort_pci() cnt %d\n",cnt));
947 if (cnt == 0)
948 return;
949
950 do {
951 changed = FALSE;
952 for (i = 0; i < cnt-1; ++i) {
953 if (!reverse_scan) {
8e9a8a0d
JG		 954 if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
955 (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
956 PCI_SLOT(pcistr[i].pdev->devfn) >
957 PCI_SLOT(pcistr[i+1].pdev->devfn))) {
1da177e4
LT		 958 temp = pcistr[i];
959 pcistr[i] = pcistr[i+1];
960 pcistr[i+1] = temp;
961 changed = TRUE;
962 }
963 } else {
8e9a8a0d
JG		 964 if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
965 (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
966 PCI_SLOT(pcistr[i].pdev->devfn) <
967 PCI_SLOT(pcistr[i+1].pdev->devfn))) {
1da177e4
LT		 968 temp = pcistr[i];
969 pcistr[i] = pcistr[i+1];
970 pcistr[i+1] = temp;
971 changed = TRUE;
972 }
973 }
974 }
975 } while (changed);
976}
977
978
979static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
980{
981 ulong32 retries,id;
982 unchar prot_ver,eisacf,i,irq_found;
983
984 TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
985
986 /* disable board interrupts, deinitialize services */
987 outb(0xff,eisa_adr+EDOORREG);
988 outb(0x00,eisa_adr+EDENABREG);
989 outb(0x00,eisa_adr+EINTENABREG);
990
991 outb(0xff,eisa_adr+LDOORREG);
992 retries = INIT_RETRIES;
993 gdth_delay(20);
994 while (inb(eisa_adr+EDOORREG) != 0xff) {
995 if (--retries == 0) {
996 printk("GDT-EISA: Initialization error (DEINIT failed)\n");
997 return 0;
998 }
999 gdth_delay(1);
1000 TRACE2(("wait for DEINIT: retries=%d\n",retries));
1001 }
1002 prot_ver = inb(eisa_adr+MAILBOXREG);
1003 outb(0xff,eisa_adr+EDOORREG);
1004 if (prot_ver != PROTOCOL_VERSION) {
1005 printk("GDT-EISA: Illegal protocol version\n");
1006 return 0;
1007 }
1008 ha->bmic = eisa_adr;
1009 ha->brd_phys = (ulong32)eisa_adr >> 12;
1010
1011 outl(0,eisa_adr+MAILBOXREG);
1012 outl(0,eisa_adr+MAILBOXREG+4);
1013 outl(0,eisa_adr+MAILBOXREG+8);
1014 outl(0,eisa_adr+MAILBOXREG+12);
1015
1016 /* detect IRQ */
1017 if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
1018 ha->oem_id = OEM_ID_ICP;
1019 ha->type = GDT_EISA;
1020 ha->stype = id;
1021 outl(1,eisa_adr+MAILBOXREG+8);
1022 outb(0xfe,eisa_adr+LDOORREG);
1023 retries = INIT_RETRIES;
1024 gdth_delay(20);
1025 while (inb(eisa_adr+EDOORREG) != 0xfe) {
1026 if (--retries == 0) {
1027 printk("GDT-EISA: Initialization error (get IRQ failed)\n");
1028 return 0;
1029 }
1030 gdth_delay(1);
1031 }
1032 ha->irq = inb(eisa_adr+MAILBOXREG);
1033 outb(0xff,eisa_adr+EDOORREG);
1034 TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
1035 /* check the result */
1036 if (ha->irq == 0) {
1037 TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
1038 for (i = 0, irq_found = FALSE;
1039 i < MAXHA && irq[i] != 0xff; ++i) {
1040 if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
1041 irq_found = TRUE;
1042 break;
1043 }
1044 }
1045 if (irq_found) {
1046 ha->irq = irq[i];
1047 irq[i] = 0;
1048 printk("GDT-EISA: Can not detect controller IRQ,\n");
1049 printk("Use IRQ setting from command line (IRQ = %d)\n",
1050 ha->irq);
1051 } else {
1052 printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
1053 printk("the controller BIOS or use command line parameters\n");
1054 return 0;
1055 }
1056 }
1057 } else {
1058 eisacf = inb(eisa_adr+EISAREG) & 7;
1059 if (eisacf > 4) /* level triggered */
1060 eisacf -= 4;
1061 ha->irq = gdth_irq_tab[eisacf];
1062 ha->oem_id = OEM_ID_ICP;
1063 ha->type = GDT_EISA;
1064 ha->stype = id;
1065 }
1066
1067 ha->dma64_support = 0;
1068 return 1;
1069}
1070
aed91cb5 1071#ifdef CONFIG_ISA
1da177e4
LT		 1072static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
1073{
1074 register gdt2_dpram_str __iomem *dp2_ptr;
1075 int i;
1076 unchar irq_drq,prot_ver;
1077 ulong32 retries;
1078
1079 TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
1080
1081 ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
1082 if (ha->brd == NULL) {
1083 printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
1084 return 0;
1085 }
1086 dp2_ptr = ha->brd;
1087 gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
1088 /* reset interface area */
1089 memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
1090 if (gdth_readl(&dp2_ptr->u) != 0) {
1091 printk("GDT-ISA: Initialization error (DPMEM write error)\n");
1092 iounmap(ha->brd);
1093 return 0;
1094 }
1095
1096 /* disable board interrupts, read DRQ and IRQ */
1097 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1098 gdth_writeb(0x00, &dp2_ptr->io.irqen);
1099 gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
1100 gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
1101
1102 irq_drq = gdth_readb(&dp2_ptr->io.rq);
1103 for (i=0; i<3; ++i) {
1104 if ((irq_drq & 1)==0)
1105 break;
1106 irq_drq >>= 1;
1107 }
1108 ha->drq = gdth_drq_tab[i];
1109
1110 irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
1111 for (i=1; i<5; ++i) {
1112 if ((irq_drq & 1)==0)
1113 break;
1114 irq_drq >>= 1;
1115 }
1116 ha->irq = gdth_irq_tab[i];
1117
1118 /* deinitialize services */
1119 gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
1120 gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
1121 gdth_writeb(0, &dp2_ptr->io.event);
1122 retries = INIT_RETRIES;
1123 gdth_delay(20);
1124 while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
1125 if (--retries == 0) {
1126 printk("GDT-ISA: Initialization error (DEINIT failed)\n");
1127 iounmap(ha->brd);
1128 return 0;
1129 }
1130 gdth_delay(1);
1131 }
1132 prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
1133 gdth_writeb(0, &dp2_ptr->u.ic.Status);
1134 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1135 if (prot_ver != PROTOCOL_VERSION) {
1136 printk("GDT-ISA: Illegal protocol version\n");
1137 iounmap(ha->brd);
1138 return 0;
1139 }
1140
1141 ha->oem_id = OEM_ID_ICP;
1142 ha->type = GDT_ISA;
1143 ha->ic_all_size = sizeof(dp2_ptr->u);
1144 ha->stype= GDT2_ID;
1145 ha->brd_phys = bios_adr >> 4;
1146
1147 /* special request to controller BIOS */
1148 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
1149 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
1150 gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
1151 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
1152 gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
1153 gdth_writeb(0, &dp2_ptr->io.event);
1154 retries = INIT_RETRIES;
1155 gdth_delay(20);
1156 while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
1157 if (--retries == 0) {
1158 printk("GDT-ISA: Initialization error\n");
1159 iounmap(ha->brd);
1160 return 0;
1161 }
1162 gdth_delay(1);
1163 }
1164 gdth_writeb(0, &dp2_ptr->u.ic.Status);
1165 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1166
1167 ha->dma64_support = 0;
1168 return 1;
1169}
aed91cb5 1170#endif /* CONFIG_ISA */
1da177e4
LT		 1171
1172static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
1173{
1174 register gdt6_dpram_str __iomem *dp6_ptr;
1175 register gdt6c_dpram_str __iomem *dp6c_ptr;
1176 register gdt6m_dpram_str __iomem *dp6m_ptr;
1177 ulong32 retries;
1178 unchar prot_ver;
1179 ushort command;
1180 int i, found = FALSE;
1181
1182 TRACE(("gdth_init_pci()\n"));
1183
8e9a8a0d 1184 if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
1da177e4
LT		 1185 ha->oem_id = OEM_ID_INTEL;
1186 else
1187 ha->oem_id = OEM_ID_ICP;
8e9a8a0d
JG		 1188 ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
1189 ha->stype = (ulong32)pcistr->pdev->device;
1da177e4
LT		 1190 ha->irq = pcistr->irq;
1191 ha->pdev = pcistr->pdev;
1192
8e9a8a0d 1193 if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
1da177e4
LT		 1194 TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1195 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
1196 if (ha->brd == NULL) {
1197 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1198 return 0;
1199 }
1200 /* check and reset interface area */
1201 dp6_ptr = ha->brd;
1202 gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
1203 if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
1204 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1205 pcistr->dpmem);
1206 found = FALSE;
1207 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1208 iounmap(ha->brd);
1209 ha->brd = ioremap(i, sizeof(ushort));
1210 if (ha->brd == NULL) {
1211 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1212 return 0;
1213 }
1214 if (gdth_readw(ha->brd) != 0xffff) {
1215 TRACE2(("init_pci_old() address 0x%x busy\n", i));
1216 continue;
1217 }
1218 iounmap(ha->brd);
1219 pci_write_config_dword(pcistr->pdev,
1220 PCI_BASE_ADDRESS_0, i);
1221 ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
1222 if (ha->brd == NULL) {
1223 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1224 return 0;
1225 }
1226 dp6_ptr = ha->brd;
1227 gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
1228 if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
1229 printk("GDT-PCI: Use free address at 0x%x\n", i);
1230 found = TRUE;
1231 break;
1232 }
1233 }
1234 if (!found) {
1235 printk("GDT-PCI: No free address found!\n");
1236 iounmap(ha->brd);
1237 return 0;
1238 }
1239 }
1240 memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
1241 if (gdth_readl(&dp6_ptr->u) != 0) {
1242 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1243 iounmap(ha->brd);
1244 return 0;
1245 }
1246
1247 /* disable board interrupts, deinit services */
1248 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1249 gdth_writeb(0x00, &dp6_ptr->io.irqen);
1250 gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
1251 gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
1252
1253 gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
1254 gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
1255 gdth_writeb(0, &dp6_ptr->io.event);
1256 retries = INIT_RETRIES;
1257 gdth_delay(20);
1258 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
1259 if (--retries == 0) {
1260 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1261 iounmap(ha->brd);
1262 return 0;
1263 }
1264 gdth_delay(1);
1265 }
1266 prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
1267 gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
1268 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1269 if (prot_ver != PROTOCOL_VERSION) {
1270 printk("GDT-PCI: Illegal protocol version\n");
1271 iounmap(ha->brd);
1272 return 0;
1273 }
1274
1275 ha->type = GDT_PCI;
1276 ha->ic_all_size = sizeof(dp6_ptr->u);
1277
1278 /* special command to controller BIOS */
1279 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
1280 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
1281 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
1282 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
1283 gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
1284 gdth_writeb(0, &dp6_ptr->io.event);
1285 retries = INIT_RETRIES;
1286 gdth_delay(20);
1287 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
1288 if (--retries == 0) {
1289 printk("GDT-PCI: Initialization error\n");
1290 iounmap(ha->brd);
1291 return 0;
1292 }
1293 gdth_delay(1);
1294 }
1295 gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
1296 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1297
1298 ha->dma64_support = 0;
1299
8e9a8a0d 1300 } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
1da177e4
LT		 1301 ha->plx = (gdt6c_plx_regs *)pcistr->io;
1302 TRACE2(("init_pci_new() dpmem %lx irq %d\n",
1303 pcistr->dpmem,ha->irq));
1304 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
1305 if (ha->brd == NULL) {
1306 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1307 iounmap(ha->brd);
1308 return 0;
1309 }
1310 /* check and reset interface area */
1311 dp6c_ptr = ha->brd;
1312 gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
1313 if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
1314 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1315 pcistr->dpmem);
1316 found = FALSE;
1317 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1318 iounmap(ha->brd);
1319 ha->brd = ioremap(i, sizeof(ushort));
1320 if (ha->brd == NULL) {
1321 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1322 return 0;
1323 }
1324 if (gdth_readw(ha->brd) != 0xffff) {
1325 TRACE2(("init_pci_plx() address 0x%x busy\n", i));
1326 continue;
1327 }
1328 iounmap(ha->brd);
1329 pci_write_config_dword(pcistr->pdev,
1330 PCI_BASE_ADDRESS_2, i);
1331 ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
1332 if (ha->brd == NULL) {
1333 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1334 return 0;
1335 }
1336 dp6c_ptr = ha->brd;
1337 gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
1338 if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
1339 printk("GDT-PCI: Use free address at 0x%x\n", i);
1340 found = TRUE;
1341 break;
1342 }
1343 }
1344 if (!found) {
1345 printk("GDT-PCI: No free address found!\n");
1346 iounmap(ha->brd);
1347 return 0;
1348 }
1349 }
1350 memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
1351 if (gdth_readl(&dp6c_ptr->u) != 0) {
1352 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1353 iounmap(ha->brd);
1354 return 0;
1355 }
1356
1357 /* disable board interrupts, deinit services */
1358 outb(0x00,PTR2USHORT(&ha->plx->control1));
1359 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
1360
1361 gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
1362 gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
1363
1364 gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
1365 gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
1366
1367 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1368
1369 retries = INIT_RETRIES;
1370 gdth_delay(20);
1371 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
1372 if (--retries == 0) {
1373 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1374 iounmap(ha->brd);
1375 return 0;
1376 }
1377 gdth_delay(1);
1378 }
1379 prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
1380 gdth_writeb(0, &dp6c_ptr->u.ic.Status);
1381 if (prot_ver != PROTOCOL_VERSION) {
1382 printk("GDT-PCI: Illegal protocol version\n");
1383 iounmap(ha->brd);
1384 return 0;
1385 }
1386
1387 ha->type = GDT_PCINEW;
1388 ha->ic_all_size = sizeof(dp6c_ptr->u);
1389
1390 /* special command to controller BIOS */
1391 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
1392 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
1393 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
1394 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
1395 gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
1396
1397 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1398
1399 retries = INIT_RETRIES;
1400 gdth_delay(20);
1401 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
1402 if (--retries == 0) {
1403 printk("GDT-PCI: Initialization error\n");
1404 iounmap(ha->brd);
1405 return 0;
1406 }
1407 gdth_delay(1);
1408 }
1409 gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
1410
1411 ha->dma64_support = 0;
1412
1413 } else { /* MPR */
1414 TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1415 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
1416 if (ha->brd == NULL) {
1417 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1418 return 0;
1419 }
1420
1421 /* manipulate config. space to enable DPMEM, start RP controller */
1422 pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
1423 command |= 6;
1424 pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
1425 if (pci_resource_start(pcistr->pdev, 8) == 1UL)
1426 pci_resource_start(pcistr->pdev, 8) = 0UL;
1427 i = 0xFEFF0001UL;
1428 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
1429 gdth_delay(1);
1430 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
1431 pci_resource_start(pcistr->pdev, 8));
1432
1433 dp6m_ptr = ha->brd;
1434
1435 /* Ensure that it is safe to access the non HW portions of DPMEM.
1436 * Aditional check needed for Xscale based RAID controllers */
1437 while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
1438 gdth_delay(1);
1439
1440 /* check and reset interface area */
1441 gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
1442 if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
1443 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1444 pcistr->dpmem);
1445 found = FALSE;
1446 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1447 iounmap(ha->brd);
1448 ha->brd = ioremap(i, sizeof(ushort));
1449 if (ha->brd == NULL) {
1450 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1451 return 0;
1452 }
1453 if (gdth_readw(ha->brd) != 0xffff) {
1454 TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
1455 continue;
1456 }
1457 iounmap(ha->brd);
1458 pci_write_config_dword(pcistr->pdev,
1459 PCI_BASE_ADDRESS_0, i);
1460 ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
1461 if (ha->brd == NULL) {
1462 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1463 return 0;
1464 }
1465 dp6m_ptr = ha->brd;
1466 gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
1467 if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
1468 printk("GDT-PCI: Use free address at 0x%x\n", i);
1469 found = TRUE;
1470 break;
1471 }
1472 }
1473 if (!found) {
1474 printk("GDT-PCI: No free address found!\n");
1475 iounmap(ha->brd);
1476 return 0;
1477 }
1478 }
1479 memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
1480
1481 /* disable board interrupts, deinit services */
1482 gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
1483 &dp6m_ptr->i960r.edoor_en_reg);
1484 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1485 gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
1486 gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
1487
1488 gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
1489 gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
1490 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1491 retries = INIT_RETRIES;
1492 gdth_delay(20);
1493 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
1494 if (--retries == 0) {
1495 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1496 iounmap(ha->brd);
1497 return 0;
1498 }
1499 gdth_delay(1);
1500 }
1501 prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
1502 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1503 if (prot_ver != PROTOCOL_VERSION) {
1504 printk("GDT-PCI: Illegal protocol version\n");
1505 iounmap(ha->brd);
1506 return 0;
1507 }
1508
1509 ha->type = GDT_PCIMPR;
1510 ha->ic_all_size = sizeof(dp6m_ptr->u);
1511
1512 /* special command to controller BIOS */
1513 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
1514 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
1515 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
1516 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
1517 gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
1518 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1519 retries = INIT_RETRIES;
1520 gdth_delay(20);
1521 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
1522 if (--retries == 0) {
1523 printk("GDT-PCI: Initialization error\n");
1524 iounmap(ha->brd);
1525 return 0;
1526 }
1527 gdth_delay(1);
1528 }
1529 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1530
1531 /* read FW version to detect 64-bit DMA support */
1532 gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
1533 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1534 retries = INIT_RETRIES;
1535 gdth_delay(20);
1536 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
1537 if (--retries == 0) {
1538 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1539 iounmap(ha->brd);
1540 return 0;
1541 }
1542 gdth_delay(1);
1543 }
1544 prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
1545 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1546 if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
1547 ha->dma64_support = 0;
1548 else
1549 ha->dma64_support = 1;
1550 }
1551
1552 return 1;
1553}
1554
1555
1556/* controller protocol functions */
1557
1558static void __init gdth_enable_int(int hanum)
1559{
1560 gdth_ha_str *ha;
1561 ulong flags;
1562 gdt2_dpram_str __iomem *dp2_ptr;
1563 gdt6_dpram_str __iomem *dp6_ptr;
1564 gdt6m_dpram_str __iomem *dp6m_ptr;
1565
1566 TRACE(("gdth_enable_int() hanum %d\n",hanum));
1567 ha = HADATA(gdth_ctr_tab[hanum]);
1568 spin_lock_irqsave(&ha->smp_lock, flags);
1569
1570 if (ha->type == GDT_EISA) {
1571 outb(0xff, ha->bmic + EDOORREG);
1572 outb(0xff, ha->bmic + EDENABREG);
1573 outb(0x01, ha->bmic + EINTENABREG);
1574 } else if (ha->type == GDT_ISA) {
1575 dp2_ptr = ha->brd;
1576 gdth_writeb(1, &dp2_ptr->io.irqdel);
1577 gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
1578 gdth_writeb(1, &dp2_ptr->io.irqen);
1579 } else if (ha->type == GDT_PCI) {
1580 dp6_ptr = ha->brd;
1581 gdth_writeb(1, &dp6_ptr->io.irqdel);
1582 gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
1583 gdth_writeb(1, &dp6_ptr->io.irqen);
1584 } else if (ha->type == GDT_PCINEW) {
1585 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
1586 outb(0x03, PTR2USHORT(&ha->plx->control1));
1587 } else if (ha->type == GDT_PCIMPR) {
1588 dp6m_ptr = ha->brd;
1589 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1590 gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
1591 &dp6m_ptr->i960r.edoor_en_reg);
1592 }
1593 spin_unlock_irqrestore(&ha->smp_lock, flags);
1594}
1595
1596
1597static int gdth_get_status(unchar *pIStatus,int irq)
1598{
1599 register gdth_ha_str *ha;
1600 int i;
1601
1602 TRACE(("gdth_get_status() irq %d ctr_count %d\n",
1603 irq,gdth_ctr_count));
1604
1605 *pIStatus = 0;
1606 for (i=0; i<gdth_ctr_count; ++i) {
1607 ha = HADATA(gdth_ctr_tab[i]);
1608 if (ha->irq != (unchar)irq) /* check IRQ */
1609 continue;
1610 if (ha->type == GDT_EISA)
1611 *pIStatus = inb((ushort)ha->bmic + EDOORREG);
1612 else if (ha->type == GDT_ISA)
1613 *pIStatus =
1614 gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1615 else if (ha->type == GDT_PCI)
1616 *pIStatus =
1617 gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1618 else if (ha->type == GDT_PCINEW)
1619 *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
1620 else if (ha->type == GDT_PCIMPR)
1621 *pIStatus =
1622 gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
1623
1624 if (*pIStatus)
1625 return i; /* board found */
1626 }
1627 return -1;
1628}
1629
1630
1631static int gdth_test_busy(int hanum)
1632{
1633 register gdth_ha_str *ha;
1634 register int gdtsema0 = 0;
1635
1636 TRACE(("gdth_test_busy() hanum %d\n",hanum));
1637
1638 ha = HADATA(gdth_ctr_tab[hanum]);
1639 if (ha->type == GDT_EISA)
1640 gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
1641 else if (ha->type == GDT_ISA)
1642 gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1643 else if (ha->type == GDT_PCI)
1644 gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1645 else if (ha->type == GDT_PCINEW)
1646 gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
1647 else if (ha->type == GDT_PCIMPR)
1648 gdtsema0 =
1649 (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1650
1651 return (gdtsema0 & 1);
1652}
1653
1654
1655static int gdth_get_cmd_index(int hanum)
1656{
1657 register gdth_ha_str *ha;
1658 int i;
1659
1660 TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
1661
1662 ha = HADATA(gdth_ctr_tab[hanum]);
1663 for (i=0; i<GDTH_MAXCMDS; ++i) {
1664 if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
1665 ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
1666 ha->cmd_tab[i].service = ha->pccb->Service;
1667 ha->pccb->CommandIndex = (ulong32)i+2;
1668 return (i+2);
1669 }
1670 }
1671 return 0;
1672}
1673
1674
1675static void gdth_set_sema0(int hanum)
1676{
1677 register gdth_ha_str *ha;
1678
1679 TRACE(("gdth_set_sema0() hanum %d\n",hanum));
1680
1681 ha = HADATA(gdth_ctr_tab[hanum]);
1682 if (ha->type == GDT_EISA) {
1683 outb(1, ha->bmic + SEMA0REG);
1684 } else if (ha->type == GDT_ISA) {
1685 gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1686 } else if (ha->type == GDT_PCI) {
1687 gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1688 } else if (ha->type == GDT_PCINEW) {
1689 outb(1, PTR2USHORT(&ha->plx->sema0_reg));
1690 } else if (ha->type == GDT_PCIMPR) {
1691 gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1692 }
1693}
1694
1695
1696static void gdth_copy_command(int hanum)
1697{
1698 register gdth_ha_str *ha;
1699 register gdth_cmd_str *cmd_ptr;
1700 register gdt6m_dpram_str __iomem *dp6m_ptr;
1701 register gdt6c_dpram_str __iomem *dp6c_ptr;
1702 gdt6_dpram_str __iomem *dp6_ptr;
1703 gdt2_dpram_str __iomem *dp2_ptr;
1704 ushort cp_count,dp_offset,cmd_no;
1705
1706 TRACE(("gdth_copy_command() hanum %d\n",hanum));
1707
1708 ha = HADATA(gdth_ctr_tab[hanum]);
1709 cp_count = ha->cmd_len;
1710 dp_offset= ha->cmd_offs_dpmem;
1711 cmd_no = ha->cmd_cnt;
1712 cmd_ptr = ha->pccb;
1713
1714 ++ha->cmd_cnt;
1715 if (ha->type == GDT_EISA)
1716 return; /* no DPMEM, no copy */
1717
1718 /* set cpcount dword aligned */
1719 if (cp_count & 3)
1720 cp_count += (4 - (cp_count & 3));
1721
1722 ha->cmd_offs_dpmem += cp_count;
1723
1724 /* set offset and service, copy command to DPMEM */
1725 if (ha->type == GDT_ISA) {
1726 dp2_ptr = ha->brd;
1727 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1728 &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
1729 gdth_writew((ushort)cmd_ptr->Service,
1730 &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
1731 memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1732 } else if (ha->type == GDT_PCI) {
1733 dp6_ptr = ha->brd;
1734 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1735 &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
1736 gdth_writew((ushort)cmd_ptr->Service,
1737 &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
1738 memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1739 } else if (ha->type == GDT_PCINEW) {
1740 dp6c_ptr = ha->brd;
1741 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1742 &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
1743 gdth_writew((ushort)cmd_ptr->Service,
1744 &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
1745 memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1746 } else if (ha->type == GDT_PCIMPR) {
1747 dp6m_ptr = ha->brd;
1748 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1749 &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
1750 gdth_writew((ushort)cmd_ptr->Service,
1751 &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
1752 memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1753 }
1754}
1755
1756
1757static void gdth_release_event(int hanum)
1758{
1759 register gdth_ha_str *ha;
1760
1761 TRACE(("gdth_release_event() hanum %d\n",hanum));
1762 ha = HADATA(gdth_ctr_tab[hanum]);
1763
1764#ifdef GDTH_STATISTICS
1765 {
1766 ulong32 i,j;
1767 for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
1768 if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
1769 ++i;
1770 }
1771 if (max_index < i) {
1772 max_index = i;
1773 TRACE3(("GDT: max_index = %d\n",(ushort)i));
1774 }
1775 }
1776#endif
1777
1778 if (ha->pccb->OpCode == GDT_INIT)
1779 ha->pccb->Service |= 0x80;
1780
1781 if (ha->type == GDT_EISA) {
1782 if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
1783 outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
1784 outb(ha->pccb->Service, ha->bmic + LDOORREG);
1785 } else if (ha->type == GDT_ISA) {
1786 gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
1787 } else if (ha->type == GDT_PCI) {
1788 gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
1789 } else if (ha->type == GDT_PCINEW) {
1790 outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
1791 } else if (ha->type == GDT_PCIMPR) {
1792 gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
1793 }
1794}
1795
1796
1797static int gdth_wait(int hanum,int index,ulong32 time)
1798{
1799 gdth_ha_str *ha;
1800 int answer_found = FALSE;
1801
1802 TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
1803
1804 ha = HADATA(gdth_ctr_tab[hanum]);
1805 if (index == 0)
1806 return 1; /* no wait required */
1807
1808 gdth_from_wait = TRUE;
1809 do {
7d12e780 1810 gdth_interrupt((int)ha->irq,ha);
1da177e4
LT		 1811 if (wait_hanum==hanum && wait_index==index) {
1812 answer_found = TRUE;
1813 break;
1814 }
1815 gdth_delay(1);
1816 } while (--time);
1817 gdth_from_wait = FALSE;
1818
1819 while (gdth_test_busy(hanum))
1820 gdth_delay(0);
1821
1822 return (answer_found);
1823}
1824
1825
1826static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
1827 ulong64 p2,ulong64 p3)
1828{
1829 register gdth_ha_str *ha;
1830 register gdth_cmd_str *cmd_ptr;
1831 int retries,index;
1832
1833 TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
1834
1835 ha = HADATA(gdth_ctr_tab[hanum]);
1836 cmd_ptr = ha->pccb;
1837 memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
1838
1839 /* make command */
1840 for (retries = INIT_RETRIES;;) {
1841 cmd_ptr->Service = service;
1842 cmd_ptr->RequestBuffer = INTERNAL_CMND;
1843 if (!(index=gdth_get_cmd_index(hanum))) {
1844 TRACE(("GDT: No free command index found\n"));
1845 return 0;
1846 }
1847 gdth_set_sema0(hanum);
1848 cmd_ptr->OpCode = opcode;
1849 cmd_ptr->BoardNode = LOCALBOARD;
1850 if (service == CACHESERVICE) {
1851 if (opcode == GDT_IOCTL) {
1852 cmd_ptr->u.ioctl.subfunc = p1;
1853 cmd_ptr->u.ioctl.channel = (ulong32)p2;
1854 cmd_ptr->u.ioctl.param_size = (ushort)p3;
1855 cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
1856 } else {
1857 if (ha->cache_feat & GDT_64BIT) {
1858 cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
1859 cmd_ptr->u.cache64.BlockNo = p2;
1860 } else {
1861 cmd_ptr->u.cache.DeviceNo = (ushort)p1;
1862 cmd_ptr->u.cache.BlockNo = (ulong32)p2;
1863 }
1864 }
1865 } else if (service == SCSIRAWSERVICE) {
1866 if (ha->raw_feat & GDT_64BIT) {
1867 cmd_ptr->u.raw64.direction = p1;
1868 cmd_ptr->u.raw64.bus = (unchar)p2;
1869 cmd_ptr->u.raw64.target = (unchar)p3;
1870 cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
1871 } else {
1872 cmd_ptr->u.raw.direction = p1;
1873 cmd_ptr->u.raw.bus = (unchar)p2;
1874 cmd_ptr->u.raw.target = (unchar)p3;
1875 cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
1876 }
1877 } else if (service == SCREENSERVICE) {
1878 if (opcode == GDT_REALTIME) {
1879 *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
1880 *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
1881 *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
1882 }
1883 }
1884 ha->cmd_len = sizeof(gdth_cmd_str);
1885 ha->cmd_offs_dpmem = 0;
1886 ha->cmd_cnt = 0;
1887 gdth_copy_command(hanum);
1888 gdth_release_event(hanum);
1889 gdth_delay(20);
1890 if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
1891 printk("GDT: Initialization error (timeout service %d)\n",service);
1892 return 0;
1893 }
1894 if (ha->status != S_BSY || --retries == 0)
1895 break;
1896 gdth_delay(1);
1897 }
1898
1899 return (ha->status != S_OK ? 0:1);
1900}
1901
1902
1903/* search for devices */
1904
1905static int __init gdth_search_drives(int hanum)
1906{
1907 register gdth_ha_str *ha;
1908 ushort cdev_cnt, i;
1909 int ok;
1910 ulong32 bus_no, drv_cnt, drv_no, j;
1911 gdth_getch_str *chn;
1912 gdth_drlist_str *drl;
1913 gdth_iochan_str *ioc;
1914 gdth_raw_iochan_str *iocr;
1915 gdth_arcdl_str *alst;
1916 gdth_alist_str *alst2;
1917 gdth_oem_str_ioctl *oemstr;
1918#ifdef INT_COAL
1919 gdth_perf_modes *pmod;
1920#endif
1921
1922#ifdef GDTH_RTC
1923 unchar rtc[12];
1924 ulong flags;
1925#endif
1926
1927 TRACE(("gdth_search_drives() hanum %d\n",hanum));
1928 ha = HADATA(gdth_ctr_tab[hanum]);
1929 ok = 0;
1930
1931 /* initialize controller services, at first: screen service */
1932 ha->screen_feat = 0;
1933 if (!force_dma32) {
1934 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
1935 if (ok)
1936 ha->screen_feat = GDT_64BIT;
1937 }
1938 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1939 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
1940 if (!ok) {
1941 printk("GDT-HA %d: Initialization error screen service (code %d)\n",
1942 hanum, ha->status);
1943 return 0;
1944 }
1945 TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
1946
1947#ifdef GDTH_RTC
1948 /* read realtime clock info, send to controller */
1949 /* 1. wait for the falling edge of update flag */
1950 spin_lock_irqsave(&rtc_lock, flags);
1951 for (j = 0; j < 1000000; ++j)
1952 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
1953 break;
1954 for (j = 0; j < 1000000; ++j)
1955 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
1956 break;
1957 /* 2. read info */
1958 do {
1959 for (j = 0; j < 12; ++j)
1960 rtc[j] = CMOS_READ(j);
1961 } while (rtc[0] != CMOS_READ(0));
7a960b76 1962 spin_unlock_irqrestore(&rtc_lock, flags);
1da177e4
LT		 1963 TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
1964 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
1965 /* 3. send to controller firmware */
1966 gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
1967 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
1968#endif
1969
1970 /* unfreeze all IOs */
1971 gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
1972
1973 /* initialize cache service */
1974 ha->cache_feat = 0;
1975 if (!force_dma32) {
1976 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
1977 if (ok)
1978 ha->cache_feat = GDT_64BIT;
1979 }
1980 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1981 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
1982 if (!ok) {
1983 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1984 hanum, ha->status);
1985 return 0;
1986 }
1987 TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
1988 cdev_cnt = (ushort)ha->info;
1989 ha->fw_vers = ha->service;
1990
1991#ifdef INT_COAL
1992 if (ha->type == GDT_PCIMPR) {
1993 /* set perf. modes */
1994 pmod = (gdth_perf_modes *)ha->pscratch;
1995 pmod->version = 1;
1996 pmod->st_mode = 1; /* enable one status buffer */
1997 *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
1998 pmod->st_buff_indx1 = COALINDEX;
1999 pmod->st_buff_addr2 = 0;
2000 pmod->st_buff_u_addr2 = 0;
2001 pmod->st_buff_indx2 = 0;
2002 pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
2003 pmod->cmd_mode = 0; // disable all cmd buffers
2004 pmod->cmd_buff_addr1 = 0;
2005 pmod->cmd_buff_u_addr1 = 0;
2006 pmod->cmd_buff_indx1 = 0;
2007 pmod->cmd_buff_addr2 = 0;
2008 pmod->cmd_buff_u_addr2 = 0;
2009 pmod->cmd_buff_indx2 = 0;
2010 pmod->cmd_buff_size = 0;
2011 pmod->reserved1 = 0;
2012 pmod->reserved2 = 0;
2013 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
2014 INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
2015 printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
2016 }
2017 }
2018#endif
2019
2020 /* detect number of buses - try new IOCTL */
2021 iocr = (gdth_raw_iochan_str *)ha->pscratch;
2022 iocr->hdr.version = 0xffffffff;
2023 iocr->hdr.list_entries = MAXBUS;
2024 iocr->hdr.first_chan = 0;
2025 iocr->hdr.last_chan = MAXBUS-1;
2026 iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
2027 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
2028 INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
2029 TRACE2(("IOCHAN_RAW_DESC supported!\n"));
2030 ha->bus_cnt = iocr->hdr.chan_count;
2031 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2032 if (iocr->list[bus_no].proc_id < MAXID)
2033 ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
2034 else
2035 ha->bus_id[bus_no] = 0xff;
2036 }
2037 } else {
2038 /* old method */
2039 chn = (gdth_getch_str *)ha->pscratch;
2040 for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
2041 chn->channel_no = bus_no;
2042 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2043 SCSI_CHAN_CNT | L_CTRL_PATTERN,
2044 IO_CHANNEL | INVALID_CHANNEL,
2045 sizeof(gdth_getch_str))) {
2046 if (bus_no == 0) {
2047 printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
2048 hanum, ha->status);
2049 return 0;
2050 }
2051 break;
2052 }
2053 if (chn->siop_id < MAXID)
2054 ha->bus_id[bus_no] = chn->siop_id;
2055 else
2056 ha->bus_id[bus_no] = 0xff;
2057 }
2058 ha->bus_cnt = (unchar)bus_no;
2059 }
2060 TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
2061
2062 /* read cache configuration */
2063 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
2064 INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
2065 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
2066 hanum, ha->status);
2067 return 0;
2068 }
2069 ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
2070 TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
2071 ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
2072 ha->cpar.write_back,ha->cpar.block_size));
2073
2074 /* read board info and features */
2075 ha->more_proc = FALSE;
2076 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
2077 INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
2078 memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
2079 sizeof(gdth_binfo_str));
2080 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
2081 INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
2082 TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
2083 ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
2084 ha->more_proc = TRUE;
2085 }
2086 } else {
2087 TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
2088 strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
2089 }
2090 TRACE2(("Controller name: %s\n",ha->binfo.type_string));
2091
2092 /* read more informations */
2093 if (ha->more_proc) {
2094 /* physical drives, channel addresses */
2095 ioc = (gdth_iochan_str *)ha->pscratch;
2096 ioc->hdr.version = 0xffffffff;
2097 ioc->hdr.list_entries = MAXBUS;
2098 ioc->hdr.first_chan = 0;
2099 ioc->hdr.last_chan = MAXBUS-1;
2100 ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
2101 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
2102 INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
2103 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2104 ha->raw[bus_no].address = ioc->list[bus_no].address;
2105 ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
2106 }
2107 } else {
2108 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2109 ha->raw[bus_no].address = IO_CHANNEL;
2110 ha->raw[bus_no].local_no = bus_no;
2111 }
2112 }
2113 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2114 chn = (gdth_getch_str *)ha->pscratch;
2115 chn->channel_no = ha->raw[bus_no].local_no;
2116 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2117 SCSI_CHAN_CNT | L_CTRL_PATTERN,
2118 ha->raw[bus_no].address | INVALID_CHANNEL,
2119 sizeof(gdth_getch_str))) {
2120 ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
2121 TRACE2(("Channel %d: %d phys. drives\n",
2122 bus_no,chn->drive_cnt));
2123 }
2124 if (ha->raw[bus_no].pdev_cnt > 0) {
2125 drl = (gdth_drlist_str *)ha->pscratch;
2126 drl->sc_no = ha->raw[bus_no].local_no;
2127 drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
2128 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2129 SCSI_DR_LIST | L_CTRL_PATTERN,
2130 ha->raw[bus_no].address | INVALID_CHANNEL,
2131 sizeof(gdth_drlist_str))) {
2132 for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
2133 ha->raw[bus_no].id_list[j] = drl->sc_list[j];
2134 } else {
2135 ha->raw[bus_no].pdev_cnt = 0;
2136 }
2137 }
2138 }
2139
2140 /* logical drives */
2141 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
2142 INVALID_CHANNEL,sizeof(ulong32))) {
2143 drv_cnt = *(ulong32 *)ha->pscratch;
2144 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
2145 INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
2146 for (j = 0; j < drv_cnt; ++j) {
2147 drv_no = ((ulong32 *)ha->pscratch)[j];
2148 if (drv_no < MAX_LDRIVES) {
2149 ha->hdr[drv_no].is_logdrv = TRUE;
2150 TRACE2(("Drive %d is log. drive\n",drv_no));
2151 }
2152 }
2153 }
2154 alst = (gdth_arcdl_str *)ha->pscratch;
2155 alst->entries_avail = MAX_LDRIVES;
2156 alst->first_entry = 0;
2157 alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
2158 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2159 ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
2160 INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
2161 (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
2162 for (j = 0; j < alst->entries_init; ++j) {
2163 ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
2164 ha->hdr[j].is_master = alst->list[j].is_master;
2165 ha->hdr[j].is_parity = alst->list[j].is_parity;
2166 ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
2167 ha->hdr[j].master_no = alst->list[j].cd_handle;
2168 }
2169 } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2170 ARRAY_DRV_LIST | LA_CTRL_PATTERN,
2171 0, 35 * sizeof(gdth_alist_str))) {
2172 for (j = 0; j < 35; ++j) {
2173 alst2 = &((gdth_alist_str *)ha->pscratch)[j];
2174 ha->hdr[j].is_arraydrv = alst2->is_arrayd;
2175 ha->hdr[j].is_master = alst2->is_master;
2176 ha->hdr[j].is_parity = alst2->is_parity;
2177 ha->hdr[j].is_hotfix = alst2->is_hotfix;
2178 ha->hdr[j].master_no = alst2->cd_handle;
2179 }
2180 }
2181 }
2182 }
2183
2184 /* initialize raw service */
2185 ha->raw_feat = 0;
2186 if (!force_dma32) {
2187 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
2188 if (ok)
2189 ha->raw_feat = GDT_64BIT;
2190 }
2191 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
2192 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
2193 if (!ok) {
2194 printk("GDT-HA %d: Initialization error raw service (code %d)\n",
2195 hanum, ha->status);
2196 return 0;
2197 }
2198 TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
2199
2200 /* set/get features raw service (scatter/gather) */
2201 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
2202 0,0)) {
2203 TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
2204 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
2205 TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
2206 ha->info));
2207 ha->raw_feat |= (ushort)ha->info;
2208 }
2209 }
2210
2211 /* set/get features cache service (equal to raw service) */
2212 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
2213 SCATTER_GATHER,0)) {
2214 TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
2215 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
2216 TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
2217 ha->info));
2218 ha->cache_feat |= (ushort)ha->info;
2219 }
2220 }
2221
2222 /* reserve drives for raw service */
2223 if (reserve_mode != 0) {
2224 gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
2225 reserve_mode == 1 ? 1 : 3, 0, 0);
2226 TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
2227 ha->status));
2228 }
2229 for (i = 0; i < MAX_RES_ARGS; i += 4) {
2230 if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
2231 reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
2232 TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
2233 reserve_list[i], reserve_list[i+1],
2234 reserve_list[i+2], reserve_list[i+3]));
2235 if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
2236 reserve_list[i+1], reserve_list[i+2] |
2237 (reserve_list[i+3] << 8))) {
2238 printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
2239 hanum, ha->status);
2240 }
2241 }
2242 }
2243
2244 /* Determine OEM string using IOCTL */
2245 oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
2246 oemstr->params.ctl_version = 0x01;
2247 oemstr->params.buffer_size = sizeof(oemstr->text);
2248 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2249 CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
2250 sizeof(gdth_oem_str_ioctl))) {
2251 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
2252 printk("GDT-HA %d: Vendor: %s Name: %s\n",
2253 hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
2254 /* Save the Host Drive inquiry data */
2255#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2256 strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
2257 sizeof(ha->oem_name));
2258#else
2259 strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7);
2260 ha->oem_name[7] = '\0';
2261#endif
2262 } else {
2263 /* Old method, based on PCI ID */
2264 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
2265 printk("GDT-HA %d: Name: %s\n",
2266 hanum,ha->binfo.type_string);
2267#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2268 if (ha->oem_id == OEM_ID_INTEL)
2269 strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
2270 else
2271 strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
2272#else
2273 if (ha->oem_id == OEM_ID_INTEL)
2274 strcpy(ha->oem_name,"Intel ");
2275 else
2276 strcpy(ha->oem_name,"ICP ");
2277#endif
2278 }
2279
2280 /* scanning for host drives */
2281 for (i = 0; i < cdev_cnt; ++i)
2282 gdth_analyse_hdrive(hanum,i);
2283
2284 TRACE(("gdth_search_drives() OK\n"));
2285 return 1;
2286}
2287
2288static int gdth_analyse_hdrive(int hanum,ushort hdrive)
2289{
2290 register gdth_ha_str *ha;
2291 ulong32 drv_cyls;
2292 int drv_hds, drv_secs;
2293
2294 TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
2295 if (hdrive >= MAX_HDRIVES)
2296 return 0;
2297 ha = HADATA(gdth_ctr_tab[hanum]);
2298
2299 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
2300 return 0;
2301 ha->hdr[hdrive].present = TRUE;
2302 ha->hdr[hdrive].size = ha->info;
2303
2304 /* evaluate mapping (sectors per head, heads per cylinder) */
2305 ha->hdr[hdrive].size &= ~SECS32;
2306 if (ha->info2 == 0) {
2307 gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
2308 } else {
2309 drv_hds = ha->info2 & 0xff;
2310 drv_secs = (ha->info2 >> 8) & 0xff;
2311 drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
2312 }
2313 ha->hdr[hdrive].heads = (unchar)drv_hds;
2314 ha->hdr[hdrive].secs = (unchar)drv_secs;
2315 /* round size */
2316 ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
2317
2318 if (ha->cache_feat & GDT_64BIT) {
2319 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
2320 && ha->info2 != 0) {
2321 ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
2322 }
2323 }
2324 TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
2325 hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
2326
2327 /* get informations about device */
2328 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
2329 TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
2330 hdrive,ha->info));
2331 ha->hdr[hdrive].devtype = (ushort)ha->info;
2332 }
2333
2334 /* cluster info */
2335 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
2336 TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
2337 hdrive,ha->info));
2338 if (!shared_access)
2339 ha->hdr[hdrive].cluster_type = (unchar)ha->info;
2340 }
2341
2342 /* R/W attributes */
2343 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
2344 TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
2345 hdrive,ha->info));
2346 ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
2347 }
2348
2349 return 1;
2350}
2351
2352
2353/* command queueing/sending functions */
2354
2355static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
2356{
2357 register gdth_ha_str *ha;
2358 register Scsi_Cmnd *pscp;
2359 register Scsi_Cmnd *nscp;
2360 ulong flags;
2361 unchar b, t;
2362
2363 TRACE(("gdth_putq() priority %d\n",priority));
2364 ha = HADATA(gdth_ctr_tab[hanum]);
2365 spin_lock_irqsave(&ha->smp_lock, flags);
2366
687d2bc4 2367 if (!IS_GDTH_INTERNAL_CMD(scp)) {
cbd5f69b
LA		 2368 scp->SCp.this_residual = (int)priority;
2369 b = virt_ctr ? NUMDATA(scp->device->host)->busnum:scp->device->channel;
2370 t = scp->device->id;
2371 if (priority >= DEFAULT_PRI) {
2372 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2373 (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
2374 TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
2375 scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
2376 }
1da177e4
LT		 2377 }
2378 }
2379
2380 if (ha->req_first==NULL) {
2381 ha->req_first = scp; /* queue was empty */
2382 scp->SCp.ptr = NULL;
2383 } else { /* queue not empty */
2384 pscp = ha->req_first;
2385 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2386 /* priority: 0-highest,..,0xff-lowest */
2387 while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
2388 pscp = nscp;
2389 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2390 }
2391 pscp->SCp.ptr = (char *)scp;
2392 scp->SCp.ptr = (char *)nscp;
2393 }
2394 spin_unlock_irqrestore(&ha->smp_lock, flags);
2395
2396#ifdef GDTH_STATISTICS
2397 flags = 0;
2398 for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
2399 ++flags;
2400 if (max_rq < flags) {
2401 max_rq = flags;
2402 TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
2403 }
2404#endif
2405}
2406
2407static void gdth_next(int hanum)
2408{
2409 register gdth_ha_str *ha;
2410 register Scsi_Cmnd *pscp;
2411 register Scsi_Cmnd *nscp;
2412 unchar b, t, l, firsttime;
2413 unchar this_cmd, next_cmd;
2414 ulong flags = 0;
2415 int cmd_index;
2416
2417 TRACE(("gdth_next() hanum %d\n",hanum));
2418 ha = HADATA(gdth_ctr_tab[hanum]);
2419 if (!gdth_polling)
2420 spin_lock_irqsave(&ha->smp_lock, flags);
2421
2422 ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
2423 this_cmd = firsttime = TRUE;
2424 next_cmd = gdth_polling ? FALSE:TRUE;
2425 cmd_index = 0;
2426
2427 for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
2428 if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
2429 pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
687d2bc4 2430 if (!IS_GDTH_INTERNAL_CMD(nscp)) {
cbd5f69b
LA		 2431 b = virt_ctr ?
2432 NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
2433 t = nscp->device->id;
2434 l = nscp->device->lun;
2435 if (nscp->SCp.this_residual >= DEFAULT_PRI) {
2436 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2437 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
2438 continue;
2439 }
2440 } else
2441 b = t = l = 0;
1da177e4
LT		 2442
2443 if (firsttime) {
2444 if (gdth_test_busy(hanum)) { /* controller busy ? */
2445 TRACE(("gdth_next() controller %d busy !\n",hanum));
2446 if (!gdth_polling) {
2447 spin_unlock_irqrestore(&ha->smp_lock, flags);
2448 return;
2449 }
2450 while (gdth_test_busy(hanum))
2451 gdth_delay(1);
2452 }
2453 firsttime = FALSE;
2454 }
2455
687d2bc4 2456 if (!IS_GDTH_INTERNAL_CMD(nscp)) {
1da177e4
LT		 2457 if (nscp->SCp.phase == -1) {
2458 nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
2459 if (nscp->cmnd[0] == TEST_UNIT_READY) {
2460 TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
2461 b, t, l));
2462 /* TEST_UNIT_READY -> set scan mode */
2463 if ((ha->scan_mode & 0x0f) == 0) {
2464 if (b == 0 && t == 0 && l == 0) {
2465 ha->scan_mode |= 1;
2466 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2467 }
2468 } else if ((ha->scan_mode & 0x0f) == 1) {
2469 if (b == 0 && ((t == 0 && l == 1) ||
2470 (t == 1 && l == 0))) {
2471 nscp->SCp.sent_command = GDT_SCAN_START;
2472 nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
2473 | SCSIRAWSERVICE;
2474 ha->scan_mode = 0x12;
2475 TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
2476 ha->scan_mode));
2477 } else {
2478 ha->scan_mode &= 0x10;
2479 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2480 }
2481 } else if (ha->scan_mode == 0x12) {
2482 if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
2483 nscp->SCp.phase = SCSIRAWSERVICE;
2484 nscp->SCp.sent_command = GDT_SCAN_END;
2485 ha->scan_mode &= 0x10;
2486 TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
2487 ha->scan_mode));
2488 }
2489 }
2490 }
2491 if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
2492 nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
2493 (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
2494 /* always GDT_CLUST_INFO! */
2495 nscp->SCp.sent_command = GDT_CLUST_INFO;
2496 }
2497 }
2498 }
2499
2500 if (nscp->SCp.sent_command != -1) {
2501 if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
2502 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2503 this_cmd = FALSE;
2504 next_cmd = FALSE;
2505 } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
2506 if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2507 this_cmd = FALSE;
2508 next_cmd = FALSE;
2509 } else {
2510 memset((char*)nscp->sense_buffer,0,16);
2511 nscp->sense_buffer[0] = 0x70;
2512 nscp->sense_buffer[2] = NOT_READY;
2513 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2514 if (!nscp->SCp.have_data_in)
2515 nscp->SCp.have_data_in++;
2516 else
b8bff2ae 2517 gdth_scsi_done(nscp);
1da177e4 2518 }
687d2bc4 2519 } else if (IS_GDTH_INTERNAL_CMD(nscp)) {
1da177e4
LT		 2520 if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
2521 this_cmd = FALSE;
2522 next_cmd = FALSE;
2523 } else if (b != ha->virt_bus) {
2524 if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
2525 !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2526 this_cmd = FALSE;
2527 else
2528 ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
2529 } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
2530 TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
2531 nscp->cmnd[0], b, t, l));
2532 nscp->result = DID_BAD_TARGET << 16;
2533 if (!nscp->SCp.have_data_in)
2534 nscp->SCp.have_data_in++;
2535 else
b8bff2ae 2536 gdth_scsi_done(nscp);
1da177e4
LT		 2537 } else {
2538 switch (nscp->cmnd[0]) {
2539 case TEST_UNIT_READY:
2540 case INQUIRY:
2541 case REQUEST_SENSE:
2542 case READ_CAPACITY:
2543 case VERIFY:
2544 case START_STOP:
2545 case MODE_SENSE:
2546 case SERVICE_ACTION_IN:
2547 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2548 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2549 nscp->cmnd[4],nscp->cmnd[5]));
2550 if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
2551 /* return UNIT_ATTENTION */
2552 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2553 nscp->cmnd[0], t));
2554 ha->hdr[t].media_changed = FALSE;
2555 memset((char*)nscp->sense_buffer,0,16);
2556 nscp->sense_buffer[0] = 0x70;
2557 nscp->sense_buffer[2] = UNIT_ATTENTION;
2558 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2559 if (!nscp->SCp.have_data_in)
2560 nscp->SCp.have_data_in++;
2561 else
b8bff2ae
MW		 2562 gdth_scsi_done(nscp);
2563 } else if (gdth_internal_cache_cmd(hanum, nscp))
2564 gdth_scsi_done(nscp);
1da177e4
LT		 2565 break;
2566
2567 case ALLOW_MEDIUM_REMOVAL:
2568 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2569 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2570 nscp->cmnd[4],nscp->cmnd[5]));
2571 if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
2572 TRACE(("Prevent r. nonremov. drive->do nothing\n"));
2573 nscp->result = DID_OK << 16;
2574 nscp->sense_buffer[0] = 0;
2575 if (!nscp->SCp.have_data_in)
2576 nscp->SCp.have_data_in++;
2577 else
b8bff2ae 2578 gdth_scsi_done(nscp);
1da177e4
LT		 2579 } else {
2580 nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
2581 TRACE(("Prevent/allow r. %d rem. drive %d\n",
2582 nscp->cmnd[4],nscp->cmnd[3]));
2583 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2584 this_cmd = FALSE;
2585 }
2586 break;
2587
2588 case RESERVE:
2589 case RELEASE:
2590 TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
2591 "RESERVE" : "RELEASE"));
2592 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2593 this_cmd = FALSE;
2594 break;
2595
2596 case READ_6:
2597 case WRITE_6:
2598 case READ_10:
2599 case WRITE_10:
2600 case READ_16:
2601 case WRITE_16:
2602 if (ha->hdr[t].media_changed) {
2603 /* return UNIT_ATTENTION */
2604 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2605 nscp->cmnd[0], t));
2606 ha->hdr[t].media_changed = FALSE;
2607 memset((char*)nscp->sense_buffer,0,16);
2608 nscp->sense_buffer[0] = 0x70;
2609 nscp->sense_buffer[2] = UNIT_ATTENTION;
2610 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2611 if (!nscp->SCp.have_data_in)
2612 nscp->SCp.have_data_in++;
2613 else
b8bff2ae
MW		 2614 gdth_scsi_done(nscp);
2615 } else if (!(cmd_index=gdth_fill_cache_cmd(hanum, nscp, t)))
1da177e4
LT		 2616 this_cmd = FALSE;
2617 break;
2618
2619 default:
2620 TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
2621 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2622 nscp->cmnd[4],nscp->cmnd[5]));
2623 printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
2624 hanum, nscp->cmnd[0]);
2625 nscp->result = DID_ABORT << 16;
2626 if (!nscp->SCp.have_data_in)
2627 nscp->SCp.have_data_in++;
2628 else
b8bff2ae 2629 gdth_scsi_done(nscp);
1da177e4
LT		 2630 break;
2631 }
2632 }
2633
2634 if (!this_cmd)
2635 break;
2636 if (nscp == ha->req_first)
2637 ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
2638 else
2639 pscp->SCp.ptr = nscp->SCp.ptr;
2640 if (!next_cmd)
2641 break;
2642 }
2643
2644 if (ha->cmd_cnt > 0) {
2645 gdth_release_event(hanum);
2646 }
2647
2648 if (!gdth_polling)
2649 spin_unlock_irqrestore(&ha->smp_lock, flags);
2650
2651 if (gdth_polling && ha->cmd_cnt > 0) {
2652 if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
2653 printk("GDT-HA %d: Command %d timed out !\n",
2654 hanum,cmd_index);
2655 }
2656}
2657
2658static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
2659 char *buffer,ushort count)
2660{
2661 ushort cpcount,i;
2662 ushort cpsum,cpnow;
2663 struct scatterlist *sl;
2664 gdth_ha_str *ha;
2665 char *address;
2666
5d5ff44f 2667 cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
1da177e4
LT		 2668 ha = HADATA(gdth_ctr_tab[hanum]);
2669
2670 if (scp->use_sg) {
2671 sl = (struct scatterlist *)scp->request_buffer;
2672 for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
cbd5f69b 2673 unsigned long flags;
1da177e4
LT		 2674 cpnow = (ushort)sl->length;
2675 TRACE(("copy_internal() now %d sum %d count %d %d\n",
2676 cpnow,cpsum,cpcount,(ushort)scp->bufflen));
2677 if (cpsum+cpnow > cpcount)
2678 cpnow = cpcount - cpsum;
2679 cpsum += cpnow;
2680 if (!sl->page) {
2681 printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
2682 hanum);
2683 return;
2684 }
cbd5f69b
LA		 2685 local_irq_save(flags);
2686#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2687 address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
2688 memcpy(address,buffer,cpnow);
2689 flush_dcache_page(sl->page);
2690 kunmap_atomic(address, KM_BIO_SRC_IRQ);
2691#else
2692 address = kmap_atomic(sl->page, KM_BH_IRQ) + sl->offset;
1da177e4 2693 memcpy(address,buffer,cpnow);
cbd5f69b
LA		 2694 flush_dcache_page(sl->page);
2695 kunmap_atomic(address, KM_BH_IRQ);
2696#endif
2697 local_irq_restore(flags);
1da177e4
LT		 2698 if (cpsum == cpcount)
2699 break;
2700 buffer += cpnow;
2701 }
2702 } else {
2703 TRACE(("copy_internal() count %d\n",cpcount));
2704 memcpy((char*)scp->request_buffer,buffer,cpcount);
2705 }
2706}
2707
2708static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
2709{
2710 register gdth_ha_str *ha;
2711 unchar t;
2712 gdth_inq_data inq;
2713 gdth_rdcap_data rdc;
2714 gdth_sense_data sd;
2715 gdth_modep_data mpd;
2716
2717 ha = HADATA(gdth_ctr_tab[hanum]);
2718 t = scp->device->id;
2719 TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
2720 scp->cmnd[0],t));
2721
2722 scp->result = DID_OK << 16;
2723 scp->sense_buffer[0] = 0;
2724
2725 switch (scp->cmnd[0]) {
2726 case TEST_UNIT_READY:
2727 case VERIFY:
2728 case START_STOP:
2729 TRACE2(("Test/Verify/Start hdrive %d\n",t));
2730 break;
2731
2732 case INQUIRY:
2733 TRACE2(("Inquiry hdrive %d devtype %d\n",
2734 t,ha->hdr[t].devtype));
2735 inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
2736 /* you can here set all disks to removable, if you want to do
2737 a flush using the ALLOW_MEDIUM_REMOVAL command */
2738 inq.modif_rmb = 0x00;
2739 if ((ha->hdr[t].devtype & 1) ||
2740 (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
2741 inq.modif_rmb = 0x80;
2742 inq.version = 2;
2743 inq.resp_aenc = 2;
2744 inq.add_length= 32;
2745 strcpy(inq.vendor,ha->oem_name);
2746 sprintf(inq.product,"Host Drive #%02d",t);
2747 strcpy(inq.revision," ");
2748 gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
2749 break;
2750
2751 case REQUEST_SENSE:
2752 TRACE2(("Request sense hdrive %d\n",t));
2753 sd.errorcode = 0x70;
2754 sd.segno = 0x00;
2755 sd.key = NO_SENSE;
2756 sd.info = 0;
2757 sd.add_length= 0;
2758 gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
2759 break;
2760
2761 case MODE_SENSE:
2762 TRACE2(("Mode sense hdrive %d\n",t));
2763 memset((char*)&mpd,0,sizeof(gdth_modep_data));
2764 mpd.hd.data_length = sizeof(gdth_modep_data);
2765 mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
2766 mpd.hd.bd_length = sizeof(mpd.bd);
2767 mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
2768 mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
2769 mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
2770 gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
2771 break;
2772
2773 case READ_CAPACITY:
2774 TRACE2(("Read capacity hdrive %d\n",t));
2775 if (ha->hdr[t].size > (ulong64)0xffffffff)
2776 rdc.last_block_no = 0xffffffff;
2777 else
2778 rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
2779 rdc.block_length = cpu_to_be32(SECTOR_SIZE);
2780 gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
2781 break;
2782
2783 case SERVICE_ACTION_IN:
2784 if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
2785 (ha->cache_feat & GDT_64BIT)) {
2786 gdth_rdcap16_data rdc16;
2787
2788 TRACE2(("Read capacity (16) hdrive %d\n",t));
2789 rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
2790 rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
2791 gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
2792 } else {
2793 scp->result = DID_ABORT << 16;
2794 }
2795 break;
2796
2797 default:
2798 TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
2799 break;
2800 }
2801
2802 if (!scp->SCp.have_data_in)
2803 scp->SCp.have_data_in++;
2804 else
2805 return 1;
2806
2807 return 0;
2808}
2809
2810static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
2811{
2812 register gdth_ha_str *ha;
2813 register gdth_cmd_str *cmdp;
2814 struct scatterlist *sl;
2815 ulong32 cnt, blockcnt;
2816 ulong64 no, blockno;
2817 dma_addr_t phys_addr;
2818 int i, cmd_index, read_write, sgcnt, mode64;
2819 struct page *page;
2820 ulong offset;
2821
2822 ha = HADATA(gdth_ctr_tab[hanum]);
2823 cmdp = ha->pccb;
2824 TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
2825 scp->cmnd[0],scp->cmd_len,hdrive));
2826
2827 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2828 return 0;
2829
2830 mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
2831 /* test for READ_16, WRITE_16 if !mode64 ? ---
2832 not required, should not occur due to error return on
2833 READ_CAPACITY_16 */
2834
2835 cmdp->Service = CACHESERVICE;
2836 cmdp->RequestBuffer = scp;
2837 /* search free command index */
2838 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
2839 TRACE(("GDT: No free command index found\n"));
2840 return 0;
2841 }
2842 /* if it's the first command, set command semaphore */
2843 if (ha->cmd_cnt == 0)
2844 gdth_set_sema0(hanum);
2845
2846 /* fill command */
2847 read_write = 0;
2848 if (scp->SCp.sent_command != -1)
2849 cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
2850 else if (scp->cmnd[0] == RESERVE)
2851 cmdp->OpCode = GDT_RESERVE_DRV;
2852 else if (scp->cmnd[0] == RELEASE)
2853 cmdp->OpCode = GDT_RELEASE_DRV;
2854 else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
2855 if (scp->cmnd[4] & 1) /* prevent ? */
2856 cmdp->OpCode = GDT_MOUNT;
2857 else if (scp->cmnd[3] & 1) /* removable drive ? */
2858 cmdp->OpCode = GDT_UNMOUNT;
2859 else
2860 cmdp->OpCode = GDT_FLUSH;
2861 } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
2862 scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
2863 ) {
2864 read_write = 1;
2865 if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
2866 (ha->cache_feat & GDT_WR_THROUGH)))
2867 cmdp->OpCode = GDT_WRITE_THR;
2868 else
2869 cmdp->OpCode = GDT_WRITE;
2870 } else {
2871 read_write = 2;
2872 cmdp->OpCode = GDT_READ;
2873 }
2874
2875 cmdp->BoardNode = LOCALBOARD;
2876 if (mode64) {
2877 cmdp->u.cache64.DeviceNo = hdrive;
2878 cmdp->u.cache64.BlockNo = 1;
2879 cmdp->u.cache64.sg_canz = 0;
2880 } else {
2881 cmdp->u.cache.DeviceNo = hdrive;
2882 cmdp->u.cache.BlockNo = 1;
2883 cmdp->u.cache.sg_canz = 0;
2884 }
2885
2886 if (read_write) {
2887 if (scp->cmd_len == 16) {
2888 memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
2889 blockno = be64_to_cpu(no);
2890 memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
2891 blockcnt = be32_to_cpu(cnt);
2892 } else if (scp->cmd_len == 10) {
2893 memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
2894 blockno = be32_to_cpu(no);
2895 memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
2896 blockcnt = be16_to_cpu(cnt);
2897 } else {
2898 memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
2899 blockno = be32_to_cpu(no) & 0x001fffffUL;
2900 blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
2901 }
2902 if (mode64) {
2903 cmdp->u.cache64.BlockNo = blockno;
2904 cmdp->u.cache64.BlockCnt = blockcnt;
2905 } else {
2906 cmdp->u.cache.BlockNo = (ulong32)blockno;
2907 cmdp->u.cache.BlockCnt = blockcnt;
2908 }
2909
2910 if (scp->use_sg) {
2911 sl = (struct scatterlist *)scp->request_buffer;
2912 sgcnt = scp->use_sg;
2913 scp->SCp.Status = GDTH_MAP_SG;
2914 scp->SCp.Message = (read_write == 1 ?
2915 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2916 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
2917 if (mode64) {
2918 cmdp->u.cache64.DestAddr= (ulong64)-1;
2919 cmdp->u.cache64.sg_canz = sgcnt;
2920 for (i=0; i<sgcnt; ++i,++sl) {
2921 cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2922#ifdef GDTH_DMA_STATISTICS
2923 if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2924 ha->dma64_cnt++;
2925 else
2926 ha->dma32_cnt++;
2927#endif
2928 cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
2929 }
2930 } else {
2931 cmdp->u.cache.DestAddr= 0xffffffff;
2932 cmdp->u.cache.sg_canz = sgcnt;
2933 for (i=0; i<sgcnt; ++i,++sl) {
2934 cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
2935#ifdef GDTH_DMA_STATISTICS
2936 ha->dma32_cnt++;
2937#endif
2938 cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
2939 }
2940 }
2941
2942#ifdef GDTH_STATISTICS
2943 if (max_sg < (ulong32)sgcnt) {
2944 max_sg = (ulong32)sgcnt;
2945 TRACE3(("GDT: max_sg = %d\n",max_sg));
2946 }
2947#endif
2948
40cdc840 2949 } else if (scp->request_bufflen) {
1da177e4
LT		 2950 scp->SCp.Status = GDTH_MAP_SINGLE;
2951 scp->SCp.Message = (read_write == 1 ?
2952 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2953 page = virt_to_page(scp->request_buffer);
2954 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
2955 phys_addr = pci_map_page(ha->pdev,page,offset,
2956 scp->request_bufflen,scp->SCp.Message);
2957 scp->SCp.dma_handle = phys_addr;
2958 if (mode64) {
2959 if (ha->cache_feat & SCATTER_GATHER) {
2960 cmdp->u.cache64.DestAddr = (ulong64)-1;
2961 cmdp->u.cache64.sg_canz = 1;
2962 cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
2963 cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
2964 cmdp->u.cache64.sg_lst[1].sg_len = 0;
2965 } else {
2966 cmdp->u.cache64.DestAddr = phys_addr;
2967 cmdp->u.cache64.sg_canz= 0;
2968 }
2969 } else {
2970 if (ha->cache_feat & SCATTER_GATHER) {
2971 cmdp->u.cache.DestAddr = 0xffffffff;
2972 cmdp->u.cache.sg_canz = 1;
2973 cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
2974 cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
2975 cmdp->u.cache.sg_lst[1].sg_len = 0;
2976 } else {
2977 cmdp->u.cache.DestAddr = phys_addr;
2978 cmdp->u.cache.sg_canz= 0;
2979 }
2980 }
2981 }
2982 }
2983 /* evaluate command size, check space */
2984 if (mode64) {
2985 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2986 cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
2987 cmdp->u.cache64.sg_lst[0].sg_ptr,
2988 cmdp->u.cache64.sg_lst[0].sg_len));
2989 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2990 cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
2991 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
2992 (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
2993 } else {
2994 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2995 cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
2996 cmdp->u.cache.sg_lst[0].sg_ptr,
2997 cmdp->u.cache.sg_lst[0].sg_len));
2998 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2999 cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
3000 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
3001 (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
3002 }
3003 if (ha->cmd_len & 3)
3004 ha->cmd_len += (4 - (ha->cmd_len & 3));
3005
3006 if (ha->cmd_cnt > 0) {
3007 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3008 ha->ic_all_size) {
3009 TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
3010 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3011 return 0;
3012 }
3013 }
3014
3015 /* copy command */
3016 gdth_copy_command(hanum);
3017 return cmd_index;
3018}
3019
3020static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
3021{
3022 register gdth_ha_str *ha;
3023 register gdth_cmd_str *cmdp;
3024 struct scatterlist *sl;
3025 ushort i;
3026 dma_addr_t phys_addr, sense_paddr;
3027 int cmd_index, sgcnt, mode64;
3028 unchar t,l;
3029 struct page *page;
3030 ulong offset;
3031
3032 ha = HADATA(gdth_ctr_tab[hanum]);
3033 t = scp->device->id;
3034 l = scp->device->lun;
3035 cmdp = ha->pccb;
3036 TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
3037 scp->cmnd[0],b,t,l));
3038
3039 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
3040 return 0;
3041
3042 mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
3043
3044 cmdp->Service = SCSIRAWSERVICE;
3045 cmdp->RequestBuffer = scp;
3046 /* search free command index */
3047 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
3048 TRACE(("GDT: No free command index found\n"));
3049 return 0;
3050 }
3051 /* if it's the first command, set command semaphore */
3052 if (ha->cmd_cnt == 0)
3053 gdth_set_sema0(hanum);
3054
3055 /* fill command */
3056 if (scp->SCp.sent_command != -1) {
3057 cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
3058 cmdp->BoardNode = LOCALBOARD;
3059 if (mode64) {
3060 cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
3061 TRACE2(("special raw cmd 0x%x param 0x%x\n",
3062 cmdp->OpCode, cmdp->u.raw64.direction));
3063 /* evaluate command size */
3064 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
3065 } else {
3066 cmdp->u.raw.direction = (scp->SCp.phase >> 8);
3067 TRACE2(("special raw cmd 0x%x param 0x%x\n",
3068 cmdp->OpCode, cmdp->u.raw.direction));
3069 /* evaluate command size */
3070 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
3071 }
3072
3073 } else {
3074 page = virt_to_page(scp->sense_buffer);
3075 offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
3076 sense_paddr = pci_map_page(ha->pdev,page,offset,
3077 16,PCI_DMA_FROMDEVICE);
cbd5f69b 3078 *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
1da177e4 3079 /* high part, if 64bit */
cbd5f69b 3080 *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
1da177e4
LT		 3081 cmdp->OpCode = GDT_WRITE; /* always */
3082 cmdp->BoardNode = LOCALBOARD;
3083 if (mode64) {
3084 cmdp->u.raw64.reserved = 0;
3085 cmdp->u.raw64.mdisc_time = 0;
3086 cmdp->u.raw64.mcon_time = 0;
3087 cmdp->u.raw64.clen = scp->cmd_len;
3088 cmdp->u.raw64.target = t;
3089 cmdp->u.raw64.lun = l;
3090 cmdp->u.raw64.bus = b;
3091 cmdp->u.raw64.priority = 0;
3092 cmdp->u.raw64.sdlen = scp->request_bufflen;
3093 cmdp->u.raw64.sense_len = 16;
3094 cmdp->u.raw64.sense_data = sense_paddr;
3095 cmdp->u.raw64.direction =
3096 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
3097 memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
bb9ba31c 3098 cmdp->u.raw64.sg_ranz = 0;
1da177e4
LT		 3099 } else {
3100 cmdp->u.raw.reserved = 0;
3101 cmdp->u.raw.mdisc_time = 0;
3102 cmdp->u.raw.mcon_time = 0;
3103 cmdp->u.raw.clen = scp->cmd_len;
3104 cmdp->u.raw.target = t;
3105 cmdp->u.raw.lun = l;
3106 cmdp->u.raw.bus = b;
3107 cmdp->u.raw.priority = 0;
3108 cmdp->u.raw.link_p = 0;
3109 cmdp->u.raw.sdlen = scp->request_bufflen;
3110 cmdp->u.raw.sense_len = 16;
3111 cmdp->u.raw.sense_data = sense_paddr;
3112 cmdp->u.raw.direction =
3113 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
3114 memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
bb9ba31c 3115 cmdp->u.raw.sg_ranz = 0;
1da177e4
LT		 3116 }
3117
3118 if (scp->use_sg) {
3119 sl = (struct scatterlist *)scp->request_buffer;
3120 sgcnt = scp->use_sg;
3121 scp->SCp.Status = GDTH_MAP_SG;
3122 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
3123 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
3124 if (mode64) {
3125 cmdp->u.raw64.sdata = (ulong64)-1;
3126 cmdp->u.raw64.sg_ranz = sgcnt;
3127 for (i=0; i<sgcnt; ++i,++sl) {
3128 cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
3129#ifdef GDTH_DMA_STATISTICS
3130 if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
3131 ha->dma64_cnt++;
3132 else
3133 ha->dma32_cnt++;
3134#endif
3135 cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
3136 }
3137 } else {
3138 cmdp->u.raw.sdata = 0xffffffff;
3139 cmdp->u.raw.sg_ranz = sgcnt;
3140 for (i=0; i<sgcnt; ++i,++sl) {
3141 cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
3142#ifdef GDTH_DMA_STATISTICS
3143 ha->dma32_cnt++;
3144#endif
3145 cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
3146 }
3147 }
3148
3149#ifdef GDTH_STATISTICS
3150 if (max_sg < sgcnt) {
3151 max_sg = sgcnt;
3152 TRACE3(("GDT: max_sg = %d\n",sgcnt));
3153 }
3154#endif
3155
cbd5f69b 3156 } else if (scp->request_bufflen) {
1da177e4
LT		 3157 scp->SCp.Status = GDTH_MAP_SINGLE;
3158 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
3159 page = virt_to_page(scp->request_buffer);
3160 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
3161 phys_addr = pci_map_page(ha->pdev,page,offset,
3162 scp->request_bufflen,scp->SCp.Message);
3163 scp->SCp.dma_handle = phys_addr;
3164
3165 if (mode64) {
3166 if (ha->raw_feat & SCATTER_GATHER) {
3167 cmdp->u.raw64.sdata = (ulong64)-1;
3168 cmdp->u.raw64.sg_ranz= 1;
3169 cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
3170 cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
3171 cmdp->u.raw64.sg_lst[1].sg_len = 0;
3172 } else {
3173 cmdp->u.raw64.sdata = phys_addr;
3174 cmdp->u.raw64.sg_ranz= 0;
3175 }
3176 } else {
3177 if (ha->raw_feat & SCATTER_GATHER) {
3178 cmdp->u.raw.sdata = 0xffffffff;
3179 cmdp->u.raw.sg_ranz= 1;
3180 cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
3181 cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
3182 cmdp->u.raw.sg_lst[1].sg_len = 0;
3183 } else {
3184 cmdp->u.raw.sdata = phys_addr;
3185 cmdp->u.raw.sg_ranz= 0;
3186 }
3187 }
3188 }
3189 if (mode64) {
3190 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
3191 cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
3192 cmdp->u.raw64.sg_lst[0].sg_ptr,
3193 cmdp->u.raw64.sg_lst[0].sg_len));
3194 /* evaluate command size */
3195 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
3196 (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
3197 } else {
3198 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
3199 cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
3200 cmdp->u.raw.sg_lst[0].sg_ptr,
3201 cmdp->u.raw.sg_lst[0].sg_len));
3202 /* evaluate command size */
3203 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
3204 (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
3205 }
3206 }
3207 /* check space */
3208 if (ha->cmd_len & 3)
3209 ha->cmd_len += (4 - (ha->cmd_len & 3));
3210
3211 if (ha->cmd_cnt > 0) {
3212 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3213 ha->ic_all_size) {
3214 TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
3215 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3216 return 0;
3217 }
3218 }
3219
3220 /* copy command */
3221 gdth_copy_command(hanum);
3222 return cmd_index;
3223}
3224
3225static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
3226{
3227 register gdth_ha_str *ha;
3228 register gdth_cmd_str *cmdp;
3229 int cmd_index;
3230
3231 ha = HADATA(gdth_ctr_tab[hanum]);
3232 cmdp= ha->pccb;
3233 TRACE2(("gdth_special_cmd(): "));
3234
3235 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
3236 return 0;
3237
3238 memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
3239 cmdp->RequestBuffer = scp;
3240
3241 /* search free command index */
3242 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
3243 TRACE(("GDT: No free command index found\n"));
3244 return 0;
3245 }
3246
3247 /* if it's the first command, set command semaphore */
3248 if (ha->cmd_cnt == 0)
3249 gdth_set_sema0(hanum);
3250
3251 /* evaluate command size, check space */
3252 if (cmdp->OpCode == GDT_IOCTL) {
3253 TRACE2(("IOCTL\n"));
3254 ha->cmd_len =
3255 GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
3256 } else if (cmdp->Service == CACHESERVICE) {
3257 TRACE2(("cache command %d\n",cmdp->OpCode));
3258 if (ha->cache_feat & GDT_64BIT)
3259 ha->cmd_len =
3260 GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
3261 else
3262 ha->cmd_len =
3263 GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
3264 } else if (cmdp->Service == SCSIRAWSERVICE) {
3265 TRACE2(("raw command %d\n",cmdp->OpCode));
3266 if (ha->raw_feat & GDT_64BIT)
3267 ha->cmd_len =
3268 GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
3269 else
3270 ha->cmd_len =
3271 GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
3272 }
3273
3274 if (ha->cmd_len & 3)
3275 ha->cmd_len += (4 - (ha->cmd_len & 3));
3276
3277 if (ha->cmd_cnt > 0) {
3278 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3279 ha->ic_all_size) {
3280 TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
3281 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3282 return 0;
3283 }
3284 }
3285
3286 /* copy command */
3287 gdth_copy_command(hanum);
3288 return cmd_index;
3289}
3290
3291
3292/* Controller event handling functions */
3293static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
3294 ushort idx, gdth_evt_data *evt)
3295{
3296 gdth_evt_str *e;
3297 struct timeval tv;
3298
3299 /* no GDTH_LOCK_HA() ! */
3300 TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
3301 if (source == 0) /* no source -> no event */
3302 return NULL;
3303
3304 if (ebuffer[elastidx].event_source == source &&
3305 ebuffer[elastidx].event_idx == idx &&
3306 ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
3307 !memcmp((char *)&ebuffer[elastidx].event_data.eu,
3308 (char *)&evt->eu, evt->size)) ||
3309 (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
3310 !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
3311 (char *)&evt->event_string)))) {
3312 e = &ebuffer[elastidx];
3313 do_gettimeofday(&tv);
3314 e->last_stamp = tv.tv_sec;
3315 ++e->same_count;
3316 } else {
3317 if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
3318 ++elastidx;
3319 if (elastidx == MAX_EVENTS)
3320 elastidx = 0;
3321 if (elastidx == eoldidx) { /* reached mark ? */
3322 ++eoldidx;
3323 if (eoldidx == MAX_EVENTS)
3324 eoldidx = 0;
3325 }
3326 }
3327 e = &ebuffer[elastidx];
3328 e->event_source = source;
3329 e->event_idx = idx;
3330 do_gettimeofday(&tv);
3331 e->first_stamp = e->last_stamp = tv.tv_sec;
3332 e->same_count = 1;
3333 e->event_data = *evt;
3334 e->application = 0;
3335 }
3336 return e;
3337}
3338
3339static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
3340{
3341 gdth_evt_str *e;
3342 int eindex;
3343 ulong flags;
3344
3345 TRACE2(("gdth_read_event() handle %d\n", handle));
3346 spin_lock_irqsave(&ha->smp_lock, flags);
3347 if (handle == -1)
3348 eindex = eoldidx;
3349 else
3350 eindex = handle;
3351 estr->event_source = 0;
3352
3353 if (eindex >= MAX_EVENTS) {
3354 spin_unlock_irqrestore(&ha->smp_lock, flags);
3355 return eindex;
3356 }
3357 e = &ebuffer[eindex];
3358 if (e->event_source != 0) {
3359 if (eindex != elastidx) {
3360 if (++eindex == MAX_EVENTS)
3361 eindex = 0;
3362 } else {
3363 eindex = -1;
3364 }
3365 memcpy(estr, e, sizeof(gdth_evt_str));
3366 }
3367 spin_unlock_irqrestore(&ha->smp_lock, flags);
3368 return eindex;
3369}
3370
3371static void gdth_readapp_event(gdth_ha_str *ha,
3372 unchar application, gdth_evt_str *estr)
3373{
3374 gdth_evt_str *e;
3375 int eindex;
3376 ulong flags;
3377 unchar found = FALSE;
3378
3379 TRACE2(("gdth_readapp_event() app. %d\n", application));
3380 spin_lock_irqsave(&ha->smp_lock, flags);
3381 eindex = eoldidx;
3382 for (;;) {
3383 e = &ebuffer[eindex];
3384 if (e->event_source == 0)
3385 break;
3386 if ((e->application & application) == 0) {
3387 e->application |= application;
3388 found = TRUE;
3389 break;
3390 }
3391 if (eindex == elastidx)
3392 break;
3393 if (++eindex == MAX_EVENTS)
3394 eindex = 0;
3395 }
3396 if (found)
3397 memcpy(estr, e, sizeof(gdth_evt_str));
3398 else
3399 estr->event_source = 0;
3400 spin_unlock_irqrestore(&ha->smp_lock, flags);
3401}
3402
3403static void gdth_clear_events(void)
3404{
3405 TRACE(("gdth_clear_events()"));
3406
3407 eoldidx = elastidx = 0;
3408 ebuffer[0].event_source = 0;
3409}
3410
3411
3412/* SCSI interface functions */
3413
7d12e780 3414static irqreturn_t gdth_interrupt(int irq,void *dev_id)
1da177e4
LT		 3415{
3416 gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
3417 register gdth_ha_str *ha;
3418 gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
3419 gdt6_dpram_str __iomem *dp6_ptr;
3420 gdt2_dpram_str __iomem *dp2_ptr;
3421 Scsi_Cmnd *scp;
3422 int hanum, rval, i;
3423 unchar IStatus;
3424 ushort Service;
3425 ulong flags = 0;
3426#ifdef INT_COAL
3427 int coalesced = FALSE;
3428 int next = FALSE;
3429 gdth_coal_status *pcs = NULL;
3430 int act_int_coal = 0;
3431#endif
3432
3433 TRACE(("gdth_interrupt() IRQ %d\n",irq));
3434
3435 /* if polling and not from gdth_wait() -> return */
3436 if (gdth_polling) {
3437 if (!gdth_from_wait) {
3438 return IRQ_HANDLED;
3439 }
3440 }
3441
3442 if (!gdth_polling)
cbd5f69b 3443 spin_lock_irqsave(&ha2->smp_lock, flags);
1da177e4
LT		 3444 wait_index = 0;
3445
3446 /* search controller */
3447 if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
3448 /* spurious interrupt */
3449 if (!gdth_polling)
3450 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3451 return IRQ_HANDLED;
3452 }
3453 ha = HADATA(gdth_ctr_tab[hanum]);
3454
3455#ifdef GDTH_STATISTICS
3456 ++act_ints;
3457#endif
3458
3459#ifdef INT_COAL
3460 /* See if the fw is returning coalesced status */
3461 if (IStatus == COALINDEX) {
3462 /* Coalesced status. Setup the initial status
3463 buffer pointer and flags */
3464 pcs = ha->coal_stat;
3465 coalesced = TRUE;
3466 next = TRUE;
3467 }
3468
3469 do {
3470 if (coalesced) {
3471 /* For coalesced requests all status
3472 information is found in the status buffer */
3473 IStatus = (unchar)(pcs->status & 0xff);
3474 }
3475#endif
3476
3477 if (ha->type == GDT_EISA) {
3478 if (IStatus & 0x80) { /* error flag */
3479 IStatus &= ~0x80;
3480 ha->status = inw(ha->bmic + MAILBOXREG+8);
3481 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3482 } else /* no error */
3483 ha->status = S_OK;
3484 ha->info = inl(ha->bmic + MAILBOXREG+12);
3485 ha->service = inw(ha->bmic + MAILBOXREG+10);
3486 ha->info2 = inl(ha->bmic + MAILBOXREG+4);
3487
3488 outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
3489 outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
3490 } else if (ha->type == GDT_ISA) {
3491 dp2_ptr = ha->brd;
3492 if (IStatus & 0x80) { /* error flag */
3493 IStatus &= ~0x80;
3494 ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
3495 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3496 } else /* no error */
3497 ha->status = S_OK;
3498 ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
3499 ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
3500 ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
3501
3502 gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
3503 gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
3504 gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
3505 } else if (ha->type == GDT_PCI) {
3506 dp6_ptr = ha->brd;
3507 if (IStatus & 0x80) { /* error flag */
3508 IStatus &= ~0x80;
3509 ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
3510 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3511 } else /* no error */
3512 ha->status = S_OK;
3513 ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
3514 ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
3515 ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
3516
3517 gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
3518 gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
3519 gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
3520 } else if (ha->type == GDT_PCINEW) {
3521 if (IStatus & 0x80) { /* error flag */
3522 IStatus &= ~0x80;
3523 ha->status = inw(PTR2USHORT(&ha->plx->status));
3524 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3525 } else
3526 ha->status = S_OK;
3527 ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
3528 ha->service = inw(PTR2USHORT(&ha->plx->service));
3529 ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
3530
3531 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
3532 outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
3533 } else if (ha->type == GDT_PCIMPR) {
3534 dp6m_ptr = ha->brd;
3535 if (IStatus & 0x80) { /* error flag */
3536 IStatus &= ~0x80;
3537#ifdef INT_COAL
3538 if (coalesced)
107e716b 3539 ha->status = pcs->ext_status & 0xffff;
1da177e4
LT		 3540 else
3541#endif
3542 ha->status = gdth_readw(&dp6m_ptr->i960r.status);
3543 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3544 } else /* no error */
3545 ha->status = S_OK;
3546#ifdef INT_COAL
3547 /* get information */
3548 if (coalesced) {
3549 ha->info = pcs->info0;
3550 ha->info2 = pcs->info1;
107e716b 3551 ha->service = (pcs->ext_status >> 16) & 0xffff;
1da177e4
LT		 3552 } else
3553#endif
3554 {
3555 ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
3556 ha->service = gdth_readw(&dp6m_ptr->i960r.service);
3557 ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
3558 }
3559 /* event string */
3560 if (IStatus == ASYNCINDEX) {
3561 if (ha->service != SCREENSERVICE &&
3562 (ha->fw_vers & 0xff) >= 0x1a) {
3563 ha->dvr.severity = gdth_readb
3564 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
3565 for (i = 0; i < 256; ++i) {
3566 ha->dvr.event_string[i] = gdth_readb
3567 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
3568 if (ha->dvr.event_string[i] == 0)
3569 break;
3570 }
3571 }
3572 }
3573#ifdef INT_COAL
3574 /* Make sure that non coalesced interrupts get cleared
3575 before being handled by gdth_async_event/gdth_sync_event */
3576 if (!coalesced)
3577#endif
3578 {
3579 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3580 gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
3581 }
3582 } else {
3583 TRACE2(("gdth_interrupt() unknown controller type\n"));
3584 if (!gdth_polling)
3585 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3586 return IRQ_HANDLED;
3587 }
3588
3589 TRACE(("gdth_interrupt() index %d stat %d info %d\n",
3590 IStatus,ha->status,ha->info));
3591
3592 if (gdth_from_wait) {
3593 wait_hanum = hanum;
3594 wait_index = (int)IStatus;
3595 }
3596
3597 if (IStatus == ASYNCINDEX) {
3598 TRACE2(("gdth_interrupt() async. event\n"));
3599 gdth_async_event(hanum);
3600 if (!gdth_polling)
3601 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3602 gdth_next(hanum);
3603 return IRQ_HANDLED;
3604 }
3605
3606 if (IStatus == SPEZINDEX) {
3607 TRACE2(("Service unknown or not initialized !\n"));
3608 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3609 ha->dvr.eu.driver.ionode = hanum;
3610 gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
3611 if (!gdth_polling)
3612 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3613 return IRQ_HANDLED;
3614 }
3615 scp = ha->cmd_tab[IStatus-2].cmnd;
3616 Service = ha->cmd_tab[IStatus-2].service;
3617 ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
3618 if (scp == UNUSED_CMND) {
3619 TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
3620 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3621 ha->dvr.eu.driver.ionode = hanum;
3622 ha->dvr.eu.driver.index = IStatus;
3623 gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
3624 if (!gdth_polling)
3625 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3626 return IRQ_HANDLED;
3627 }
3628 if (scp == INTERNAL_CMND) {
3629 TRACE(("gdth_interrupt() answer to internal command\n"));
3630 if (!gdth_polling)
3631 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3632 return IRQ_HANDLED;
3633 }
3634
3635 TRACE(("gdth_interrupt() sync. status\n"));
3636 rval = gdth_sync_event(hanum,Service,IStatus,scp);
3637 if (!gdth_polling)
3638 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3639 if (rval == 2) {
3640 gdth_putq(hanum,scp,scp->SCp.this_residual);
3641 } else if (rval == 1) {
b8bff2ae 3642 gdth_scsi_done(scp);
1da177e4
LT		 3643 }
3644
3645#ifdef INT_COAL
3646 if (coalesced) {
3647 /* go to the next status in the status buffer */
3648 ++pcs;
3649#ifdef GDTH_STATISTICS
3650 ++act_int_coal;
3651 if (act_int_coal > max_int_coal) {
3652 max_int_coal = act_int_coal;
3653 printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
3654 }
3655#endif
3656 /* see if there is another status */
3657 if (pcs->status == 0)
3658 /* Stop the coalesce loop */
3659 next = FALSE;
3660 }
3661 } while (next);
3662
3663 /* coalescing only for new GDT_PCIMPR controllers available */
3664 if (ha->type == GDT_PCIMPR && coalesced) {
3665 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3666 gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
3667 }
3668#endif
3669
3670 gdth_next(hanum);
3671 return IRQ_HANDLED;
3672}
3673
3674static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
3675{
3676 register gdth_ha_str *ha;
3677 gdth_msg_str *msg;
3678 gdth_cmd_str *cmdp;
3679 unchar b, t;
3680
3681 ha = HADATA(gdth_ctr_tab[hanum]);
3682 cmdp = ha->pccb;
3683 TRACE(("gdth_sync_event() serv %d status %d\n",
3684 service,ha->status));
3685
3686 if (service == SCREENSERVICE) {
3687 msg = ha->pmsg;
3688 TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
3689 msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
3690 if (msg->msg_len > MSGLEN+1)
3691 msg->msg_len = MSGLEN+1;
3692 if (msg->msg_len)
3693 if (!(msg->msg_answer && msg->msg_ext)) {
3694 msg->msg_text[msg->msg_len] = '\0';
3695 printk("%s",msg->msg_text);
3696 }
3697
3698 if (msg->msg_ext && !msg->msg_answer) {
3699 while (gdth_test_busy(hanum))
3700 gdth_delay(0);
3701 cmdp->Service = SCREENSERVICE;
3702 cmdp->RequestBuffer = SCREEN_CMND;
3703 gdth_get_cmd_index(hanum);
3704 gdth_set_sema0(hanum);
3705 cmdp->OpCode = GDT_READ;
3706 cmdp->BoardNode = LOCALBOARD;
3707 cmdp->u.screen.reserved = 0;
3708 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3709 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3710 ha->cmd_offs_dpmem = 0;
3711 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3712 + sizeof(ulong64);
3713 ha->cmd_cnt = 0;
3714 gdth_copy_command(hanum);
3715 gdth_release_event(hanum);
3716 return 0;
3717 }
3718
3719 if (msg->msg_answer && msg->msg_alen) {
3720 /* default answers (getchar() not possible) */
3721 if (msg->msg_alen == 1) {
3722 msg->msg_alen = 0;
3723 msg->msg_len = 1;
3724 msg->msg_text[0] = 0;
3725 } else {
3726 msg->msg_alen -= 2;
3727 msg->msg_len = 2;
3728 msg->msg_text[0] = 1;
3729 msg->msg_text[1] = 0;
3730 }
3731 msg->msg_ext = 0;
3732 msg->msg_answer = 0;
3733 while (gdth_test_busy(hanum))
3734 gdth_delay(0);
3735 cmdp->Service = SCREENSERVICE;
3736 cmdp->RequestBuffer = SCREEN_CMND;
3737 gdth_get_cmd_index(hanum);
3738 gdth_set_sema0(hanum);
3739 cmdp->OpCode = GDT_WRITE;
3740 cmdp->BoardNode = LOCALBOARD;
3741 cmdp->u.screen.reserved = 0;
3742 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3743 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3744 ha->cmd_offs_dpmem = 0;
3745 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3746 + sizeof(ulong64);
3747 ha->cmd_cnt = 0;
3748 gdth_copy_command(hanum);
3749 gdth_release_event(hanum);
3750 return 0;
3751 }
3752 printk("\n");
3753
3754 } else {
3755 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
3756 t = scp->device->id;
3757 if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
3758 ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
3759 }
3760 /* cache or raw service */
3761 if (ha->status == S_BSY) {
3762 TRACE2(("Controller busy -> retry !\n"));
3763 if (scp->SCp.sent_command == GDT_MOUNT)
3764 scp->SCp.sent_command = GDT_CLUST_INFO;
3765 /* retry */
3766 return 2;
3767 }
3768 if (scp->SCp.Status == GDTH_MAP_SG)
3769 pci_unmap_sg(ha->pdev,scp->request_buffer,
3770 scp->use_sg,scp->SCp.Message);
3771 else if (scp->SCp.Status == GDTH_MAP_SINGLE)
3772 pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
3773 scp->request_bufflen,scp->SCp.Message);
3774 if (scp->SCp.buffer) {
3775 dma_addr_t addr;
cbd5f69b 3776 addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
1da177e4 3777 if (scp->host_scribble)
cbd5f69b
LA		 3778 addr += (dma_addr_t)
3779 ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
1da177e4
LT		 3780 pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
3781 }
3782
3783 if (ha->status == S_OK) {
3784 scp->SCp.Status = S_OK;
3785 scp->SCp.Message = ha->info;
3786 if (scp->SCp.sent_command != -1) {
3787 TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
3788 scp->SCp.sent_command));
3789 /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
3790 if (scp->SCp.sent_command == GDT_CLUST_INFO) {
3791 ha->hdr[t].cluster_type = (unchar)ha->info;
3792 if (!(ha->hdr[t].cluster_type &
3793 CLUSTER_MOUNTED)) {
3794 /* NOT MOUNTED -> MOUNT */
3795 scp->SCp.sent_command = GDT_MOUNT;
3796 if (ha->hdr[t].cluster_type &
3797 CLUSTER_RESERVED) {
3798 /* cluster drive RESERVED (on the other node) */
3799 scp->SCp.phase = -2; /* reservation conflict */
3800 }
3801 } else {
3802 scp->SCp.sent_command = -1;
3803 }
3804 } else {
3805 if (scp->SCp.sent_command == GDT_MOUNT) {
3806 ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
3807 ha->hdr[t].media_changed = TRUE;
3808 } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
3809 ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
3810 ha->hdr[t].media_changed = TRUE;
3811 }
3812 scp->SCp.sent_command = -1;
3813 }
3814 /* retry */
3815 scp->SCp.this_residual = HIGH_PRI;
3816 return 2;
3817 } else {
3818 /* RESERVE/RELEASE ? */
3819 if (scp->cmnd[0] == RESERVE) {
3820 ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
3821 } else if (scp->cmnd[0] == RELEASE) {
3822 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3823 }
3824 scp->result = DID_OK << 16;
3825 scp->sense_buffer[0] = 0;
3826 }
3827 } else {
3828 scp->SCp.Status = ha->status;
3829 scp->SCp.Message = ha->info;
3830
3831 if (scp->SCp.sent_command != -1) {
3832 TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
3833 scp->SCp.sent_command, ha->status));
3834 if (scp->SCp.sent_command == GDT_SCAN_START ||
3835 scp->SCp.sent_command == GDT_SCAN_END) {
3836 scp->SCp.sent_command = -1;
3837 /* retry */
3838 scp->SCp.this_residual = HIGH_PRI;
3839 return 2;
3840 }
3841 memset((char*)scp->sense_buffer,0,16);
3842 scp->sense_buffer[0] = 0x70;
3843 scp->sense_buffer[2] = NOT_READY;
3844 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3845 } else if (service == CACHESERVICE) {
3846 if (ha->status == S_CACHE_UNKNOWN &&
3847 (ha->hdr[t].cluster_type &
3848 CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
3849 /* bus reset -> force GDT_CLUST_INFO */
3850 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3851 }
3852 memset((char*)scp->sense_buffer,0,16);
3853 if (ha->status == (ushort)S_CACHE_RESERV) {
3854 scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
3855 } else {
3856 scp->sense_buffer[0] = 0x70;
3857 scp->sense_buffer[2] = NOT_READY;
3858 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3859 }
687d2bc4 3860 if (!IS_GDTH_INTERNAL_CMD(scp)) {
1da177e4
LT		 3861 ha->dvr.size = sizeof(ha->dvr.eu.sync);
3862 ha->dvr.eu.sync.ionode = hanum;
3863 ha->dvr.eu.sync.service = service;
3864 ha->dvr.eu.sync.status = ha->status;
3865 ha->dvr.eu.sync.info = ha->info;
3866 ha->dvr.eu.sync.hostdrive = t;
3867 if (ha->status >= 0x8000)
3868 gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
3869 else
3870 gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
3871 }
3872 } else {
3873 /* sense buffer filled from controller firmware (DMA) */
3874 if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
3875 scp->result = DID_BAD_TARGET << 16;
3876 } else {
3877 scp->result = (DID_OK << 16) | ha->info;
3878 }
3879 }
3880 }
3881 if (!scp->SCp.have_data_in)
3882 scp->SCp.have_data_in++;
3883 else
3884 return 1;
3885 }
3886
3887 return 0;
3888}
3889
3890static char *async_cache_tab[] = {
3891/* 0*/ "\011\000\002\002\002\004\002\006\004"
3892 "GDT HA %u, service %u, async. status %u/%lu unknown",
3893/* 1*/ "\011\000\002\002\002\004\002\006\004"
3894 "GDT HA %u, service %u, async. status %u/%lu unknown",
3895/* 2*/ "\005\000\002\006\004"
3896 "GDT HA %u, Host Drive %lu not ready",
3897/* 3*/ "\005\000\002\006\004"
3898 "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3899/* 4*/ "\005\000\002\006\004"
3900 "GDT HA %u, mirror update on Host Drive %lu failed",
3901/* 5*/ "\005\000\002\006\004"
3902 "GDT HA %u, Mirror Drive %lu failed",
3903/* 6*/ "\005\000\002\006\004"
3904 "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3905/* 7*/ "\005\000\002\006\004"
3906 "GDT HA %u, Host Drive %lu write protected",
3907/* 8*/ "\005\000\002\006\004"
3908 "GDT HA %u, media changed in Host Drive %lu",
3909/* 9*/ "\005\000\002\006\004"
3910 "GDT HA %u, Host Drive %lu is offline",
3911/*10*/ "\005\000\002\006\004"
3912 "GDT HA %u, media change of Mirror Drive %lu",
3913/*11*/ "\005\000\002\006\004"
3914 "GDT HA %u, Mirror Drive %lu is write protected",
3915/*12*/ "\005\000\002\006\004"
3916 "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
3917/*13*/ "\007\000\002\006\002\010\002"
3918 "GDT HA %u, Array Drive %u: Cache Drive %u failed",
3919/*14*/ "\005\000\002\006\002"
3920 "GDT HA %u, Array Drive %u: FAIL state entered",
3921/*15*/ "\005\000\002\006\002"
3922 "GDT HA %u, Array Drive %u: error",
3923/*16*/ "\007\000\002\006\002\010\002"
3924 "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
3925/*17*/ "\005\000\002\006\002"
3926 "GDT HA %u, Array Drive %u: parity build failed",
3927/*18*/ "\005\000\002\006\002"
3928 "GDT HA %u, Array Drive %u: drive rebuild failed",
3929/*19*/ "\005\000\002\010\002"
3930 "GDT HA %u, Test of Hot Fix %u failed",
3931/*20*/ "\005\000\002\006\002"
3932 "GDT HA %u, Array Drive %u: drive build finished successfully",
3933/*21*/ "\005\000\002\006\002"
3934 "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
3935/*22*/ "\007\000\002\006\002\010\002"
3936 "GDT HA %u, Array Drive %u: Hot Fix %u activated",
3937/*23*/ "\005\000\002\006\002"
3938 "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
3939/*24*/ "\005\000\002\010\002"
3940 "GDT HA %u, mirror update on Cache Drive %u completed",
3941/*25*/ "\005\000\002\010\002"
3942 "GDT HA %u, mirror update on Cache Drive %lu failed",
3943/*26*/ "\005\000\002\006\002"
3944 "GDT HA %u, Array Drive %u: drive rebuild started",
3945/*27*/ "\005\000\002\012\001"
3946 "GDT HA %u, Fault bus %u: SHELF OK detected",
3947/*28*/ "\005\000\002\012\001"
3948 "GDT HA %u, Fault bus %u: SHELF not OK detected",
3949/*29*/ "\007\000\002\012\001\013\001"
3950 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
3951/*30*/ "\007\000\002\012\001\013\001"
3952 "GDT HA %u, Fault bus %u, ID %u: new disk detected",
3953/*31*/ "\007\000\002\012\001\013\001"
3954 "GDT HA %u, Fault bus %u, ID %u: old disk detected",
3955/*32*/ "\007\000\002\012\001\013\001"
3956 "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
3957/*33*/ "\007\000\002\012\001\013\001"
3958 "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
3959/*34*/ "\011\000\002\012\001\013\001\006\004"
3960 "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
3961/*35*/ "\007\000\002\012\001\013\001"
3962 "GDT HA %u, Fault bus %u, ID %u: disk write protected",
3963/*36*/ "\007\000\002\012\001\013\001"
3964 "GDT HA %u, Fault bus %u, ID %u: disk not available",
3965/*37*/ "\007\000\002\012\001\006\004"
3966 "GDT HA %u, Fault bus %u: swap detected (%lu)",
3967/*38*/ "\007\000\002\012\001\013\001"
3968 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
3969/*39*/ "\007\000\002\012\001\013\001"
3970 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
3971/*40*/ "\007\000\002\012\001\013\001"
3972 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
3973/*41*/ "\007\000\002\012\001\013\001"
3974 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
3975/*42*/ "\005\000\002\006\002"
3976 "GDT HA %u, Array Drive %u: drive build started",
3977/*43*/ "\003\000\002"
3978 "GDT HA %u, DRAM parity error detected",
3979/*44*/ "\005\000\002\006\002"
3980 "GDT HA %u, Mirror Drive %u: update started",
3981/*45*/ "\007\000\002\006\002\010\002"
3982 "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
3983/*46*/ "\005\000\002\006\002"
3984 "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
3985/*47*/ "\005\000\002\006\002"
3986 "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
3987/*48*/ "\005\000\002\006\002"
3988 "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
3989/*49*/ "\005\000\002\006\002"
3990 "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
3991/*50*/ "\007\000\002\012\001\013\001"
3992 "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
3993/*51*/ "\005\000\002\006\002"
3994 "GDT HA %u, Array Drive %u: expand started",
3995/*52*/ "\005\000\002\006\002"
3996 "GDT HA %u, Array Drive %u: expand finished successfully",
3997/*53*/ "\005\000\002\006\002"
3998 "GDT HA %u, Array Drive %u: expand failed",
3999/*54*/ "\003\000\002"
4000 "GDT HA %u, CPU temperature critical",
4001/*55*/ "\003\000\002"
4002 "GDT HA %u, CPU temperature OK",
4003/*56*/ "\005\000\002\006\004"
4004 "GDT HA %u, Host drive %lu created",
4005/*57*/ "\005\000\002\006\002"
4006 "GDT HA %u, Array Drive %u: expand restarted",
4007/*58*/ "\005\000\002\006\002"
4008 "GDT HA %u, Array Drive %u: expand stopped",
4009/*59*/ "\005\000\002\010\002"
4010 "GDT HA %u, Mirror Drive %u: drive build quited",
4011/*60*/ "\005\000\002\006\002"
4012 "GDT HA %u, Array Drive %u: parity build quited",
4013/*61*/ "\005\000\002\006\002"
4014 "GDT HA %u, Array Drive %u: drive rebuild quited",
4015/*62*/ "\005\000\002\006\002"
4016 "GDT HA %u, Array Drive %u: parity verify started",
4017/*63*/ "\005\000\002\006\002"
4018 "GDT HA %u, Array Drive %u: parity verify done",
4019/*64*/ "\005\000\002\006\002"
4020 "GDT HA %u, Array Drive %u: parity verify failed",
4021/*65*/ "\005\000\002\006\002"
4022 "GDT HA %u, Array Drive %u: parity error detected",
4023/*66*/ "\005\000\002\006\002"
4024 "GDT HA %u, Array Drive %u: parity verify quited",
4025/*67*/ "\005\000\002\006\002"
4026 "GDT HA %u, Host Drive %u reserved",
4027/*68*/ "\005\000\002\006\002"
4028 "GDT HA %u, Host Drive %u mounted and released",
4029/*69*/ "\005\000\002\006\002"
4030 "GDT HA %u, Host Drive %u released",
4031/*70*/ "\003\000\002"
4032 "GDT HA %u, DRAM error detected and corrected with ECC",
4033/*71*/ "\003\000\002"
4034 "GDT HA %u, Uncorrectable DRAM error detected with ECC",
4035/*72*/ "\011\000\002\012\001\013\001\014\001"
4036 "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
4037/*73*/ "\005\000\002\006\002"
4038 "GDT HA %u, Host drive %u resetted locally",
4039/*74*/ "\005\000\002\006\002"
4040 "GDT HA %u, Host drive %u resetted remotely",
4041/*75*/ "\003\000\002"
4042 "GDT HA %u, async. status 75 unknown",
4043};
4044
4045
4046static int gdth_async_event(int hanum)
4047{
4048 gdth_ha_str *ha;
4049 gdth_cmd_str *cmdp;
4050 int cmd_index;
4051
4052 ha = HADATA(gdth_ctr_tab[hanum]);
4053 cmdp= ha->pccb;
4054 TRACE2(("gdth_async_event() ha %d serv %d\n",
4055 hanum,ha->service));
4056
4057 if (ha->service == SCREENSERVICE) {
4058 if (ha->status == MSG_REQUEST) {
4059 while (gdth_test_busy(hanum))
4060 gdth_delay(0);
4061 cmdp->Service = SCREENSERVICE;
4062 cmdp->RequestBuffer = SCREEN_CMND;
4063 cmd_index = gdth_get_cmd_index(hanum);
4064 gdth_set_sema0(hanum);
4065 cmdp->OpCode = GDT_READ;
4066 cmdp->BoardNode = LOCALBOARD;
4067 cmdp->u.screen.reserved = 0;
4068 cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
4069 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
4070 ha->cmd_offs_dpmem = 0;
4071 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
4072 + sizeof(ulong64);
4073 ha->cmd_cnt = 0;
4074 gdth_copy_command(hanum);
4075 if (ha->type == GDT_EISA)
4076 printk("[EISA slot %d] ",(ushort)ha->brd_phys);
4077 else if (ha->type == GDT_ISA)
4078 printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
4079 else
4080 printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
4081 (ushort)((ha->brd_phys>>3)&0x1f));
4082 gdth_release_event(hanum);
4083 }
4084
4085 } else {
4086 if (ha->type == GDT_PCIMPR &&
4087 (ha->fw_vers & 0xff) >= 0x1a) {
4088 ha->dvr.size = 0;
4089 ha->dvr.eu.async.ionode = hanum;
4090 ha->dvr.eu.async.status = ha->status;
4091 /* severity and event_string already set! */
4092 } else {
4093 ha->dvr.size = sizeof(ha->dvr.eu.async);
4094 ha->dvr.eu.async.ionode = hanum;
4095 ha->dvr.eu.async.service = ha->service;
4096 ha->dvr.eu.async.status = ha->status;
4097 ha->dvr.eu.async.info = ha->info;
4098 *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
4099 }
4100 gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
4101 gdth_log_event( &ha->dvr, NULL );
4102
4103 /* new host drive from expand? */
4104 if (ha->service == CACHESERVICE && ha->status == 56) {
4105 TRACE2(("gdth_async_event(): new host drive %d created\n",
4106 (ushort)ha->info));
4107 /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
4108 }
4109 }
4110 return 1;
4111}
4112
4113static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
4114{
4115 gdth_stackframe stack;
4116 char *f = NULL;
4117 int i,j;
4118
4119 TRACE2(("gdth_log_event()\n"));
4120 if (dvr->size == 0) {
4121 if (buffer == NULL) {
4122 printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
4123 } else {
4124 sprintf(buffer,"Adapter %d: %s\n",
4125 dvr->eu.async.ionode,dvr->event_string);
4126 }
4127 } else if (dvr->eu.async.service == CACHESERVICE &&
4128 INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
4129 TRACE2(("GDT: Async. event cache service, event no.: %d\n",
4130 dvr->eu.async.status));
4131
4132 f = async_cache_tab[dvr->eu.async.status];
4133
4134 /* i: parameter to push, j: stack element to fill */
4135 for (j=0,i=1; i < f[0]; i+=2) {
4136 switch (f[i+1]) {
4137 case 4:
4138 stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
4139 break;
4140 case 2:
4141 stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
4142 break;
4143 case 1:
4144 stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
4145 break;
4146 default:
4147 break;
4148 }
4149 }
4150
4151 if (buffer == NULL) {
4152 printk(&f[(int)f[0]],stack);
4153 printk("\n");
4154 } else {
4155 sprintf(buffer,&f[(int)f[0]],stack);
4156 }
4157
4158 } else {
4159 if (buffer == NULL) {
4160 printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
4161 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
4162 } else {
4163 sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
4164 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
4165 }
4166 }
4167}
4168
4169#ifdef GDTH_STATISTICS
8e879041 4170static void gdth_timeout(ulong data)
1da177e4
LT		 4171{
4172 ulong32 i;
4173 Scsi_Cmnd *nscp;
4174 gdth_ha_str *ha;
4175 ulong flags;
4176 int hanum = 0;
4177
4178 ha = HADATA(gdth_ctr_tab[hanum]);
4179 spin_lock_irqsave(&ha->smp_lock, flags);
4180
4181 for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
4182 if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
4183 ++act_stats;
4184
4185 for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
4186 ++act_rq;
4187
4188 TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
4189 act_ints, act_ios, act_stats, act_rq));
4190 act_ints = act_ios = 0;
4191
4192 gdth_timer.expires = jiffies + 30 * HZ;
4193 add_timer(&gdth_timer);
4194 spin_unlock_irqrestore(&ha->smp_lock, flags);
4195}
4196#endif
4197
8e879041 4198static void __init internal_setup(char *str,int *ints)
1da177e4
LT		 4199{
4200 int i, argc;
4201 char *cur_str, *argv;
4202
4203 TRACE2(("internal_setup() str %s ints[0] %d\n",
4204 str ? str:"NULL", ints ? ints[0]:0));
4205
4206 /* read irq[] from ints[] */
4207 if (ints) {
4208 argc = ints[0];
4209 if (argc > 0) {
4210 if (argc > MAXHA)
4211 argc = MAXHA;
4212 for (i = 0; i < argc; ++i)
4213 irq[i] = ints[i+1];
4214 }
4215 }
4216
4217 /* analyse string */
4218 argv = str;
4219 while (argv && (cur_str = strchr(argv, ':'))) {
4220 int val = 0, c = *++cur_str;
4221
4222 if (c == 'n' || c == 'N')
4223 val = 0;
4224 else if (c == 'y' || c == 'Y')
4225 val = 1;
4226 else
4227 val = (int)simple_strtoul(cur_str, NULL, 0);
4228
4229 if (!strncmp(argv, "disable:", 8))
4230 disable = val;
4231 else if (!strncmp(argv, "reserve_mode:", 13))
4232 reserve_mode = val;
4233 else if (!strncmp(argv, "reverse_scan:", 13))
4234 reverse_scan = val;
4235 else if (!strncmp(argv, "hdr_channel:", 12))
4236 hdr_channel = val;
4237 else if (!strncmp(argv, "max_ids:", 8))
4238 max_ids = val;
4239 else if (!strncmp(argv, "rescan:", 7))
4240 rescan = val;
4241 else if (!strncmp(argv, "virt_ctr:", 9))
4242 virt_ctr = val;
4243 else if (!strncmp(argv, "shared_access:", 14))
4244 shared_access = val;
4245 else if (!strncmp(argv, "probe_eisa_isa:", 15))
4246 probe_eisa_isa = val;
4247 else if (!strncmp(argv, "reserve_list:", 13)) {
4248 reserve_list[0] = val;
4249 for (i = 1; i < MAX_RES_ARGS; i++) {
4250 cur_str = strchr(cur_str, ',');
4251 if (!cur_str)
4252 break;
4253 if (!isdigit((int)*++cur_str)) {
4254 --cur_str;
4255 break;
4256 }
4257 reserve_list[i] =
4258 (int)simple_strtoul(cur_str, NULL, 0);
4259 }
4260 if (!cur_str)
4261 break;
4262 argv = ++cur_str;
4263 continue;
4264 }
4265
4266 if ((argv = strchr(argv, ',')))
4267 ++argv;
4268 }
4269}
4270
4271int __init option_setup(char *str)
4272{
4273 int ints[MAXHA];
4274 char *cur = str;
4275 int i = 1;
4276
4277 TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
4278
4279 while (cur && isdigit(*cur) && i <= MAXHA) {
4280 ints[i++] = simple_strtoul(cur, NULL, 0);
4281 if ((cur = strchr(cur, ',')) != NULL) cur++;
4282 }
4283
4284 ints[0] = i - 1;
4285 internal_setup(cur, ints);
4286 return 1;
4287}
4288
aed91cb5 4289
cbd5f69b 4290#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
d0be4a7d 4291static int __init gdth_detect(struct scsi_host_template *shtp)
cbd5f69b
LA		 4292#else
4293static int __init gdth_detect(Scsi_Host_Template *shtp)
4294#endif
1da177e4
LT		 4295{
4296 struct Scsi_Host *shp;
4297 gdth_pci_str pcistr[MAXHA];
4298 gdth_ha_str *ha;
1da177e4
LT		 4299 ushort eisa_slot;
4300 int i,hanum,cnt,ctr,err;
4301 unchar b;
4302
4303
4304#ifdef DEBUG_GDTH
4305 printk("GDT: This driver contains debugging information !! Trace level = %d\n",
4306 DebugState);
4307 printk(" Destination of debugging information: ");
4308#ifdef __SERIAL__
4309#ifdef __COM2__
4310 printk("Serial port COM2\n");
4311#else
4312 printk("Serial port COM1\n");
4313#endif
4314#else
4315 printk("Console\n");
4316#endif
4317 gdth_delay(3000);
4318#endif
4319
4320 TRACE(("gdth_detect()\n"));
4321
4322 if (disable) {
4323 printk("GDT-HA: Controller driver disabled from command line !\n");
4324 return 0;
4325 }
4326
cbd5f69b 4327 printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR);
1da177e4
LT		 4328 /* initializations */
4329 gdth_polling = TRUE; b = 0;
4330 gdth_clear_events();
4331
4332 /* As default we do not probe for EISA or ISA controllers */
4333 if (probe_eisa_isa) {
4334 /* scanning for controllers, at first: ISA controller */
aed91cb5
CH		 4335#ifdef CONFIG_ISA
4336 ulong32 isa_bios;
4337 for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
4338 isa_bios += 0x8000UL) {
4339 if (gdth_ctr_count >= MAXHA)
1da177e4 4340 break;
aed91cb5 4341 gdth_isa_probe_one(shtp, isa_bios);
1da177e4 4342 }
aed91cb5 4343#endif
1da177e4 4344
1da177e4
LT		 4345 for (eisa_slot=0x1000; eisa_slot<=0x8000; eisa_slot+=0x1000) {
4346 dma_addr_t scratch_dma_handle;
4347 scratch_dma_handle = 0;
4348
4349 if (gdth_ctr_count >= MAXHA)
4350 break;
4351 if (gdth_search_eisa(eisa_slot)) { /* controller found */
4352 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4353 if (shp == NULL)
4354 continue;
4355
4356 ha = HADATA(shp);
4357 if (!gdth_init_eisa(eisa_slot,ha)) {
4358 scsi_unregister(shp);
4359 continue;
4360 }
4361 /* controller found and initialized */
4362 printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
4363 eisa_slot>>12,ha->irq);
4364
1d6f359a 4365 if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
1da177e4
LT		 4366 printk("GDT-EISA: Unable to allocate IRQ\n");
4367 scsi_unregister(shp);
4368 continue;
4369 }
4370 shp->unchecked_isa_dma = 0;
4371 shp->irq = ha->irq;
4372 shp->dma_channel = 0xff;
4373 hanum = gdth_ctr_count;
4374 gdth_ctr_tab[gdth_ctr_count++] = shp;
4375 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4376
4377 NUMDATA(shp)->hanum = (ushort)hanum;
4378 NUMDATA(shp)->busnum= 0;
4379 TRACE2(("EISA detect Bus 0: hanum %d\n",
4380 NUMDATA(shp)->hanum));
4381
4382 ha->pccb = CMDDATA(shp);
4383 ha->ccb_phys = 0L;
4384
4385 ha->pdev = NULL;
4386 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4387 &scratch_dma_handle);
4388 ha->scratch_phys = scratch_dma_handle;
4389 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4390 &scratch_dma_handle);
4391 ha->msg_phys = scratch_dma_handle;
4392#ifdef INT_COAL
4393 ha->coal_stat = (gdth_coal_status *)
4394 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4395 MAXOFFSETS, &scratch_dma_handle);
4396 ha->coal_stat_phys = scratch_dma_handle;
4397#endif
4398 ha->ccb_phys =
4399 pci_map_single(ha->pdev,ha->pccb,
4400 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4401 ha->scratch_busy = FALSE;
4402 ha->req_first = NULL;
4403 ha->tid_cnt = MAX_HDRIVES;
4404 if (max_ids > 0 && max_ids < ha->tid_cnt)
4405 ha->tid_cnt = max_ids;
4406 for (i=0; i<GDTH_MAXCMDS; ++i)
4407 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4408 ha->scan_mode = rescan ? 0x10 : 0;
4409
4410 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4411 !gdth_search_drives(hanum)) {
4412 printk("GDT-EISA: Error during device scan\n");
4413 --gdth_ctr_count;
4414 --gdth_ctr_vcount;
4415#ifdef INT_COAL
4416 if (ha->coal_stat)
4417 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4418 MAXOFFSETS, ha->coal_stat,
4419 ha->coal_stat_phys);
4420#endif
4421 if (ha->pscratch)
4422 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4423 ha->pscratch, ha->scratch_phys);
4424 if (ha->pmsg)
4425 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4426 ha->pmsg, ha->msg_phys);
4427 if (ha->ccb_phys)
4428 pci_unmap_single(ha->pdev,ha->ccb_phys,
4429 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4430 free_irq(ha->irq,ha);
4431 scsi_unregister(shp);
4432 continue;
4433 }
4434 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4435 hdr_channel = ha->bus_cnt;
4436 ha->virt_bus = hdr_channel;
4437
4438#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
4439 LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
4440 shp->highmem_io = 0;
4441#endif
4442 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4443 shp->max_cmd_len = 16;
4444
4445 shp->max_id = ha->tid_cnt;
4446 shp->max_lun = MAXLUN;
4447 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4448 if (virt_ctr) {
4449 virt_ctr = 1;
4450 /* register addit. SCSI channels as virtual controllers */
4451 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4452 shp = scsi_register(shtp,sizeof(gdth_num_str));
4453 shp->unchecked_isa_dma = 0;
4454 shp->irq = ha->irq;
4455 shp->dma_channel = 0xff;
4456 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4457 NUMDATA(shp)->hanum = (ushort)hanum;
4458 NUMDATA(shp)->busnum = b;
4459 }
4460 }
4461
4462 spin_lock_init(&ha->smp_lock);
4463 gdth_enable_int(hanum);
4464 }
4465 }
4466 }
4467
4468 /* scanning for PCI controllers */
4469 cnt = gdth_search_pci(pcistr);
4470 printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
4471 gdth_sort_pci(pcistr,cnt);
4472 for (ctr = 0; ctr < cnt; ++ctr) {
4473 dma_addr_t scratch_dma_handle;
4474 scratch_dma_handle = 0;
4475
4476 if (gdth_ctr_count >= MAXHA)
4477 break;
4478 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4479 if (shp == NULL)
4480 continue;
4481
4482 ha = HADATA(shp);
4483 if (!gdth_init_pci(&pcistr[ctr],ha)) {
4484 scsi_unregister(shp);
4485 continue;
4486 }
4487 /* controller found and initialized */
4488 printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
8e9a8a0d
JG		 4489 pcistr[ctr].pdev->bus->number,
4490 PCI_SLOT(pcistr[ctr].pdev->devfn), ha->irq);
1da177e4
LT		 4491
4492 if (request_irq(ha->irq, gdth_interrupt,
1d6f359a 4493 IRQF_DISABLED|IRQF_SHARED, "gdth", ha))
1da177e4
LT		 4494 {
4495 printk("GDT-PCI: Unable to allocate IRQ\n");
4496 scsi_unregister(shp);
4497 continue;
4498 }
4499 shp->unchecked_isa_dma = 0;
4500 shp->irq = ha->irq;
4501 shp->dma_channel = 0xff;
4502 hanum = gdth_ctr_count;
4503 gdth_ctr_tab[gdth_ctr_count++] = shp;
4504 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4505
4506 NUMDATA(shp)->hanum = (ushort)hanum;
4507 NUMDATA(shp)->busnum= 0;
4508
4509 ha->pccb = CMDDATA(shp);
4510 ha->ccb_phys = 0L;
4511
4512 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4513 &scratch_dma_handle);
4514 ha->scratch_phys = scratch_dma_handle;
4515 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4516 &scratch_dma_handle);
4517 ha->msg_phys = scratch_dma_handle;
4518#ifdef INT_COAL
4519 ha->coal_stat = (gdth_coal_status *)
4520 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4521 MAXOFFSETS, &scratch_dma_handle);
4522 ha->coal_stat_phys = scratch_dma_handle;
4523#endif
4524 ha->scratch_busy = FALSE;
4525 ha->req_first = NULL;
8e9a8a0d 4526 ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
1da177e4
LT		 4527 if (max_ids > 0 && max_ids < ha->tid_cnt)
4528 ha->tid_cnt = max_ids;
4529 for (i=0; i<GDTH_MAXCMDS; ++i)
4530 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4531 ha->scan_mode = rescan ? 0x10 : 0;
4532
4533 err = FALSE;
4534 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4535 !gdth_search_drives(hanum)) {
4536 err = TRUE;
4537 } else {
4538 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4539 hdr_channel = ha->bus_cnt;
4540 ha->virt_bus = hdr_channel;
4541
4542
12413197 4543#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
1da177e4
LT		 4544 scsi_set_pci_device(shp, pcistr[ctr].pdev);
4545#endif
4546 if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat &GDT_64BIT)||
4547 /* 64-bit DMA only supported from FW >= x.43 */
4548 (!ha->dma64_support)) {
910638ae 4549 if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 4550 printk(KERN_WARNING "GDT-PCI %d: Unable to set 32-bit DMA\n", hanum);
4551 err = TRUE;
4552 }
4553 } else {
4554 shp->max_cmd_len = 16;
910638ae 4555 if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
1da177e4 4556 printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
910638ae 4557 } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 4558 printk(KERN_WARNING "GDT-PCI %d: Unable to set 64/32-bit DMA\n", hanum);
4559 err = TRUE;
4560 }
4561 }
4562 }
4563
4564 if (err) {
4565 printk("GDT-PCI %d: Error during device scan\n", hanum);
4566 --gdth_ctr_count;
4567 --gdth_ctr_vcount;
4568#ifdef INT_COAL
4569 if (ha->coal_stat)
4570 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4571 MAXOFFSETS, ha->coal_stat,
4572 ha->coal_stat_phys);
4573#endif
4574 if (ha->pscratch)
4575 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4576 ha->pscratch, ha->scratch_phys);
4577 if (ha->pmsg)
4578 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4579 ha->pmsg, ha->msg_phys);
4580 free_irq(ha->irq,ha);
4581 scsi_unregister(shp);
4582 continue;
4583 }
4584
4585 shp->max_id = ha->tid_cnt;
4586 shp->max_lun = MAXLUN;
4587 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4588 if (virt_ctr) {
4589 virt_ctr = 1;
4590 /* register addit. SCSI channels as virtual controllers */
4591 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4592 shp = scsi_register(shtp,sizeof(gdth_num_str));
4593 shp->unchecked_isa_dma = 0;
4594 shp->irq = ha->irq;
4595 shp->dma_channel = 0xff;
4596 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4597 NUMDATA(shp)->hanum = (ushort)hanum;
4598 NUMDATA(shp)->busnum = b;
4599 }
4600 }
4601
4602 spin_lock_init(&ha->smp_lock);
4603 gdth_enable_int(hanum);
4604 }
4605
4606 TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
4607 if (gdth_ctr_count > 0) {
4608#ifdef GDTH_STATISTICS
4609 TRACE2(("gdth_detect(): Initializing timer !\n"));
4610 init_timer(&gdth_timer);
4611 gdth_timer.expires = jiffies + HZ;
4612 gdth_timer.data = 0L;
4613 gdth_timer.function = gdth_timeout;
4614 add_timer(&gdth_timer);
4615#endif
4616 major = register_chrdev(0,"gdth",&gdth_fops);
e041c683 4617 notifier_disabled = 0;
1da177e4
LT		 4618 register_reboot_notifier(&gdth_notifier);
4619 }
4620 gdth_polling = FALSE;
4621 return gdth_ctr_vcount;
4622}
4623
8e879041 4624static int gdth_release(struct Scsi_Host *shp)
1da177e4
LT		 4625{
4626 int hanum;
4627 gdth_ha_str *ha;
4628
4629 TRACE2(("gdth_release()\n"));
4630 if (NUMDATA(shp)->busnum == 0) {
4631 hanum = NUMDATA(shp)->hanum;
4632 ha = HADATA(gdth_ctr_tab[hanum]);
4633 if (ha->sdev) {
4634 scsi_free_host_dev(ha->sdev);
4635 ha->sdev = NULL;
4636 }
4637 gdth_flush(hanum);
4638
4639 if (shp->irq) {
4640 free_irq(shp->irq,ha);
4641 }
aed91cb5 4642#ifdef CONFIG_ISA
1da177e4
LT		 4643 if (shp->dma_channel != 0xff) {
4644 free_dma(shp->dma_channel);
4645 }
4646#endif
4647#ifdef INT_COAL
4648 if (ha->coal_stat)
4649 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4650 MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
4651#endif
4652 if (ha->pscratch)
4653 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4654 ha->pscratch, ha->scratch_phys);
4655 if (ha->pmsg)
4656 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4657 ha->pmsg, ha->msg_phys);
4658 if (ha->ccb_phys)
4659 pci_unmap_single(ha->pdev,ha->ccb_phys,
4660 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4661 gdth_ctr_released++;
4662 TRACE2(("gdth_release(): HA %d of %d\n",
4663 gdth_ctr_released, gdth_ctr_count));
4664
4665 if (gdth_ctr_released == gdth_ctr_count) {
4666#ifdef GDTH_STATISTICS
4667 del_timer(&gdth_timer);
4668#endif
4669 unregister_chrdev(major,"gdth");
4670 unregister_reboot_notifier(&gdth_notifier);
4671 }
4672 }
4673
4674 scsi_unregister(shp);
4675 return 0;
4676}
4677
4678
4679static const char *gdth_ctr_name(int hanum)
4680{
4681 gdth_ha_str *ha;
4682
4683 TRACE2(("gdth_ctr_name()\n"));
4684
4685 ha = HADATA(gdth_ctr_tab[hanum]);
4686
4687 if (ha->type == GDT_EISA) {
4688 switch (ha->stype) {
4689 case GDT3_ID:
4690 return("GDT3000/3020");
4691 case GDT3A_ID:
4692 return("GDT3000A/3020A/3050A");
4693 case GDT3B_ID:
4694 return("GDT3000B/3010A");
4695 }
4696 } else if (ha->type == GDT_ISA) {
4697 return("GDT2000/2020");
4698 } else if (ha->type == GDT_PCI) {
8e9a8a0d 4699 switch (ha->pdev->device) {
1da177e4
LT		 4700 case PCI_DEVICE_ID_VORTEX_GDT60x0:
4701 return("GDT6000/6020/6050");
4702 case PCI_DEVICE_ID_VORTEX_GDT6000B:
4703 return("GDT6000B/6010");
4704 }
4705 }
4706 /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
4707
4708 return("");
4709}
4710
8e879041 4711static const char *gdth_info(struct Scsi_Host *shp)
1da177e4
LT		 4712{
4713 int hanum;
4714 gdth_ha_str *ha;
4715
4716 TRACE2(("gdth_info()\n"));
4717 hanum = NUMDATA(shp)->hanum;
4718 ha = HADATA(gdth_ctr_tab[hanum]);
4719
4720 return ((const char *)ha->binfo.type_string);
4721}
4722
8e879041 4723static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
1da177e4
LT		 4724{
4725 int i, hanum;
4726 gdth_ha_str *ha;
4727 ulong flags;
4728 Scsi_Cmnd *cmnd;
4729 unchar b;
4730
4731 TRACE2(("gdth_eh_bus_reset()\n"));
4732
4733 hanum = NUMDATA(scp->device->host)->hanum;
4734 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
4735 ha = HADATA(gdth_ctr_tab[hanum]);
4736
4737 /* clear command tab */
4738 spin_lock_irqsave(&ha->smp_lock, flags);
4739 for (i = 0; i < GDTH_MAXCMDS; ++i) {
4740 cmnd = ha->cmd_tab[i].cmnd;
4741 if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
4742 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4743 }
4744 spin_unlock_irqrestore(&ha->smp_lock, flags);
4745
4746 if (b == ha->virt_bus) {
4747 /* host drives */
4748 for (i = 0; i < MAX_HDRIVES; ++i) {
4749 if (ha->hdr[i].present) {
4750 spin_lock_irqsave(&ha->smp_lock, flags);
4751 gdth_polling = TRUE;
4752 while (gdth_test_busy(hanum))
4753 gdth_delay(0);
4754 if (gdth_internal_cmd(hanum, CACHESERVICE,
4755 GDT_CLUST_RESET, i, 0, 0))
4756 ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
4757 gdth_polling = FALSE;
4758 spin_unlock_irqrestore(&ha->smp_lock, flags);
4759 }
4760 }
4761 } else {
4762 /* raw devices */
4763 spin_lock_irqsave(&ha->smp_lock, flags);
4764 for (i = 0; i < MAXID; ++i)
4765 ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
4766 gdth_polling = TRUE;
4767 while (gdth_test_busy(hanum))
4768 gdth_delay(0);
4769 gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
4770 BUS_L2P(ha,b), 0, 0);
4771 gdth_polling = FALSE;
cbd5f69b 4772 spin_unlock_irqrestore(&ha->smp_lock, flags);
1da177e4
LT		 4773 }
4774 return SUCCESS;
4775}
4776
1da177e4 4777#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
8e879041 4778static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
1da177e4 4779#else
8e879041 4780static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip)
1da177e4
LT		 4781#endif
4782{
4783 unchar b, t;
4784 int hanum;
4785 gdth_ha_str *ha;
4786 struct scsi_device *sd;
4787 unsigned capacity;
4788
4789#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4790 sd = sdev;
4791 capacity = cap;
4792#else
4793 sd = disk->device;
4794 capacity = disk->capacity;
4795#endif
4796 hanum = NUMDATA(sd->host)->hanum;
4797 b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
4798 t = sd->id;
4799 TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
4800 ha = HADATA(gdth_ctr_tab[hanum]);
4801
4802 if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
4803 /* raw device or host drive without mapping information */
4804 TRACE2(("Evaluate mapping\n"));
4805 gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
4806 } else {
4807 ip[0] = ha->hdr[t].heads;
4808 ip[1] = ha->hdr[t].secs;
4809 ip[2] = capacity / ip[0] / ip[1];
4810 }
4811
4812 TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
4813 ip[0],ip[1],ip[2]));
4814 return 0;
4815}
4816
4817
b8bff2ae
MW		 4818static int gdth_queuecommand(struct scsi_cmnd *scp,
4819 void (*done)(struct scsi_cmnd *))
1da177e4
LT		 4820{
4821 int hanum;
4822 int priority;
4823
4824 TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
4825
b8bff2ae 4826 scp->scsi_done = done;
1da177e4
LT		 4827 scp->SCp.have_data_in = 1;
4828 scp->SCp.phase = -1;
4829 scp->SCp.sent_command = -1;
4830 scp->SCp.Status = GDTH_MAP_NONE;
4831 scp->SCp.buffer = (struct scatterlist *)NULL;
4832
4833 hanum = NUMDATA(scp->device->host)->hanum;
4834#ifdef GDTH_STATISTICS
4835 ++act_ios;
4836#endif
4837
4838 priority = DEFAULT_PRI;
687d2bc4 4839 if (IS_GDTH_INTERNAL_CMD(scp))
1da177e4 4840 priority = scp->SCp.this_residual;
cbd5f69b
LA		 4841 else
4842 gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
4843
1da177e4
LT		 4844 gdth_putq( hanum, scp, priority );
4845 gdth_next( hanum );
4846 return 0;
4847}
4848
4849
4850static int gdth_open(struct inode *inode, struct file *filep)
4851{
4852 gdth_ha_str *ha;
4853 int i;
4854
4855 for (i = 0; i < gdth_ctr_count; i++) {
4856 ha = HADATA(gdth_ctr_tab[i]);
4857 if (!ha->sdev)
4858 ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
4859 }
4860
4861 TRACE(("gdth_open()\n"));
4862 return 0;
4863}
4864
4865static int gdth_close(struct inode *inode, struct file *filep)
4866{
4867 TRACE(("gdth_close()\n"));
4868 return 0;
4869}
4870
4871static int ioc_event(void __user *arg)
4872{
4873 gdth_ioctl_event evt;
4874 gdth_ha_str *ha;
4875 ulong flags;
4876
4877 if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
4878 evt.ionode >= gdth_ctr_count)
4879 return -EFAULT;
4880 ha = HADATA(gdth_ctr_tab[evt.ionode]);
4881
4882 if (evt.erase == 0xff) {
4883 if (evt.event.event_source == ES_TEST)
4884 evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
4885 else if (evt.event.event_source == ES_DRIVER)
4886 evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
4887 else if (evt.event.event_source == ES_SYNC)
4888 evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
4889 else
4890 evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
4891 spin_lock_irqsave(&ha->smp_lock, flags);
4892 gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
4893 &evt.event.event_data);
4894 spin_unlock_irqrestore(&ha->smp_lock, flags);
4895 } else if (evt.erase == 0xfe) {
4896 gdth_clear_events();
4897 } else if (evt.erase == 0) {
4898 evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
4899 } else {
4900 gdth_readapp_event(ha, evt.erase, &evt.event);
4901 }
4902 if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
4903 return -EFAULT;
4904 return 0;
4905}
4906
4907static int ioc_lockdrv(void __user *arg)
4908{
4909 gdth_ioctl_lockdrv ldrv;
4910 unchar i, j;
4911 ulong flags;
4912 gdth_ha_str *ha;
4913
4914 if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
4915 ldrv.ionode >= gdth_ctr_count)
4916 return -EFAULT;
4917 ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
4918
4919 for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
4920 j = ldrv.drives[i];
4921 if (j >= MAX_HDRIVES || !ha->hdr[j].present)
4922 continue;
4923 if (ldrv.lock) {
4924 spin_lock_irqsave(&ha->smp_lock, flags);
4925 ha->hdr[j].lock = 1;
4926 spin_unlock_irqrestore(&ha->smp_lock, flags);
4927 gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
4928 gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
4929 } else {
4930 spin_lock_irqsave(&ha->smp_lock, flags);
4931 ha->hdr[j].lock = 0;
4932 spin_unlock_irqrestore(&ha->smp_lock, flags);
4933 gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
4934 gdth_next(ldrv.ionode);
4935 }
4936 }
4937 return 0;
4938}
4939
4940static int ioc_resetdrv(void __user *arg, char *cmnd)
4941{
4942 gdth_ioctl_reset res;
4943 gdth_cmd_str cmd;
4944 int hanum;
4945 gdth_ha_str *ha;
cbd5f69b 4946 int rval;
1da177e4
LT		 4947
4948 if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
4949 res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
4950 return -EFAULT;
4951 hanum = res.ionode;
4952 ha = HADATA(gdth_ctr_tab[hanum]);
4953
4954 if (!ha->hdr[res.number].present)
4955 return 0;
4956 memset(&cmd, 0, sizeof(gdth_cmd_str));
4957 cmd.Service = CACHESERVICE;
4958 cmd.OpCode = GDT_CLUST_RESET;
4959 if (ha->cache_feat & GDT_64BIT)
4960 cmd.u.cache64.DeviceNo = res.number;
4961 else
4962 cmd.u.cache.DeviceNo = res.number;
cbd5f69b
LA		 4963
4964 rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
4965 if (rval < 0)
4966 return rval;
4967 res.status = rval;
1da177e4
LT		 4968
4969 if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
4970 return -EFAULT;
4971 return 0;
4972}
4973
4974static int ioc_general(void __user *arg, char *cmnd)
4975{
4976 gdth_ioctl_general gen;
4977 char *buf = NULL;
4978 ulong64 paddr;
4979 int hanum;
cbd5f69b
LA		 4980 gdth_ha_str *ha;
4981 int rval;
1da177e4
LT		 4982
4983 if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
4984 gen.ionode >= gdth_ctr_count)
4985 return -EFAULT;
4986 hanum = gen.ionode;
4987 ha = HADATA(gdth_ctr_tab[hanum]);
4988 if (gen.data_len + gen.sense_len != 0) {
4989 if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
4990 FALSE, &paddr)))
4991 return -EFAULT;
4992 if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
4993 gen.data_len + gen.sense_len)) {
4994 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
4995 return -EFAULT;
4996 }
4997
4998 if (gen.command.OpCode == GDT_IOCTL) {
4999 gen.command.u.ioctl.p_param = paddr;
5000 } else if (gen.command.Service == CACHESERVICE) {
5001 if (ha->cache_feat & GDT_64BIT) {
5002 /* copy elements from 32-bit IOCTL structure */
5003 gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
5004 gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
5005 gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
5006 /* addresses */
5007 if (ha->cache_feat & SCATTER_GATHER) {
5008 gen.command.u.cache64.DestAddr = (ulong64)-1;
5009 gen.command.u.cache64.sg_canz = 1;
5010 gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
5011 gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
5012 gen.command.u.cache64.sg_lst[1].sg_len = 0;
5013 } else {
5014 gen.command.u.cache64.DestAddr = paddr;
5015 gen.command.u.cache64.sg_canz = 0;
5016 }
5017 } else {
5018 if (ha->cache_feat & SCATTER_GATHER) {
5019 gen.command.u.cache.DestAddr = 0xffffffff;
5020 gen.command.u.cache.sg_canz = 1;
5021 gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
5022 gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
5023 gen.command.u.cache.sg_lst[1].sg_len = 0;
5024 } else {
5025 gen.command.u.cache.DestAddr = paddr;
5026 gen.command.u.cache.sg_canz = 0;
5027 }
5028 }
5029 } else if (gen.command.Service == SCSIRAWSERVICE) {
5030 if (ha->raw_feat & GDT_64BIT) {
5031 /* copy elements from 32-bit IOCTL structure */
5032 char cmd[16];
5033 gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
5034 gen.command.u.raw64.bus = gen.command.u.raw.bus;
5035 gen.command.u.raw64.lun = gen.command.u.raw.lun;
5036 gen.command.u.raw64.target = gen.command.u.raw.target;
5037 memcpy(cmd, gen.command.u.raw.cmd, 16);
5038 memcpy(gen.command.u.raw64.cmd, cmd, 16);
5039 gen.command.u.raw64.clen = gen.command.u.raw.clen;
5040 gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
5041 gen.command.u.raw64.direction = gen.command.u.raw.direction;
5042 /* addresses */
5043 if (ha->raw_feat & SCATTER_GATHER) {
5044 gen.command.u.raw64.sdata = (ulong64)-1;
5045 gen.command.u.raw64.sg_ranz = 1;
5046 gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
5047 gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
5048 gen.command.u.raw64.sg_lst[1].sg_len = 0;
5049 } else {
5050 gen.command.u.raw64.sdata = paddr;
5051 gen.command.u.raw64.sg_ranz = 0;
5052 }
5053 gen.command.u.raw64.sense_data = paddr + gen.data_len;
5054 } else {
5055 if (ha->raw_feat & SCATTER_GATHER) {
5056 gen.command.u.raw.sdata = 0xffffffff;
5057 gen.command.u.raw.sg_ranz = 1;
5058 gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
5059 gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
5060 gen.command.u.raw.sg_lst[1].sg_len = 0;
5061 } else {
5062 gen.command.u.raw.sdata = paddr;
5063 gen.command.u.raw.sg_ranz = 0;
5064 }
5065 gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
5066 }
5067 } else {
5068 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5069 return -EFAULT;
5070 }
5071 }
5072
cbd5f69b
LA		 5073 rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
5074 if (rval < 0)
5075 return rval;
5076 gen.status = rval;
1da177e4
LT		 5077
5078 if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
5079 gen.data_len + gen.sense_len)) {
5080 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5081 return -EFAULT;
5082 }
5083 if (copy_to_user(arg, &gen,
5084 sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
5085 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5086 return -EFAULT;
5087 }
5088 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5089 return 0;
5090}
5091
5092static int ioc_hdrlist(void __user *arg, char *cmnd)
5093{
5094 gdth_ioctl_rescan *rsc;
5095 gdth_cmd_str *cmd;
5096 gdth_ha_str *ha;
5097 unchar i;
5098 int hanum, rc = -ENOMEM;
cbd5f69b
LA		 5099 u32 cluster_type = 0;
5100
1da177e4
LT		 5101 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
5102 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
5103 if (!rsc || !cmd)
cbd5f69b 5104 goto free_fail;
1da177e4
LT		 5105
5106 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
5107 rsc->ionode >= gdth_ctr_count) {
5108 rc = -EFAULT;
cbd5f69b 5109 goto free_fail;
1da177e4
LT		 5110 }
5111 hanum = rsc->ionode;
5112 ha = HADATA(gdth_ctr_tab[hanum]);
5113 memset(cmd, 0, sizeof(gdth_cmd_str));
5114
1da177e4
LT		 5115 for (i = 0; i < MAX_HDRIVES; ++i) {
5116 if (!ha->hdr[i].present) {
5117 rsc->hdr_list[i].bus = 0xff;
5118 continue;
5119 }
5120 rsc->hdr_list[i].bus = ha->virt_bus;
5121 rsc->hdr_list[i].target = i;
5122 rsc->hdr_list[i].lun = 0;
5123 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
5124 if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
5125 cmd->Service = CACHESERVICE;
5126 cmd->OpCode = GDT_CLUST_INFO;
5127 if (ha->cache_feat & GDT_64BIT)
5128 cmd->u.cache64.DeviceNo = i;
5129 else
5130 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 5131 if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
5132 rsc->hdr_list[i].cluster_type = cluster_type;
1da177e4
LT		 5133 }
5134 }
cbd5f69b 5135
1da177e4
LT		 5136 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
5137 rc = -EFAULT;
5138 else
cbd5f69b 5139 rc = 0;
1da177e4
LT		 5140
5141free_fail:
5142 kfree(rsc);
5143 kfree(cmd);
5144 return rc;
5145}
5146
5147static int ioc_rescan(void __user *arg, char *cmnd)
5148{
5149 gdth_ioctl_rescan *rsc;
5150 gdth_cmd_str *cmd;
5151 ushort i, status, hdr_cnt;
5152 ulong32 info;
5153 int hanum, cyls, hds, secs;
5154 int rc = -ENOMEM;
5155 ulong flags;
5156 gdth_ha_str *ha;
1da177e4
LT		 5157
5158 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
5159 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
5160 if (!cmd || !rsc)
cbd5f69b 5161 goto free_fail;
1da177e4
LT		 5162
5163 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
5164 rsc->ionode >= gdth_ctr_count) {
cbd5f69b
LA		 5165 rc = -EFAULT;
5166 goto free_fail;
1da177e4
LT		 5167 }
5168 hanum = rsc->ionode;
5169 ha = HADATA(gdth_ctr_tab[hanum]);
5170 memset(cmd, 0, sizeof(gdth_cmd_str));
5171
1da177e4
LT		 5172 if (rsc->flag == 0) {
5173 /* old method: re-init. cache service */
5174 cmd->Service = CACHESERVICE;
5175 if (ha->cache_feat & GDT_64BIT) {
5176 cmd->OpCode = GDT_X_INIT_HOST;
5177 cmd->u.cache64.DeviceNo = LINUX_OS;
5178 } else {
5179 cmd->OpCode = GDT_INIT;
5180 cmd->u.cache.DeviceNo = LINUX_OS;
5181 }
cbd5f69b
LA		 5182
5183 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
1da177e4
LT		 5184 i = 0;
5185 hdr_cnt = (status == S_OK ? (ushort)info : 0);
5186 } else {
5187 i = rsc->hdr_no;
5188 hdr_cnt = i + 1;
5189 }
5190
5191 for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
5192 cmd->Service = CACHESERVICE;
5193 cmd->OpCode = GDT_INFO;
5194 if (ha->cache_feat & GDT_64BIT)
5195 cmd->u.cache64.DeviceNo = i;
5196 else
5197 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 5198
5199 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5200
1da177e4
LT		 5201 spin_lock_irqsave(&ha->smp_lock, flags);
5202 rsc->hdr_list[i].bus = ha->virt_bus;
5203 rsc->hdr_list[i].target = i;
5204 rsc->hdr_list[i].lun = 0;
5205 if (status != S_OK) {
5206 ha->hdr[i].present = FALSE;
5207 } else {
5208 ha->hdr[i].present = TRUE;
5209 ha->hdr[i].size = info;
5210 /* evaluate mapping */
5211 ha->hdr[i].size &= ~SECS32;
5212 gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
5213 ha->hdr[i].heads = hds;
5214 ha->hdr[i].secs = secs;
5215 /* round size */
5216 ha->hdr[i].size = cyls * hds * secs;
5217 }
5218 spin_unlock_irqrestore(&ha->smp_lock, flags);
5219 if (status != S_OK)
5220 continue;
5221
5222 /* extended info, if GDT_64BIT, for drives > 2 TB */
5223 /* but we need ha->info2, not yet stored in scp->SCp */
5224
5225 /* devtype, cluster info, R/W attribs */
5226 cmd->Service = CACHESERVICE;
5227 cmd->OpCode = GDT_DEVTYPE;
5228 if (ha->cache_feat & GDT_64BIT)
5229 cmd->u.cache64.DeviceNo = i;
5230 else
5231 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 5232
5233 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5234
1da177e4
LT		 5235 spin_lock_irqsave(&ha->smp_lock, flags);
5236 ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
5237 spin_unlock_irqrestore(&ha->smp_lock, flags);
5238
5239 cmd->Service = CACHESERVICE;
5240 cmd->OpCode = GDT_CLUST_INFO;
5241 if (ha->cache_feat & GDT_64BIT)
5242 cmd->u.cache64.DeviceNo = i;
5243 else
5244 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 5245
5246 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5247
1da177e4
LT		 5248 spin_lock_irqsave(&ha->smp_lock, flags);
5249 ha->hdr[i].cluster_type =
5250 ((status == S_OK && !shared_access) ? (ushort)info : 0);
5251 spin_unlock_irqrestore(&ha->smp_lock, flags);
5252 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
5253
5254 cmd->Service = CACHESERVICE;
5255 cmd->OpCode = GDT_RW_ATTRIBS;
5256 if (ha->cache_feat & GDT_64BIT)
5257 cmd->u.cache64.DeviceNo = i;
5258 else
5259 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 5260
5261 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5262
1da177e4
LT		 5263 spin_lock_irqsave(&ha->smp_lock, flags);
5264 ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
5265 spin_unlock_irqrestore(&ha->smp_lock, flags);
5266 }
1da177e4
LT		 5267
5268 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
5269 rc = -EFAULT;
5270 else
cbd5f69b 5271 rc = 0;
1da177e4
LT		 5272
5273free_fail:
5274 kfree(rsc);
5275 kfree(cmd);
5276 return rc;
5277}
5278
5279static int gdth_ioctl(struct inode *inode, struct file *filep,
5280 unsigned int cmd, unsigned long arg)
5281{
5282 gdth_ha_str *ha;
5283 Scsi_Cmnd *scp;
5284 ulong flags;
5285 char cmnd[MAX_COMMAND_SIZE];
5286 void __user *argp = (void __user *)arg;
5287
5288 memset(cmnd, 0xff, 12);
5289
5290 TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
5291
5292 switch (cmd) {
5293 case GDTIOCTL_CTRCNT:
5294 {
5295 int cnt = gdth_ctr_count;
5296 if (put_user(cnt, (int __user *)argp))
5297 return -EFAULT;
5298 break;
5299 }
5300
5301 case GDTIOCTL_DRVERS:
5302 {
5303 int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
5304 if (put_user(ver, (int __user *)argp))
5305 return -EFAULT;
5306 break;
5307 }
5308
5309 case GDTIOCTL_OSVERS:
5310 {
5311 gdth_ioctl_osvers osv;
5312
5313 osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
5314 osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
5315 osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
5316 if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
5317 return -EFAULT;
5318 break;
5319 }
5320
5321 case GDTIOCTL_CTRTYPE:
5322 {
5323 gdth_ioctl_ctrtype ctrt;
5324
5325 if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
5326 ctrt.ionode >= gdth_ctr_count)
5327 return -EFAULT;
5328 ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
5329 if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
5330 ctrt.type = (unchar)((ha->stype>>20) - 0x10);
5331 } else {
5332 if (ha->type != GDT_PCIMPR) {
5333 ctrt.type = (unchar)((ha->stype<<4) + 6);
5334 } else {
5335 ctrt.type =
5336 (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
5337 if (ha->stype >= 0x300)
8e9a8a0d 5338 ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
1da177e4
LT		 5339 else
5340 ctrt.ext_type = 0x6000 | ha->stype;
5341 }
8e9a8a0d
JG		 5342 ctrt.device_id = ha->pdev->device;
5343 ctrt.sub_device_id = ha->pdev->subsystem_device;
1da177e4
LT		 5344 }
5345 ctrt.info = ha->brd_phys;
5346 ctrt.oem_id = ha->oem_id;
5347 if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
5348 return -EFAULT;
5349 break;
5350 }
5351
5352 case GDTIOCTL_GENERAL:
5353 return ioc_general(argp, cmnd);
5354
5355 case GDTIOCTL_EVENT:
5356 return ioc_event(argp);
5357
5358 case GDTIOCTL_LOCKDRV:
5359 return ioc_lockdrv(argp);
5360
5361 case GDTIOCTL_LOCKCHN:
5362 {
5363 gdth_ioctl_lockchn lchn;
5364 unchar i, j;
5365
5366 if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
5367 lchn.ionode >= gdth_ctr_count)
5368 return -EFAULT;
5369 ha = HADATA(gdth_ctr_tab[lchn.ionode]);
5370
5371 i = lchn.channel;
5372 if (i < ha->bus_cnt) {
5373 if (lchn.lock) {
5374 spin_lock_irqsave(&ha->smp_lock, flags);
5375 ha->raw[i].lock = 1;
5376 spin_unlock_irqrestore(&ha->smp_lock, flags);
5377 for (j = 0; j < ha->tid_cnt; ++j) {
5378 gdth_wait_completion(lchn.ionode, i, j);
5379 gdth_stop_timeout(lchn.ionode, i, j);
5380 }
5381 } else {
5382 spin_lock_irqsave(&ha->smp_lock, flags);
5383 ha->raw[i].lock = 0;
5384 spin_unlock_irqrestore(&ha->smp_lock, flags);
5385 for (j = 0; j < ha->tid_cnt; ++j) {
5386 gdth_start_timeout(lchn.ionode, i, j);
5387 gdth_next(lchn.ionode);
5388 }
5389 }
5390 }
5391 break;
5392 }
5393
5394 case GDTIOCTL_RESCAN:
5395 return ioc_rescan(argp, cmnd);
5396
5397 case GDTIOCTL_HDRLIST:
5398 return ioc_hdrlist(argp, cmnd);
5399
5400 case GDTIOCTL_RESET_BUS:
5401 {
5402 gdth_ioctl_reset res;
5403 int hanum, rval;
5404
5405 if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
5406 res.ionode >= gdth_ctr_count)
5407 return -EFAULT;
5408 hanum = res.ionode;
5409 ha = HADATA(gdth_ctr_tab[hanum]);
5410
1da177e4 5411#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
bbfbbbc1 5412 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
1da177e4
LT		 5413 if (!scp)
5414 return -ENOMEM;
cbd5f69b 5415 scp->device = ha->sdev;
1da177e4
LT		 5416 scp->cmd_len = 12;
5417 scp->use_sg = 0;
5418 scp->device->channel = virt_ctr ? 0 : res.number;
5419 rval = gdth_eh_bus_reset(scp);
5420 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
cbd5f69b 5421 kfree(scp);
1da177e4
LT		 5422#else
5423 scp = scsi_allocate_device(ha->sdev, 1, FALSE);
5424 if (!scp)
5425 return -ENOMEM;
5426 scp->cmd_len = 12;
5427 scp->use_sg = 0;
5428 scp->channel = virt_ctr ? 0 : res.number;
5429 rval = gdth_eh_bus_reset(scp);
5430 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
5431 scsi_release_command(scp);
5432#endif
5433 if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
5434 return -EFAULT;
5435 break;
5436 }
5437
5438 case GDTIOCTL_RESET_DRV:
5439 return ioc_resetdrv(argp, cmnd);
5440
5441 default:
5442 break;
5443 }
5444 return 0;
5445}
5446
5447
5448/* flush routine */
5449static void gdth_flush(int hanum)
5450{
5451 int i;
5452 gdth_ha_str *ha;
5453 gdth_cmd_str gdtcmd;
1da177e4
LT		 5454 char cmnd[MAX_COMMAND_SIZE];
5455 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
5456
5457 TRACE2(("gdth_flush() hanum %d\n",hanum));
5458 ha = HADATA(gdth_ctr_tab[hanum]);
5459
1da177e4
LT		 5460 for (i = 0; i < MAX_HDRIVES; ++i) {
5461 if (ha->hdr[i].present) {
5462 gdtcmd.BoardNode = LOCALBOARD;
5463 gdtcmd.Service = CACHESERVICE;
5464 gdtcmd.OpCode = GDT_FLUSH;
5465 if (ha->cache_feat & GDT_64BIT) {
5466 gdtcmd.u.cache64.DeviceNo = i;
5467 gdtcmd.u.cache64.BlockNo = 1;
5468 gdtcmd.u.cache64.sg_canz = 0;
5469 } else {
5470 gdtcmd.u.cache.DeviceNo = i;
5471 gdtcmd.u.cache.BlockNo = 1;
5472 gdtcmd.u.cache.sg_canz = 0;
5473 }
5474 TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
cbd5f69b
LA		 5475
5476 gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 30, NULL);
1da177e4
LT		 5477 }
5478 }
1da177e4
LT		 5479}
5480
5481/* shutdown routine */
5482static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
5483{
5484 int hanum;
5485#ifndef __alpha__
5486 gdth_cmd_str gdtcmd;
1da177e4
LT		 5487 char cmnd[MAX_COMMAND_SIZE];
5488#endif
5489
e041c683 5490 if (notifier_disabled)
cbd5f69b 5491 return NOTIFY_OK;
e041c683 5492
1da177e4
LT		 5493 TRACE2(("gdth_halt() event %d\n",(int)event));
5494 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
5495 return NOTIFY_DONE;
5496
e041c683 5497 notifier_disabled = 1;
1da177e4
LT		 5498 printk("GDT-HA: Flushing all host drives .. ");
5499 for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
5500 gdth_flush(hanum);
5501
5502#ifndef __alpha__
5503 /* controller reset */
5504 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
5505 gdtcmd.BoardNode = LOCALBOARD;
5506 gdtcmd.Service = CACHESERVICE;
5507 gdtcmd.OpCode = GDT_RESET;
5508 TRACE2(("gdth_halt(): reset controller %d\n", hanum));
cbd5f69b 5509 gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 10, NULL);
1da177e4
LT		 5510#endif
5511 }
5512 printk("Done.\n");
5513
5514#ifdef GDTH_STATISTICS
5515 del_timer(&gdth_timer);
5516#endif
1da177e4
LT		 5517 return NOTIFY_OK;
5518}
5519
cbd5f69b
LA		 5520#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5521/* configure lun */
5522static int gdth_slave_configure(struct scsi_device *sdev)
5523{
5524 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
5525 sdev->skip_ms_page_3f = 1;
5526 sdev->skip_ms_page_8 = 1;
5527 return 0;
5528}
5529#endif
5530
5531#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
d0be4a7d 5532static struct scsi_host_template driver_template = {
cbd5f69b
LA		 5533#else
5534static Scsi_Host_Template driver_template = {
5535#endif
1da177e4
LT		 5536 .proc_name = "gdth",
5537 .proc_info = gdth_proc_info,
5538 .name = "GDT SCSI Disk Array Controller",
5539 .detect = gdth_detect,
5540 .release = gdth_release,
5541 .info = gdth_info,
5542 .queuecommand = gdth_queuecommand,
1da177e4 5543 .eh_bus_reset_handler = gdth_eh_bus_reset,
1da177e4
LT		 5544 .bios_param = gdth_bios_param,
5545 .can_queue = GDTH_MAXCMDS,
cbd5f69b
LA		 5546#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5547 .slave_configure = gdth_slave_configure,
5548#endif
1da177e4
LT		 5549 .this_id = -1,
5550 .sg_tablesize = GDTH_MAXSG,
5551 .cmd_per_lun = GDTH_MAXC_P_L,
5552 .unchecked_isa_dma = 1,
5553 .use_clustering = ENABLE_CLUSTERING,
5554#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
5555 .use_new_eh_code = 1,
5556#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
5557 .highmem_io = 1,
5558#endif
5559#endif
5560};
5561
aed91cb5
CH		 5562#ifdef CONFIG_ISA
5563static int gdth_isa_probe_one(struct scsi_host_template *shtp, ulong32 isa_bios)
5564{
5565 struct Scsi_Host *shp;
5566 gdth_ha_str *ha;
5567 dma_addr_t scratch_dma_handle = 0;
5568 int error, hanum, i;
5569 u8 b;
5570
5571 if (!gdth_search_isa(isa_bios))
5572 return -ENXIO;
5573
5574 shp = scsi_register(shtp, sizeof(gdth_ext_str));
5575 if (!shp)
5576 return -ENOMEM;
5577 ha = HADATA(shp);
5578
5579 error = -ENODEV;
5580 if (!gdth_init_isa(isa_bios,ha))
5581 goto out_host_put;
5582
5583 /* controller found and initialized */
5584 printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
5585 isa_bios, ha->irq, ha->drq);
5586
5587 error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
5588 if (error) {
5589 printk("GDT-ISA: Unable to allocate IRQ\n");
5590 goto out_host_put;
5591 }
5592
5593 error = request_dma(ha->drq, "gdth");
5594 if (error) {
5595 printk("GDT-ISA: Unable to allocate DMA channel\n");
5596 goto out_free_irq;
5597 }
5598
5599 set_dma_mode(ha->drq,DMA_MODE_CASCADE);
5600 enable_dma(ha->drq);
5601 shp->unchecked_isa_dma = 1;
5602 shp->irq = ha->irq;
5603 shp->dma_channel = ha->drq;
5604 hanum = gdth_ctr_count;
5605 gdth_ctr_tab[gdth_ctr_count++] = shp;
5606 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
5607
5608 NUMDATA(shp)->hanum = (ushort)hanum;
5609 NUMDATA(shp)->busnum= 0;
5610
5611 ha->pccb = CMDDATA(shp);
5612 ha->ccb_phys = 0L;
5613 ha->pdev = NULL;
5614
5615 error = -ENOMEM;
5616
5617 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
5618 &scratch_dma_handle);
5619 if (!ha->pscratch)
5620 goto out_dec_counters;
5621 ha->scratch_phys = scratch_dma_handle;
5622
5623 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
5624 &scratch_dma_handle);
5625 if (!ha->pmsg)
5626 goto out_free_pscratch;
5627 ha->msg_phys = scratch_dma_handle;
5628
5629#ifdef INT_COAL
5630 ha->coal_stat = pci_alloc_consistent(ha->pdev,
5631 sizeof(gdth_coal_status) * MAXOFFSETS,
5632 &scratch_dma_handle);
5633 if (!ha->coal_stat)
5634 goto out_free_pmsg;
5635 ha->coal_stat_phys = scratch_dma_handle;
5636#endif
5637
5638 ha->scratch_busy = FALSE;
5639 ha->req_first = NULL;
5640 ha->tid_cnt = MAX_HDRIVES;
5641 if (max_ids > 0 && max_ids < ha->tid_cnt)
5642 ha->tid_cnt = max_ids;
5643 for (i = 0; i < GDTH_MAXCMDS; ++i)
5644 ha->cmd_tab[i].cmnd = UNUSED_CMND;
5645 ha->scan_mode = rescan ? 0x10 : 0;
5646
5647 error = -ENODEV;
5648 if (!gdth_search_drives(hanum)) {
5649 printk("GDT-ISA: Error during device scan\n");
5650 goto out_free_coal_stat;
5651 }
5652
5653 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
5654 hdr_channel = ha->bus_cnt;
5655 ha->virt_bus = hdr_channel;
5656
5657 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
5658 shp->max_cmd_len = 16;
5659
5660 shp->max_id = ha->tid_cnt;
5661 shp->max_lun = MAXLUN;
5662 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
5663 if (virt_ctr) {
5664 virt_ctr = 1;
5665 /* register addit. SCSI channels as virtual controllers */
5666 for (b = 1; b < ha->bus_cnt + 1; ++b) {
5667 shp = scsi_register(shtp,sizeof(gdth_num_str));
5668 shp->unchecked_isa_dma = 1;
5669 shp->irq = ha->irq;
5670 shp->dma_channel = ha->drq;
5671 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
5672 NUMDATA(shp)->hanum = (ushort)hanum;
5673 NUMDATA(shp)->busnum = b;
5674 }
5675 }
5676
5677 spin_lock_init(&ha->smp_lock);
5678 gdth_enable_int(hanum);
5679
5680 return 0;
5681
5682 out_free_coal_stat:
5683#ifdef INT_COAL
5684 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
5685 ha->coal_stat, ha->coal_stat_phys);
5686 out_free_pmsg:
5687#endif
5688 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5689 ha->pmsg, ha->msg_phys);
5690 out_free_pscratch:
5691 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5692 ha->pscratch, ha->scratch_phys);
5693 out_dec_counters:
5694 gdth_ctr_count--;
5695 gdth_ctr_vcount--;
5696 out_free_irq:
5697 free_irq(ha->irq, ha);
5698 out_host_put:
5699 scsi_unregister(shp);
5700 return error;
5701}
5702#endif /* CONFIG_ISA */
5703
5704
1da177e4
LT		 5705#include "scsi_module.c"
5706#ifndef MODULE
5707__setup("gdth=", option_setup);
5708#endif
Linux kernel - Deliverables
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