projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 3417ba8a JG |
1 | /* |
| 2 | * Copyright (c) 2016 Linaro Ltd. | |
| 3 | * Copyright (c) 2016 Hisilicon Limited. | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify | |
| 6 | * it under the terms of the GNU General Public License as published by | |
| 7 | * the Free Software Foundation; either version 2 of the License, or | |
| 8 | * (at your option) any later version. | |
| 9 | * | |
| 10 | */ | |
| 11 | ||
| 12 | #include "hisi_sas.h" | |
| 13 | #define DRV_NAME "hisi_sas_v2_hw" | |
| 14 | ||
| 45c901b8 JG |
15 | /* global registers need init*/ |
| 16 | #define DLVRY_QUEUE_ENABLE 0x0 | |
| 17 | #define IOST_BASE_ADDR_LO 0x8 | |
| 18 | #define IOST_BASE_ADDR_HI 0xc | |
| 19 | #define ITCT_BASE_ADDR_LO 0x10 | |
| 20 | #define ITCT_BASE_ADDR_HI 0x14 | |
| 21 | #define IO_BROKEN_MSG_ADDR_LO 0x18 | |
| 22 | #define IO_BROKEN_MSG_ADDR_HI 0x1c | |
| 23 | #define PHY_CONTEXT 0x20 | |
| 24 | #define PHY_STATE 0x24 | |
| 25 | #define PHY_PORT_NUM_MA 0x28 | |
| 26 | #define PORT_STATE 0x2c | |
| 27 | #define PORT_STATE_PHY8_PORT_NUM_OFF 16 | |
| 28 | #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF) | |
| 29 | #define PORT_STATE_PHY8_CONN_RATE_OFF 20 | |
| 30 | #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF) | |
| 31 | #define PHY_CONN_RATE 0x30 | |
| 32 | #define HGC_TRANS_TASK_CNT_LIMIT 0x38 | |
| 33 | #define AXI_AHB_CLK_CFG 0x3c | |
| 34 | #define ITCT_CLR 0x44 | |
| 35 | #define ITCT_CLR_EN_OFF 16 | |
| 36 | #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) | |
| 37 | #define ITCT_DEV_OFF 0 | |
| 38 | #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) | |
| 39 | #define AXI_USER1 0x48 | |
| 40 | #define AXI_USER2 0x4c | |
| 41 | #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 | |
| 42 | #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c | |
| 43 | #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 | |
| 44 | #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 | |
| 45 | #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 | |
| 46 | #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 | |
| 47 | #define HGC_GET_ITV_TIME 0x90 | |
| 48 | #define DEVICE_MSG_WORK_MODE 0x94 | |
| 49 | #define OPENA_WT_CONTI_TIME 0x9c | |
| 50 | #define I_T_NEXUS_LOSS_TIME 0xa0 | |
| 51 | #define MAX_CON_TIME_LIMIT_TIME 0xa4 | |
| 52 | #define BUS_INACTIVE_LIMIT_TIME 0xa8 | |
| 53 | #define REJECT_TO_OPEN_LIMIT_TIME 0xac | |
| 54 | #define CFG_AGING_TIME 0xbc | |
| 55 | #define HGC_DFX_CFG2 0xc0 | |
| 56 | #define HGC_IOMB_PROC1_STATUS 0x104 | |
| 57 | #define CFG_1US_TIMER_TRSH 0xcc | |
| 58 | #define HGC_INVLD_DQE_INFO 0x148 | |
| 59 | #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9 | |
| 60 | #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF) | |
| 61 | #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18 | |
| 62 | #define INT_COAL_EN 0x19c | |
| 63 | #define OQ_INT_COAL_TIME 0x1a0 | |
| 64 | #define OQ_INT_COAL_CNT 0x1a4 | |
| 65 | #define ENT_INT_COAL_TIME 0x1a8 | |
| 66 | #define ENT_INT_COAL_CNT 0x1ac | |
| 67 | #define OQ_INT_SRC 0x1b0 | |
| 68 | #define OQ_INT_SRC_MSK 0x1b4 | |
| 69 | #define ENT_INT_SRC1 0x1b8 | |
| 70 | #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 | |
| 71 | #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) | |
| 72 | #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 | |
| 73 | #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) | |
| 74 | #define ENT_INT_SRC2 0x1bc | |
| 75 | #define ENT_INT_SRC3 0x1c0 | |
| 76 | #define ENT_INT_SRC3_ITC_INT_OFF 15 | |
| 77 | #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) | |
| 78 | #define ENT_INT_SRC_MSK1 0x1c4 | |
| 79 | #define ENT_INT_SRC_MSK2 0x1c8 | |
| 80 | #define ENT_INT_SRC_MSK3 0x1cc | |
| 81 | #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 | |
| 82 | #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) | |
| 83 | #define SAS_ECC_INTR_MSK 0x1ec | |
| 84 | #define HGC_ERR_STAT_EN 0x238 | |
| 85 | #define DLVRY_Q_0_BASE_ADDR_LO 0x260 | |
| 86 | #define DLVRY_Q_0_BASE_ADDR_HI 0x264 | |
| 87 | #define DLVRY_Q_0_DEPTH 0x268 | |
| 88 | #define DLVRY_Q_0_WR_PTR 0x26c | |
| 89 | #define DLVRY_Q_0_RD_PTR 0x270 | |
| 90 | #define HYPER_STREAM_ID_EN_CFG 0xc80 | |
| 91 | #define OQ0_INT_SRC_MSK 0xc90 | |
| 92 | #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 | |
| 93 | #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 | |
| 94 | #define COMPL_Q_0_DEPTH 0x4e8 | |
| 95 | #define COMPL_Q_0_WR_PTR 0x4ec | |
| 96 | #define COMPL_Q_0_RD_PTR 0x4f0 | |
| 97 | ||
| 98 | /* phy registers need init */ | |
| 99 | #define PORT_BASE (0x2000) | |
| 100 | ||
| 101 | #define PHY_CFG (PORT_BASE + 0x0) | |
| 102 | #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) | |
| 103 | #define PHY_CFG_ENA_OFF 0 | |
| 104 | #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) | |
| 105 | #define PHY_CFG_DC_OPT_OFF 2 | |
| 106 | #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) | |
| 107 | #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) | |
| 108 | #define PROG_PHY_LINK_RATE_MAX_OFF 0 | |
| 109 | #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF) | |
| 110 | #define PHY_CTRL (PORT_BASE + 0x14) | |
| 111 | #define PHY_CTRL_RESET_OFF 0 | |
| 112 | #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) | |
| 113 | #define SAS_PHY_CTRL (PORT_BASE + 0x20) | |
| 114 | #define SL_CFG (PORT_BASE + 0x84) | |
| 115 | #define PHY_PCN (PORT_BASE + 0x44) | |
| 116 | #define SL_TOUT_CFG (PORT_BASE + 0x8c) | |
| 117 | #define SL_CONTROL (PORT_BASE + 0x94) | |
| 118 | #define SL_CONTROL_NOTIFY_EN_OFF 0 | |
| 119 | #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) | |
| 120 | #define TX_ID_DWORD0 (PORT_BASE + 0x9c) | |
| 121 | #define TX_ID_DWORD1 (PORT_BASE + 0xa0) | |
| 122 | #define TX_ID_DWORD2 (PORT_BASE + 0xa4) | |
| 123 | #define TX_ID_DWORD3 (PORT_BASE + 0xa8) | |
| 124 | #define TX_ID_DWORD4 (PORT_BASE + 0xaC) | |
| 125 | #define TX_ID_DWORD5 (PORT_BASE + 0xb0) | |
| 126 | #define TX_ID_DWORD6 (PORT_BASE + 0xb4) | |
| 127 | #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) | |
| 128 | #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8) | |
| 129 | #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc) | |
| 130 | #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0) | |
| 131 | #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4) | |
| 132 | #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8) | |
| 133 | #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc) | |
| 134 | #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) | |
| 135 | #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c) | |
| 136 | #define CHL_INT0 (PORT_BASE + 0x1b4) | |
| 137 | #define CHL_INT0_HOTPLUG_TOUT_OFF 0 | |
| 138 | #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) | |
| 139 | #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 | |
| 140 | #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) | |
| 141 | #define CHL_INT0_SL_PHY_ENABLE_OFF 2 | |
| 142 | #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) | |
| 143 | #define CHL_INT0_NOT_RDY_OFF 4 | |
| 144 | #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) | |
| 145 | #define CHL_INT0_PHY_RDY_OFF 5 | |
| 146 | #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) | |
| 147 | #define CHL_INT1 (PORT_BASE + 0x1b8) | |
| 148 | #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 | |
| 149 | #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) | |
| 150 | #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 | |
| 151 | #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) | |
| 152 | #define CHL_INT2 (PORT_BASE + 0x1bc) | |
| 153 | #define CHL_INT0_MSK (PORT_BASE + 0x1c0) | |
| 154 | #define CHL_INT1_MSK (PORT_BASE + 0x1c4) | |
| 155 | #define CHL_INT2_MSK (PORT_BASE + 0x1c8) | |
| 156 | #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) | |
| 157 | #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) | |
| 158 | #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) | |
| 159 | #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) | |
| 160 | #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) | |
| 161 | #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) | |
| 162 | #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) | |
| 163 | #define DMA_TX_STATUS (PORT_BASE + 0x2d0) | |
| 164 | #define DMA_TX_STATUS_BUSY_OFF 0 | |
| 165 | #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) | |
| 166 | #define DMA_RX_STATUS (PORT_BASE + 0x2e8) | |
| 167 | #define DMA_RX_STATUS_BUSY_OFF 0 | |
| 168 | #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) | |
| 169 | ||
| 170 | #define AXI_CFG (0x5100) | |
| 171 | #define AM_CFG_MAX_TRANS (0x5010) | |
| 172 | #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) | |
| 173 | ||
| 174 | /* HW dma structures */ | |
| 175 | /* Delivery queue header */ | |
| 176 | /* dw0 */ | |
| 177 | #define CMD_HDR_RESP_REPORT_OFF 5 | |
| 178 | #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) | |
| 179 | #define CMD_HDR_TLR_CTRL_OFF 6 | |
| 180 | #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) | |
| 181 | #define CMD_HDR_PORT_OFF 18 | |
| 182 | #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) | |
| 183 | #define CMD_HDR_PRIORITY_OFF 27 | |
| 184 | #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) | |
| 185 | #define CMD_HDR_CMD_OFF 29 | |
| 186 | #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) | |
| 187 | /* dw1 */ | |
| 188 | #define CMD_HDR_DIR_OFF 5 | |
| 189 | #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) | |
| 190 | #define CMD_HDR_RESET_OFF 7 | |
| 191 | #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) | |
| 192 | #define CMD_HDR_VDTL_OFF 10 | |
| 193 | #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) | |
| 194 | #define CMD_HDR_FRAME_TYPE_OFF 11 | |
| 195 | #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) | |
| 196 | #define CMD_HDR_DEV_ID_OFF 16 | |
| 197 | #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) | |
| 198 | /* dw2 */ | |
| 199 | #define CMD_HDR_CFL_OFF 0 | |
| 200 | #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) | |
| 201 | #define CMD_HDR_NCQ_TAG_OFF 10 | |
| 202 | #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) | |
| 203 | #define CMD_HDR_MRFL_OFF 15 | |
| 204 | #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) | |
| 205 | #define CMD_HDR_SG_MOD_OFF 24 | |
| 206 | #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) | |
| 207 | #define CMD_HDR_FIRST_BURST_OFF 26 | |
| 208 | #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF) | |
| 209 | /* dw3 */ | |
| 210 | #define CMD_HDR_IPTT_OFF 0 | |
| 211 | #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) | |
| 212 | /* dw6 */ | |
| 213 | #define CMD_HDR_DIF_SGL_LEN_OFF 0 | |
| 214 | #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) | |
| 215 | #define CMD_HDR_DATA_SGL_LEN_OFF 16 | |
| 216 | #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) | |
| 217 | ||
| 218 | /* Completion header */ | |
| 219 | /* dw0 */ | |
| 220 | #define CMPLT_HDR_RSPNS_XFRD_OFF 10 | |
| 221 | #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) | |
| 222 | #define CMPLT_HDR_ERX_OFF 12 | |
| 223 | #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) | |
| 224 | /* dw1 */ | |
| 225 | #define CMPLT_HDR_IPTT_OFF 0 | |
| 226 | #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) | |
| 227 | #define CMPLT_HDR_DEV_ID_OFF 16 | |
| 228 | #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) | |
| 229 | ||
| 230 | /* ITCT header */ | |
| 231 | /* qw0 */ | |
| 232 | #define ITCT_HDR_DEV_TYPE_OFF 0 | |
| 233 | #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) | |
| 234 | #define ITCT_HDR_VALID_OFF 2 | |
| 235 | #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) | |
| 236 | #define ITCT_HDR_MCR_OFF 5 | |
| 237 | #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) | |
| 238 | #define ITCT_HDR_VLN_OFF 9 | |
| 239 | #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) | |
| 240 | #define ITCT_HDR_PORT_ID_OFF 28 | |
| 241 | #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) | |
| 242 | /* qw2 */ | |
| 243 | #define ITCT_HDR_INLT_OFF 0 | |
| 244 | #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) | |
| 245 | #define ITCT_HDR_BITLT_OFF 16 | |
| 246 | #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF) | |
| 247 | #define ITCT_HDR_MCTLT_OFF 32 | |
| 248 | #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF) | |
| 249 | #define ITCT_HDR_RTOLT_OFF 48 | |
| 250 | #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) | |
| 251 | ||
| 3417ba8a JG |
252 | static const struct hisi_sas_hw hisi_sas_v2_hw = { |
| 253 | }; | |
| 254 | ||
| 255 | static int hisi_sas_v2_probe(struct platform_device *pdev) | |
| 256 | { | |
| 257 | return hisi_sas_probe(pdev, &hisi_sas_v2_hw); | |
| 258 | } | |
| 259 | ||
| 260 | static int hisi_sas_v2_remove(struct platform_device *pdev) | |
| 261 | { | |
| 262 | return hisi_sas_remove(pdev); | |
| 263 | } | |
| 264 | ||
| 265 | static const struct of_device_id sas_v2_of_match[] = { | |
| 266 | { .compatible = "hisilicon,hip06-sas-v2",}, | |
| 267 | {}, | |
| 268 | }; | |
| 269 | MODULE_DEVICE_TABLE(of, sas_v2_of_match); | |
| 270 | ||
| 271 | static struct platform_driver hisi_sas_v2_driver = { | |
| 272 | .probe = hisi_sas_v2_probe, | |
| 273 | .remove = hisi_sas_v2_remove, | |
| 274 | .driver = { | |
| 275 | .name = DRV_NAME, | |
| 276 | .of_match_table = sas_v2_of_match, | |
| 277 | }, | |
| 278 | }; | |
| 279 | ||
| 280 | module_platform_driver(hisi_sas_v2_driver); | |
| 281 | ||
| 282 | MODULE_LICENSE("GPL"); | |
| 283 | MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); | |
| 284 | MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver"); | |
| 285 | MODULE_ALIAS("platform:" DRV_NAME); |