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hisi_sas: add v2 path to send ATA command
[deliverable/linux.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
CommitLineData
3417ba8a
JG		 1/*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12#include "hisi_sas.h"
13#define DRV_NAME "hisi_sas_v2_hw"
14
45c901b8
JG		 15/* global registers need init*/
16#define DLVRY_QUEUE_ENABLE 0x0
17#define IOST_BASE_ADDR_LO 0x8
18#define IOST_BASE_ADDR_HI 0xc
19#define ITCT_BASE_ADDR_LO 0x10
20#define ITCT_BASE_ADDR_HI 0x14
21#define IO_BROKEN_MSG_ADDR_LO 0x18
22#define IO_BROKEN_MSG_ADDR_HI 0x1c
23#define PHY_CONTEXT 0x20
24#define PHY_STATE 0x24
25#define PHY_PORT_NUM_MA 0x28
26#define PORT_STATE 0x2c
27#define PORT_STATE_PHY8_PORT_NUM_OFF 16
28#define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29#define PORT_STATE_PHY8_CONN_RATE_OFF 20
30#define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31#define PHY_CONN_RATE 0x30
32#define HGC_TRANS_TASK_CNT_LIMIT 0x38
33#define AXI_AHB_CLK_CFG 0x3c
34#define ITCT_CLR 0x44
35#define ITCT_CLR_EN_OFF 16
36#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37#define ITCT_DEV_OFF 0
38#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39#define AXI_USER1 0x48
40#define AXI_USER2 0x4c
41#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43#define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44#define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47#define HGC_GET_ITV_TIME 0x90
48#define DEVICE_MSG_WORK_MODE 0x94
49#define OPENA_WT_CONTI_TIME 0x9c
50#define I_T_NEXUS_LOSS_TIME 0xa0
51#define MAX_CON_TIME_LIMIT_TIME 0xa4
52#define BUS_INACTIVE_LIMIT_TIME 0xa8
53#define REJECT_TO_OPEN_LIMIT_TIME 0xac
54#define CFG_AGING_TIME 0xbc
55#define HGC_DFX_CFG2 0xc0
56#define HGC_IOMB_PROC1_STATUS 0x104
57#define CFG_1US_TIMER_TRSH 0xcc
58#define HGC_INVLD_DQE_INFO 0x148
59#define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
60#define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
61#define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
62#define INT_COAL_EN 0x19c
63#define OQ_INT_COAL_TIME 0x1a0
64#define OQ_INT_COAL_CNT 0x1a4
65#define ENT_INT_COAL_TIME 0x1a8
66#define ENT_INT_COAL_CNT 0x1ac
67#define OQ_INT_SRC 0x1b0
68#define OQ_INT_SRC_MSK 0x1b4
69#define ENT_INT_SRC1 0x1b8
70#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
71#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
72#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
73#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
74#define ENT_INT_SRC2 0x1bc
75#define ENT_INT_SRC3 0x1c0
76#define ENT_INT_SRC3_ITC_INT_OFF 15
77#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
78#define ENT_INT_SRC_MSK1 0x1c4
79#define ENT_INT_SRC_MSK2 0x1c8
80#define ENT_INT_SRC_MSK3 0x1cc
81#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
82#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
83#define SAS_ECC_INTR_MSK 0x1ec
84#define HGC_ERR_STAT_EN 0x238
85#define DLVRY_Q_0_BASE_ADDR_LO 0x260
86#define DLVRY_Q_0_BASE_ADDR_HI 0x264
87#define DLVRY_Q_0_DEPTH 0x268
88#define DLVRY_Q_0_WR_PTR 0x26c
89#define DLVRY_Q_0_RD_PTR 0x270
90#define HYPER_STREAM_ID_EN_CFG 0xc80
91#define OQ0_INT_SRC_MSK 0xc90
92#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
93#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
94#define COMPL_Q_0_DEPTH 0x4e8
95#define COMPL_Q_0_WR_PTR 0x4ec
96#define COMPL_Q_0_RD_PTR 0x4f0
97
98/* phy registers need init */
99#define PORT_BASE (0x2000)
100
101#define PHY_CFG (PORT_BASE + 0x0)
102#define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
103#define PHY_CFG_ENA_OFF 0
104#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
105#define PHY_CFG_DC_OPT_OFF 2
106#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
107#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
108#define PROG_PHY_LINK_RATE_MAX_OFF 0
109#define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
110#define PHY_CTRL (PORT_BASE + 0x14)
111#define PHY_CTRL_RESET_OFF 0
112#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
113#define SAS_PHY_CTRL (PORT_BASE + 0x20)
114#define SL_CFG (PORT_BASE + 0x84)
115#define PHY_PCN (PORT_BASE + 0x44)
116#define SL_TOUT_CFG (PORT_BASE + 0x8c)
117#define SL_CONTROL (PORT_BASE + 0x94)
118#define SL_CONTROL_NOTIFY_EN_OFF 0
119#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
120#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
121#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
122#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
123#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
124#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
125#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
126#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
127#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
128#define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
129#define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
130#define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
131#define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
132#define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
133#define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
134#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
135#define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
136#define CHL_INT0 (PORT_BASE + 0x1b4)
137#define CHL_INT0_HOTPLUG_TOUT_OFF 0
138#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
139#define CHL_INT0_SL_RX_BCST_ACK_OFF 1
140#define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
141#define CHL_INT0_SL_PHY_ENABLE_OFF 2
142#define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
143#define CHL_INT0_NOT_RDY_OFF 4
144#define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
145#define CHL_INT0_PHY_RDY_OFF 5
146#define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
147#define CHL_INT1 (PORT_BASE + 0x1b8)
148#define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
149#define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
150#define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
151#define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
152#define CHL_INT2 (PORT_BASE + 0x1bc)
153#define CHL_INT0_MSK (PORT_BASE + 0x1c0)
154#define CHL_INT1_MSK (PORT_BASE + 0x1c4)
155#define CHL_INT2_MSK (PORT_BASE + 0x1c8)
156#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
157#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
158#define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
159#define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
160#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
161#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
162#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
163#define DMA_TX_STATUS (PORT_BASE + 0x2d0)
164#define DMA_TX_STATUS_BUSY_OFF 0
165#define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
166#define DMA_RX_STATUS (PORT_BASE + 0x2e8)
167#define DMA_RX_STATUS_BUSY_OFF 0
168#define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
169
170#define AXI_CFG (0x5100)
171#define AM_CFG_MAX_TRANS (0x5010)
172#define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
173
174/* HW dma structures */
175/* Delivery queue header */
176/* dw0 */
177#define CMD_HDR_RESP_REPORT_OFF 5
178#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
179#define CMD_HDR_TLR_CTRL_OFF 6
180#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
181#define CMD_HDR_PORT_OFF 18
182#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
183#define CMD_HDR_PRIORITY_OFF 27
184#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
185#define CMD_HDR_CMD_OFF 29
186#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
187/* dw1 */
188#define CMD_HDR_DIR_OFF 5
189#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
190#define CMD_HDR_RESET_OFF 7
191#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
192#define CMD_HDR_VDTL_OFF 10
193#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
194#define CMD_HDR_FRAME_TYPE_OFF 11
195#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
196#define CMD_HDR_DEV_ID_OFF 16
197#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
198/* dw2 */
199#define CMD_HDR_CFL_OFF 0
200#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
201#define CMD_HDR_NCQ_TAG_OFF 10
202#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
203#define CMD_HDR_MRFL_OFF 15
204#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
205#define CMD_HDR_SG_MOD_OFF 24
206#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
207#define CMD_HDR_FIRST_BURST_OFF 26
208#define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
209/* dw3 */
210#define CMD_HDR_IPTT_OFF 0
211#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
212/* dw6 */
213#define CMD_HDR_DIF_SGL_LEN_OFF 0
214#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
215#define CMD_HDR_DATA_SGL_LEN_OFF 16
216#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
217
218/* Completion header */
219/* dw0 */
220#define CMPLT_HDR_RSPNS_XFRD_OFF 10
221#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
222#define CMPLT_HDR_ERX_OFF 12
223#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
224/* dw1 */
225#define CMPLT_HDR_IPTT_OFF 0
226#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
227#define CMPLT_HDR_DEV_ID_OFF 16
228#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
229
230/* ITCT header */
231/* qw0 */
232#define ITCT_HDR_DEV_TYPE_OFF 0
233#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
234#define ITCT_HDR_VALID_OFF 2
235#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
236#define ITCT_HDR_MCR_OFF 5
237#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
238#define ITCT_HDR_VLN_OFF 9
239#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
240#define ITCT_HDR_PORT_ID_OFF 28
241#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
242/* qw2 */
243#define ITCT_HDR_INLT_OFF 0
244#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
245#define ITCT_HDR_BITLT_OFF 16
246#define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
247#define ITCT_HDR_MCTLT_OFF 32
248#define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
249#define ITCT_HDR_RTOLT_OFF 48
250#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
251
94eac9e1
JG		 252struct hisi_sas_complete_v2_hdr {
253 __le32 dw0;
254 __le32 dw1;
255 __le32 act;
256 __le32 dw3;
257};
258
7911e66f
JG		 259enum {
260 HISI_SAS_PHY_PHY_UPDOWN,
d3bf3d84 261 HISI_SAS_PHY_CHNL_INT,
7911e66f
JG		 262 HISI_SAS_PHY_INT_NR
263};
264
94eac9e1
JG		 265#define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
266
8c36e31d
JG		 267#define DIR_NO_DATA 0
268#define DIR_TO_INI 1
269#define DIR_TO_DEVICE 2
270#define DIR_RESERVED 3
271
6f2ff1a1
JG		 272#define SATA_PROTOCOL_NONDATA 0x1
273#define SATA_PROTOCOL_PIO 0x2
274#define SATA_PROTOCOL_DMA 0x4
275#define SATA_PROTOCOL_FPDMA 0x8
276#define SATA_PROTOCOL_ATAPI 0x10
277
94eac9e1
JG		 278static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
279{
280 void __iomem *regs = hisi_hba->regs + off;
281
282 return readl(regs);
283}
284
8c36e31d
JG		 285static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
286{
287 void __iomem *regs = hisi_hba->regs + off;
288
289 return readl_relaxed(regs);
290}
291
94eac9e1
JG		 292static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
293{
294 void __iomem *regs = hisi_hba->regs + off;
295
296 writel(val, regs);
297}
298
299static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
300 u32 off, u32 val)
301{
302 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
303
304 writel(val, regs);
305}
306
307static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
308 int phy_no, u32 off)
309{
310 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
311
312 return readl(regs);
313}
314
29a20428
JG		 315static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
316{
317 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
318
319 cfg &= ~PHY_CFG_DC_OPT_MSK;
320 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
321 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
322}
323
806bb768
JG		 324static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
325{
326 struct sas_identify_frame identify_frame;
327 u32 *identify_buffer;
328
329 memset(&identify_frame, 0, sizeof(identify_frame));
330 identify_frame.dev_type = SAS_END_DEVICE;
331 identify_frame.frame_type = 0;
332 identify_frame._un1 = 1;
333 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
334 identify_frame.target_bits = SAS_PROTOCOL_NONE;
335 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
336 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
337 identify_frame.phy_id = phy_no;
338 identify_buffer = (u32 *)(&identify_frame);
339
340 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
341 __swab32(identify_buffer[0]));
342 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
343 identify_buffer[2]);
344 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
345 identify_buffer[1]);
346 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
347 identify_buffer[4]);
348 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
349 identify_buffer[3]);
350 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
351 __swab32(identify_buffer[5]));
352}
353
354static void init_id_frame_v2_hw(struct hisi_hba *hisi_hba)
355{
356 int i;
357
358 for (i = 0; i < hisi_hba->n_phy; i++)
359 config_id_frame_v2_hw(hisi_hba, i);
360}
361
85b2c3c0
JG		 362static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
363 struct hisi_sas_device *sas_dev)
364{
365 struct domain_device *device = sas_dev->sas_device;
366 struct device *dev = &hisi_hba->pdev->dev;
367 u64 qw0, device_id = sas_dev->device_id;
368 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
369 struct domain_device *parent_dev = device->parent;
370 struct hisi_sas_port *port = device->port->lldd_port;
371
372 memset(itct, 0, sizeof(*itct));
373
374 /* qw0 */
375 qw0 = 0;
376 switch (sas_dev->dev_type) {
377 case SAS_END_DEVICE:
378 case SAS_EDGE_EXPANDER_DEVICE:
379 case SAS_FANOUT_EXPANDER_DEVICE:
380 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
381 break;
382 case SAS_SATA_DEV:
383 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
384 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
385 else
386 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
387 break;
388 default:
389 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
390 sas_dev->dev_type);
391 }
392
393 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
394 (device->max_linkrate << ITCT_HDR_MCR_OFF) |
395 (1 << ITCT_HDR_VLN_OFF) |
396 (port->id << ITCT_HDR_PORT_ID_OFF));
397 itct->qw0 = cpu_to_le64(qw0);
398
399 /* qw1 */
400 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
401 itct->sas_addr = __swab64(itct->sas_addr);
402
403 /* qw2 */
404 itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_INLT_OFF) |
405 (0xff00ULL << ITCT_HDR_BITLT_OFF) |
406 (0xff00ULL << ITCT_HDR_MCTLT_OFF) |
407 (0xff00ULL << ITCT_HDR_RTOLT_OFF));
408}
409
410static void free_device_v2_hw(struct hisi_hba *hisi_hba,
411 struct hisi_sas_device *sas_dev)
412{
413 u64 qw0, dev_id = sas_dev->device_id;
414 struct device *dev = &hisi_hba->pdev->dev;
415 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
416 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
417 int i;
418
419 /* clear the itct interrupt state */
420 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
421 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
422 ENT_INT_SRC3_ITC_INT_MSK);
423
424 /* clear the itct int*/
425 for (i = 0; i < 2; i++) {
426 /* clear the itct table*/
427 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
428 reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
429 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
430
431 udelay(10);
432 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
433 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) {
434 dev_dbg(dev, "got clear ITCT done interrupt\n");
435
436 /* invalid the itct state*/
437 qw0 = cpu_to_le64(itct->qw0);
438 qw0 &= ~(1 << ITCT_HDR_VALID_OFF);
439 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
440 ENT_INT_SRC3_ITC_INT_MSK);
441 hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED;
442 hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL;
443
444 /* clear the itct */
445 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
446 dev_dbg(dev, "clear ITCT ok\n");
447 break;
448 }
449 }
450}
451
94eac9e1
JG		 452static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
453{
454 int i, reset_val;
455 u32 val;
456 unsigned long end_time;
457 struct device *dev = &hisi_hba->pdev->dev;
458
459 /* The mask needs to be set depending on the number of phys */
460 if (hisi_hba->n_phy == 9)
461 reset_val = 0x1fffff;
462 else
463 reset_val = 0x7ffff;
464
465 /* Disable all of the DQ */
466 for (i = 0; i < HISI_SAS_MAX_QUEUES; i++)
467 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
468
469 /* Disable all of the PHYs */
470 for (i = 0; i < hisi_hba->n_phy; i++) {
471 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
472
473 phy_cfg &= ~PHY_CTRL_RESET_MSK;
474 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
475 }
476 udelay(50);
477
478 /* Ensure DMA tx & rx idle */
479 for (i = 0; i < hisi_hba->n_phy; i++) {
480 u32 dma_tx_status, dma_rx_status;
481
482 end_time = jiffies + msecs_to_jiffies(1000);
483
484 while (1) {
485 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
486 DMA_TX_STATUS);
487 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
488 DMA_RX_STATUS);
489
490 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
491 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
492 break;
493
494 msleep(20);
495 if (time_after(jiffies, end_time))
496 return -EIO;
497 }
498 }
499
500 /* Ensure axi bus idle */
501 end_time = jiffies + msecs_to_jiffies(1000);
502 while (1) {
503 u32 axi_status =
504 hisi_sas_read32(hisi_hba, AXI_CFG);
505
506 if (axi_status == 0)
507 break;
508
509 msleep(20);
510 if (time_after(jiffies, end_time))
511 return -EIO;
512 }
513
514 /* reset and disable clock*/
515 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
516 reset_val);
517 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
518 reset_val);
519 msleep(1);
520 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
521 if (reset_val != (val & reset_val)) {
522 dev_err(dev, "SAS reset fail.\n");
523 return -EIO;
524 }
525
526 /* De-reset and enable clock*/
527 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
528 reset_val);
529 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
530 reset_val);
531 msleep(1);
532 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
533 &val);
534 if (val & reset_val) {
535 dev_err(dev, "SAS de-reset fail.\n");
536 return -EIO;
537 }
538
539 return 0;
540}
541
542static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
543{
544 struct device *dev = &hisi_hba->pdev->dev;
545 struct device_node *np = dev->of_node;
546 int i;
547
548 /* Global registers init */
549
550 /* Deal with am-max-transmissions quirk */
551 if (of_get_property(np, "hip06-sas-v2-quirk-amt", NULL)) {
552 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
553 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
554 0x2020);
555 } /* Else, use defaults -> do nothing */
556
557 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
558 (u32)((1ULL << hisi_hba->queue_count) - 1));
559 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
560 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
561 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
562 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
563 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
564 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
565 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x4E20);
566 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
567 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
568 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
569 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
570 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
571 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
572 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
573 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
574 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
575 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
576 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
577 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
578 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
579 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
580 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
581 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe);
582 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0);
583 for (i = 0; i < hisi_hba->queue_count; i++)
584 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
585
586 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
587 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
588
589 for (i = 0; i < hisi_hba->n_phy; i++) {
590 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
591 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
592 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
593 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10);
594 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
595 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
596 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
597 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
598 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
599 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
600 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc);
601 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
602 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
603 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
604 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
605 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
606 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
607 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
608 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
609 }
610
611 for (i = 0; i < hisi_hba->queue_count; i++) {
612 /* Delivery queue */
613 hisi_sas_write32(hisi_hba,
614 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
615 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
616
617 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
618 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
619
620 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
621 HISI_SAS_QUEUE_SLOTS);
622
623 /* Completion queue */
624 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
625 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
626
627 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
628 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
629
630 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
631 HISI_SAS_QUEUE_SLOTS);
632 }
633
634 /* itct */
635 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
636 lower_32_bits(hisi_hba->itct_dma));
637
638 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
639 upper_32_bits(hisi_hba->itct_dma));
640
641 /* iost */
642 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
643 lower_32_bits(hisi_hba->iost_dma));
644
645 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
646 upper_32_bits(hisi_hba->iost_dma));
647
648 /* breakpoint */
649 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
650 lower_32_bits(hisi_hba->breakpoint_dma));
651
652 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
653 upper_32_bits(hisi_hba->breakpoint_dma));
654
655 /* SATA broken msg */
656 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
657 lower_32_bits(hisi_hba->sata_breakpoint_dma));
658
659 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
660 upper_32_bits(hisi_hba->sata_breakpoint_dma));
661
662 /* SATA initial fis */
663 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
664 lower_32_bits(hisi_hba->initial_fis_dma));
665
666 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
667 upper_32_bits(hisi_hba->initial_fis_dma));
668}
669
670static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
671{
672 struct device *dev = &hisi_hba->pdev->dev;
673 int rc;
674
675 rc = reset_hw_v2_hw(hisi_hba);
676 if (rc) {
677 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
678 return rc;
679 }
680
681 msleep(100);
682 init_reg_v2_hw(hisi_hba);
683
806bb768
JG		 684 init_id_frame_v2_hw(hisi_hba);
685
94eac9e1
JG		 686 return 0;
687}
688
29a20428
JG		 689static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
690{
691 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
692
693 cfg |= PHY_CFG_ENA_MSK;
694 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
695}
696
697static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
698{
699 config_id_frame_v2_hw(hisi_hba, phy_no);
700 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
701 enable_phy_v2_hw(hisi_hba, phy_no);
702}
703
704static void start_phys_v2_hw(unsigned long data)
705{
706 struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
707 int i;
708
709 for (i = 0; i < hisi_hba->n_phy; i++)
710 start_phy_v2_hw(hisi_hba, i);
711}
712
713static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
714{
715 int i;
716 struct timer_list *timer = &hisi_hba->timer;
717
718 for (i = 0; i < hisi_hba->n_phy; i++) {
719 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
720 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
721 }
722
723 setup_timer(timer, start_phys_v2_hw, (unsigned long)hisi_hba);
724 mod_timer(timer, jiffies + HZ);
725}
726
7911e66f
JG		 727static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
728{
729 u32 sl_control;
730
731 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
732 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
733 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
734 msleep(1);
735 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
736 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
737 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
738}
739
5473c060
JG		 740static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
741{
742 int i, bitmap = 0;
743 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
744 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
745
746 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
747 if (phy_state & 1 << i)
748 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
749 bitmap |= 1 << i;
750
751 if (hisi_hba->n_phy == 9) {
752 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
753
754 if (phy_state & 1 << 8)
755 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
756 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
757 bitmap |= 1 << 9;
758 }
759
760 return bitmap;
761}
762
8c36e31d
JG		 763/**
764 * This function allocates across all queues to load balance.
765 * Slots are allocated from queues in a round-robin fashion.
766 *
767 * The callpath to this function and upto writing the write
768 * queue pointer should be safe from interruption.
769 */
770static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, int *q, int *s)
771{
772 struct device *dev = &hisi_hba->pdev->dev;
773 u32 r, w;
774 int queue = hisi_hba->queue;
775
776 while (1) {
777 w = hisi_sas_read32_relaxed(hisi_hba,
778 DLVRY_Q_0_WR_PTR + (queue * 0x14));
779 r = hisi_sas_read32_relaxed(hisi_hba,
780 DLVRY_Q_0_RD_PTR + (queue * 0x14));
781 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
782 queue = (queue + 1) % hisi_hba->queue_count;
783 if (queue == hisi_hba->queue) {
784 dev_warn(dev, "could not find free slot\n");
785 return -EAGAIN;
786 }
787 continue;
788 }
789 break;
790 }
791 hisi_hba->queue = (queue + 1) % hisi_hba->queue_count;
792 *q = queue;
793 *s = w;
794 return 0;
795}
796
797static void start_delivery_v2_hw(struct hisi_hba *hisi_hba)
798{
799 int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
800 int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
801
802 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
803 ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS);
804}
805
806static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
807 struct hisi_sas_slot *slot,
808 struct hisi_sas_cmd_hdr *hdr,
809 struct scatterlist *scatter,
810 int n_elem)
811{
812 struct device *dev = &hisi_hba->pdev->dev;
813 struct scatterlist *sg;
814 int i;
815
816 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
817 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
818 n_elem);
819 return -EINVAL;
820 }
821
822 slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
823 &slot->sge_page_dma);
824 if (!slot->sge_page)
825 return -ENOMEM;
826
827 for_each_sg(scatter, sg, n_elem, i) {
828 struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
829
830 entry->addr = cpu_to_le64(sg_dma_address(sg));
831 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
832 entry->data_len = cpu_to_le32(sg_dma_len(sg));
833 entry->data_off = 0;
834 }
835
836 hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
837
838 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
839
840 return 0;
841}
842
c2d89392
JG		 843static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
844 struct hisi_sas_slot *slot)
845{
846 struct sas_task *task = slot->task;
847 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
848 struct domain_device *device = task->dev;
849 struct device *dev = &hisi_hba->pdev->dev;
850 struct hisi_sas_port *port = slot->port;
851 struct scatterlist *sg_req, *sg_resp;
852 struct hisi_sas_device *sas_dev = device->lldd_dev;
853 dma_addr_t req_dma_addr;
854 unsigned int req_len, resp_len;
855 int elem, rc;
856
857 /*
858 * DMA-map SMP request, response buffers
859 */
860 /* req */
861 sg_req = &task->smp_task.smp_req;
862 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
863 if (!elem)
864 return -ENOMEM;
865 req_len = sg_dma_len(sg_req);
866 req_dma_addr = sg_dma_address(sg_req);
867
868 /* resp */
869 sg_resp = &task->smp_task.smp_resp;
870 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
871 if (!elem) {
872 rc = -ENOMEM;
873 goto err_out_req;
874 }
875 resp_len = sg_dma_len(sg_resp);
876 if ((req_len & 0x3) || (resp_len & 0x3)) {
877 rc = -EINVAL;
878 goto err_out_resp;
879 }
880
881 /* create header */
882 /* dw0 */
883 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
884 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
885 (2 << CMD_HDR_CMD_OFF)); /* smp */
886
887 /* map itct entry */
888 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
889 (1 << CMD_HDR_FRAME_TYPE_OFF) |
890 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
891
892 /* dw2 */
893 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
894 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
895 CMD_HDR_MRFL_OFF));
896
897 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
898
899 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
900 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
901
902 return 0;
903
904err_out_resp:
905 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
906 DMA_FROM_DEVICE);
907err_out_req:
908 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
909 DMA_TO_DEVICE);
910 return rc;
911}
912
8c36e31d
JG		 913static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
914 struct hisi_sas_slot *slot, int is_tmf,
915 struct hisi_sas_tmf_task *tmf)
916{
917 struct sas_task *task = slot->task;
918 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
919 struct domain_device *device = task->dev;
920 struct hisi_sas_device *sas_dev = device->lldd_dev;
921 struct hisi_sas_port *port = slot->port;
922 struct sas_ssp_task *ssp_task = &task->ssp_task;
923 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
924 int has_data = 0, rc, priority = is_tmf;
925 u8 *buf_cmd;
926 u32 dw1 = 0, dw2 = 0;
927
928 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
929 (2 << CMD_HDR_TLR_CTRL_OFF) |
930 (port->id << CMD_HDR_PORT_OFF) |
931 (priority << CMD_HDR_PRIORITY_OFF) |
932 (1 << CMD_HDR_CMD_OFF)); /* ssp */
933
934 dw1 = 1 << CMD_HDR_VDTL_OFF;
935 if (is_tmf) {
936 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
937 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
938 } else {
939 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
940 switch (scsi_cmnd->sc_data_direction) {
941 case DMA_TO_DEVICE:
942 has_data = 1;
943 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
944 break;
945 case DMA_FROM_DEVICE:
946 has_data = 1;
947 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
948 break;
949 default:
950 dw1 &= ~CMD_HDR_DIR_MSK;
951 }
952 }
953
954 /* map itct entry */
955 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
956 hdr->dw1 = cpu_to_le32(dw1);
957
958 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
959 + 3) / 4) << CMD_HDR_CFL_OFF) |
960 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
961 (2 << CMD_HDR_SG_MOD_OFF);
962 hdr->dw2 = cpu_to_le32(dw2);
963
964 hdr->transfer_tags = cpu_to_le32(slot->idx);
965
966 if (has_data) {
967 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
968 slot->n_elem);
969 if (rc)
970 return rc;
971 }
972
973 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
974 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
975 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
976
977 buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
978
979 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
980 if (!is_tmf) {
981 buf_cmd[9] = task->ssp_task.task_attr |
982 (task->ssp_task.task_prio << 3);
983 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
984 task->ssp_task.cmd->cmd_len);
985 } else {
986 buf_cmd[10] = tmf->tmf;
987 switch (tmf->tmf) {
988 case TMF_ABORT_TASK:
989 case TMF_QUERY_TASK:
990 buf_cmd[12] =
991 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
992 buf_cmd[13] =
993 tmf->tag_of_task_to_be_managed & 0xff;
994 break;
995 default:
996 break;
997 }
998 }
999
1000 return 0;
1001}
1002
6f2ff1a1
JG		 1003static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1004 struct hisi_sas_slot *slot)
1005{
1006 struct task_status_struct *ts = &task->task_status;
1007 struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf;
1008 struct dev_to_host_fis *d2h = slot->status_buffer +
1009 sizeof(struct hisi_sas_err_record);
1010
1011 resp->frame_len = sizeof(struct dev_to_host_fis);
1012 memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis));
1013
1014 ts->buf_valid_size = sizeof(*resp);
1015}
31a9cfa6
JG		 1016static int
1017slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot,
1018 int abort)
1019{
1020 struct sas_task *task = slot->task;
1021 struct hisi_sas_device *sas_dev;
1022 struct device *dev = &hisi_hba->pdev->dev;
1023 struct task_status_struct *ts;
1024 struct domain_device *device;
1025 enum exec_status sts;
1026 struct hisi_sas_complete_v2_hdr *complete_queue =
1027 hisi_hba->complete_hdr[slot->cmplt_queue];
1028 struct hisi_sas_complete_v2_hdr *complete_hdr =
1029 &complete_queue[slot->cmplt_queue_slot];
1030
1031 if (unlikely(!task || !task->lldd_task || !task->dev))
1032 return -EINVAL;
1033
1034 ts = &task->task_status;
1035 device = task->dev;
1036 sas_dev = device->lldd_dev;
1037
1038 task->task_state_flags &=
1039 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1040 task->task_state_flags |= SAS_TASK_STATE_DONE;
1041
1042 memset(ts, 0, sizeof(*ts));
1043 ts->resp = SAS_TASK_COMPLETE;
1044
1045 if (unlikely(!sas_dev || abort)) {
1046 if (!sas_dev)
1047 dev_dbg(dev, "slot complete: port has not device\n");
1048 ts->stat = SAS_PHY_DOWN;
1049 goto out;
1050 }
1051
1052 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
1053 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
1054 dev_dbg(dev, "%s slot %d has error info 0x%x\n",
1055 __func__, slot->cmplt_queue_slot,
1056 complete_hdr->dw0 & CMPLT_HDR_ERX_MSK);
1057
1058 goto out;
1059 }
1060
1061 switch (task->task_proto) {
1062 case SAS_PROTOCOL_SSP:
1063 {
1064 struct ssp_response_iu *iu = slot->status_buffer +
1065 sizeof(struct hisi_sas_err_record);
1066
1067 sas_ssp_task_response(dev, task, iu);
1068 break;
1069 }
1070 case SAS_PROTOCOL_SMP:
1071 {
1072 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1073 void *to;
1074
1075 ts->stat = SAM_STAT_GOOD;
1076 to = kmap_atomic(sg_page(sg_resp));
1077
1078 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1079 DMA_FROM_DEVICE);
1080 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1081 DMA_TO_DEVICE);
1082 memcpy(to + sg_resp->offset,
1083 slot->status_buffer +
1084 sizeof(struct hisi_sas_err_record),
1085 sg_dma_len(sg_resp));
1086 kunmap_atomic(to);
1087 break;
1088 }
1089 case SAS_PROTOCOL_SATA:
1090 case SAS_PROTOCOL_STP:
1091 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
6f2ff1a1
JG		 1092 {
1093 ts->stat = SAM_STAT_GOOD;
1094 sata_done_v2_hw(hisi_hba, task, slot);
1095 break;
1096 }
31a9cfa6
JG		 1097 default:
1098 ts->stat = SAM_STAT_CHECK_CONDITION;
1099 break;
1100 }
1101
1102 if (!slot->port->port_attached) {
1103 dev_err(dev, "slot complete: port %d has removed\n",
1104 slot->port->sas_port.id);
1105 ts->stat = SAS_PHY_DOWN;
1106 }
1107
1108out:
1109 if (sas_dev && sas_dev->running_req)
1110 sas_dev->running_req--;
1111
1112 hisi_sas_slot_task_free(hisi_hba, task, slot);
1113 sts = ts->stat;
1114
1115 if (task->task_done)
1116 task->task_done(task);
1117
1118 return sts;
1119}
1120
6f2ff1a1
JG		 1121static u8 get_ata_protocol(u8 cmd, int direction)
1122{
1123 switch (cmd) {
1124 case ATA_CMD_FPDMA_WRITE:
1125 case ATA_CMD_FPDMA_READ:
1126 return SATA_PROTOCOL_FPDMA;
1127
1128 case ATA_CMD_ID_ATA:
1129 case ATA_CMD_PMP_READ:
1130 case ATA_CMD_READ_LOG_EXT:
1131 case ATA_CMD_PIO_READ:
1132 case ATA_CMD_PIO_READ_EXT:
1133 case ATA_CMD_PMP_WRITE:
1134 case ATA_CMD_WRITE_LOG_EXT:
1135 case ATA_CMD_PIO_WRITE:
1136 case ATA_CMD_PIO_WRITE_EXT:
1137 return SATA_PROTOCOL_PIO;
1138
1139 case ATA_CMD_READ:
1140 case ATA_CMD_READ_EXT:
1141 case ATA_CMD_READ_LOG_DMA_EXT:
1142 case ATA_CMD_WRITE:
1143 case ATA_CMD_WRITE_EXT:
1144 case ATA_CMD_WRITE_QUEUED:
1145 case ATA_CMD_WRITE_LOG_DMA_EXT:
1146 return SATA_PROTOCOL_DMA;
1147
1148 case ATA_CMD_DOWNLOAD_MICRO:
1149 case ATA_CMD_DEV_RESET:
1150 case ATA_CMD_CHK_POWER:
1151 case ATA_CMD_FLUSH:
1152 case ATA_CMD_FLUSH_EXT:
1153 case ATA_CMD_VERIFY:
1154 case ATA_CMD_VERIFY_EXT:
1155 case ATA_CMD_SET_FEATURES:
1156 case ATA_CMD_STANDBY:
1157 case ATA_CMD_STANDBYNOW1:
1158 return SATA_PROTOCOL_NONDATA;
1159 default:
1160 if (direction == DMA_NONE)
1161 return SATA_PROTOCOL_NONDATA;
1162 return SATA_PROTOCOL_PIO;
1163 }
1164}
1165
1166static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag)
1167{
1168 struct ata_queued_cmd *qc = task->uldd_task;
1169
1170 if (qc) {
1171 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
1172 qc->tf.command == ATA_CMD_FPDMA_READ) {
1173 *tag = qc->tag;
1174 return 1;
1175 }
1176 }
1177 return 0;
1178}
1179
1180static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
1181 struct hisi_sas_slot *slot)
1182{
1183 struct sas_task *task = slot->task;
1184 struct domain_device *device = task->dev;
1185 struct domain_device *parent_dev = device->parent;
1186 struct hisi_sas_device *sas_dev = device->lldd_dev;
1187 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1188 struct hisi_sas_port *port = device->port->lldd_port;
1189 u8 *buf_cmd;
1190 int has_data = 0, rc = 0, hdr_tag = 0;
1191 u32 dw1 = 0, dw2 = 0;
1192
1193 /* create header */
1194 /* dw0 */
1195 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1196 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1197 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1198 else
1199 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1200
1201 /* dw1 */
1202 switch (task->data_dir) {
1203 case DMA_TO_DEVICE:
1204 has_data = 1;
1205 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1206 break;
1207 case DMA_FROM_DEVICE:
1208 has_data = 1;
1209 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1210 break;
1211 default:
1212 dw1 &= ~CMD_HDR_DIR_MSK;
1213 }
1214
1215 if (0 == task->ata_task.fis.command)
1216 dw1 |= 1 << CMD_HDR_RESET_OFF;
1217
1218 dw1 |= (get_ata_protocol(task->ata_task.fis.command, task->data_dir))
1219 << CMD_HDR_FRAME_TYPE_OFF;
1220 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1221 hdr->dw1 = cpu_to_le32(dw1);
1222
1223 /* dw2 */
1224 if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) {
1225 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1226 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1227 }
1228
1229 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1230 2 << CMD_HDR_SG_MOD_OFF;
1231 hdr->dw2 = cpu_to_le32(dw2);
1232
1233 /* dw3 */
1234 hdr->transfer_tags = cpu_to_le32(slot->idx);
1235
1236 if (has_data) {
1237 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1238 slot->n_elem);
1239 if (rc)
1240 return rc;
1241 }
1242
1243
1244 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1245 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
1246 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1247
1248 buf_cmd = slot->command_table;
1249
1250 if (likely(!task->ata_task.device_control_reg_update))
1251 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1252 /* fill in command FIS */
1253 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1254
1255 return 0;
1256}
1257
7911e66f
JG		 1258static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1259{
1260 int i, res = 0;
1261 u32 context, port_id, link_rate, hard_phy_linkrate;
1262 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1263 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1264 struct device *dev = &hisi_hba->pdev->dev;
1265 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1266 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
1267
1268 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1269
1270 /* Check for SATA dev */
1271 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1272 if (context & (1 << phy_no))
1273 goto end;
1274
1275 if (phy_no == 8) {
1276 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1277
1278 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1279 PORT_STATE_PHY8_PORT_NUM_OFF;
1280 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
1281 PORT_STATE_PHY8_CONN_RATE_OFF;
1282 } else {
1283 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1284 port_id = (port_id >> (4 * phy_no)) & 0xf;
1285 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1286 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1287 }
1288
1289 if (port_id == 0xf) {
1290 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1291 res = IRQ_NONE;
1292 goto end;
1293 }
1294
1295 for (i = 0; i < 6; i++) {
1296 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1297 RX_IDAF_DWORD0 + (i * 4));
1298 frame_rcvd[i] = __swab32(idaf);
1299 }
1300
1301 /* Get the linkrates */
1302 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1303 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1304 sas_phy->linkrate = link_rate;
1305 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1306 HARD_PHY_LINKRATE);
1307 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1308 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1309
1310 sas_phy->oob_mode = SAS_OOB_MODE;
1311 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
1312 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1313 phy->port_id = port_id;
1314 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1315 phy->phy_type |= PORT_TYPE_SAS;
1316 phy->phy_attached = 1;
1317 phy->identify.device_type = id->dev_type;
1318 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1319 if (phy->identify.device_type == SAS_END_DEVICE)
1320 phy->identify.target_port_protocols =
1321 SAS_PROTOCOL_SSP;
1322 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1323 phy->identify.target_port_protocols =
1324 SAS_PROTOCOL_SMP;
1325 queue_work(hisi_hba->wq, &phy->phyup_ws);
1326
1327end:
1328 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1329 CHL_INT0_SL_PHY_ENABLE_MSK);
1330 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1331
1332 return res;
1333}
1334
5473c060
JG		 1335static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1336{
1337 int res = 0;
1338 u32 phy_cfg, phy_state;
1339
1340 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1341
1342 phy_cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1343
1344 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1345
1346 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1347
1348 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1349 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1350
1351 return res;
1352}
1353
7911e66f
JG		 1354static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
1355{
1356 struct hisi_hba *hisi_hba = p;
1357 u32 irq_msk;
1358 int phy_no = 0;
1359 irqreturn_t res = IRQ_HANDLED;
1360
1361 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
1362 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
1363 while (irq_msk) {
1364 if (irq_msk & 1) {
1365 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1366 CHL_INT0);
1367
1368 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1369 /* phy up */
1370 if (phy_up_v2_hw(phy_no, hisi_hba)) {
1371 res = IRQ_NONE;
1372 goto end;
1373 }
1374
5473c060
JG		 1375 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1376 /* phy down */
1377 if (phy_down_v2_hw(phy_no, hisi_hba)) {
1378 res = IRQ_NONE;
1379 goto end;
1380 }
7911e66f
JG		 1381 }
1382 irq_msk >>= 1;
1383 phy_no++;
1384 }
1385
1386end:
1387 return res;
1388}
1389
d3bf3d84
JG		 1390static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1391{
1392 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1393 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1394 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1395 unsigned long flags;
1396
1397 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1398
1399 spin_lock_irqsave(&hisi_hba->lock, flags);
1400 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1401 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1402
1403 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1404 CHL_INT0_SL_RX_BCST_ACK_MSK);
1405 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1406}
1407
1408static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
1409{
1410 struct hisi_hba *hisi_hba = p;
1411 struct device *dev = &hisi_hba->pdev->dev;
1412 u32 ent_msk, ent_tmp, irq_msk;
1413 int phy_no = 0;
1414
1415 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1416 ent_tmp = ent_msk;
1417 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1418 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1419
1420 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
1421 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
1422
1423 while (irq_msk) {
1424 if (irq_msk & (1 << phy_no)) {
1425 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1426 CHL_INT0);
1427 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1428 CHL_INT1);
1429 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1430 CHL_INT2);
1431
1432 if (irq_value1) {
1433 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
1434 CHL_INT1_DMAC_TX_ECC_ERR_MSK))
1435 panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
1436 dev_name(dev), irq_value1);
1437
1438 hisi_sas_phy_write32(hisi_hba, phy_no,
1439 CHL_INT1, irq_value1);
1440 }
1441
1442 if (irq_value2)
1443 hisi_sas_phy_write32(hisi_hba, phy_no,
1444 CHL_INT2, irq_value2);
1445
1446
1447 if (irq_value0) {
1448 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
1449 phy_bcast_v2_hw(phy_no, hisi_hba);
1450
1451 hisi_sas_phy_write32(hisi_hba, phy_no,
1452 CHL_INT0, irq_value0
1453 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
1454 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1455 & (~CHL_INT0_NOT_RDY_MSK));
1456 }
1457 }
1458 irq_msk &= ~(1 << phy_no);
1459 phy_no++;
1460 }
1461
1462 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1463
1464 return IRQ_HANDLED;
1465}
1466
31a9cfa6
JG		 1467static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
1468{
1469 struct hisi_sas_cq *cq = p;
1470 struct hisi_hba *hisi_hba = cq->hisi_hba;
1471 struct hisi_sas_slot *slot;
1472 struct hisi_sas_itct *itct;
1473 struct hisi_sas_complete_v2_hdr *complete_queue;
1474 u32 irq_value, rd_point, wr_point, dev_id;
1475 int queue = cq->id;
1476
1477 complete_queue = hisi_hba->complete_hdr[queue];
1478 irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC);
1479
1480 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1481
1482 rd_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_RD_PTR +
1483 (0x14 * queue));
1484 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1485 (0x14 * queue));
1486
1487 while (rd_point != wr_point) {
1488 struct hisi_sas_complete_v2_hdr *complete_hdr;
1489 int iptt;
1490
1491 complete_hdr = &complete_queue[rd_point];
1492
1493 /* Check for NCQ completion */
1494 if (complete_hdr->act) {
1495 u32 act_tmp = complete_hdr->act;
1496 int ncq_tag_count = ffs(act_tmp);
1497
1498 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
1499 CMPLT_HDR_DEV_ID_OFF;
1500 itct = &hisi_hba->itct[dev_id];
1501
1502 /* The NCQ tags are held in the itct header */
1503 while (ncq_tag_count) {
1504 __le64 *ncq_tag = &itct->qw4_15[0];
1505
1506 ncq_tag_count -= 1;
1507 iptt = (ncq_tag[ncq_tag_count / 5]
1508 >> (ncq_tag_count % 5) * 12) & 0xfff;
1509
1510 slot = &hisi_hba->slot_info[iptt];
1511 slot->cmplt_queue_slot = rd_point;
1512 slot->cmplt_queue = queue;
1513 slot_complete_v2_hw(hisi_hba, slot, 0);
1514
1515 act_tmp &= ~(1 << ncq_tag_count);
1516 ncq_tag_count = ffs(act_tmp);
1517 }
1518 } else {
1519 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1520 slot = &hisi_hba->slot_info[iptt];
1521 slot->cmplt_queue_slot = rd_point;
1522 slot->cmplt_queue = queue;
1523 slot_complete_v2_hw(hisi_hba, slot, 0);
1524 }
1525
1526 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1527 rd_point = 0;
1528 }
1529
1530 /* update rd_point */
1531 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1532 return IRQ_HANDLED;
1533}
1534
d43f9cdb
JG		 1535static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
1536{
1537 struct hisi_sas_phy *phy = p;
1538 struct hisi_hba *hisi_hba = phy->hisi_hba;
1539 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1540 struct device *dev = &hisi_hba->pdev->dev;
1541 struct hisi_sas_initial_fis *initial_fis;
1542 struct dev_to_host_fis *fis;
1543 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
1544 irqreturn_t res = IRQ_HANDLED;
1545 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1546 int phy_no;
1547
1548 phy_no = sas_phy->id;
1549 initial_fis = &hisi_hba->initial_fis[phy_no];
1550 fis = &initial_fis->fis;
1551
1552 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1);
1553 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk | 1 << phy_no);
1554
1555 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1);
1556 ent_tmp = ent_int;
1557 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
1558 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
1559 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
1560 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, ent_tmp);
1561 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk);
1562 res = IRQ_NONE;
1563 goto end;
1564 }
1565
1566 if (unlikely(phy_no == 8)) {
1567 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1568
1569 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1570 PORT_STATE_PHY8_PORT_NUM_OFF;
1571 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
1572 PORT_STATE_PHY8_CONN_RATE_OFF;
1573 } else {
1574 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1575 port_id = (port_id >> (4 * phy_no)) & 0xf;
1576 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1577 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1578 }
1579
1580 if (port_id == 0xf) {
1581 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
1582 res = IRQ_NONE;
1583 goto end;
1584 }
1585
1586 sas_phy->linkrate = link_rate;
1587 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1588 HARD_PHY_LINKRATE);
1589 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1590 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1591
1592 sas_phy->oob_mode = SATA_OOB_MODE;
1593 /* Make up some unique SAS address */
1594 attached_sas_addr[0] = 0x50;
1595 attached_sas_addr[7] = phy_no;
1596 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
1597 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
1598 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1599 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1600 phy->port_id = port_id;
1601 phy->phy_type |= PORT_TYPE_SATA;
1602 phy->phy_attached = 1;
1603 phy->identify.device_type = SAS_SATA_DEV;
1604 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1605 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1606 queue_work(hisi_hba->wq, &phy->phyup_ws);
1607
1608end:
1609 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, ent_tmp);
1610 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk);
1611
1612 return res;
1613}
1614
7911e66f
JG		 1615static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
1616 int_phy_updown_v2_hw,
d3bf3d84 1617 int_chnl_int_v2_hw,
7911e66f
JG		 1618};
1619
1620/**
1621 * There is a limitation in the hip06 chipset that we need
1622 * to map in all mbigen interrupts, even if they are not used.
1623 */
1624static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
1625{
1626 struct platform_device *pdev = hisi_hba->pdev;
1627 struct device *dev = &pdev->dev;
1628 int i, irq, rc, irq_map[128];
1629
1630
1631 for (i = 0; i < 128; i++)
1632 irq_map[i] = platform_get_irq(pdev, i);
1633
1634 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
1635 int idx = i;
1636
1637 irq = irq_map[idx + 1]; /* Phy up/down is irq1 */
1638 if (!irq) {
1639 dev_err(dev, "irq init: fail map phy interrupt %d\n",
1640 idx);
1641 return -ENOENT;
1642 }
1643
1644 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
1645 DRV_NAME " phy", hisi_hba);
1646 if (rc) {
1647 dev_err(dev, "irq init: could not request "
1648 "phy interrupt %d, rc=%d\n",
1649 irq, rc);
1650 return -ENOENT;
1651 }
1652 }
1653
d43f9cdb
JG		 1654 for (i = 0; i < hisi_hba->n_phy; i++) {
1655 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1656 int idx = i + 72; /* First SATA interrupt is irq72 */
1657
1658 irq = irq_map[idx];
1659 if (!irq) {
1660 dev_err(dev, "irq init: fail map phy interrupt %d\n",
1661 idx);
1662 return -ENOENT;
1663 }
1664
1665 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
1666 DRV_NAME " sata", phy);
1667 if (rc) {
1668 dev_err(dev, "irq init: could not request "
1669 "sata interrupt %d, rc=%d\n",
1670 irq, rc);
1671 return -ENOENT;
1672 }
1673 }
31a9cfa6
JG		 1674
1675 for (i = 0; i < hisi_hba->queue_count; i++) {
1676 int idx = i + 96; /* First cq interrupt is irq96 */
1677
1678 irq = irq_map[idx];
1679 if (!irq) {
1680 dev_err(dev,
1681 "irq init: could not map cq interrupt %d\n",
1682 idx);
1683 return -ENOENT;
1684 }
1685 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
1686 DRV_NAME " cq", &hisi_hba->cq[i]);
1687 if (rc) {
1688 dev_err(dev,
1689 "irq init: could not request cq interrupt %d, rc=%d\n",
1690 irq, rc);
1691 return -ENOENT;
1692 }
1693 }
1694
7911e66f
JG		 1695 return 0;
1696}
1697
94eac9e1
JG		 1698static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
1699{
1700 int rc;
1701
1702 rc = hw_init_v2_hw(hisi_hba);
1703 if (rc)
1704 return rc;
1705
7911e66f
JG		 1706 rc = interrupt_init_v2_hw(hisi_hba);
1707 if (rc)
1708 return rc;
1709
29a20428
JG		 1710 phys_init_v2_hw(hisi_hba);
1711
94eac9e1
JG		 1712 return 0;
1713}
1714
3417ba8a 1715static const struct hisi_sas_hw hisi_sas_v2_hw = {
94eac9e1 1716 .hw_init = hisi_sas_v2_init,
85b2c3c0 1717 .setup_itct = setup_itct_v2_hw,
7911e66f 1718 .sl_notify = sl_notify_v2_hw,
5473c060 1719 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
85b2c3c0 1720 .free_device = free_device_v2_hw,
c2d89392 1721 .prep_smp = prep_smp_v2_hw,
8c36e31d 1722 .prep_ssp = prep_ssp_v2_hw,
6f2ff1a1 1723 .prep_stp = prep_ata_v2_hw,
8c36e31d
JG		 1724 .get_free_slot = get_free_slot_v2_hw,
1725 .start_delivery = start_delivery_v2_hw,
31a9cfa6 1726 .slot_complete = slot_complete_v2_hw,
94eac9e1
JG		 1727 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
1728 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3417ba8a
JG		 1729};
1730
1731static int hisi_sas_v2_probe(struct platform_device *pdev)
1732{
1733 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
1734}
1735
1736static int hisi_sas_v2_remove(struct platform_device *pdev)
1737{
1738 return hisi_sas_remove(pdev);
1739}
1740
1741static const struct of_device_id sas_v2_of_match[] = {
1742 { .compatible = "hisilicon,hip06-sas-v2",},
1743 {},
1744};
1745MODULE_DEVICE_TABLE(of, sas_v2_of_match);
1746
1747static struct platform_driver hisi_sas_v2_driver = {
1748 .probe = hisi_sas_v2_probe,
1749 .remove = hisi_sas_v2_remove,
1750 .driver = {
1751 .name = DRV_NAME,
1752 .of_match_table = sas_v2_of_match,
1753 },
1754};
1755
1756module_platform_driver(hisi_sas_v2_driver);
1757
1758MODULE_LICENSE("GPL");
1759MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
1760MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
1761MODULE_ALIAS("platform:" DRV_NAME);
Linux kernel - Deliverables
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