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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
94c7bc31 3 * Copyright 2016 Microsemi Corporation
1358f6dc
DB		 4 * Copyright 2014-2015 PMC-Sierra, Inc.
5 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
edd16368
SC		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
14 * NON INFRINGEMENT. See the GNU General Public License for more details.
15 *
94c7bc31 16 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
edd16368
SC		 17 *
18 */
19
20#include <linux/module.h>
21#include <linux/interrupt.h>
22#include <linux/types.h>
23#include <linux/pci.h>
e5a44df8 24#include <linux/pci-aspm.h>
edd16368
SC		 25#include <linux/kernel.h>
26#include <linux/slab.h>
27#include <linux/delay.h>
28#include <linux/fs.h>
29#include <linux/timer.h>
edd16368
SC		 30#include <linux/init.h>
31#include <linux/spinlock.h>
edd16368
SC		 32#include <linux/compat.h>
33#include <linux/blktrace_api.h>
34#include <linux/uaccess.h>
35#include <linux/io.h>
36#include <linux/dma-mapping.h>
37#include <linux/completion.h>
38#include <linux/moduleparam.h>
39#include <scsi/scsi.h>
40#include <scsi/scsi_cmnd.h>
41#include <scsi/scsi_device.h>
42#include <scsi/scsi_host.h>
667e23d4 43#include <scsi/scsi_tcq.h>
9437ac43 44#include <scsi/scsi_eh.h>
d04e62b9 45#include <scsi/scsi_transport_sas.h>
73153fe5 46#include <scsi/scsi_dbg.h>
edd16368
SC		 47#include <linux/cciss_ioctl.h>
48#include <linux/string.h>
49#include <linux/bitmap.h>
60063497 50#include <linux/atomic.h>
a0c12413 51#include <linux/jiffies.h>
42a91641 52#include <linux/percpu-defs.h>
094963da 53#include <linux/percpu.h>
2b08b3e9 54#include <asm/unaligned.h>
283b4a9b 55#include <asm/div64.h>
edd16368
SC		 56#include "hpsa_cmd.h"
57#include "hpsa.h"
58
ec2c3aa9
DB		 59/*
60 * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.'
61 * with an optional trailing '-' followed by a byte value (0-255).
62 */
ff54aee4 63#define HPSA_DRIVER_VERSION "3.4.16-0"
edd16368 64#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 65#define HPSA "hpsa"
edd16368 66
007e7aa9
RE		 67/* How long to wait for CISS doorbell communication */
68#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
69#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
70#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
71#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 72#define MAX_IOCTL_CONFIG_WAIT 1000
73
74/*define how many times we will try a command because of bus resets */
75#define MAX_CMD_RETRIES 3
76
77/* Embedded module documentation macros - see modules.h */
78MODULE_AUTHOR("Hewlett-Packard Company");
79MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
80 HPSA_DRIVER_VERSION);
81MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
82MODULE_VERSION(HPSA_DRIVER_VERSION);
83MODULE_LICENSE("GPL");
84
85static int hpsa_allow_any;
86module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
87MODULE_PARM_DESC(hpsa_allow_any,
88 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 89static int hpsa_simple_mode;
90module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
91MODULE_PARM_DESC(hpsa_simple_mode,
92 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 93
94/* define the PCI info for the cards we can control */
95static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 131 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
132 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
133 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
134 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
135 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
fdfa4b6d 136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
cbb47dcb
DB		 137 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
138 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
139 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
140 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
141 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
8e616a5e
SC		 142 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
143 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
144 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
145 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
146 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 147 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 148 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 149 {0,}
150};
151
152MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
153
154/* board_id = Subsystem Device ID & Vendor ID
155 * product = Marketing Name for the board
156 * access = Address of the struct of function pointers
157 */
158static struct board_type products[] = {
edd16368
SC		 159 {0x3241103C, "Smart Array P212", &SA5_access},
160 {0x3243103C, "Smart Array P410", &SA5_access},
161 {0x3245103C, "Smart Array P410i", &SA5_access},
162 {0x3247103C, "Smart Array P411", &SA5_access},
163 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 164 {0x324A103C, "Smart Array P712m", &SA5_access},
165 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 166 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 167 {0x3350103C, "Smart Array P222", &SA5_access},
168 {0x3351103C, "Smart Array P420", &SA5_access},
169 {0x3352103C, "Smart Array P421", &SA5_access},
170 {0x3353103C, "Smart Array P822", &SA5_access},
171 {0x3354103C, "Smart Array P420i", &SA5_access},
172 {0x3355103C, "Smart Array P220i", &SA5_access},
173 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 174 {0x1921103C, "Smart Array P830i", &SA5_access},
175 {0x1922103C, "Smart Array P430", &SA5_access},
176 {0x1923103C, "Smart Array P431", &SA5_access},
177 {0x1924103C, "Smart Array P830", &SA5_access},
178 {0x1926103C, "Smart Array P731m", &SA5_access},
179 {0x1928103C, "Smart Array P230i", &SA5_access},
180 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 181 {0x21BD103C, "Smart Array P244br", &SA5_access},
182 {0x21BE103C, "Smart Array P741m", &SA5_access},
183 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
184 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 185 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 186 {0x21C2103C, "Smart Array P440", &SA5_access},
187 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 188 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 189 {0x21C5103C, "Smart Array P841", &SA5_access},
190 {0x21C6103C, "Smart HBA H244br", &SA5_access},
191 {0x21C7103C, "Smart HBA H240", &SA5_access},
192 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 193 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 194 {0x21CA103C, "Smart Array P246br", &SA5_access},
195 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 196 {0x21CC103C, "Smart Array", &SA5_access},
197 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 198 {0x21CE103C, "Smart HBA", &SA5_access},
fdfa4b6d 199 {0x05809005, "SmartHBA-SA", &SA5_access},
cbb47dcb
DB		 200 {0x05819005, "SmartHBA-SA 8i", &SA5_access},
201 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
202 {0x05839005, "SmartHBA-SA 8e", &SA5_access},
203 {0x05849005, "SmartHBA-SA 16i", &SA5_access},
204 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
8e616a5e
SC		 205 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
206 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
207 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
208 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
209 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 210 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
211};
212
d04e62b9
KB		 213static struct scsi_transport_template *hpsa_sas_transport_template;
214static int hpsa_add_sas_host(struct ctlr_info *h);
215static void hpsa_delete_sas_host(struct ctlr_info *h);
216static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
217 struct hpsa_scsi_dev_t *device);
218static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device);
219static struct hpsa_scsi_dev_t
220 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
221 struct sas_rphy *rphy);
222
a58e7e53
WS		 223#define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
224static const struct scsi_cmnd hpsa_cmd_busy;
225#define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
226static const struct scsi_cmnd hpsa_cmd_idle;
edd16368
SC		 227static int number_of_controllers;
228
10f66018
SC		 229static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
230static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 231static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 232
233#ifdef CONFIG_COMPAT
42a91641
DB		 234static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
235 void __user *arg);
edd16368
SC		 236#endif
237
238static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 239static struct CommandList *cmd_alloc(struct ctlr_info *h);
73153fe5
WS		 240static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
241static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
242 struct scsi_cmnd *scmd);
a2dac136 243static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 244 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 245 int cmd_type);
2c143342 246static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 247#define VPD_PAGE (1 << 8)
b48d9804 248#define HPSA_SIMPLE_ERROR_BITS 0x03
edd16368 249
f281233d 250static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 251static void hpsa_scan_start(struct Scsi_Host *);
252static int hpsa_scan_finished(struct Scsi_Host *sh,
253 unsigned long elapsed_time);
7c0a0229 254static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 255
256static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 257static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 258static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 259static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 260static void hpsa_slave_destroy(struct scsi_device *sdev);
261
8aa60681 262static void hpsa_update_scsi_devices(struct ctlr_info *h);
edd16368
SC		 263static int check_for_unit_attention(struct ctlr_info *h,
264 struct CommandList *c);
265static void check_ioctl_unit_attention(struct ctlr_info *h,
266 struct CommandList *c);
303932fd
DB		 267/* performant mode helper functions */
268static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 269 int nsgs, int min_blocks, u32 *bucket_map);
105a3dbc
RE		 270static void hpsa_free_performant_mode(struct ctlr_info *h);
271static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 272static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 273static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
274 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
275 u64 *cfg_offset);
276static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
277 unsigned long *memory_bar);
278static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
279static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
280 int wait_for_ready);
75167d2c 281static inline void finish_cmd(struct CommandList *c);
c706a795 282static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 283#define BOARD_NOT_READY 0
284#define BOARD_READY 1
23100dd9 285static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 286static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 287static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
288 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 289 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 290static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 291static u32 lockup_detected(struct ctlr_info *h);
292static int detect_controller_lockup(struct ctlr_info *h);
c2adae44 293static void hpsa_disable_rld_caching(struct ctlr_info *h);
d04e62b9
KB		 294static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
295 struct ReportExtendedLUNdata *buf, int bufsize);
34592254 296static int hpsa_luns_changed(struct ctlr_info *h);
ba74fdc4
DB		 297static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
298 struct hpsa_scsi_dev_t *dev,
299 unsigned char *scsi3addr);
edd16368 300
edd16368
SC		 301static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
302{
303 unsigned long *priv = shost_priv(sdev->host);
304 return (struct ctlr_info *) *priv;
305}
306
a23513e8
SC		 307static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
308{
309 unsigned long *priv = shost_priv(sh);
310 return (struct ctlr_info *) *priv;
311}
312
a58e7e53
WS		 313static inline bool hpsa_is_cmd_idle(struct CommandList *c)
314{
315 return c->scsi_cmd == SCSI_CMD_IDLE;
316}
317
d604f533
WS		 318static inline bool hpsa_is_pending_event(struct CommandList *c)
319{
320 return c->abort_pending || c->reset_pending;
321}
322
9437ac43
SC		 323/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
324static void decode_sense_data(const u8 *sense_data, int sense_data_len,
325 u8 *sense_key, u8 *asc, u8 *ascq)
326{
327 struct scsi_sense_hdr sshdr;
328 bool rc;
329
330 *sense_key = -1;
331 *asc = -1;
332 *ascq = -1;
333
334 if (sense_data_len < 1)
335 return;
336
337 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
338 if (rc) {
339 *sense_key = sshdr.sense_key;
340 *asc = sshdr.asc;
341 *ascq = sshdr.ascq;
342 }
343}
344
edd16368
SC		 345static int check_for_unit_attention(struct ctlr_info *h,
346 struct CommandList *c)
347{
9437ac43
SC		 348 u8 sense_key, asc, ascq;
349 int sense_len;
350
351 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
352 sense_len = sizeof(c->err_info->SenseInfo);
353 else
354 sense_len = c->err_info->SenseLen;
355
356 decode_sense_data(c->err_info->SenseInfo, sense_len,
357 &sense_key, &asc, &ascq);
81c27557 358 if (sense_key != UNIT_ATTENTION || asc == 0xff)
edd16368
SC		 359 return 0;
360
9437ac43 361 switch (asc) {
edd16368 362 case STATE_CHANGED:
9437ac43 363 dev_warn(&h->pdev->dev,
2946e82b
RE		 364 "%s: a state change detected, command retried\n",
365 h->devname);
edd16368
SC		 366 break;
367 case LUN_FAILED:
7f73695a 368 dev_warn(&h->pdev->dev,
2946e82b 369 "%s: LUN failure detected\n", h->devname);
edd16368
SC		 370 break;
371 case REPORT_LUNS_CHANGED:
7f73695a 372 dev_warn(&h->pdev->dev,
2946e82b 373 "%s: report LUN data changed\n", h->devname);
edd16368 374 /*
4f4eb9f1
ST		 375 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
376 * target (array) devices.
edd16368
SC		 377 */
378 break;
379 case POWER_OR_RESET:
2946e82b
RE		 380 dev_warn(&h->pdev->dev,
381 "%s: a power on or device reset detected\n",
382 h->devname);
edd16368
SC		 383 break;
384 case UNIT_ATTENTION_CLEARED:
2946e82b
RE		 385 dev_warn(&h->pdev->dev,
386 "%s: unit attention cleared by another initiator\n",
387 h->devname);
edd16368
SC		 388 break;
389 default:
2946e82b
RE		 390 dev_warn(&h->pdev->dev,
391 "%s: unknown unit attention detected\n",
392 h->devname);
edd16368
SC		 393 break;
394 }
395 return 1;
396}
397
852af20a
MB		 398static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
399{
400 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
401 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
402 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
403 return 0;
404 dev_warn(&h->pdev->dev, HPSA "device busy");
405 return 1;
406}
407
e985c58f
SC		 408static u32 lockup_detected(struct ctlr_info *h);
409static ssize_t host_show_lockup_detected(struct device *dev,
410 struct device_attribute *attr, char *buf)
411{
412 int ld;
413 struct ctlr_info *h;
414 struct Scsi_Host *shost = class_to_shost(dev);
415
416 h = shost_to_hba(shost);
417 ld = lockup_detected(h);
418
419 return sprintf(buf, "ld=%d\n", ld);
420}
421
da0697bd
ST		 422static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
423 struct device_attribute *attr,
424 const char *buf, size_t count)
425{
426 int status, len;
427 struct ctlr_info *h;
428 struct Scsi_Host *shost = class_to_shost(dev);
429 char tmpbuf[10];
430
431 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
432 return -EACCES;
433 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
434 strncpy(tmpbuf, buf, len);
435 tmpbuf[len] = '\0';
436 if (sscanf(tmpbuf, "%d", &status) != 1)
437 return -EINVAL;
438 h = shost_to_hba(shost);
439 h->acciopath_status = !!status;
440 dev_warn(&h->pdev->dev,
441 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
442 h->acciopath_status ? "enabled" : "disabled");
443 return count;
444}
445
2ba8bfc8
SC		 446static ssize_t host_store_raid_offload_debug(struct device *dev,
447 struct device_attribute *attr,
448 const char *buf, size_t count)
449{
450 int debug_level, len;
451 struct ctlr_info *h;
452 struct Scsi_Host *shost = class_to_shost(dev);
453 char tmpbuf[10];
454
455 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
456 return -EACCES;
457 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
458 strncpy(tmpbuf, buf, len);
459 tmpbuf[len] = '\0';
460 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
461 return -EINVAL;
462 if (debug_level < 0)
463 debug_level = 0;
464 h = shost_to_hba(shost);
465 h->raid_offload_debug = debug_level;
466 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
467 h->raid_offload_debug);
468 return count;
469}
470
edd16368
SC		 471static ssize_t host_store_rescan(struct device *dev,
472 struct device_attribute *attr,
473 const char *buf, size_t count)
474{
475 struct ctlr_info *h;
476 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 477 h = shost_to_hba(shost);
31468401 478 hpsa_scan_start(h->scsi_host);
edd16368
SC		 479 return count;
480}
481
d28ce020
SC		 482static ssize_t host_show_firmware_revision(struct device *dev,
483 struct device_attribute *attr, char *buf)
484{
485 struct ctlr_info *h;
486 struct Scsi_Host *shost = class_to_shost(dev);
487 unsigned char *fwrev;
488
489 h = shost_to_hba(shost);
490 if (!h->hba_inquiry_data)
491 return 0;
492 fwrev = &h->hba_inquiry_data[32];
493 return snprintf(buf, 20, "%c%c%c%c\n",
494 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
495}
496
94a13649
SC		 497static ssize_t host_show_commands_outstanding(struct device *dev,
498 struct device_attribute *attr, char *buf)
499{
500 struct Scsi_Host *shost = class_to_shost(dev);
501 struct ctlr_info *h = shost_to_hba(shost);
502
0cbf768e
SC		 503 return snprintf(buf, 20, "%d\n",
504 atomic_read(&h->commands_outstanding));
94a13649
SC		 505}
506
745a7a25
SC		 507static ssize_t host_show_transport_mode(struct device *dev,
508 struct device_attribute *attr, char *buf)
509{
510 struct ctlr_info *h;
511 struct Scsi_Host *shost = class_to_shost(dev);
512
513 h = shost_to_hba(shost);
514 return snprintf(buf, 20, "%s\n",
960a30e7 515 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 516 "performant" : "simple");
517}
518
da0697bd
ST		 519static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
520 struct device_attribute *attr, char *buf)
521{
522 struct ctlr_info *h;
523 struct Scsi_Host *shost = class_to_shost(dev);
524
525 h = shost_to_hba(shost);
526 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
527 (h->acciopath_status == 1) ? "enabled" : "disabled");
528}
529
46380786 530/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 531static u32 unresettable_controller[] = {
532 0x324a103C, /* Smart Array P712m */
9b5c48c2 533 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 534 0x3223103C, /* Smart Array P800 */
535 0x3234103C, /* Smart Array P400 */
536 0x3235103C, /* Smart Array P400i */
537 0x3211103C, /* Smart Array E200i */
538 0x3212103C, /* Smart Array E200 */
539 0x3213103C, /* Smart Array E200i */
540 0x3214103C, /* Smart Array E200i */
541 0x3215103C, /* Smart Array E200i */
542 0x3237103C, /* Smart Array E500 */
543 0x323D103C, /* Smart Array P700m */
7af0abbc 544 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 545 0x409C0E11, /* Smart Array 6400 */
546 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 547 0x40700E11, /* Smart Array 5300 */
548 0x40820E11, /* Smart Array 532 */
549 0x40830E11, /* Smart Array 5312 */
550 0x409A0E11, /* Smart Array 641 */
551 0x409B0E11, /* Smart Array 642 */
552 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 553};
554
46380786
SC		 555/* List of controllers which cannot even be soft reset */
556static u32 soft_unresettable_controller[] = {
7af0abbc 557 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 558 0x40700E11, /* Smart Array 5300 */
559 0x40820E11, /* Smart Array 532 */
560 0x40830E11, /* Smart Array 5312 */
561 0x409A0E11, /* Smart Array 641 */
562 0x409B0E11, /* Smart Array 642 */
563 0x40910E11, /* Smart Array 6i */
46380786
SC		 564 /* Exclude 640x boards. These are two pci devices in one slot
565 * which share a battery backed cache module. One controls the
566 * cache, the other accesses the cache through the one that controls
567 * it. If we reset the one controlling the cache, the other will
568 * likely not be happy. Just forbid resetting this conjoined mess.
569 * The 640x isn't really supported by hpsa anyway.
570 */
571 0x409C0E11, /* Smart Array 6400 */
572 0x409D0E11, /* Smart Array 6400 EM */
573};
574
9b5c48c2
SC		 575static u32 needs_abort_tags_swizzled[] = {
576 0x323D103C, /* Smart Array P700m */
577 0x324a103C, /* Smart Array P712m */
578 0x324b103C, /* SmartArray P711m */
579};
580
581static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 582{
583 int i;
584
9b5c48c2
SC		 585 for (i = 0; i < nelems; i++)
586 if (a[i] == board_id)
587 return 1;
588 return 0;
46380786
SC		 589}
590
9b5c48c2 591static int ctlr_is_hard_resettable(u32 board_id)
46380786 592{
9b5c48c2
SC		 593 return !board_id_in_array(unresettable_controller,
594 ARRAY_SIZE(unresettable_controller), board_id);
595}
46380786 596
9b5c48c2
SC		 597static int ctlr_is_soft_resettable(u32 board_id)
598{
599 return !board_id_in_array(soft_unresettable_controller,
600 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 601}
602
46380786
SC		 603static int ctlr_is_resettable(u32 board_id)
604{
605 return ctlr_is_hard_resettable(board_id) ||
606 ctlr_is_soft_resettable(board_id);
607}
608
9b5c48c2
SC		 609static int ctlr_needs_abort_tags_swizzled(u32 board_id)
610{
611 return board_id_in_array(needs_abort_tags_swizzled,
612 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
613}
614
941b1cda
SC		 615static ssize_t host_show_resettable(struct device *dev,
616 struct device_attribute *attr, char *buf)
617{
618 struct ctlr_info *h;
619 struct Scsi_Host *shost = class_to_shost(dev);
620
621 h = shost_to_hba(shost);
46380786 622 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 623}
624
edd16368
SC		 625static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
626{
627 return (scsi3addr[3] & 0xC0) == 0x40;
628}
629
f2ef0ce7 630static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
7c59a0d4 631 "1(+0)ADM", "UNKNOWN", "PHYS DRV"
edd16368 632};
6b80b18f
ST		 633#define HPSA_RAID_0 0
634#define HPSA_RAID_4 1
635#define HPSA_RAID_1 2 /* also used for RAID 10 */
636#define HPSA_RAID_5 3 /* also used for RAID 50 */
637#define HPSA_RAID_51 4
638#define HPSA_RAID_6 5 /* also used for RAID 60 */
639#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
7c59a0d4
DB		 640#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2)
641#define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1)
edd16368 642
f3f01730
KB		 643static inline bool is_logical_device(struct hpsa_scsi_dev_t *device)
644{
645 return !device->physical_device;
646}
edd16368
SC		 647
648static ssize_t raid_level_show(struct device *dev,
649 struct device_attribute *attr, char *buf)
650{
651 ssize_t l = 0;
82a72c0a 652 unsigned char rlevel;
edd16368
SC		 653 struct ctlr_info *h;
654 struct scsi_device *sdev;
655 struct hpsa_scsi_dev_t *hdev;
656 unsigned long flags;
657
658 sdev = to_scsi_device(dev);
659 h = sdev_to_hba(sdev);
660 spin_lock_irqsave(&h->lock, flags);
661 hdev = sdev->hostdata;
662 if (!hdev) {
663 spin_unlock_irqrestore(&h->lock, flags);
664 return -ENODEV;
665 }
666
667 /* Is this even a logical drive? */
f3f01730 668 if (!is_logical_device(hdev)) {
edd16368
SC		 669 spin_unlock_irqrestore(&h->lock, flags);
670 l = snprintf(buf, PAGE_SIZE, "N/A\n");
671 return l;
672 }
673
674 rlevel = hdev->raid_level;
675 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 676 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 677 rlevel = RAID_UNKNOWN;
678 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
679 return l;
680}
681
682static ssize_t lunid_show(struct device *dev,
683 struct device_attribute *attr, char *buf)
684{
685 struct ctlr_info *h;
686 struct scsi_device *sdev;
687 struct hpsa_scsi_dev_t *hdev;
688 unsigned long flags;
689 unsigned char lunid[8];
690
691 sdev = to_scsi_device(dev);
692 h = sdev_to_hba(sdev);
693 spin_lock_irqsave(&h->lock, flags);
694 hdev = sdev->hostdata;
695 if (!hdev) {
696 spin_unlock_irqrestore(&h->lock, flags);
697 return -ENODEV;
698 }
699 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
700 spin_unlock_irqrestore(&h->lock, flags);
701 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
702 lunid[0], lunid[1], lunid[2], lunid[3],
703 lunid[4], lunid[5], lunid[6], lunid[7]);
704}
705
706static ssize_t unique_id_show(struct device *dev,
707 struct device_attribute *attr, char *buf)
708{
709 struct ctlr_info *h;
710 struct scsi_device *sdev;
711 struct hpsa_scsi_dev_t *hdev;
712 unsigned long flags;
713 unsigned char sn[16];
714
715 sdev = to_scsi_device(dev);
716 h = sdev_to_hba(sdev);
717 spin_lock_irqsave(&h->lock, flags);
718 hdev = sdev->hostdata;
719 if (!hdev) {
720 spin_unlock_irqrestore(&h->lock, flags);
721 return -ENODEV;
722 }
723 memcpy(sn, hdev->device_id, sizeof(sn));
724 spin_unlock_irqrestore(&h->lock, flags);
725 return snprintf(buf, 16 * 2 + 2,
726 "%02X%02X%02X%02X%02X%02X%02X%02X"
727 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
728 sn[0], sn[1], sn[2], sn[3],
729 sn[4], sn[5], sn[6], sn[7],
730 sn[8], sn[9], sn[10], sn[11],
731 sn[12], sn[13], sn[14], sn[15]);
732}
733
ded1be4a
JH		 734static ssize_t sas_address_show(struct device *dev,
735 struct device_attribute *attr, char *buf)
736{
737 struct ctlr_info *h;
738 struct scsi_device *sdev;
739 struct hpsa_scsi_dev_t *hdev;
740 unsigned long flags;
741 u64 sas_address;
742
743 sdev = to_scsi_device(dev);
744 h = sdev_to_hba(sdev);
745 spin_lock_irqsave(&h->lock, flags);
746 hdev = sdev->hostdata;
747 if (!hdev || is_logical_device(hdev) || !hdev->expose_device) {
748 spin_unlock_irqrestore(&h->lock, flags);
749 return -ENODEV;
750 }
751 sas_address = hdev->sas_address;
752 spin_unlock_irqrestore(&h->lock, flags);
753
754 return snprintf(buf, PAGE_SIZE, "0x%016llx\n", sas_address);
755}
756
c1988684
ST		 757static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
758 struct device_attribute *attr, char *buf)
759{
760 struct ctlr_info *h;
761 struct scsi_device *sdev;
762 struct hpsa_scsi_dev_t *hdev;
763 unsigned long flags;
764 int offload_enabled;
765
766 sdev = to_scsi_device(dev);
767 h = sdev_to_hba(sdev);
768 spin_lock_irqsave(&h->lock, flags);
769 hdev = sdev->hostdata;
770 if (!hdev) {
771 spin_unlock_irqrestore(&h->lock, flags);
772 return -ENODEV;
773 }
774 offload_enabled = hdev->offload_enabled;
775 spin_unlock_irqrestore(&h->lock, flags);
776 return snprintf(buf, 20, "%d\n", offload_enabled);
777}
778
8270b862 779#define MAX_PATHS 8
8270b862
JH		 780static ssize_t path_info_show(struct device *dev,
781 struct device_attribute *attr, char *buf)
782{
783 struct ctlr_info *h;
784 struct scsi_device *sdev;
785 struct hpsa_scsi_dev_t *hdev;
786 unsigned long flags;
787 int i;
788 int output_len = 0;
789 u8 box;
790 u8 bay;
791 u8 path_map_index = 0;
792 char *active;
793 unsigned char phys_connector[2];
8270b862 794
8270b862
JH		 795 sdev = to_scsi_device(dev);
796 h = sdev_to_hba(sdev);
797 spin_lock_irqsave(&h->devlock, flags);
798 hdev = sdev->hostdata;
799 if (!hdev) {
800 spin_unlock_irqrestore(&h->devlock, flags);
801 return -ENODEV;
802 }
803
804 bay = hdev->bay;
805 for (i = 0; i < MAX_PATHS; i++) {
806 path_map_index = 1<<i;
807 if (i == hdev->active_path_index)
808 active = "Active";
809 else if (hdev->path_map & path_map_index)
810 active = "Inactive";
811 else
812 continue;
813
1faf072c
RV		 814 output_len += scnprintf(buf + output_len,
815 PAGE_SIZE - output_len,
816 "[%d:%d:%d:%d] %20.20s ",
8270b862
JH		 817 h->scsi_host->host_no,
818 hdev->bus, hdev->target, hdev->lun,
819 scsi_device_type(hdev->devtype));
820
cca8f13b 821 if (hdev->devtype == TYPE_RAID || is_logical_device(hdev)) {
2708f295 822 output_len += scnprintf(buf + output_len,
1faf072c
RV		 823 PAGE_SIZE - output_len,
824 "%s\n", active);
8270b862
JH		 825 continue;
826 }
827
828 box = hdev->box[i];
829 memcpy(&phys_connector, &hdev->phys_connector[i],
830 sizeof(phys_connector));
831 if (phys_connector[0] < '0')
832 phys_connector[0] = '0';
833 if (phys_connector[1] < '0')
834 phys_connector[1] = '0';
cca8f13b 835 output_len += scnprintf(buf + output_len,
1faf072c 836 PAGE_SIZE - output_len,
8270b862
JH		 837 "PORT: %.2s ",
838 phys_connector);
af15ed36
DB		 839 if ((hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) &&
840 hdev->expose_device) {
8270b862 841 if (box == 0 || box == 0xFF) {
2708f295 842 output_len += scnprintf(buf + output_len,
1faf072c 843 PAGE_SIZE - output_len,
8270b862
JH		 844 "BAY: %hhu %s\n",
845 bay, active);
846 } else {
2708f295 847 output_len += scnprintf(buf + output_len,
1faf072c 848 PAGE_SIZE - output_len,
8270b862
JH		 849 "BOX: %hhu BAY: %hhu %s\n",
850 box, bay, active);
851 }
852 } else if (box != 0 && box != 0xFF) {
2708f295 853 output_len += scnprintf(buf + output_len,
1faf072c 854 PAGE_SIZE - output_len, "BOX: %hhu %s\n",
8270b862
JH		 855 box, active);
856 } else
2708f295 857 output_len += scnprintf(buf + output_len,
1faf072c 858 PAGE_SIZE - output_len, "%s\n", active);
8270b862
JH		 859 }
860
861 spin_unlock_irqrestore(&h->devlock, flags);
1faf072c 862 return output_len;
8270b862
JH		 863}
864
3f5eac3a
SC		 865static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
866static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
867static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
868static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
ded1be4a 869static DEVICE_ATTR(sas_address, S_IRUGO, sas_address_show, NULL);
c1988684
ST		 870static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
871 host_show_hp_ssd_smart_path_enabled, NULL);
8270b862 872static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
da0697bd
ST		 873static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
874 host_show_hp_ssd_smart_path_status,
875 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 876static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
877 host_store_raid_offload_debug);
3f5eac3a
SC		 878static DEVICE_ATTR(firmware_revision, S_IRUGO,
879 host_show_firmware_revision, NULL);
880static DEVICE_ATTR(commands_outstanding, S_IRUGO,
881 host_show_commands_outstanding, NULL);
882static DEVICE_ATTR(transport_mode, S_IRUGO,
883 host_show_transport_mode, NULL);
941b1cda
SC		 884static DEVICE_ATTR(resettable, S_IRUGO,
885 host_show_resettable, NULL);
e985c58f
SC		 886static DEVICE_ATTR(lockup_detected, S_IRUGO,
887 host_show_lockup_detected, NULL);
3f5eac3a
SC		 888
889static struct device_attribute *hpsa_sdev_attrs[] = {
890 &dev_attr_raid_level,
891 &dev_attr_lunid,
892 &dev_attr_unique_id,
c1988684 893 &dev_attr_hp_ssd_smart_path_enabled,
8270b862 894 &dev_attr_path_info,
ded1be4a 895 &dev_attr_sas_address,
3f5eac3a
SC		 896 NULL,
897};
898
899static struct device_attribute *hpsa_shost_attrs[] = {
900 &dev_attr_rescan,
901 &dev_attr_firmware_revision,
902 &dev_attr_commands_outstanding,
903 &dev_attr_transport_mode,
941b1cda 904 &dev_attr_resettable,
da0697bd 905 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 906 &dev_attr_raid_offload_debug,
fb53c439 907 &dev_attr_lockup_detected,
3f5eac3a
SC		 908 NULL,
909};
910
41ce4c35
SC		 911#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
912 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
913
3f5eac3a
SC		 914static struct scsi_host_template hpsa_driver_template = {
915 .module = THIS_MODULE,
f79cfec6
SC		 916 .name = HPSA,
917 .proc_name = HPSA,
3f5eac3a
SC		 918 .queuecommand = hpsa_scsi_queue_command,
919 .scan_start = hpsa_scan_start,
920 .scan_finished = hpsa_scan_finished,
7c0a0229 921 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 922 .this_id = -1,
923 .use_clustering = ENABLE_CLUSTERING,
75167d2c 924 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 925 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
926 .ioctl = hpsa_ioctl,
927 .slave_alloc = hpsa_slave_alloc,
41ce4c35 928 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 929 .slave_destroy = hpsa_slave_destroy,
930#ifdef CONFIG_COMPAT
931 .compat_ioctl = hpsa_compat_ioctl,
932#endif
933 .sdev_attrs = hpsa_sdev_attrs,
934 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 935 .max_sectors = 8192,
54b2b50c 936 .no_write_same = 1,
3f5eac3a
SC		 937};
938
254f796b 939static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 940{
941 u32 a;
072b0518 942 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 943
e1f7de0c
MG		 944 if (h->transMethod & CFGTBL_Trans_io_accel1)
945 return h->access.command_completed(h, q);
946
3f5eac3a 947 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 948 return h->access.command_completed(h, q);
3f5eac3a 949
254f796b
MG		 950 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
951 a = rq->head[rq->current_entry];
952 rq->current_entry++;
0cbf768e 953 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 954 } else {
955 a = FIFO_EMPTY;
956 }
957 /* Check for wraparound */
254f796b
MG		 958 if (rq->current_entry == h->max_commands) {
959 rq->current_entry = 0;
960 rq->wraparound ^= 1;
3f5eac3a
SC		 961 }
962 return a;
963}
964
c349775e
ST		 965/*
966 * There are some special bits in the bus address of the
967 * command that we have to set for the controller to know
968 * how to process the command:
969 *
970 * Normal performant mode:
971 * bit 0: 1 means performant mode, 0 means simple mode.
972 * bits 1-3 = block fetch table entry
973 * bits 4-6 = command type (== 0)
974 *
975 * ioaccel1 mode:
976 * bit 0 = "performant mode" bit.
977 * bits 1-3 = block fetch table entry
978 * bits 4-6 = command type (== 110)
979 * (command type is needed because ioaccel1 mode
980 * commands are submitted through the same register as normal
981 * mode commands, so this is how the controller knows whether
982 * the command is normal mode or ioaccel1 mode.)
983 *
984 * ioaccel2 mode:
985 * bit 0 = "performant mode" bit.
986 * bits 1-4 = block fetch table entry (note extra bit)
987 * bits 4-6 = not needed, because ioaccel2 mode has
988 * a separate special register for submitting commands.
989 */
990
25163bd5
WS		 991/*
992 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 993 * set bit 0 for pull model, bits 3-1 for block fetch
994 * register number
995 */
25163bd5
WS		 996#define DEFAULT_REPLY_QUEUE (-1)
997static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
998 int reply_queue)
3f5eac3a 999{
254f796b 1000 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 1001 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 1002 if (unlikely(!h->msix_vector))
1003 return;
1004 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 1005 c->Header.ReplyQueue =
804a5cb5 1006 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 1007 else
1008 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 1009 }
3f5eac3a
SC		 1010}
1011
c349775e 1012static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1013 struct CommandList *c,
1014 int reply_queue)
c349775e
ST		 1015{
1016 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
1017
25163bd5
WS		 1018 /*
1019 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1020 * processor. This seems to give the best I/O throughput.
1021 */
25163bd5
WS		 1022 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1023 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
1024 else
1025 cp->ReplyQueue = reply_queue % h->nreply_queues;
1026 /*
1027 * Set the bits in the address sent down to include:
c349775e
ST		 1028 * - performant mode bit (bit 0)
1029 * - pull count (bits 1-3)
1030 * - command type (bits 4-6)
1031 */
1032 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
1033 IOACCEL1_BUSADDR_CMDTYPE;
1034}
1035
8be986cc
SC		 1036static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
1037 struct CommandList *c,
1038 int reply_queue)
1039{
1040 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
1041 &h->ioaccel2_cmd_pool[c->cmdindex];
1042
1043 /* Tell the controller to post the reply to the queue for this
1044 * processor. This seems to give the best I/O throughput.
1045 */
1046 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1047 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1048 else
1049 cp->reply_queue = reply_queue % h->nreply_queues;
1050 /* Set the bits in the address sent down to include:
1051 * - performant mode bit not used in ioaccel mode 2
1052 * - pull count (bits 0-3)
1053 * - command type isn't needed for ioaccel2
1054 */
1055 c->busaddr |= h->ioaccel2_blockFetchTable[0];
1056}
1057
c349775e 1058static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1059 struct CommandList *c,
1060 int reply_queue)
c349775e
ST		 1061{
1062 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
1063
25163bd5
WS		 1064 /*
1065 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1066 * processor. This seems to give the best I/O throughput.
1067 */
25163bd5
WS		 1068 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1069 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1070 else
1071 cp->reply_queue = reply_queue % h->nreply_queues;
1072 /*
1073 * Set the bits in the address sent down to include:
c349775e
ST		 1074 * - performant mode bit not used in ioaccel mode 2
1075 * - pull count (bits 0-3)
1076 * - command type isn't needed for ioaccel2
1077 */
1078 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
1079}
1080
e85c5974
SC		 1081static int is_firmware_flash_cmd(u8 *cdb)
1082{
1083 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
1084}
1085
1086/*
1087 * During firmware flash, the heartbeat register may not update as frequently
1088 * as it should. So we dial down lockup detection during firmware flash. and
1089 * dial it back up when firmware flash completes.
1090 */
1091#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
1092#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
1093static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
1094 struct CommandList *c)
1095{
1096 if (!is_firmware_flash_cmd(c->Request.CDB))
1097 return;
1098 atomic_inc(&h->firmware_flash_in_progress);
1099 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
1100}
1101
1102static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
1103 struct CommandList *c)
1104{
1105 if (is_firmware_flash_cmd(c->Request.CDB) &&
1106 atomic_dec_and_test(&h->firmware_flash_in_progress))
1107 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
1108}
1109
25163bd5
WS		 1110static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
1111 struct CommandList *c, int reply_queue)
3f5eac3a 1112{
c05e8866
SC		 1113 dial_down_lockup_detection_during_fw_flash(h, c);
1114 atomic_inc(&h->commands_outstanding);
c349775e
ST		 1115 switch (c->cmd_type) {
1116 case CMD_IOACCEL1:
25163bd5 1117 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 1118 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 1119 break;
1120 case CMD_IOACCEL2:
25163bd5 1121 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 1122 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e 1123 break;
8be986cc
SC		 1124 case IOACCEL2_TMF:
1125 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
1126 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1127 break;
c349775e 1128 default:
25163bd5 1129 set_performant_mode(h, c, reply_queue);
c05e8866 1130 h->access.submit_command(h, c);
c349775e 1131 }
3f5eac3a
SC		 1132}
1133
a58e7e53 1134static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
25163bd5 1135{
d604f533 1136 if (unlikely(hpsa_is_pending_event(c)))
a58e7e53
WS		 1137 return finish_cmd(c);
1138
25163bd5
WS		 1139 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
1140}
1141
3f5eac3a
SC		 1142static inline int is_hba_lunid(unsigned char scsi3addr[])
1143{
1144 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
1145}
1146
1147static inline int is_scsi_rev_5(struct ctlr_info *h)
1148{
1149 if (!h->hba_inquiry_data)
1150 return 0;
1151 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1152 return 1;
1153 return 0;
1154}
1155
edd16368
SC		 1156static int hpsa_find_target_lun(struct ctlr_info *h,
1157 unsigned char scsi3addr[], int bus, int *target, int *lun)
1158{
1159 /* finds an unused bus, target, lun for a new physical device
1160 * assumes h->devlock is held
1161 */
1162 int i, found = 0;
cfe5badc 1163 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 1164
263d9401 1165 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 1166
1167 for (i = 0; i < h->ndevices; i++) {
1168 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 1169 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 1170 }
1171
263d9401
AM		 1172 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1173 if (i < HPSA_MAX_DEVICES) {
1174 /* *bus = 1; */
1175 *target = i;
1176 *lun = 0;
1177 found = 1;
edd16368
SC		 1178 }
1179 return !found;
1180}
1181
1d33d85d 1182static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
0d96ef5f
WS		 1183 struct hpsa_scsi_dev_t *dev, char *description)
1184{
7c59a0d4
DB		 1185#define LABEL_SIZE 25
1186 char label[LABEL_SIZE];
1187
9975ec9d
DB		 1188 if (h == NULL || h->pdev == NULL || h->scsi_host == NULL)
1189 return;
1190
7c59a0d4
DB		 1191 switch (dev->devtype) {
1192 case TYPE_RAID:
1193 snprintf(label, LABEL_SIZE, "controller");
1194 break;
1195 case TYPE_ENCLOSURE:
1196 snprintf(label, LABEL_SIZE, "enclosure");
1197 break;
1198 case TYPE_DISK:
af15ed36 1199 case TYPE_ZBC:
7c59a0d4
DB		 1200 if (dev->external)
1201 snprintf(label, LABEL_SIZE, "external");
1202 else if (!is_logical_dev_addr_mode(dev->scsi3addr))
1203 snprintf(label, LABEL_SIZE, "%s",
1204 raid_label[PHYSICAL_DRIVE]);
1205 else
1206 snprintf(label, LABEL_SIZE, "RAID-%s",
1207 dev->raid_level > RAID_UNKNOWN ? "?" :
1208 raid_label[dev->raid_level]);
1209 break;
1210 case TYPE_ROM:
1211 snprintf(label, LABEL_SIZE, "rom");
1212 break;
1213 case TYPE_TAPE:
1214 snprintf(label, LABEL_SIZE, "tape");
1215 break;
1216 case TYPE_MEDIUM_CHANGER:
1217 snprintf(label, LABEL_SIZE, "changer");
1218 break;
1219 default:
1220 snprintf(label, LABEL_SIZE, "UNKNOWN");
1221 break;
1222 }
1223
0d96ef5f 1224 dev_printk(level, &h->pdev->dev,
7c59a0d4 1225 "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n",
0d96ef5f
WS		 1226 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1227 description,
1228 scsi_device_type(dev->devtype),
1229 dev->vendor,
1230 dev->model,
7c59a0d4 1231 label,
0d96ef5f
WS		 1232 dev->offload_config ? '+' : '-',
1233 dev->offload_enabled ? '+' : '-',
2a168208 1234 dev->expose_device);
0d96ef5f
WS		 1235}
1236
edd16368 1237/* Add an entry into h->dev[] array. */
8aa60681 1238static int hpsa_scsi_add_entry(struct ctlr_info *h,
edd16368
SC		 1239 struct hpsa_scsi_dev_t *device,
1240 struct hpsa_scsi_dev_t *added[], int *nadded)
1241{
1242 /* assumes h->devlock is held */
1243 int n = h->ndevices;
1244 int i;
1245 unsigned char addr1[8], addr2[8];
1246 struct hpsa_scsi_dev_t *sd;
1247
cfe5badc 1248 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1249 dev_err(&h->pdev->dev, "too many devices, some will be "
1250 "inaccessible.\n");
1251 return -1;
1252 }
1253
1254 /* physical devices do not have lun or target assigned until now. */
1255 if (device->lun != -1)
1256 /* Logical device, lun is already assigned. */
1257 goto lun_assigned;
1258
1259 /* If this device a non-zero lun of a multi-lun device
1260 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1261 * unit no, zero otherwise.
edd16368
SC		 1262 */
1263 if (device->scsi3addr[4] == 0) {
1264 /* This is not a non-zero lun of a multi-lun device */
1265 if (hpsa_find_target_lun(h, device->scsi3addr,
1266 device->bus, &device->target, &device->lun) != 0)
1267 return -1;
1268 goto lun_assigned;
1269 }
1270
1271 /* This is a non-zero lun of a multi-lun device.
1272 * Search through our list and find the device which
9a4178b7 1273 * has the same 8 byte LUN address, excepting byte 4 and 5.
edd16368
SC		 1274 * Assign the same bus and target for this new LUN.
1275 * Use the logical unit number from the firmware.
1276 */
1277 memcpy(addr1, device->scsi3addr, 8);
1278 addr1[4] = 0;
9a4178b7 1279 addr1[5] = 0;
edd16368
SC		 1280 for (i = 0; i < n; i++) {
1281 sd = h->dev[i];
1282 memcpy(addr2, sd->scsi3addr, 8);
1283 addr2[4] = 0;
9a4178b7 1284 addr2[5] = 0;
1285 /* differ only in byte 4 and 5? */
edd16368
SC		 1286 if (memcmp(addr1, addr2, 8) == 0) {
1287 device->bus = sd->bus;
1288 device->target = sd->target;
1289 device->lun = device->scsi3addr[4];
1290 break;
1291 }
1292 }
1293 if (device->lun == -1) {
1294 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1295 " suspect firmware bug or unsupported hardware "
1296 "configuration.\n");
1297 return -1;
1298 }
1299
1300lun_assigned:
1301
1302 h->dev[n] = device;
1303 h->ndevices++;
1304 added[*nadded] = device;
1305 (*nadded)++;
0d96ef5f 1306 hpsa_show_dev_msg(KERN_INFO, h, device,
2a168208 1307 device->expose_device ? "added" : "masked");
a473d86c
RE		 1308 device->offload_to_be_enabled = device->offload_enabled;
1309 device->offload_enabled = 0;
edd16368
SC		 1310 return 0;
1311}
1312
bd9244f7 1313/* Update an entry in h->dev[] array. */
8aa60681 1314static void hpsa_scsi_update_entry(struct ctlr_info *h,
bd9244f7
ST		 1315 int entry, struct hpsa_scsi_dev_t *new_entry)
1316{
a473d86c 1317 int offload_enabled;
bd9244f7
ST		 1318 /* assumes h->devlock is held */
1319 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1320
1321 /* Raid level changed. */
1322 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1323
03383736
DB		 1324 /* Raid offload parameters changed. Careful about the ordering. */
1325 if (new_entry->offload_config && new_entry->offload_enabled) {
1326 /*
1327 * if drive is newly offload_enabled, we want to copy the
1328 * raid map data first. If previously offload_enabled and
1329 * offload_config were set, raid map data had better be
1330 * the same as it was before. if raid map data is changed
1331 * then it had better be the case that
1332 * h->dev[entry]->offload_enabled is currently 0.
1333 */
1334 h->dev[entry]->raid_map = new_entry->raid_map;
1335 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1336 }
a3144e0b
JH		 1337 if (new_entry->hba_ioaccel_enabled) {
1338 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1339 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1340 }
1341 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1342 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1343 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1344 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1345
41ce4c35
SC		 1346 /*
1347 * We can turn off ioaccel offload now, but need to delay turning
1348 * it on until we can update h->dev[entry]->phys_disk[], but we
1349 * can't do that until all the devices are updated.
1350 */
1351 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1352 if (!new_entry->offload_enabled)
1353 h->dev[entry]->offload_enabled = 0;
1354
a473d86c
RE		 1355 offload_enabled = h->dev[entry]->offload_enabled;
1356 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1357 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1358 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1359}
1360
2a8ccf31 1361/* Replace an entry from h->dev[] array. */
8aa60681 1362static void hpsa_scsi_replace_entry(struct ctlr_info *h,
2a8ccf31
SC		 1363 int entry, struct hpsa_scsi_dev_t *new_entry,
1364 struct hpsa_scsi_dev_t *added[], int *nadded,
1365 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1366{
1367 /* assumes h->devlock is held */
cfe5badc 1368 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1369 removed[*nremoved] = h->dev[entry];
1370 (*nremoved)++;
01350d05
SC		 1371
1372 /*
1373 * New physical devices won't have target/lun assigned yet
1374 * so we need to preserve the values in the slot we are replacing.
1375 */
1376 if (new_entry->target == -1) {
1377 new_entry->target = h->dev[entry]->target;
1378 new_entry->lun = h->dev[entry]->lun;
1379 }
1380
2a8ccf31
SC		 1381 h->dev[entry] = new_entry;
1382 added[*nadded] = new_entry;
1383 (*nadded)++;
0d96ef5f 1384 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1385 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1386 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1387}
1388
edd16368 1389/* Remove an entry from h->dev[] array. */
8aa60681 1390static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
edd16368
SC		 1391 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1392{
1393 /* assumes h->devlock is held */
1394 int i;
1395 struct hpsa_scsi_dev_t *sd;
1396
cfe5badc 1397 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1398
1399 sd = h->dev[entry];
1400 removed[*nremoved] = h->dev[entry];
1401 (*nremoved)++;
1402
1403 for (i = entry; i < h->ndevices-1; i++)
1404 h->dev[i] = h->dev[i+1];
1405 h->ndevices--;
0d96ef5f 1406 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1407}
1408
1409#define SCSI3ADDR_EQ(a, b) ( \
1410 (a)[7] == (b)[7] && \
1411 (a)[6] == (b)[6] && \
1412 (a)[5] == (b)[5] && \
1413 (a)[4] == (b)[4] && \
1414 (a)[3] == (b)[3] && \
1415 (a)[2] == (b)[2] && \
1416 (a)[1] == (b)[1] && \
1417 (a)[0] == (b)[0])
1418
1419static void fixup_botched_add(struct ctlr_info *h,
1420 struct hpsa_scsi_dev_t *added)
1421{
1422 /* called when scsi_add_device fails in order to re-adjust
1423 * h->dev[] to match the mid layer's view.
1424 */
1425 unsigned long flags;
1426 int i, j;
1427
1428 spin_lock_irqsave(&h->lock, flags);
1429 for (i = 0; i < h->ndevices; i++) {
1430 if (h->dev[i] == added) {
1431 for (j = i; j < h->ndevices-1; j++)
1432 h->dev[j] = h->dev[j+1];
1433 h->ndevices--;
1434 break;
1435 }
1436 }
1437 spin_unlock_irqrestore(&h->lock, flags);
1438 kfree(added);
1439}
1440
1441static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1442 struct hpsa_scsi_dev_t *dev2)
1443{
edd16368
SC		 1444 /* we compare everything except lun and target as these
1445 * are not yet assigned. Compare parts likely
1446 * to differ first
1447 */
1448 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1449 sizeof(dev1->scsi3addr)) != 0)
1450 return 0;
1451 if (memcmp(dev1->device_id, dev2->device_id,
1452 sizeof(dev1->device_id)) != 0)
1453 return 0;
1454 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1455 return 0;
1456 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1457 return 0;
edd16368
SC		 1458 if (dev1->devtype != dev2->devtype)
1459 return 0;
edd16368
SC		 1460 if (dev1->bus != dev2->bus)
1461 return 0;
1462 return 1;
1463}
1464
bd9244f7
ST		 1465static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1466 struct hpsa_scsi_dev_t *dev2)
1467{
1468 /* Device attributes that can change, but don't mean
1469 * that the device is a different device, nor that the OS
1470 * needs to be told anything about the change.
1471 */
1472 if (dev1->raid_level != dev2->raid_level)
1473 return 1;
250fb125
SC		 1474 if (dev1->offload_config != dev2->offload_config)
1475 return 1;
1476 if (dev1->offload_enabled != dev2->offload_enabled)
1477 return 1;
93849508
DB		 1478 if (!is_logical_dev_addr_mode(dev1->scsi3addr))
1479 if (dev1->queue_depth != dev2->queue_depth)
1480 return 1;
bd9244f7
ST		 1481 return 0;
1482}
1483
edd16368
SC		 1484/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1485 * and return needle location in *index. If scsi3addr matches, but not
1486 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1487 * location in *index.
1488 * In the case of a minor device attribute change, such as RAID level, just
1489 * return DEVICE_UPDATED, along with the updated device's location in index.
1490 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1491 */
1492static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1493 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1494 int *index)
1495{
1496 int i;
1497#define DEVICE_NOT_FOUND 0
1498#define DEVICE_CHANGED 1
1499#define DEVICE_SAME 2
bd9244f7 1500#define DEVICE_UPDATED 3
1d33d85d
DB		 1501 if (needle == NULL)
1502 return DEVICE_NOT_FOUND;
1503
edd16368 1504 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1505 if (haystack[i] == NULL) /* previously removed. */
1506 continue;
edd16368
SC		 1507 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1508 *index = i;
bd9244f7
ST		 1509 if (device_is_the_same(needle, haystack[i])) {
1510 if (device_updated(needle, haystack[i]))
1511 return DEVICE_UPDATED;
edd16368 1512 return DEVICE_SAME;
bd9244f7 1513 } else {
9846590e
SC		 1514 /* Keep offline devices offline */
1515 if (needle->volume_offline)
1516 return DEVICE_NOT_FOUND;
edd16368 1517 return DEVICE_CHANGED;
bd9244f7 1518 }
edd16368
SC		 1519 }
1520 }
1521 *index = -1;
1522 return DEVICE_NOT_FOUND;
1523}
1524
9846590e
SC		 1525static void hpsa_monitor_offline_device(struct ctlr_info *h,
1526 unsigned char scsi3addr[])
1527{
1528 struct offline_device_entry *device;
1529 unsigned long flags;
1530
1531 /* Check to see if device is already on the list */
1532 spin_lock_irqsave(&h->offline_device_lock, flags);
1533 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1534 if (memcmp(device->scsi3addr, scsi3addr,
1535 sizeof(device->scsi3addr)) == 0) {
1536 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1537 return;
1538 }
1539 }
1540 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1541
1542 /* Device is not on the list, add it. */
1543 device = kmalloc(sizeof(*device), GFP_KERNEL);
1544 if (!device) {
1545 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1546 return;
1547 }
1548 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1549 spin_lock_irqsave(&h->offline_device_lock, flags);
1550 list_add_tail(&device->offline_list, &h->offline_device_list);
1551 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1552}
1553
1554/* Print a message explaining various offline volume states */
1555static void hpsa_show_volume_status(struct ctlr_info *h,
1556 struct hpsa_scsi_dev_t *sd)
1557{
1558 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1559 dev_info(&h->pdev->dev,
1560 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1561 h->scsi_host->host_no,
1562 sd->bus, sd->target, sd->lun);
1563 switch (sd->volume_offline) {
1564 case HPSA_LV_OK:
1565 break;
1566 case HPSA_LV_UNDERGOING_ERASE:
1567 dev_info(&h->pdev->dev,
1568 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1569 h->scsi_host->host_no,
1570 sd->bus, sd->target, sd->lun);
1571 break;
5ca01204
SB		 1572 case HPSA_LV_NOT_AVAILABLE:
1573 dev_info(&h->pdev->dev,
1574 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
1575 h->scsi_host->host_no,
1576 sd->bus, sd->target, sd->lun);
1577 break;
9846590e
SC		 1578 case HPSA_LV_UNDERGOING_RPI:
1579 dev_info(&h->pdev->dev,
5ca01204 1580 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
9846590e
SC		 1581 h->scsi_host->host_no,
1582 sd->bus, sd->target, sd->lun);
1583 break;
1584 case HPSA_LV_PENDING_RPI:
1585 dev_info(&h->pdev->dev,
5ca01204
SB		 1586 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1587 h->scsi_host->host_no,
1588 sd->bus, sd->target, sd->lun);
9846590e
SC		 1589 break;
1590 case HPSA_LV_ENCRYPTED_NO_KEY:
1591 dev_info(&h->pdev->dev,
1592 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1593 h->scsi_host->host_no,
1594 sd->bus, sd->target, sd->lun);
1595 break;
1596 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1597 dev_info(&h->pdev->dev,
1598 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1599 h->scsi_host->host_no,
1600 sd->bus, sd->target, sd->lun);
1601 break;
1602 case HPSA_LV_UNDERGOING_ENCRYPTION:
1603 dev_info(&h->pdev->dev,
1604 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1605 h->scsi_host->host_no,
1606 sd->bus, sd->target, sd->lun);
1607 break;
1608 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1609 dev_info(&h->pdev->dev,
1610 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1611 h->scsi_host->host_no,
1612 sd->bus, sd->target, sd->lun);
1613 break;
1614 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1615 dev_info(&h->pdev->dev,
1616 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1617 h->scsi_host->host_no,
1618 sd->bus, sd->target, sd->lun);
1619 break;
1620 case HPSA_LV_PENDING_ENCRYPTION:
1621 dev_info(&h->pdev->dev,
1622 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1623 h->scsi_host->host_no,
1624 sd->bus, sd->target, sd->lun);
1625 break;
1626 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1627 dev_info(&h->pdev->dev,
1628 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1629 h->scsi_host->host_no,
1630 sd->bus, sd->target, sd->lun);
1631 break;
1632 }
1633}
1634
03383736
DB		 1635/*
1636 * Figure the list of physical drive pointers for a logical drive with
1637 * raid offload configured.
1638 */
1639static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1640 struct hpsa_scsi_dev_t *dev[], int ndevices,
1641 struct hpsa_scsi_dev_t *logical_drive)
1642{
1643 struct raid_map_data *map = &logical_drive->raid_map;
1644 struct raid_map_disk_data *dd = &map->data[0];
1645 int i, j;
1646 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1647 le16_to_cpu(map->metadata_disks_per_row);
1648 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1649 le16_to_cpu(map->layout_map_count) *
1650 total_disks_per_row;
1651 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1652 total_disks_per_row;
1653 int qdepth;
1654
1655 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1656 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1657
d604f533
WS		 1658 logical_drive->nphysical_disks = nraid_map_entries;
1659
03383736
DB		 1660 qdepth = 0;
1661 for (i = 0; i < nraid_map_entries; i++) {
1662 logical_drive->phys_disk[i] = NULL;
1663 if (!logical_drive->offload_config)
1664 continue;
1665 for (j = 0; j < ndevices; j++) {
1d33d85d
DB		 1666 if (dev[j] == NULL)
1667 continue;
ff615f06
PK		 1668 if (dev[j]->devtype != TYPE_DISK &&
1669 dev[j]->devtype != TYPE_ZBC)
af15ed36 1670 continue;
f3f01730 1671 if (is_logical_device(dev[j]))
03383736
DB		 1672 continue;
1673 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1674 continue;
1675
1676 logical_drive->phys_disk[i] = dev[j];
1677 if (i < nphys_disk)
1678 qdepth = min(h->nr_cmds, qdepth +
1679 logical_drive->phys_disk[i]->queue_depth);
1680 break;
1681 }
1682
1683 /*
1684 * This can happen if a physical drive is removed and
1685 * the logical drive is degraded. In that case, the RAID
1686 * map data will refer to a physical disk which isn't actually
1687 * present. And in that case offload_enabled should already
1688 * be 0, but we'll turn it off here just in case
1689 */
1690 if (!logical_drive->phys_disk[i]) {
1691 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1692 logical_drive->offload_to_be_enabled = 0;
1693 logical_drive->queue_depth = 8;
03383736
DB		 1694 }
1695 }
1696 if (nraid_map_entries)
1697 /*
1698 * This is correct for reads, too high for full stripe writes,
1699 * way too high for partial stripe writes
1700 */
1701 logical_drive->queue_depth = qdepth;
1702 else
1703 logical_drive->queue_depth = h->nr_cmds;
1704}
1705
1706static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1707 struct hpsa_scsi_dev_t *dev[], int ndevices)
1708{
1709 int i;
1710
1711 for (i = 0; i < ndevices; i++) {
1d33d85d
DB		 1712 if (dev[i] == NULL)
1713 continue;
ff615f06
PK		 1714 if (dev[i]->devtype != TYPE_DISK &&
1715 dev[i]->devtype != TYPE_ZBC)
af15ed36 1716 continue;
f3f01730 1717 if (!is_logical_device(dev[i]))
03383736 1718 continue;
41ce4c35
SC		 1719
1720 /*
1721 * If offload is currently enabled, the RAID map and
1722 * phys_disk[] assignment *better* not be changing
1723 * and since it isn't changing, we do not need to
1724 * update it.
1725 */
1726 if (dev[i]->offload_enabled)
1727 continue;
1728
03383736
DB		 1729 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1730 }
1731}
1732
096ccff4
KB		 1733static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
1734{
1735 int rc = 0;
1736
1737 if (!h->scsi_host)
1738 return 1;
1739
d04e62b9
KB		 1740 if (is_logical_device(device)) /* RAID */
1741 rc = scsi_add_device(h->scsi_host, device->bus,
096ccff4 1742 device->target, device->lun);
d04e62b9
KB		 1743 else /* HBA */
1744 rc = hpsa_add_sas_device(h->sas_host, device);
1745
096ccff4
KB		 1746 return rc;
1747}
1748
ba74fdc4
DB		 1749static int hpsa_find_outstanding_commands_for_dev(struct ctlr_info *h,
1750 struct hpsa_scsi_dev_t *dev)
1751{
1752 int i;
1753 int count = 0;
1754
1755 for (i = 0; i < h->nr_cmds; i++) {
1756 struct CommandList *c = h->cmd_pool + i;
1757 int refcount = atomic_inc_return(&c->refcount);
1758
1759 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev,
1760 dev->scsi3addr)) {
1761 unsigned long flags;
1762
1763 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
1764 if (!hpsa_is_cmd_idle(c))
1765 ++count;
1766 spin_unlock_irqrestore(&h->lock, flags);
1767 }
1768
1769 cmd_free(h, c);
1770 }
1771
1772 return count;
1773}
1774
1775static void hpsa_wait_for_outstanding_commands_for_dev(struct ctlr_info *h,
1776 struct hpsa_scsi_dev_t *device)
1777{
1778 int cmds = 0;
1779 int waits = 0;
1780
1781 while (1) {
1782 cmds = hpsa_find_outstanding_commands_for_dev(h, device);
1783 if (cmds == 0)
1784 break;
1785 if (++waits > 20)
1786 break;
1787 dev_warn(&h->pdev->dev,
1788 "%s: removing device with %d outstanding commands!\n",
1789 __func__, cmds);
1790 msleep(1000);
1791 }
1792}
1793
096ccff4
KB		 1794static void hpsa_remove_device(struct ctlr_info *h,
1795 struct hpsa_scsi_dev_t *device)
1796{
1797 struct scsi_device *sdev = NULL;
1798
1799 if (!h->scsi_host)
1800 return;
1801
d04e62b9
KB		 1802 if (is_logical_device(device)) { /* RAID */
1803 sdev = scsi_device_lookup(h->scsi_host, device->bus,
096ccff4 1804 device->target, device->lun);
d04e62b9
KB		 1805 if (sdev) {
1806 scsi_remove_device(sdev);
1807 scsi_device_put(sdev);
1808 } else {
1809 /*
1810 * We don't expect to get here. Future commands
1811 * to this device will get a selection timeout as
1812 * if the device were gone.
1813 */
1814 hpsa_show_dev_msg(KERN_WARNING, h, device,
096ccff4 1815 "didn't find device for removal.");
d04e62b9 1816 }
ba74fdc4
DB		 1817 } else { /* HBA */
1818
1819 device->removed = 1;
1820 hpsa_wait_for_outstanding_commands_for_dev(h, device);
1821
d04e62b9 1822 hpsa_remove_sas_device(device);
ba74fdc4 1823 }
096ccff4
KB		 1824}
1825
8aa60681 1826static void adjust_hpsa_scsi_table(struct ctlr_info *h,
edd16368
SC		 1827 struct hpsa_scsi_dev_t *sd[], int nsds)
1828{
1829 /* sd contains scsi3 addresses and devtypes, and inquiry
1830 * data. This function takes what's in sd to be the current
1831 * reality and updates h->dev[] to reflect that reality.
1832 */
1833 int i, entry, device_change, changes = 0;
1834 struct hpsa_scsi_dev_t *csd;
1835 unsigned long flags;
1836 struct hpsa_scsi_dev_t **added, **removed;
1837 int nadded, nremoved;
edd16368 1838
da03ded0
DB		 1839 /*
1840 * A reset can cause a device status to change
1841 * re-schedule the scan to see what happened.
1842 */
1843 if (h->reset_in_progress) {
1844 h->drv_req_rescan = 1;
1845 return;
1846 }
edd16368 1847
cfe5badc
ST		 1848 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1849 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1850
1851 if (!added || !removed) {
1852 dev_warn(&h->pdev->dev, "out of memory in "
1853 "adjust_hpsa_scsi_table\n");
1854 goto free_and_out;
1855 }
1856
1857 spin_lock_irqsave(&h->devlock, flags);
1858
1859 /* find any devices in h->dev[] that are not in
1860 * sd[] and remove them from h->dev[], and for any
1861 * devices which have changed, remove the old device
1862 * info and add the new device info.
bd9244f7
ST		 1863 * If minor device attributes change, just update
1864 * the existing device structure.
edd16368
SC		 1865 */
1866 i = 0;
1867 nremoved = 0;
1868 nadded = 0;
1869 while (i < h->ndevices) {
1870 csd = h->dev[i];
1871 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1872 if (device_change == DEVICE_NOT_FOUND) {
1873 changes++;
8aa60681 1874 hpsa_scsi_remove_entry(h, i, removed, &nremoved);
edd16368
SC		 1875 continue; /* remove ^^^, hence i not incremented */
1876 } else if (device_change == DEVICE_CHANGED) {
1877 changes++;
8aa60681 1878 hpsa_scsi_replace_entry(h, i, sd[entry],
2a8ccf31 1879 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1880 /* Set it to NULL to prevent it from being freed
1881 * at the bottom of hpsa_update_scsi_devices()
1882 */
1883 sd[entry] = NULL;
bd9244f7 1884 } else if (device_change == DEVICE_UPDATED) {
8aa60681 1885 hpsa_scsi_update_entry(h, i, sd[entry]);
edd16368
SC		 1886 }
1887 i++;
1888 }
1889
1890 /* Now, make sure every device listed in sd[] is also
1891 * listed in h->dev[], adding them if they aren't found
1892 */
1893
1894 for (i = 0; i < nsds; i++) {
1895 if (!sd[i]) /* if already added above. */
1896 continue;
9846590e
SC		 1897
1898 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1899 * as the SCSI mid-layer does not handle such devices well.
1900 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1901 * at 160Hz, and prevents the system from coming up.
1902 */
1903 if (sd[i]->volume_offline) {
1904 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1905 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1906 continue;
1907 }
1908
edd16368
SC		 1909 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1910 h->ndevices, &entry);
1911 if (device_change == DEVICE_NOT_FOUND) {
1912 changes++;
8aa60681 1913 if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
edd16368
SC		 1914 break;
1915 sd[i] = NULL; /* prevent from being freed later. */
1916 } else if (device_change == DEVICE_CHANGED) {
1917 /* should never happen... */
1918 changes++;
1919 dev_warn(&h->pdev->dev,
1920 "device unexpectedly changed.\n");
1921 /* but if it does happen, we just ignore that device */
1922 }
1923 }
41ce4c35
SC		 1924 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1925
1926 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1927 * any logical drives that need it enabled.
1928 */
1d33d85d
DB		 1929 for (i = 0; i < h->ndevices; i++) {
1930 if (h->dev[i] == NULL)
1931 continue;
41ce4c35 1932 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1d33d85d 1933 }
41ce4c35 1934
edd16368
SC		 1935 spin_unlock_irqrestore(&h->devlock, flags);
1936
9846590e
SC		 1937 /* Monitor devices which are in one of several NOT READY states to be
1938 * brought online later. This must be done without holding h->devlock,
1939 * so don't touch h->dev[]
1940 */
1941 for (i = 0; i < nsds; i++) {
1942 if (!sd[i]) /* if already added above. */
1943 continue;
1944 if (sd[i]->volume_offline)
1945 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1946 }
1947
edd16368
SC		 1948 /* Don't notify scsi mid layer of any changes the first time through
1949 * (or if there are no changes) scsi_scan_host will do it later the
1950 * first time through.
1951 */
8aa60681 1952 if (!changes)
edd16368
SC		 1953 goto free_and_out;
1954
edd16368
SC		 1955 /* Notify scsi mid layer of any removed devices */
1956 for (i = 0; i < nremoved; i++) {
1d33d85d
DB		 1957 if (removed[i] == NULL)
1958 continue;
096ccff4
KB		 1959 if (removed[i]->expose_device)
1960 hpsa_remove_device(h, removed[i]);
edd16368
SC		 1961 kfree(removed[i]);
1962 removed[i] = NULL;
1963 }
1964
1965 /* Notify scsi mid layer of any added devices */
1966 for (i = 0; i < nadded; i++) {
096ccff4
KB		 1967 int rc = 0;
1968
1d33d85d
DB		 1969 if (added[i] == NULL)
1970 continue;
2a168208 1971 if (!(added[i]->expose_device))
41ce4c35 1972 continue;
096ccff4
KB		 1973 rc = hpsa_add_device(h, added[i]);
1974 if (!rc)
edd16368 1975 continue;
096ccff4
KB		 1976 dev_warn(&h->pdev->dev,
1977 "addition failed %d, device not added.", rc);
edd16368
SC		 1978 /* now we have to remove it from h->dev,
1979 * since it didn't get added to scsi mid layer
1980 */
1981 fixup_botched_add(h, added[i]);
853633e8 1982 h->drv_req_rescan = 1;
edd16368
SC		 1983 }
1984
1985free_and_out:
1986 kfree(added);
1987 kfree(removed);
edd16368
SC		 1988}
1989
1990/*
9e03aa2f 1991 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1992 * Assume's h->devlock is held.
1993 */
1994static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1995 int bus, int target, int lun)
1996{
1997 int i;
1998 struct hpsa_scsi_dev_t *sd;
1999
2000 for (i = 0; i < h->ndevices; i++) {
2001 sd = h->dev[i];
2002 if (sd->bus == bus && sd->target == target && sd->lun == lun)
2003 return sd;
2004 }
2005 return NULL;
2006}
2007
edd16368
SC		 2008static int hpsa_slave_alloc(struct scsi_device *sdev)
2009{
2010 struct hpsa_scsi_dev_t *sd;
2011 unsigned long flags;
2012 struct ctlr_info *h;
2013
2014 h = sdev_to_hba(sdev);
2015 spin_lock_irqsave(&h->devlock, flags);
d04e62b9
KB		 2016 if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) {
2017 struct scsi_target *starget;
2018 struct sas_rphy *rphy;
2019
2020 starget = scsi_target(sdev);
2021 rphy = target_to_rphy(starget);
2022 sd = hpsa_find_device_by_sas_rphy(h, rphy);
2023 if (sd) {
2024 sd->target = sdev_id(sdev);
2025 sd->lun = sdev->lun;
2026 }
2027 } else
2028 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
2029 sdev_id(sdev), sdev->lun);
2030
2031 if (sd && sd->expose_device) {
03383736 2032 atomic_set(&sd->ioaccel_cmds_out, 0);
d04e62b9 2033 sdev->hostdata = sd;
41ce4c35
SC		 2034 } else
2035 sdev->hostdata = NULL;
edd16368
SC		 2036 spin_unlock_irqrestore(&h->devlock, flags);
2037 return 0;
2038}
2039
41ce4c35
SC		 2040/* configure scsi device based on internal per-device structure */
2041static int hpsa_slave_configure(struct scsi_device *sdev)
2042{
2043 struct hpsa_scsi_dev_t *sd;
2044 int queue_depth;
2045
2046 sd = sdev->hostdata;
2a168208 2047 sdev->no_uld_attach = !sd || !sd->expose_device;
41ce4c35
SC		 2048
2049 if (sd)
2050 queue_depth = sd->queue_depth != 0 ?
2051 sd->queue_depth : sdev->host->can_queue;
2052 else
2053 queue_depth = sdev->host->can_queue;
2054
2055 scsi_change_queue_depth(sdev, queue_depth);
2056
2057 return 0;
2058}
2059
edd16368
SC		 2060static void hpsa_slave_destroy(struct scsi_device *sdev)
2061{
bcc44255 2062 /* nothing to do. */
edd16368
SC		 2063}
2064
d9a729f3
WS		 2065static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
2066{
2067 int i;
2068
2069 if (!h->ioaccel2_cmd_sg_list)
2070 return;
2071 for (i = 0; i < h->nr_cmds; i++) {
2072 kfree(h->ioaccel2_cmd_sg_list[i]);
2073 h->ioaccel2_cmd_sg_list[i] = NULL;
2074 }
2075 kfree(h->ioaccel2_cmd_sg_list);
2076 h->ioaccel2_cmd_sg_list = NULL;
2077}
2078
2079static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
2080{
2081 int i;
2082
2083 if (h->chainsize <= 0)
2084 return 0;
2085
2086 h->ioaccel2_cmd_sg_list =
2087 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
2088 GFP_KERNEL);
2089 if (!h->ioaccel2_cmd_sg_list)
2090 return -ENOMEM;
2091 for (i = 0; i < h->nr_cmds; i++) {
2092 h->ioaccel2_cmd_sg_list[i] =
2093 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
2094 h->maxsgentries, GFP_KERNEL);
2095 if (!h->ioaccel2_cmd_sg_list[i])
2096 goto clean;
2097 }
2098 return 0;
2099
2100clean:
2101 hpsa_free_ioaccel2_sg_chain_blocks(h);
2102 return -ENOMEM;
2103}
2104
33a2ffce
SC		 2105static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
2106{
2107 int i;
2108
2109 if (!h->cmd_sg_list)
2110 return;
2111 for (i = 0; i < h->nr_cmds; i++) {
2112 kfree(h->cmd_sg_list[i]);
2113 h->cmd_sg_list[i] = NULL;
2114 }
2115 kfree(h->cmd_sg_list);
2116 h->cmd_sg_list = NULL;
2117}
2118
105a3dbc 2119static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
33a2ffce
SC		 2120{
2121 int i;
2122
2123 if (h->chainsize <= 0)
2124 return 0;
2125
2126 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
2127 GFP_KERNEL);
3d4e6af8
RE		 2128 if (!h->cmd_sg_list) {
2129 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 2130 return -ENOMEM;
3d4e6af8 2131 }
33a2ffce
SC		 2132 for (i = 0; i < h->nr_cmds; i++) {
2133 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
2134 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 2135 if (!h->cmd_sg_list[i]) {
2136 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 2137 goto clean;
3d4e6af8 2138 }
33a2ffce
SC		 2139 }
2140 return 0;
2141
2142clean:
2143 hpsa_free_sg_chain_blocks(h);
2144 return -ENOMEM;
2145}
2146
d9a729f3
WS		 2147static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
2148 struct io_accel2_cmd *cp, struct CommandList *c)
2149{
2150 struct ioaccel2_sg_element *chain_block;
2151 u64 temp64;
2152 u32 chain_size;
2153
2154 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
a736e9b6 2155 chain_size = le32_to_cpu(cp->sg[0].length);
d9a729f3
WS		 2156 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
2157 PCI_DMA_TODEVICE);
2158 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2159 /* prevent subsequent unmapping */
2160 cp->sg->address = 0;
2161 return -1;
2162 }
2163 cp->sg->address = cpu_to_le64(temp64);
2164 return 0;
2165}
2166
2167static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
2168 struct io_accel2_cmd *cp)
2169{
2170 struct ioaccel2_sg_element *chain_sg;
2171 u64 temp64;
2172 u32 chain_size;
2173
2174 chain_sg = cp->sg;
2175 temp64 = le64_to_cpu(chain_sg->address);
a736e9b6 2176 chain_size = le32_to_cpu(cp->sg[0].length);
d9a729f3
WS		 2177 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
2178}
2179
e2bea6df 2180static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 2181 struct CommandList *c)
2182{
2183 struct SGDescriptor *chain_sg, *chain_block;
2184 u64 temp64;
50a0decf 2185 u32 chain_len;
33a2ffce
SC		 2186
2187 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
2188 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 2189 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
2190 chain_len = sizeof(*chain_sg) *
2b08b3e9 2191 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 2192 chain_sg->Len = cpu_to_le32(chain_len);
2193 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 2194 PCI_DMA_TODEVICE);
e2bea6df
SC		 2195 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2196 /* prevent subsequent unmapping */
50a0decf 2197 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 2198 return -1;
2199 }
50a0decf 2200 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 2201 return 0;
33a2ffce
SC		 2202}
2203
2204static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
2205 struct CommandList *c)
2206{
2207 struct SGDescriptor *chain_sg;
33a2ffce 2208
50a0decf 2209 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 2210 return;
2211
2212 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 2213 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
2214 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 2215}
2216
a09c1441
ST		 2217
2218/* Decode the various types of errors on ioaccel2 path.
2219 * Return 1 for any error that should generate a RAID path retry.
2220 * Return 0 for errors that don't require a RAID path retry.
2221 */
2222static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 2223 struct CommandList *c,
2224 struct scsi_cmnd *cmd,
ba74fdc4
DB		 2225 struct io_accel2_cmd *c2,
2226 struct hpsa_scsi_dev_t *dev)
c349775e
ST		 2227{
2228 int data_len;
a09c1441 2229 int retry = 0;
c40820d5 2230 u32 ioaccel2_resid = 0;
c349775e
ST		 2231
2232 switch (c2->error_data.serv_response) {
2233 case IOACCEL2_SERV_RESPONSE_COMPLETE:
2234 switch (c2->error_data.status) {
2235 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
2236 break;
2237 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
ee6b1889 2238 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 2239 if (c2->error_data.data_present !=
ee6b1889
SC		 2240 IOACCEL2_SENSE_DATA_PRESENT) {
2241 memset(cmd->sense_buffer, 0,
2242 SCSI_SENSE_BUFFERSIZE);
c349775e 2243 break;
ee6b1889 2244 }
c349775e
ST		 2245 /* copy the sense data */
2246 data_len = c2->error_data.sense_data_len;
2247 if (data_len > SCSI_SENSE_BUFFERSIZE)
2248 data_len = SCSI_SENSE_BUFFERSIZE;
2249 if (data_len > sizeof(c2->error_data.sense_data_buff))
2250 data_len =
2251 sizeof(c2->error_data.sense_data_buff);
2252 memcpy(cmd->sense_buffer,
2253 c2->error_data.sense_data_buff, data_len);
a09c1441 2254 retry = 1;
c349775e
ST		 2255 break;
2256 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
a09c1441 2257 retry = 1;
c349775e
ST		 2258 break;
2259 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
a09c1441 2260 retry = 1;
c349775e
ST		 2261 break;
2262 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 2263 retry = 1;
c349775e
ST		 2264 break;
2265 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
a09c1441 2266 retry = 1;
c349775e
ST		 2267 break;
2268 default:
a09c1441 2269 retry = 1;
c349775e
ST		 2270 break;
2271 }
2272 break;
2273 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 2274 switch (c2->error_data.status) {
2275 case IOACCEL2_STATUS_SR_IO_ERROR:
2276 case IOACCEL2_STATUS_SR_IO_ABORTED:
2277 case IOACCEL2_STATUS_SR_OVERRUN:
2278 retry = 1;
2279 break;
2280 case IOACCEL2_STATUS_SR_UNDERRUN:
2281 cmd->result = (DID_OK << 16); /* host byte */
2282 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2283 ioaccel2_resid = get_unaligned_le32(
2284 &c2->error_data.resid_cnt[0]);
2285 scsi_set_resid(cmd, ioaccel2_resid);
2286 break;
2287 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
2288 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
2289 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
ba74fdc4
DB		 2290 /*
2291 * Did an HBA disk disappear? We will eventually
2292 * get a state change event from the controller but
2293 * in the meantime, we need to tell the OS that the
2294 * HBA disk is no longer there and stop I/O
2295 * from going down. This allows the potential re-insert
2296 * of the disk to get the same device node.
2297 */
2298 if (dev->physical_device && dev->expose_device) {
2299 cmd->result = DID_NO_CONNECT << 16;
2300 dev->removed = 1;
2301 h->drv_req_rescan = 1;
2302 dev_warn(&h->pdev->dev,
2303 "%s: device is gone!\n", __func__);
2304 } else
2305 /*
2306 * Retry by sending down the RAID path.
2307 * We will get an event from ctlr to
2308 * trigger rescan regardless.
2309 */
2310 retry = 1;
c40820d5
JH		 2311 break;
2312 default:
2313 retry = 1;
c40820d5 2314 }
c349775e
ST		 2315 break;
2316 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
2317 break;
2318 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
2319 break;
2320 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
a09c1441 2321 retry = 1;
c349775e
ST		 2322 break;
2323 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
c349775e
ST		 2324 break;
2325 default:
a09c1441 2326 retry = 1;
c349775e
ST		 2327 break;
2328 }
a09c1441
ST		 2329
2330 return retry; /* retry on raid path? */
c349775e
ST		 2331}
2332
a58e7e53
WS		 2333static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2334 struct CommandList *c)
2335{
d604f533
WS		 2336 bool do_wake = false;
2337
a58e7e53
WS		 2338 /*
2339 * Prevent the following race in the abort handler:
2340 *
2341 * 1. LLD is requested to abort a SCSI command
2342 * 2. The SCSI command completes
2343 * 3. The struct CommandList associated with step 2 is made available
2344 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2345 * 5. Abort handler follows scsi_cmnd->host_scribble and
2346 * finds struct CommandList and tries to aborts it
2347 * Now we have aborted the wrong command.
2348 *
d604f533
WS		 2349 * Reset c->scsi_cmd here so that the abort or reset handler will know
2350 * this command has completed. Then, check to see if the handler is
a58e7e53
WS		 2351 * waiting for this command, and, if so, wake it.
2352 */
2353 c->scsi_cmd = SCSI_CMD_IDLE;
d604f533 2354 mb(); /* Declare command idle before checking for pending events. */
a58e7e53 2355 if (c->abort_pending) {
d604f533 2356 do_wake = true;
a58e7e53 2357 c->abort_pending = false;
a58e7e53 2358 }
d604f533
WS		 2359 if (c->reset_pending) {
2360 unsigned long flags;
2361 struct hpsa_scsi_dev_t *dev;
2362
2363 /*
2364 * There appears to be a reset pending; lock the lock and
2365 * reconfirm. If so, then decrement the count of outstanding
2366 * commands and wake the reset command if this is the last one.
2367 */
2368 spin_lock_irqsave(&h->lock, flags);
2369 dev = c->reset_pending; /* Re-fetch under the lock. */
2370 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2371 do_wake = true;
2372 c->reset_pending = NULL;
2373 spin_unlock_irqrestore(&h->lock, flags);
2374 }
2375
2376 if (do_wake)
2377 wake_up_all(&h->event_sync_wait_queue);
a58e7e53
WS		 2378}
2379
73153fe5
WS		 2380static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2381 struct CommandList *c)
2382{
2383 hpsa_cmd_resolve_events(h, c);
2384 cmd_tagged_free(h, c);
2385}
2386
8a0ff92c
WS		 2387static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2388 struct CommandList *c, struct scsi_cmnd *cmd)
2389{
73153fe5 2390 hpsa_cmd_resolve_and_free(h, c);
8a0ff92c
WS		 2391 cmd->scsi_done(cmd);
2392}
2393
2394static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2395{
2396 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2397 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2398}
2399
a58e7e53
WS		 2400static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2401{
2402 cmd->result = DID_ABORT << 16;
2403}
2404
2405static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2406 struct scsi_cmnd *cmd)
2407{
2408 hpsa_set_scsi_cmd_aborted(cmd);
2409 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2410 c->Request.CDB, c->err_info->ScsiStatus);
73153fe5 2411 hpsa_cmd_resolve_and_free(h, c);
a58e7e53
WS		 2412}
2413
c349775e
ST		 2414static void process_ioaccel2_completion(struct ctlr_info *h,
2415 struct CommandList *c, struct scsi_cmnd *cmd,
2416 struct hpsa_scsi_dev_t *dev)
2417{
2418 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2419
2420 /* check for good status */
2421 if (likely(c2->error_data.serv_response == 0 &&
8a0ff92c
WS		 2422 c2->error_data.status == 0))
2423 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e 2424
8a0ff92c
WS		 2425 /*
2426 * Any RAID offload error results in retry which will use
c349775e
ST		 2427 * the normal I/O path so the controller can handle whatever's
2428 * wrong.
2429 */
f3f01730 2430 if (is_logical_device(dev) &&
c349775e
ST		 2431 c2->error_data.serv_response ==
2432 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc 2433 if (c2->error_data.status ==
064d1b1d 2434 IOACCEL2_STATUS_SR_IOACCEL_DISABLED) {
080ef1cc 2435 dev->offload_enabled = 0;
064d1b1d
DB		 2436 dev->offload_to_be_enabled = 0;
2437 }
8a0ff92c
WS		 2438
2439 return hpsa_retry_cmd(h, c);
a09c1441 2440 }
080ef1cc 2441
ba74fdc4 2442 if (handle_ioaccel_mode2_error(h, c, cmd, c2, dev))
8a0ff92c 2443 return hpsa_retry_cmd(h, c);
080ef1cc 2444
8a0ff92c 2445 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e
ST		 2446}
2447
9437ac43
SC		 2448/* Returns 0 on success, < 0 otherwise. */
2449static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2450 struct CommandList *cp)
2451{
2452 u8 tmf_status = cp->err_info->ScsiStatus;
2453
2454 switch (tmf_status) {
2455 case CISS_TMF_COMPLETE:
2456 /*
2457 * CISS_TMF_COMPLETE never happens, instead,
2458 * ei->CommandStatus == 0 for this case.
2459 */
2460 case CISS_TMF_SUCCESS:
2461 return 0;
2462 case CISS_TMF_INVALID_FRAME:
2463 case CISS_TMF_NOT_SUPPORTED:
2464 case CISS_TMF_FAILED:
2465 case CISS_TMF_WRONG_LUN:
2466 case CISS_TMF_OVERLAPPED_TAG:
2467 break;
2468 default:
2469 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2470 tmf_status);
2471 break;
2472 }
2473 return -tmf_status;
2474}
2475
1fb011fb 2476static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2477{
2478 struct scsi_cmnd *cmd;
2479 struct ctlr_info *h;
2480 struct ErrorInfo *ei;
283b4a9b 2481 struct hpsa_scsi_dev_t *dev;
d9a729f3 2482 struct io_accel2_cmd *c2;
edd16368 2483
9437ac43
SC		 2484 u8 sense_key;
2485 u8 asc; /* additional sense code */
2486 u8 ascq; /* additional sense code qualifier */
db111e18 2487 unsigned long sense_data_size;
edd16368
SC		 2488
2489 ei = cp->err_info;
7fa3030c 2490 cmd = cp->scsi_cmd;
edd16368 2491 h = cp->h;
283b4a9b 2492 dev = cmd->device->hostdata;
d9a729f3 2493 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2494
2495 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2496 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2497 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2498 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2499
d9a729f3
WS		 2500 if ((cp->cmd_type == CMD_IOACCEL2) &&
2501 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2502 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2503
edd16368
SC		 2504 cmd->result = (DID_OK << 16); /* host byte */
2505 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2506
03383736
DB		 2507 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2508 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2509
25163bd5
WS		 2510 /*
2511 * We check for lockup status here as it may be set for
2512 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2513 * fail_all_oustanding_cmds()
2514 */
2515 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2516 /* DID_NO_CONNECT will prevent a retry */
2517 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 2518 return hpsa_cmd_free_and_done(h, cp, cmd);
25163bd5
WS		 2519 }
2520
d604f533
WS		 2521 if ((unlikely(hpsa_is_pending_event(cp)))) {
2522 if (cp->reset_pending)
2523 return hpsa_cmd_resolve_and_free(h, cp);
2524 if (cp->abort_pending)
2525 return hpsa_cmd_abort_and_free(h, cp, cmd);
2526 }
2527
c349775e
ST		 2528 if (cp->cmd_type == CMD_IOACCEL2)
2529 return process_ioaccel2_completion(h, cp, cmd, dev);
2530
6aa4c361 2531 scsi_set_resid(cmd, ei->ResidualCnt);
8a0ff92c
WS		 2532 if (ei->CommandStatus == 0)
2533 return hpsa_cmd_free_and_done(h, cp, cmd);
6aa4c361 2534
e1f7de0c
MG		 2535 /* For I/O accelerator commands, copy over some fields to the normal
2536 * CISS header used below for error handling.
2537 */
2538 if (cp->cmd_type == CMD_IOACCEL1) {
2539 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2540 cp->Header.SGList = scsi_sg_count(cmd);
2541 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2542 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2543 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2544 cp->Header.tag = c->tag;
e1f7de0c
MG		 2545 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2546 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2547
2548 /* Any RAID offload error results in retry which will use
2549 * the normal I/O path so the controller can handle whatever's
2550 * wrong.
2551 */
f3f01730 2552 if (is_logical_device(dev)) {
283b4a9b
SC		 2553 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2554 dev->offload_enabled = 0;
d604f533 2555 return hpsa_retry_cmd(h, cp);
283b4a9b 2556 }
e1f7de0c
MG		 2557 }
2558
edd16368
SC		 2559 /* an error has occurred */
2560 switch (ei->CommandStatus) {
2561
2562 case CMD_TARGET_STATUS:
9437ac43
SC		 2563 cmd->result |= ei->ScsiStatus;
2564 /* copy the sense data */
2565 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2566 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2567 else
2568 sense_data_size = sizeof(ei->SenseInfo);
2569 if (ei->SenseLen < sense_data_size)
2570 sense_data_size = ei->SenseLen;
2571 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2572 if (ei->ScsiStatus)
2573 decode_sense_data(ei->SenseInfo, sense_data_size,
2574 &sense_key, &asc, &ascq);
edd16368 2575 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2576 if (sense_key == ABORTED_COMMAND) {
2e311fba 2577 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2578 break;
2579 }
edd16368
SC		 2580 break;
2581 }
edd16368
SC		 2582 /* Problem was not a check condition
2583 * Pass it up to the upper layers...
2584 */
2585 if (ei->ScsiStatus) {
2586 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2587 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2588 "Returning result: 0x%x\n",
2589 cp, ei->ScsiStatus,
2590 sense_key, asc, ascq,
2591 cmd->result);
2592 } else { /* scsi status is zero??? How??? */
2593 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2594 "Returning no connection.\n", cp),
2595
2596 /* Ordinarily, this case should never happen,
2597 * but there is a bug in some released firmware
2598 * revisions that allows it to happen if, for
2599 * example, a 4100 backplane loses power and
2600 * the tape drive is in it. We assume that
2601 * it's a fatal error of some kind because we
2602 * can't show that it wasn't. We will make it
2603 * look like selection timeout since that is
2604 * the most common reason for this to occur,
2605 * and it's severe enough.
2606 */
2607
2608 cmd->result = DID_NO_CONNECT << 16;
2609 }
2610 break;
2611
2612 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2613 break;
2614 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2615 dev_warn(&h->pdev->dev,
2616 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2617 break;
2618 case CMD_INVALID: {
2619 /* print_bytes(cp, sizeof(*cp), 1, 0);
2620 print_cmd(cp); */
2621 /* We get CMD_INVALID if you address a non-existent device
2622 * instead of a selection timeout (no response). You will
2623 * see this if you yank out a drive, then try to access it.
2624 * This is kind of a shame because it means that any other
2625 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2626 * missing target. */
2627 cmd->result = DID_NO_CONNECT << 16;
2628 }
2629 break;
2630 case CMD_PROTOCOL_ERR:
256d0eaa 2631 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2632 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2633 cp->Request.CDB);
edd16368
SC		 2634 break;
2635 case CMD_HARDWARE_ERR:
2636 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2637 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2638 cp->Request.CDB);
edd16368
SC		 2639 break;
2640 case CMD_CONNECTION_LOST:
2641 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2642 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2643 cp->Request.CDB);
edd16368
SC		 2644 break;
2645 case CMD_ABORTED:
a58e7e53
WS		 2646 /* Return now to avoid calling scsi_done(). */
2647 return hpsa_cmd_abort_and_free(h, cp, cmd);
edd16368
SC		 2648 case CMD_ABORT_FAILED:
2649 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2650 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2651 cp->Request.CDB);
edd16368
SC		 2652 break;
2653 case CMD_UNSOLICITED_ABORT:
f6e76055 2654 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2655 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2656 cp->Request.CDB);
edd16368
SC		 2657 break;
2658 case CMD_TIMEOUT:
2659 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2660 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2661 cp->Request.CDB);
edd16368 2662 break;
1d5e2ed0
SC		 2663 case CMD_UNABORTABLE:
2664 cmd->result = DID_ERROR << 16;
2665 dev_warn(&h->pdev->dev, "Command unabortable\n");
2666 break;
9437ac43
SC		 2667 case CMD_TMF_STATUS:
2668 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2669 cmd->result = DID_ERROR << 16;
2670 break;
283b4a9b
SC		 2671 case CMD_IOACCEL_DISABLED:
2672 /* This only handles the direct pass-through case since RAID
2673 * offload is handled above. Just attempt a retry.
2674 */
2675 cmd->result = DID_SOFT_ERROR << 16;
2676 dev_warn(&h->pdev->dev,
2677 "cp %p had HP SSD Smart Path error\n", cp);
2678 break;
edd16368
SC		 2679 default:
2680 cmd->result = DID_ERROR << 16;
2681 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2682 cp, ei->CommandStatus);
2683 }
8a0ff92c
WS		 2684
2685 return hpsa_cmd_free_and_done(h, cp, cmd);
edd16368
SC		 2686}
2687
edd16368
SC		 2688static void hpsa_pci_unmap(struct pci_dev *pdev,
2689 struct CommandList *c, int sg_used, int data_direction)
2690{
2691 int i;
edd16368 2692
50a0decf
SC		 2693 for (i = 0; i < sg_used; i++)
2694 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2695 le32_to_cpu(c->SG[i].Len),
2696 data_direction);
edd16368
SC		 2697}
2698
a2dac136 2699static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2700 struct CommandList *cp,
2701 unsigned char *buf,
2702 size_t buflen,
2703 int data_direction)
2704{
01a02ffc 2705 u64 addr64;
edd16368
SC		 2706
2707 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2708 cp->Header.SGList = 0;
50a0decf 2709 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2710 return 0;
edd16368
SC		 2711 }
2712
50a0decf 2713 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2714 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2715 /* Prevent subsequent unmap of something never mapped */
eceaae18 2716 cp->Header.SGList = 0;
50a0decf 2717 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2718 return -1;
eceaae18 2719 }
50a0decf
SC		 2720 cp->SG[0].Addr = cpu_to_le64(addr64);
2721 cp->SG[0].Len = cpu_to_le32(buflen);
2722 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2723 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2724 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2725 return 0;
edd16368
SC		 2726}
2727
25163bd5
WS		 2728#define NO_TIMEOUT ((unsigned long) -1)
2729#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2730static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2731 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2732{
2733 DECLARE_COMPLETION_ONSTACK(wait);
2734
2735 c->waiting = &wait;
25163bd5
WS		 2736 __enqueue_cmd_and_start_io(h, c, reply_queue);
2737 if (timeout_msecs == NO_TIMEOUT) {
2738 /* TODO: get rid of this no-timeout thing */
2739 wait_for_completion_io(&wait);
2740 return IO_OK;
2741 }
2742 if (!wait_for_completion_io_timeout(&wait,
2743 msecs_to_jiffies(timeout_msecs))) {
2744 dev_warn(&h->pdev->dev, "Command timed out.\n");
2745 return -ETIMEDOUT;
2746 }
2747 return IO_OK;
2748}
2749
2750static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2751 int reply_queue, unsigned long timeout_msecs)
2752{
2753 if (unlikely(lockup_detected(h))) {
2754 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2755 return IO_OK;
2756 }
2757 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2758}
2759
094963da
SC		 2760static u32 lockup_detected(struct ctlr_info *h)
2761{
2762 int cpu;
2763 u32 rc, *lockup_detected;
2764
2765 cpu = get_cpu();
2766 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2767 rc = *lockup_detected;
2768 put_cpu();
2769 return rc;
2770}
2771
9c2fc160 2772#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2773static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2774 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2775{
9c2fc160 2776 int backoff_time = 10, retry_count = 0;
25163bd5 2777 int rc;
edd16368
SC		 2778
2779 do {
7630abd0 2780 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2781 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2782 timeout_msecs);
2783 if (rc)
2784 break;
edd16368 2785 retry_count++;
9c2fc160
SC		 2786 if (retry_count > 3) {
2787 msleep(backoff_time);
2788 if (backoff_time < 1000)
2789 backoff_time *= 2;
2790 }
852af20a 2791 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2792 check_for_busy(h, c)) &&
2793 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2794 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2795 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2796 rc = -EIO;
2797 return rc;
edd16368
SC		 2798}
2799
d1e8beac
SC		 2800static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2801 struct CommandList *c)
edd16368 2802{
d1e8beac
SC		 2803 const u8 *cdb = c->Request.CDB;
2804 const u8 *lun = c->Header.LUN.LunAddrBytes;
2805
2806 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2807 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2808 txt, lun[0], lun[1], lun[2], lun[3],
2809 lun[4], lun[5], lun[6], lun[7],
2810 cdb[0], cdb[1], cdb[2], cdb[3],
2811 cdb[4], cdb[5], cdb[6], cdb[7],
2812 cdb[8], cdb[9], cdb[10], cdb[11],
2813 cdb[12], cdb[13], cdb[14], cdb[15]);
2814}
2815
2816static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2817 struct CommandList *cp)
2818{
2819 const struct ErrorInfo *ei = cp->err_info;
edd16368 2820 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2821 u8 sense_key, asc, ascq;
2822 int sense_len;
edd16368 2823
edd16368
SC		 2824 switch (ei->CommandStatus) {
2825 case CMD_TARGET_STATUS:
9437ac43
SC		 2826 if (ei->SenseLen > sizeof(ei->SenseInfo))
2827 sense_len = sizeof(ei->SenseInfo);
2828 else
2829 sense_len = ei->SenseLen;
2830 decode_sense_data(ei->SenseInfo, sense_len,
2831 &sense_key, &asc, &ascq);
d1e8beac
SC		 2832 hpsa_print_cmd(h, "SCSI status", cp);
2833 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2834 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2835 sense_key, asc, ascq);
d1e8beac 2836 else
9437ac43 2837 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2838 if (ei->ScsiStatus == 0)
2839 dev_warn(d, "SCSI status is abnormally zero. "
2840 "(probably indicates selection timeout "
2841 "reported incorrectly due to a known "
2842 "firmware bug, circa July, 2001.)\n");
2843 break;
2844 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2845 break;
2846 case CMD_DATA_OVERRUN:
d1e8beac 2847 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2848 break;
2849 case CMD_INVALID: {
2850 /* controller unfortunately reports SCSI passthru's
2851 * to non-existent targets as invalid commands.
2852 */
d1e8beac
SC		 2853 hpsa_print_cmd(h, "invalid command", cp);
2854 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2855 }
2856 break;
2857 case CMD_PROTOCOL_ERR:
d1e8beac 2858 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2859 break;
2860 case CMD_HARDWARE_ERR:
d1e8beac 2861 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2862 break;
2863 case CMD_CONNECTION_LOST:
d1e8beac 2864 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2865 break;
2866 case CMD_ABORTED:
d1e8beac 2867 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2868 break;
2869 case CMD_ABORT_FAILED:
d1e8beac 2870 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2871 break;
2872 case CMD_UNSOLICITED_ABORT:
d1e8beac 2873 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2874 break;
2875 case CMD_TIMEOUT:
d1e8beac 2876 hpsa_print_cmd(h, "timed out", cp);
edd16368 2877 break;
1d5e2ed0 2878 case CMD_UNABORTABLE:
d1e8beac 2879 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2880 break;
25163bd5
WS		 2881 case CMD_CTLR_LOCKUP:
2882 hpsa_print_cmd(h, "controller lockup detected", cp);
2883 break;
edd16368 2884 default:
d1e8beac
SC		 2885 hpsa_print_cmd(h, "unknown status", cp);
2886 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2887 ei->CommandStatus);
2888 }
2889}
2890
2891static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2892 u16 page, unsigned char *buf,
edd16368
SC		 2893 unsigned char bufsize)
2894{
2895 int rc = IO_OK;
2896 struct CommandList *c;
2897 struct ErrorInfo *ei;
2898
45fcb86e 2899 c = cmd_alloc(h);
edd16368 2900
a2dac136
SC		 2901 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2902 page, scsi3addr, TYPE_CMD)) {
2903 rc = -1;
2904 goto out;
2905 }
25163bd5 2906 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 2907 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 2908 if (rc)
2909 goto out;
edd16368
SC		 2910 ei = c->err_info;
2911 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2912 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2913 rc = -1;
2914 }
a2dac136 2915out:
45fcb86e 2916 cmd_free(h, c);
edd16368
SC		 2917 return rc;
2918}
2919
bf711ac6 2920static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2921 u8 reset_type, int reply_queue)
edd16368
SC		 2922{
2923 int rc = IO_OK;
2924 struct CommandList *c;
2925 struct ErrorInfo *ei;
2926
45fcb86e 2927 c = cmd_alloc(h);
edd16368 2928
edd16368 2929
a2dac136 2930 /* fill_cmd can't fail here, no data buffer to map. */
0b9b7b6e 2931 (void) fill_cmd(c, reset_type, h, NULL, 0, 0,
bf711ac6 2932 scsi3addr, TYPE_MSG);
c448ecfa 2933 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
25163bd5
WS		 2934 if (rc) {
2935 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2936 goto out;
2937 }
edd16368
SC		 2938 /* no unmap needed here because no data xfer. */
2939
2940 ei = c->err_info;
2941 if (ei->CommandStatus != 0) {
d1e8beac 2942 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2943 rc = -1;
2944 }
25163bd5 2945out:
45fcb86e 2946 cmd_free(h, c);
edd16368
SC		 2947 return rc;
2948}
2949
d604f533
WS		 2950static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2951 struct hpsa_scsi_dev_t *dev,
2952 unsigned char *scsi3addr)
2953{
2954 int i;
2955 bool match = false;
2956 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2957 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2958
2959 if (hpsa_is_cmd_idle(c))
2960 return false;
2961
2962 switch (c->cmd_type) {
2963 case CMD_SCSI:
2964 case CMD_IOCTL_PEND:
2965 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2966 sizeof(c->Header.LUN.LunAddrBytes));
2967 break;
2968
2969 case CMD_IOACCEL1:
2970 case CMD_IOACCEL2:
2971 if (c->phys_disk == dev) {
2972 /* HBA mode match */
2973 match = true;
2974 } else {
2975 /* Possible RAID mode -- check each phys dev. */
2976 /* FIXME: Do we need to take out a lock here? If
2977 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2978 * instead. */
2979 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2980 /* FIXME: an alternate test might be
2981 *
2982 * match = dev->phys_disk[i]->ioaccel_handle
2983 * == c2->scsi_nexus; */
2984 match = dev->phys_disk[i] == c->phys_disk;
2985 }
2986 }
2987 break;
2988
2989 case IOACCEL2_TMF:
2990 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2991 match = dev->phys_disk[i]->ioaccel_handle ==
2992 le32_to_cpu(ac->it_nexus);
2993 }
2994 break;
2995
2996 case 0: /* The command is in the middle of being initialized. */
2997 match = false;
2998 break;
2999
3000 default:
3001 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
3002 c->cmd_type);
3003 BUG();
3004 }
3005
3006 return match;
3007}
3008
3009static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
3010 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
3011{
3012 int i;
3013 int rc = 0;
3014
3015 /* We can really only handle one reset at a time */
3016 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
3017 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
3018 return -EINTR;
3019 }
3020
3021 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
3022
3023 for (i = 0; i < h->nr_cmds; i++) {
3024 struct CommandList *c = h->cmd_pool + i;
3025 int refcount = atomic_inc_return(&c->refcount);
3026
3027 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
3028 unsigned long flags;
3029
3030 /*
3031 * Mark the target command as having a reset pending,
3032 * then lock a lock so that the command cannot complete
3033 * while we're considering it. If the command is not
3034 * idle then count it; otherwise revoke the event.
3035 */
3036 c->reset_pending = dev;
3037 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
3038 if (!hpsa_is_cmd_idle(c))
3039 atomic_inc(&dev->reset_cmds_out);
3040 else
3041 c->reset_pending = NULL;
3042 spin_unlock_irqrestore(&h->lock, flags);
3043 }
3044
3045 cmd_free(h, c);
3046 }
3047
3048 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
3049 if (!rc)
3050 wait_event(h->event_sync_wait_queue,
3051 atomic_read(&dev->reset_cmds_out) == 0 ||
3052 lockup_detected(h));
3053
3054 if (unlikely(lockup_detected(h))) {
77678d3a
DB		 3055 dev_warn(&h->pdev->dev,
3056 "Controller lockup detected during reset wait\n");
3057 rc = -ENODEV;
3058 }
d604f533
WS		 3059
3060 if (unlikely(rc))
3061 atomic_set(&dev->reset_cmds_out, 0);
3062
3063 mutex_unlock(&h->reset_mutex);
3064 return rc;
3065}
3066
edd16368
SC		 3067static void hpsa_get_raid_level(struct ctlr_info *h,
3068 unsigned char *scsi3addr, unsigned char *raid_level)
3069{
3070 int rc;
3071 unsigned char *buf;
3072
3073 *raid_level = RAID_UNKNOWN;
3074 buf = kzalloc(64, GFP_KERNEL);
3075 if (!buf)
3076 return;
b7bb24eb 3077 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 3078 if (rc == 0)
3079 *raid_level = buf[8];
3080 if (*raid_level > RAID_UNKNOWN)
3081 *raid_level = RAID_UNKNOWN;
3082 kfree(buf);
3083 return;
3084}
3085
283b4a9b
SC		 3086#define HPSA_MAP_DEBUG
3087#ifdef HPSA_MAP_DEBUG
3088static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
3089 struct raid_map_data *map_buff)
3090{
3091 struct raid_map_disk_data *dd = &map_buff->data[0];
3092 int map, row, col;
3093 u16 map_cnt, row_cnt, disks_per_row;
3094
3095 if (rc != 0)
3096 return;
3097
2ba8bfc8
SC		 3098 /* Show details only if debugging has been activated. */
3099 if (h->raid_offload_debug < 2)
3100 return;
3101
283b4a9b
SC		 3102 dev_info(&h->pdev->dev, "structure_size = %u\n",
3103 le32_to_cpu(map_buff->structure_size));
3104 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
3105 le32_to_cpu(map_buff->volume_blk_size));
3106 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
3107 le64_to_cpu(map_buff->volume_blk_cnt));
3108 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
3109 map_buff->phys_blk_shift);
3110 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
3111 map_buff->parity_rotation_shift);
3112 dev_info(&h->pdev->dev, "strip_size = %u\n",
3113 le16_to_cpu(map_buff->strip_size));
3114 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
3115 le64_to_cpu(map_buff->disk_starting_blk));
3116 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
3117 le64_to_cpu(map_buff->disk_blk_cnt));
3118 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
3119 le16_to_cpu(map_buff->data_disks_per_row));
3120 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
3121 le16_to_cpu(map_buff->metadata_disks_per_row));
3122 dev_info(&h->pdev->dev, "row_cnt = %u\n",
3123 le16_to_cpu(map_buff->row_cnt));
3124 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
3125 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 3126 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 3127 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 3128 dev_info(&h->pdev->dev, "encrypytion = %s\n",
3129 le16_to_cpu(map_buff->flags) &
3130 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 3131 dev_info(&h->pdev->dev, "dekindex = %u\n",
3132 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 3133 map_cnt = le16_to_cpu(map_buff->layout_map_count);
3134 for (map = 0; map < map_cnt; map++) {
3135 dev_info(&h->pdev->dev, "Map%u:\n", map);
3136 row_cnt = le16_to_cpu(map_buff->row_cnt);
3137 for (row = 0; row < row_cnt; row++) {
3138 dev_info(&h->pdev->dev, " Row%u:\n", row);
3139 disks_per_row =
3140 le16_to_cpu(map_buff->data_disks_per_row);
3141 for (col = 0; col < disks_per_row; col++, dd++)
3142 dev_info(&h->pdev->dev,
3143 " D%02u: h=0x%04x xor=%u,%u\n",
3144 col, dd->ioaccel_handle,
3145 dd->xor_mult[0], dd->xor_mult[1]);
3146 disks_per_row =
3147 le16_to_cpu(map_buff->metadata_disks_per_row);
3148 for (col = 0; col < disks_per_row; col++, dd++)
3149 dev_info(&h->pdev->dev,
3150 " M%02u: h=0x%04x xor=%u,%u\n",
3151 col, dd->ioaccel_handle,
3152 dd->xor_mult[0], dd->xor_mult[1]);
3153 }
3154 }
3155}
3156#else
3157static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
3158 __attribute__((unused)) int rc,
3159 __attribute__((unused)) struct raid_map_data *map_buff)
3160{
3161}
3162#endif
3163
3164static int hpsa_get_raid_map(struct ctlr_info *h,
3165 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3166{
3167 int rc = 0;
3168 struct CommandList *c;
3169 struct ErrorInfo *ei;
3170
45fcb86e 3171 c = cmd_alloc(h);
bf43caf3 3172
283b4a9b
SC		 3173 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
3174 sizeof(this_device->raid_map), 0,
3175 scsi3addr, TYPE_CMD)) {
2dd02d74
RE		 3176 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
3177 cmd_free(h, c);
3178 return -1;
283b4a9b 3179 }
25163bd5 3180 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3181 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 3182 if (rc)
3183 goto out;
283b4a9b
SC		 3184 ei = c->err_info;
3185 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3186 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 3187 rc = -1;
3188 goto out;
283b4a9b 3189 }
45fcb86e 3190 cmd_free(h, c);
283b4a9b
SC		 3191
3192 /* @todo in the future, dynamically allocate RAID map memory */
3193 if (le32_to_cpu(this_device->raid_map.structure_size) >
3194 sizeof(this_device->raid_map)) {
3195 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
3196 rc = -1;
3197 }
3198 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
3199 return rc;
25163bd5
WS		 3200out:
3201 cmd_free(h, c);
3202 return rc;
283b4a9b
SC		 3203}
3204
d04e62b9
KB		 3205static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h,
3206 unsigned char scsi3addr[], u16 bmic_device_index,
3207 struct bmic_sense_subsystem_info *buf, size_t bufsize)
3208{
3209 int rc = IO_OK;
3210 struct CommandList *c;
3211 struct ErrorInfo *ei;
3212
3213 c = cmd_alloc(h);
3214
3215 rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize,
3216 0, RAID_CTLR_LUNID, TYPE_CMD);
3217 if (rc)
3218 goto out;
3219
3220 c->Request.CDB[2] = bmic_device_index & 0xff;
3221 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3222
3223 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3224 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
d04e62b9
KB		 3225 if (rc)
3226 goto out;
3227 ei = c->err_info;
3228 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3229 hpsa_scsi_interpret_error(h, c);
3230 rc = -1;
3231 }
3232out:
3233 cmd_free(h, c);
3234 return rc;
3235}
3236
66749d0d
ST		 3237static int hpsa_bmic_id_controller(struct ctlr_info *h,
3238 struct bmic_identify_controller *buf, size_t bufsize)
3239{
3240 int rc = IO_OK;
3241 struct CommandList *c;
3242 struct ErrorInfo *ei;
3243
3244 c = cmd_alloc(h);
3245
3246 rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize,
3247 0, RAID_CTLR_LUNID, TYPE_CMD);
3248 if (rc)
3249 goto out;
3250
3251 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3252 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
66749d0d
ST		 3253 if (rc)
3254 goto out;
3255 ei = c->err_info;
3256 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3257 hpsa_scsi_interpret_error(h, c);
3258 rc = -1;
3259 }
3260out:
3261 cmd_free(h, c);
3262 return rc;
3263}
3264
03383736
DB		 3265static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
3266 unsigned char scsi3addr[], u16 bmic_device_index,
3267 struct bmic_identify_physical_device *buf, size_t bufsize)
3268{
3269 int rc = IO_OK;
3270 struct CommandList *c;
3271 struct ErrorInfo *ei;
3272
3273 c = cmd_alloc(h);
3274 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
3275 0, RAID_CTLR_LUNID, TYPE_CMD);
3276 if (rc)
3277 goto out;
3278
3279 c->Request.CDB[2] = bmic_device_index & 0xff;
3280 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3281
25163bd5 3282 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
c448ecfa 3283 DEFAULT_TIMEOUT);
03383736
DB		 3284 ei = c->err_info;
3285 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3286 hpsa_scsi_interpret_error(h, c);
3287 rc = -1;
3288 }
3289out:
3290 cmd_free(h, c);
d04e62b9 3291
03383736
DB		 3292 return rc;
3293}
3294
cca8f13b
DB		 3295/*
3296 * get enclosure information
3297 * struct ReportExtendedLUNdata *rlep - Used for BMIC drive number
3298 * struct hpsa_scsi_dev_t *encl_dev - device entry for enclosure
3299 * Uses id_physical_device to determine the box_index.
3300 */
3301static void hpsa_get_enclosure_info(struct ctlr_info *h,
3302 unsigned char *scsi3addr,
3303 struct ReportExtendedLUNdata *rlep, int rle_index,
3304 struct hpsa_scsi_dev_t *encl_dev)
3305{
3306 int rc = -1;
3307 struct CommandList *c = NULL;
3308 struct ErrorInfo *ei = NULL;
3309 struct bmic_sense_storage_box_params *bssbp = NULL;
3310 struct bmic_identify_physical_device *id_phys = NULL;
3311 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
3312 u16 bmic_device_index = 0;
3313
3314 bmic_device_index = GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]);
3315
17a9e54a
DB		 3316 if (bmic_device_index == 0xFF00 || MASKED_DEVICE(&rle->lunid[0])) {
3317 rc = IO_OK;
cca8f13b 3318 goto out;
17a9e54a 3319 }
cca8f13b
DB		 3320
3321 bssbp = kzalloc(sizeof(*bssbp), GFP_KERNEL);
3322 if (!bssbp)
3323 goto out;
3324
3325 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
3326 if (!id_phys)
3327 goto out;
3328
3329 rc = hpsa_bmic_id_physical_device(h, scsi3addr, bmic_device_index,
3330 id_phys, sizeof(*id_phys));
3331 if (rc) {
3332 dev_warn(&h->pdev->dev, "%s: id_phys failed %d bdi[0x%x]\n",
3333 __func__, encl_dev->external, bmic_device_index);
3334 goto out;
3335 }
3336
3337 c = cmd_alloc(h);
3338
3339 rc = fill_cmd(c, BMIC_SENSE_STORAGE_BOX_PARAMS, h, bssbp,
3340 sizeof(*bssbp), 0, RAID_CTLR_LUNID, TYPE_CMD);
3341
3342 if (rc)
3343 goto out;
3344
3345 if (id_phys->phys_connector[1] == 'E')
3346 c->Request.CDB[5] = id_phys->box_index;
3347 else
3348 c->Request.CDB[5] = 0;
3349
3350 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
c448ecfa 3351 DEFAULT_TIMEOUT);
cca8f13b
DB		 3352 if (rc)
3353 goto out;
3354
3355 ei = c->err_info;
3356 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3357 rc = -1;
3358 goto out;
3359 }
3360
3361 encl_dev->box[id_phys->active_path_number] = bssbp->phys_box_on_port;
3362 memcpy(&encl_dev->phys_connector[id_phys->active_path_number],
3363 bssbp->phys_connector, sizeof(bssbp->phys_connector));
3364
3365 rc = IO_OK;
3366out:
3367 kfree(bssbp);
3368 kfree(id_phys);
3369
3370 if (c)
3371 cmd_free(h, c);
3372
3373 if (rc != IO_OK)
3374 hpsa_show_dev_msg(KERN_INFO, h, encl_dev,
3375 "Error, could not get enclosure information\n");
3376}
3377
d04e62b9
KB		 3378static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h,
3379 unsigned char *scsi3addr)
3380{
3381 struct ReportExtendedLUNdata *physdev;
3382 u32 nphysicals;
3383 u64 sa = 0;
3384 int i;
3385
3386 physdev = kzalloc(sizeof(*physdev), GFP_KERNEL);
3387 if (!physdev)
3388 return 0;
3389
3390 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
3391 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3392 kfree(physdev);
3393 return 0;
3394 }
3395 nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24;
3396
3397 for (i = 0; i < nphysicals; i++)
3398 if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) {
3399 sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]);
3400 break;
3401 }
3402
3403 kfree(physdev);
3404
3405 return sa;
3406}
3407
3408static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr,
3409 struct hpsa_scsi_dev_t *dev)
3410{
3411 int rc;
3412 u64 sa = 0;
3413
3414 if (is_hba_lunid(scsi3addr)) {
3415 struct bmic_sense_subsystem_info *ssi;
3416
3417 ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
3418 if (ssi == NULL) {
3419 dev_warn(&h->pdev->dev,
3420 "%s: out of memory\n", __func__);
3421 return;
3422 }
3423
3424 rc = hpsa_bmic_sense_subsystem_information(h,
3425 scsi3addr, 0, ssi, sizeof(*ssi));
3426 if (rc == 0) {
3427 sa = get_unaligned_be64(ssi->primary_world_wide_id);
3428 h->sas_address = sa;
3429 }
3430
3431 kfree(ssi);
3432 } else
3433 sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr);
3434
3435 dev->sas_address = sa;
3436}
3437
3438/* Get a device id from inquiry page 0x83 */
1b70150a
SC		 3439static int hpsa_vpd_page_supported(struct ctlr_info *h,
3440 unsigned char scsi3addr[], u8 page)
3441{
3442 int rc;
3443 int i;
3444 int pages;
3445 unsigned char *buf, bufsize;
3446
3447 buf = kzalloc(256, GFP_KERNEL);
3448 if (!buf)
3449 return 0;
3450
3451 /* Get the size of the page list first */
3452 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3453 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3454 buf, HPSA_VPD_HEADER_SZ);
3455 if (rc != 0)
3456 goto exit_unsupported;
3457 pages = buf[3];
3458 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3459 bufsize = pages + HPSA_VPD_HEADER_SZ;
3460 else
3461 bufsize = 255;
3462
3463 /* Get the whole VPD page list */
3464 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3465 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3466 buf, bufsize);
3467 if (rc != 0)
3468 goto exit_unsupported;
3469
3470 pages = buf[3];
3471 for (i = 1; i <= pages; i++)
3472 if (buf[3 + i] == page)
3473 goto exit_supported;
3474exit_unsupported:
3475 kfree(buf);
3476 return 0;
3477exit_supported:
3478 kfree(buf);
3479 return 1;
3480}
3481
283b4a9b
SC		 3482static void hpsa_get_ioaccel_status(struct ctlr_info *h,
3483 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3484{
3485 int rc;
3486 unsigned char *buf;
3487 u8 ioaccel_status;
3488
3489 this_device->offload_config = 0;
3490 this_device->offload_enabled = 0;
41ce4c35 3491 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 3492
3493 buf = kzalloc(64, GFP_KERNEL);
3494 if (!buf)
3495 return;
1b70150a
SC		 3496 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
3497 goto out;
283b4a9b 3498 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 3499 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 3500 if (rc != 0)
3501 goto out;
3502
3503#define IOACCEL_STATUS_BYTE 4
3504#define OFFLOAD_CONFIGURED_BIT 0x01
3505#define OFFLOAD_ENABLED_BIT 0x02
3506 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
3507 this_device->offload_config =
3508 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3509 if (this_device->offload_config) {
3510 this_device->offload_enabled =
3511 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3512 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3513 this_device->offload_enabled = 0;
3514 }
41ce4c35 3515 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 3516out:
3517 kfree(buf);
3518 return;
3519}
3520
edd16368
SC		 3521/* Get the device id from inquiry page 0x83 */
3522static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
75d23d89 3523 unsigned char *device_id, int index, int buflen)
edd16368
SC		 3524{
3525 int rc;
3526 unsigned char *buf;
3527
3528 if (buflen > 16)
3529 buflen = 16;
3530 buf = kzalloc(64, GFP_KERNEL);
3531 if (!buf)
a84d794d 3532 return -ENOMEM;
b7bb24eb 3533 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368 3534 if (rc == 0)
75d23d89
DB		 3535 memcpy(device_id, &buf[index], buflen);
3536
edd16368 3537 kfree(buf);
75d23d89 3538
edd16368
SC		 3539 return rc != 0;
3540}
3541
3542static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 3543 void *buf, int bufsize,
edd16368
SC		 3544 int extended_response)
3545{
3546 int rc = IO_OK;
3547 struct CommandList *c;
3548 unsigned char scsi3addr[8];
3549 struct ErrorInfo *ei;
3550
45fcb86e 3551 c = cmd_alloc(h);
bf43caf3 3552
e89c0ae7
SC		 3553 /* address the controller */
3554 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 3555 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3556 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3557 rc = -1;
3558 goto out;
3559 }
edd16368
SC		 3560 if (extended_response)
3561 c->Request.CDB[1] = extended_response;
25163bd5 3562 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3563 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 3564 if (rc)
3565 goto out;
edd16368
SC		 3566 ei = c->err_info;
3567 if (ei->CommandStatus != 0 &&
3568 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3569 hpsa_scsi_interpret_error(h, c);
edd16368 3570 rc = -1;
283b4a9b 3571 } else {
03383736
DB		 3572 struct ReportLUNdata *rld = buf;
3573
3574 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 3575 dev_err(&h->pdev->dev,
3576 "report luns requested format %u, got %u\n",
3577 extended_response,
03383736 3578 rld->extended_response_flag);
283b4a9b
SC		 3579 rc = -1;
3580 }
edd16368 3581 }
a2dac136 3582out:
45fcb86e 3583 cmd_free(h, c);
edd16368
SC		 3584 return rc;
3585}
3586
3587static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 3588 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 3589{
03383736
DB		 3590 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3591 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 3592}
3593
3594static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3595 struct ReportLUNdata *buf, int bufsize)
3596{
3597 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3598}
3599
3600static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3601 int bus, int target, int lun)
3602{
3603 device->bus = bus;
3604 device->target = target;
3605 device->lun = lun;
3606}
3607
9846590e
SC		 3608/* Use VPD inquiry to get details of volume status */
3609static int hpsa_get_volume_status(struct ctlr_info *h,
3610 unsigned char scsi3addr[])
3611{
3612 int rc;
3613 int status;
3614 int size;
3615 unsigned char *buf;
3616
3617 buf = kzalloc(64, GFP_KERNEL);
3618 if (!buf)
3619 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3620
3621 /* Does controller have VPD for logical volume status? */
24a4b078 3622 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 3623 goto exit_failed;
9846590e
SC		 3624
3625 /* Get the size of the VPD return buffer */
3626 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3627 buf, HPSA_VPD_HEADER_SZ);
24a4b078 3628 if (rc != 0)
9846590e 3629 goto exit_failed;
9846590e
SC		 3630 size = buf[3];
3631
3632 /* Now get the whole VPD buffer */
3633 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3634 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 3635 if (rc != 0)
9846590e 3636 goto exit_failed;
9846590e
SC		 3637 status = buf[4]; /* status byte */
3638
3639 kfree(buf);
3640 return status;
3641exit_failed:
3642 kfree(buf);
3643 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3644}
3645
3646/* Determine offline status of a volume.
3647 * Return either:
3648 * 0 (not offline)
67955ba3 3649 * 0xff (offline for unknown reasons)
9846590e
SC		 3650 * # (integer code indicating one of several NOT READY states
3651 * describing why a volume is to be kept offline)
3652 */
67955ba3 3653static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 3654 unsigned char scsi3addr[])
3655{
3656 struct CommandList *c;
9437ac43
SC		 3657 unsigned char *sense;
3658 u8 sense_key, asc, ascq;
3659 int sense_len;
25163bd5 3660 int rc, ldstat = 0;
9846590e
SC		 3661 u16 cmd_status;
3662 u8 scsi_status;
3663#define ASC_LUN_NOT_READY 0x04
3664#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3665#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3666
3667 c = cmd_alloc(h);
bf43caf3 3668
9846590e 3669 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
c448ecfa
DB		 3670 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
3671 DEFAULT_TIMEOUT);
25163bd5
WS		 3672 if (rc) {
3673 cmd_free(h, c);
3674 return 0;
3675 }
9846590e 3676 sense = c->err_info->SenseInfo;
9437ac43
SC		 3677 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3678 sense_len = sizeof(c->err_info->SenseInfo);
3679 else
3680 sense_len = c->err_info->SenseLen;
3681 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 3682 cmd_status = c->err_info->CommandStatus;
3683 scsi_status = c->err_info->ScsiStatus;
3684 cmd_free(h, c);
3685 /* Is the volume 'not ready'? */
3686 if (cmd_status != CMD_TARGET_STATUS ||
3687 scsi_status != SAM_STAT_CHECK_CONDITION ||
3688 sense_key != NOT_READY ||
3689 asc != ASC_LUN_NOT_READY) {
3690 return 0;
3691 }
3692
3693 /* Determine the reason for not ready state */
3694 ldstat = hpsa_get_volume_status(h, scsi3addr);
3695
3696 /* Keep volume offline in certain cases: */
3697 switch (ldstat) {
3698 case HPSA_LV_UNDERGOING_ERASE:
5ca01204 3699 case HPSA_LV_NOT_AVAILABLE:
9846590e
SC		 3700 case HPSA_LV_UNDERGOING_RPI:
3701 case HPSA_LV_PENDING_RPI:
3702 case HPSA_LV_ENCRYPTED_NO_KEY:
3703 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3704 case HPSA_LV_UNDERGOING_ENCRYPTION:
3705 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3706 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3707 return ldstat;
3708 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3709 /* If VPD status page isn't available,
3710 * use ASC/ASCQ to determine state
3711 */
3712 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3713 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3714 return ldstat;
3715 break;
3716 default:
3717 break;
3718 }
3719 return 0;
3720}
3721
9b5c48c2
SC		 3722/*
3723 * Find out if a logical device supports aborts by simply trying one.
3724 * Smart Array may claim not to support aborts on logical drives, but
3725 * if a MSA2000 * is connected, the drives on that will be presented
3726 * by the Smart Array as logical drives, and aborts may be sent to
3727 * those devices successfully. So the simplest way to find out is
3728 * to simply try an abort and see how the device responds.
3729 */
3730static int hpsa_device_supports_aborts(struct ctlr_info *h,
3731 unsigned char *scsi3addr)
3732{
3733 struct CommandList *c;
3734 struct ErrorInfo *ei;
3735 int rc = 0;
3736
3737 u64 tag = (u64) -1; /* bogus tag */
3738
3739 /* Assume that physical devices support aborts */
3740 if (!is_logical_dev_addr_mode(scsi3addr))
3741 return 1;
3742
3743 c = cmd_alloc(h);
bf43caf3 3744
9b5c48c2 3745 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
c448ecfa
DB		 3746 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
3747 DEFAULT_TIMEOUT);
9b5c48c2
SC		 3748 /* no unmap needed here because no data xfer. */
3749 ei = c->err_info;
3750 switch (ei->CommandStatus) {
3751 case CMD_INVALID:
3752 rc = 0;
3753 break;
3754 case CMD_UNABORTABLE:
3755 case CMD_ABORT_FAILED:
3756 rc = 1;
3757 break;
9437ac43
SC		 3758 case CMD_TMF_STATUS:
3759 rc = hpsa_evaluate_tmf_status(h, c);
3760 break;
9b5c48c2
SC		 3761 default:
3762 rc = 0;
3763 break;
3764 }
3765 cmd_free(h, c);
3766 return rc;
3767}
3768
edd16368 3769static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3770 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3771 unsigned char *is_OBDR_device)
edd16368 3772{
0b0e1d6c
SC		 3773
3774#define OBDR_SIG_OFFSET 43
3775#define OBDR_TAPE_SIG "$DR-10"
3776#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3777#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3778
ea6d3bc3 3779 unsigned char *inq_buff;
0b0e1d6c 3780 unsigned char *obdr_sig;
683fc444 3781 int rc = 0;
edd16368 3782
ea6d3bc3 3783 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
683fc444
DB		 3784 if (!inq_buff) {
3785 rc = -ENOMEM;
edd16368 3786 goto bail_out;
683fc444 3787 }
edd16368 3788
edd16368
SC		 3789 /* Do an inquiry to the device to see what it is. */
3790 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3791 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3792 /* Inquiry failed (msg printed already) */
3793 dev_err(&h->pdev->dev,
3794 "hpsa_update_device_info: inquiry failed\n");
683fc444 3795 rc = -EIO;
edd16368
SC		 3796 goto bail_out;
3797 }
3798
4af61e4f
DB		 3799 scsi_sanitize_inquiry_string(&inq_buff[8], 8);
3800 scsi_sanitize_inquiry_string(&inq_buff[16], 16);
75d23d89 3801
edd16368
SC		 3802 this_device->devtype = (inq_buff[0] & 0x1f);
3803 memcpy(this_device->scsi3addr, scsi3addr, 8);
3804 memcpy(this_device->vendor, &inq_buff[8],
3805 sizeof(this_device->vendor));
3806 memcpy(this_device->model, &inq_buff[16],
3807 sizeof(this_device->model));
edd16368
SC		 3808 memset(this_device->device_id, 0,
3809 sizeof(this_device->device_id));
75d23d89 3810 hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8,
edd16368
SC		 3811 sizeof(this_device->device_id));
3812
af15ed36
DB		 3813 if ((this_device->devtype == TYPE_DISK ||
3814 this_device->devtype == TYPE_ZBC) &&
283b4a9b 3815 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3816 int volume_offline;
3817
edd16368 3818 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3819 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3820 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3821 volume_offline = hpsa_volume_offline(h, scsi3addr);
3822 if (volume_offline < 0 || volume_offline > 0xff)
3823 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3824 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3825 } else {
edd16368 3826 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3827 this_device->offload_config = 0;
3828 this_device->offload_enabled = 0;
41ce4c35 3829 this_device->offload_to_be_enabled = 0;
a3144e0b 3830 this_device->hba_ioaccel_enabled = 0;
9846590e 3831 this_device->volume_offline = 0;
03383736 3832 this_device->queue_depth = h->nr_cmds;
283b4a9b 3833 }
edd16368 3834
0b0e1d6c
SC		 3835 if (is_OBDR_device) {
3836 /* See if this is a One-Button-Disaster-Recovery device
3837 * by looking for "$DR-10" at offset 43 in inquiry data.
3838 */
3839 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3840 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3841 strncmp(obdr_sig, OBDR_TAPE_SIG,
3842 OBDR_SIG_LEN) == 0);
3843 }
edd16368
SC		 3844 kfree(inq_buff);
3845 return 0;
3846
3847bail_out:
3848 kfree(inq_buff);
683fc444 3849 return rc;
edd16368
SC		 3850}
3851
9b5c48c2
SC		 3852static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3853 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3854{
3855 unsigned long flags;
3856 int rc, entry;
3857 /*
3858 * See if this device supports aborts. If we already know
3859 * the device, we already know if it supports aborts, otherwise
3860 * we have to find out if it supports aborts by trying one.
3861 */
3862 spin_lock_irqsave(&h->devlock, flags);
3863 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3864 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3865 entry >= 0 && entry < h->ndevices) {
3866 dev->supports_aborts = h->dev[entry]->supports_aborts;
3867 spin_unlock_irqrestore(&h->devlock, flags);
3868 } else {
3869 spin_unlock_irqrestore(&h->devlock, flags);
3870 dev->supports_aborts =
3871 hpsa_device_supports_aborts(h, scsi3addr);
3872 if (dev->supports_aborts < 0)
3873 dev->supports_aborts = 0;
3874 }
3875}
3876
c795505a
KB		 3877/*
3878 * Helper function to assign bus, target, lun mapping of devices.
edd16368
SC		 3879 * Logical drive target and lun are assigned at this time, but
3880 * physical device lun and target assignment are deferred (assigned
3881 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
c795505a 3882*/
edd16368 3883static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3884 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3885{
c795505a 3886 u32 lunid = get_unaligned_le32(lunaddrbytes);
1f310bde
SC		 3887
3888 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3889 /* physical device, target and lun filled in later */
edd16368 3890 if (is_hba_lunid(lunaddrbytes))
c795505a
KB		 3891 hpsa_set_bus_target_lun(device,
3892 HPSA_HBA_BUS, 0, lunid & 0x3fff);
edd16368 3893 else
1f310bde 3894 /* defer target, lun assignment for physical devices */
c795505a
KB		 3895 hpsa_set_bus_target_lun(device,
3896 HPSA_PHYSICAL_DEVICE_BUS, -1, -1);
1f310bde
SC		 3897 return;
3898 }
3899 /* It's a logical device */
66749d0d 3900 if (device->external) {
1f310bde 3901 hpsa_set_bus_target_lun(device,
c795505a
KB		 3902 HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff,
3903 lunid & 0x00ff);
1f310bde 3904 return;
edd16368 3905 }
c795505a
KB		 3906 hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS,
3907 0, lunid & 0x3fff);
edd16368
SC		 3908}
3909
edd16368 3910
54b6e9e9
ST		 3911/*
3912 * Get address of physical disk used for an ioaccel2 mode command:
3913 * 1. Extract ioaccel2 handle from the command.
3914 * 2. Find a matching ioaccel2 handle from list of physical disks.
3915 * 3. Return:
3916 * 1 and set scsi3addr to address of matching physical
3917 * 0 if no matching physical disk was found.
3918 */
3919static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3920 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3921{
41ce4c35
SC		 3922 struct io_accel2_cmd *c2 =
3923 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3924 unsigned long flags;
54b6e9e9 3925 int i;
54b6e9e9 3926
41ce4c35
SC		 3927 spin_lock_irqsave(&h->devlock, flags);
3928 for (i = 0; i < h->ndevices; i++)
3929 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3930 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3931 sizeof(h->dev[i]->scsi3addr));
3932 spin_unlock_irqrestore(&h->devlock, flags);
3933 return 1;
3934 }
3935 spin_unlock_irqrestore(&h->devlock, flags);
3936 return 0;
54b6e9e9 3937}
41ce4c35 3938
66749d0d
ST		 3939static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position,
3940 int i, int nphysicals, int nlocal_logicals)
3941{
3942 /* In report logicals, local logicals are listed first,
3943 * then any externals.
3944 */
3945 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3946
3947 if (i == raid_ctlr_position)
3948 return 0;
3949
3950 if (i < logicals_start)
3951 return 0;
3952
3953 /* i is in logicals range, but still within local logicals */
3954 if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals)
3955 return 0;
3956
3957 return 1; /* it's an external lun */
3958}
3959
edd16368
SC		 3960/*
3961 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3962 * logdev. The number of luns in physdev and logdev are returned in
3963 * *nphysicals and *nlogicals, respectively.
3964 * Returns 0 on success, -1 otherwise.
3965 */
3966static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3967 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3968 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3969{
03383736 3970 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3971 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3972 return -1;
3973 }
03383736 3974 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3975 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3976 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3977 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3978 *nphysicals = HPSA_MAX_PHYS_LUN;
3979 }
03383736 3980 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3981 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3982 return -1;
3983 }
6df1e954 3984 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3985 /* Reject Logicals in excess of our max capability. */
3986 if (*nlogicals > HPSA_MAX_LUN) {
3987 dev_warn(&h->pdev->dev,
3988 "maximum logical LUNs (%d) exceeded. "
3989 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3990 *nlogicals - HPSA_MAX_LUN);
3991 *nlogicals = HPSA_MAX_LUN;
3992 }
3993 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3994 dev_warn(&h->pdev->dev,
3995 "maximum logical + physical LUNs (%d) exceeded. "
3996 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3997 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3998 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3999 }
4000 return 0;
4001}
4002
42a91641
DB		 4003static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
4004 int i, int nphysicals, int nlogicals,
a93aa1fe 4005 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 4006 struct ReportLUNdata *logdev_list)
4007{
4008 /* Helper function, figure out where the LUN ID info is coming from
4009 * given index i, lists of physical and logical devices, where in
4010 * the list the raid controller is supposed to appear (first or last)
4011 */
4012
4013 int logicals_start = nphysicals + (raid_ctlr_position == 0);
4014 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
4015
4016 if (i == raid_ctlr_position)
4017 return RAID_CTLR_LUNID;
4018
4019 if (i < logicals_start)
d5b5d964
SC		 4020 return &physdev_list->LUN[i -
4021 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 4022
4023 if (i < last_device)
4024 return &logdev_list->LUN[i - nphysicals -
4025 (raid_ctlr_position == 0)][0];
4026 BUG();
4027 return NULL;
4028}
4029
03383736
DB		 4030/* get physical drive ioaccel handle and queue depth */
4031static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
4032 struct hpsa_scsi_dev_t *dev,
f2039b03 4033 struct ReportExtendedLUNdata *rlep, int rle_index,
03383736
DB		 4034 struct bmic_identify_physical_device *id_phys)
4035{
4036 int rc;
f2039b03 4037 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
03383736
DB		 4038
4039 dev->ioaccel_handle = rle->ioaccel_handle;
f2039b03 4040 if ((rle->device_flags & 0x08) && dev->ioaccel_handle)
a3144e0b 4041 dev->hba_ioaccel_enabled = 1;
03383736 4042 memset(id_phys, 0, sizeof(*id_phys));
f2039b03
DB		 4043 rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0],
4044 GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys,
03383736
DB		 4045 sizeof(*id_phys));
4046 if (!rc)
4047 /* Reserve space for FW operations */
4048#define DRIVE_CMDS_RESERVED_FOR_FW 2
4049#define DRIVE_QUEUE_DEPTH 7
4050 dev->queue_depth =
4051 le16_to_cpu(id_phys->current_queue_depth_limit) -
4052 DRIVE_CMDS_RESERVED_FOR_FW;
4053 else
4054 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
03383736
DB		 4055}
4056
8270b862 4057static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
f2039b03 4058 struct ReportExtendedLUNdata *rlep, int rle_index,
8270b862
JH		 4059 struct bmic_identify_physical_device *id_phys)
4060{
f2039b03
DB		 4061 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
4062
4063 if ((rle->device_flags & 0x08) && this_device->ioaccel_handle)
8270b862
JH		 4064 this_device->hba_ioaccel_enabled = 1;
4065
4066 memcpy(&this_device->active_path_index,
4067 &id_phys->active_path_number,
4068 sizeof(this_device->active_path_index));
4069 memcpy(&this_device->path_map,
4070 &id_phys->redundant_path_present_map,
4071 sizeof(this_device->path_map));
4072 memcpy(&this_device->box,
4073 &id_phys->alternate_paths_phys_box_on_port,
4074 sizeof(this_device->box));
4075 memcpy(&this_device->phys_connector,
4076 &id_phys->alternate_paths_phys_connector,
4077 sizeof(this_device->phys_connector));
4078 memcpy(&this_device->bay,
4079 &id_phys->phys_bay_in_box,
4080 sizeof(this_device->bay));
4081}
4082
66749d0d
ST		 4083/* get number of local logical disks. */
4084static int hpsa_set_local_logical_count(struct ctlr_info *h,
4085 struct bmic_identify_controller *id_ctlr,
4086 u32 *nlocals)
4087{
4088 int rc;
4089
4090 if (!id_ctlr) {
4091 dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n",
4092 __func__);
4093 return -ENOMEM;
4094 }
4095 memset(id_ctlr, 0, sizeof(*id_ctlr));
4096 rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr));
4097 if (!rc)
4098 if (id_ctlr->configured_logical_drive_count < 256)
4099 *nlocals = id_ctlr->configured_logical_drive_count;
4100 else
4101 *nlocals = le16_to_cpu(
4102 id_ctlr->extended_logical_unit_count);
4103 else
4104 *nlocals = -1;
4105 return rc;
4106}
4107
4108
8aa60681 4109static void hpsa_update_scsi_devices(struct ctlr_info *h)
edd16368
SC		 4110{
4111 /* the idea here is we could get notified
4112 * that some devices have changed, so we do a report
4113 * physical luns and report logical luns cmd, and adjust
4114 * our list of devices accordingly.
4115 *
4116 * The scsi3addr's of devices won't change so long as the
4117 * adapter is not reset. That means we can rescan and
4118 * tell which devices we already know about, vs. new
4119 * devices, vs. disappearing devices.
4120 */
a93aa1fe 4121 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 4122 struct ReportLUNdata *logdev_list = NULL;
03383736 4123 struct bmic_identify_physical_device *id_phys = NULL;
66749d0d 4124 struct bmic_identify_controller *id_ctlr = NULL;
01a02ffc
SC		 4125 u32 nphysicals = 0;
4126 u32 nlogicals = 0;
66749d0d 4127 u32 nlocal_logicals = 0;
01a02ffc 4128 u32 ndev_allocated = 0;
edd16368
SC		 4129 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
4130 int ncurrent = 0;
4f4eb9f1 4131 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 4132 int raid_ctlr_position;
04fa2f44 4133 bool physical_device;
aca4a520 4134 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 4135
cfe5badc 4136 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 4137 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
4138 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 4139 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 4140 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
66749d0d 4141 id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL);
edd16368 4142
03383736 4143 if (!currentsd || !physdev_list || !logdev_list ||
66749d0d 4144 !tmpdevice || !id_phys || !id_ctlr) {
edd16368
SC		 4145 dev_err(&h->pdev->dev, "out of memory\n");
4146 goto out;
4147 }
4148 memset(lunzerobits, 0, sizeof(lunzerobits));
4149
853633e8
DB		 4150 h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */
4151
03383736 4152 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
853633e8
DB		 4153 logdev_list, &nlogicals)) {
4154 h->drv_req_rescan = 1;
edd16368 4155 goto out;
853633e8 4156 }
edd16368 4157
66749d0d
ST		 4158 /* Set number of local logicals (non PTRAID) */
4159 if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) {
4160 dev_warn(&h->pdev->dev,
4161 "%s: Can't determine number of local logical devices.\n",
4162 __func__);
4163 }
edd16368 4164
aca4a520
ST		 4165 /* We might see up to the maximum number of logical and physical disks
4166 * plus external target devices, and a device for the local RAID
4167 * controller.
edd16368 4168 */
aca4a520 4169 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 4170
4171 /* Allocate the per device structures */
4172 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 4173 if (i >= HPSA_MAX_DEVICES) {
4174 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
4175 " %d devices ignored.\n", HPSA_MAX_DEVICES,
4176 ndevs_to_allocate - HPSA_MAX_DEVICES);
4177 break;
4178 }
4179
edd16368
SC		 4180 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
4181 if (!currentsd[i]) {
4182 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
4183 __FILE__, __LINE__);
853633e8 4184 h->drv_req_rescan = 1;
edd16368
SC		 4185 goto out;
4186 }
4187 ndev_allocated++;
4188 }
4189
8645291b 4190 if (is_scsi_rev_5(h))
339b2b14
SC		 4191 raid_ctlr_position = 0;
4192 else
4193 raid_ctlr_position = nphysicals + nlogicals;
4194
edd16368 4195 /* adjust our table of devices */
4f4eb9f1 4196 n_ext_target_devs = 0;
edd16368 4197 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 4198 u8 *lunaddrbytes, is_OBDR = 0;
683fc444 4199 int rc = 0;
f2039b03 4200 int phys_dev_index = i - (raid_ctlr_position == 0);
edd16368 4201
04fa2f44 4202 physical_device = i < nphysicals + (raid_ctlr_position == 0);
edd16368
SC		 4203
4204 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 4205 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
4206 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 4207
4208 /* skip masked non-disk devices */
04fa2f44 4209 if (MASKED_DEVICE(lunaddrbytes) && physical_device &&
cca8f13b
DB		 4210 (physdev_list->LUN[phys_dev_index].device_type != 0x06) &&
4211 (physdev_list->LUN[phys_dev_index].device_flags & 0x01))
04fa2f44 4212 continue;
edd16368
SC		 4213
4214 /* Get device type, vendor, model, device id */
683fc444
DB		 4215 rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
4216 &is_OBDR);
4217 if (rc == -ENOMEM) {
4218 dev_warn(&h->pdev->dev,
4219 "Out of memory, rescan deferred.\n");
853633e8 4220 h->drv_req_rescan = 1;
683fc444 4221 goto out;
853633e8 4222 }
683fc444
DB		 4223 if (rc) {
4224 dev_warn(&h->pdev->dev,
4225 "Inquiry failed, skipping device.\n");
4226 continue;
4227 }
4228
66749d0d
ST		 4229 /* Determine if this is a lun from an external target array */
4230 tmpdevice->external =
4231 figure_external_status(h, raid_ctlr_position, i,
4232 nphysicals, nlocal_logicals);
4233
1f310bde 4234 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 4235 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 4236 this_device = currentsd[ncurrent];
4237
34592254
ST		 4238 /* Turn on discovery_polling if there are ext target devices.
4239 * Event-based change notification is unreliable for those.
edd16368 4240 */
34592254
ST		 4241 if (!h->discovery_polling) {
4242 if (tmpdevice->external) {
4243 h->discovery_polling = 1;
4244 dev_info(&h->pdev->dev,
4245 "External target, activate discovery polling.\n");
4246 }
edd16368
SC		 4247 }
4248
34592254 4249
edd16368 4250 *this_device = *tmpdevice;
04fa2f44 4251 this_device->physical_device = physical_device;
edd16368 4252
04fa2f44
KB		 4253 /*
4254 * Expose all devices except for physical devices that
4255 * are masked.
4256 */
4257 if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device)
2a168208
KB		 4258 this_device->expose_device = 0;
4259 else
4260 this_device->expose_device = 1;
41ce4c35 4261
d04e62b9
KB		 4262
4263 /*
4264 * Get the SAS address for physical devices that are exposed.
4265 */
4266 if (this_device->physical_device && this_device->expose_device)
4267 hpsa_get_sas_address(h, lunaddrbytes, this_device);
41ce4c35 4268
edd16368 4269 switch (this_device->devtype) {
0b0e1d6c 4270 case TYPE_ROM:
edd16368
SC		 4271 /* We don't *really* support actual CD-ROM devices,
4272 * just "One Button Disaster Recovery" tape drive
4273 * which temporarily pretends to be a CD-ROM drive.
4274 * So we check that the device is really an OBDR tape
4275 * device by checking for "$DR-10" in bytes 43-48 of
4276 * the inquiry data.
4277 */
0b0e1d6c
SC		 4278 if (is_OBDR)
4279 ncurrent++;
edd16368
SC		 4280 break;
4281 case TYPE_DISK:
af15ed36 4282 case TYPE_ZBC:
04fa2f44 4283 if (this_device->physical_device) {
b9092b79
KB		 4284 /* The disk is in HBA mode. */
4285 /* Never use RAID mapper in HBA mode. */
ecf418d1 4286 this_device->offload_enabled = 0;
b9092b79 4287 hpsa_get_ioaccel_drive_info(h, this_device,
f2039b03
DB		 4288 physdev_list, phys_dev_index, id_phys);
4289 hpsa_get_path_info(this_device,
4290 physdev_list, phys_dev_index, id_phys);
b9092b79 4291 }
ecf418d1 4292 ncurrent++;
edd16368
SC		 4293 break;
4294 case TYPE_TAPE:
4295 case TYPE_MEDIUM_CHANGER:
cca8f13b
DB		 4296 ncurrent++;
4297 break;
41ce4c35 4298 case TYPE_ENCLOSURE:
17a9e54a
DB		 4299 if (!this_device->external)
4300 hpsa_get_enclosure_info(h, lunaddrbytes,
cca8f13b
DB		 4301 physdev_list, phys_dev_index,
4302 this_device);
b9092b79 4303 ncurrent++;
41ce4c35 4304 break;
edd16368
SC		 4305 case TYPE_RAID:
4306 /* Only present the Smartarray HBA as a RAID controller.
4307 * If it's a RAID controller other than the HBA itself
4308 * (an external RAID controller, MSA500 or similar)
4309 * don't present it.
4310 */
4311 if (!is_hba_lunid(lunaddrbytes))
4312 break;
4313 ncurrent++;
4314 break;
4315 default:
4316 break;
4317 }
cfe5badc 4318 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 4319 break;
4320 }
d04e62b9
KB		 4321
4322 if (h->sas_host == NULL) {
4323 int rc = 0;
4324
4325 rc = hpsa_add_sas_host(h);
4326 if (rc) {
4327 dev_warn(&h->pdev->dev,
4328 "Could not add sas host %d\n", rc);
4329 goto out;
4330 }
4331 }
4332
8aa60681 4333 adjust_hpsa_scsi_table(h, currentsd, ncurrent);
edd16368
SC		 4334out:
4335 kfree(tmpdevice);
4336 for (i = 0; i < ndev_allocated; i++)
4337 kfree(currentsd[i]);
4338 kfree(currentsd);
edd16368
SC		 4339 kfree(physdev_list);
4340 kfree(logdev_list);
66749d0d 4341 kfree(id_ctlr);
03383736 4342 kfree(id_phys);
edd16368
SC		 4343}
4344
ec5cbf04
WS		 4345static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
4346 struct scatterlist *sg)
4347{
4348 u64 addr64 = (u64) sg_dma_address(sg);
4349 unsigned int len = sg_dma_len(sg);
4350
4351 desc->Addr = cpu_to_le64(addr64);
4352 desc->Len = cpu_to_le32(len);
4353 desc->Ext = 0;
4354}
4355
c7ee65b3
WS		 4356/*
4357 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 4358 * dma mapping and fills in the scatter gather entries of the
4359 * hpsa command, cp.
4360 */
33a2ffce 4361static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 4362 struct CommandList *cp,
4363 struct scsi_cmnd *cmd)
4364{
edd16368 4365 struct scatterlist *sg;
b3a7ba7c 4366 int use_sg, i, sg_limit, chained, last_sg;
33a2ffce 4367 struct SGDescriptor *curr_sg;
edd16368 4368
33a2ffce 4369 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 4370
4371 use_sg = scsi_dma_map(cmd);
4372 if (use_sg < 0)
4373 return use_sg;
4374
4375 if (!use_sg)
4376 goto sglist_finished;
4377
b3a7ba7c
WS		 4378 /*
4379 * If the number of entries is greater than the max for a single list,
4380 * then we have a chained list; we will set up all but one entry in the
4381 * first list (the last entry is saved for link information);
4382 * otherwise, we don't have a chained list and we'll set up at each of
4383 * the entries in the one list.
4384 */
33a2ffce 4385 curr_sg = cp->SG;
b3a7ba7c
WS		 4386 chained = use_sg > h->max_cmd_sg_entries;
4387 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
4388 last_sg = scsi_sg_count(cmd) - 1;
4389 scsi_for_each_sg(cmd, sg, sg_limit, i) {
ec5cbf04 4390 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 4391 curr_sg++;
4392 }
ec5cbf04 4393
b3a7ba7c
WS		 4394 if (chained) {
4395 /*
4396 * Continue with the chained list. Set curr_sg to the chained
4397 * list. Modify the limit to the total count less the entries
4398 * we've already set up. Resume the scan at the list entry
4399 * where the previous loop left off.
4400 */
4401 curr_sg = h->cmd_sg_list[cp->cmdindex];
4402 sg_limit = use_sg - sg_limit;
4403 for_each_sg(sg, sg, sg_limit, i) {
4404 hpsa_set_sg_descriptor(curr_sg, sg);
4405 curr_sg++;
4406 }
4407 }
4408
ec5cbf04 4409 /* Back the pointer up to the last entry and mark it as "last". */
b3a7ba7c 4410 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 4411
4412 if (use_sg + chained > h->maxSG)
4413 h->maxSG = use_sg + chained;
4414
4415 if (chained) {
4416 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 4417 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 4418 if (hpsa_map_sg_chain_block(h, cp)) {
4419 scsi_dma_unmap(cmd);
4420 return -1;
4421 }
33a2ffce 4422 return 0;
edd16368
SC		 4423 }
4424
4425sglist_finished:
4426
01a02ffc 4427 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 4428 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 4429 return 0;
4430}
4431
283b4a9b
SC		 4432#define IO_ACCEL_INELIGIBLE (1)
4433static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
4434{
4435 int is_write = 0;
4436 u32 block;
4437 u32 block_cnt;
4438
4439 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
4440 switch (cdb[0]) {
4441 case WRITE_6:
4442 case WRITE_12:
4443 is_write = 1;
4444 case READ_6:
4445 case READ_12:
4446 if (*cdb_len == 6) {
c8a6c9a6 4447 block = get_unaligned_be16(&cdb[2]);
283b4a9b 4448 block_cnt = cdb[4];
c8a6c9a6
DB		 4449 if (block_cnt == 0)
4450 block_cnt = 256;
283b4a9b
SC		 4451 } else {
4452 BUG_ON(*cdb_len != 12);
c8a6c9a6
DB		 4453 block = get_unaligned_be32(&cdb[2]);
4454 block_cnt = get_unaligned_be32(&cdb[6]);
283b4a9b
SC		 4455 }
4456 if (block_cnt > 0xffff)
4457 return IO_ACCEL_INELIGIBLE;
4458
4459 cdb[0] = is_write ? WRITE_10 : READ_10;
4460 cdb[1] = 0;
4461 cdb[2] = (u8) (block >> 24);
4462 cdb[3] = (u8) (block >> 16);
4463 cdb[4] = (u8) (block >> 8);
4464 cdb[5] = (u8) (block);
4465 cdb[6] = 0;
4466 cdb[7] = (u8) (block_cnt >> 8);
4467 cdb[8] = (u8) (block_cnt);
4468 cdb[9] = 0;
4469 *cdb_len = 10;
4470 break;
4471 }
4472 return 0;
4473}
4474
c349775e 4475static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 4476 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4477 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 4478{
4479 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 4480 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
4481 unsigned int len;
4482 unsigned int total_len = 0;
4483 struct scatterlist *sg;
4484 u64 addr64;
4485 int use_sg, i;
4486 struct SGDescriptor *curr_sg;
4487 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
4488
283b4a9b 4489 /* TODO: implement chaining support */
03383736
DB		 4490 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
4491 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4492 return IO_ACCEL_INELIGIBLE;
03383736 4493 }
283b4a9b 4494
e1f7de0c
MG		 4495 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
4496
03383736
DB		 4497 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4498 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4499 return IO_ACCEL_INELIGIBLE;
03383736 4500 }
283b4a9b 4501
e1f7de0c
MG		 4502 c->cmd_type = CMD_IOACCEL1;
4503
4504 /* Adjust the DMA address to point to the accelerated command buffer */
4505 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
4506 (c->cmdindex * sizeof(*cp));
4507 BUG_ON(c->busaddr & 0x0000007F);
4508
4509 use_sg = scsi_dma_map(cmd);
03383736
DB		 4510 if (use_sg < 0) {
4511 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 4512 return use_sg;
03383736 4513 }
e1f7de0c
MG		 4514
4515 if (use_sg) {
4516 curr_sg = cp->SG;
4517 scsi_for_each_sg(cmd, sg, use_sg, i) {
4518 addr64 = (u64) sg_dma_address(sg);
4519 len = sg_dma_len(sg);
4520 total_len += len;
50a0decf
SC		 4521 curr_sg->Addr = cpu_to_le64(addr64);
4522 curr_sg->Len = cpu_to_le32(len);
4523 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 4524 curr_sg++;
4525 }
50a0decf 4526 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 4527
4528 switch (cmd->sc_data_direction) {
4529 case DMA_TO_DEVICE:
4530 control |= IOACCEL1_CONTROL_DATA_OUT;
4531 break;
4532 case DMA_FROM_DEVICE:
4533 control |= IOACCEL1_CONTROL_DATA_IN;
4534 break;
4535 case DMA_NONE:
4536 control |= IOACCEL1_CONTROL_NODATAXFER;
4537 break;
4538 default:
4539 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4540 cmd->sc_data_direction);
4541 BUG();
4542 break;
4543 }
4544 } else {
4545 control |= IOACCEL1_CONTROL_NODATAXFER;
4546 }
4547
c349775e 4548 c->Header.SGList = use_sg;
e1f7de0c 4549 /* Fill out the command structure to submit */
2b08b3e9
DB		 4550 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4551 cp->transfer_len = cpu_to_le32(total_len);
4552 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4553 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4554 cp->control = cpu_to_le32(control);
283b4a9b
SC		 4555 memcpy(cp->CDB, cdb, cdb_len);
4556 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 4557 /* Tag was already set at init time. */
283b4a9b 4558 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 4559 return 0;
4560}
edd16368 4561
283b4a9b
SC		 4562/*
4563 * Queue a command directly to a device behind the controller using the
4564 * I/O accelerator path.
4565 */
4566static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4567 struct CommandList *c)
4568{
4569 struct scsi_cmnd *cmd = c->scsi_cmd;
4570 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4571
03383736
DB		 4572 c->phys_disk = dev;
4573
283b4a9b 4574 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 4575 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 4576}
4577
dd0e19f3
ST		 4578/*
4579 * Set encryption parameters for the ioaccel2 request
4580 */
4581static void set_encrypt_ioaccel2(struct ctlr_info *h,
4582 struct CommandList *c, struct io_accel2_cmd *cp)
4583{
4584 struct scsi_cmnd *cmd = c->scsi_cmd;
4585 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4586 struct raid_map_data *map = &dev->raid_map;
4587 u64 first_block;
4588
dd0e19f3 4589 /* Are we doing encryption on this device */
2b08b3e9 4590 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 4591 return;
4592 /* Set the data encryption key index. */
4593 cp->dekindex = map->dekindex;
4594
4595 /* Set the encryption enable flag, encoded into direction field. */
4596 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4597
4598 /* Set encryption tweak values based on logical block address
4599 * If block size is 512, tweak value is LBA.
4600 * For other block sizes, tweak is (LBA * block size)/ 512)
4601 */
4602 switch (cmd->cmnd[0]) {
4603 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
4604 case WRITE_6:
4605 case READ_6:
2b08b3e9 4606 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 4607 break;
4608 case WRITE_10:
4609 case READ_10:
dd0e19f3
ST		 4610 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4611 case WRITE_12:
4612 case READ_12:
2b08b3e9 4613 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 4614 break;
4615 case WRITE_16:
4616 case READ_16:
2b08b3e9 4617 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 4618 break;
4619 default:
4620 dev_err(&h->pdev->dev,
2b08b3e9
DB		 4621 "ERROR: %s: size (0x%x) not supported for encryption\n",
4622 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 4623 BUG();
4624 break;
4625 }
2b08b3e9
DB		 4626
4627 if (le32_to_cpu(map->volume_blk_size) != 512)
4628 first_block = first_block *
4629 le32_to_cpu(map->volume_blk_size)/512;
4630
4631 cp->tweak_lower = cpu_to_le32(first_block);
4632 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 4633}
4634
c349775e
ST		 4635static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4636 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4637 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 4638{
4639 struct scsi_cmnd *cmd = c->scsi_cmd;
4640 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4641 struct ioaccel2_sg_element *curr_sg;
4642 int use_sg, i;
4643 struct scatterlist *sg;
4644 u64 addr64;
4645 u32 len;
4646 u32 total_len = 0;
4647
d9a729f3 4648 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 4649
03383736
DB		 4650 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4651 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4652 return IO_ACCEL_INELIGIBLE;
03383736
DB		 4653 }
4654
c349775e
ST		 4655 c->cmd_type = CMD_IOACCEL2;
4656 /* Adjust the DMA address to point to the accelerated command buffer */
4657 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4658 (c->cmdindex * sizeof(*cp));
4659 BUG_ON(c->busaddr & 0x0000007F);
4660
4661 memset(cp, 0, sizeof(*cp));
4662 cp->IU_type = IOACCEL2_IU_TYPE;
4663
4664 use_sg = scsi_dma_map(cmd);
03383736
DB		 4665 if (use_sg < 0) {
4666 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4667 return use_sg;
03383736 4668 }
c349775e
ST		 4669
4670 if (use_sg) {
c349775e 4671 curr_sg = cp->sg;
d9a729f3
WS		 4672 if (use_sg > h->ioaccel_maxsg) {
4673 addr64 = le64_to_cpu(
4674 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4675 curr_sg->address = cpu_to_le64(addr64);
4676 curr_sg->length = 0;
4677 curr_sg->reserved[0] = 0;
4678 curr_sg->reserved[1] = 0;
4679 curr_sg->reserved[2] = 0;
4680 curr_sg->chain_indicator = 0x80;
4681
4682 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4683 }
c349775e
ST		 4684 scsi_for_each_sg(cmd, sg, use_sg, i) {
4685 addr64 = (u64) sg_dma_address(sg);
4686 len = sg_dma_len(sg);
4687 total_len += len;
4688 curr_sg->address = cpu_to_le64(addr64);
4689 curr_sg->length = cpu_to_le32(len);
4690 curr_sg->reserved[0] = 0;
4691 curr_sg->reserved[1] = 0;
4692 curr_sg->reserved[2] = 0;
4693 curr_sg->chain_indicator = 0;
4694 curr_sg++;
4695 }
4696
4697 switch (cmd->sc_data_direction) {
4698 case DMA_TO_DEVICE:
dd0e19f3
ST		 4699 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4700 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 4701 break;
4702 case DMA_FROM_DEVICE:
dd0e19f3
ST		 4703 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4704 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 4705 break;
4706 case DMA_NONE:
dd0e19f3
ST		 4707 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4708 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 4709 break;
4710 default:
4711 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4712 cmd->sc_data_direction);
4713 BUG();
4714 break;
4715 }
4716 } else {
dd0e19f3
ST		 4717 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4718 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 4719 }
dd0e19f3
ST		 4720
4721 /* Set encryption parameters, if necessary */
4722 set_encrypt_ioaccel2(h, c, cp);
4723
2b08b3e9 4724 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 4725 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 4726 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 4727
c349775e
ST		 4728 cp->data_len = cpu_to_le32(total_len);
4729 cp->err_ptr = cpu_to_le64(c->busaddr +
4730 offsetof(struct io_accel2_cmd, error_data));
50a0decf 4731 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 4732
d9a729f3
WS		 4733 /* fill in sg elements */
4734 if (use_sg > h->ioaccel_maxsg) {
4735 cp->sg_count = 1;
a736e9b6 4736 cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0]));
d9a729f3
WS		 4737 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4738 atomic_dec(&phys_disk->ioaccel_cmds_out);
4739 scsi_dma_unmap(cmd);
4740 return -1;
4741 }
4742 } else
4743 cp->sg_count = (u8) use_sg;
4744
c349775e
ST		 4745 enqueue_cmd_and_start_io(h, c);
4746 return 0;
4747}
4748
4749/*
4750 * Queue a command to the correct I/O accelerator path.
4751 */
4752static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4753 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4754 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 4755{
03383736
DB		 4756 /* Try to honor the device's queue depth */
4757 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4758 phys_disk->queue_depth) {
4759 atomic_dec(&phys_disk->ioaccel_cmds_out);
4760 return IO_ACCEL_INELIGIBLE;
4761 }
c349775e
ST		 4762 if (h->transMethod & CFGTBL_Trans_io_accel1)
4763 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4764 cdb, cdb_len, scsi3addr,
4765 phys_disk);
c349775e
ST		 4766 else
4767 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4768 cdb, cdb_len, scsi3addr,
4769 phys_disk);
c349775e
ST		 4770}
4771
6b80b18f
ST		 4772static void raid_map_helper(struct raid_map_data *map,
4773 int offload_to_mirror, u32 *map_index, u32 *current_group)
4774{
4775 if (offload_to_mirror == 0) {
4776 /* use physical disk in the first mirrored group. */
2b08b3e9 4777 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4778 return;
4779 }
4780 do {
4781 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4782 *current_group = *map_index /
4783 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4784 if (offload_to_mirror == *current_group)
4785 continue;
2b08b3e9 4786 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4787 /* select map index from next group */
2b08b3e9 4788 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4789 (*current_group)++;
4790 } else {
4791 /* select map index from first group */
2b08b3e9 4792 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4793 *current_group = 0;
4794 }
4795 } while (offload_to_mirror != *current_group);
4796}
4797
283b4a9b
SC		 4798/*
4799 * Attempt to perform offload RAID mapping for a logical volume I/O.
4800 */
4801static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4802 struct CommandList *c)
4803{
4804 struct scsi_cmnd *cmd = c->scsi_cmd;
4805 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4806 struct raid_map_data *map = &dev->raid_map;
4807 struct raid_map_disk_data *dd = &map->data[0];
4808 int is_write = 0;
4809 u32 map_index;
4810 u64 first_block, last_block;
4811 u32 block_cnt;
4812 u32 blocks_per_row;
4813 u64 first_row, last_row;
4814 u32 first_row_offset, last_row_offset;
4815 u32 first_column, last_column;
6b80b18f
ST		 4816 u64 r0_first_row, r0_last_row;
4817 u32 r5or6_blocks_per_row;
4818 u64 r5or6_first_row, r5or6_last_row;
4819 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4820 u32 r5or6_first_column, r5or6_last_column;
4821 u32 total_disks_per_row;
4822 u32 stripesize;
4823 u32 first_group, last_group, current_group;
283b4a9b
SC		 4824 u32 map_row;
4825 u32 disk_handle;
4826 u64 disk_block;
4827 u32 disk_block_cnt;
4828 u8 cdb[16];
4829 u8 cdb_len;
2b08b3e9 4830 u16 strip_size;
283b4a9b
SC		 4831#if BITS_PER_LONG == 32
4832 u64 tmpdiv;
4833#endif
6b80b18f 4834 int offload_to_mirror;
283b4a9b 4835
283b4a9b
SC		 4836 /* check for valid opcode, get LBA and block count */
4837 switch (cmd->cmnd[0]) {
4838 case WRITE_6:
4839 is_write = 1;
4840 case READ_6:
c8a6c9a6 4841 first_block = get_unaligned_be16(&cmd->cmnd[2]);
283b4a9b 4842 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4843 if (block_cnt == 0)
4844 block_cnt = 256;
283b4a9b
SC		 4845 break;
4846 case WRITE_10:
4847 is_write = 1;
4848 case READ_10:
4849 first_block =
4850 (((u64) cmd->cmnd[2]) << 24) |
4851 (((u64) cmd->cmnd[3]) << 16) |
4852 (((u64) cmd->cmnd[4]) << 8) |
4853 cmd->cmnd[5];
4854 block_cnt =
4855 (((u32) cmd->cmnd[7]) << 8) |
4856 cmd->cmnd[8];
4857 break;
4858 case WRITE_12:
4859 is_write = 1;
4860 case READ_12:
4861 first_block =
4862 (((u64) cmd->cmnd[2]) << 24) |
4863 (((u64) cmd->cmnd[3]) << 16) |
4864 (((u64) cmd->cmnd[4]) << 8) |
4865 cmd->cmnd[5];
4866 block_cnt =
4867 (((u32) cmd->cmnd[6]) << 24) |
4868 (((u32) cmd->cmnd[7]) << 16) |
4869 (((u32) cmd->cmnd[8]) << 8) |
4870 cmd->cmnd[9];
4871 break;
4872 case WRITE_16:
4873 is_write = 1;
4874 case READ_16:
4875 first_block =
4876 (((u64) cmd->cmnd[2]) << 56) |
4877 (((u64) cmd->cmnd[3]) << 48) |
4878 (((u64) cmd->cmnd[4]) << 40) |
4879 (((u64) cmd->cmnd[5]) << 32) |
4880 (((u64) cmd->cmnd[6]) << 24) |
4881 (((u64) cmd->cmnd[7]) << 16) |
4882 (((u64) cmd->cmnd[8]) << 8) |
4883 cmd->cmnd[9];
4884 block_cnt =
4885 (((u32) cmd->cmnd[10]) << 24) |
4886 (((u32) cmd->cmnd[11]) << 16) |
4887 (((u32) cmd->cmnd[12]) << 8) |
4888 cmd->cmnd[13];
4889 break;
4890 default:
4891 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4892 }
283b4a9b
SC		 4893 last_block = first_block + block_cnt - 1;
4894
4895 /* check for write to non-RAID-0 */
4896 if (is_write && dev->raid_level != 0)
4897 return IO_ACCEL_INELIGIBLE;
4898
4899 /* check for invalid block or wraparound */
2b08b3e9
DB		 4900 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4901 last_block < first_block)
283b4a9b
SC		 4902 return IO_ACCEL_INELIGIBLE;
4903
4904 /* calculate stripe information for the request */
2b08b3e9
DB		 4905 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4906 le16_to_cpu(map->strip_size);
4907 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4908#if BITS_PER_LONG == 32
4909 tmpdiv = first_block;
4910 (void) do_div(tmpdiv, blocks_per_row);
4911 first_row = tmpdiv;
4912 tmpdiv = last_block;
4913 (void) do_div(tmpdiv, blocks_per_row);
4914 last_row = tmpdiv;
4915 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4916 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4917 tmpdiv = first_row_offset;
2b08b3e9 4918 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4919 first_column = tmpdiv;
4920 tmpdiv = last_row_offset;
2b08b3e9 4921 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4922 last_column = tmpdiv;
4923#else
4924 first_row = first_block / blocks_per_row;
4925 last_row = last_block / blocks_per_row;
4926 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4927 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4928 first_column = first_row_offset / strip_size;
4929 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4930#endif
4931
4932 /* if this isn't a single row/column then give to the controller */
4933 if ((first_row != last_row) || (first_column != last_column))
4934 return IO_ACCEL_INELIGIBLE;
4935
4936 /* proceeding with driver mapping */
2b08b3e9
DB		 4937 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4938 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4939 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4940 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4941 map_index = (map_row * total_disks_per_row) + first_column;
4942
4943 switch (dev->raid_level) {
4944 case HPSA_RAID_0:
4945 break; /* nothing special to do */
4946 case HPSA_RAID_1:
4947 /* Handles load balance across RAID 1 members.
4948 * (2-drive R1 and R10 with even # of drives.)
4949 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4950 */
2b08b3e9 4951 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4952 if (dev->offload_to_mirror)
2b08b3e9 4953 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4954 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4955 break;
4956 case HPSA_RAID_ADM:
4957 /* Handles N-way mirrors (R1-ADM)
4958 * and R10 with # of drives divisible by 3.)
4959 */
2b08b3e9 4960 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4961
4962 offload_to_mirror = dev->offload_to_mirror;
4963 raid_map_helper(map, offload_to_mirror,
4964 &map_index, &current_group);
4965 /* set mirror group to use next time */
4966 offload_to_mirror =
2b08b3e9
DB		 4967 (offload_to_mirror >=
4968 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4969 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4970 dev->offload_to_mirror = offload_to_mirror;
4971 /* Avoid direct use of dev->offload_to_mirror within this
4972 * function since multiple threads might simultaneously
4973 * increment it beyond the range of dev->layout_map_count -1.
4974 */
4975 break;
4976 case HPSA_RAID_5:
4977 case HPSA_RAID_6:
2b08b3e9 4978 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4979 break;
4980
4981 /* Verify first and last block are in same RAID group */
4982 r5or6_blocks_per_row =
2b08b3e9
DB		 4983 le16_to_cpu(map->strip_size) *
4984 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4985 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4986 stripesize = r5or6_blocks_per_row *
4987 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4988#if BITS_PER_LONG == 32
4989 tmpdiv = first_block;
4990 first_group = do_div(tmpdiv, stripesize);
4991 tmpdiv = first_group;
4992 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4993 first_group = tmpdiv;
4994 tmpdiv = last_block;
4995 last_group = do_div(tmpdiv, stripesize);
4996 tmpdiv = last_group;
4997 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4998 last_group = tmpdiv;
4999#else
5000 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
5001 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 5002#endif
000ff7c2 5003 if (first_group != last_group)
6b80b18f
ST		 5004 return IO_ACCEL_INELIGIBLE;
5005
5006 /* Verify request is in a single row of RAID 5/6 */
5007#if BITS_PER_LONG == 32
5008 tmpdiv = first_block;
5009 (void) do_div(tmpdiv, stripesize);
5010 first_row = r5or6_first_row = r0_first_row = tmpdiv;
5011 tmpdiv = last_block;
5012 (void) do_div(tmpdiv, stripesize);
5013 r5or6_last_row = r0_last_row = tmpdiv;
5014#else
5015 first_row = r5or6_first_row = r0_first_row =
5016 first_block / stripesize;
5017 r5or6_last_row = r0_last_row = last_block / stripesize;
5018#endif
5019 if (r5or6_first_row != r5or6_last_row)
5020 return IO_ACCEL_INELIGIBLE;
5021
5022
5023 /* Verify request is in a single column */
5024#if BITS_PER_LONG == 32
5025 tmpdiv = first_block;
5026 first_row_offset = do_div(tmpdiv, stripesize);
5027 tmpdiv = first_row_offset;
5028 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
5029 r5or6_first_row_offset = first_row_offset;
5030 tmpdiv = last_block;
5031 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
5032 tmpdiv = r5or6_last_row_offset;
5033 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
5034 tmpdiv = r5or6_first_row_offset;
5035 (void) do_div(tmpdiv, map->strip_size);
5036 first_column = r5or6_first_column = tmpdiv;
5037 tmpdiv = r5or6_last_row_offset;
5038 (void) do_div(tmpdiv, map->strip_size);
5039 r5or6_last_column = tmpdiv;
5040#else
5041 first_row_offset = r5or6_first_row_offset =
5042 (u32)((first_block % stripesize) %
5043 r5or6_blocks_per_row);
5044
5045 r5or6_last_row_offset =
5046 (u32)((last_block % stripesize) %
5047 r5or6_blocks_per_row);
5048
5049 first_column = r5or6_first_column =
2b08b3e9 5050 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 5051 r5or6_last_column =
2b08b3e9 5052 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 5053#endif
5054 if (r5or6_first_column != r5or6_last_column)
5055 return IO_ACCEL_INELIGIBLE;
5056
5057 /* Request is eligible */
5058 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 5059 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 5060
5061 map_index = (first_group *
2b08b3e9 5062 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 5063 (map_row * total_disks_per_row) + first_column;
5064 break;
5065 default:
5066 return IO_ACCEL_INELIGIBLE;
283b4a9b 5067 }
6b80b18f 5068
07543e0c
SC		 5069 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
5070 return IO_ACCEL_INELIGIBLE;
5071
03383736 5072 c->phys_disk = dev->phys_disk[map_index];
c3390df4
DB		 5073 if (!c->phys_disk)
5074 return IO_ACCEL_INELIGIBLE;
03383736 5075
283b4a9b 5076 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 5077 disk_block = le64_to_cpu(map->disk_starting_blk) +
5078 first_row * le16_to_cpu(map->strip_size) +
5079 (first_row_offset - first_column *
5080 le16_to_cpu(map->strip_size));
283b4a9b
SC		 5081 disk_block_cnt = block_cnt;
5082
5083 /* handle differing logical/physical block sizes */
5084 if (map->phys_blk_shift) {
5085 disk_block <<= map->phys_blk_shift;
5086 disk_block_cnt <<= map->phys_blk_shift;
5087 }
5088 BUG_ON(disk_block_cnt > 0xffff);
5089
5090 /* build the new CDB for the physical disk I/O */
5091 if (disk_block > 0xffffffff) {
5092 cdb[0] = is_write ? WRITE_16 : READ_16;
5093 cdb[1] = 0;
5094 cdb[2] = (u8) (disk_block >> 56);
5095 cdb[3] = (u8) (disk_block >> 48);
5096 cdb[4] = (u8) (disk_block >> 40);
5097 cdb[5] = (u8) (disk_block >> 32);
5098 cdb[6] = (u8) (disk_block >> 24);
5099 cdb[7] = (u8) (disk_block >> 16);
5100 cdb[8] = (u8) (disk_block >> 8);
5101 cdb[9] = (u8) (disk_block);
5102 cdb[10] = (u8) (disk_block_cnt >> 24);
5103 cdb[11] = (u8) (disk_block_cnt >> 16);
5104 cdb[12] = (u8) (disk_block_cnt >> 8);
5105 cdb[13] = (u8) (disk_block_cnt);
5106 cdb[14] = 0;
5107 cdb[15] = 0;
5108 cdb_len = 16;
5109 } else {
5110 cdb[0] = is_write ? WRITE_10 : READ_10;
5111 cdb[1] = 0;
5112 cdb[2] = (u8) (disk_block >> 24);
5113 cdb[3] = (u8) (disk_block >> 16);
5114 cdb[4] = (u8) (disk_block >> 8);
5115 cdb[5] = (u8) (disk_block);
5116 cdb[6] = 0;
5117 cdb[7] = (u8) (disk_block_cnt >> 8);
5118 cdb[8] = (u8) (disk_block_cnt);
5119 cdb[9] = 0;
5120 cdb_len = 10;
5121 }
5122 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 5123 dev->scsi3addr,
5124 dev->phys_disk[map_index]);
283b4a9b
SC		 5125}
5126
25163bd5
WS		 5127/*
5128 * Submit commands down the "normal" RAID stack path
5129 * All callers to hpsa_ciss_submit must check lockup_detected
5130 * beforehand, before (opt.) and after calling cmd_alloc
5131 */
574f05d3
SC		 5132static int hpsa_ciss_submit(struct ctlr_info *h,
5133 struct CommandList *c, struct scsi_cmnd *cmd,
5134 unsigned char scsi3addr[])
edd16368 5135{
edd16368 5136 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 5137 c->cmd_type = CMD_SCSI;
5138 c->scsi_cmd = cmd;
5139 c->Header.ReplyQueue = 0; /* unused in simple mode */
5140 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 5141 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 5142
5143 /* Fill in the request block... */
5144
5145 c->Request.Timeout = 0;
edd16368
SC		 5146 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
5147 c->Request.CDBLen = cmd->cmd_len;
5148 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 5149 switch (cmd->sc_data_direction) {
5150 case DMA_TO_DEVICE:
a505b86f
SC		 5151 c->Request.type_attr_dir =
5152 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5153 break;
5154 case DMA_FROM_DEVICE:
a505b86f
SC		 5155 c->Request.type_attr_dir =
5156 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5157 break;
5158 case DMA_NONE:
a505b86f
SC		 5159 c->Request.type_attr_dir =
5160 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5161 break;
5162 case DMA_BIDIRECTIONAL:
5163 /* This can happen if a buggy application does a scsi passthru
5164 * and sets both inlen and outlen to non-zero. ( see
5165 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
5166 */
5167
a505b86f
SC		 5168 c->Request.type_attr_dir =
5169 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 5170 /* This is technically wrong, and hpsa controllers should
5171 * reject it with CMD_INVALID, which is the most correct
5172 * response, but non-fibre backends appear to let it
5173 * slide by, and give the same results as if this field
5174 * were set correctly. Either way is acceptable for
5175 * our purposes here.
5176 */
5177
5178 break;
5179
5180 default:
5181 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
5182 cmd->sc_data_direction);
5183 BUG();
5184 break;
5185 }
5186
33a2ffce 5187 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
73153fe5 5188 hpsa_cmd_resolve_and_free(h, c);
edd16368
SC		 5189 return SCSI_MLQUEUE_HOST_BUSY;
5190 }
5191 enqueue_cmd_and_start_io(h, c);
5192 /* the cmd'll come back via intr handler in complete_scsi_command() */
5193 return 0;
5194}
5195
360c73bd
SC		 5196static void hpsa_cmd_init(struct ctlr_info *h, int index,
5197 struct CommandList *c)
5198{
5199 dma_addr_t cmd_dma_handle, err_dma_handle;
5200
5201 /* Zero out all of commandlist except the last field, refcount */
5202 memset(c, 0, offsetof(struct CommandList, refcount));
5203 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
5204 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
5205 c->err_info = h->errinfo_pool + index;
5206 memset(c->err_info, 0, sizeof(*c->err_info));
5207 err_dma_handle = h->errinfo_pool_dhandle
5208 + index * sizeof(*c->err_info);
5209 c->cmdindex = index;
5210 c->busaddr = (u32) cmd_dma_handle;
5211 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
5212 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
5213 c->h = h;
a58e7e53 5214 c->scsi_cmd = SCSI_CMD_IDLE;
360c73bd
SC		 5215}
5216
5217static void hpsa_preinitialize_commands(struct ctlr_info *h)
5218{
5219 int i;
5220
5221 for (i = 0; i < h->nr_cmds; i++) {
5222 struct CommandList *c = h->cmd_pool + i;
5223
5224 hpsa_cmd_init(h, i, c);
5225 atomic_set(&c->refcount, 0);
5226 }
5227}
5228
5229static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
5230 struct CommandList *c)
5231{
5232 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
5233
73153fe5
WS		 5234 BUG_ON(c->cmdindex != index);
5235
360c73bd
SC		 5236 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
5237 memset(c->err_info, 0, sizeof(*c->err_info));
5238 c->busaddr = (u32) cmd_dma_handle;
5239}
5240
592a0ad5
WS		 5241static int hpsa_ioaccel_submit(struct ctlr_info *h,
5242 struct CommandList *c, struct scsi_cmnd *cmd,
5243 unsigned char *scsi3addr)
5244{
5245 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
5246 int rc = IO_ACCEL_INELIGIBLE;
5247
5248 cmd->host_scribble = (unsigned char *) c;
5249
5250 if (dev->offload_enabled) {
5251 hpsa_cmd_init(h, c->cmdindex, c);
5252 c->cmd_type = CMD_SCSI;
5253 c->scsi_cmd = cmd;
5254 rc = hpsa_scsi_ioaccel_raid_map(h, c);
5255 if (rc < 0) /* scsi_dma_map failed. */
5256 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 5257 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 5258 hpsa_cmd_init(h, c->cmdindex, c);
5259 c->cmd_type = CMD_SCSI;
5260 c->scsi_cmd = cmd;
5261 rc = hpsa_scsi_ioaccel_direct_map(h, c);
5262 if (rc < 0) /* scsi_dma_map failed. */
5263 rc = SCSI_MLQUEUE_HOST_BUSY;
5264 }
5265 return rc;
5266}
5267
080ef1cc
DB		 5268static void hpsa_command_resubmit_worker(struct work_struct *work)
5269{
5270 struct scsi_cmnd *cmd;
5271 struct hpsa_scsi_dev_t *dev;
8a0ff92c 5272 struct CommandList *c = container_of(work, struct CommandList, work);
080ef1cc
DB		 5273
5274 cmd = c->scsi_cmd;
5275 dev = cmd->device->hostdata;
5276 if (!dev) {
5277 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 5278 return hpsa_cmd_free_and_done(c->h, c, cmd);
080ef1cc 5279 }
d604f533
WS		 5280 if (c->reset_pending)
5281 return hpsa_cmd_resolve_and_free(c->h, c);
a58e7e53
WS		 5282 if (c->abort_pending)
5283 return hpsa_cmd_abort_and_free(c->h, c, cmd);
592a0ad5
WS		 5284 if (c->cmd_type == CMD_IOACCEL2) {
5285 struct ctlr_info *h = c->h;
5286 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5287 int rc;
5288
5289 if (c2->error_data.serv_response ==
5290 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
5291 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
5292 if (rc == 0)
5293 return;
5294 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
5295 /*
5296 * If we get here, it means dma mapping failed.
5297 * Try again via scsi mid layer, which will
5298 * then get SCSI_MLQUEUE_HOST_BUSY.
5299 */
5300 cmd->result = DID_IMM_RETRY << 16;
8a0ff92c 5301 return hpsa_cmd_free_and_done(h, c, cmd);
592a0ad5
WS		 5302 }
5303 /* else, fall thru and resubmit down CISS path */
5304 }
5305 }
360c73bd 5306 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 5307 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
5308 /*
5309 * If we get here, it means dma mapping failed. Try
5310 * again via scsi mid layer, which will then get
5311 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 5312 *
5313 * hpsa_ciss_submit will have already freed c
5314 * if it encountered a dma mapping failure.
080ef1cc
DB		 5315 */
5316 cmd->result = DID_IMM_RETRY << 16;
5317 cmd->scsi_done(cmd);
5318 }
5319}
5320
574f05d3
SC		 5321/* Running in struct Scsi_Host->host_lock less mode */
5322static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
5323{
5324 struct ctlr_info *h;
5325 struct hpsa_scsi_dev_t *dev;
5326 unsigned char scsi3addr[8];
5327 struct CommandList *c;
5328 int rc = 0;
5329
5330 /* Get the ptr to our adapter structure out of cmd->host. */
5331 h = sdev_to_hba(cmd->device);
73153fe5
WS		 5332
5333 BUG_ON(cmd->request->tag < 0);
5334
574f05d3
SC		 5335 dev = cmd->device->hostdata;
5336 if (!dev) {
ba74fdc4
DB		 5337 cmd->result = NOT_READY << 16; /* host byte */
5338 cmd->scsi_done(cmd);
5339 return 0;
5340 }
5341
5342 if (dev->removed) {
574f05d3
SC		 5343 cmd->result = DID_NO_CONNECT << 16;
5344 cmd->scsi_done(cmd);
5345 return 0;
5346 }
574f05d3 5347
73153fe5 5348 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
bf43caf3 5349
407863cb 5350 if (unlikely(lockup_detected(h))) {
25163bd5 5351 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 5352 cmd->scsi_done(cmd);
5353 return 0;
5354 }
73153fe5 5355 c = cmd_tagged_alloc(h, cmd);
574f05d3 5356
407863cb
SC		 5357 /*
5358 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 5359 * Retries always go down the normal I/O path.
5360 */
5361 if (likely(cmd->retries == 0 &&
5362 cmd->request->cmd_type == REQ_TYPE_FS &&
5363 h->acciopath_status)) {
592a0ad5
WS		 5364 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
5365 if (rc == 0)
5366 return 0;
5367 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
73153fe5 5368 hpsa_cmd_resolve_and_free(h, c);
592a0ad5 5369 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 5370 }
5371 }
5372 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
5373}
5374
8ebc9248 5375static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 5376{
5377 unsigned long flags;
5378
8ebc9248
WS		 5379 spin_lock_irqsave(&h->scan_lock, flags);
5380 h->scan_finished = 1;
5381 wake_up_all(&h->scan_wait_queue);
5382 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 5383}
5384
a08a8471
SC		 5385static void hpsa_scan_start(struct Scsi_Host *sh)
5386{
5387 struct ctlr_info *h = shost_to_hba(sh);
5388 unsigned long flags;
5389
8ebc9248
WS		 5390 /*
5391 * Don't let rescans be initiated on a controller known to be locked
5392 * up. If the controller locks up *during* a rescan, that thread is
5393 * probably hosed, but at least we can prevent new rescan threads from
5394 * piling up on a locked up controller.
5395 */
5396 if (unlikely(lockup_detected(h)))
5397 return hpsa_scan_complete(h);
5f389360 5398
a08a8471
SC		 5399 /* wait until any scan already in progress is finished. */
5400 while (1) {
5401 spin_lock_irqsave(&h->scan_lock, flags);
5402 if (h->scan_finished)
5403 break;
5404 spin_unlock_irqrestore(&h->scan_lock, flags);
5405 wait_event(h->scan_wait_queue, h->scan_finished);
5406 /* Note: We don't need to worry about a race between this
5407 * thread and driver unload because the midlayer will
5408 * have incremented the reference count, so unload won't
5409 * happen if we're in here.
5410 */
5411 }
5412 h->scan_finished = 0; /* mark scan as in progress */
5413 spin_unlock_irqrestore(&h->scan_lock, flags);
5414
8ebc9248
WS		 5415 if (unlikely(lockup_detected(h)))
5416 return hpsa_scan_complete(h);
5f389360 5417
8aa60681 5418 hpsa_update_scsi_devices(h);
a08a8471 5419
8ebc9248 5420 hpsa_scan_complete(h);
a08a8471
SC		 5421}
5422
7c0a0229
DB		 5423static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
5424{
03383736
DB		 5425 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
5426
5427 if (!logical_drive)
5428 return -ENODEV;
7c0a0229
DB		 5429
5430 if (qdepth < 1)
5431 qdepth = 1;
03383736
DB		 5432 else if (qdepth > logical_drive->queue_depth)
5433 qdepth = logical_drive->queue_depth;
5434
5435 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 5436}
5437
a08a8471
SC		 5438static int hpsa_scan_finished(struct Scsi_Host *sh,
5439 unsigned long elapsed_time)
5440{
5441 struct ctlr_info *h = shost_to_hba(sh);
5442 unsigned long flags;
5443 int finished;
5444
5445 spin_lock_irqsave(&h->scan_lock, flags);
5446 finished = h->scan_finished;
5447 spin_unlock_irqrestore(&h->scan_lock, flags);
5448 return finished;
5449}
5450
2946e82b 5451static int hpsa_scsi_host_alloc(struct ctlr_info *h)
edd16368 5452{
b705690d 5453 struct Scsi_Host *sh;
edd16368 5454
b705690d 5455 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2946e82b
RE		 5456 if (sh == NULL) {
5457 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
5458 return -ENOMEM;
5459 }
b705690d
SC		 5460
5461 sh->io_port = 0;
5462 sh->n_io_port = 0;
5463 sh->this_id = -1;
5464 sh->max_channel = 3;
5465 sh->max_cmd_len = MAX_COMMAND_SIZE;
5466 sh->max_lun = HPSA_MAX_LUN;
5467 sh->max_id = HPSA_MAX_LUN;
41ce4c35 5468 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 5469 sh->cmd_per_lun = sh->can_queue;
b705690d 5470 sh->sg_tablesize = h->maxsgentries;
d04e62b9 5471 sh->transportt = hpsa_sas_transport_template;
b705690d
SC		 5472 sh->hostdata[0] = (unsigned long) h;
5473 sh->irq = h->intr[h->intr_mode];
5474 sh->unique_id = sh->irq;
64d513ac 5475
2946e82b 5476 h->scsi_host = sh;
b705690d 5477 return 0;
2946e82b 5478}
b705690d 5479
2946e82b
RE		 5480static int hpsa_scsi_add_host(struct ctlr_info *h)
5481{
5482 int rv;
5483
5484 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
5485 if (rv) {
5486 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
5487 return rv;
5488 }
5489 scsi_scan_host(h->scsi_host);
5490 return 0;
edd16368
SC		 5491}
5492
73153fe5
WS		 5493/*
5494 * The block layer has already gone to the trouble of picking out a unique,
5495 * small-integer tag for this request. We use an offset from that value as
5496 * an index to select our command block. (The offset allows us to reserve the
5497 * low-numbered entries for our own uses.)
5498 */
5499static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
5500{
5501 int idx = scmd->request->tag;
5502
5503 if (idx < 0)
5504 return idx;
5505
5506 /* Offset to leave space for internal cmds. */
5507 return idx += HPSA_NRESERVED_CMDS;
5508}
5509
b69324ff
WS		 5510/*
5511 * Send a TEST_UNIT_READY command to the specified LUN using the specified
5512 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5513 */
5514static int hpsa_send_test_unit_ready(struct ctlr_info *h,
5515 struct CommandList *c, unsigned char lunaddr[],
5516 int reply_queue)
5517{
5518 int rc;
5519
5520 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
5521 (void) fill_cmd(c, TEST_UNIT_READY, h,
5522 NULL, 0, 0, lunaddr, TYPE_CMD);
c448ecfa 5523 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
b69324ff
WS		 5524 if (rc)
5525 return rc;
5526 /* no unmap needed here because no data xfer. */
5527
5528 /* Check if the unit is already ready. */
5529 if (c->err_info->CommandStatus == CMD_SUCCESS)
5530 return 0;
5531
5532 /*
5533 * The first command sent after reset will receive "unit attention" to
5534 * indicate that the LUN has been reset...this is actually what we're
5535 * looking for (but, success is good too).
5536 */
5537 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5538 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5539 (c->err_info->SenseInfo[2] == NO_SENSE ||
5540 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5541 return 0;
5542
5543 return 1;
5544}
5545
5546/*
5547 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5548 * returns zero when the unit is ready, and non-zero when giving up.
5549 */
5550static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5551 struct CommandList *c,
5552 unsigned char lunaddr[], int reply_queue)
edd16368 5553{
8919358e 5554 int rc;
edd16368
SC		 5555 int count = 0;
5556 int waittime = 1; /* seconds */
edd16368
SC		 5557
5558 /* Send test unit ready until device ready, or give up. */
b69324ff 5559 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
edd16368 5560
b69324ff
WS		 5561 /*
5562 * Wait for a bit. do this first, because if we send
edd16368
SC		 5563 * the TUR right away, the reset will just abort it.
5564 */
5565 msleep(1000 * waittime);
b69324ff
WS		 5566
5567 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5568 if (!rc)
5569 break;
edd16368
SC		 5570
5571 /* Increase wait time with each try, up to a point. */
5572 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
b69324ff 5573 waittime *= 2;
edd16368 5574
b69324ff
WS		 5575 dev_warn(&h->pdev->dev,
5576 "waiting %d secs for device to become ready.\n",
5577 waittime);
5578 }
edd16368 5579
b69324ff
WS		 5580 return rc;
5581}
edd16368 5582
b69324ff
WS		 5583static int wait_for_device_to_become_ready(struct ctlr_info *h,
5584 unsigned char lunaddr[],
5585 int reply_queue)
5586{
5587 int first_queue;
5588 int last_queue;
5589 int rq;
5590 int rc = 0;
5591 struct CommandList *c;
5592
5593 c = cmd_alloc(h);
5594
5595 /*
5596 * If no specific reply queue was requested, then send the TUR
5597 * repeatedly, requesting a reply on each reply queue; otherwise execute
5598 * the loop exactly once using only the specified queue.
5599 */
5600 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5601 first_queue = 0;
5602 last_queue = h->nreply_queues - 1;
5603 } else {
5604 first_queue = reply_queue;
5605 last_queue = reply_queue;
5606 }
5607
5608 for (rq = first_queue; rq <= last_queue; rq++) {
5609 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5610 if (rc)
edd16368 5611 break;
edd16368
SC		 5612 }
5613
5614 if (rc)
5615 dev_warn(&h->pdev->dev, "giving up on device.\n");
5616 else
5617 dev_warn(&h->pdev->dev, "device is ready.\n");
5618
45fcb86e 5619 cmd_free(h, c);
edd16368
SC		 5620 return rc;
5621}
5622
5623/* Need at least one of these error handlers to keep ../scsi/hosts.c from
5624 * complaining. Doing a host- or bus-reset can't do anything good here.
5625 */
5626static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5627{
5628 int rc;
5629 struct ctlr_info *h;
5630 struct hpsa_scsi_dev_t *dev;
0b9b7b6e 5631 u8 reset_type;
2dc127bb 5632 char msg[48];
edd16368
SC		 5633
5634 /* find the controller to which the command to be aborted was sent */
5635 h = sdev_to_hba(scsicmd->device);
5636 if (h == NULL) /* paranoia */
5637 return FAILED;
e345893b
DB		 5638
5639 if (lockup_detected(h))
5640 return FAILED;
5641
edd16368
SC		 5642 dev = scsicmd->device->hostdata;
5643 if (!dev) {
d604f533 5644 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
edd16368
SC		 5645 return FAILED;
5646 }
25163bd5
WS		 5647
5648 /* if controller locked up, we can guarantee command won't complete */
5649 if (lockup_detected(h)) {
2dc127bb
DC		 5650 snprintf(msg, sizeof(msg),
5651 "cmd %d RESET FAILED, lockup detected",
5652 hpsa_get_cmd_index(scsicmd));
73153fe5 5653 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5654 return FAILED;
5655 }
5656
5657 /* this reset request might be the result of a lockup; check */
5658 if (detect_controller_lockup(h)) {
2dc127bb
DC		 5659 snprintf(msg, sizeof(msg),
5660 "cmd %d RESET FAILED, new lockup detected",
5661 hpsa_get_cmd_index(scsicmd));
73153fe5 5662 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5663 return FAILED;
5664 }
5665
d604f533
WS		 5666 /* Do not attempt on controller */
5667 if (is_hba_lunid(dev->scsi3addr))
5668 return SUCCESS;
5669
0b9b7b6e
ST		 5670 if (is_logical_dev_addr_mode(dev->scsi3addr))
5671 reset_type = HPSA_DEVICE_RESET_MSG;
5672 else
5673 reset_type = HPSA_PHYS_TARGET_RESET;
5674
5675 sprintf(msg, "resetting %s",
5676 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ");
5677 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5 5678
da03ded0 5679 h->reset_in_progress = 1;
25163bd5 5680
edd16368 5681 /* send a reset to the SCSI LUN which the command was sent to */
0b9b7b6e 5682 rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type,
d604f533 5683 DEFAULT_REPLY_QUEUE);
0b9b7b6e
ST		 5684 sprintf(msg, "reset %s %s",
5685 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ",
5686 rc == 0 ? "completed successfully" : "failed");
d604f533 5687 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
da03ded0 5688 h->reset_in_progress = 0;
d604f533 5689 return rc == 0 ? SUCCESS : FAILED;
edd16368
SC		 5690}
5691
6cba3f19
SC		 5692static void swizzle_abort_tag(u8 *tag)
5693{
5694 u8 original_tag[8];
5695
5696 memcpy(original_tag, tag, 8);
5697 tag[0] = original_tag[3];
5698 tag[1] = original_tag[2];
5699 tag[2] = original_tag[1];
5700 tag[3] = original_tag[0];
5701 tag[4] = original_tag[7];
5702 tag[5] = original_tag[6];
5703 tag[6] = original_tag[5];
5704 tag[7] = original_tag[4];
5705}
5706
17eb87d2 5707static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 5708 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 5709{
2b08b3e9 5710 u64 tag;
17eb87d2
ST		 5711 if (c->cmd_type == CMD_IOACCEL1) {
5712 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5713 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 5714 tag = le64_to_cpu(cm1->tag);
5715 *tagupper = cpu_to_le32(tag >> 32);
5716 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 5717 return;
5718 }
5719 if (c->cmd_type == CMD_IOACCEL2) {
5720 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5721 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 5722 /* upper tag not used in ioaccel2 mode */
5723 memset(tagupper, 0, sizeof(*tagupper));
5724 *taglower = cm2->Tag;
54b6e9e9 5725 return;
17eb87d2 5726 }
2b08b3e9
DB		 5727 tag = le64_to_cpu(c->Header.tag);
5728 *tagupper = cpu_to_le32(tag >> 32);
5729 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 5730}
5731
75167d2c 5732static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 5733 struct CommandList *abort, int reply_queue)
75167d2c
SC		 5734{
5735 int rc = IO_OK;
5736 struct CommandList *c;
5737 struct ErrorInfo *ei;
2b08b3e9 5738 __le32 tagupper, taglower;
75167d2c 5739
45fcb86e 5740 c = cmd_alloc(h);
75167d2c 5741
a2dac136 5742 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 5743 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 5744 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 5745 if (h->needs_abort_tags_swizzled)
6cba3f19 5746 swizzle_abort_tag(&c->Request.CDB[4]);
c448ecfa 5747 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
17eb87d2 5748 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5749 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 5750 __func__, tagupper, taglower);
75167d2c
SC		 5751 /* no unmap needed here because no data xfer. */
5752
5753 ei = c->err_info;
5754 switch (ei->CommandStatus) {
5755 case CMD_SUCCESS:
5756 break;
9437ac43
SC		 5757 case CMD_TMF_STATUS:
5758 rc = hpsa_evaluate_tmf_status(h, c);
5759 break;
75167d2c
SC		 5760 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5761 rc = -1;
5762 break;
5763 default:
5764 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 5765 __func__, tagupper, taglower);
d1e8beac 5766 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 5767 rc = -1;
5768 break;
5769 }
45fcb86e 5770 cmd_free(h, c);
dd0e19f3
ST		 5771 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5772 __func__, tagupper, taglower);
75167d2c
SC		 5773 return rc;
5774}
5775
8be986cc
SC		 5776static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5777 struct CommandList *command_to_abort, int reply_queue)
5778{
5779 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5780 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5781 struct io_accel2_cmd *c2a =
5782 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
a58e7e53 5783 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
8be986cc
SC		 5784 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5785
5786 /*
5787 * We're overlaying struct hpsa_tmf_struct on top of something which
5788 * was allocated as a struct io_accel2_cmd, so we better be sure it
5789 * actually fits, and doesn't overrun the error info space.
5790 */
5791 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5792 sizeof(struct io_accel2_cmd));
5793 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5794 offsetof(struct hpsa_tmf_struct, error_len) +
5795 sizeof(ac->error_len));
5796
5797 c->cmd_type = IOACCEL2_TMF;
a58e7e53
WS		 5798 c->scsi_cmd = SCSI_CMD_BUSY;
5799
8be986cc
SC		 5800 /* Adjust the DMA address to point to the accelerated command buffer */
5801 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5802 (c->cmdindex * sizeof(struct io_accel2_cmd));
5803 BUG_ON(c->busaddr & 0x0000007F);
5804
5805 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5806 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5807 ac->reply_queue = reply_queue;
5808 ac->tmf = IOACCEL2_TMF_ABORT;
5809 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5810 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5811 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5812 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5813 ac->error_ptr = cpu_to_le64(c->busaddr +
5814 offsetof(struct io_accel2_cmd, error_data));
5815 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5816}
5817
54b6e9e9
ST		 5818/* ioaccel2 path firmware cannot handle abort task requests.
5819 * Change abort requests to physical target reset, and send to the
5820 * address of the physical disk used for the ioaccel 2 command.
5821 * Return 0 on success (IO_OK)
5822 * -1 on failure
5823 */
5824
5825static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 5826 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 5827{
5828 int rc = IO_OK;
5829 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5830 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5831 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5832 unsigned char *psa = &phys_scsi3addr[0];
5833
5834 /* Get a pointer to the hpsa logical device. */
7fa3030c 5835 scmd = abort->scsi_cmd;
54b6e9e9
ST		 5836 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5837 if (dev == NULL) {
5838 dev_warn(&h->pdev->dev,
5839 "Cannot abort: no device pointer for command.\n");
5840 return -1; /* not abortable */
5841 }
5842
2ba8bfc8
SC		 5843 if (h->raid_offload_debug > 0)
5844 dev_info(&h->pdev->dev,
0d96ef5f 5845 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 5846 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 5847 "Reset as abort",
2ba8bfc8
SC		 5848 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5849 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5850
54b6e9e9
ST		 5851 if (!dev->offload_enabled) {
5852 dev_warn(&h->pdev->dev,
5853 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5854 return -1; /* not abortable */
5855 }
5856
5857 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5858 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5859 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5860 return -1; /* not abortable */
5861 }
5862
5863 /* send the reset */
2ba8bfc8
SC		 5864 if (h->raid_offload_debug > 0)
5865 dev_info(&h->pdev->dev,
5866 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5867 psa[0], psa[1], psa[2], psa[3],
5868 psa[4], psa[5], psa[6], psa[7]);
d604f533 5869 rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 5870 if (rc != 0) {
5871 dev_warn(&h->pdev->dev,
5872 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5873 psa[0], psa[1], psa[2], psa[3],
5874 psa[4], psa[5], psa[6], psa[7]);
5875 return rc; /* failed to reset */
5876 }
5877
5878 /* wait for device to recover */
b69324ff 5879 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
54b6e9e9
ST		 5880 dev_warn(&h->pdev->dev,
5881 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5882 psa[0], psa[1], psa[2], psa[3],
5883 psa[4], psa[5], psa[6], psa[7]);
5884 return -1; /* failed to recover */
5885 }
5886
5887 /* device recovered */
5888 dev_info(&h->pdev->dev,
5889 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5890 psa[0], psa[1], psa[2], psa[3],
5891 psa[4], psa[5], psa[6], psa[7]);
5892
5893 return rc; /* success */
5894}
5895
8be986cc
SC		 5896static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
5897 struct CommandList *abort, int reply_queue)
5898{
5899 int rc = IO_OK;
5900 struct CommandList *c;
5901 __le32 taglower, tagupper;
5902 struct hpsa_scsi_dev_t *dev;
5903 struct io_accel2_cmd *c2;
5904
5905 dev = abort->scsi_cmd->device->hostdata;
5906 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
5907 return -1;
5908
5909 c = cmd_alloc(h);
5910 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
5911 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
c448ecfa 5912 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
8be986cc
SC		 5913 hpsa_get_tag(h, abort, &taglower, &tagupper);
5914 dev_dbg(&h->pdev->dev,
5915 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
5916 __func__, tagupper, taglower);
5917 /* no unmap needed here because no data xfer. */
5918
5919 dev_dbg(&h->pdev->dev,
5920 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
5921 __func__, tagupper, taglower, c2->error_data.serv_response);
5922 switch (c2->error_data.serv_response) {
5923 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
5924 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
5925 rc = 0;
5926 break;
5927 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
5928 case IOACCEL2_SERV_RESPONSE_FAILURE:
5929 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
5930 rc = -1;
5931 break;
5932 default:
5933 dev_warn(&h->pdev->dev,
5934 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
5935 __func__, tagupper, taglower,
5936 c2->error_data.serv_response);
5937 rc = -1;
5938 }
5939 cmd_free(h, c);
5940 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
5941 tagupper, taglower);
5942 return rc;
5943}
5944
6cba3f19 5945static int hpsa_send_abort_both_ways(struct ctlr_info *h,
39f3deb2 5946 struct hpsa_scsi_dev_t *dev, struct CommandList *abort, int reply_queue)
6cba3f19 5947{
8be986cc
SC		 5948 /*
5949 * ioccelerator mode 2 commands should be aborted via the
54b6e9e9 5950 * accelerated path, since RAID path is unaware of these commands,
8be986cc
SC		 5951 * but not all underlying firmware can handle abort TMF.
5952 * Change abort to physical device reset when abort TMF is unsupported.
54b6e9e9 5953 */
8be986cc 5954 if (abort->cmd_type == CMD_IOACCEL2) {
39f3deb2
DB		 5955 if ((HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags) ||
5956 dev->physical_device)
8be986cc
SC		 5957 return hpsa_send_abort_ioaccel2(h, abort,
5958 reply_queue);
5959 else
39f3deb2
DB		 5960 return hpsa_send_reset_as_abort_ioaccel2(h,
5961 dev->scsi3addr,
25163bd5 5962 abort, reply_queue);
8be986cc 5963 }
39f3deb2 5964 return hpsa_send_abort(h, dev->scsi3addr, abort, reply_queue);
25163bd5 5965}
54b6e9e9 5966
25163bd5
WS		 5967/* Find out which reply queue a command was meant to return on */
5968static int hpsa_extract_reply_queue(struct ctlr_info *h,
5969 struct CommandList *c)
5970{
5971 if (c->cmd_type == CMD_IOACCEL2)
5972 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5973 return c->Header.ReplyQueue;
6cba3f19
SC		 5974}
5975
9b5c48c2
SC		 5976/*
5977 * Limit concurrency of abort commands to prevent
5978 * over-subscription of commands
5979 */
5980static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5981{
5982#define ABORT_CMD_WAIT_MSECS 5000
5983 return !wait_event_timeout(h->abort_cmd_wait_queue,
5984 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5985 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5986}
5987
75167d2c
SC		 5988/* Send an abort for the specified command.
5989 * If the device and controller support it,
5990 * send a task abort request.
5991 */
5992static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5993{
5994
a58e7e53 5995 int rc;
75167d2c
SC		 5996 struct ctlr_info *h;
5997 struct hpsa_scsi_dev_t *dev;
5998 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 5999 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
6000 char msg[256]; /* For debug messaging. */
6001 int ml = 0;
2b08b3e9 6002 __le32 tagupper, taglower;
25163bd5
WS		 6003 int refcount, reply_queue;
6004
6005 if (sc == NULL)
6006 return FAILED;
75167d2c 6007
9b5c48c2
SC		 6008 if (sc->device == NULL)
6009 return FAILED;
6010
75167d2c
SC		 6011 /* Find the controller of the command to be aborted */
6012 h = sdev_to_hba(sc->device);
9b5c48c2 6013 if (h == NULL)
75167d2c
SC		 6014 return FAILED;
6015
25163bd5
WS		 6016 /* Find the device of the command to be aborted */
6017 dev = sc->device->hostdata;
6018 if (!dev) {
6019 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
6020 msg);
e345893b 6021 return FAILED;
25163bd5
WS		 6022 }
6023
6024 /* If controller locked up, we can guarantee command won't complete */
6025 if (lockup_detected(h)) {
6026 hpsa_show_dev_msg(KERN_WARNING, h, dev,
6027 "ABORT FAILED, lockup detected");
6028 return FAILED;
6029 }
6030
6031 /* This is a good time to check if controller lockup has occurred */
6032 if (detect_controller_lockup(h)) {
6033 hpsa_show_dev_msg(KERN_WARNING, h, dev,
6034 "ABORT FAILED, new lockup detected");
6035 return FAILED;
6036 }
e345893b 6037
75167d2c
SC		 6038 /* Check that controller supports some kind of task abort */
6039 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
6040 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6041 return FAILED;
6042
6043 memset(msg, 0, sizeof(msg));
4b761557 6044 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
75167d2c 6045 h->scsi_host->host_no, sc->device->channel,
0d96ef5f 6046 sc->device->id, sc->device->lun,
4b761557 6047 "Aborting command", sc);
75167d2c 6048
75167d2c
SC		 6049 /* Get SCSI command to be aborted */
6050 abort = (struct CommandList *) sc->host_scribble;
6051 if (abort == NULL) {
281a7fd0
WS		 6052 /* This can happen if the command already completed. */
6053 return SUCCESS;
6054 }
6055 refcount = atomic_inc_return(&abort->refcount);
6056 if (refcount == 1) { /* Command is done already. */
6057 cmd_free(h, abort);
6058 return SUCCESS;
75167d2c 6059 }
9b5c48c2
SC		 6060
6061 /* Don't bother trying the abort if we know it won't work. */
6062 if (abort->cmd_type != CMD_IOACCEL2 &&
6063 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
6064 cmd_free(h, abort);
6065 return FAILED;
6066 }
6067
a58e7e53
WS		 6068 /*
6069 * Check that we're aborting the right command.
6070 * It's possible the CommandList already completed and got re-used.
6071 */
6072 if (abort->scsi_cmd != sc) {
6073 cmd_free(h, abort);
6074 return SUCCESS;
6075 }
6076
6077 abort->abort_pending = true;
17eb87d2 6078 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 6079 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 6080 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 6081 as = abort->scsi_cmd;
75167d2c 6082 if (as != NULL)
4b761557
RE		 6083 ml += sprintf(msg+ml,
6084 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
6085 as->cmd_len, as->cmnd[0], as->cmnd[1],
6086 as->serial_number);
6087 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
0d96ef5f 6088 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
4b761557 6089
75167d2c
SC		 6090 /*
6091 * Command is in flight, or possibly already completed
6092 * by the firmware (but not to the scsi mid layer) but we can't
6093 * distinguish which. Send the abort down.
6094 */
9b5c48c2
SC		 6095 if (wait_for_available_abort_cmd(h)) {
6096 dev_warn(&h->pdev->dev,
4b761557
RE		 6097 "%s FAILED, timeout waiting for an abort command to become available.\n",
6098 msg);
9b5c48c2
SC		 6099 cmd_free(h, abort);
6100 return FAILED;
6101 }
39f3deb2 6102 rc = hpsa_send_abort_both_ways(h, dev, abort, reply_queue);
9b5c48c2
SC		 6103 atomic_inc(&h->abort_cmds_available);
6104 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 6105 if (rc != 0) {
4b761557 6106 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
0d96ef5f 6107 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4b761557 6108 "FAILED to abort command");
281a7fd0 6109 cmd_free(h, abort);
75167d2c
SC		 6110 return FAILED;
6111 }
4b761557 6112 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
d604f533 6113 wait_event(h->event_sync_wait_queue,
a58e7e53 6114 abort->scsi_cmd != sc || lockup_detected(h));
281a7fd0 6115 cmd_free(h, abort);
a58e7e53 6116 return !lockup_detected(h) ? SUCCESS : FAILED;
75167d2c
SC		 6117}
6118
73153fe5
WS		 6119/*
6120 * For operations with an associated SCSI command, a command block is allocated
6121 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
6122 * block request tag as an index into a table of entries. cmd_tagged_free() is
6123 * the complement, although cmd_free() may be called instead.
6124 */
6125static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
6126 struct scsi_cmnd *scmd)
6127{
6128 int idx = hpsa_get_cmd_index(scmd);
6129 struct CommandList *c = h->cmd_pool + idx;
6130
6131 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
6132 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
6133 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
6134 /* The index value comes from the block layer, so if it's out of
6135 * bounds, it's probably not our bug.
6136 */
6137 BUG();
6138 }
6139
6140 atomic_inc(&c->refcount);
6141 if (unlikely(!hpsa_is_cmd_idle(c))) {
6142 /*
6143 * We expect that the SCSI layer will hand us a unique tag
6144 * value. Thus, there should never be a collision here between
6145 * two requests...because if the selected command isn't idle
6146 * then someone is going to be very disappointed.
6147 */
6148 dev_err(&h->pdev->dev,
6149 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
6150 idx);
6151 if (c->scsi_cmd != NULL)
6152 scsi_print_command(c->scsi_cmd);
6153 scsi_print_command(scmd);
6154 }
6155
6156 hpsa_cmd_partial_init(h, idx, c);
6157 return c;
6158}
6159
6160static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
6161{
6162 /*
6163 * Release our reference to the block. We don't need to do anything
6164 * else to free it, because it is accessed by index. (There's no point
6165 * in checking the result of the decrement, since we cannot guarantee
6166 * that there isn't a concurrent abort which is also accessing it.)
6167 */
6168 (void)atomic_dec(&c->refcount);
6169}
6170
edd16368
SC		 6171/*
6172 * For operations that cannot sleep, a command block is allocated at init,
6173 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
6174 * which ones are free or in use. Lock must be held when calling this.
6175 * cmd_free() is the complement.
bf43caf3
RE		 6176 * This function never gives up and returns NULL. If it hangs,
6177 * another thread must call cmd_free() to free some tags.
edd16368 6178 */
281a7fd0 6179
edd16368
SC		 6180static struct CommandList *cmd_alloc(struct ctlr_info *h)
6181{
6182 struct CommandList *c;
360c73bd 6183 int refcount, i;
73153fe5 6184 int offset = 0;
4c413128 6185
33811026
RE		 6186 /*
6187 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 6188 * multiple threads could get in here, and one thread could
6189 * be scanning through the list of bits looking for a free
6190 * one, but the free ones are always behind him, and other
6191 * threads sneak in behind him and eat them before he can
6192 * get to them, so that while there is always a free one, a
6193 * very unlucky thread might be starved anyway, never able to
6194 * beat the other threads. In reality, this happens so
6195 * infrequently as to be indistinguishable from never.
73153fe5
WS		 6196 *
6197 * Note that we start allocating commands before the SCSI host structure
6198 * is initialized. Since the search starts at bit zero, this
6199 * all works, since we have at least one command structure available;
6200 * however, it means that the structures with the low indexes have to be
6201 * reserved for driver-initiated requests, while requests from the block
6202 * layer will use the higher indexes.
4c413128 6203 */
edd16368 6204
281a7fd0 6205 for (;;) {
73153fe5
WS		 6206 i = find_next_zero_bit(h->cmd_pool_bits,
6207 HPSA_NRESERVED_CMDS,
6208 offset);
6209 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
281a7fd0
WS		 6210 offset = 0;
6211 continue;
6212 }
6213 c = h->cmd_pool + i;
6214 refcount = atomic_inc_return(&c->refcount);
6215 if (unlikely(refcount > 1)) {
6216 cmd_free(h, c); /* already in use */
73153fe5 6217 offset = (i + 1) % HPSA_NRESERVED_CMDS;
281a7fd0
WS		 6218 continue;
6219 }
6220 set_bit(i & (BITS_PER_LONG - 1),
6221 h->cmd_pool_bits + (i / BITS_PER_LONG));
6222 break; /* it's ours now. */
6223 }
360c73bd 6224 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 6225 return c;
6226}
6227
73153fe5
WS		 6228/*
6229 * This is the complementary operation to cmd_alloc(). Note, however, in some
6230 * corner cases it may also be used to free blocks allocated by
6231 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
6232 * the clear-bit is harmless.
6233 */
edd16368
SC		 6234static void cmd_free(struct ctlr_info *h, struct CommandList *c)
6235{
281a7fd0
WS		 6236 if (atomic_dec_and_test(&c->refcount)) {
6237 int i;
edd16368 6238
281a7fd0
WS		 6239 i = c - h->cmd_pool;
6240 clear_bit(i & (BITS_PER_LONG - 1),
6241 h->cmd_pool_bits + (i / BITS_PER_LONG));
6242 }
edd16368
SC		 6243}
6244
edd16368
SC		 6245#ifdef CONFIG_COMPAT
6246
42a91641
DB		 6247static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
6248 void __user *arg)
edd16368
SC		 6249{
6250 IOCTL32_Command_struct __user *arg32 =
6251 (IOCTL32_Command_struct __user *) arg;
6252 IOCTL_Command_struct arg64;
6253 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
6254 int err;
6255 u32 cp;
6256
938abd84 6257 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 6258 err = 0;
6259 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
6260 sizeof(arg64.LUN_info));
6261 err |= copy_from_user(&arg64.Request, &arg32->Request,
6262 sizeof(arg64.Request));
6263 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
6264 sizeof(arg64.error_info));
6265 err |= get_user(arg64.buf_size, &arg32->buf_size);
6266 err |= get_user(cp, &arg32->buf);
6267 arg64.buf = compat_ptr(cp);
6268 err |= copy_to_user(p, &arg64, sizeof(arg64));
6269
6270 if (err)
6271 return -EFAULT;
6272
42a91641 6273 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 6274 if (err)
6275 return err;
6276 err |= copy_in_user(&arg32->error_info, &p->error_info,
6277 sizeof(arg32->error_info));
6278 if (err)
6279 return -EFAULT;
6280 return err;
6281}
6282
6283static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 6284 int cmd, void __user *arg)
edd16368
SC		 6285{
6286 BIG_IOCTL32_Command_struct __user *arg32 =
6287 (BIG_IOCTL32_Command_struct __user *) arg;
6288 BIG_IOCTL_Command_struct arg64;
6289 BIG_IOCTL_Command_struct __user *p =
6290 compat_alloc_user_space(sizeof(arg64));
6291 int err;
6292 u32 cp;
6293
938abd84 6294 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 6295 err = 0;
6296 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
6297 sizeof(arg64.LUN_info));
6298 err |= copy_from_user(&arg64.Request, &arg32->Request,
6299 sizeof(arg64.Request));
6300 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
6301 sizeof(arg64.error_info));
6302 err |= get_user(arg64.buf_size, &arg32->buf_size);
6303 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
6304 err |= get_user(cp, &arg32->buf);
6305 arg64.buf = compat_ptr(cp);
6306 err |= copy_to_user(p, &arg64, sizeof(arg64));
6307
6308 if (err)
6309 return -EFAULT;
6310
42a91641 6311 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 6312 if (err)
6313 return err;
6314 err |= copy_in_user(&arg32->error_info, &p->error_info,
6315 sizeof(arg32->error_info));
6316 if (err)
6317 return -EFAULT;
6318 return err;
6319}
71fe75a7 6320
42a91641 6321static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 6322{
6323 switch (cmd) {
6324 case CCISS_GETPCIINFO:
6325 case CCISS_GETINTINFO:
6326 case CCISS_SETINTINFO:
6327 case CCISS_GETNODENAME:
6328 case CCISS_SETNODENAME:
6329 case CCISS_GETHEARTBEAT:
6330 case CCISS_GETBUSTYPES:
6331 case CCISS_GETFIRMVER:
6332 case CCISS_GETDRIVVER:
6333 case CCISS_REVALIDVOLS:
6334 case CCISS_DEREGDISK:
6335 case CCISS_REGNEWDISK:
6336 case CCISS_REGNEWD:
6337 case CCISS_RESCANDISK:
6338 case CCISS_GETLUNINFO:
6339 return hpsa_ioctl(dev, cmd, arg);
6340
6341 case CCISS_PASSTHRU32:
6342 return hpsa_ioctl32_passthru(dev, cmd, arg);
6343 case CCISS_BIG_PASSTHRU32:
6344 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
6345
6346 default:
6347 return -ENOIOCTLCMD;
6348 }
6349}
edd16368
SC		 6350#endif
6351
6352static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
6353{
6354 struct hpsa_pci_info pciinfo;
6355
6356 if (!argp)
6357 return -EINVAL;
6358 pciinfo.domain = pci_domain_nr(h->pdev->bus);
6359 pciinfo.bus = h->pdev->bus->number;
6360 pciinfo.dev_fn = h->pdev->devfn;
6361 pciinfo.board_id = h->board_id;
6362 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
6363 return -EFAULT;
6364 return 0;
6365}
6366
6367static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
6368{
6369 DriverVer_type DriverVer;
6370 unsigned char vmaj, vmin, vsubmin;
6371 int rc;
6372
6373 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
6374 &vmaj, &vmin, &vsubmin);
6375 if (rc != 3) {
6376 dev_info(&h->pdev->dev, "driver version string '%s' "
6377 "unrecognized.", HPSA_DRIVER_VERSION);
6378 vmaj = 0;
6379 vmin = 0;
6380 vsubmin = 0;
6381 }
6382 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
6383 if (!argp)
6384 return -EINVAL;
6385 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
6386 return -EFAULT;
6387 return 0;
6388}
6389
6390static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6391{
6392 IOCTL_Command_struct iocommand;
6393 struct CommandList *c;
6394 char *buff = NULL;
50a0decf 6395 u64 temp64;
c1f63c8f 6396 int rc = 0;
edd16368
SC		 6397
6398 if (!argp)
6399 return -EINVAL;
6400 if (!capable(CAP_SYS_RAWIO))
6401 return -EPERM;
6402 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
6403 return -EFAULT;
6404 if ((iocommand.buf_size < 1) &&
6405 (iocommand.Request.Type.Direction != XFER_NONE)) {
6406 return -EINVAL;
6407 }
6408 if (iocommand.buf_size > 0) {
6409 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
6410 if (buff == NULL)
2dd02d74 6411 return -ENOMEM;
9233fb10 6412 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 6413 /* Copy the data into the buffer we created */
6414 if (copy_from_user(buff, iocommand.buf,
6415 iocommand.buf_size)) {
c1f63c8f
SC		 6416 rc = -EFAULT;
6417 goto out_kfree;
b03a7771
SC		 6418 }
6419 } else {
6420 memset(buff, 0, iocommand.buf_size);
edd16368 6421 }
b03a7771 6422 }
45fcb86e 6423 c = cmd_alloc(h);
bf43caf3 6424
edd16368
SC		 6425 /* Fill in the command type */
6426 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6427 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6428 /* Fill in Command Header */
6429 c->Header.ReplyQueue = 0; /* unused in simple mode */
6430 if (iocommand.buf_size > 0) { /* buffer to fill */
6431 c->Header.SGList = 1;
50a0decf 6432 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6433 } else { /* no buffers to fill */
6434 c->Header.SGList = 0;
50a0decf 6435 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 6436 }
6437 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6438
6439 /* Fill in Request block */
6440 memcpy(&c->Request, &iocommand.Request,
6441 sizeof(c->Request));
6442
6443 /* Fill in the scatter gather information */
6444 if (iocommand.buf_size > 0) {
50a0decf 6445 temp64 = pci_map_single(h->pdev, buff,
edd16368 6446 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6447 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
6448 c->SG[0].Addr = cpu_to_le64(0);
6449 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 6450 rc = -ENOMEM;
6451 goto out;
6452 }
50a0decf
SC		 6453 c->SG[0].Addr = cpu_to_le64(temp64);
6454 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
6455 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 6456 }
c448ecfa
DB		 6457 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
6458 DEFAULT_TIMEOUT);
c2dd32e0
SC		 6459 if (iocommand.buf_size > 0)
6460 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 6461 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6462 if (rc) {
6463 rc = -EIO;
6464 goto out;
6465 }
edd16368
SC		 6466
6467 /* Copy the error information out */
6468 memcpy(&iocommand.error_info, c->err_info,
6469 sizeof(iocommand.error_info));
6470 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 6471 rc = -EFAULT;
6472 goto out;
edd16368 6473 }
9233fb10 6474 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 6475 iocommand.buf_size > 0) {
edd16368
SC		 6476 /* Copy the data out of the buffer we created */
6477 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 6478 rc = -EFAULT;
6479 goto out;
edd16368
SC		 6480 }
6481 }
c1f63c8f 6482out:
45fcb86e 6483 cmd_free(h, c);
c1f63c8f
SC		 6484out_kfree:
6485 kfree(buff);
6486 return rc;
edd16368
SC		 6487}
6488
6489static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6490{
6491 BIG_IOCTL_Command_struct *ioc;
6492 struct CommandList *c;
6493 unsigned char **buff = NULL;
6494 int *buff_size = NULL;
50a0decf 6495 u64 temp64;
edd16368
SC		 6496 BYTE sg_used = 0;
6497 int status = 0;
01a02ffc
SC		 6498 u32 left;
6499 u32 sz;
edd16368
SC		 6500 BYTE __user *data_ptr;
6501
6502 if (!argp)
6503 return -EINVAL;
6504 if (!capable(CAP_SYS_RAWIO))
6505 return -EPERM;
6506 ioc = (BIG_IOCTL_Command_struct *)
6507 kmalloc(sizeof(*ioc), GFP_KERNEL);
6508 if (!ioc) {
6509 status = -ENOMEM;
6510 goto cleanup1;
6511 }
6512 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
6513 status = -EFAULT;
6514 goto cleanup1;
6515 }
6516 if ((ioc->buf_size < 1) &&
6517 (ioc->Request.Type.Direction != XFER_NONE)) {
6518 status = -EINVAL;
6519 goto cleanup1;
6520 }
6521 /* Check kmalloc limits using all SGs */
6522 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
6523 status = -EINVAL;
6524 goto cleanup1;
6525 }
d66ae08b 6526 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 6527 status = -EINVAL;
6528 goto cleanup1;
6529 }
d66ae08b 6530 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 6531 if (!buff) {
6532 status = -ENOMEM;
6533 goto cleanup1;
6534 }
d66ae08b 6535 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 6536 if (!buff_size) {
6537 status = -ENOMEM;
6538 goto cleanup1;
6539 }
6540 left = ioc->buf_size;
6541 data_ptr = ioc->buf;
6542 while (left) {
6543 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6544 buff_size[sg_used] = sz;
6545 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6546 if (buff[sg_used] == NULL) {
6547 status = -ENOMEM;
6548 goto cleanup1;
6549 }
9233fb10 6550 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 6551 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 6552 status = -EFAULT;
edd16368
SC		 6553 goto cleanup1;
6554 }
6555 } else
6556 memset(buff[sg_used], 0, sz);
6557 left -= sz;
6558 data_ptr += sz;
6559 sg_used++;
6560 }
45fcb86e 6561 c = cmd_alloc(h);
bf43caf3 6562
edd16368 6563 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6564 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368 6565 c->Header.ReplyQueue = 0;
50a0decf
SC		 6566 c->Header.SGList = (u8) sg_used;
6567 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 6568 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6569 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6570 if (ioc->buf_size > 0) {
6571 int i;
6572 for (i = 0; i < sg_used; i++) {
50a0decf 6573 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 6574 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6575 if (dma_mapping_error(&h->pdev->dev,
6576 (dma_addr_t) temp64)) {
6577 c->SG[i].Addr = cpu_to_le64(0);
6578 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 6579 hpsa_pci_unmap(h->pdev, c, i,
6580 PCI_DMA_BIDIRECTIONAL);
6581 status = -ENOMEM;
e2d4a1f6 6582 goto cleanup0;
bcc48ffa 6583 }
50a0decf
SC		 6584 c->SG[i].Addr = cpu_to_le64(temp64);
6585 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6586 c->SG[i].Ext = cpu_to_le32(0);
edd16368 6587 }
50a0decf 6588 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 6589 }
c448ecfa
DB		 6590 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
6591 DEFAULT_TIMEOUT);
b03a7771
SC		 6592 if (sg_used)
6593 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 6594 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6595 if (status) {
6596 status = -EIO;
6597 goto cleanup0;
6598 }
6599
edd16368
SC		 6600 /* Copy the error information out */
6601 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6602 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 6603 status = -EFAULT;
e2d4a1f6 6604 goto cleanup0;
edd16368 6605 }
9233fb10 6606 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 6607 int i;
6608
edd16368
SC		 6609 /* Copy the data out of the buffer we created */
6610 BYTE __user *ptr = ioc->buf;
6611 for (i = 0; i < sg_used; i++) {
6612 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 6613 status = -EFAULT;
e2d4a1f6 6614 goto cleanup0;
edd16368
SC		 6615 }
6616 ptr += buff_size[i];
6617 }
6618 }
edd16368 6619 status = 0;
e2d4a1f6 6620cleanup0:
45fcb86e 6621 cmd_free(h, c);
edd16368
SC		 6622cleanup1:
6623 if (buff) {
2b08b3e9
DB		 6624 int i;
6625
edd16368
SC		 6626 for (i = 0; i < sg_used; i++)
6627 kfree(buff[i]);
6628 kfree(buff);
6629 }
6630 kfree(buff_size);
6631 kfree(ioc);
6632 return status;
6633}
6634
6635static void check_ioctl_unit_attention(struct ctlr_info *h,
6636 struct CommandList *c)
6637{
6638 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6639 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6640 (void) check_for_unit_attention(h, c);
6641}
0390f0c0 6642
edd16368
SC		 6643/*
6644 * ioctl
6645 */
42a91641 6646static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 6647{
6648 struct ctlr_info *h;
6649 void __user *argp = (void __user *)arg;
0390f0c0 6650 int rc;
edd16368
SC		 6651
6652 h = sdev_to_hba(dev);
6653
6654 switch (cmd) {
6655 case CCISS_DEREGDISK:
6656 case CCISS_REGNEWDISK:
6657 case CCISS_REGNEWD:
a08a8471 6658 hpsa_scan_start(h->scsi_host);
edd16368
SC		 6659 return 0;
6660 case CCISS_GETPCIINFO:
6661 return hpsa_getpciinfo_ioctl(h, argp);
6662 case CCISS_GETDRIVVER:
6663 return hpsa_getdrivver_ioctl(h, argp);
6664 case CCISS_PASSTHRU:
34f0c627 6665 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6666 return -EAGAIN;
6667 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 6668 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6669 return rc;
edd16368 6670 case CCISS_BIG_PASSTHRU:
34f0c627 6671 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6672 return -EAGAIN;
6673 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 6674 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6675 return rc;
edd16368
SC		 6676 default:
6677 return -ENOTTY;
6678 }
6679}
6680
bf43caf3 6681static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6f039790 6682 u8 reset_type)
64670ac8
SC		 6683{
6684 struct CommandList *c;
6685
6686 c = cmd_alloc(h);
bf43caf3 6687
a2dac136
SC		 6688 /* fill_cmd can't fail here, no data buffer to map */
6689 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 6690 RAID_CTLR_LUNID, TYPE_MSG);
6691 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6692 c->waiting = NULL;
6693 enqueue_cmd_and_start_io(h, c);
6694 /* Don't wait for completion, the reset won't complete. Don't free
6695 * the command either. This is the last command we will send before
6696 * re-initializing everything, so it doesn't matter and won't leak.
6697 */
bf43caf3 6698 return;
64670ac8
SC		 6699}
6700
a2dac136 6701static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 6702 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 6703 int cmd_type)
6704{
6705 int pci_dir = XFER_NONE;
9b5c48c2 6706 u64 tag; /* for commands to be aborted */
edd16368
SC		 6707
6708 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6709 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6710 c->Header.ReplyQueue = 0;
6711 if (buff != NULL && size > 0) {
6712 c->Header.SGList = 1;
50a0decf 6713 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6714 } else {
6715 c->Header.SGList = 0;
50a0decf 6716 c->Header.SGTotal = cpu_to_le16(0);
edd16368 6717 }
edd16368
SC		 6718 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6719
edd16368
SC		 6720 if (cmd_type == TYPE_CMD) {
6721 switch (cmd) {
6722 case HPSA_INQUIRY:
6723 /* are we trying to read a vital product page */
b7bb24eb 6724 if (page_code & VPD_PAGE) {
edd16368 6725 c->Request.CDB[1] = 0x01;
b7bb24eb 6726 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 6727 }
6728 c->Request.CDBLen = 6;
a505b86f
SC		 6729 c->Request.type_attr_dir =
6730 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6731 c->Request.Timeout = 0;
6732 c->Request.CDB[0] = HPSA_INQUIRY;
6733 c->Request.CDB[4] = size & 0xFF;
6734 break;
6735 case HPSA_REPORT_LOG:
6736 case HPSA_REPORT_PHYS:
6737 /* Talking to controller so It's a physical command
6738 mode = 00 target = 0. Nothing to write.
6739 */
6740 c->Request.CDBLen = 12;
a505b86f
SC		 6741 c->Request.type_attr_dir =
6742 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6743 c->Request.Timeout = 0;
6744 c->Request.CDB[0] = cmd;
6745 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6746 c->Request.CDB[7] = (size >> 16) & 0xFF;
6747 c->Request.CDB[8] = (size >> 8) & 0xFF;
6748 c->Request.CDB[9] = size & 0xFF;
6749 break;
c2adae44
ST		 6750 case BMIC_SENSE_DIAG_OPTIONS:
6751 c->Request.CDBLen = 16;
6752 c->Request.type_attr_dir =
6753 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6754 c->Request.Timeout = 0;
6755 /* Spec says this should be BMIC_WRITE */
6756 c->Request.CDB[0] = BMIC_READ;
6757 c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS;
6758 break;
6759 case BMIC_SET_DIAG_OPTIONS:
6760 c->Request.CDBLen = 16;
6761 c->Request.type_attr_dir =
6762 TYPE_ATTR_DIR(cmd_type,
6763 ATTR_SIMPLE, XFER_WRITE);
6764 c->Request.Timeout = 0;
6765 c->Request.CDB[0] = BMIC_WRITE;
6766 c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS;
6767 break;
edd16368
SC		 6768 case HPSA_CACHE_FLUSH:
6769 c->Request.CDBLen = 12;
a505b86f
SC		 6770 c->Request.type_attr_dir =
6771 TYPE_ATTR_DIR(cmd_type,
6772 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 6773 c->Request.Timeout = 0;
6774 c->Request.CDB[0] = BMIC_WRITE;
6775 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 6776 c->Request.CDB[7] = (size >> 8) & 0xFF;
6777 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 6778 break;
6779 case TEST_UNIT_READY:
6780 c->Request.CDBLen = 6;
a505b86f
SC		 6781 c->Request.type_attr_dir =
6782 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 6783 c->Request.Timeout = 0;
6784 break;
283b4a9b
SC		 6785 case HPSA_GET_RAID_MAP:
6786 c->Request.CDBLen = 12;
a505b86f
SC		 6787 c->Request.type_attr_dir =
6788 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 6789 c->Request.Timeout = 0;
6790 c->Request.CDB[0] = HPSA_CISS_READ;
6791 c->Request.CDB[1] = cmd;
6792 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6793 c->Request.CDB[7] = (size >> 16) & 0xFF;
6794 c->Request.CDB[8] = (size >> 8) & 0xFF;
6795 c->Request.CDB[9] = size & 0xFF;
6796 break;
316b221a
SC		 6797 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6798 c->Request.CDBLen = 10;
a505b86f
SC		 6799 c->Request.type_attr_dir =
6800 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 6801 c->Request.Timeout = 0;
6802 c->Request.CDB[0] = BMIC_READ;
6803 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6804 c->Request.CDB[7] = (size >> 16) & 0xFF;
6805 c->Request.CDB[8] = (size >> 8) & 0xFF;
6806 break;
03383736
DB		 6807 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6808 c->Request.CDBLen = 10;
6809 c->Request.type_attr_dir =
6810 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6811 c->Request.Timeout = 0;
6812 c->Request.CDB[0] = BMIC_READ;
6813 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6814 c->Request.CDB[7] = (size >> 16) & 0xFF;
6815 c->Request.CDB[8] = (size >> 8) & 0XFF;
6816 break;
d04e62b9
KB		 6817 case BMIC_SENSE_SUBSYSTEM_INFORMATION:
6818 c->Request.CDBLen = 10;
6819 c->Request.type_attr_dir =
6820 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6821 c->Request.Timeout = 0;
6822 c->Request.CDB[0] = BMIC_READ;
6823 c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION;
6824 c->Request.CDB[7] = (size >> 16) & 0xFF;
6825 c->Request.CDB[8] = (size >> 8) & 0XFF;
6826 break;
cca8f13b
DB		 6827 case BMIC_SENSE_STORAGE_BOX_PARAMS:
6828 c->Request.CDBLen = 10;
6829 c->Request.type_attr_dir =
6830 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6831 c->Request.Timeout = 0;
6832 c->Request.CDB[0] = BMIC_READ;
6833 c->Request.CDB[6] = BMIC_SENSE_STORAGE_BOX_PARAMS;
6834 c->Request.CDB[7] = (size >> 16) & 0xFF;
6835 c->Request.CDB[8] = (size >> 8) & 0XFF;
6836 break;
66749d0d
ST		 6837 case BMIC_IDENTIFY_CONTROLLER:
6838 c->Request.CDBLen = 10;
6839 c->Request.type_attr_dir =
6840 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6841 c->Request.Timeout = 0;
6842 c->Request.CDB[0] = BMIC_READ;
6843 c->Request.CDB[1] = 0;
6844 c->Request.CDB[2] = 0;
6845 c->Request.CDB[3] = 0;
6846 c->Request.CDB[4] = 0;
6847 c->Request.CDB[5] = 0;
6848 c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER;
6849 c->Request.CDB[7] = (size >> 16) & 0xFF;
6850 c->Request.CDB[8] = (size >> 8) & 0XFF;
6851 c->Request.CDB[9] = 0;
6852 break;
edd16368
SC		 6853 default:
6854 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6855 BUG();
a2dac136 6856 return -1;
edd16368
SC		 6857 }
6858 } else if (cmd_type == TYPE_MSG) {
6859 switch (cmd) {
6860
0b9b7b6e
ST		 6861 case HPSA_PHYS_TARGET_RESET:
6862 c->Request.CDBLen = 16;
6863 c->Request.type_attr_dir =
6864 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
6865 c->Request.Timeout = 0; /* Don't time out */
6866 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6867 c->Request.CDB[0] = HPSA_RESET;
6868 c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE;
6869 /* Physical target reset needs no control bytes 4-7*/
6870 c->Request.CDB[4] = 0x00;
6871 c->Request.CDB[5] = 0x00;
6872 c->Request.CDB[6] = 0x00;
6873 c->Request.CDB[7] = 0x00;
6874 break;
edd16368
SC		 6875 case HPSA_DEVICE_RESET_MSG:
6876 c->Request.CDBLen = 16;
a505b86f
SC		 6877 c->Request.type_attr_dir =
6878 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 6879 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 6880 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6881 c->Request.CDB[0] = cmd;
21e89afd 6882 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 6883 /* If bytes 4-7 are zero, it means reset the */
6884 /* LunID device */
6885 c->Request.CDB[4] = 0x00;
6886 c->Request.CDB[5] = 0x00;
6887 c->Request.CDB[6] = 0x00;
6888 c->Request.CDB[7] = 0x00;
75167d2c
SC		 6889 break;
6890 case HPSA_ABORT_MSG:
9b5c48c2 6891 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 6892 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 6893 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
6894 tag, c->Header.tag);
75167d2c 6895 c->Request.CDBLen = 16;
a505b86f
SC		 6896 c->Request.type_attr_dir =
6897 TYPE_ATTR_DIR(cmd_type,
6898 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 6899 c->Request.Timeout = 0; /* Don't time out */
6900 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
6901 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
6902 c->Request.CDB[2] = 0x00; /* reserved */
6903 c->Request.CDB[3] = 0x00; /* reserved */
6904 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 6905 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 6906 c->Request.CDB[12] = 0x00; /* reserved */
6907 c->Request.CDB[13] = 0x00; /* reserved */
6908 c->Request.CDB[14] = 0x00; /* reserved */
6909 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 6910 break;
edd16368
SC		 6911 default:
6912 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6913 cmd);
6914 BUG();
6915 }
6916 } else {
6917 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6918 BUG();
6919 }
6920
a505b86f 6921 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 6922 case XFER_READ:
6923 pci_dir = PCI_DMA_FROMDEVICE;
6924 break;
6925 case XFER_WRITE:
6926 pci_dir = PCI_DMA_TODEVICE;
6927 break;
6928 case XFER_NONE:
6929 pci_dir = PCI_DMA_NONE;
6930 break;
6931 default:
6932 pci_dir = PCI_DMA_BIDIRECTIONAL;
6933 }
a2dac136
SC		 6934 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
6935 return -1;
6936 return 0;
edd16368
SC		 6937}
6938
6939/*
6940 * Map (physical) PCI mem into (virtual) kernel space
6941 */
6942static void __iomem *remap_pci_mem(ulong base, ulong size)
6943{
6944 ulong page_base = ((ulong) base) & PAGE_MASK;
6945 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 6946 void __iomem *page_remapped = ioremap_nocache(page_base,
6947 page_offs + size);
edd16368
SC		 6948
6949 return page_remapped ? (page_remapped + page_offs) : NULL;
6950}
6951
254f796b 6952static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 6953{
254f796b 6954 return h->access.command_completed(h, q);
edd16368
SC		 6955}
6956
900c5440 6957static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 6958{
6959 return h->access.intr_pending(h);
6960}
6961
6962static inline long interrupt_not_for_us(struct ctlr_info *h)
6963{
10f66018
SC		 6964 return (h->access.intr_pending(h) == 0) ||
6965 (h->interrupts_enabled == 0);
edd16368
SC		 6966}
6967
01a02ffc
SC		 6968static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6969 u32 raw_tag)
edd16368
SC		 6970{
6971 if (unlikely(tag_index >= h->nr_cmds)) {
6972 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6973 return 1;
6974 }
6975 return 0;
6976}
6977
5a3d16f5 6978static inline void finish_cmd(struct CommandList *c)
edd16368 6979{
e85c5974 6980 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 6981 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6982 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 6983 complete_scsi_command(c);
8be986cc 6984 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
edd16368 6985 complete(c->waiting);
a104c99f
SC		 6986}
6987
303932fd 6988/* process completion of an indexed ("direct lookup") command */
1d94f94d 6989static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 6990 u32 raw_tag)
6991{
6992 u32 tag_index;
6993 struct CommandList *c;
6994
f2405db8 6995 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 6996 if (!bad_tag(h, tag_index, raw_tag)) {
6997 c = h->cmd_pool + tag_index;
6998 finish_cmd(c);
6999 }
303932fd
DB		 7000}
7001
64670ac8
SC		 7002/* Some controllers, like p400, will give us one interrupt
7003 * after a soft reset, even if we turned interrupts off.
7004 * Only need to check for this in the hpsa_xxx_discard_completions
7005 * functions.
7006 */
7007static int ignore_bogus_interrupt(struct ctlr_info *h)
7008{
7009 if (likely(!reset_devices))
7010 return 0;
7011
7012 if (likely(h->interrupts_enabled))
7013 return 0;
7014
7015 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
7016 "(known firmware bug.) Ignoring.\n");
7017
7018 return 1;
7019}
7020
254f796b
MG		 7021/*
7022 * Convert &h->q[x] (passed to interrupt handlers) back to h.
7023 * Relies on (h-q[x] == x) being true for x such that
7024 * 0 <= x < MAX_REPLY_QUEUES.
7025 */
7026static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 7027{
254f796b
MG		 7028 return container_of((queue - *queue), struct ctlr_info, q[0]);
7029}
7030
7031static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
7032{
7033 struct ctlr_info *h = queue_to_hba(queue);
7034 u8 q = *(u8 *) queue;
64670ac8
SC		 7035 u32 raw_tag;
7036
7037 if (ignore_bogus_interrupt(h))
7038 return IRQ_NONE;
7039
7040 if (interrupt_not_for_us(h))
7041 return IRQ_NONE;
a0c12413 7042 h->last_intr_timestamp = get_jiffies_64();
64670ac8 7043 while (interrupt_pending(h)) {
254f796b 7044 raw_tag = get_next_completion(h, q);
64670ac8 7045 while (raw_tag != FIFO_EMPTY)
254f796b 7046 raw_tag = next_command(h, q);
64670ac8 7047 }
64670ac8
SC		 7048 return IRQ_HANDLED;
7049}
7050
254f796b 7051static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 7052{
254f796b 7053 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 7054 u32 raw_tag;
254f796b 7055 u8 q = *(u8 *) queue;
64670ac8
SC		 7056
7057 if (ignore_bogus_interrupt(h))
7058 return IRQ_NONE;
7059
a0c12413 7060 h->last_intr_timestamp = get_jiffies_64();
254f796b 7061 raw_tag = get_next_completion(h, q);
64670ac8 7062 while (raw_tag != FIFO_EMPTY)
254f796b 7063 raw_tag = next_command(h, q);
64670ac8
SC		 7064 return IRQ_HANDLED;
7065}
7066
254f796b 7067static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 7068{
254f796b 7069 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 7070 u32 raw_tag;
254f796b 7071 u8 q = *(u8 *) queue;
edd16368
SC		 7072
7073 if (interrupt_not_for_us(h))
7074 return IRQ_NONE;
a0c12413 7075 h->last_intr_timestamp = get_jiffies_64();
10f66018 7076 while (interrupt_pending(h)) {
254f796b 7077 raw_tag = get_next_completion(h, q);
10f66018 7078 while (raw_tag != FIFO_EMPTY) {
f2405db8 7079 process_indexed_cmd(h, raw_tag);
254f796b 7080 raw_tag = next_command(h, q);
10f66018
SC		 7081 }
7082 }
10f66018
SC		 7083 return IRQ_HANDLED;
7084}
7085
254f796b 7086static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 7087{
254f796b 7088 struct ctlr_info *h = queue_to_hba(queue);
10f66018 7089 u32 raw_tag;
254f796b 7090 u8 q = *(u8 *) queue;
10f66018 7091
a0c12413 7092 h->last_intr_timestamp = get_jiffies_64();
254f796b 7093 raw_tag = get_next_completion(h, q);
303932fd 7094 while (raw_tag != FIFO_EMPTY) {
f2405db8 7095 process_indexed_cmd(h, raw_tag);
254f796b 7096 raw_tag = next_command(h, q);
edd16368 7097 }
edd16368
SC		 7098 return IRQ_HANDLED;
7099}
7100
a9a3a273
SC		 7101/* Send a message CDB to the firmware. Careful, this only works
7102 * in simple mode, not performant mode due to the tag lookup.
7103 * We only ever use this immediately after a controller reset.
7104 */
6f039790
GKH		 7105static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
7106 unsigned char type)
edd16368
SC		 7107{
7108 struct Command {
7109 struct CommandListHeader CommandHeader;
7110 struct RequestBlock Request;
7111 struct ErrDescriptor ErrorDescriptor;
7112 };
7113 struct Command *cmd;
7114 static const size_t cmd_sz = sizeof(*cmd) +
7115 sizeof(cmd->ErrorDescriptor);
7116 dma_addr_t paddr64;
2b08b3e9
DB		 7117 __le32 paddr32;
7118 u32 tag;
edd16368
SC		 7119 void __iomem *vaddr;
7120 int i, err;
7121
7122 vaddr = pci_ioremap_bar(pdev, 0);
7123 if (vaddr == NULL)
7124 return -ENOMEM;
7125
7126 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
7127 * CCISS commands, so they must be allocated from the lower 4GiB of
7128 * memory.
7129 */
7130 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
7131 if (err) {
7132 iounmap(vaddr);
1eaec8f3 7133 return err;
edd16368
SC		 7134 }
7135
7136 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
7137 if (cmd == NULL) {
7138 iounmap(vaddr);
7139 return -ENOMEM;
7140 }
7141
7142 /* This must fit, because of the 32-bit consistent DMA mask. Also,
7143 * although there's no guarantee, we assume that the address is at
7144 * least 4-byte aligned (most likely, it's page-aligned).
7145 */
2b08b3e9 7146 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 7147
7148 cmd->CommandHeader.ReplyQueue = 0;
7149 cmd->CommandHeader.SGList = 0;
50a0decf 7150 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 7151 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 7152 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
7153
7154 cmd->Request.CDBLen = 16;
a505b86f
SC		 7155 cmd->Request.type_attr_dir =
7156 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 7157 cmd->Request.Timeout = 0; /* Don't time out */
7158 cmd->Request.CDB[0] = opcode;
7159 cmd->Request.CDB[1] = type;
7160 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 7161 cmd->ErrorDescriptor.Addr =
2b08b3e9 7162 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 7163 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 7164
2b08b3e9 7165 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 7166
7167 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
7168 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 7169 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 7170 break;
7171 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
7172 }
7173
7174 iounmap(vaddr);
7175
7176 /* we leak the DMA buffer here ... no choice since the controller could
7177 * still complete the command.
7178 */
7179 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
7180 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
7181 opcode, type);
7182 return -ETIMEDOUT;
7183 }
7184
7185 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
7186
7187 if (tag & HPSA_ERROR_BIT) {
7188 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
7189 opcode, type);
7190 return -EIO;
7191 }
7192
7193 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
7194 opcode, type);
7195 return 0;
7196}
7197
edd16368
SC		 7198#define hpsa_noop(p) hpsa_message(p, 3, 0)
7199
1df8552a 7200static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 7201 void __iomem *vaddr, u32 use_doorbell)
1df8552a 7202{
1df8552a
SC		 7203
7204 if (use_doorbell) {
7205 /* For everything after the P600, the PCI power state method
7206 * of resetting the controller doesn't work, so we have this
7207 * other way using the doorbell register.
7208 */
7209 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 7210 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 7211
00701a96 7212 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 7213 * doorbell reset and before any attempt to talk to the board
7214 * at all to ensure that this actually works and doesn't fall
7215 * over in some weird corner cases.
7216 */
00701a96 7217 msleep(10000);
1df8552a
SC		 7218 } else { /* Try to do it the PCI power state way */
7219
7220 /* Quoting from the Open CISS Specification: "The Power
7221 * Management Control/Status Register (CSR) controls the power
7222 * state of the device. The normal operating state is D0,
7223 * CSR=00h. The software off state is D3, CSR=03h. To reset
7224 * the controller, place the interface device in D3 then to D0,
7225 * this causes a secondary PCI reset which will reset the
7226 * controller." */
2662cab8
DB		 7227
7228 int rc = 0;
7229
1df8552a 7230 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 7231
1df8552a 7232 /* enter the D3hot power management state */
2662cab8
DB		 7233 rc = pci_set_power_state(pdev, PCI_D3hot);
7234 if (rc)
7235 return rc;
1df8552a
SC		 7236
7237 msleep(500);
7238
7239 /* enter the D0 power management state */
2662cab8
DB		 7240 rc = pci_set_power_state(pdev, PCI_D0);
7241 if (rc)
7242 return rc;
c4853efe
MM		 7243
7244 /*
7245 * The P600 requires a small delay when changing states.
7246 * Otherwise we may think the board did not reset and we bail.
7247 * This for kdump only and is particular to the P600.
7248 */
7249 msleep(500);
1df8552a
SC		 7250 }
7251 return 0;
7252}
7253
6f039790 7254static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 7255{
7256 memset(driver_version, 0, len);
f79cfec6 7257 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 7258}
7259
6f039790 7260static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 7261{
7262 char *driver_version;
7263 int i, size = sizeof(cfgtable->driver_version);
7264
7265 driver_version = kmalloc(size, GFP_KERNEL);
7266 if (!driver_version)
7267 return -ENOMEM;
7268
7269 init_driver_version(driver_version, size);
7270 for (i = 0; i < size; i++)
7271 writeb(driver_version[i], &cfgtable->driver_version[i]);
7272 kfree(driver_version);
7273 return 0;
7274}
7275
6f039790
GKH		 7276static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
7277 unsigned char *driver_ver)
580ada3c
SC		 7278{
7279 int i;
7280
7281 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
7282 driver_ver[i] = readb(&cfgtable->driver_version[i]);
7283}
7284
6f039790 7285static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 7286{
7287
7288 char *driver_ver, *old_driver_ver;
7289 int rc, size = sizeof(cfgtable->driver_version);
7290
7291 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
7292 if (!old_driver_ver)
7293 return -ENOMEM;
7294 driver_ver = old_driver_ver + size;
7295
7296 /* After a reset, the 32 bytes of "driver version" in the cfgtable
7297 * should have been changed, otherwise we know the reset failed.
7298 */
7299 init_driver_version(old_driver_ver, size);
7300 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
7301 rc = !memcmp(driver_ver, old_driver_ver, size);
7302 kfree(old_driver_ver);
7303 return rc;
7304}
edd16368 7305/* This does a hard reset of the controller using PCI power management
1df8552a 7306 * states or the using the doorbell register.
edd16368 7307 */
6b6c1cd7 7308static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 7309{
1df8552a
SC		 7310 u64 cfg_offset;
7311 u32 cfg_base_addr;
7312 u64 cfg_base_addr_index;
7313 void __iomem *vaddr;
7314 unsigned long paddr;
580ada3c 7315 u32 misc_fw_support;
270d05de 7316 int rc;
1df8552a 7317 struct CfgTable __iomem *cfgtable;
cf0b08d0 7318 u32 use_doorbell;
270d05de 7319 u16 command_register;
edd16368 7320
1df8552a
SC		 7321 /* For controllers as old as the P600, this is very nearly
7322 * the same thing as
edd16368
SC		 7323 *
7324 * pci_save_state(pci_dev);
7325 * pci_set_power_state(pci_dev, PCI_D3hot);
7326 * pci_set_power_state(pci_dev, PCI_D0);
7327 * pci_restore_state(pci_dev);
7328 *
1df8552a
SC		 7329 * For controllers newer than the P600, the pci power state
7330 * method of resetting doesn't work so we have another way
7331 * using the doorbell register.
edd16368 7332 */
18867659 7333
60f923b9
RE		 7334 if (!ctlr_is_resettable(board_id)) {
7335 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 7336 return -ENODEV;
7337 }
46380786
SC		 7338
7339 /* if controller is soft- but not hard resettable... */
7340 if (!ctlr_is_hard_resettable(board_id))
7341 return -ENOTSUPP; /* try soft reset later. */
18867659 7342
270d05de
SC		 7343 /* Save the PCI command register */
7344 pci_read_config_word(pdev, 4, &command_register);
270d05de 7345 pci_save_state(pdev);
edd16368 7346
1df8552a
SC		 7347 /* find the first memory BAR, so we can find the cfg table */
7348 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
7349 if (rc)
7350 return rc;
7351 vaddr = remap_pci_mem(paddr, 0x250);
7352 if (!vaddr)
7353 return -ENOMEM;
edd16368 7354
1df8552a
SC		 7355 /* find cfgtable in order to check if reset via doorbell is supported */
7356 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
7357 &cfg_base_addr_index, &cfg_offset);
7358 if (rc)
7359 goto unmap_vaddr;
7360 cfgtable = remap_pci_mem(pci_resource_start(pdev,
7361 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
7362 if (!cfgtable) {
7363 rc = -ENOMEM;
7364 goto unmap_vaddr;
7365 }
580ada3c
SC		 7366 rc = write_driver_ver_to_cfgtable(cfgtable);
7367 if (rc)
03741d95 7368 goto unmap_cfgtable;
edd16368 7369
cf0b08d0
SC		 7370 /* If reset via doorbell register is supported, use that.
7371 * There are two such methods. Favor the newest method.
7372 */
1df8552a 7373 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 7374 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
7375 if (use_doorbell) {
7376 use_doorbell = DOORBELL_CTLR_RESET2;
7377 } else {
7378 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
7379 if (use_doorbell) {
050f7147
SC		 7380 dev_warn(&pdev->dev,
7381 "Soft reset not supported. Firmware update is required.\n");
64670ac8 7382 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 7383 goto unmap_cfgtable;
7384 }
7385 }
edd16368 7386
1df8552a
SC		 7387 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
7388 if (rc)
7389 goto unmap_cfgtable;
edd16368 7390
270d05de 7391 pci_restore_state(pdev);
270d05de 7392 pci_write_config_word(pdev, 4, command_register);
edd16368 7393
1df8552a
SC		 7394 /* Some devices (notably the HP Smart Array 5i Controller)
7395 need a little pause here */
7396 msleep(HPSA_POST_RESET_PAUSE_MSECS);
7397
fe5389c8
SC		 7398 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
7399 if (rc) {
7400 dev_warn(&pdev->dev,
050f7147 7401 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 7402 goto unmap_cfgtable;
7403 }
fe5389c8 7404
580ada3c
SC		 7405 rc = controller_reset_failed(vaddr);
7406 if (rc < 0)
7407 goto unmap_cfgtable;
7408 if (rc) {
64670ac8
SC		 7409 dev_warn(&pdev->dev, "Unable to successfully reset "
7410 "controller. Will try soft reset.\n");
7411 rc = -ENOTSUPP;
580ada3c 7412 } else {
64670ac8 7413 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 7414 }
7415
7416unmap_cfgtable:
7417 iounmap(cfgtable);
7418
7419unmap_vaddr:
7420 iounmap(vaddr);
7421 return rc;
edd16368
SC		 7422}
7423
7424/*
7425 * We cannot read the structure directly, for portability we must use
7426 * the io functions.
7427 * This is for debug only.
7428 */
42a91641 7429static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 7430{
58f8665c 7431#ifdef HPSA_DEBUG
edd16368
SC		 7432 int i;
7433 char temp_name[17];
7434
7435 dev_info(dev, "Controller Configuration information\n");
7436 dev_info(dev, "------------------------------------\n");
7437 for (i = 0; i < 4; i++)
7438 temp_name[i] = readb(&(tb->Signature[i]));
7439 temp_name[4] = '\0';
7440 dev_info(dev, " Signature = %s\n", temp_name);
7441 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
7442 dev_info(dev, " Transport methods supported = 0x%x\n",
7443 readl(&(tb->TransportSupport)));
7444 dev_info(dev, " Transport methods active = 0x%x\n",
7445 readl(&(tb->TransportActive)));
7446 dev_info(dev, " Requested transport Method = 0x%x\n",
7447 readl(&(tb->HostWrite.TransportRequest)));
7448 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
7449 readl(&(tb->HostWrite.CoalIntDelay)));
7450 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
7451 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 7452 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 7453 readl(&(tb->CmdsOutMax)));
7454 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
7455 for (i = 0; i < 16; i++)
7456 temp_name[i] = readb(&(tb->ServerName[i]));
7457 temp_name[16] = '\0';
7458 dev_info(dev, " Server Name = %s\n", temp_name);
7459 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
7460 readl(&(tb->HeartBeat)));
edd16368 7461#endif /* HPSA_DEBUG */
58f8665c 7462}
edd16368
SC		 7463
7464static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
7465{
7466 int i, offset, mem_type, bar_type;
7467
7468 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
7469 return 0;
7470 offset = 0;
7471 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
7472 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
7473 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
7474 offset += 4;
7475 else {
7476 mem_type = pci_resource_flags(pdev, i) &
7477 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
7478 switch (mem_type) {
7479 case PCI_BASE_ADDRESS_MEM_TYPE_32:
7480 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
7481 offset += 4; /* 32 bit */
7482 break;
7483 case PCI_BASE_ADDRESS_MEM_TYPE_64:
7484 offset += 8;
7485 break;
7486 default: /* reserved in PCI 2.2 */
7487 dev_warn(&pdev->dev,
7488 "base address is invalid\n");
7489 return -1;
7490 break;
7491 }
7492 }
7493 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
7494 return i + 1;
7495 }
7496 return -1;
7497}
7498
cc64c817
RE		 7499static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
7500{
7501 if (h->msix_vector) {
7502 if (h->pdev->msix_enabled)
7503 pci_disable_msix(h->pdev);
105a3dbc 7504 h->msix_vector = 0;
cc64c817
RE		 7505 } else if (h->msi_vector) {
7506 if (h->pdev->msi_enabled)
7507 pci_disable_msi(h->pdev);
105a3dbc 7508 h->msi_vector = 0;
cc64c817
RE		 7509 }
7510}
7511
edd16368 7512/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 7513 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 7514 */
6f039790 7515static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 7516{
7517#ifdef CONFIG_PCI_MSI
254f796b
MG		 7518 int err, i;
7519 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
7520
7521 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
7522 hpsa_msix_entries[i].vector = 0;
7523 hpsa_msix_entries[i].entry = i;
7524 }
edd16368
SC		 7525
7526 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 7527 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
7528 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 7529 goto default_int_mode;
55c06c71 7530 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 7531 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 7532 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 7533 if (h->msix_vector > num_online_cpus())
7534 h->msix_vector = num_online_cpus();
18fce3c4
AG		 7535 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
7536 1, h->msix_vector);
7537 if (err < 0) {
7538 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
7539 h->msix_vector = 0;
7540 goto single_msi_mode;
7541 } else if (err < h->msix_vector) {
55c06c71 7542 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 7543 "available\n", err);
edd16368 7544 }
18fce3c4
AG		 7545 h->msix_vector = err;
7546 for (i = 0; i < h->msix_vector; i++)
7547 h->intr[i] = hpsa_msix_entries[i].vector;
7548 return;
edd16368 7549 }
18fce3c4 7550single_msi_mode:
55c06c71 7551 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 7552 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 7553 if (!pci_enable_msi(h->pdev))
edd16368
SC		 7554 h->msi_vector = 1;
7555 else
55c06c71 7556 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 7557 }
7558default_int_mode:
7559#endif /* CONFIG_PCI_MSI */
7560 /* if we get here we're going to use the default interrupt mode */
a9a3a273 7561 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 7562}
7563
6f039790 7564static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 7565{
7566 int i;
7567 u32 subsystem_vendor_id, subsystem_device_id;
7568
7569 subsystem_vendor_id = pdev->subsystem_vendor;
7570 subsystem_device_id = pdev->subsystem_device;
7571 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
7572 subsystem_vendor_id;
7573
7574 for (i = 0; i < ARRAY_SIZE(products); i++)
7575 if (*board_id == products[i].board_id)
7576 return i;
7577
6798cc0a
SC		 7578 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
7579 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
7580 !hpsa_allow_any) {
e5c880d1
SC		 7581 dev_warn(&pdev->dev, "unrecognized board ID: "
7582 "0x%08x, ignoring.\n", *board_id);
7583 return -ENODEV;
7584 }
7585 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
7586}
7587
6f039790
GKH		 7588static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
7589 unsigned long *memory_bar)
3a7774ce
SC		 7590{
7591 int i;
7592
7593 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 7594 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 7595 /* addressing mode bits already removed */
12d2cd47
SC		 7596 *memory_bar = pci_resource_start(pdev, i);
7597 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 7598 *memory_bar);
7599 return 0;
7600 }
12d2cd47 7601 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 7602 return -ENODEV;
7603}
7604
6f039790
GKH		 7605static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7606 int wait_for_ready)
2c4c8c8b 7607{
fe5389c8 7608 int i, iterations;
2c4c8c8b 7609 u32 scratchpad;
fe5389c8
SC		 7610 if (wait_for_ready)
7611 iterations = HPSA_BOARD_READY_ITERATIONS;
7612 else
7613 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 7614
fe5389c8
SC		 7615 for (i = 0; i < iterations; i++) {
7616 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7617 if (wait_for_ready) {
7618 if (scratchpad == HPSA_FIRMWARE_READY)
7619 return 0;
7620 } else {
7621 if (scratchpad != HPSA_FIRMWARE_READY)
7622 return 0;
7623 }
2c4c8c8b
SC		 7624 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7625 }
fe5389c8 7626 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 7627 return -ENODEV;
7628}
7629
6f039790
GKH		 7630static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7631 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7632 u64 *cfg_offset)
a51fd47f
SC		 7633{
7634 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7635 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7636 *cfg_base_addr &= (u32) 0x0000ffff;
7637 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7638 if (*cfg_base_addr_index == -1) {
7639 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7640 return -ENODEV;
7641 }
7642 return 0;
7643}
7644
195f2c65
RE		 7645static void hpsa_free_cfgtables(struct ctlr_info *h)
7646{
105a3dbc 7647 if (h->transtable) {
195f2c65 7648 iounmap(h->transtable);
105a3dbc
RE		 7649 h->transtable = NULL;
7650 }
7651 if (h->cfgtable) {
195f2c65 7652 iounmap(h->cfgtable);
105a3dbc
RE		 7653 h->cfgtable = NULL;
7654 }
195f2c65
RE		 7655}
7656
7657/* Find and map CISS config table and transfer table
7658+ * several items must be unmapped (freed) later
7659+ * */
6f039790 7660static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 7661{
01a02ffc
SC		 7662 u64 cfg_offset;
7663 u32 cfg_base_addr;
7664 u64 cfg_base_addr_index;
303932fd 7665 u32 trans_offset;
a51fd47f 7666 int rc;
77c4495c 7667
a51fd47f
SC		 7668 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7669 &cfg_base_addr_index, &cfg_offset);
7670 if (rc)
7671 return rc;
77c4495c 7672 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 7673 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 7674 if (!h->cfgtable) {
7675 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 7676 return -ENOMEM;
cd3c81c4 7677 }
580ada3c
SC		 7678 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7679 if (rc)
7680 return rc;
77c4495c 7681 /* Find performant mode table. */
a51fd47f 7682 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 7683 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7684 cfg_base_addr_index)+cfg_offset+trans_offset,
7685 sizeof(*h->transtable));
195f2c65
RE		 7686 if (!h->transtable) {
7687 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7688 hpsa_free_cfgtables(h);
77c4495c 7689 return -ENOMEM;
195f2c65 7690 }
77c4495c
SC		 7691 return 0;
7692}
7693
6f039790 7694static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 7695{
41ce4c35
SC		 7696#define MIN_MAX_COMMANDS 16
7697 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7698
7699 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 7700
7701 /* Limit commands in memory limited kdump scenario. */
7702 if (reset_devices && h->max_commands > 32)
7703 h->max_commands = 32;
7704
41ce4c35
SC		 7705 if (h->max_commands < MIN_MAX_COMMANDS) {
7706 dev_warn(&h->pdev->dev,
7707 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7708 h->max_commands,
7709 MIN_MAX_COMMANDS);
7710 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 7711 }
7712}
7713
c7ee65b3
WS		 7714/* If the controller reports that the total max sg entries is greater than 512,
7715 * then we know that chained SG blocks work. (Original smart arrays did not
7716 * support chained SG blocks and would return zero for max sg entries.)
7717 */
7718static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7719{
7720 return h->maxsgentries > 512;
7721}
7722
b93d7536
SC		 7723/* Interrogate the hardware for some limits:
7724 * max commands, max SG elements without chaining, and with chaining,
7725 * SG chain block size, etc.
7726 */
6f039790 7727static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 7728{
cba3d38b 7729 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 7730 h->nr_cmds = h->max_commands;
b93d7536 7731 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 7732 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 7733 if (hpsa_supports_chained_sg_blocks(h)) {
7734 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 7735 h->max_cmd_sg_entries = 32;
1a63ea6f 7736 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 7737 h->maxsgentries--; /* save one for chain pointer */
7738 } else {
c7ee65b3
WS		 7739 /*
7740 * Original smart arrays supported at most 31 s/g entries
7741 * embedded inline in the command (trying to use more
7742 * would lock up the controller)
7743 */
7744 h->max_cmd_sg_entries = 31;
1a63ea6f 7745 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 7746 h->chainsize = 0;
b93d7536 7747 }
75167d2c
SC		 7748
7749 /* Find out what task management functions are supported and cache */
7750 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 7751 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7752 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7753 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7754 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
8be986cc
SC		 7755 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7756 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
b93d7536
SC		 7757}
7758
76c46e49
SC		 7759static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7760{
0fc9fd40 7761 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 7762 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 7763 return false;
7764 }
7765 return true;
7766}
7767
97a5e98c 7768static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 7769{
97a5e98c 7770 u32 driver_support;
f7c39101 7771
97a5e98c 7772 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 7773 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7774#ifdef CONFIG_X86
97a5e98c 7775 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 7776#endif
28e13446
SC		 7777 driver_support |= ENABLE_UNIT_ATTN;
7778 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 7779}
7780
3d0eab67
SC		 7781/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7782 * in a prefetch beyond physical memory.
7783 */
7784static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7785{
7786 u32 dma_prefetch;
7787
7788 if (h->board_id != 0x3225103C)
7789 return;
7790 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7791 dma_prefetch |= 0x8000;
7792 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7793}
7794
c706a795 7795static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 7796{
7797 int i;
7798 u32 doorbell_value;
7799 unsigned long flags;
7800 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 7801 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 7802 spin_lock_irqsave(&h->lock, flags);
7803 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7804 spin_unlock_irqrestore(&h->lock, flags);
7805 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 7806 goto done;
76438d08 7807 /* delay and try again */
007e7aa9 7808 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 7809 }
c706a795
RE		 7810 return -ENODEV;
7811done:
7812 return 0;
76438d08
SC		 7813}
7814
c706a795 7815static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 7816{
7817 int i;
6eaf46fd
SC		 7818 u32 doorbell_value;
7819 unsigned long flags;
eb6b2ae9
SC		 7820
7821 /* under certain very rare conditions, this can take awhile.
7822 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7823 * as we enter this code.)
7824 */
007e7aa9 7825 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 7826 if (h->remove_in_progress)
7827 goto done;
6eaf46fd
SC		 7828 spin_lock_irqsave(&h->lock, flags);
7829 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7830 spin_unlock_irqrestore(&h->lock, flags);
382be668 7831 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 7832 goto done;
eb6b2ae9 7833 /* delay and try again */
007e7aa9 7834 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 7835 }
c706a795
RE		 7836 return -ENODEV;
7837done:
7838 return 0;
3f4336f3
SC		 7839}
7840
c706a795 7841/* return -ENODEV or other reason on error, 0 on success */
6f039790 7842static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 7843{
7844 u32 trans_support;
7845
7846 trans_support = readl(&(h->cfgtable->TransportSupport));
7847 if (!(trans_support & SIMPLE_MODE))
7848 return -ENOTSUPP;
7849
7850 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 7851
3f4336f3
SC		 7852 /* Update the field, and then ring the doorbell */
7853 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 7854 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 7855 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7856 if (hpsa_wait_for_mode_change_ack(h))
7857 goto error;
eb6b2ae9 7858 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 7859 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7860 goto error;
960a30e7 7861 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 7862 return 0;
283b4a9b 7863error:
050f7147 7864 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 7865 return -ENODEV;
eb6b2ae9
SC		 7866}
7867
195f2c65
RE		 7868/* free items allocated or mapped by hpsa_pci_init */
7869static void hpsa_free_pci_init(struct ctlr_info *h)
7870{
7871 hpsa_free_cfgtables(h); /* pci_init 4 */
7872 iounmap(h->vaddr); /* pci_init 3 */
105a3dbc 7873 h->vaddr = NULL;
195f2c65 7874 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
943a7021
RE		 7875 /*
7876 * call pci_disable_device before pci_release_regions per
7877 * Documentation/PCI/pci.txt
7878 */
195f2c65 7879 pci_disable_device(h->pdev); /* pci_init 1 */
943a7021 7880 pci_release_regions(h->pdev); /* pci_init 2 */
195f2c65
RE		 7881}
7882
7883/* several items must be freed later */
6f039790 7884static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 7885{
eb6b2ae9 7886 int prod_index, err;
edd16368 7887
e5c880d1
SC		 7888 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
7889 if (prod_index < 0)
60f923b9 7890 return prod_index;
e5c880d1
SC		 7891 h->product_name = products[prod_index].product_name;
7892 h->access = *(products[prod_index].access);
edd16368 7893
9b5c48c2
SC		 7894 h->needs_abort_tags_swizzled =
7895 ctlr_needs_abort_tags_swizzled(h->board_id);
7896
e5a44df8
MG		 7897 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7898 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7899
55c06c71 7900 err = pci_enable_device(h->pdev);
edd16368 7901 if (err) {
195f2c65 7902 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
943a7021 7903 pci_disable_device(h->pdev);
edd16368
SC		 7904 return err;
7905 }
7906
f79cfec6 7907 err = pci_request_regions(h->pdev, HPSA);
edd16368 7908 if (err) {
55c06c71 7909 dev_err(&h->pdev->dev,
195f2c65 7910 "failed to obtain PCI resources\n");
943a7021
RE		 7911 pci_disable_device(h->pdev);
7912 return err;
edd16368 7913 }
4fa604e1
RE		 7914
7915 pci_set_master(h->pdev);
7916
6b3f4c52 7917 hpsa_interrupt_mode(h);
12d2cd47 7918 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 7919 if (err)
195f2c65 7920 goto clean2; /* intmode+region, pci */
edd16368 7921 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 7922 if (!h->vaddr) {
195f2c65 7923 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 7924 err = -ENOMEM;
195f2c65 7925 goto clean2; /* intmode+region, pci */
204892e9 7926 }
fe5389c8 7927 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 7928 if (err)
195f2c65 7929 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 7930 err = hpsa_find_cfgtables(h);
7931 if (err)
195f2c65 7932 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 7933 hpsa_find_board_params(h);
edd16368 7934
76c46e49 7935 if (!hpsa_CISS_signature_present(h)) {
edd16368 7936 err = -ENODEV;
195f2c65 7937 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 7938 }
97a5e98c 7939 hpsa_set_driver_support_bits(h);
3d0eab67 7940 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 7941 err = hpsa_enter_simple_mode(h);
7942 if (err)
195f2c65 7943 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 7944 return 0;
7945
195f2c65
RE		 7946clean4: /* cfgtables, vaddr, intmode+region, pci */
7947 hpsa_free_cfgtables(h);
7948clean3: /* vaddr, intmode+region, pci */
7949 iounmap(h->vaddr);
105a3dbc 7950 h->vaddr = NULL;
195f2c65
RE		 7951clean2: /* intmode+region, pci */
7952 hpsa_disable_interrupt_mode(h);
943a7021
RE		 7953 /*
7954 * call pci_disable_device before pci_release_regions per
7955 * Documentation/PCI/pci.txt
7956 */
195f2c65 7957 pci_disable_device(h->pdev);
943a7021 7958 pci_release_regions(h->pdev);
edd16368
SC		 7959 return err;
7960}
7961
6f039790 7962static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 7963{
7964 int rc;
7965
7966#define HBA_INQUIRY_BYTE_COUNT 64
7967 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7968 if (!h->hba_inquiry_data)
7969 return;
7970 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7971 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7972 if (rc != 0) {
7973 kfree(h->hba_inquiry_data);
7974 h->hba_inquiry_data = NULL;
7975 }
7976}
7977
6b6c1cd7 7978static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 7979{
1df8552a 7980 int rc, i;
3b747298 7981 void __iomem *vaddr;
4c2a8c40
SC		 7982
7983 if (!reset_devices)
7984 return 0;
7985
132aa220
TH		 7986 /* kdump kernel is loading, we don't know in which state is
7987 * the pci interface. The dev->enable_cnt is equal zero
7988 * so we call enable+disable, wait a while and switch it on.
7989 */
7990 rc = pci_enable_device(pdev);
7991 if (rc) {
7992 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7993 return -ENODEV;
7994 }
7995 pci_disable_device(pdev);
7996 msleep(260); /* a randomly chosen number */
7997 rc = pci_enable_device(pdev);
7998 if (rc) {
7999 dev_warn(&pdev->dev, "failed to enable device.\n");
8000 return -ENODEV;
8001 }
4fa604e1 8002
859c75ab 8003 pci_set_master(pdev);
4fa604e1 8004
3b747298
TH		 8005 vaddr = pci_ioremap_bar(pdev, 0);
8006 if (vaddr == NULL) {
8007 rc = -ENOMEM;
8008 goto out_disable;
8009 }
8010 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8011 iounmap(vaddr);
8012
1df8552a 8013 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 8014 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 8015
1df8552a
SC		 8016 /* -ENOTSUPP here means we cannot reset the controller
8017 * but it's already (and still) up and running in
18867659
SC		 8018 * "performant mode". Or, it might be 640x, which can't reset
8019 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 8020 */
adf1b3a3 8021 if (rc)
132aa220 8022 goto out_disable;
4c2a8c40
SC		 8023
8024 /* Now try to get the controller to respond to a no-op */
1ba66c9c 8025 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 8026 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
8027 if (hpsa_noop(pdev) == 0)
8028 break;
8029 else
8030 dev_warn(&pdev->dev, "no-op failed%s\n",
8031 (i < 11 ? "; re-trying" : ""));
8032 }
132aa220
TH		 8033
8034out_disable:
8035
8036 pci_disable_device(pdev);
8037 return rc;
4c2a8c40
SC		 8038}
8039
1fb7c98a
RE		 8040static void hpsa_free_cmd_pool(struct ctlr_info *h)
8041{
8042 kfree(h->cmd_pool_bits);
105a3dbc
RE		 8043 h->cmd_pool_bits = NULL;
8044 if (h->cmd_pool) {
1fb7c98a
RE		 8045 pci_free_consistent(h->pdev,
8046 h->nr_cmds * sizeof(struct CommandList),
8047 h->cmd_pool,
8048 h->cmd_pool_dhandle);
105a3dbc
RE		 8049 h->cmd_pool = NULL;
8050 h->cmd_pool_dhandle = 0;
8051 }
8052 if (h->errinfo_pool) {
1fb7c98a
RE		 8053 pci_free_consistent(h->pdev,
8054 h->nr_cmds * sizeof(struct ErrorInfo),
8055 h->errinfo_pool,
8056 h->errinfo_pool_dhandle);
105a3dbc
RE		 8057 h->errinfo_pool = NULL;
8058 h->errinfo_pool_dhandle = 0;
8059 }
1fb7c98a
RE		 8060}
8061
d37ffbe4 8062static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 8063{
8064 h->cmd_pool_bits = kzalloc(
8065 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
8066 sizeof(unsigned long), GFP_KERNEL);
8067 h->cmd_pool = pci_alloc_consistent(h->pdev,
8068 h->nr_cmds * sizeof(*h->cmd_pool),
8069 &(h->cmd_pool_dhandle));
8070 h->errinfo_pool = pci_alloc_consistent(h->pdev,
8071 h->nr_cmds * sizeof(*h->errinfo_pool),
8072 &(h->errinfo_pool_dhandle));
8073 if ((h->cmd_pool_bits == NULL)
8074 || (h->cmd_pool == NULL)
8075 || (h->errinfo_pool == NULL)) {
8076 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 8077 goto clean_up;
2e9d1b36 8078 }
360c73bd 8079 hpsa_preinitialize_commands(h);
2e9d1b36 8080 return 0;
2c143342
RE		 8081clean_up:
8082 hpsa_free_cmd_pool(h);
8083 return -ENOMEM;
2e9d1b36
SC		 8084}
8085
41b3cf08
SC		 8086static void hpsa_irq_affinity_hints(struct ctlr_info *h)
8087{
ec429952 8088 int i, cpu;
41b3cf08
SC		 8089
8090 cpu = cpumask_first(cpu_online_mask);
8091 for (i = 0; i < h->msix_vector; i++) {
ec429952 8092 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 8093 cpu = cpumask_next(cpu, cpu_online_mask);
8094 }
8095}
8096
ec501a18
RE		 8097/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
8098static void hpsa_free_irqs(struct ctlr_info *h)
8099{
8100 int i;
8101
8102 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
8103 /* Single reply queue, only one irq to free */
8104 i = h->intr_mode;
8105 irq_set_affinity_hint(h->intr[i], NULL);
8106 free_irq(h->intr[i], &h->q[i]);
105a3dbc 8107 h->q[i] = 0;
ec501a18
RE		 8108 return;
8109 }
8110
8111 for (i = 0; i < h->msix_vector; i++) {
8112 irq_set_affinity_hint(h->intr[i], NULL);
8113 free_irq(h->intr[i], &h->q[i]);
105a3dbc 8114 h->q[i] = 0;
ec501a18 8115 }
a4e17fc1
RE		 8116 for (; i < MAX_REPLY_QUEUES; i++)
8117 h->q[i] = 0;
ec501a18
RE		 8118}
8119
9ee61794
RE		 8120/* returns 0 on success; cleans up and returns -Enn on error */
8121static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 8122 irqreturn_t (*msixhandler)(int, void *),
8123 irqreturn_t (*intxhandler)(int, void *))
8124{
254f796b 8125 int rc, i;
0ae01a32 8126
254f796b
MG		 8127 /*
8128 * initialize h->q[x] = x so that interrupt handlers know which
8129 * queue to process.
8130 */
8131 for (i = 0; i < MAX_REPLY_QUEUES; i++)
8132 h->q[i] = (u8) i;
8133
eee0f03a 8134 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 8135 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 8136 for (i = 0; i < h->msix_vector; i++) {
8b47004a 8137 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
254f796b 8138 rc = request_irq(h->intr[i], msixhandler,
8b47004a 8139 0, h->intrname[i],
254f796b 8140 &h->q[i]);
a4e17fc1
RE		 8141 if (rc) {
8142 int j;
8143
8144 dev_err(&h->pdev->dev,
8145 "failed to get irq %d for %s\n",
8146 h->intr[i], h->devname);
8147 for (j = 0; j < i; j++) {
8148 free_irq(h->intr[j], &h->q[j]);
8149 h->q[j] = 0;
8150 }
8151 for (; j < MAX_REPLY_QUEUES; j++)
8152 h->q[j] = 0;
8153 return rc;
8154 }
8155 }
41b3cf08 8156 hpsa_irq_affinity_hints(h);
254f796b
MG		 8157 } else {
8158 /* Use single reply pool */
eee0f03a 8159 if (h->msix_vector > 0 || h->msi_vector) {
8b47004a
RE		 8160 if (h->msix_vector)
8161 sprintf(h->intrname[h->intr_mode],
8162 "%s-msix", h->devname);
8163 else
8164 sprintf(h->intrname[h->intr_mode],
8165 "%s-msi", h->devname);
254f796b 8166 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 8167 msixhandler, 0,
8168 h->intrname[h->intr_mode],
254f796b
MG		 8169 &h->q[h->intr_mode]);
8170 } else {
8b47004a
RE		 8171 sprintf(h->intrname[h->intr_mode],
8172 "%s-intx", h->devname);
254f796b 8173 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 8174 intxhandler, IRQF_SHARED,
8175 h->intrname[h->intr_mode],
254f796b
MG		 8176 &h->q[h->intr_mode]);
8177 }
105a3dbc 8178 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
254f796b 8179 }
0ae01a32 8180 if (rc) {
195f2c65 8181 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 8182 h->intr[h->intr_mode], h->devname);
195f2c65 8183 hpsa_free_irqs(h);
0ae01a32
SC		 8184 return -ENODEV;
8185 }
8186 return 0;
8187}
8188
6f039790 8189static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8 8190{
39c53f55 8191 int rc;
bf43caf3 8192 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
64670ac8
SC		 8193
8194 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
39c53f55
RE		 8195 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
8196 if (rc) {
64670ac8 8197 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
39c53f55 8198 return rc;
64670ac8
SC		 8199 }
8200
8201 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
39c53f55
RE		 8202 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
8203 if (rc) {
64670ac8
SC		 8204 dev_warn(&h->pdev->dev, "Board failed to become ready "
8205 "after soft reset.\n");
39c53f55 8206 return rc;
64670ac8
SC		 8207 }
8208
8209 return 0;
8210}
8211
072b0518
SC		 8212static void hpsa_free_reply_queues(struct ctlr_info *h)
8213{
8214 int i;
8215
8216 for (i = 0; i < h->nreply_queues; i++) {
8217 if (!h->reply_queue[i].head)
8218 continue;
1fb7c98a
RE		 8219 pci_free_consistent(h->pdev,
8220 h->reply_queue_size,
8221 h->reply_queue[i].head,
8222 h->reply_queue[i].busaddr);
072b0518
SC		 8223 h->reply_queue[i].head = NULL;
8224 h->reply_queue[i].busaddr = 0;
8225 }
105a3dbc 8226 h->reply_queue_size = 0;
072b0518
SC		 8227}
8228
0097f0f4
SC		 8229static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
8230{
105a3dbc
RE		 8231 hpsa_free_performant_mode(h); /* init_one 7 */
8232 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8233 hpsa_free_cmd_pool(h); /* init_one 5 */
8234 hpsa_free_irqs(h); /* init_one 4 */
2946e82b
RE		 8235 scsi_host_put(h->scsi_host); /* init_one 3 */
8236 h->scsi_host = NULL; /* init_one 3 */
8237 hpsa_free_pci_init(h); /* init_one 2_5 */
9ecd953a
RE		 8238 free_percpu(h->lockup_detected); /* init_one 2 */
8239 h->lockup_detected = NULL; /* init_one 2 */
8240 if (h->resubmit_wq) {
8241 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
8242 h->resubmit_wq = NULL;
8243 }
8244 if (h->rescan_ctlr_wq) {
8245 destroy_workqueue(h->rescan_ctlr_wq);
8246 h->rescan_ctlr_wq = NULL;
8247 }
105a3dbc 8248 kfree(h); /* init_one 1 */
64670ac8
SC		 8249}
8250
a0c12413 8251/* Called when controller lockup detected. */
f2405db8 8252static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 8253{
281a7fd0
WS		 8254 int i, refcount;
8255 struct CommandList *c;
25163bd5 8256 int failcount = 0;
a0c12413 8257
080ef1cc 8258 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 8259 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8260 c = h->cmd_pool + i;
281a7fd0
WS		 8261 refcount = atomic_inc_return(&c->refcount);
8262 if (refcount > 1) {
25163bd5 8263 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 8264 finish_cmd(c);
433b5f4d 8265 atomic_dec(&h->commands_outstanding);
25163bd5 8266 failcount++;
281a7fd0
WS		 8267 }
8268 cmd_free(h, c);
a0c12413 8269 }
25163bd5
WS		 8270 dev_warn(&h->pdev->dev,
8271 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 8272}
8273
094963da
SC		 8274static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
8275{
c8ed0010 8276 int cpu;
094963da 8277
c8ed0010 8278 for_each_online_cpu(cpu) {
094963da
SC		 8279 u32 *lockup_detected;
8280 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
8281 *lockup_detected = value;
094963da
SC		 8282 }
8283 wmb(); /* be sure the per-cpu variables are out to memory */
8284}
8285
a0c12413
SC		 8286static void controller_lockup_detected(struct ctlr_info *h)
8287{
8288 unsigned long flags;
094963da 8289 u32 lockup_detected;
a0c12413 8290
a0c12413
SC		 8291 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8292 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 8293 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
8294 if (!lockup_detected) {
8295 /* no heartbeat, but controller gave us a zero. */
8296 dev_warn(&h->pdev->dev,
25163bd5
WS		 8297 "lockup detected after %d but scratchpad register is zero\n",
8298 h->heartbeat_sample_interval / HZ);
094963da
SC		 8299 lockup_detected = 0xffffffff;
8300 }
8301 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 8302 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 8303 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
8304 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 8305 pci_disable_device(h->pdev);
f2405db8 8306 fail_all_outstanding_cmds(h);
a0c12413
SC		 8307}
8308
25163bd5 8309static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 8310{
8311 u64 now;
8312 u32 heartbeat;
8313 unsigned long flags;
8314
a0c12413
SC		 8315 now = get_jiffies_64();
8316 /* If we've received an interrupt recently, we're ok. */
8317 if (time_after64(h->last_intr_timestamp +
e85c5974 8318 (h->heartbeat_sample_interval), now))
25163bd5 8319 return false;
a0c12413
SC		 8320
8321 /*
8322 * If we've already checked the heartbeat recently, we're ok.
8323 * This could happen if someone sends us a signal. We
8324 * otherwise don't care about signals in this thread.
8325 */
8326 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 8327 (h->heartbeat_sample_interval), now))
25163bd5 8328 return false;
a0c12413
SC		 8329
8330 /* If heartbeat has not changed since we last looked, we're not ok. */
8331 spin_lock_irqsave(&h->lock, flags);
8332 heartbeat = readl(&h->cfgtable->HeartBeat);
8333 spin_unlock_irqrestore(&h->lock, flags);
8334 if (h->last_heartbeat == heartbeat) {
8335 controller_lockup_detected(h);
25163bd5 8336 return true;
a0c12413
SC		 8337 }
8338
8339 /* We're ok. */
8340 h->last_heartbeat = heartbeat;
8341 h->last_heartbeat_timestamp = now;
25163bd5 8342 return false;
a0c12413
SC		 8343}
8344
9846590e 8345static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 8346{
8347 int i;
8348 char *event_type;
8349
e4aa3e6a
SC		 8350 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
8351 return;
8352
76438d08 8353 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 8354 if ((h->transMethod & (CFGTBL_Trans_io_accel1
8355 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 8356 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
8357 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
8358
8359 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
8360 event_type = "state change";
8361 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
8362 event_type = "configuration change";
8363 /* Stop sending new RAID offload reqs via the IO accelerator */
8364 scsi_block_requests(h->scsi_host);
5323ed74 8365 for (i = 0; i < h->ndevices; i++) {
76438d08 8366 h->dev[i]->offload_enabled = 0;
5323ed74
DB		 8367 h->dev[i]->offload_to_be_enabled = 0;
8368 }
23100dd9 8369 hpsa_drain_accel_commands(h);
76438d08
SC		 8370 /* Set 'accelerator path config change' bit */
8371 dev_warn(&h->pdev->dev,
8372 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
8373 h->events, event_type);
8374 writel(h->events, &(h->cfgtable->clear_event_notify));
8375 /* Set the "clear event notify field update" bit 6 */
8376 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
8377 /* Wait until ctlr clears 'clear event notify field', bit 6 */
8378 hpsa_wait_for_clear_event_notify_ack(h);
8379 scsi_unblock_requests(h->scsi_host);
8380 } else {
8381 /* Acknowledge controller notification events. */
8382 writel(h->events, &(h->cfgtable->clear_event_notify));
8383 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
8384 hpsa_wait_for_clear_event_notify_ack(h);
8385#if 0
8386 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
8387 hpsa_wait_for_mode_change_ack(h);
8388#endif
8389 }
9846590e 8390 return;
76438d08
SC		 8391}
8392
8393/* Check a register on the controller to see if there are configuration
8394 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 8395 * we should rescan the controller for devices.
8396 * Also check flag for driver-initiated rescan.
76438d08 8397 */
9846590e 8398static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 8399{
853633e8
DB		 8400 if (h->drv_req_rescan) {
8401 h->drv_req_rescan = 0;
8402 return 1;
8403 }
8404
76438d08 8405 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 8406 return 0;
76438d08
SC		 8407
8408 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 8409 return h->events & RESCAN_REQUIRED_EVENT_BITS;
8410}
76438d08 8411
9846590e
SC		 8412/*
8413 * Check if any of the offline devices have become ready
8414 */
8415static int hpsa_offline_devices_ready(struct ctlr_info *h)
8416{
8417 unsigned long flags;
8418 struct offline_device_entry *d;
8419 struct list_head *this, *tmp;
8420
8421 spin_lock_irqsave(&h->offline_device_lock, flags);
8422 list_for_each_safe(this, tmp, &h->offline_device_list) {
8423 d = list_entry(this, struct offline_device_entry,
8424 offline_list);
8425 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 8426 if (!hpsa_volume_offline(h, d->scsi3addr)) {
8427 spin_lock_irqsave(&h->offline_device_lock, flags);
8428 list_del(&d->offline_list);
8429 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 8430 return 1;
d1fea47c 8431 }
9846590e
SC		 8432 spin_lock_irqsave(&h->offline_device_lock, flags);
8433 }
8434 spin_unlock_irqrestore(&h->offline_device_lock, flags);
8435 return 0;
76438d08
SC		 8436}
8437
34592254
ST		 8438static int hpsa_luns_changed(struct ctlr_info *h)
8439{
8440 int rc = 1; /* assume there are changes */
8441 struct ReportLUNdata *logdev = NULL;
8442
8443 /* if we can't find out if lun data has changed,
8444 * assume that it has.
8445 */
8446
8447 if (!h->lastlogicals)
8448 goto out;
8449
8450 logdev = kzalloc(sizeof(*logdev), GFP_KERNEL);
8451 if (!logdev) {
8452 dev_warn(&h->pdev->dev,
8453 "Out of memory, can't track lun changes.\n");
8454 goto out;
8455 }
8456 if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) {
8457 dev_warn(&h->pdev->dev,
8458 "report luns failed, can't track lun changes.\n");
8459 goto out;
8460 }
8461 if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) {
8462 dev_info(&h->pdev->dev,
8463 "Lun changes detected.\n");
8464 memcpy(h->lastlogicals, logdev, sizeof(*logdev));
8465 goto out;
8466 } else
8467 rc = 0; /* no changes detected. */
8468out:
8469 kfree(logdev);
8470 return rc;
8471}
8472
6636e7f4 8473static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 8474{
8475 unsigned long flags;
8a98db73 8476 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 8477 struct ctlr_info, rescan_ctlr_work);
8478
8479
8480 if (h->remove_in_progress)
8a98db73 8481 return;
9846590e
SC		 8482
8483 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
8484 scsi_host_get(h->scsi_host);
9846590e
SC		 8485 hpsa_ack_ctlr_events(h);
8486 hpsa_scan_start(h->scsi_host);
8487 scsi_host_put(h->scsi_host);
34592254 8488 } else if (h->discovery_polling) {
c2adae44 8489 hpsa_disable_rld_caching(h);
34592254
ST		 8490 if (hpsa_luns_changed(h)) {
8491 struct Scsi_Host *sh = NULL;
8492
8493 dev_info(&h->pdev->dev,
8494 "driver discovery polling rescan.\n");
8495 sh = scsi_host_get(h->scsi_host);
8496 if (sh != NULL) {
8497 hpsa_scan_start(sh);
8498 scsi_host_put(sh);
8499 }
8500 }
9846590e 8501 }
8a98db73 8502 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 8503 if (!h->remove_in_progress)
8504 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8505 h->heartbeat_sample_interval);
8506 spin_unlock_irqrestore(&h->lock, flags);
8507}
8508
8509static void hpsa_monitor_ctlr_worker(struct work_struct *work)
8510{
8511 unsigned long flags;
8512 struct ctlr_info *h = container_of(to_delayed_work(work),
8513 struct ctlr_info, monitor_ctlr_work);
8514
8515 detect_controller_lockup(h);
8516 if (lockup_detected(h))
a0c12413 8517 return;
6636e7f4
DB		 8518
8519 spin_lock_irqsave(&h->lock, flags);
8520 if (!h->remove_in_progress)
8521 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 8522 h->heartbeat_sample_interval);
8523 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 8524}
8525
6636e7f4
DB		 8526static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
8527 char *name)
8528{
8529 struct workqueue_struct *wq = NULL;
6636e7f4 8530
397ea9cb 8531 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 8532 if (!wq)
8533 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
8534
8535 return wq;
8536}
8537
6f039790 8538static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 8539{
4c2a8c40 8540 int dac, rc;
edd16368 8541 struct ctlr_info *h;
64670ac8
SC		 8542 int try_soft_reset = 0;
8543 unsigned long flags;
6b6c1cd7 8544 u32 board_id;
edd16368
SC		 8545
8546 if (number_of_controllers == 0)
8547 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 8548
6b6c1cd7
TH		 8549 rc = hpsa_lookup_board_id(pdev, &board_id);
8550 if (rc < 0) {
8551 dev_warn(&pdev->dev, "Board ID not found\n");
8552 return rc;
8553 }
8554
8555 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 8556 if (rc) {
8557 if (rc != -ENOTSUPP)
8558 return rc;
8559 /* If the reset fails in a particular way (it has no way to do
8560 * a proper hard reset, so returns -ENOTSUPP) we can try to do
8561 * a soft reset once we get the controller configured up to the
8562 * point that it can accept a command.
8563 */
8564 try_soft_reset = 1;
8565 rc = 0;
8566 }
8567
8568reinit_after_soft_reset:
edd16368 8569
303932fd
DB		 8570 /* Command structures must be aligned on a 32-byte boundary because
8571 * the 5 lower bits of the address are used by the hardware. and by
8572 * the driver. See comments in hpsa.h for more info.
8573 */
303932fd 8574 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368 8575 h = kzalloc(sizeof(*h), GFP_KERNEL);
105a3dbc
RE		 8576 if (!h) {
8577 dev_err(&pdev->dev, "Failed to allocate controller head\n");
ecd9aad4 8578 return -ENOMEM;
105a3dbc 8579 }
edd16368 8580
55c06c71 8581 h->pdev = pdev;
105a3dbc 8582
a9a3a273 8583 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 8584 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 8585 spin_lock_init(&h->lock);
9846590e 8586 spin_lock_init(&h->offline_device_lock);
6eaf46fd 8587 spin_lock_init(&h->scan_lock);
34f0c627 8588 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 8589 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da
SC		 8590
8591 /* Allocate and clear per-cpu variable lockup_detected */
8592 h->lockup_detected = alloc_percpu(u32);
2a5ac326 8593 if (!h->lockup_detected) {
105a3dbc 8594 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
2a5ac326 8595 rc = -ENOMEM;
2efa5929 8596 goto clean1; /* aer/h */
2a5ac326 8597 }
094963da
SC		 8598 set_lockup_detected_for_all_cpus(h, 0);
8599
55c06c71 8600 rc = hpsa_pci_init(h);
105a3dbc 8601 if (rc)
2946e82b
RE		 8602 goto clean2; /* lu, aer/h */
8603
8604 /* relies on h-> settings made by hpsa_pci_init, including
8605 * interrupt_mode h->intr */
8606 rc = hpsa_scsi_host_alloc(h);
8607 if (rc)
8608 goto clean2_5; /* pci, lu, aer/h */
edd16368 8609
2946e82b 8610 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
edd16368
SC		 8611 h->ctlr = number_of_controllers;
8612 number_of_controllers++;
edd16368
SC		 8613
8614 /* configure PCI DMA stuff */
ecd9aad4
SC		 8615 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
8616 if (rc == 0) {
edd16368 8617 dac = 1;
ecd9aad4
SC		 8618 } else {
8619 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8620 if (rc == 0) {
8621 dac = 0;
8622 } else {
8623 dev_err(&pdev->dev, "no suitable DMA available\n");
2946e82b 8624 goto clean3; /* shost, pci, lu, aer/h */
ecd9aad4 8625 }
edd16368
SC		 8626 }
8627
8628 /* make sure the board interrupts are off */
8629 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 8630
105a3dbc
RE		 8631 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
8632 if (rc)
2946e82b 8633 goto clean3; /* shost, pci, lu, aer/h */
d37ffbe4 8634 rc = hpsa_alloc_cmd_pool(h);
8947fd10 8635 if (rc)
2946e82b 8636 goto clean4; /* irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8637 rc = hpsa_alloc_sg_chain_blocks(h);
8638 if (rc)
2946e82b 8639 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
a08a8471 8640 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 8641 init_waitqueue_head(&h->abort_cmd_wait_queue);
d604f533
WS		 8642 init_waitqueue_head(&h->event_sync_wait_queue);
8643 mutex_init(&h->reset_mutex);
a08a8471 8644 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 8645
8646 pci_set_drvdata(pdev, h);
9a41338e 8647 h->ndevices = 0;
2946e82b 8648
9a41338e 8649 spin_lock_init(&h->devlock);
105a3dbc
RE		 8650 rc = hpsa_put_ctlr_into_performant_mode(h);
8651 if (rc)
2946e82b
RE		 8652 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8653
2efa5929
RE		 8654 /* create the resubmit workqueue */
8655 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8656 if (!h->rescan_ctlr_wq) {
8657 rc = -ENOMEM;
8658 goto clean7;
8659 }
8660
8661 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8662 if (!h->resubmit_wq) {
8663 rc = -ENOMEM;
8664 goto clean7; /* aer/h */
8665 }
64670ac8 8666
105a3dbc
RE		 8667 /*
8668 * At this point, the controller is ready to take commands.
64670ac8
SC		 8669 * Now, if reset_devices and the hard reset didn't work, try
8670 * the soft reset and see if that works.
8671 */
8672 if (try_soft_reset) {
8673
8674 /* This is kind of gross. We may or may not get a completion
8675 * from the soft reset command, and if we do, then the value
8676 * from the fifo may or may not be valid. So, we wait 10 secs
8677 * after the reset throwing away any completions we get during
8678 * that time. Unregister the interrupt handler and register
8679 * fake ones to scoop up any residual completions.
8680 */
8681 spin_lock_irqsave(&h->lock, flags);
8682 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8683 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 8684 hpsa_free_irqs(h);
9ee61794 8685 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 8686 hpsa_intx_discard_completions);
8687 if (rc) {
9ee61794
RE		 8688 dev_warn(&h->pdev->dev,
8689 "Failed to request_irq after soft reset.\n");
d498757c 8690 /*
b2ef480c
RE		 8691 * cannot goto clean7 or free_irqs will be called
8692 * again. Instead, do its work
8693 */
8694 hpsa_free_performant_mode(h); /* clean7 */
8695 hpsa_free_sg_chain_blocks(h); /* clean6 */
8696 hpsa_free_cmd_pool(h); /* clean5 */
8697 /*
8698 * skip hpsa_free_irqs(h) clean4 since that
8699 * was just called before request_irqs failed
d498757c
RE		 8700 */
8701 goto clean3;
64670ac8
SC		 8702 }
8703
8704 rc = hpsa_kdump_soft_reset(h);
8705 if (rc)
8706 /* Neither hard nor soft reset worked, we're hosed. */
7ef7323f 8707 goto clean7;
64670ac8
SC		 8708
8709 dev_info(&h->pdev->dev, "Board READY.\n");
8710 dev_info(&h->pdev->dev,
8711 "Waiting for stale completions to drain.\n");
8712 h->access.set_intr_mask(h, HPSA_INTR_ON);
8713 msleep(10000);
8714 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8715
8716 rc = controller_reset_failed(h->cfgtable);
8717 if (rc)
8718 dev_info(&h->pdev->dev,
8719 "Soft reset appears to have failed.\n");
8720
8721 /* since the controller's reset, we have to go back and re-init
8722 * everything. Easiest to just forget what we've done and do it
8723 * all over again.
8724 */
8725 hpsa_undo_allocations_after_kdump_soft_reset(h);
8726 try_soft_reset = 0;
8727 if (rc)
b2ef480c 8728 /* don't goto clean, we already unallocated */
64670ac8
SC		 8729 return -ENODEV;
8730
8731 goto reinit_after_soft_reset;
8732 }
edd16368 8733
105a3dbc
RE		 8734 /* Enable Accelerated IO path at driver layer */
8735 h->acciopath_status = 1;
34592254
ST		 8736 /* Disable discovery polling.*/
8737 h->discovery_polling = 0;
da0697bd 8738
e863d68e 8739
edd16368
SC		 8740 /* Turn the interrupts on so we can service requests */
8741 h->access.set_intr_mask(h, HPSA_INTR_ON);
8742
339b2b14 8743 hpsa_hba_inquiry(h);
8a98db73 8744
34592254
ST		 8745 h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL);
8746 if (!h->lastlogicals)
8747 dev_info(&h->pdev->dev,
8748 "Can't track change to report lun data\n");
8749
cf477237
DB		 8750 /* hook into SCSI subsystem */
8751 rc = hpsa_scsi_add_host(h);
8752 if (rc)
8753 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
8754
8a98db73
SC		 8755 /* Monitor the controller for firmware lockups */
8756 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8757 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8758 schedule_delayed_work(&h->monitor_ctlr_work,
8759 h->heartbeat_sample_interval);
6636e7f4
DB		 8760 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8761 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8762 h->heartbeat_sample_interval);
88bf6d62 8763 return 0;
edd16368 8764
2946e82b 8765clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8766 hpsa_free_performant_mode(h);
8767 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8768clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
33a2ffce 8769 hpsa_free_sg_chain_blocks(h);
2946e82b 8770clean5: /* cmd, irq, shost, pci, lu, aer/h */
2e9d1b36 8771 hpsa_free_cmd_pool(h);
2946e82b 8772clean4: /* irq, shost, pci, lu, aer/h */
ec501a18 8773 hpsa_free_irqs(h);
2946e82b
RE		 8774clean3: /* shost, pci, lu, aer/h */
8775 scsi_host_put(h->scsi_host);
8776 h->scsi_host = NULL;
8777clean2_5: /* pci, lu, aer/h */
195f2c65 8778 hpsa_free_pci_init(h);
2946e82b 8779clean2: /* lu, aer/h */
105a3dbc
RE		 8780 if (h->lockup_detected) {
8781 free_percpu(h->lockup_detected);
8782 h->lockup_detected = NULL;
8783 }
8784clean1: /* wq/aer/h */
8785 if (h->resubmit_wq) {
080ef1cc 8786 destroy_workqueue(h->resubmit_wq);
105a3dbc
RE		 8787 h->resubmit_wq = NULL;
8788 }
8789 if (h->rescan_ctlr_wq) {
6636e7f4 8790 destroy_workqueue(h->rescan_ctlr_wq);
105a3dbc
RE		 8791 h->rescan_ctlr_wq = NULL;
8792 }
edd16368 8793 kfree(h);
ecd9aad4 8794 return rc;
edd16368
SC		 8795}
8796
8797static void hpsa_flush_cache(struct ctlr_info *h)
8798{
8799 char *flush_buf;
8800 struct CommandList *c;
25163bd5 8801 int rc;
702890e3 8802
094963da 8803 if (unlikely(lockup_detected(h)))
702890e3 8804 return;
edd16368
SC		 8805 flush_buf = kzalloc(4, GFP_KERNEL);
8806 if (!flush_buf)
8807 return;
8808
45fcb86e 8809 c = cmd_alloc(h);
bf43caf3 8810
a2dac136
SC		 8811 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8812 RAID_CTLR_LUNID, TYPE_CMD)) {
8813 goto out;
8814 }
25163bd5 8815 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 8816 PCI_DMA_TODEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 8817 if (rc)
8818 goto out;
edd16368 8819 if (c->err_info->CommandStatus != 0)
a2dac136 8820out:
edd16368
SC		 8821 dev_warn(&h->pdev->dev,
8822 "error flushing cache on controller\n");
45fcb86e 8823 cmd_free(h, c);
edd16368
SC		 8824 kfree(flush_buf);
8825}
8826
c2adae44
ST		 8827/* Make controller gather fresh report lun data each time we
8828 * send down a report luns request
8829 */
8830static void hpsa_disable_rld_caching(struct ctlr_info *h)
8831{
8832 u32 *options;
8833 struct CommandList *c;
8834 int rc;
8835
8836 /* Don't bother trying to set diag options if locked up */
8837 if (unlikely(h->lockup_detected))
8838 return;
8839
8840 options = kzalloc(sizeof(*options), GFP_KERNEL);
8841 if (!options) {
8842 dev_err(&h->pdev->dev,
8843 "Error: failed to disable rld caching, during alloc.\n");
8844 return;
8845 }
8846
8847 c = cmd_alloc(h);
8848
8849 /* first, get the current diag options settings */
8850 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
8851 RAID_CTLR_LUNID, TYPE_CMD))
8852 goto errout;
8853
8854 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 8855 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
c2adae44
ST		 8856 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8857 goto errout;
8858
8859 /* Now, set the bit for disabling the RLD caching */
8860 *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING;
8861
8862 if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0,
8863 RAID_CTLR_LUNID, TYPE_CMD))
8864 goto errout;
8865
8866 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 8867 PCI_DMA_TODEVICE, DEFAULT_TIMEOUT);
c2adae44
ST		 8868 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8869 goto errout;
8870
8871 /* Now verify that it got set: */
8872 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
8873 RAID_CTLR_LUNID, TYPE_CMD))
8874 goto errout;
8875
8876 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 8877 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
c2adae44
ST		 8878 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8879 goto errout;
8880
d8a080c3 8881 if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING)
c2adae44
ST		 8882 goto out;
8883
8884errout:
8885 dev_err(&h->pdev->dev,
8886 "Error: failed to disable report lun data caching.\n");
8887out:
8888 cmd_free(h, c);
8889 kfree(options);
8890}
8891
edd16368
SC		 8892static void hpsa_shutdown(struct pci_dev *pdev)
8893{
8894 struct ctlr_info *h;
8895
8896 h = pci_get_drvdata(pdev);
8897 /* Turn board interrupts off and send the flush cache command
8898 * sendcmd will turn off interrupt, and send the flush...
8899 * To write all data in the battery backed cache to disks
8900 */
8901 hpsa_flush_cache(h);
8902 h->access.set_intr_mask(h, HPSA_INTR_OFF);
105a3dbc 8903 hpsa_free_irqs(h); /* init_one 4 */
cc64c817 8904 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 8905}
8906
6f039790 8907static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 8908{
8909 int i;
8910
105a3dbc 8911 for (i = 0; i < h->ndevices; i++) {
55e14e76 8912 kfree(h->dev[i]);
105a3dbc
RE		 8913 h->dev[i] = NULL;
8914 }
55e14e76
SC		 8915}
8916
6f039790 8917static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 8918{
8919 struct ctlr_info *h;
8a98db73 8920 unsigned long flags;
edd16368
SC		 8921
8922 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 8923 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 8924 return;
8925 }
8926 h = pci_get_drvdata(pdev);
8a98db73
SC		 8927
8928 /* Get rid of any controller monitoring work items */
8929 spin_lock_irqsave(&h->lock, flags);
8930 h->remove_in_progress = 1;
8a98db73 8931 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 8932 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8933 cancel_delayed_work_sync(&h->rescan_ctlr_work);
8934 destroy_workqueue(h->rescan_ctlr_wq);
8935 destroy_workqueue(h->resubmit_wq);
cc64c817 8936
2d041306
DB		 8937 /*
8938 * Call before disabling interrupts.
8939 * scsi_remove_host can trigger I/O operations especially
8940 * when multipath is enabled. There can be SYNCHRONIZE CACHE
8941 * operations which cannot complete and will hang the system.
8942 */
8943 if (h->scsi_host)
8944 scsi_remove_host(h->scsi_host); /* init_one 8 */
105a3dbc 8945 /* includes hpsa_free_irqs - init_one 4 */
195f2c65 8946 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 8947 hpsa_shutdown(pdev);
cc64c817 8948
105a3dbc
RE		 8949 hpsa_free_device_info(h); /* scan */
8950
2946e82b
RE		 8951 kfree(h->hba_inquiry_data); /* init_one 10 */
8952 h->hba_inquiry_data = NULL; /* init_one 10 */
2946e82b 8953 hpsa_free_ioaccel2_sg_chain_blocks(h);
105a3dbc
RE		 8954 hpsa_free_performant_mode(h); /* init_one 7 */
8955 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8956 hpsa_free_cmd_pool(h); /* init_one 5 */
34592254 8957 kfree(h->lastlogicals);
105a3dbc
RE		 8958
8959 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
195f2c65 8960
2946e82b
RE		 8961 scsi_host_put(h->scsi_host); /* init_one 3 */
8962 h->scsi_host = NULL; /* init_one 3 */
8963
195f2c65 8964 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
2946e82b 8965 hpsa_free_pci_init(h); /* init_one 2.5 */
195f2c65 8966
105a3dbc
RE		 8967 free_percpu(h->lockup_detected); /* init_one 2 */
8968 h->lockup_detected = NULL; /* init_one 2 */
8969 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
d04e62b9
KB		 8970
8971 hpsa_delete_sas_host(h);
8972
105a3dbc 8973 kfree(h); /* init_one 1 */
edd16368
SC		 8974}
8975
8976static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8977 __attribute__((unused)) pm_message_t state)
8978{
8979 return -ENOSYS;
8980}
8981
8982static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8983{
8984 return -ENOSYS;
8985}
8986
8987static struct pci_driver hpsa_pci_driver = {
f79cfec6 8988 .name = HPSA,
edd16368 8989 .probe = hpsa_init_one,
6f039790 8990 .remove = hpsa_remove_one,
edd16368
SC		 8991 .id_table = hpsa_pci_device_id, /* id_table */
8992 .shutdown = hpsa_shutdown,
8993 .suspend = hpsa_suspend,
8994 .resume = hpsa_resume,
8995};
8996
303932fd
DB		 8997/* Fill in bucket_map[], given nsgs (the max number of
8998 * scatter gather elements supported) and bucket[],
8999 * which is an array of 8 integers. The bucket[] array
9000 * contains 8 different DMA transfer sizes (in 16
9001 * byte increments) which the controller uses to fetch
9002 * commands. This function fills in bucket_map[], which
9003 * maps a given number of scatter gather elements to one of
9004 * the 8 DMA transfer sizes. The point of it is to allow the
9005 * controller to only do as much DMA as needed to fetch the
9006 * command, with the DMA transfer size encoded in the lower
9007 * bits of the command address.
9008 */
9009static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 9010 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 9011{
9012 int i, j, b, size;
9013
303932fd
DB		 9014 /* Note, bucket_map must have nsgs+1 entries. */
9015 for (i = 0; i <= nsgs; i++) {
9016 /* Compute size of a command with i SG entries */
e1f7de0c 9017 size = i + min_blocks;
303932fd
DB		 9018 b = num_buckets; /* Assume the biggest bucket */
9019 /* Find the bucket that is just big enough */
e1f7de0c 9020 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 9021 if (bucket[j] >= size) {
9022 b = j;
9023 break;
9024 }
9025 }
9026 /* for a command with i SG entries, use bucket b. */
9027 bucket_map[i] = b;
9028 }
9029}
9030
105a3dbc
RE		 9031/*
9032 * return -ENODEV on err, 0 on success (or no action)
9033 * allocates numerous items that must be freed later
9034 */
c706a795 9035static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 9036{
6c311b57
SC		 9037 int i;
9038 unsigned long register_value;
e1f7de0c
MG		 9039 unsigned long transMethod = CFGTBL_Trans_Performant |
9040 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 9041 CFGTBL_Trans_enable_directed_msix |
9042 (trans_support & (CFGTBL_Trans_io_accel1 |
9043 CFGTBL_Trans_io_accel2));
e1f7de0c 9044 struct access_method access = SA5_performant_access;
def342bd
SC		 9045
9046 /* This is a bit complicated. There are 8 registers on
9047 * the controller which we write to to tell it 8 different
9048 * sizes of commands which there may be. It's a way of
9049 * reducing the DMA done to fetch each command. Encoded into
9050 * each command's tag are 3 bits which communicate to the controller
9051 * which of the eight sizes that command fits within. The size of
9052 * each command depends on how many scatter gather entries there are.
9053 * Each SG entry requires 16 bytes. The eight registers are programmed
9054 * with the number of 16-byte blocks a command of that size requires.
9055 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 9056 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 9057 * blocks. Note, this only extends to the SG entries contained
9058 * within the command block, and does not extend to chained blocks
9059 * of SG elements. bft[] contains the eight values we write to
9060 * the registers. They are not evenly distributed, but have more
9061 * sizes for small commands, and fewer sizes for larger commands.
9062 */
d66ae08b 9063 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 9064#define MIN_IOACCEL2_BFT_ENTRY 5
9065#define HPSA_IOACCEL2_HEADER_SZ 4
9066 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
9067 13, 14, 15, 16, 17, 18, 19,
9068 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
9069 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
9070 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
9071 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
9072 16 * MIN_IOACCEL2_BFT_ENTRY);
9073 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 9074 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 9075 /* 5 = 1 s/g entry or 4k
9076 * 6 = 2 s/g entry or 8k
9077 * 8 = 4 s/g entry or 16k
9078 * 10 = 6 s/g entry or 24k
9079 */
303932fd 9080
b3a52e79
SC		 9081 /* If the controller supports either ioaccel method then
9082 * we can also use the RAID stack submit path that does not
9083 * perform the superfluous readl() after each command submission.
9084 */
9085 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
9086 access = SA5_performant_access_no_read;
9087
303932fd 9088 /* Controller spec: zero out this buffer. */
072b0518
SC		 9089 for (i = 0; i < h->nreply_queues; i++)
9090 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 9091
d66ae08b
SC		 9092 bft[7] = SG_ENTRIES_IN_CMD + 4;
9093 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 9094 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 9095 for (i = 0; i < 8; i++)
9096 writel(bft[i], &h->transtable->BlockFetch[i]);
9097
9098 /* size of controller ring buffer */
9099 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 9100 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 9101 writel(0, &h->transtable->RepQCtrAddrLow32);
9102 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 9103
9104 for (i = 0; i < h->nreply_queues; i++) {
9105 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 9106 writel(h->reply_queue[i].busaddr,
254f796b
MG		 9107 &h->transtable->RepQAddr[i].lower);
9108 }
9109
b9af4937 9110 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 9111 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
9112 /*
9113 * enable outbound interrupt coalescing in accelerator mode;
9114 */
9115 if (trans_support & CFGTBL_Trans_io_accel1) {
9116 access = SA5_ioaccel_mode1_access;
9117 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
9118 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 9119 } else {
9120 if (trans_support & CFGTBL_Trans_io_accel2) {
9121 access = SA5_ioaccel_mode2_access;
9122 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
9123 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
9124 }
e1f7de0c 9125 }
303932fd 9126 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 9127 if (hpsa_wait_for_mode_change_ack(h)) {
9128 dev_err(&h->pdev->dev,
9129 "performant mode problem - doorbell timeout\n");
9130 return -ENODEV;
9131 }
303932fd
DB		 9132 register_value = readl(&(h->cfgtable->TransportActive));
9133 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 9134 dev_err(&h->pdev->dev,
9135 "performant mode problem - transport not active\n");
c706a795 9136 return -ENODEV;
303932fd 9137 }
960a30e7 9138 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 9139 h->access = access;
9140 h->transMethod = transMethod;
9141
b9af4937
SC		 9142 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
9143 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 9144 return 0;
e1f7de0c 9145
b9af4937
SC		 9146 if (trans_support & CFGTBL_Trans_io_accel1) {
9147 /* Set up I/O accelerator mode */
9148 for (i = 0; i < h->nreply_queues; i++) {
9149 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
9150 h->reply_queue[i].current_entry =
9151 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
9152 }
9153 bft[7] = h->ioaccel_maxsg + 8;
9154 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
9155 h->ioaccel1_blockFetchTable);
e1f7de0c 9156
b9af4937 9157 /* initialize all reply queue entries to unused */
072b0518
SC		 9158 for (i = 0; i < h->nreply_queues; i++)
9159 memset(h->reply_queue[i].head,
9160 (u8) IOACCEL_MODE1_REPLY_UNUSED,
9161 h->reply_queue_size);
e1f7de0c 9162
b9af4937
SC		 9163 /* set all the constant fields in the accelerator command
9164 * frames once at init time to save CPU cycles later.
9165 */
9166 for (i = 0; i < h->nr_cmds; i++) {
9167 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
9168
9169 cp->function = IOACCEL1_FUNCTION_SCSIIO;
9170 cp->err_info = (u32) (h->errinfo_pool_dhandle +
9171 (i * sizeof(struct ErrorInfo)));
9172 cp->err_info_len = sizeof(struct ErrorInfo);
9173 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 9174 cp->host_context_flags =
9175 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 9176 cp->timeout_sec = 0;
9177 cp->ReplyQueue = 0;
50a0decf 9178 cp->tag =
f2405db8 9179 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 9180 cp->host_addr =
9181 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 9182 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 9183 }
9184 } else if (trans_support & CFGTBL_Trans_io_accel2) {
9185 u64 cfg_offset, cfg_base_addr_index;
9186 u32 bft2_offset, cfg_base_addr;
9187 int rc;
9188
9189 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
9190 &cfg_base_addr_index, &cfg_offset);
9191 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
9192 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
9193 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
9194 4, h->ioaccel2_blockFetchTable);
9195 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
9196 BUILD_BUG_ON(offsetof(struct CfgTable,
9197 io_accel_request_size_offset) != 0xb8);
9198 h->ioaccel2_bft2_regs =
9199 remap_pci_mem(pci_resource_start(h->pdev,
9200 cfg_base_addr_index) +
9201 cfg_offset + bft2_offset,
9202 ARRAY_SIZE(bft2) *
9203 sizeof(*h->ioaccel2_bft2_regs));
9204 for (i = 0; i < ARRAY_SIZE(bft2); i++)
9205 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 9206 }
b9af4937 9207 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 9208 if (hpsa_wait_for_mode_change_ack(h)) {
9209 dev_err(&h->pdev->dev,
9210 "performant mode problem - enabling ioaccel mode\n");
9211 return -ENODEV;
9212 }
9213 return 0;
e1f7de0c
MG		 9214}
9215
1fb7c98a
RE		 9216/* Free ioaccel1 mode command blocks and block fetch table */
9217static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
9218{
105a3dbc 9219 if (h->ioaccel_cmd_pool) {
1fb7c98a
RE		 9220 pci_free_consistent(h->pdev,
9221 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
9222 h->ioaccel_cmd_pool,
9223 h->ioaccel_cmd_pool_dhandle);
105a3dbc
RE		 9224 h->ioaccel_cmd_pool = NULL;
9225 h->ioaccel_cmd_pool_dhandle = 0;
9226 }
1fb7c98a 9227 kfree(h->ioaccel1_blockFetchTable);
105a3dbc 9228 h->ioaccel1_blockFetchTable = NULL;
1fb7c98a
RE		 9229}
9230
d37ffbe4
RE		 9231/* Allocate ioaccel1 mode command blocks and block fetch table */
9232static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 9233{
283b4a9b
SC		 9234 h->ioaccel_maxsg =
9235 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
9236 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
9237 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
9238
e1f7de0c
MG		 9239 /* Command structures must be aligned on a 128-byte boundary
9240 * because the 7 lower bits of the address are used by the
9241 * hardware.
9242 */
e1f7de0c
MG		 9243 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
9244 IOACCEL1_COMMANDLIST_ALIGNMENT);
9245 h->ioaccel_cmd_pool =
9246 pci_alloc_consistent(h->pdev,
9247 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
9248 &(h->ioaccel_cmd_pool_dhandle));
9249
9250 h->ioaccel1_blockFetchTable =
283b4a9b 9251 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 9252 sizeof(u32)), GFP_KERNEL);
9253
9254 if ((h->ioaccel_cmd_pool == NULL) ||
9255 (h->ioaccel1_blockFetchTable == NULL))
9256 goto clean_up;
9257
9258 memset(h->ioaccel_cmd_pool, 0,
9259 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
9260 return 0;
9261
9262clean_up:
1fb7c98a 9263 hpsa_free_ioaccel1_cmd_and_bft(h);
2dd02d74 9264 return -ENOMEM;
6c311b57
SC		 9265}
9266
1fb7c98a
RE		 9267/* Free ioaccel2 mode command blocks and block fetch table */
9268static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
9269{
d9a729f3
WS		 9270 hpsa_free_ioaccel2_sg_chain_blocks(h);
9271
105a3dbc 9272 if (h->ioaccel2_cmd_pool) {
1fb7c98a
RE		 9273 pci_free_consistent(h->pdev,
9274 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
9275 h->ioaccel2_cmd_pool,
9276 h->ioaccel2_cmd_pool_dhandle);
105a3dbc
RE		 9277 h->ioaccel2_cmd_pool = NULL;
9278 h->ioaccel2_cmd_pool_dhandle = 0;
9279 }
1fb7c98a 9280 kfree(h->ioaccel2_blockFetchTable);
105a3dbc 9281 h->ioaccel2_blockFetchTable = NULL;
1fb7c98a
RE		 9282}
9283
d37ffbe4
RE		 9284/* Allocate ioaccel2 mode command blocks and block fetch table */
9285static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 9286{
d9a729f3
WS		 9287 int rc;
9288
aca9012a
SC		 9289 /* Allocate ioaccel2 mode command blocks and block fetch table */
9290
9291 h->ioaccel_maxsg =
9292 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
9293 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
9294 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
9295
aca9012a
SC		 9296 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
9297 IOACCEL2_COMMANDLIST_ALIGNMENT);
9298 h->ioaccel2_cmd_pool =
9299 pci_alloc_consistent(h->pdev,
9300 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
9301 &(h->ioaccel2_cmd_pool_dhandle));
9302
9303 h->ioaccel2_blockFetchTable =
9304 kmalloc(((h->ioaccel_maxsg + 1) *
9305 sizeof(u32)), GFP_KERNEL);
9306
9307 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 9308 (h->ioaccel2_blockFetchTable == NULL)) {
9309 rc = -ENOMEM;
9310 goto clean_up;
9311 }
9312
9313 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
9314 if (rc)
aca9012a
SC		 9315 goto clean_up;
9316
9317 memset(h->ioaccel2_cmd_pool, 0,
9318 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
9319 return 0;
9320
9321clean_up:
1fb7c98a 9322 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 9323 return rc;
aca9012a
SC		 9324}
9325
105a3dbc
RE		 9326/* Free items allocated by hpsa_put_ctlr_into_performant_mode */
9327static void hpsa_free_performant_mode(struct ctlr_info *h)
9328{
9329 kfree(h->blockFetchTable);
9330 h->blockFetchTable = NULL;
9331 hpsa_free_reply_queues(h);
9332 hpsa_free_ioaccel1_cmd_and_bft(h);
9333 hpsa_free_ioaccel2_cmd_and_bft(h);
9334}
9335
9336/* return -ENODEV on error, 0 on success (or no action)
9337 * allocates numerous items that must be freed later
9338 */
9339static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 9340{
9341 u32 trans_support;
e1f7de0c
MG		 9342 unsigned long transMethod = CFGTBL_Trans_Performant |
9343 CFGTBL_Trans_use_short_tags;
105a3dbc 9344 int i, rc;
6c311b57 9345
02ec19c8 9346 if (hpsa_simple_mode)
105a3dbc 9347 return 0;
02ec19c8 9348
67c99a72 9349 trans_support = readl(&(h->cfgtable->TransportSupport));
9350 if (!(trans_support & PERFORMANT_MODE))
105a3dbc 9351 return 0;
67c99a72 9352
e1f7de0c
MG		 9353 /* Check for I/O accelerator mode support */
9354 if (trans_support & CFGTBL_Trans_io_accel1) {
9355 transMethod |= CFGTBL_Trans_io_accel1 |
9356 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 9357 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
9358 if (rc)
9359 return rc;
9360 } else if (trans_support & CFGTBL_Trans_io_accel2) {
9361 transMethod |= CFGTBL_Trans_io_accel2 |
aca9012a 9362 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 9363 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
9364 if (rc)
9365 return rc;
e1f7de0c
MG		 9366 }
9367
eee0f03a 9368 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 9369 hpsa_get_max_perf_mode_cmds(h);
6c311b57 9370 /* Performant mode ring buffer and supporting data structures */
072b0518 9371 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 9372
254f796b 9373 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 9374 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
9375 h->reply_queue_size,
9376 &(h->reply_queue[i].busaddr));
105a3dbc
RE		 9377 if (!h->reply_queue[i].head) {
9378 rc = -ENOMEM;
9379 goto clean1; /* rq, ioaccel */
9380 }
254f796b
MG		 9381 h->reply_queue[i].size = h->max_commands;
9382 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
9383 h->reply_queue[i].current_entry = 0;
9384 }
9385
6c311b57 9386 /* Need a block fetch table for performant mode */
d66ae08b 9387 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 9388 sizeof(u32)), GFP_KERNEL);
105a3dbc
RE		 9389 if (!h->blockFetchTable) {
9390 rc = -ENOMEM;
9391 goto clean1; /* rq, ioaccel */
9392 }
6c311b57 9393
105a3dbc
RE		 9394 rc = hpsa_enter_performant_mode(h, trans_support);
9395 if (rc)
9396 goto clean2; /* bft, rq, ioaccel */
9397 return 0;
303932fd 9398
105a3dbc 9399clean2: /* bft, rq, ioaccel */
303932fd 9400 kfree(h->blockFetchTable);
105a3dbc
RE		 9401 h->blockFetchTable = NULL;
9402clean1: /* rq, ioaccel */
9403 hpsa_free_reply_queues(h);
9404 hpsa_free_ioaccel1_cmd_and_bft(h);
9405 hpsa_free_ioaccel2_cmd_and_bft(h);
9406 return rc;
303932fd
DB		 9407}
9408
23100dd9 9409static int is_accelerated_cmd(struct CommandList *c)
76438d08 9410{
23100dd9
SC		 9411 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
9412}
9413
9414static void hpsa_drain_accel_commands(struct ctlr_info *h)
9415{
9416 struct CommandList *c = NULL;
f2405db8 9417 int i, accel_cmds_out;
281a7fd0 9418 int refcount;
76438d08 9419
f2405db8 9420 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 9421 accel_cmds_out = 0;
f2405db8 9422 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 9423 c = h->cmd_pool + i;
281a7fd0
WS		 9424 refcount = atomic_inc_return(&c->refcount);
9425 if (refcount > 1) /* Command is allocated */
9426 accel_cmds_out += is_accelerated_cmd(c);
9427 cmd_free(h, c);
f2405db8 9428 }
23100dd9 9429 if (accel_cmds_out <= 0)
281a7fd0 9430 break;
76438d08
SC		 9431 msleep(100);
9432 } while (1);
9433}
9434
d04e62b9
KB		 9435static struct hpsa_sas_phy *hpsa_alloc_sas_phy(
9436 struct hpsa_sas_port *hpsa_sas_port)
9437{
9438 struct hpsa_sas_phy *hpsa_sas_phy;
9439 struct sas_phy *phy;
9440
9441 hpsa_sas_phy = kzalloc(sizeof(*hpsa_sas_phy), GFP_KERNEL);
9442 if (!hpsa_sas_phy)
9443 return NULL;
9444
9445 phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev,
9446 hpsa_sas_port->next_phy_index);
9447 if (!phy) {
9448 kfree(hpsa_sas_phy);
9449 return NULL;
9450 }
9451
9452 hpsa_sas_port->next_phy_index++;
9453 hpsa_sas_phy->phy = phy;
9454 hpsa_sas_phy->parent_port = hpsa_sas_port;
9455
9456 return hpsa_sas_phy;
9457}
9458
9459static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy)
9460{
9461 struct sas_phy *phy = hpsa_sas_phy->phy;
9462
9463 sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy);
9464 sas_phy_free(phy);
9465 if (hpsa_sas_phy->added_to_port)
9466 list_del(&hpsa_sas_phy->phy_list_entry);
9467 kfree(hpsa_sas_phy);
9468}
9469
9470static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy)
9471{
9472 int rc;
9473 struct hpsa_sas_port *hpsa_sas_port;
9474 struct sas_phy *phy;
9475 struct sas_identify *identify;
9476
9477 hpsa_sas_port = hpsa_sas_phy->parent_port;
9478 phy = hpsa_sas_phy->phy;
9479
9480 identify = &phy->identify;
9481 memset(identify, 0, sizeof(*identify));
9482 identify->sas_address = hpsa_sas_port->sas_address;
9483 identify->device_type = SAS_END_DEVICE;
9484 identify->initiator_port_protocols = SAS_PROTOCOL_STP;
9485 identify->target_port_protocols = SAS_PROTOCOL_STP;
9486 phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
9487 phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
9488 phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN;
9489 phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN;
9490 phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN;
9491
9492 rc = sas_phy_add(hpsa_sas_phy->phy);
9493 if (rc)
9494 return rc;
9495
9496 sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy);
9497 list_add_tail(&hpsa_sas_phy->phy_list_entry,
9498 &hpsa_sas_port->phy_list_head);
9499 hpsa_sas_phy->added_to_port = true;
9500
9501 return 0;
9502}
9503
9504static int
9505 hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port,
9506 struct sas_rphy *rphy)
9507{
9508 struct sas_identify *identify;
9509
9510 identify = &rphy->identify;
9511 identify->sas_address = hpsa_sas_port->sas_address;
9512 identify->initiator_port_protocols = SAS_PROTOCOL_STP;
9513 identify->target_port_protocols = SAS_PROTOCOL_STP;
9514
9515 return sas_rphy_add(rphy);
9516}
9517
9518static struct hpsa_sas_port
9519 *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node,
9520 u64 sas_address)
9521{
9522 int rc;
9523 struct hpsa_sas_port *hpsa_sas_port;
9524 struct sas_port *port;
9525
9526 hpsa_sas_port = kzalloc(sizeof(*hpsa_sas_port), GFP_KERNEL);
9527 if (!hpsa_sas_port)
9528 return NULL;
9529
9530 INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head);
9531 hpsa_sas_port->parent_node = hpsa_sas_node;
9532
9533 port = sas_port_alloc_num(hpsa_sas_node->parent_dev);
9534 if (!port)
9535 goto free_hpsa_port;
9536
9537 rc = sas_port_add(port);
9538 if (rc)
9539 goto free_sas_port;
9540
9541 hpsa_sas_port->port = port;
9542 hpsa_sas_port->sas_address = sas_address;
9543 list_add_tail(&hpsa_sas_port->port_list_entry,
9544 &hpsa_sas_node->port_list_head);
9545
9546 return hpsa_sas_port;
9547
9548free_sas_port:
9549 sas_port_free(port);
9550free_hpsa_port:
9551 kfree(hpsa_sas_port);
9552
9553 return NULL;
9554}
9555
9556static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port)
9557{
9558 struct hpsa_sas_phy *hpsa_sas_phy;
9559 struct hpsa_sas_phy *next;
9560
9561 list_for_each_entry_safe(hpsa_sas_phy, next,
9562 &hpsa_sas_port->phy_list_head, phy_list_entry)
9563 hpsa_free_sas_phy(hpsa_sas_phy);
9564
9565 sas_port_delete(hpsa_sas_port->port);
9566 list_del(&hpsa_sas_port->port_list_entry);
9567 kfree(hpsa_sas_port);
9568}
9569
9570static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev)
9571{
9572 struct hpsa_sas_node *hpsa_sas_node;
9573
9574 hpsa_sas_node = kzalloc(sizeof(*hpsa_sas_node), GFP_KERNEL);
9575 if (hpsa_sas_node) {
9576 hpsa_sas_node->parent_dev = parent_dev;
9577 INIT_LIST_HEAD(&hpsa_sas_node->port_list_head);
9578 }
9579
9580 return hpsa_sas_node;
9581}
9582
9583static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node)
9584{
9585 struct hpsa_sas_port *hpsa_sas_port;
9586 struct hpsa_sas_port *next;
9587
9588 if (!hpsa_sas_node)
9589 return;
9590
9591 list_for_each_entry_safe(hpsa_sas_port, next,
9592 &hpsa_sas_node->port_list_head, port_list_entry)
9593 hpsa_free_sas_port(hpsa_sas_port);
9594
9595 kfree(hpsa_sas_node);
9596}
9597
9598static struct hpsa_scsi_dev_t
9599 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
9600 struct sas_rphy *rphy)
9601{
9602 int i;
9603 struct hpsa_scsi_dev_t *device;
9604
9605 for (i = 0; i < h->ndevices; i++) {
9606 device = h->dev[i];
9607 if (!device->sas_port)
9608 continue;
9609 if (device->sas_port->rphy == rphy)
9610 return device;
9611 }
9612
9613 return NULL;
9614}
9615
9616static int hpsa_add_sas_host(struct ctlr_info *h)
9617{
9618 int rc;
9619 struct device *parent_dev;
9620 struct hpsa_sas_node *hpsa_sas_node;
9621 struct hpsa_sas_port *hpsa_sas_port;
9622 struct hpsa_sas_phy *hpsa_sas_phy;
9623
9624 parent_dev = &h->scsi_host->shost_gendev;
9625
9626 hpsa_sas_node = hpsa_alloc_sas_node(parent_dev);
9627 if (!hpsa_sas_node)
9628 return -ENOMEM;
9629
9630 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address);
9631 if (!hpsa_sas_port) {
9632 rc = -ENODEV;
9633 goto free_sas_node;
9634 }
9635
9636 hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port);
9637 if (!hpsa_sas_phy) {
9638 rc = -ENODEV;
9639 goto free_sas_port;
9640 }
9641
9642 rc = hpsa_sas_port_add_phy(hpsa_sas_phy);
9643 if (rc)
9644 goto free_sas_phy;
9645
9646 h->sas_host = hpsa_sas_node;
9647
9648 return 0;
9649
9650free_sas_phy:
9651 hpsa_free_sas_phy(hpsa_sas_phy);
9652free_sas_port:
9653 hpsa_free_sas_port(hpsa_sas_port);
9654free_sas_node:
9655 hpsa_free_sas_node(hpsa_sas_node);
9656
9657 return rc;
9658}
9659
9660static void hpsa_delete_sas_host(struct ctlr_info *h)
9661{
9662 hpsa_free_sas_node(h->sas_host);
9663}
9664
9665static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
9666 struct hpsa_scsi_dev_t *device)
9667{
9668 int rc;
9669 struct hpsa_sas_port *hpsa_sas_port;
9670 struct sas_rphy *rphy;
9671
9672 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address);
9673 if (!hpsa_sas_port)
9674 return -ENOMEM;
9675
9676 rphy = sas_end_device_alloc(hpsa_sas_port->port);
9677 if (!rphy) {
9678 rc = -ENODEV;
9679 goto free_sas_port;
9680 }
9681
9682 hpsa_sas_port->rphy = rphy;
9683 device->sas_port = hpsa_sas_port;
9684
9685 rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy);
9686 if (rc)
9687 goto free_sas_port;
9688
9689 return 0;
9690
9691free_sas_port:
9692 hpsa_free_sas_port(hpsa_sas_port);
9693 device->sas_port = NULL;
9694
9695 return rc;
9696}
9697
9698static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device)
9699{
9700 if (device->sas_port) {
9701 hpsa_free_sas_port(device->sas_port);
9702 device->sas_port = NULL;
9703 }
9704}
9705
9706static int
9707hpsa_sas_get_linkerrors(struct sas_phy *phy)
9708{
9709 return 0;
9710}
9711
9712static int
9713hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier)
9714{
aa105695 9715 *identifier = 0;
d04e62b9
KB		 9716 return 0;
9717}
9718
9719static int
9720hpsa_sas_get_bay_identifier(struct sas_rphy *rphy)
9721{
9722 return -ENXIO;
9723}
9724
9725static int
9726hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset)
9727{
9728 return 0;
9729}
9730
9731static int
9732hpsa_sas_phy_enable(struct sas_phy *phy, int enable)
9733{
9734 return 0;
9735}
9736
9737static int
9738hpsa_sas_phy_setup(struct sas_phy *phy)
9739{
9740 return 0;
9741}
9742
9743static void
9744hpsa_sas_phy_release(struct sas_phy *phy)
9745{
9746}
9747
9748static int
9749hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates)
9750{
9751 return -EINVAL;
9752}
9753
9754/* SMP = Serial Management Protocol */
9755static int
9756hpsa_sas_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy,
9757struct request *req)
9758{
9759 return -EINVAL;
9760}
9761
9762static struct sas_function_template hpsa_sas_transport_functions = {
9763 .get_linkerrors = hpsa_sas_get_linkerrors,
9764 .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier,
9765 .get_bay_identifier = hpsa_sas_get_bay_identifier,
9766 .phy_reset = hpsa_sas_phy_reset,
9767 .phy_enable = hpsa_sas_phy_enable,
9768 .phy_setup = hpsa_sas_phy_setup,
9769 .phy_release = hpsa_sas_phy_release,
9770 .set_phy_speed = hpsa_sas_phy_speed,
9771 .smp_handler = hpsa_sas_smp_handler,
9772};
9773
edd16368
SC		 9774/*
9775 * This is it. Register the PCI driver information for the cards we control
9776 * the OS will call our registered routines when it finds one of our cards.
9777 */
9778static int __init hpsa_init(void)
9779{
d04e62b9
KB		 9780 int rc;
9781
9782 hpsa_sas_transport_template =
9783 sas_attach_transport(&hpsa_sas_transport_functions);
9784 if (!hpsa_sas_transport_template)
9785 return -ENODEV;
9786
9787 rc = pci_register_driver(&hpsa_pci_driver);
9788
9789 if (rc)
9790 sas_release_transport(hpsa_sas_transport_template);
9791
9792 return rc;
edd16368
SC		 9793}
9794
9795static void __exit hpsa_cleanup(void)
9796{
9797 pci_unregister_driver(&hpsa_pci_driver);
d04e62b9 9798 sas_release_transport(hpsa_sas_transport_template);
edd16368
SC		 9799}
9800
e1f7de0c
MG		 9801static void __attribute__((unused)) verify_offsets(void)
9802{
dd0e19f3
ST		 9803#define VERIFY_OFFSET(member, offset) \
9804 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
9805
9806 VERIFY_OFFSET(structure_size, 0);
9807 VERIFY_OFFSET(volume_blk_size, 4);
9808 VERIFY_OFFSET(volume_blk_cnt, 8);
9809 VERIFY_OFFSET(phys_blk_shift, 16);
9810 VERIFY_OFFSET(parity_rotation_shift, 17);
9811 VERIFY_OFFSET(strip_size, 18);
9812 VERIFY_OFFSET(disk_starting_blk, 20);
9813 VERIFY_OFFSET(disk_blk_cnt, 28);
9814 VERIFY_OFFSET(data_disks_per_row, 36);
9815 VERIFY_OFFSET(metadata_disks_per_row, 38);
9816 VERIFY_OFFSET(row_cnt, 40);
9817 VERIFY_OFFSET(layout_map_count, 42);
9818 VERIFY_OFFSET(flags, 44);
9819 VERIFY_OFFSET(dekindex, 46);
9820 /* VERIFY_OFFSET(reserved, 48 */
9821 VERIFY_OFFSET(data, 64);
9822
9823#undef VERIFY_OFFSET
9824
b66cc250
MM		 9825#define VERIFY_OFFSET(member, offset) \
9826 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
9827
9828 VERIFY_OFFSET(IU_type, 0);
9829 VERIFY_OFFSET(direction, 1);
9830 VERIFY_OFFSET(reply_queue, 2);
9831 /* VERIFY_OFFSET(reserved1, 3); */
9832 VERIFY_OFFSET(scsi_nexus, 4);
9833 VERIFY_OFFSET(Tag, 8);
9834 VERIFY_OFFSET(cdb, 16);
9835 VERIFY_OFFSET(cciss_lun, 32);
9836 VERIFY_OFFSET(data_len, 40);
9837 VERIFY_OFFSET(cmd_priority_task_attr, 44);
9838 VERIFY_OFFSET(sg_count, 45);
9839 /* VERIFY_OFFSET(reserved3 */
9840 VERIFY_OFFSET(err_ptr, 48);
9841 VERIFY_OFFSET(err_len, 56);
9842 /* VERIFY_OFFSET(reserved4 */
9843 VERIFY_OFFSET(sg, 64);
9844
9845#undef VERIFY_OFFSET
9846
e1f7de0c
MG		 9847#define VERIFY_OFFSET(member, offset) \
9848 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
9849
9850 VERIFY_OFFSET(dev_handle, 0x00);
9851 VERIFY_OFFSET(reserved1, 0x02);
9852 VERIFY_OFFSET(function, 0x03);
9853 VERIFY_OFFSET(reserved2, 0x04);
9854 VERIFY_OFFSET(err_info, 0x0C);
9855 VERIFY_OFFSET(reserved3, 0x10);
9856 VERIFY_OFFSET(err_info_len, 0x12);
9857 VERIFY_OFFSET(reserved4, 0x13);
9858 VERIFY_OFFSET(sgl_offset, 0x14);
9859 VERIFY_OFFSET(reserved5, 0x15);
9860 VERIFY_OFFSET(transfer_len, 0x1C);
9861 VERIFY_OFFSET(reserved6, 0x20);
9862 VERIFY_OFFSET(io_flags, 0x24);
9863 VERIFY_OFFSET(reserved7, 0x26);
9864 VERIFY_OFFSET(LUN, 0x34);
9865 VERIFY_OFFSET(control, 0x3C);
9866 VERIFY_OFFSET(CDB, 0x40);
9867 VERIFY_OFFSET(reserved8, 0x50);
9868 VERIFY_OFFSET(host_context_flags, 0x60);
9869 VERIFY_OFFSET(timeout_sec, 0x62);
9870 VERIFY_OFFSET(ReplyQueue, 0x64);
9871 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 9872 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 9873 VERIFY_OFFSET(host_addr, 0x70);
9874 VERIFY_OFFSET(CISS_LUN, 0x78);
9875 VERIFY_OFFSET(SG, 0x78 + 8);
9876#undef VERIFY_OFFSET
9877}
9878
edd16368
SC		 9879module_init(hpsa_init);
9880module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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