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[SCSI] hpsa: update raid offload status on device rescan
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
edd16368 50#include <linux/kthread.h>
a0c12413 51#include <linux/jiffies.h>
283b4a9b 52#include <asm/div64.h>
edd16368
SC		 53#include "hpsa_cmd.h"
54#include "hpsa.h"
55
56/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
e481cce8 57#define HPSA_DRIVER_VERSION "3.4.0-1"
edd16368 58#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 59#define HPSA "hpsa"
edd16368
SC		 60
61/* How long to wait (in milliseconds) for board to go into simple mode */
62#define MAX_CONFIG_WAIT 30000
63#define MAX_IOCTL_CONFIG_WAIT 1000
64
65/*define how many times we will try a command because of bus resets */
66#define MAX_CMD_RETRIES 3
67
68/* Embedded module documentation macros - see modules.h */
69MODULE_AUTHOR("Hewlett-Packard Company");
70MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
71 HPSA_DRIVER_VERSION);
72MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
73MODULE_VERSION(HPSA_DRIVER_VERSION);
74MODULE_LICENSE("GPL");
75
76static int hpsa_allow_any;
77module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(hpsa_allow_any,
79 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 80static int hpsa_simple_mode;
81module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_simple_mode,
83 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 84
85/* define the PCI info for the cards we can control */
86static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
7c03b870 122 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 123 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 124 {0,}
125};
126
127MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
128
129/* board_id = Subsystem Device ID & Vendor ID
130 * product = Marketing Name for the board
131 * access = Address of the struct of function pointers
132 */
133static struct board_type products[] = {
edd16368
SC		 134 {0x3241103C, "Smart Array P212", &SA5_access},
135 {0x3243103C, "Smart Array P410", &SA5_access},
136 {0x3245103C, "Smart Array P410i", &SA5_access},
137 {0x3247103C, "Smart Array P411", &SA5_access},
138 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 139 {0x324A103C, "Smart Array P712m", &SA5_access},
140 {0x324B103C, "Smart Array P711m", &SA5_access},
fe0c9610
MM		 141 {0x3350103C, "Smart Array P222", &SA5_access},
142 {0x3351103C, "Smart Array P420", &SA5_access},
143 {0x3352103C, "Smart Array P421", &SA5_access},
144 {0x3353103C, "Smart Array P822", &SA5_access},
145 {0x3354103C, "Smart Array P420i", &SA5_access},
146 {0x3355103C, "Smart Array P220i", &SA5_access},
147 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 148 {0x1921103C, "Smart Array P830i", &SA5_access},
149 {0x1922103C, "Smart Array P430", &SA5_access},
150 {0x1923103C, "Smart Array P431", &SA5_access},
151 {0x1924103C, "Smart Array P830", &SA5_access},
152 {0x1926103C, "Smart Array P731m", &SA5_access},
153 {0x1928103C, "Smart Array P230i", &SA5_access},
154 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 155 {0x21BD103C, "Smart Array", &SA5_access},
156 {0x21BE103C, "Smart Array", &SA5_access},
157 {0x21BF103C, "Smart Array", &SA5_access},
158 {0x21C0103C, "Smart Array", &SA5_access},
159 {0x21C1103C, "Smart Array", &SA5_access},
160 {0x21C2103C, "Smart Array", &SA5_access},
161 {0x21C3103C, "Smart Array", &SA5_access},
162 {0x21C4103C, "Smart Array", &SA5_access},
163 {0x21C5103C, "Smart Array", &SA5_access},
164 {0x21C7103C, "Smart Array", &SA5_access},
165 {0x21C8103C, "Smart Array", &SA5_access},
166 {0x21C9103C, "Smart Array", &SA5_access},
edd16368
SC		 167 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
168};
169
170static int number_of_controllers;
171
10f66018
SC		 172static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
173static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
edd16368
SC		 174static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
175static void start_io(struct ctlr_info *h);
176
177#ifdef CONFIG_COMPAT
178static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
179#endif
180
181static void cmd_free(struct ctlr_info *h, struct CommandList *c);
182static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
183static struct CommandList *cmd_alloc(struct ctlr_info *h);
184static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
a2dac136 185static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
01a02ffc 186 void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
edd16368
SC		 187 int cmd_type);
188
f281233d 189static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 190static void hpsa_scan_start(struct Scsi_Host *);
191static int hpsa_scan_finished(struct Scsi_Host *sh,
192 unsigned long elapsed_time);
667e23d4
SC		 193static int hpsa_change_queue_depth(struct scsi_device *sdev,
194 int qdepth, int reason);
edd16368
SC		 195
196static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 197static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 198static int hpsa_slave_alloc(struct scsi_device *sdev);
199static void hpsa_slave_destroy(struct scsi_device *sdev);
200
edd16368 201static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 202static int check_for_unit_attention(struct ctlr_info *h,
203 struct CommandList *c);
204static void check_ioctl_unit_attention(struct ctlr_info *h,
205 struct CommandList *c);
303932fd
DB		 206/* performant mode helper functions */
207static void calc_bucket_map(int *bucket, int num_buckets,
e1f7de0c 208 int nsgs, int min_blocks, int *bucket_map);
6f039790 209static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 210static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 211static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
212 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
213 u64 *cfg_offset);
214static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
215 unsigned long *memory_bar);
216static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
217static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
218 int wait_for_ready);
75167d2c 219static inline void finish_cmd(struct CommandList *c);
283b4a9b 220static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 221#define BOARD_NOT_READY 0
222#define BOARD_READY 1
edd16368 223
edd16368
SC		 224static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
225{
226 unsigned long *priv = shost_priv(sdev->host);
227 return (struct ctlr_info *) *priv;
228}
229
a23513e8
SC		 230static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
231{
232 unsigned long *priv = shost_priv(sh);
233 return (struct ctlr_info *) *priv;
234}
235
edd16368
SC		 236static int check_for_unit_attention(struct ctlr_info *h,
237 struct CommandList *c)
238{
239 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
240 return 0;
241
242 switch (c->err_info->SenseInfo[12]) {
243 case STATE_CHANGED:
f79cfec6 244 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 245 "detected, command retried\n", h->ctlr);
246 break;
247 case LUN_FAILED:
f79cfec6 248 dev_warn(&h->pdev->dev, HPSA "%d: LUN failure "
edd16368
SC		 249 "detected, action required\n", h->ctlr);
250 break;
251 case REPORT_LUNS_CHANGED:
f79cfec6 252 dev_warn(&h->pdev->dev, HPSA "%d: report LUN data "
31468401 253 "changed, action required\n", h->ctlr);
edd16368 254 /*
4f4eb9f1
ST		 255 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
256 * target (array) devices.
edd16368
SC		 257 */
258 break;
259 case POWER_OR_RESET:
f79cfec6 260 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 261 "or device reset detected\n", h->ctlr);
262 break;
263 case UNIT_ATTENTION_CLEARED:
f79cfec6 264 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 265 "cleared by another initiator\n", h->ctlr);
266 break;
267 default:
f79cfec6 268 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 269 "unit attention detected\n", h->ctlr);
270 break;
271 }
272 return 1;
273}
274
852af20a
MB		 275static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
276{
277 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
278 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
279 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
280 return 0;
281 dev_warn(&h->pdev->dev, HPSA "device busy");
282 return 1;
283}
284
edd16368
SC		 285static ssize_t host_store_rescan(struct device *dev,
286 struct device_attribute *attr,
287 const char *buf, size_t count)
288{
289 struct ctlr_info *h;
290 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 291 h = shost_to_hba(shost);
31468401 292 hpsa_scan_start(h->scsi_host);
edd16368
SC		 293 return count;
294}
295
d28ce020
SC		 296static ssize_t host_show_firmware_revision(struct device *dev,
297 struct device_attribute *attr, char *buf)
298{
299 struct ctlr_info *h;
300 struct Scsi_Host *shost = class_to_shost(dev);
301 unsigned char *fwrev;
302
303 h = shost_to_hba(shost);
304 if (!h->hba_inquiry_data)
305 return 0;
306 fwrev = &h->hba_inquiry_data[32];
307 return snprintf(buf, 20, "%c%c%c%c\n",
308 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
309}
310
94a13649
SC		 311static ssize_t host_show_commands_outstanding(struct device *dev,
312 struct device_attribute *attr, char *buf)
313{
314 struct Scsi_Host *shost = class_to_shost(dev);
315 struct ctlr_info *h = shost_to_hba(shost);
316
317 return snprintf(buf, 20, "%d\n", h->commands_outstanding);
318}
319
745a7a25
SC		 320static ssize_t host_show_transport_mode(struct device *dev,
321 struct device_attribute *attr, char *buf)
322{
323 struct ctlr_info *h;
324 struct Scsi_Host *shost = class_to_shost(dev);
325
326 h = shost_to_hba(shost);
327 return snprintf(buf, 20, "%s\n",
960a30e7 328 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 329 "performant" : "simple");
330}
331
46380786 332/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 333static u32 unresettable_controller[] = {
334 0x324a103C, /* Smart Array P712m */
335 0x324b103C, /* SmartArray P711m */
336 0x3223103C, /* Smart Array P800 */
337 0x3234103C, /* Smart Array P400 */
338 0x3235103C, /* Smart Array P400i */
339 0x3211103C, /* Smart Array E200i */
340 0x3212103C, /* Smart Array E200 */
341 0x3213103C, /* Smart Array E200i */
342 0x3214103C, /* Smart Array E200i */
343 0x3215103C, /* Smart Array E200i */
344 0x3237103C, /* Smart Array E500 */
345 0x323D103C, /* Smart Array P700m */
7af0abbc 346 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 347 0x409C0E11, /* Smart Array 6400 */
348 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 349 0x40700E11, /* Smart Array 5300 */
350 0x40820E11, /* Smart Array 532 */
351 0x40830E11, /* Smart Array 5312 */
352 0x409A0E11, /* Smart Array 641 */
353 0x409B0E11, /* Smart Array 642 */
354 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 355};
356
46380786
SC		 357/* List of controllers which cannot even be soft reset */
358static u32 soft_unresettable_controller[] = {
7af0abbc 359 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 360 0x40700E11, /* Smart Array 5300 */
361 0x40820E11, /* Smart Array 532 */
362 0x40830E11, /* Smart Array 5312 */
363 0x409A0E11, /* Smart Array 641 */
364 0x409B0E11, /* Smart Array 642 */
365 0x40910E11, /* Smart Array 6i */
46380786
SC		 366 /* Exclude 640x boards. These are two pci devices in one slot
367 * which share a battery backed cache module. One controls the
368 * cache, the other accesses the cache through the one that controls
369 * it. If we reset the one controlling the cache, the other will
370 * likely not be happy. Just forbid resetting this conjoined mess.
371 * The 640x isn't really supported by hpsa anyway.
372 */
373 0x409C0E11, /* Smart Array 6400 */
374 0x409D0E11, /* Smart Array 6400 EM */
375};
376
377static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 378{
379 int i;
380
381 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 382 if (unresettable_controller[i] == board_id)
383 return 0;
384 return 1;
385}
386
387static int ctlr_is_soft_resettable(u32 board_id)
388{
389 int i;
390
391 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
392 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 393 return 0;
394 return 1;
395}
396
46380786
SC		 397static int ctlr_is_resettable(u32 board_id)
398{
399 return ctlr_is_hard_resettable(board_id) ||
400 ctlr_is_soft_resettable(board_id);
401}
402
941b1cda
SC		 403static ssize_t host_show_resettable(struct device *dev,
404 struct device_attribute *attr, char *buf)
405{
406 struct ctlr_info *h;
407 struct Scsi_Host *shost = class_to_shost(dev);
408
409 h = shost_to_hba(shost);
46380786 410 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 411}
412
edd16368
SC		 413static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
414{
415 return (scsi3addr[3] & 0xC0) == 0x40;
416}
417
418static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
d82357ea 419 "1(ADM)", "UNKNOWN"
edd16368
SC		 420};
421#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
422
423static ssize_t raid_level_show(struct device *dev,
424 struct device_attribute *attr, char *buf)
425{
426 ssize_t l = 0;
82a72c0a 427 unsigned char rlevel;
edd16368
SC		 428 struct ctlr_info *h;
429 struct scsi_device *sdev;
430 struct hpsa_scsi_dev_t *hdev;
431 unsigned long flags;
432
433 sdev = to_scsi_device(dev);
434 h = sdev_to_hba(sdev);
435 spin_lock_irqsave(&h->lock, flags);
436 hdev = sdev->hostdata;
437 if (!hdev) {
438 spin_unlock_irqrestore(&h->lock, flags);
439 return -ENODEV;
440 }
441
442 /* Is this even a logical drive? */
443 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
444 spin_unlock_irqrestore(&h->lock, flags);
445 l = snprintf(buf, PAGE_SIZE, "N/A\n");
446 return l;
447 }
448
449 rlevel = hdev->raid_level;
450 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 451 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 452 rlevel = RAID_UNKNOWN;
453 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
454 return l;
455}
456
457static ssize_t lunid_show(struct device *dev,
458 struct device_attribute *attr, char *buf)
459{
460 struct ctlr_info *h;
461 struct scsi_device *sdev;
462 struct hpsa_scsi_dev_t *hdev;
463 unsigned long flags;
464 unsigned char lunid[8];
465
466 sdev = to_scsi_device(dev);
467 h = sdev_to_hba(sdev);
468 spin_lock_irqsave(&h->lock, flags);
469 hdev = sdev->hostdata;
470 if (!hdev) {
471 spin_unlock_irqrestore(&h->lock, flags);
472 return -ENODEV;
473 }
474 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
475 spin_unlock_irqrestore(&h->lock, flags);
476 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
477 lunid[0], lunid[1], lunid[2], lunid[3],
478 lunid[4], lunid[5], lunid[6], lunid[7]);
479}
480
481static ssize_t unique_id_show(struct device *dev,
482 struct device_attribute *attr, char *buf)
483{
484 struct ctlr_info *h;
485 struct scsi_device *sdev;
486 struct hpsa_scsi_dev_t *hdev;
487 unsigned long flags;
488 unsigned char sn[16];
489
490 sdev = to_scsi_device(dev);
491 h = sdev_to_hba(sdev);
492 spin_lock_irqsave(&h->lock, flags);
493 hdev = sdev->hostdata;
494 if (!hdev) {
495 spin_unlock_irqrestore(&h->lock, flags);
496 return -ENODEV;
497 }
498 memcpy(sn, hdev->device_id, sizeof(sn));
499 spin_unlock_irqrestore(&h->lock, flags);
500 return snprintf(buf, 16 * 2 + 2,
501 "%02X%02X%02X%02X%02X%02X%02X%02X"
502 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
503 sn[0], sn[1], sn[2], sn[3],
504 sn[4], sn[5], sn[6], sn[7],
505 sn[8], sn[9], sn[10], sn[11],
506 sn[12], sn[13], sn[14], sn[15]);
507}
508
3f5eac3a
SC		 509static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
510static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
511static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
512static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
513static DEVICE_ATTR(firmware_revision, S_IRUGO,
514 host_show_firmware_revision, NULL);
515static DEVICE_ATTR(commands_outstanding, S_IRUGO,
516 host_show_commands_outstanding, NULL);
517static DEVICE_ATTR(transport_mode, S_IRUGO,
518 host_show_transport_mode, NULL);
941b1cda
SC		 519static DEVICE_ATTR(resettable, S_IRUGO,
520 host_show_resettable, NULL);
3f5eac3a
SC		 521
522static struct device_attribute *hpsa_sdev_attrs[] = {
523 &dev_attr_raid_level,
524 &dev_attr_lunid,
525 &dev_attr_unique_id,
526 NULL,
527};
528
529static struct device_attribute *hpsa_shost_attrs[] = {
530 &dev_attr_rescan,
531 &dev_attr_firmware_revision,
532 &dev_attr_commands_outstanding,
533 &dev_attr_transport_mode,
941b1cda 534 &dev_attr_resettable,
3f5eac3a
SC		 535 NULL,
536};
537
538static struct scsi_host_template hpsa_driver_template = {
539 .module = THIS_MODULE,
f79cfec6
SC		 540 .name = HPSA,
541 .proc_name = HPSA,
3f5eac3a
SC		 542 .queuecommand = hpsa_scsi_queue_command,
543 .scan_start = hpsa_scan_start,
544 .scan_finished = hpsa_scan_finished,
545 .change_queue_depth = hpsa_change_queue_depth,
546 .this_id = -1,
547 .use_clustering = ENABLE_CLUSTERING,
75167d2c 548 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 549 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
550 .ioctl = hpsa_ioctl,
551 .slave_alloc = hpsa_slave_alloc,
552 .slave_destroy = hpsa_slave_destroy,
553#ifdef CONFIG_COMPAT
554 .compat_ioctl = hpsa_compat_ioctl,
555#endif
556 .sdev_attrs = hpsa_sdev_attrs,
557 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 558 .max_sectors = 8192,
54b2b50c 559 .no_write_same = 1,
3f5eac3a
SC		 560};
561
562
563/* Enqueuing and dequeuing functions for cmdlists. */
564static inline void addQ(struct list_head *list, struct CommandList *c)
565{
566 list_add_tail(&c->list, list);
567}
568
254f796b 569static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 570{
571 u32 a;
254f796b 572 struct reply_pool *rq = &h->reply_queue[q];
e16a33ad 573 unsigned long flags;
3f5eac3a 574
e1f7de0c
MG		 575 if (h->transMethod & CFGTBL_Trans_io_accel1)
576 return h->access.command_completed(h, q);
577
3f5eac3a 578 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 579 return h->access.command_completed(h, q);
3f5eac3a 580
254f796b
MG		 581 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
582 a = rq->head[rq->current_entry];
583 rq->current_entry++;
e16a33ad 584 spin_lock_irqsave(&h->lock, flags);
3f5eac3a 585 h->commands_outstanding--;
e16a33ad 586 spin_unlock_irqrestore(&h->lock, flags);
3f5eac3a
SC		 587 } else {
588 a = FIFO_EMPTY;
589 }
590 /* Check for wraparound */
254f796b
MG		 591 if (rq->current_entry == h->max_commands) {
592 rq->current_entry = 0;
593 rq->wraparound ^= 1;
3f5eac3a
SC		 594 }
595 return a;
596}
597
598/* set_performant_mode: Modify the tag for cciss performant
599 * set bit 0 for pull model, bits 3-1 for block fetch
600 * register number
601 */
602static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
603{
254f796b 604 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 605 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 606 if (likely(h->msix_vector > 0))
254f796b 607 c->Header.ReplyQueue =
804a5cb5 608 raw_smp_processor_id() % h->nreply_queues;
254f796b 609 }
3f5eac3a
SC		 610}
611
e85c5974
SC		 612static int is_firmware_flash_cmd(u8 *cdb)
613{
614 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
615}
616
617/*
618 * During firmware flash, the heartbeat register may not update as frequently
619 * as it should. So we dial down lockup detection during firmware flash. and
620 * dial it back up when firmware flash completes.
621 */
622#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
623#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
624static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
625 struct CommandList *c)
626{
627 if (!is_firmware_flash_cmd(c->Request.CDB))
628 return;
629 atomic_inc(&h->firmware_flash_in_progress);
630 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
631}
632
633static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
634 struct CommandList *c)
635{
636 if (is_firmware_flash_cmd(c->Request.CDB) &&
637 atomic_dec_and_test(&h->firmware_flash_in_progress))
638 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
639}
640
3f5eac3a
SC		 641static void enqueue_cmd_and_start_io(struct ctlr_info *h,
642 struct CommandList *c)
643{
644 unsigned long flags;
645
646 set_performant_mode(h, c);
e85c5974 647 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 648 spin_lock_irqsave(&h->lock, flags);
649 addQ(&h->reqQ, c);
650 h->Qdepth++;
3f5eac3a 651 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 652 start_io(h);
3f5eac3a
SC		 653}
654
655static inline void removeQ(struct CommandList *c)
656{
657 if (WARN_ON(list_empty(&c->list)))
658 return;
659 list_del_init(&c->list);
660}
661
662static inline int is_hba_lunid(unsigned char scsi3addr[])
663{
664 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
665}
666
667static inline int is_scsi_rev_5(struct ctlr_info *h)
668{
669 if (!h->hba_inquiry_data)
670 return 0;
671 if ((h->hba_inquiry_data[2] & 0x07) == 5)
672 return 1;
673 return 0;
674}
675
edd16368
SC		 676static int hpsa_find_target_lun(struct ctlr_info *h,
677 unsigned char scsi3addr[], int bus, int *target, int *lun)
678{
679 /* finds an unused bus, target, lun for a new physical device
680 * assumes h->devlock is held
681 */
682 int i, found = 0;
cfe5badc 683 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 684
263d9401 685 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 686
687 for (i = 0; i < h->ndevices; i++) {
688 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 689 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 690 }
691
263d9401
AM		 692 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
693 if (i < HPSA_MAX_DEVICES) {
694 /* *bus = 1; */
695 *target = i;
696 *lun = 0;
697 found = 1;
edd16368
SC		 698 }
699 return !found;
700}
701
702/* Add an entry into h->dev[] array. */
703static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
704 struct hpsa_scsi_dev_t *device,
705 struct hpsa_scsi_dev_t *added[], int *nadded)
706{
707 /* assumes h->devlock is held */
708 int n = h->ndevices;
709 int i;
710 unsigned char addr1[8], addr2[8];
711 struct hpsa_scsi_dev_t *sd;
712
cfe5badc 713 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 714 dev_err(&h->pdev->dev, "too many devices, some will be "
715 "inaccessible.\n");
716 return -1;
717 }
718
719 /* physical devices do not have lun or target assigned until now. */
720 if (device->lun != -1)
721 /* Logical device, lun is already assigned. */
722 goto lun_assigned;
723
724 /* If this device a non-zero lun of a multi-lun device
725 * byte 4 of the 8-byte LUN addr will contain the logical
726 * unit no, zero otherise.
727 */
728 if (device->scsi3addr[4] == 0) {
729 /* This is not a non-zero lun of a multi-lun device */
730 if (hpsa_find_target_lun(h, device->scsi3addr,
731 device->bus, &device->target, &device->lun) != 0)
732 return -1;
733 goto lun_assigned;
734 }
735
736 /* This is a non-zero lun of a multi-lun device.
737 * Search through our list and find the device which
738 * has the same 8 byte LUN address, excepting byte 4.
739 * Assign the same bus and target for this new LUN.
740 * Use the logical unit number from the firmware.
741 */
742 memcpy(addr1, device->scsi3addr, 8);
743 addr1[4] = 0;
744 for (i = 0; i < n; i++) {
745 sd = h->dev[i];
746 memcpy(addr2, sd->scsi3addr, 8);
747 addr2[4] = 0;
748 /* differ only in byte 4? */
749 if (memcmp(addr1, addr2, 8) == 0) {
750 device->bus = sd->bus;
751 device->target = sd->target;
752 device->lun = device->scsi3addr[4];
753 break;
754 }
755 }
756 if (device->lun == -1) {
757 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
758 " suspect firmware bug or unsupported hardware "
759 "configuration.\n");
760 return -1;
761 }
762
763lun_assigned:
764
765 h->dev[n] = device;
766 h->ndevices++;
767 added[*nadded] = device;
768 (*nadded)++;
769
770 /* initially, (before registering with scsi layer) we don't
771 * know our hostno and we don't want to print anything first
772 * time anyway (the scsi layer's inquiries will show that info)
773 */
774 /* if (hostno != -1) */
775 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
776 scsi_device_type(device->devtype), hostno,
777 device->bus, device->target, device->lun);
778 return 0;
779}
780
bd9244f7
ST		 781/* Update an entry in h->dev[] array. */
782static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
783 int entry, struct hpsa_scsi_dev_t *new_entry)
784{
785 /* assumes h->devlock is held */
786 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
787
788 /* Raid level changed. */
789 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 790
791 /* Raid offload parameters changed. */
792 h->dev[entry]->offload_config = new_entry->offload_config;
793 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
794
bd9244f7
ST		 795 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
796 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
797 new_entry->target, new_entry->lun);
798}
799
2a8ccf31
SC		 800/* Replace an entry from h->dev[] array. */
801static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
802 int entry, struct hpsa_scsi_dev_t *new_entry,
803 struct hpsa_scsi_dev_t *added[], int *nadded,
804 struct hpsa_scsi_dev_t *removed[], int *nremoved)
805{
806 /* assumes h->devlock is held */
cfe5badc 807 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 808 removed[*nremoved] = h->dev[entry];
809 (*nremoved)++;
01350d05
SC		 810
811 /*
812 * New physical devices won't have target/lun assigned yet
813 * so we need to preserve the values in the slot we are replacing.
814 */
815 if (new_entry->target == -1) {
816 new_entry->target = h->dev[entry]->target;
817 new_entry->lun = h->dev[entry]->lun;
818 }
819
2a8ccf31
SC		 820 h->dev[entry] = new_entry;
821 added[*nadded] = new_entry;
822 (*nadded)++;
823 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
824 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
825 new_entry->target, new_entry->lun);
826}
827
edd16368
SC		 828/* Remove an entry from h->dev[] array. */
829static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
830 struct hpsa_scsi_dev_t *removed[], int *nremoved)
831{
832 /* assumes h->devlock is held */
833 int i;
834 struct hpsa_scsi_dev_t *sd;
835
cfe5badc 836 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 837
838 sd = h->dev[entry];
839 removed[*nremoved] = h->dev[entry];
840 (*nremoved)++;
841
842 for (i = entry; i < h->ndevices-1; i++)
843 h->dev[i] = h->dev[i+1];
844 h->ndevices--;
845 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
846 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
847 sd->lun);
848}
849
850#define SCSI3ADDR_EQ(a, b) ( \
851 (a)[7] == (b)[7] && \
852 (a)[6] == (b)[6] && \
853 (a)[5] == (b)[5] && \
854 (a)[4] == (b)[4] && \
855 (a)[3] == (b)[3] && \
856 (a)[2] == (b)[2] && \
857 (a)[1] == (b)[1] && \
858 (a)[0] == (b)[0])
859
860static void fixup_botched_add(struct ctlr_info *h,
861 struct hpsa_scsi_dev_t *added)
862{
863 /* called when scsi_add_device fails in order to re-adjust
864 * h->dev[] to match the mid layer's view.
865 */
866 unsigned long flags;
867 int i, j;
868
869 spin_lock_irqsave(&h->lock, flags);
870 for (i = 0; i < h->ndevices; i++) {
871 if (h->dev[i] == added) {
872 for (j = i; j < h->ndevices-1; j++)
873 h->dev[j] = h->dev[j+1];
874 h->ndevices--;
875 break;
876 }
877 }
878 spin_unlock_irqrestore(&h->lock, flags);
879 kfree(added);
880}
881
882static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
883 struct hpsa_scsi_dev_t *dev2)
884{
edd16368
SC		 885 /* we compare everything except lun and target as these
886 * are not yet assigned. Compare parts likely
887 * to differ first
888 */
889 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
890 sizeof(dev1->scsi3addr)) != 0)
891 return 0;
892 if (memcmp(dev1->device_id, dev2->device_id,
893 sizeof(dev1->device_id)) != 0)
894 return 0;
895 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
896 return 0;
897 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
898 return 0;
edd16368
SC		 899 if (dev1->devtype != dev2->devtype)
900 return 0;
edd16368
SC		 901 if (dev1->bus != dev2->bus)
902 return 0;
903 return 1;
904}
905
bd9244f7
ST		 906static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
907 struct hpsa_scsi_dev_t *dev2)
908{
909 /* Device attributes that can change, but don't mean
910 * that the device is a different device, nor that the OS
911 * needs to be told anything about the change.
912 */
913 if (dev1->raid_level != dev2->raid_level)
914 return 1;
250fb125
SC		 915 if (dev1->offload_config != dev2->offload_config)
916 return 1;
917 if (dev1->offload_enabled != dev2->offload_enabled)
918 return 1;
bd9244f7
ST		 919 return 0;
920}
921
edd16368
SC		 922/* Find needle in haystack. If exact match found, return DEVICE_SAME,
923 * and return needle location in *index. If scsi3addr matches, but not
924 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 925 * location in *index.
926 * In the case of a minor device attribute change, such as RAID level, just
927 * return DEVICE_UPDATED, along with the updated device's location in index.
928 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 929 */
930static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
931 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
932 int *index)
933{
934 int i;
935#define DEVICE_NOT_FOUND 0
936#define DEVICE_CHANGED 1
937#define DEVICE_SAME 2
bd9244f7 938#define DEVICE_UPDATED 3
edd16368 939 for (i = 0; i < haystack_size; i++) {
23231048
SC		 940 if (haystack[i] == NULL) /* previously removed. */
941 continue;
edd16368
SC		 942 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
943 *index = i;
bd9244f7
ST		 944 if (device_is_the_same(needle, haystack[i])) {
945 if (device_updated(needle, haystack[i]))
946 return DEVICE_UPDATED;
edd16368 947 return DEVICE_SAME;
bd9244f7 948 } else {
edd16368 949 return DEVICE_CHANGED;
bd9244f7 950 }
edd16368
SC		 951 }
952 }
953 *index = -1;
954 return DEVICE_NOT_FOUND;
955}
956
4967bd3e 957static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 958 struct hpsa_scsi_dev_t *sd[], int nsds)
959{
960 /* sd contains scsi3 addresses and devtypes, and inquiry
961 * data. This function takes what's in sd to be the current
962 * reality and updates h->dev[] to reflect that reality.
963 */
964 int i, entry, device_change, changes = 0;
965 struct hpsa_scsi_dev_t *csd;
966 unsigned long flags;
967 struct hpsa_scsi_dev_t **added, **removed;
968 int nadded, nremoved;
969 struct Scsi_Host *sh = NULL;
970
cfe5badc
ST		 971 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
972 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 973
974 if (!added || !removed) {
975 dev_warn(&h->pdev->dev, "out of memory in "
976 "adjust_hpsa_scsi_table\n");
977 goto free_and_out;
978 }
979
980 spin_lock_irqsave(&h->devlock, flags);
981
982 /* find any devices in h->dev[] that are not in
983 * sd[] and remove them from h->dev[], and for any
984 * devices which have changed, remove the old device
985 * info and add the new device info.
bd9244f7
ST		 986 * If minor device attributes change, just update
987 * the existing device structure.
edd16368
SC		 988 */
989 i = 0;
990 nremoved = 0;
991 nadded = 0;
992 while (i < h->ndevices) {
993 csd = h->dev[i];
994 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
995 if (device_change == DEVICE_NOT_FOUND) {
996 changes++;
997 hpsa_scsi_remove_entry(h, hostno, i,
998 removed, &nremoved);
999 continue; /* remove ^^^, hence i not incremented */
1000 } else if (device_change == DEVICE_CHANGED) {
1001 changes++;
2a8ccf31
SC		 1002 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1003 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1004 /* Set it to NULL to prevent it from being freed
1005 * at the bottom of hpsa_update_scsi_devices()
1006 */
1007 sd[entry] = NULL;
bd9244f7
ST		 1008 } else if (device_change == DEVICE_UPDATED) {
1009 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1010 }
1011 i++;
1012 }
1013
1014 /* Now, make sure every device listed in sd[] is also
1015 * listed in h->dev[], adding them if they aren't found
1016 */
1017
1018 for (i = 0; i < nsds; i++) {
1019 if (!sd[i]) /* if already added above. */
1020 continue;
1021 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1022 h->ndevices, &entry);
1023 if (device_change == DEVICE_NOT_FOUND) {
1024 changes++;
1025 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1026 added, &nadded) != 0)
1027 break;
1028 sd[i] = NULL; /* prevent from being freed later. */
1029 } else if (device_change == DEVICE_CHANGED) {
1030 /* should never happen... */
1031 changes++;
1032 dev_warn(&h->pdev->dev,
1033 "device unexpectedly changed.\n");
1034 /* but if it does happen, we just ignore that device */
1035 }
1036 }
1037 spin_unlock_irqrestore(&h->devlock, flags);
1038
1039 /* Don't notify scsi mid layer of any changes the first time through
1040 * (or if there are no changes) scsi_scan_host will do it later the
1041 * first time through.
1042 */
1043 if (hostno == -1 || !changes)
1044 goto free_and_out;
1045
1046 sh = h->scsi_host;
1047 /* Notify scsi mid layer of any removed devices */
1048 for (i = 0; i < nremoved; i++) {
1049 struct scsi_device *sdev =
1050 scsi_device_lookup(sh, removed[i]->bus,
1051 removed[i]->target, removed[i]->lun);
1052 if (sdev != NULL) {
1053 scsi_remove_device(sdev);
1054 scsi_device_put(sdev);
1055 } else {
1056 /* We don't expect to get here.
1057 * future cmds to this device will get selection
1058 * timeout as if the device was gone.
1059 */
1060 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1061 " for removal.", hostno, removed[i]->bus,
1062 removed[i]->target, removed[i]->lun);
1063 }
1064 kfree(removed[i]);
1065 removed[i] = NULL;
1066 }
1067
1068 /* Notify scsi mid layer of any added devices */
1069 for (i = 0; i < nadded; i++) {
1070 if (scsi_add_device(sh, added[i]->bus,
1071 added[i]->target, added[i]->lun) == 0)
1072 continue;
1073 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1074 "device not added.\n", hostno, added[i]->bus,
1075 added[i]->target, added[i]->lun);
1076 /* now we have to remove it from h->dev,
1077 * since it didn't get added to scsi mid layer
1078 */
1079 fixup_botched_add(h, added[i]);
1080 }
1081
1082free_and_out:
1083 kfree(added);
1084 kfree(removed);
edd16368
SC		 1085}
1086
1087/*
9e03aa2f 1088 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1089 * Assume's h->devlock is held.
1090 */
1091static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1092 int bus, int target, int lun)
1093{
1094 int i;
1095 struct hpsa_scsi_dev_t *sd;
1096
1097 for (i = 0; i < h->ndevices; i++) {
1098 sd = h->dev[i];
1099 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1100 return sd;
1101 }
1102 return NULL;
1103}
1104
1105/* link sdev->hostdata to our per-device structure. */
1106static int hpsa_slave_alloc(struct scsi_device *sdev)
1107{
1108 struct hpsa_scsi_dev_t *sd;
1109 unsigned long flags;
1110 struct ctlr_info *h;
1111
1112 h = sdev_to_hba(sdev);
1113 spin_lock_irqsave(&h->devlock, flags);
1114 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1115 sdev_id(sdev), sdev->lun);
1116 if (sd != NULL)
1117 sdev->hostdata = sd;
1118 spin_unlock_irqrestore(&h->devlock, flags);
1119 return 0;
1120}
1121
1122static void hpsa_slave_destroy(struct scsi_device *sdev)
1123{
bcc44255 1124 /* nothing to do. */
edd16368
SC		 1125}
1126
33a2ffce
SC		 1127static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1128{
1129 int i;
1130
1131 if (!h->cmd_sg_list)
1132 return;
1133 for (i = 0; i < h->nr_cmds; i++) {
1134 kfree(h->cmd_sg_list[i]);
1135 h->cmd_sg_list[i] = NULL;
1136 }
1137 kfree(h->cmd_sg_list);
1138 h->cmd_sg_list = NULL;
1139}
1140
1141static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1142{
1143 int i;
1144
1145 if (h->chainsize <= 0)
1146 return 0;
1147
1148 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1149 GFP_KERNEL);
1150 if (!h->cmd_sg_list)
1151 return -ENOMEM;
1152 for (i = 0; i < h->nr_cmds; i++) {
1153 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1154 h->chainsize, GFP_KERNEL);
1155 if (!h->cmd_sg_list[i])
1156 goto clean;
1157 }
1158 return 0;
1159
1160clean:
1161 hpsa_free_sg_chain_blocks(h);
1162 return -ENOMEM;
1163}
1164
e2bea6df 1165static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1166 struct CommandList *c)
1167{
1168 struct SGDescriptor *chain_sg, *chain_block;
1169 u64 temp64;
1170
1171 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1172 chain_block = h->cmd_sg_list[c->cmdindex];
1173 chain_sg->Ext = HPSA_SG_CHAIN;
1174 chain_sg->Len = sizeof(*chain_sg) *
1175 (c->Header.SGTotal - h->max_cmd_sg_entries);
1176 temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
1177 PCI_DMA_TODEVICE);
e2bea6df
SC		 1178 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1179 /* prevent subsequent unmapping */
1180 chain_sg->Addr.lower = 0;
1181 chain_sg->Addr.upper = 0;
1182 return -1;
1183 }
33a2ffce
SC		 1184 chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
1185 chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
e2bea6df 1186 return 0;
33a2ffce
SC		 1187}
1188
1189static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1190 struct CommandList *c)
1191{
1192 struct SGDescriptor *chain_sg;
1193 union u64bit temp64;
1194
1195 if (c->Header.SGTotal <= h->max_cmd_sg_entries)
1196 return;
1197
1198 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1199 temp64.val32.lower = chain_sg->Addr.lower;
1200 temp64.val32.upper = chain_sg->Addr.upper;
1201 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
1202}
1203
1fb011fb 1204static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1205{
1206 struct scsi_cmnd *cmd;
1207 struct ctlr_info *h;
1208 struct ErrorInfo *ei;
283b4a9b 1209 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1210
1211 unsigned char sense_key;
1212 unsigned char asc; /* additional sense code */
1213 unsigned char ascq; /* additional sense code qualifier */
db111e18 1214 unsigned long sense_data_size;
edd16368
SC		 1215
1216 ei = cp->err_info;
1217 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1218 h = cp->h;
283b4a9b 1219 dev = cmd->device->hostdata;
edd16368
SC		 1220
1221 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c
MG		 1222 if ((cp->cmd_type == CMD_SCSI) &&
1223 (cp->Header.SGTotal > h->max_cmd_sg_entries))
33a2ffce 1224 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1225
1226 cmd->result = (DID_OK << 16); /* host byte */
1227 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
5512672f 1228 cmd->result |= ei->ScsiStatus;
edd16368
SC		 1229
1230 /* copy the sense data whether we need to or not. */
db111e18
SC		 1231 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1232 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1233 else
1234 sense_data_size = sizeof(ei->SenseInfo);
1235 if (ei->SenseLen < sense_data_size)
1236 sense_data_size = ei->SenseLen;
1237
1238 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368
SC		 1239 scsi_set_resid(cmd, ei->ResidualCnt);
1240
1241 if (ei->CommandStatus == 0) {
edd16368 1242 cmd_free(h, cp);
2cc5bfaf 1243 cmd->scsi_done(cmd);
edd16368
SC		 1244 return;
1245 }
1246
e1f7de0c
MG		 1247 /* For I/O accelerator commands, copy over some fields to the normal
1248 * CISS header used below for error handling.
1249 */
1250 if (cp->cmd_type == CMD_IOACCEL1) {
1251 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
1252 cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd);
1253 cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK;
1254 cp->Header.Tag.lower = c->Tag.lower;
1255 cp->Header.Tag.upper = c->Tag.upper;
1256 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1257 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1258
1259 /* Any RAID offload error results in retry which will use
1260 * the normal I/O path so the controller can handle whatever's
1261 * wrong.
1262 */
1263 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1264 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1265 dev->offload_enabled = 0;
1266 cmd->result = DID_SOFT_ERROR << 16;
1267 cmd_free(h, cp);
1268 cmd->scsi_done(cmd);
1269 return;
1270 }
e1f7de0c
MG		 1271 }
1272
edd16368
SC		 1273 /* an error has occurred */
1274 switch (ei->CommandStatus) {
1275
1276 case CMD_TARGET_STATUS:
1277 if (ei->ScsiStatus) {
1278 /* Get sense key */
1279 sense_key = 0xf & ei->SenseInfo[2];
1280 /* Get additional sense code */
1281 asc = ei->SenseInfo[12];
1282 /* Get addition sense code qualifier */
1283 ascq = ei->SenseInfo[13];
1284 }
1285
1286 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
3ce438df 1287 if (check_for_unit_attention(h, cp))
edd16368 1288 break;
edd16368
SC		 1289 if (sense_key == ILLEGAL_REQUEST) {
1290 /*
1291 * SCSI REPORT_LUNS is commonly unsupported on
1292 * Smart Array. Suppress noisy complaint.
1293 */
1294 if (cp->Request.CDB[0] == REPORT_LUNS)
1295 break;
1296
1297 /* If ASC/ASCQ indicate Logical Unit
1298 * Not Supported condition,
1299 */
1300 if ((asc == 0x25) && (ascq == 0x0)) {
1301 dev_warn(&h->pdev->dev, "cp %p "
1302 "has check condition\n", cp);
1303 break;
1304 }
1305 }
1306
1307 if (sense_key == NOT_READY) {
1308 /* If Sense is Not Ready, Logical Unit
1309 * Not ready, Manual Intervention
1310 * required
1311 */
1312 if ((asc == 0x04) && (ascq == 0x03)) {
edd16368
SC		 1313 dev_warn(&h->pdev->dev, "cp %p "
1314 "has check condition: unit "
1315 "not ready, manual "
1316 "intervention required\n", cp);
1317 break;
1318 }
1319 }
1d3b3609
MG		 1320 if (sense_key == ABORTED_COMMAND) {
1321 /* Aborted command is retryable */
1322 dev_warn(&h->pdev->dev, "cp %p "
1323 "has check condition: aborted command: "
1324 "ASC: 0x%x, ASCQ: 0x%x\n",
1325 cp, asc, ascq);
2e311fba 1326 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1327 break;
1328 }
edd16368 1329 /* Must be some other type of check condition */
21b8e4ef 1330 dev_dbg(&h->pdev->dev, "cp %p has check condition: "
edd16368
SC		 1331 "unknown type: "
1332 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1333 "Returning result: 0x%x, "
1334 "cmd=[%02x %02x %02x %02x %02x "
807be732 1335 "%02x %02x %02x %02x %02x %02x "
edd16368
SC		 1336 "%02x %02x %02x %02x %02x]\n",
1337 cp, sense_key, asc, ascq,
1338 cmd->result,
1339 cmd->cmnd[0], cmd->cmnd[1],
1340 cmd->cmnd[2], cmd->cmnd[3],
1341 cmd->cmnd[4], cmd->cmnd[5],
1342 cmd->cmnd[6], cmd->cmnd[7],
807be732
MM		 1343 cmd->cmnd[8], cmd->cmnd[9],
1344 cmd->cmnd[10], cmd->cmnd[11],
1345 cmd->cmnd[12], cmd->cmnd[13],
1346 cmd->cmnd[14], cmd->cmnd[15]);
edd16368
SC		 1347 break;
1348 }
1349
1350
1351 /* Problem was not a check condition
1352 * Pass it up to the upper layers...
1353 */
1354 if (ei->ScsiStatus) {
1355 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1356 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1357 "Returning result: 0x%x\n",
1358 cp, ei->ScsiStatus,
1359 sense_key, asc, ascq,
1360 cmd->result);
1361 } else { /* scsi status is zero??? How??? */
1362 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1363 "Returning no connection.\n", cp),
1364
1365 /* Ordinarily, this case should never happen,
1366 * but there is a bug in some released firmware
1367 * revisions that allows it to happen if, for
1368 * example, a 4100 backplane loses power and
1369 * the tape drive is in it. We assume that
1370 * it's a fatal error of some kind because we
1371 * can't show that it wasn't. We will make it
1372 * look like selection timeout since that is
1373 * the most common reason for this to occur,
1374 * and it's severe enough.
1375 */
1376
1377 cmd->result = DID_NO_CONNECT << 16;
1378 }
1379 break;
1380
1381 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1382 break;
1383 case CMD_DATA_OVERRUN:
1384 dev_warn(&h->pdev->dev, "cp %p has"
1385 " completed with data overrun "
1386 "reported\n", cp);
1387 break;
1388 case CMD_INVALID: {
1389 /* print_bytes(cp, sizeof(*cp), 1, 0);
1390 print_cmd(cp); */
1391 /* We get CMD_INVALID if you address a non-existent device
1392 * instead of a selection timeout (no response). You will
1393 * see this if you yank out a drive, then try to access it.
1394 * This is kind of a shame because it means that any other
1395 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1396 * missing target. */
1397 cmd->result = DID_NO_CONNECT << 16;
1398 }
1399 break;
1400 case CMD_PROTOCOL_ERR:
256d0eaa 1401 cmd->result = DID_ERROR << 16;
edd16368 1402 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1403 "protocol error\n", cp);
edd16368
SC		 1404 break;
1405 case CMD_HARDWARE_ERR:
1406 cmd->result = DID_ERROR << 16;
1407 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1408 break;
1409 case CMD_CONNECTION_LOST:
1410 cmd->result = DID_ERROR << 16;
1411 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1412 break;
1413 case CMD_ABORTED:
1414 cmd->result = DID_ABORT << 16;
1415 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1416 cp, ei->ScsiStatus);
1417 break;
1418 case CMD_ABORT_FAILED:
1419 cmd->result = DID_ERROR << 16;
1420 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1421 break;
1422 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1423 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1424 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1425 "abort\n", cp);
1426 break;
1427 case CMD_TIMEOUT:
1428 cmd->result = DID_TIME_OUT << 16;
1429 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1430 break;
1d5e2ed0
SC		 1431 case CMD_UNABORTABLE:
1432 cmd->result = DID_ERROR << 16;
1433 dev_warn(&h->pdev->dev, "Command unabortable\n");
1434 break;
283b4a9b
SC		 1435 case CMD_IOACCEL_DISABLED:
1436 /* This only handles the direct pass-through case since RAID
1437 * offload is handled above. Just attempt a retry.
1438 */
1439 cmd->result = DID_SOFT_ERROR << 16;
1440 dev_warn(&h->pdev->dev,
1441 "cp %p had HP SSD Smart Path error\n", cp);
1442 break;
edd16368
SC		 1443 default:
1444 cmd->result = DID_ERROR << 16;
1445 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1446 cp, ei->CommandStatus);
1447 }
edd16368 1448 cmd_free(h, cp);
2cc5bfaf 1449 cmd->scsi_done(cmd);
edd16368
SC		 1450}
1451
edd16368
SC		 1452static void hpsa_pci_unmap(struct pci_dev *pdev,
1453 struct CommandList *c, int sg_used, int data_direction)
1454{
1455 int i;
1456 union u64bit addr64;
1457
1458 for (i = 0; i < sg_used; i++) {
1459 addr64.val32.lower = c->SG[i].Addr.lower;
1460 addr64.val32.upper = c->SG[i].Addr.upper;
1461 pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
1462 data_direction);
1463 }
1464}
1465
a2dac136 1466static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1467 struct CommandList *cp,
1468 unsigned char *buf,
1469 size_t buflen,
1470 int data_direction)
1471{
01a02ffc 1472 u64 addr64;
edd16368
SC		 1473
1474 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1475 cp->Header.SGList = 0;
1476 cp->Header.SGTotal = 0;
a2dac136 1477 return 0;
edd16368
SC		 1478 }
1479
01a02ffc 1480 addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1481 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1482 /* Prevent subsequent unmap of something never mapped */
eceaae18
SK		 1483 cp->Header.SGList = 0;
1484 cp->Header.SGTotal = 0;
a2dac136 1485 return -1;
eceaae18 1486 }
edd16368 1487 cp->SG[0].Addr.lower =
01a02ffc 1488 (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
edd16368 1489 cp->SG[0].Addr.upper =
01a02ffc 1490 (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
edd16368 1491 cp->SG[0].Len = buflen;
e1d9cbfa 1492 cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */
01a02ffc
SC		 1493 cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
1494 cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
a2dac136 1495 return 0;
edd16368
SC		 1496}
1497
1498static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1499 struct CommandList *c)
1500{
1501 DECLARE_COMPLETION_ONSTACK(wait);
1502
1503 c->waiting = &wait;
1504 enqueue_cmd_and_start_io(h, c);
1505 wait_for_completion(&wait);
1506}
1507
a0c12413
SC		 1508static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1509 struct CommandList *c)
1510{
1511 unsigned long flags;
1512
1513 /* If controller lockup detected, fake a hardware error. */
1514 spin_lock_irqsave(&h->lock, flags);
1515 if (unlikely(h->lockup_detected)) {
1516 spin_unlock_irqrestore(&h->lock, flags);
1517 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
1518 } else {
1519 spin_unlock_irqrestore(&h->lock, flags);
1520 hpsa_scsi_do_simple_cmd_core(h, c);
1521 }
1522}
1523
9c2fc160 1524#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 1525static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
1526 struct CommandList *c, int data_direction)
1527{
9c2fc160 1528 int backoff_time = 10, retry_count = 0;
edd16368
SC		 1529
1530 do {
7630abd0 1531 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 1532 hpsa_scsi_do_simple_cmd_core(h, c);
1533 retry_count++;
9c2fc160
SC		 1534 if (retry_count > 3) {
1535 msleep(backoff_time);
1536 if (backoff_time < 1000)
1537 backoff_time *= 2;
1538 }
852af20a 1539 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 1540 check_for_busy(h, c)) &&
1541 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 1542 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
1543}
1544
1545static void hpsa_scsi_interpret_error(struct CommandList *cp)
1546{
1547 struct ErrorInfo *ei;
1548 struct device *d = &cp->h->pdev->dev;
1549
1550 ei = cp->err_info;
1551 switch (ei->CommandStatus) {
1552 case CMD_TARGET_STATUS:
1553 dev_warn(d, "cmd %p has completed with errors\n", cp);
1554 dev_warn(d, "cmd %p has SCSI Status = %x\n", cp,
1555 ei->ScsiStatus);
1556 if (ei->ScsiStatus == 0)
1557 dev_warn(d, "SCSI status is abnormally zero. "
1558 "(probably indicates selection timeout "
1559 "reported incorrectly due to a known "
1560 "firmware bug, circa July, 2001.)\n");
1561 break;
1562 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1563 dev_info(d, "UNDERRUN\n");
1564 break;
1565 case CMD_DATA_OVERRUN:
1566 dev_warn(d, "cp %p has completed with data overrun\n", cp);
1567 break;
1568 case CMD_INVALID: {
1569 /* controller unfortunately reports SCSI passthru's
1570 * to non-existent targets as invalid commands.
1571 */
1572 dev_warn(d, "cp %p is reported invalid (probably means "
1573 "target device no longer present)\n", cp);
1574 /* print_bytes((unsigned char *) cp, sizeof(*cp), 1, 0);
1575 print_cmd(cp); */
1576 }
1577 break;
1578 case CMD_PROTOCOL_ERR:
1579 dev_warn(d, "cp %p has protocol error \n", cp);
1580 break;
1581 case CMD_HARDWARE_ERR:
1582 /* cmd->result = DID_ERROR << 16; */
1583 dev_warn(d, "cp %p had hardware error\n", cp);
1584 break;
1585 case CMD_CONNECTION_LOST:
1586 dev_warn(d, "cp %p had connection lost\n", cp);
1587 break;
1588 case CMD_ABORTED:
1589 dev_warn(d, "cp %p was aborted\n", cp);
1590 break;
1591 case CMD_ABORT_FAILED:
1592 dev_warn(d, "cp %p reports abort failed\n", cp);
1593 break;
1594 case CMD_UNSOLICITED_ABORT:
1595 dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp);
1596 break;
1597 case CMD_TIMEOUT:
1598 dev_warn(d, "cp %p timed out\n", cp);
1599 break;
1d5e2ed0
SC		 1600 case CMD_UNABORTABLE:
1601 dev_warn(d, "Command unabortable\n");
1602 break;
edd16368
SC		 1603 default:
1604 dev_warn(d, "cp %p returned unknown status %x\n", cp,
1605 ei->CommandStatus);
1606 }
1607}
1608
1609static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
1610 unsigned char page, unsigned char *buf,
1611 unsigned char bufsize)
1612{
1613 int rc = IO_OK;
1614 struct CommandList *c;
1615 struct ErrorInfo *ei;
1616
1617 c = cmd_special_alloc(h);
1618
1619 if (c == NULL) { /* trouble... */
1620 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
ecd9aad4 1621 return -ENOMEM;
edd16368
SC		 1622 }
1623
a2dac136
SC		 1624 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
1625 page, scsi3addr, TYPE_CMD)) {
1626 rc = -1;
1627 goto out;
1628 }
edd16368
SC		 1629 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
1630 ei = c->err_info;
1631 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
1632 hpsa_scsi_interpret_error(c);
1633 rc = -1;
1634 }
a2dac136 1635out:
edd16368
SC		 1636 cmd_special_free(h, c);
1637 return rc;
1638}
1639
1640static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr)
1641{
1642 int rc = IO_OK;
1643 struct CommandList *c;
1644 struct ErrorInfo *ei;
1645
1646 c = cmd_special_alloc(h);
1647
1648 if (c == NULL) { /* trouble... */
1649 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
e9ea04a6 1650 return -ENOMEM;
edd16368
SC		 1651 }
1652
a2dac136
SC		 1653 /* fill_cmd can't fail here, no data buffer to map. */
1654 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h,
1655 NULL, 0, 0, scsi3addr, TYPE_MSG);
edd16368
SC		 1656 hpsa_scsi_do_simple_cmd_core(h, c);
1657 /* no unmap needed here because no data xfer. */
1658
1659 ei = c->err_info;
1660 if (ei->CommandStatus != 0) {
1661 hpsa_scsi_interpret_error(c);
1662 rc = -1;
1663 }
1664 cmd_special_free(h, c);
1665 return rc;
1666}
1667
1668static void hpsa_get_raid_level(struct ctlr_info *h,
1669 unsigned char *scsi3addr, unsigned char *raid_level)
1670{
1671 int rc;
1672 unsigned char *buf;
1673
1674 *raid_level = RAID_UNKNOWN;
1675 buf = kzalloc(64, GFP_KERNEL);
1676 if (!buf)
1677 return;
1678 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0xC1, buf, 64);
1679 if (rc == 0)
1680 *raid_level = buf[8];
1681 if (*raid_level > RAID_UNKNOWN)
1682 *raid_level = RAID_UNKNOWN;
1683 kfree(buf);
1684 return;
1685}
1686
283b4a9b
SC		 1687#define HPSA_MAP_DEBUG
1688#ifdef HPSA_MAP_DEBUG
1689static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
1690 struct raid_map_data *map_buff)
1691{
1692 struct raid_map_disk_data *dd = &map_buff->data[0];
1693 int map, row, col;
1694 u16 map_cnt, row_cnt, disks_per_row;
1695
1696 if (rc != 0)
1697 return;
1698
1699 dev_info(&h->pdev->dev, "structure_size = %u\n",
1700 le32_to_cpu(map_buff->structure_size));
1701 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
1702 le32_to_cpu(map_buff->volume_blk_size));
1703 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
1704 le64_to_cpu(map_buff->volume_blk_cnt));
1705 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
1706 map_buff->phys_blk_shift);
1707 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
1708 map_buff->parity_rotation_shift);
1709 dev_info(&h->pdev->dev, "strip_size = %u\n",
1710 le16_to_cpu(map_buff->strip_size));
1711 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
1712 le64_to_cpu(map_buff->disk_starting_blk));
1713 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
1714 le64_to_cpu(map_buff->disk_blk_cnt));
1715 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
1716 le16_to_cpu(map_buff->data_disks_per_row));
1717 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
1718 le16_to_cpu(map_buff->metadata_disks_per_row));
1719 dev_info(&h->pdev->dev, "row_cnt = %u\n",
1720 le16_to_cpu(map_buff->row_cnt));
1721 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
1722 le16_to_cpu(map_buff->layout_map_count));
1723
1724 map_cnt = le16_to_cpu(map_buff->layout_map_count);
1725 for (map = 0; map < map_cnt; map++) {
1726 dev_info(&h->pdev->dev, "Map%u:\n", map);
1727 row_cnt = le16_to_cpu(map_buff->row_cnt);
1728 for (row = 0; row < row_cnt; row++) {
1729 dev_info(&h->pdev->dev, " Row%u:\n", row);
1730 disks_per_row =
1731 le16_to_cpu(map_buff->data_disks_per_row);
1732 for (col = 0; col < disks_per_row; col++, dd++)
1733 dev_info(&h->pdev->dev,
1734 " D%02u: h=0x%04x xor=%u,%u\n",
1735 col, dd->ioaccel_handle,
1736 dd->xor_mult[0], dd->xor_mult[1]);
1737 disks_per_row =
1738 le16_to_cpu(map_buff->metadata_disks_per_row);
1739 for (col = 0; col < disks_per_row; col++, dd++)
1740 dev_info(&h->pdev->dev,
1741 " M%02u: h=0x%04x xor=%u,%u\n",
1742 col, dd->ioaccel_handle,
1743 dd->xor_mult[0], dd->xor_mult[1]);
1744 }
1745 }
1746}
1747#else
1748static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
1749 __attribute__((unused)) int rc,
1750 __attribute__((unused)) struct raid_map_data *map_buff)
1751{
1752}
1753#endif
1754
1755static int hpsa_get_raid_map(struct ctlr_info *h,
1756 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
1757{
1758 int rc = 0;
1759 struct CommandList *c;
1760 struct ErrorInfo *ei;
1761
1762 c = cmd_special_alloc(h);
1763 if (c == NULL) {
1764 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
1765 return -ENOMEM;
1766 }
1767 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
1768 sizeof(this_device->raid_map), 0,
1769 scsi3addr, TYPE_CMD)) {
1770 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
1771 cmd_special_free(h, c);
1772 return -ENOMEM;
1773 }
1774 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
1775 ei = c->err_info;
1776 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
1777 hpsa_scsi_interpret_error(c);
1778 cmd_special_free(h, c);
1779 return -1;
1780 }
1781 cmd_special_free(h, c);
1782
1783 /* @todo in the future, dynamically allocate RAID map memory */
1784 if (le32_to_cpu(this_device->raid_map.structure_size) >
1785 sizeof(this_device->raid_map)) {
1786 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
1787 rc = -1;
1788 }
1789 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
1790 return rc;
1791}
1792
1793static void hpsa_get_ioaccel_status(struct ctlr_info *h,
1794 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
1795{
1796 int rc;
1797 unsigned char *buf;
1798 u8 ioaccel_status;
1799
1800 this_device->offload_config = 0;
1801 this_device->offload_enabled = 0;
1802
1803 buf = kzalloc(64, GFP_KERNEL);
1804 if (!buf)
1805 return;
1806 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
1807 HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
1808 if (rc != 0)
1809 goto out;
1810
1811#define IOACCEL_STATUS_BYTE 4
1812#define OFFLOAD_CONFIGURED_BIT 0x01
1813#define OFFLOAD_ENABLED_BIT 0x02
1814 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
1815 this_device->offload_config =
1816 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
1817 if (this_device->offload_config) {
1818 this_device->offload_enabled =
1819 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
1820 if (hpsa_get_raid_map(h, scsi3addr, this_device))
1821 this_device->offload_enabled = 0;
1822 }
1823out:
1824 kfree(buf);
1825 return;
1826}
1827
edd16368
SC		 1828/* Get the device id from inquiry page 0x83 */
1829static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
1830 unsigned char *device_id, int buflen)
1831{
1832 int rc;
1833 unsigned char *buf;
1834
1835 if (buflen > 16)
1836 buflen = 16;
1837 buf = kzalloc(64, GFP_KERNEL);
1838 if (!buf)
1839 return -1;
1840 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0x83, buf, 64);
1841 if (rc == 0)
1842 memcpy(device_id, &buf[8], buflen);
1843 kfree(buf);
1844 return rc != 0;
1845}
1846
1847static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
1848 struct ReportLUNdata *buf, int bufsize,
1849 int extended_response)
1850{
1851 int rc = IO_OK;
1852 struct CommandList *c;
1853 unsigned char scsi3addr[8];
1854 struct ErrorInfo *ei;
1855
1856 c = cmd_special_alloc(h);
1857 if (c == NULL) { /* trouble... */
1858 dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
1859 return -1;
1860 }
e89c0ae7
SC		 1861 /* address the controller */
1862 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 1863 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
1864 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
1865 rc = -1;
1866 goto out;
1867 }
edd16368
SC		 1868 if (extended_response)
1869 c->Request.CDB[1] = extended_response;
1870 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
1871 ei = c->err_info;
1872 if (ei->CommandStatus != 0 &&
1873 ei->CommandStatus != CMD_DATA_UNDERRUN) {
1874 hpsa_scsi_interpret_error(c);
1875 rc = -1;
283b4a9b
SC		 1876 } else {
1877 if (buf->extended_response_flag != extended_response) {
1878 dev_err(&h->pdev->dev,
1879 "report luns requested format %u, got %u\n",
1880 extended_response,
1881 buf->extended_response_flag);
1882 rc = -1;
1883 }
edd16368 1884 }
a2dac136 1885out:
edd16368
SC		 1886 cmd_special_free(h, c);
1887 return rc;
1888}
1889
1890static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
1891 struct ReportLUNdata *buf,
1892 int bufsize, int extended_response)
1893{
1894 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
1895}
1896
1897static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
1898 struct ReportLUNdata *buf, int bufsize)
1899{
1900 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
1901}
1902
1903static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
1904 int bus, int target, int lun)
1905{
1906 device->bus = bus;
1907 device->target = target;
1908 device->lun = lun;
1909}
1910
1911static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 1912 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
1913 unsigned char *is_OBDR_device)
edd16368 1914{
0b0e1d6c
SC		 1915
1916#define OBDR_SIG_OFFSET 43
1917#define OBDR_TAPE_SIG "$DR-10"
1918#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
1919#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
1920
ea6d3bc3 1921 unsigned char *inq_buff;
0b0e1d6c 1922 unsigned char *obdr_sig;
edd16368 1923
ea6d3bc3 1924 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 1925 if (!inq_buff)
1926 goto bail_out;
1927
edd16368
SC		 1928 /* Do an inquiry to the device to see what it is. */
1929 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
1930 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
1931 /* Inquiry failed (msg printed already) */
1932 dev_err(&h->pdev->dev,
1933 "hpsa_update_device_info: inquiry failed\n");
1934 goto bail_out;
1935 }
1936
edd16368
SC		 1937 this_device->devtype = (inq_buff[0] & 0x1f);
1938 memcpy(this_device->scsi3addr, scsi3addr, 8);
1939 memcpy(this_device->vendor, &inq_buff[8],
1940 sizeof(this_device->vendor));
1941 memcpy(this_device->model, &inq_buff[16],
1942 sizeof(this_device->model));
edd16368
SC		 1943 memset(this_device->device_id, 0,
1944 sizeof(this_device->device_id));
1945 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
1946 sizeof(this_device->device_id));
1947
1948 if (this_device->devtype == TYPE_DISK &&
283b4a9b 1949 is_logical_dev_addr_mode(scsi3addr)) {
edd16368 1950 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 1951 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
1952 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
1953 } else {
edd16368 1954 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 1955 this_device->offload_config = 0;
1956 this_device->offload_enabled = 0;
1957 }
edd16368 1958
0b0e1d6c
SC		 1959 if (is_OBDR_device) {
1960 /* See if this is a One-Button-Disaster-Recovery device
1961 * by looking for "$DR-10" at offset 43 in inquiry data.
1962 */
1963 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
1964 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
1965 strncmp(obdr_sig, OBDR_TAPE_SIG,
1966 OBDR_SIG_LEN) == 0);
1967 }
1968
edd16368
SC		 1969 kfree(inq_buff);
1970 return 0;
1971
1972bail_out:
1973 kfree(inq_buff);
1974 return 1;
1975}
1976
4f4eb9f1 1977static unsigned char *ext_target_model[] = {
edd16368
SC		 1978 "MSA2012",
1979 "MSA2024",
1980 "MSA2312",
1981 "MSA2324",
fda38518 1982 "P2000 G3 SAS",
e06c8e5c 1983 "MSA 2040 SAS",
edd16368
SC		 1984 NULL,
1985};
1986
4f4eb9f1 1987static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 1988{
1989 int i;
1990
4f4eb9f1
ST		 1991 for (i = 0; ext_target_model[i]; i++)
1992 if (strncmp(device->model, ext_target_model[i],
1993 strlen(ext_target_model[i])) == 0)
edd16368
SC		 1994 return 1;
1995 return 0;
1996}
1997
1998/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 1999 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2000 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2001 * Logical drive target and lun are assigned at this time, but
2002 * physical device lun and target assignment are deferred (assigned
2003 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2004 */
2005static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2006 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2007{
1f310bde
SC		 2008 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2009
2010 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2011 /* physical device, target and lun filled in later */
edd16368 2012 if (is_hba_lunid(lunaddrbytes))
1f310bde 2013 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2014 else
1f310bde
SC		 2015 /* defer target, lun assignment for physical devices */
2016 hpsa_set_bus_target_lun(device, 2, -1, -1);
2017 return;
2018 }
2019 /* It's a logical device */
4f4eb9f1
ST		 2020 if (is_ext_target(h, device)) {
2021 /* external target way, put logicals on bus 1
1f310bde
SC		 2022 * and match target/lun numbers box
2023 * reports, other smart array, bus 0, target 0, match lunid
2024 */
2025 hpsa_set_bus_target_lun(device,
2026 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2027 return;
edd16368 2028 }
1f310bde 2029 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2030}
2031
2032/*
2033 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2034 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2035 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2036 * it for some reason. *tmpdevice is the target we're adding,
2037 * this_device is a pointer into the current element of currentsd[]
2038 * that we're building up in update_scsi_devices(), below.
2039 * lunzerobits is a bitmap that tracks which targets already have a
2040 * lun 0 assigned.
2041 * Returns 1 if an enclosure was added, 0 if not.
2042 */
4f4eb9f1 2043static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2044 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2045 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2046 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2047{
2048 unsigned char scsi3addr[8];
2049
1f310bde 2050 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2051 return 0; /* There is already a lun 0 on this target. */
2052
2053 if (!is_logical_dev_addr_mode(lunaddrbytes))
2054 return 0; /* It's the logical targets that may lack lun 0. */
2055
4f4eb9f1
ST		 2056 if (!is_ext_target(h, tmpdevice))
2057 return 0; /* Only external target devices have this problem. */
edd16368 2058
1f310bde 2059 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2060 return 0;
2061
c4f8a299 2062 memset(scsi3addr, 0, 8);
1f310bde 2063 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2064 if (is_hba_lunid(scsi3addr))
2065 return 0; /* Don't add the RAID controller here. */
2066
339b2b14
SC		 2067 if (is_scsi_rev_5(h))
2068 return 0; /* p1210m doesn't need to do this. */
2069
4f4eb9f1 2070 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2071 dev_warn(&h->pdev->dev, "Maximum number of external "
2072 "target devices exceeded. Check your hardware "
edd16368
SC		 2073 "configuration.");
2074 return 0;
2075 }
2076
0b0e1d6c 2077 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2078 return 0;
4f4eb9f1 2079 (*n_ext_target_devs)++;
1f310bde
SC		 2080 hpsa_set_bus_target_lun(this_device,
2081 tmpdevice->bus, tmpdevice->target, 0);
2082 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2083 return 1;
2084}
2085
2086/*
2087 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2088 * logdev. The number of luns in physdev and logdev are returned in
2089 * *nphysicals and *nlogicals, respectively.
2090 * Returns 0 on success, -1 otherwise.
2091 */
2092static int hpsa_gather_lun_info(struct ctlr_info *h,
2093 int reportlunsize,
283b4a9b 2094 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2095 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2096{
283b4a9b
SC		 2097 int physical_entry_size = 8;
2098
2099 *physical_mode = 0;
2100
2101 /* For I/O accelerator mode we need to read physical device handles */
2102 if (h->transMethod & CFGTBL_Trans_io_accel1) {
2103 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2104 physical_entry_size = 24;
2105 }
a93aa1fe 2106 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize,
283b4a9b 2107 *physical_mode)) {
edd16368
SC		 2108 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2109 return -1;
2110 }
283b4a9b
SC		 2111 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2112 physical_entry_size;
edd16368
SC		 2113 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2114 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2115 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2116 *nphysicals - HPSA_MAX_PHYS_LUN);
2117 *nphysicals = HPSA_MAX_PHYS_LUN;
2118 }
2119 if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
2120 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2121 return -1;
2122 }
6df1e954 2123 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2124 /* Reject Logicals in excess of our max capability. */
2125 if (*nlogicals > HPSA_MAX_LUN) {
2126 dev_warn(&h->pdev->dev,
2127 "maximum logical LUNs (%d) exceeded. "
2128 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2129 *nlogicals - HPSA_MAX_LUN);
2130 *nlogicals = HPSA_MAX_LUN;
2131 }
2132 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2133 dev_warn(&h->pdev->dev,
2134 "maximum logical + physical LUNs (%d) exceeded. "
2135 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2136 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2137 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2138 }
2139 return 0;
2140}
2141
339b2b14 2142u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
a93aa1fe
MG		 2143 int nphysicals, int nlogicals,
2144 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2145 struct ReportLUNdata *logdev_list)
2146{
2147 /* Helper function, figure out where the LUN ID info is coming from
2148 * given index i, lists of physical and logical devices, where in
2149 * the list the raid controller is supposed to appear (first or last)
2150 */
2151
2152 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2153 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2154
2155 if (i == raid_ctlr_position)
2156 return RAID_CTLR_LUNID;
2157
2158 if (i < logicals_start)
2159 return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
2160
2161 if (i < last_device)
2162 return &logdev_list->LUN[i - nphysicals -
2163 (raid_ctlr_position == 0)][0];
2164 BUG();
2165 return NULL;
2166}
2167
edd16368
SC		 2168static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2169{
2170 /* the idea here is we could get notified
2171 * that some devices have changed, so we do a report
2172 * physical luns and report logical luns cmd, and adjust
2173 * our list of devices accordingly.
2174 *
2175 * The scsi3addr's of devices won't change so long as the
2176 * adapter is not reset. That means we can rescan and
2177 * tell which devices we already know about, vs. new
2178 * devices, vs. disappearing devices.
2179 */
a93aa1fe 2180 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 2181 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 2182 u32 nphysicals = 0;
2183 u32 nlogicals = 0;
283b4a9b 2184 int physical_mode = 0;
01a02ffc 2185 u32 ndev_allocated = 0;
edd16368
SC		 2186 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
2187 int ncurrent = 0;
283b4a9b 2188 int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 24;
4f4eb9f1 2189 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 2190 int raid_ctlr_position;
aca4a520 2191 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 2192
cfe5badc 2193 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 2194 physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
2195 logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
edd16368
SC		 2196 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
2197
0b0e1d6c 2198 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 2199 dev_err(&h->pdev->dev, "out of memory\n");
2200 goto out;
2201 }
2202 memset(lunzerobits, 0, sizeof(lunzerobits));
2203
a93aa1fe
MG		 2204 if (hpsa_gather_lun_info(h, reportlunsize,
2205 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 2206 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 2207 goto out;
2208
aca4a520
ST		 2209 /* We might see up to the maximum number of logical and physical disks
2210 * plus external target devices, and a device for the local RAID
2211 * controller.
edd16368 2212 */
aca4a520 2213 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 2214
2215 /* Allocate the per device structures */
2216 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 2217 if (i >= HPSA_MAX_DEVICES) {
2218 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
2219 " %d devices ignored.\n", HPSA_MAX_DEVICES,
2220 ndevs_to_allocate - HPSA_MAX_DEVICES);
2221 break;
2222 }
2223
edd16368
SC		 2224 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
2225 if (!currentsd[i]) {
2226 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
2227 __FILE__, __LINE__);
2228 goto out;
2229 }
2230 ndev_allocated++;
2231 }
2232
339b2b14
SC		 2233 if (unlikely(is_scsi_rev_5(h)))
2234 raid_ctlr_position = 0;
2235 else
2236 raid_ctlr_position = nphysicals + nlogicals;
2237
edd16368 2238 /* adjust our table of devices */
4f4eb9f1 2239 n_ext_target_devs = 0;
edd16368 2240 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 2241 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 2242
2243 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 2244 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
2245 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 2246 /* skip masked physical devices. */
339b2b14
SC		 2247 if (lunaddrbytes[3] & 0xC0 &&
2248 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 2249 continue;
2250
2251 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 2252 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
2253 &is_OBDR))
edd16368 2254 continue; /* skip it if we can't talk to it. */
1f310bde 2255 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 2256 this_device = currentsd[ncurrent];
2257
2258 /*
4f4eb9f1 2259 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 2260 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
2261 * is nonetheless an enclosure device there. We have to
2262 * present that otherwise linux won't find anything if
2263 * there is no lun 0.
2264 */
4f4eb9f1 2265 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 2266 lunaddrbytes, lunzerobits,
4f4eb9f1 2267 &n_ext_target_devs)) {
edd16368
SC		 2268 ncurrent++;
2269 this_device = currentsd[ncurrent];
2270 }
2271
2272 *this_device = *tmpdevice;
edd16368
SC		 2273
2274 switch (this_device->devtype) {
0b0e1d6c 2275 case TYPE_ROM:
edd16368
SC		 2276 /* We don't *really* support actual CD-ROM devices,
2277 * just "One Button Disaster Recovery" tape drive
2278 * which temporarily pretends to be a CD-ROM drive.
2279 * So we check that the device is really an OBDR tape
2280 * device by checking for "$DR-10" in bytes 43-48 of
2281 * the inquiry data.
2282 */
0b0e1d6c
SC		 2283 if (is_OBDR)
2284 ncurrent++;
edd16368
SC		 2285 break;
2286 case TYPE_DISK:
283b4a9b
SC		 2287 if (i >= nphysicals) {
2288 ncurrent++;
edd16368 2289 break;
283b4a9b
SC		 2290 }
2291 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
2292 memcpy(&this_device->ioaccel_handle,
2293 &lunaddrbytes[20],
2294 sizeof(this_device->ioaccel_handle));
2295 ncurrent++;
2296 }
edd16368
SC		 2297 break;
2298 case TYPE_TAPE:
2299 case TYPE_MEDIUM_CHANGER:
2300 ncurrent++;
2301 break;
2302 case TYPE_RAID:
2303 /* Only present the Smartarray HBA as a RAID controller.
2304 * If it's a RAID controller other than the HBA itself
2305 * (an external RAID controller, MSA500 or similar)
2306 * don't present it.
2307 */
2308 if (!is_hba_lunid(lunaddrbytes))
2309 break;
2310 ncurrent++;
2311 break;
2312 default:
2313 break;
2314 }
cfe5badc 2315 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 2316 break;
2317 }
2318 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
2319out:
2320 kfree(tmpdevice);
2321 for (i = 0; i < ndev_allocated; i++)
2322 kfree(currentsd[i]);
2323 kfree(currentsd);
edd16368
SC		 2324 kfree(physdev_list);
2325 kfree(logdev_list);
edd16368
SC		 2326}
2327
2328/* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
2329 * dma mapping and fills in the scatter gather entries of the
2330 * hpsa command, cp.
2331 */
33a2ffce 2332static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 2333 struct CommandList *cp,
2334 struct scsi_cmnd *cmd)
2335{
2336 unsigned int len;
2337 struct scatterlist *sg;
01a02ffc 2338 u64 addr64;
33a2ffce
SC		 2339 int use_sg, i, sg_index, chained;
2340 struct SGDescriptor *curr_sg;
edd16368 2341
33a2ffce 2342 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 2343
2344 use_sg = scsi_dma_map(cmd);
2345 if (use_sg < 0)
2346 return use_sg;
2347
2348 if (!use_sg)
2349 goto sglist_finished;
2350
33a2ffce
SC		 2351 curr_sg = cp->SG;
2352 chained = 0;
2353 sg_index = 0;
edd16368 2354 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 2355 if (i == h->max_cmd_sg_entries - 1 &&
2356 use_sg > h->max_cmd_sg_entries) {
2357 chained = 1;
2358 curr_sg = h->cmd_sg_list[cp->cmdindex];
2359 sg_index = 0;
2360 }
01a02ffc 2361 addr64 = (u64) sg_dma_address(sg);
edd16368 2362 len = sg_dma_len(sg);
33a2ffce
SC		 2363 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2364 curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2365 curr_sg->Len = len;
e1d9cbfa 2366 curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST;
33a2ffce
SC		 2367 curr_sg++;
2368 }
2369
2370 if (use_sg + chained > h->maxSG)
2371 h->maxSG = use_sg + chained;
2372
2373 if (chained) {
2374 cp->Header.SGList = h->max_cmd_sg_entries;
2375 cp->Header.SGTotal = (u16) (use_sg + 1);
e2bea6df
SC		 2376 if (hpsa_map_sg_chain_block(h, cp)) {
2377 scsi_dma_unmap(cmd);
2378 return -1;
2379 }
33a2ffce 2380 return 0;
edd16368
SC		 2381 }
2382
2383sglist_finished:
2384
01a02ffc
SC		 2385 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
2386 cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
edd16368
SC		 2387 return 0;
2388}
2389
283b4a9b
SC		 2390#define IO_ACCEL_INELIGIBLE (1)
2391static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
2392{
2393 int is_write = 0;
2394 u32 block;
2395 u32 block_cnt;
2396
2397 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
2398 switch (cdb[0]) {
2399 case WRITE_6:
2400 case WRITE_12:
2401 is_write = 1;
2402 case READ_6:
2403 case READ_12:
2404 if (*cdb_len == 6) {
2405 block = (((u32) cdb[2]) << 8) | cdb[3];
2406 block_cnt = cdb[4];
2407 } else {
2408 BUG_ON(*cdb_len != 12);
2409 block = (((u32) cdb[2]) << 24) |
2410 (((u32) cdb[3]) << 16) |
2411 (((u32) cdb[4]) << 8) |
2412 cdb[5];
2413 block_cnt =
2414 (((u32) cdb[6]) << 24) |
2415 (((u32) cdb[7]) << 16) |
2416 (((u32) cdb[8]) << 8) |
2417 cdb[9];
2418 }
2419 if (block_cnt > 0xffff)
2420 return IO_ACCEL_INELIGIBLE;
2421
2422 cdb[0] = is_write ? WRITE_10 : READ_10;
2423 cdb[1] = 0;
2424 cdb[2] = (u8) (block >> 24);
2425 cdb[3] = (u8) (block >> 16);
2426 cdb[4] = (u8) (block >> 8);
2427 cdb[5] = (u8) (block);
2428 cdb[6] = 0;
2429 cdb[7] = (u8) (block_cnt >> 8);
2430 cdb[8] = (u8) (block_cnt);
2431 cdb[9] = 0;
2432 *cdb_len = 10;
2433 break;
2434 }
2435 return 0;
2436}
2437
e1f7de0c
MG		 2438/*
2439 * Queue a command to the I/O accelerator path.
e1f7de0c
MG		 2440 */
2441static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
283b4a9b
SC		 2442 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2443 u8 *scsi3addr)
e1f7de0c
MG		 2444{
2445 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 2446 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
2447 unsigned int len;
2448 unsigned int total_len = 0;
2449 struct scatterlist *sg;
2450 u64 addr64;
2451 int use_sg, i;
2452 struct SGDescriptor *curr_sg;
2453 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
2454
283b4a9b
SC		 2455 /* TODO: implement chaining support */
2456 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
2457 return IO_ACCEL_INELIGIBLE;
2458
e1f7de0c
MG		 2459 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
2460
283b4a9b
SC		 2461 if (fixup_ioaccel_cdb(cdb, &cdb_len))
2462 return IO_ACCEL_INELIGIBLE;
2463
e1f7de0c
MG		 2464 c->cmd_type = CMD_IOACCEL1;
2465
2466 /* Adjust the DMA address to point to the accelerated command buffer */
2467 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
2468 (c->cmdindex * sizeof(*cp));
2469 BUG_ON(c->busaddr & 0x0000007F);
2470
2471 use_sg = scsi_dma_map(cmd);
2472 if (use_sg < 0)
2473 return use_sg;
2474
2475 if (use_sg) {
2476 curr_sg = cp->SG;
2477 scsi_for_each_sg(cmd, sg, use_sg, i) {
2478 addr64 = (u64) sg_dma_address(sg);
2479 len = sg_dma_len(sg);
2480 total_len += len;
2481 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2482 curr_sg->Addr.upper =
2483 (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2484 curr_sg->Len = len;
2485
2486 if (i == (scsi_sg_count(cmd) - 1))
2487 curr_sg->Ext = HPSA_SG_LAST;
2488 else
2489 curr_sg->Ext = 0; /* we are not chaining */
2490 curr_sg++;
2491 }
2492
2493 switch (cmd->sc_data_direction) {
2494 case DMA_TO_DEVICE:
2495 control |= IOACCEL1_CONTROL_DATA_OUT;
2496 break;
2497 case DMA_FROM_DEVICE:
2498 control |= IOACCEL1_CONTROL_DATA_IN;
2499 break;
2500 case DMA_NONE:
2501 control |= IOACCEL1_CONTROL_NODATAXFER;
2502 break;
2503 default:
2504 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
2505 cmd->sc_data_direction);
2506 BUG();
2507 break;
2508 }
2509 } else {
2510 control |= IOACCEL1_CONTROL_NODATAXFER;
2511 }
2512
2513 /* Fill out the command structure to submit */
283b4a9b 2514 cp->dev_handle = ioaccel_handle & 0xFFFF;
e1f7de0c
MG		 2515 cp->transfer_len = total_len;
2516 cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ |
283b4a9b 2517 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK);
e1f7de0c 2518 cp->control = control;
283b4a9b
SC		 2519 memcpy(cp->CDB, cdb, cdb_len);
2520 memcpy(cp->CISS_LUN, scsi3addr, 8);
e1f7de0c
MG		 2521
2522 /* Tell the controller to post the reply to the queue for this
2523 * processor. This seems to give the best I/O throughput.
2524 */
2525 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
2526
2527 /* Set the bits in the address sent down to include:
2528 * - performant mode bit (bit 0)
2529 * - pull count (bits 1-3)
2530 * - command type (bits 4-6)
2531 */
2532 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[use_sg] << 1) |
2533 IOACCEL1_BUSADDR_CMDTYPE;
283b4a9b 2534 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 2535 return 0;
2536}
edd16368 2537
283b4a9b
SC		 2538/*
2539 * Queue a command directly to a device behind the controller using the
2540 * I/O accelerator path.
2541 */
2542static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
2543 struct CommandList *c)
2544{
2545 struct scsi_cmnd *cmd = c->scsi_cmd;
2546 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
2547
2548 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
2549 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
2550}
2551
2552/*
2553 * Attempt to perform offload RAID mapping for a logical volume I/O.
2554 */
2555static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
2556 struct CommandList *c)
2557{
2558 struct scsi_cmnd *cmd = c->scsi_cmd;
2559 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
2560 struct raid_map_data *map = &dev->raid_map;
2561 struct raid_map_disk_data *dd = &map->data[0];
2562 int is_write = 0;
2563 u32 map_index;
2564 u64 first_block, last_block;
2565 u32 block_cnt;
2566 u32 blocks_per_row;
2567 u64 first_row, last_row;
2568 u32 first_row_offset, last_row_offset;
2569 u32 first_column, last_column;
2570 u32 map_row;
2571 u32 disk_handle;
2572 u64 disk_block;
2573 u32 disk_block_cnt;
2574 u8 cdb[16];
2575 u8 cdb_len;
2576#if BITS_PER_LONG == 32
2577 u64 tmpdiv;
2578#endif
2579
2580 BUG_ON(!(dev->offload_config && dev->offload_enabled));
2581
2582 /* check for valid opcode, get LBA and block count */
2583 switch (cmd->cmnd[0]) {
2584 case WRITE_6:
2585 is_write = 1;
2586 case READ_6:
2587 first_block =
2588 (((u64) cmd->cmnd[2]) << 8) |
2589 cmd->cmnd[3];
2590 block_cnt = cmd->cmnd[4];
2591 break;
2592 case WRITE_10:
2593 is_write = 1;
2594 case READ_10:
2595 first_block =
2596 (((u64) cmd->cmnd[2]) << 24) |
2597 (((u64) cmd->cmnd[3]) << 16) |
2598 (((u64) cmd->cmnd[4]) << 8) |
2599 cmd->cmnd[5];
2600 block_cnt =
2601 (((u32) cmd->cmnd[7]) << 8) |
2602 cmd->cmnd[8];
2603 break;
2604 case WRITE_12:
2605 is_write = 1;
2606 case READ_12:
2607 first_block =
2608 (((u64) cmd->cmnd[2]) << 24) |
2609 (((u64) cmd->cmnd[3]) << 16) |
2610 (((u64) cmd->cmnd[4]) << 8) |
2611 cmd->cmnd[5];
2612 block_cnt =
2613 (((u32) cmd->cmnd[6]) << 24) |
2614 (((u32) cmd->cmnd[7]) << 16) |
2615 (((u32) cmd->cmnd[8]) << 8) |
2616 cmd->cmnd[9];
2617 break;
2618 case WRITE_16:
2619 is_write = 1;
2620 case READ_16:
2621 first_block =
2622 (((u64) cmd->cmnd[2]) << 56) |
2623 (((u64) cmd->cmnd[3]) << 48) |
2624 (((u64) cmd->cmnd[4]) << 40) |
2625 (((u64) cmd->cmnd[5]) << 32) |
2626 (((u64) cmd->cmnd[6]) << 24) |
2627 (((u64) cmd->cmnd[7]) << 16) |
2628 (((u64) cmd->cmnd[8]) << 8) |
2629 cmd->cmnd[9];
2630 block_cnt =
2631 (((u32) cmd->cmnd[10]) << 24) |
2632 (((u32) cmd->cmnd[11]) << 16) |
2633 (((u32) cmd->cmnd[12]) << 8) |
2634 cmd->cmnd[13];
2635 break;
2636 default:
2637 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
2638 }
2639 BUG_ON(block_cnt == 0);
2640 last_block = first_block + block_cnt - 1;
2641
2642 /* check for write to non-RAID-0 */
2643 if (is_write && dev->raid_level != 0)
2644 return IO_ACCEL_INELIGIBLE;
2645
2646 /* check for invalid block or wraparound */
2647 if (last_block >= map->volume_blk_cnt || last_block < first_block)
2648 return IO_ACCEL_INELIGIBLE;
2649
2650 /* calculate stripe information for the request */
2651 blocks_per_row = map->data_disks_per_row * map->strip_size;
2652#if BITS_PER_LONG == 32
2653 tmpdiv = first_block;
2654 (void) do_div(tmpdiv, blocks_per_row);
2655 first_row = tmpdiv;
2656 tmpdiv = last_block;
2657 (void) do_div(tmpdiv, blocks_per_row);
2658 last_row = tmpdiv;
2659 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
2660 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2661 tmpdiv = first_row_offset;
2662 (void) do_div(tmpdiv, map->strip_size);
2663 first_column = tmpdiv;
2664 tmpdiv = last_row_offset;
2665 (void) do_div(tmpdiv, map->strip_size);
2666 last_column = tmpdiv;
2667#else
2668 first_row = first_block / blocks_per_row;
2669 last_row = last_block / blocks_per_row;
2670 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
2671 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2672 first_column = first_row_offset / map->strip_size;
2673 last_column = last_row_offset / map->strip_size;
2674#endif
2675
2676 /* if this isn't a single row/column then give to the controller */
2677 if ((first_row != last_row) || (first_column != last_column))
2678 return IO_ACCEL_INELIGIBLE;
2679
2680 /* proceeding with driver mapping */
2681 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2682 map->row_cnt;
2683 map_index = (map_row * (map->data_disks_per_row +
2684 map->metadata_disks_per_row)) + first_column;
2685 if (dev->raid_level == 2) {
2686 /* simple round-robin balancing of RAID 1+0 reads across
2687 * primary and mirror members. this is appropriate for SSD
2688 * but not optimal for HDD.
2689 */
2690 if (dev->offload_to_mirror)
2691 map_index += map->data_disks_per_row;
2692 dev->offload_to_mirror = !dev->offload_to_mirror;
2693 }
2694 disk_handle = dd[map_index].ioaccel_handle;
2695 disk_block = map->disk_starting_blk + (first_row * map->strip_size) +
2696 (first_row_offset - (first_column * map->strip_size));
2697 disk_block_cnt = block_cnt;
2698
2699 /* handle differing logical/physical block sizes */
2700 if (map->phys_blk_shift) {
2701 disk_block <<= map->phys_blk_shift;
2702 disk_block_cnt <<= map->phys_blk_shift;
2703 }
2704 BUG_ON(disk_block_cnt > 0xffff);
2705
2706 /* build the new CDB for the physical disk I/O */
2707 if (disk_block > 0xffffffff) {
2708 cdb[0] = is_write ? WRITE_16 : READ_16;
2709 cdb[1] = 0;
2710 cdb[2] = (u8) (disk_block >> 56);
2711 cdb[3] = (u8) (disk_block >> 48);
2712 cdb[4] = (u8) (disk_block >> 40);
2713 cdb[5] = (u8) (disk_block >> 32);
2714 cdb[6] = (u8) (disk_block >> 24);
2715 cdb[7] = (u8) (disk_block >> 16);
2716 cdb[8] = (u8) (disk_block >> 8);
2717 cdb[9] = (u8) (disk_block);
2718 cdb[10] = (u8) (disk_block_cnt >> 24);
2719 cdb[11] = (u8) (disk_block_cnt >> 16);
2720 cdb[12] = (u8) (disk_block_cnt >> 8);
2721 cdb[13] = (u8) (disk_block_cnt);
2722 cdb[14] = 0;
2723 cdb[15] = 0;
2724 cdb_len = 16;
2725 } else {
2726 cdb[0] = is_write ? WRITE_10 : READ_10;
2727 cdb[1] = 0;
2728 cdb[2] = (u8) (disk_block >> 24);
2729 cdb[3] = (u8) (disk_block >> 16);
2730 cdb[4] = (u8) (disk_block >> 8);
2731 cdb[5] = (u8) (disk_block);
2732 cdb[6] = 0;
2733 cdb[7] = (u8) (disk_block_cnt >> 8);
2734 cdb[8] = (u8) (disk_block_cnt);
2735 cdb[9] = 0;
2736 cdb_len = 10;
2737 }
2738 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
2739 dev->scsi3addr);
2740}
2741
f281233d 2742static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
edd16368
SC		 2743 void (*done)(struct scsi_cmnd *))
2744{
2745 struct ctlr_info *h;
2746 struct hpsa_scsi_dev_t *dev;
2747 unsigned char scsi3addr[8];
2748 struct CommandList *c;
2749 unsigned long flags;
283b4a9b 2750 int rc = 0;
edd16368
SC		 2751
2752 /* Get the ptr to our adapter structure out of cmd->host. */
2753 h = sdev_to_hba(cmd->device);
2754 dev = cmd->device->hostdata;
2755 if (!dev) {
2756 cmd->result = DID_NO_CONNECT << 16;
2757 done(cmd);
2758 return 0;
2759 }
2760 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
2761
edd16368 2762 spin_lock_irqsave(&h->lock, flags);
a0c12413
SC		 2763 if (unlikely(h->lockup_detected)) {
2764 spin_unlock_irqrestore(&h->lock, flags);
2765 cmd->result = DID_ERROR << 16;
2766 done(cmd);
2767 return 0;
2768 }
edd16368 2769 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 2770 c = cmd_alloc(h);
edd16368
SC		 2771 if (c == NULL) { /* trouble... */
2772 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
2773 return SCSI_MLQUEUE_HOST_BUSY;
2774 }
2775
2776 /* Fill in the command list header */
2777
2778 cmd->scsi_done = done; /* save this for use by completion code */
2779
2780 /* save c in case we have to abort it */
2781 cmd->host_scribble = (unsigned char *) c;
2782
2783 c->cmd_type = CMD_SCSI;
2784 c->scsi_cmd = cmd;
e1f7de0c 2785
283b4a9b
SC		 2786 /* Call alternate submit routine for I/O accelerated commands.
2787 * Retries always go down the normal I/O path.
2788 */
2789 if (likely(cmd->retries == 0 &&
2790 cmd->request->cmd_type == REQ_TYPE_FS)) {
2791 if (dev->offload_enabled) {
2792 rc = hpsa_scsi_ioaccel_raid_map(h, c);
2793 if (rc == 0)
2794 return 0; /* Sent on ioaccel path */
2795 if (rc < 0) { /* scsi_dma_map failed. */
2796 cmd_free(h, c);
2797 return SCSI_MLQUEUE_HOST_BUSY;
2798 }
2799 } else if (dev->ioaccel_handle) {
2800 rc = hpsa_scsi_ioaccel_direct_map(h, c);
2801 if (rc == 0)
2802 return 0; /* Sent on direct map path */
2803 if (rc < 0) { /* scsi_dma_map failed. */
2804 cmd_free(h, c);
2805 return SCSI_MLQUEUE_HOST_BUSY;
2806 }
2807 }
2808 }
e1f7de0c 2809
edd16368
SC		 2810 c->Header.ReplyQueue = 0; /* unused in simple mode */
2811 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
303932fd
DB		 2812 c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
2813 c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
edd16368
SC		 2814
2815 /* Fill in the request block... */
2816
2817 c->Request.Timeout = 0;
2818 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
2819 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
2820 c->Request.CDBLen = cmd->cmd_len;
2821 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
2822 c->Request.Type.Type = TYPE_CMD;
2823 c->Request.Type.Attribute = ATTR_SIMPLE;
2824 switch (cmd->sc_data_direction) {
2825 case DMA_TO_DEVICE:
2826 c->Request.Type.Direction = XFER_WRITE;
2827 break;
2828 case DMA_FROM_DEVICE:
2829 c->Request.Type.Direction = XFER_READ;
2830 break;
2831 case DMA_NONE:
2832 c->Request.Type.Direction = XFER_NONE;
2833 break;
2834 case DMA_BIDIRECTIONAL:
2835 /* This can happen if a buggy application does a scsi passthru
2836 * and sets both inlen and outlen to non-zero. ( see
2837 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
2838 */
2839
2840 c->Request.Type.Direction = XFER_RSVD;
2841 /* This is technically wrong, and hpsa controllers should
2842 * reject it with CMD_INVALID, which is the most correct
2843 * response, but non-fibre backends appear to let it
2844 * slide by, and give the same results as if this field
2845 * were set correctly. Either way is acceptable for
2846 * our purposes here.
2847 */
2848
2849 break;
2850
2851 default:
2852 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
2853 cmd->sc_data_direction);
2854 BUG();
2855 break;
2856 }
2857
33a2ffce 2858 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 2859 cmd_free(h, c);
2860 return SCSI_MLQUEUE_HOST_BUSY;
2861 }
2862 enqueue_cmd_and_start_io(h, c);
2863 /* the cmd'll come back via intr handler in complete_scsi_command() */
2864 return 0;
2865}
2866
f281233d
JG		 2867static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
2868
a08a8471
SC		 2869static void hpsa_scan_start(struct Scsi_Host *sh)
2870{
2871 struct ctlr_info *h = shost_to_hba(sh);
2872 unsigned long flags;
2873
2874 /* wait until any scan already in progress is finished. */
2875 while (1) {
2876 spin_lock_irqsave(&h->scan_lock, flags);
2877 if (h->scan_finished)
2878 break;
2879 spin_unlock_irqrestore(&h->scan_lock, flags);
2880 wait_event(h->scan_wait_queue, h->scan_finished);
2881 /* Note: We don't need to worry about a race between this
2882 * thread and driver unload because the midlayer will
2883 * have incremented the reference count, so unload won't
2884 * happen if we're in here.
2885 */
2886 }
2887 h->scan_finished = 0; /* mark scan as in progress */
2888 spin_unlock_irqrestore(&h->scan_lock, flags);
2889
2890 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
2891
2892 spin_lock_irqsave(&h->scan_lock, flags);
2893 h->scan_finished = 1; /* mark scan as finished. */
2894 wake_up_all(&h->scan_wait_queue);
2895 spin_unlock_irqrestore(&h->scan_lock, flags);
2896}
2897
2898static int hpsa_scan_finished(struct Scsi_Host *sh,
2899 unsigned long elapsed_time)
2900{
2901 struct ctlr_info *h = shost_to_hba(sh);
2902 unsigned long flags;
2903 int finished;
2904
2905 spin_lock_irqsave(&h->scan_lock, flags);
2906 finished = h->scan_finished;
2907 spin_unlock_irqrestore(&h->scan_lock, flags);
2908 return finished;
2909}
2910
667e23d4
SC		 2911static int hpsa_change_queue_depth(struct scsi_device *sdev,
2912 int qdepth, int reason)
2913{
2914 struct ctlr_info *h = sdev_to_hba(sdev);
2915
2916 if (reason != SCSI_QDEPTH_DEFAULT)
2917 return -ENOTSUPP;
2918
2919 if (qdepth < 1)
2920 qdepth = 1;
2921 else
2922 if (qdepth > h->nr_cmds)
2923 qdepth = h->nr_cmds;
2924 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
2925 return sdev->queue_depth;
2926}
2927
edd16368
SC		 2928static void hpsa_unregister_scsi(struct ctlr_info *h)
2929{
2930 /* we are being forcibly unloaded, and may not refuse. */
2931 scsi_remove_host(h->scsi_host);
2932 scsi_host_put(h->scsi_host);
2933 h->scsi_host = NULL;
2934}
2935
2936static int hpsa_register_scsi(struct ctlr_info *h)
2937{
b705690d
SC		 2938 struct Scsi_Host *sh;
2939 int error;
edd16368 2940
b705690d
SC		 2941 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2942 if (sh == NULL)
2943 goto fail;
2944
2945 sh->io_port = 0;
2946 sh->n_io_port = 0;
2947 sh->this_id = -1;
2948 sh->max_channel = 3;
2949 sh->max_cmd_len = MAX_COMMAND_SIZE;
2950 sh->max_lun = HPSA_MAX_LUN;
2951 sh->max_id = HPSA_MAX_LUN;
2952 sh->can_queue = h->nr_cmds;
2953 sh->cmd_per_lun = h->nr_cmds;
2954 sh->sg_tablesize = h->maxsgentries;
2955 h->scsi_host = sh;
2956 sh->hostdata[0] = (unsigned long) h;
2957 sh->irq = h->intr[h->intr_mode];
2958 sh->unique_id = sh->irq;
2959 error = scsi_add_host(sh, &h->pdev->dev);
2960 if (error)
2961 goto fail_host_put;
2962 scsi_scan_host(sh);
2963 return 0;
2964
2965 fail_host_put:
2966 dev_err(&h->pdev->dev, "%s: scsi_add_host"
2967 " failed for controller %d\n", __func__, h->ctlr);
2968 scsi_host_put(sh);
2969 return error;
2970 fail:
2971 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
2972 " failed for controller %d\n", __func__, h->ctlr);
2973 return -ENOMEM;
edd16368
SC		 2974}
2975
2976static int wait_for_device_to_become_ready(struct ctlr_info *h,
2977 unsigned char lunaddr[])
2978{
2979 int rc = 0;
2980 int count = 0;
2981 int waittime = 1; /* seconds */
2982 struct CommandList *c;
2983
2984 c = cmd_special_alloc(h);
2985 if (!c) {
2986 dev_warn(&h->pdev->dev, "out of memory in "
2987 "wait_for_device_to_become_ready.\n");
2988 return IO_ERROR;
2989 }
2990
2991 /* Send test unit ready until device ready, or give up. */
2992 while (count < HPSA_TUR_RETRY_LIMIT) {
2993
2994 /* Wait for a bit. do this first, because if we send
2995 * the TUR right away, the reset will just abort it.
2996 */
2997 msleep(1000 * waittime);
2998 count++;
2999
3000 /* Increase wait time with each try, up to a point. */
3001 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
3002 waittime = waittime * 2;
3003
a2dac136
SC		 3004 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
3005 (void) fill_cmd(c, TEST_UNIT_READY, h,
3006 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 3007 hpsa_scsi_do_simple_cmd_core(h, c);
3008 /* no unmap needed here because no data xfer. */
3009
3010 if (c->err_info->CommandStatus == CMD_SUCCESS)
3011 break;
3012
3013 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
3014 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
3015 (c->err_info->SenseInfo[2] == NO_SENSE ||
3016 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
3017 break;
3018
3019 dev_warn(&h->pdev->dev, "waiting %d secs "
3020 "for device to become ready.\n", waittime);
3021 rc = 1; /* device not ready. */
3022 }
3023
3024 if (rc)
3025 dev_warn(&h->pdev->dev, "giving up on device.\n");
3026 else
3027 dev_warn(&h->pdev->dev, "device is ready.\n");
3028
3029 cmd_special_free(h, c);
3030 return rc;
3031}
3032
3033/* Need at least one of these error handlers to keep ../scsi/hosts.c from
3034 * complaining. Doing a host- or bus-reset can't do anything good here.
3035 */
3036static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
3037{
3038 int rc;
3039 struct ctlr_info *h;
3040 struct hpsa_scsi_dev_t *dev;
3041
3042 /* find the controller to which the command to be aborted was sent */
3043 h = sdev_to_hba(scsicmd->device);
3044 if (h == NULL) /* paranoia */
3045 return FAILED;
edd16368
SC		 3046 dev = scsicmd->device->hostdata;
3047 if (!dev) {
3048 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
3049 "device lookup failed.\n");
3050 return FAILED;
3051 }
d416b0c7
SC		 3052 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
3053 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368
SC		 3054 /* send a reset to the SCSI LUN which the command was sent to */
3055 rc = hpsa_send_reset(h, dev->scsi3addr);
3056 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
3057 return SUCCESS;
3058
3059 dev_warn(&h->pdev->dev, "resetting device failed.\n");
3060 return FAILED;
3061}
3062
6cba3f19
SC		 3063static void swizzle_abort_tag(u8 *tag)
3064{
3065 u8 original_tag[8];
3066
3067 memcpy(original_tag, tag, 8);
3068 tag[0] = original_tag[3];
3069 tag[1] = original_tag[2];
3070 tag[2] = original_tag[1];
3071 tag[3] = original_tag[0];
3072 tag[4] = original_tag[7];
3073 tag[5] = original_tag[6];
3074 tag[6] = original_tag[5];
3075 tag[7] = original_tag[4];
3076}
3077
17eb87d2
ST		 3078static void hpsa_get_tag(struct ctlr_info *h,
3079 struct CommandList *c, u32 *taglower, u32 *tagupper)
3080{
3081 if (c->cmd_type == CMD_IOACCEL1) {
3082 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
3083 &h->ioaccel_cmd_pool[c->cmdindex];
3084 *tagupper = cm1->Tag.upper;
3085 *taglower = cm1->Tag.lower;
3086 } else {
3087 *tagupper = c->Header.Tag.upper;
3088 *taglower = c->Header.Tag.lower;
3089 }
3090}
3091
75167d2c 3092static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 3093 struct CommandList *abort, int swizzle)
75167d2c
SC		 3094{
3095 int rc = IO_OK;
3096 struct CommandList *c;
3097 struct ErrorInfo *ei;
17eb87d2 3098 u32 tagupper, taglower;
75167d2c
SC		 3099
3100 c = cmd_special_alloc(h);
3101 if (c == NULL) { /* trouble... */
3102 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
3103 return -ENOMEM;
3104 }
3105
a2dac136
SC		 3106 /* fill_cmd can't fail here, no buffer to map */
3107 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
3108 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 3109 if (swizzle)
3110 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 3111 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 3112 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 3113 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 3114 __func__, tagupper, taglower);
75167d2c
SC		 3115 /* no unmap needed here because no data xfer. */
3116
3117 ei = c->err_info;
3118 switch (ei->CommandStatus) {
3119 case CMD_SUCCESS:
3120 break;
3121 case CMD_UNABORTABLE: /* Very common, don't make noise. */
3122 rc = -1;
3123 break;
3124 default:
3125 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 3126 __func__, tagupper, taglower);
75167d2c
SC		 3127 hpsa_scsi_interpret_error(c);
3128 rc = -1;
3129 break;
3130 }
3131 cmd_special_free(h, c);
3132 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
3133 abort->Header.Tag.upper, abort->Header.Tag.lower);
3134 return rc;
3135}
3136
3137/*
3138 * hpsa_find_cmd_in_queue
3139 *
3140 * Used to determine whether a command (find) is still present
3141 * in queue_head. Optionally excludes the last element of queue_head.
3142 *
3143 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
3144 * not yet been submitted, and so can be aborted by the driver without
3145 * sending an abort to the hardware.
3146 *
3147 * Returns pointer to command if found in queue, NULL otherwise.
3148 */
3149static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
3150 struct scsi_cmnd *find, struct list_head *queue_head)
3151{
3152 unsigned long flags;
3153 struct CommandList *c = NULL; /* ptr into cmpQ */
3154
3155 if (!find)
3156 return 0;
3157 spin_lock_irqsave(&h->lock, flags);
3158 list_for_each_entry(c, queue_head, list) {
3159 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
3160 continue;
3161 if (c->scsi_cmd == find) {
3162 spin_unlock_irqrestore(&h->lock, flags);
3163 return c;
3164 }
3165 }
3166 spin_unlock_irqrestore(&h->lock, flags);
3167 return NULL;
3168}
3169
6cba3f19
SC		 3170static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
3171 u8 *tag, struct list_head *queue_head)
3172{
3173 unsigned long flags;
3174 struct CommandList *c;
3175
3176 spin_lock_irqsave(&h->lock, flags);
3177 list_for_each_entry(c, queue_head, list) {
3178 if (memcmp(&c->Header.Tag, tag, 8) != 0)
3179 continue;
3180 spin_unlock_irqrestore(&h->lock, flags);
3181 return c;
3182 }
3183 spin_unlock_irqrestore(&h->lock, flags);
3184 return NULL;
3185}
3186
3187/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
3188 * tell which kind we're dealing with, so we send the abort both ways. There
3189 * shouldn't be any collisions between swizzled and unswizzled tags due to the
3190 * way we construct our tags but we check anyway in case the assumptions which
3191 * make this true someday become false.
3192 */
3193static int hpsa_send_abort_both_ways(struct ctlr_info *h,
3194 unsigned char *scsi3addr, struct CommandList *abort)
3195{
3196 u8 swizzled_tag[8];
3197 struct CommandList *c;
3198 int rc = 0, rc2 = 0;
3199
3200 /* we do not expect to find the swizzled tag in our queue, but
3201 * check anyway just to be sure the assumptions which make this
3202 * the case haven't become wrong.
3203 */
3204 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
3205 swizzle_abort_tag(swizzled_tag);
3206 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
3207 if (c != NULL) {
3208 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
3209 return hpsa_send_abort(h, scsi3addr, abort, 0);
3210 }
3211 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
3212
3213 /* if the command is still in our queue, we can't conclude that it was
3214 * aborted (it might have just completed normally) but in any case
3215 * we don't need to try to abort it another way.
3216 */
3217 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
3218 if (c)
3219 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
3220 return rc && rc2;
3221}
3222
75167d2c
SC		 3223/* Send an abort for the specified command.
3224 * If the device and controller support it,
3225 * send a task abort request.
3226 */
3227static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
3228{
3229
3230 int i, rc;
3231 struct ctlr_info *h;
3232 struct hpsa_scsi_dev_t *dev;
3233 struct CommandList *abort; /* pointer to command to be aborted */
3234 struct CommandList *found;
3235 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
3236 char msg[256]; /* For debug messaging. */
3237 int ml = 0;
17eb87d2 3238 u32 tagupper, taglower;
75167d2c
SC		 3239
3240 /* Find the controller of the command to be aborted */
3241 h = sdev_to_hba(sc->device);
3242 if (WARN(h == NULL,
3243 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
3244 return FAILED;
3245
3246 /* Check that controller supports some kind of task abort */
3247 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
3248 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
3249 return FAILED;
3250
3251 memset(msg, 0, sizeof(msg));
3252 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ",
3253 h->scsi_host->host_no, sc->device->channel,
3254 sc->device->id, sc->device->lun);
3255
3256 /* Find the device of the command to be aborted */
3257 dev = sc->device->hostdata;
3258 if (!dev) {
3259 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
3260 msg);
3261 return FAILED;
3262 }
3263
3264 /* Get SCSI command to be aborted */
3265 abort = (struct CommandList *) sc->host_scribble;
3266 if (abort == NULL) {
3267 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
3268 msg);
3269 return FAILED;
3270 }
17eb87d2
ST		 3271 hpsa_get_tag(h, abort, &taglower, &tagupper);
3272 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 3273 as = (struct scsi_cmnd *) abort->scsi_cmd;
3274 if (as != NULL)
3275 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
3276 as->cmnd[0], as->serial_number);
3277 dev_dbg(&h->pdev->dev, "%s\n", msg);
3278 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
3279 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
3280
3281 /* Search reqQ to See if command is queued but not submitted,
3282 * if so, complete the command with aborted status and remove
3283 * it from the reqQ.
3284 */
3285 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
3286 if (found) {
3287 found->err_info->CommandStatus = CMD_ABORTED;
3288 finish_cmd(found);
3289 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
3290 msg);
3291 return SUCCESS;
3292 }
3293
3294 /* not in reqQ, if also not in cmpQ, must have already completed */
3295 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
3296 if (!found) {
d6ebd0f7 3297 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 3298 msg);
3299 return SUCCESS;
3300 }
3301
3302 /*
3303 * Command is in flight, or possibly already completed
3304 * by the firmware (but not to the scsi mid layer) but we can't
3305 * distinguish which. Send the abort down.
3306 */
6cba3f19 3307 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 3308 if (rc != 0) {
3309 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
3310 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
3311 h->scsi_host->host_no,
3312 dev->bus, dev->target, dev->lun);
3313 return FAILED;
3314 }
3315 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
3316
3317 /* If the abort(s) above completed and actually aborted the
3318 * command, then the command to be aborted should already be
3319 * completed. If not, wait around a bit more to see if they
3320 * manage to complete normally.
3321 */
3322#define ABORT_COMPLETE_WAIT_SECS 30
3323 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
3324 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
3325 if (!found)
3326 return SUCCESS;
3327 msleep(100);
3328 }
3329 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
3330 msg, ABORT_COMPLETE_WAIT_SECS);
3331 return FAILED;
3332}
3333
3334
edd16368
SC		 3335/*
3336 * For operations that cannot sleep, a command block is allocated at init,
3337 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
3338 * which ones are free or in use. Lock must be held when calling this.
3339 * cmd_free() is the complement.
3340 */
3341static struct CommandList *cmd_alloc(struct ctlr_info *h)
3342{
3343 struct CommandList *c;
3344 int i;
3345 union u64bit temp64;
3346 dma_addr_t cmd_dma_handle, err_dma_handle;
e16a33ad 3347 unsigned long flags;
edd16368 3348
e16a33ad 3349 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 3350 do {
3351 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
e16a33ad
MG		 3352 if (i == h->nr_cmds) {
3353 spin_unlock_irqrestore(&h->lock, flags);
edd16368 3354 return NULL;
e16a33ad 3355 }
edd16368
SC		 3356 } while (test_and_set_bit
3357 (i & (BITS_PER_LONG - 1),
3358 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
e16a33ad
MG		 3359 spin_unlock_irqrestore(&h->lock, flags);
3360
edd16368
SC		 3361 c = h->cmd_pool + i;
3362 memset(c, 0, sizeof(*c));
3363 cmd_dma_handle = h->cmd_pool_dhandle
3364 + i * sizeof(*c);
3365 c->err_info = h->errinfo_pool + i;
3366 memset(c->err_info, 0, sizeof(*c->err_info));
3367 err_dma_handle = h->errinfo_pool_dhandle
3368 + i * sizeof(*c->err_info);
edd16368
SC		 3369
3370 c->cmdindex = i;
3371
9e0fc764 3372 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 3373 c->busaddr = (u32) cmd_dma_handle;
3374 temp64.val = (u64) err_dma_handle;
edd16368
SC		 3375 c->ErrDesc.Addr.lower = temp64.val32.lower;
3376 c->ErrDesc.Addr.upper = temp64.val32.upper;
3377 c->ErrDesc.Len = sizeof(*c->err_info);
3378
3379 c->h = h;
3380 return c;
3381}
3382
3383/* For operations that can wait for kmalloc to possibly sleep,
3384 * this routine can be called. Lock need not be held to call
3385 * cmd_special_alloc. cmd_special_free() is the complement.
3386 */
3387static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
3388{
3389 struct CommandList *c;
3390 union u64bit temp64;
3391 dma_addr_t cmd_dma_handle, err_dma_handle;
3392
3393 c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
3394 if (c == NULL)
3395 return NULL;
3396 memset(c, 0, sizeof(*c));
3397
e1f7de0c 3398 c->cmd_type = CMD_SCSI;
edd16368
SC		 3399 c->cmdindex = -1;
3400
3401 c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
3402 &err_dma_handle);
3403
3404 if (c->err_info == NULL) {
3405 pci_free_consistent(h->pdev,
3406 sizeof(*c), c, cmd_dma_handle);
3407 return NULL;
3408 }
3409 memset(c->err_info, 0, sizeof(*c->err_info));
3410
9e0fc764 3411 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 3412 c->busaddr = (u32) cmd_dma_handle;
3413 temp64.val = (u64) err_dma_handle;
edd16368
SC		 3414 c->ErrDesc.Addr.lower = temp64.val32.lower;
3415 c->ErrDesc.Addr.upper = temp64.val32.upper;
3416 c->ErrDesc.Len = sizeof(*c->err_info);
3417
3418 c->h = h;
3419 return c;
3420}
3421
3422static void cmd_free(struct ctlr_info *h, struct CommandList *c)
3423{
3424 int i;
e16a33ad 3425 unsigned long flags;
edd16368
SC		 3426
3427 i = c - h->cmd_pool;
e16a33ad 3428 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 3429 clear_bit(i & (BITS_PER_LONG - 1),
3430 h->cmd_pool_bits + (i / BITS_PER_LONG));
e16a33ad 3431 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 3432}
3433
3434static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
3435{
3436 union u64bit temp64;
3437
3438 temp64.val32.lower = c->ErrDesc.Addr.lower;
3439 temp64.val32.upper = c->ErrDesc.Addr.upper;
3440 pci_free_consistent(h->pdev, sizeof(*c->err_info),
3441 c->err_info, (dma_addr_t) temp64.val);
3442 pci_free_consistent(h->pdev, sizeof(*c),
d896f3f3 3443 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
edd16368
SC		 3444}
3445
3446#ifdef CONFIG_COMPAT
3447
edd16368
SC		 3448static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
3449{
3450 IOCTL32_Command_struct __user *arg32 =
3451 (IOCTL32_Command_struct __user *) arg;
3452 IOCTL_Command_struct arg64;
3453 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
3454 int err;
3455 u32 cp;
3456
938abd84 3457 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 3458 err = 0;
3459 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
3460 sizeof(arg64.LUN_info));
3461 err |= copy_from_user(&arg64.Request, &arg32->Request,
3462 sizeof(arg64.Request));
3463 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
3464 sizeof(arg64.error_info));
3465 err |= get_user(arg64.buf_size, &arg32->buf_size);
3466 err |= get_user(cp, &arg32->buf);
3467 arg64.buf = compat_ptr(cp);
3468 err |= copy_to_user(p, &arg64, sizeof(arg64));
3469
3470 if (err)
3471 return -EFAULT;
3472
e39eeaed 3473 err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
edd16368
SC		 3474 if (err)
3475 return err;
3476 err |= copy_in_user(&arg32->error_info, &p->error_info,
3477 sizeof(arg32->error_info));
3478 if (err)
3479 return -EFAULT;
3480 return err;
3481}
3482
3483static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
3484 int cmd, void *arg)
3485{
3486 BIG_IOCTL32_Command_struct __user *arg32 =
3487 (BIG_IOCTL32_Command_struct __user *) arg;
3488 BIG_IOCTL_Command_struct arg64;
3489 BIG_IOCTL_Command_struct __user *p =
3490 compat_alloc_user_space(sizeof(arg64));
3491 int err;
3492 u32 cp;
3493
938abd84 3494 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 3495 err = 0;
3496 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
3497 sizeof(arg64.LUN_info));
3498 err |= copy_from_user(&arg64.Request, &arg32->Request,
3499 sizeof(arg64.Request));
3500 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
3501 sizeof(arg64.error_info));
3502 err |= get_user(arg64.buf_size, &arg32->buf_size);
3503 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
3504 err |= get_user(cp, &arg32->buf);
3505 arg64.buf = compat_ptr(cp);
3506 err |= copy_to_user(p, &arg64, sizeof(arg64));
3507
3508 if (err)
3509 return -EFAULT;
3510
e39eeaed 3511 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
edd16368
SC		 3512 if (err)
3513 return err;
3514 err |= copy_in_user(&arg32->error_info, &p->error_info,
3515 sizeof(arg32->error_info));
3516 if (err)
3517 return -EFAULT;
3518 return err;
3519}
71fe75a7
SC		 3520
3521static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
3522{
3523 switch (cmd) {
3524 case CCISS_GETPCIINFO:
3525 case CCISS_GETINTINFO:
3526 case CCISS_SETINTINFO:
3527 case CCISS_GETNODENAME:
3528 case CCISS_SETNODENAME:
3529 case CCISS_GETHEARTBEAT:
3530 case CCISS_GETBUSTYPES:
3531 case CCISS_GETFIRMVER:
3532 case CCISS_GETDRIVVER:
3533 case CCISS_REVALIDVOLS:
3534 case CCISS_DEREGDISK:
3535 case CCISS_REGNEWDISK:
3536 case CCISS_REGNEWD:
3537 case CCISS_RESCANDISK:
3538 case CCISS_GETLUNINFO:
3539 return hpsa_ioctl(dev, cmd, arg);
3540
3541 case CCISS_PASSTHRU32:
3542 return hpsa_ioctl32_passthru(dev, cmd, arg);
3543 case CCISS_BIG_PASSTHRU32:
3544 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
3545
3546 default:
3547 return -ENOIOCTLCMD;
3548 }
3549}
edd16368
SC		 3550#endif
3551
3552static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
3553{
3554 struct hpsa_pci_info pciinfo;
3555
3556 if (!argp)
3557 return -EINVAL;
3558 pciinfo.domain = pci_domain_nr(h->pdev->bus);
3559 pciinfo.bus = h->pdev->bus->number;
3560 pciinfo.dev_fn = h->pdev->devfn;
3561 pciinfo.board_id = h->board_id;
3562 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
3563 return -EFAULT;
3564 return 0;
3565}
3566
3567static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
3568{
3569 DriverVer_type DriverVer;
3570 unsigned char vmaj, vmin, vsubmin;
3571 int rc;
3572
3573 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
3574 &vmaj, &vmin, &vsubmin);
3575 if (rc != 3) {
3576 dev_info(&h->pdev->dev, "driver version string '%s' "
3577 "unrecognized.", HPSA_DRIVER_VERSION);
3578 vmaj = 0;
3579 vmin = 0;
3580 vsubmin = 0;
3581 }
3582 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
3583 if (!argp)
3584 return -EINVAL;
3585 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
3586 return -EFAULT;
3587 return 0;
3588}
3589
3590static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
3591{
3592 IOCTL_Command_struct iocommand;
3593 struct CommandList *c;
3594 char *buff = NULL;
3595 union u64bit temp64;
c1f63c8f 3596 int rc = 0;
edd16368
SC		 3597
3598 if (!argp)
3599 return -EINVAL;
3600 if (!capable(CAP_SYS_RAWIO))
3601 return -EPERM;
3602 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
3603 return -EFAULT;
3604 if ((iocommand.buf_size < 1) &&
3605 (iocommand.Request.Type.Direction != XFER_NONE)) {
3606 return -EINVAL;
3607 }
3608 if (iocommand.buf_size > 0) {
3609 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
3610 if (buff == NULL)
3611 return -EFAULT;
b03a7771
SC		 3612 if (iocommand.Request.Type.Direction == XFER_WRITE) {
3613 /* Copy the data into the buffer we created */
3614 if (copy_from_user(buff, iocommand.buf,
3615 iocommand.buf_size)) {
c1f63c8f
SC		 3616 rc = -EFAULT;
3617 goto out_kfree;
b03a7771
SC		 3618 }
3619 } else {
3620 memset(buff, 0, iocommand.buf_size);
edd16368 3621 }
b03a7771 3622 }
edd16368
SC		 3623 c = cmd_special_alloc(h);
3624 if (c == NULL) {
c1f63c8f
SC		 3625 rc = -ENOMEM;
3626 goto out_kfree;
edd16368
SC		 3627 }
3628 /* Fill in the command type */
3629 c->cmd_type = CMD_IOCTL_PEND;
3630 /* Fill in Command Header */
3631 c->Header.ReplyQueue = 0; /* unused in simple mode */
3632 if (iocommand.buf_size > 0) { /* buffer to fill */
3633 c->Header.SGList = 1;
3634 c->Header.SGTotal = 1;
3635 } else { /* no buffers to fill */
3636 c->Header.SGList = 0;
3637 c->Header.SGTotal = 0;
3638 }
3639 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
3640 /* use the kernel address the cmd block for tag */
3641 c->Header.Tag.lower = c->busaddr;
3642
3643 /* Fill in Request block */
3644 memcpy(&c->Request, &iocommand.Request,
3645 sizeof(c->Request));
3646
3647 /* Fill in the scatter gather information */
3648 if (iocommand.buf_size > 0) {
3649 temp64.val = pci_map_single(h->pdev, buff,
3650 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 3651 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
3652 c->SG[0].Addr.lower = 0;
3653 c->SG[0].Addr.upper = 0;
3654 c->SG[0].Len = 0;
3655 rc = -ENOMEM;
3656 goto out;
3657 }
edd16368
SC		 3658 c->SG[0].Addr.lower = temp64.val32.lower;
3659 c->SG[0].Addr.upper = temp64.val32.upper;
3660 c->SG[0].Len = iocommand.buf_size;
e1d9cbfa 3661 c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/
edd16368 3662 }
a0c12413 3663 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 3664 if (iocommand.buf_size > 0)
3665 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 3666 check_ioctl_unit_attention(h, c);
3667
3668 /* Copy the error information out */
3669 memcpy(&iocommand.error_info, c->err_info,
3670 sizeof(iocommand.error_info));
3671 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 3672 rc = -EFAULT;
3673 goto out;
edd16368 3674 }
b03a7771
SC		 3675 if (iocommand.Request.Type.Direction == XFER_READ &&
3676 iocommand.buf_size > 0) {
edd16368
SC		 3677 /* Copy the data out of the buffer we created */
3678 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 3679 rc = -EFAULT;
3680 goto out;
edd16368
SC		 3681 }
3682 }
c1f63c8f 3683out:
edd16368 3684 cmd_special_free(h, c);
c1f63c8f
SC		 3685out_kfree:
3686 kfree(buff);
3687 return rc;
edd16368
SC		 3688}
3689
3690static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
3691{
3692 BIG_IOCTL_Command_struct *ioc;
3693 struct CommandList *c;
3694 unsigned char **buff = NULL;
3695 int *buff_size = NULL;
3696 union u64bit temp64;
3697 BYTE sg_used = 0;
3698 int status = 0;
3699 int i;
01a02ffc
SC		 3700 u32 left;
3701 u32 sz;
edd16368
SC		 3702 BYTE __user *data_ptr;
3703
3704 if (!argp)
3705 return -EINVAL;
3706 if (!capable(CAP_SYS_RAWIO))
3707 return -EPERM;
3708 ioc = (BIG_IOCTL_Command_struct *)
3709 kmalloc(sizeof(*ioc), GFP_KERNEL);
3710 if (!ioc) {
3711 status = -ENOMEM;
3712 goto cleanup1;
3713 }
3714 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
3715 status = -EFAULT;
3716 goto cleanup1;
3717 }
3718 if ((ioc->buf_size < 1) &&
3719 (ioc->Request.Type.Direction != XFER_NONE)) {
3720 status = -EINVAL;
3721 goto cleanup1;
3722 }
3723 /* Check kmalloc limits using all SGs */
3724 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
3725 status = -EINVAL;
3726 goto cleanup1;
3727 }
d66ae08b 3728 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 3729 status = -EINVAL;
3730 goto cleanup1;
3731 }
d66ae08b 3732 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 3733 if (!buff) {
3734 status = -ENOMEM;
3735 goto cleanup1;
3736 }
d66ae08b 3737 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 3738 if (!buff_size) {
3739 status = -ENOMEM;
3740 goto cleanup1;
3741 }
3742 left = ioc->buf_size;
3743 data_ptr = ioc->buf;
3744 while (left) {
3745 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
3746 buff_size[sg_used] = sz;
3747 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
3748 if (buff[sg_used] == NULL) {
3749 status = -ENOMEM;
3750 goto cleanup1;
3751 }
3752 if (ioc->Request.Type.Direction == XFER_WRITE) {
3753 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
3754 status = -ENOMEM;
3755 goto cleanup1;
3756 }
3757 } else
3758 memset(buff[sg_used], 0, sz);
3759 left -= sz;
3760 data_ptr += sz;
3761 sg_used++;
3762 }
3763 c = cmd_special_alloc(h);
3764 if (c == NULL) {
3765 status = -ENOMEM;
3766 goto cleanup1;
3767 }
3768 c->cmd_type = CMD_IOCTL_PEND;
3769 c->Header.ReplyQueue = 0;
b03a7771 3770 c->Header.SGList = c->Header.SGTotal = sg_used;
edd16368
SC		 3771 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
3772 c->Header.Tag.lower = c->busaddr;
3773 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
3774 if (ioc->buf_size > 0) {
3775 int i;
3776 for (i = 0; i < sg_used; i++) {
3777 temp64.val = pci_map_single(h->pdev, buff[i],
3778 buff_size[i], PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 3779 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
3780 c->SG[i].Addr.lower = 0;
3781 c->SG[i].Addr.upper = 0;
3782 c->SG[i].Len = 0;
3783 hpsa_pci_unmap(h->pdev, c, i,
3784 PCI_DMA_BIDIRECTIONAL);
3785 status = -ENOMEM;
e2d4a1f6 3786 goto cleanup0;
bcc48ffa 3787 }
edd16368
SC		 3788 c->SG[i].Addr.lower = temp64.val32.lower;
3789 c->SG[i].Addr.upper = temp64.val32.upper;
3790 c->SG[i].Len = buff_size[i];
e1d9cbfa 3791 c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST;
edd16368
SC		 3792 }
3793 }
a0c12413 3794 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 3795 if (sg_used)
3796 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 3797 check_ioctl_unit_attention(h, c);
3798 /* Copy the error information out */
3799 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
3800 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 3801 status = -EFAULT;
e2d4a1f6 3802 goto cleanup0;
edd16368 3803 }
b03a7771 3804 if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
edd16368
SC		 3805 /* Copy the data out of the buffer we created */
3806 BYTE __user *ptr = ioc->buf;
3807 for (i = 0; i < sg_used; i++) {
3808 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 3809 status = -EFAULT;
e2d4a1f6 3810 goto cleanup0;
edd16368
SC		 3811 }
3812 ptr += buff_size[i];
3813 }
3814 }
edd16368 3815 status = 0;
e2d4a1f6
SC		 3816cleanup0:
3817 cmd_special_free(h, c);
edd16368
SC		 3818cleanup1:
3819 if (buff) {
3820 for (i = 0; i < sg_used; i++)
3821 kfree(buff[i]);
3822 kfree(buff);
3823 }
3824 kfree(buff_size);
3825 kfree(ioc);
3826 return status;
3827}
3828
3829static void check_ioctl_unit_attention(struct ctlr_info *h,
3830 struct CommandList *c)
3831{
3832 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
3833 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
3834 (void) check_for_unit_attention(h, c);
3835}
0390f0c0
SC		 3836
3837static int increment_passthru_count(struct ctlr_info *h)
3838{
3839 unsigned long flags;
3840
3841 spin_lock_irqsave(&h->passthru_count_lock, flags);
3842 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
3843 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
3844 return -1;
3845 }
3846 h->passthru_count++;
3847 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
3848 return 0;
3849}
3850
3851static void decrement_passthru_count(struct ctlr_info *h)
3852{
3853 unsigned long flags;
3854
3855 spin_lock_irqsave(&h->passthru_count_lock, flags);
3856 if (h->passthru_count <= 0) {
3857 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
3858 /* not expecting to get here. */
3859 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
3860 return;
3861 }
3862 h->passthru_count--;
3863 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
3864}
3865
edd16368
SC		 3866/*
3867 * ioctl
3868 */
3869static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
3870{
3871 struct ctlr_info *h;
3872 void __user *argp = (void __user *)arg;
0390f0c0 3873 int rc;
edd16368
SC		 3874
3875 h = sdev_to_hba(dev);
3876
3877 switch (cmd) {
3878 case CCISS_DEREGDISK:
3879 case CCISS_REGNEWDISK:
3880 case CCISS_REGNEWD:
a08a8471 3881 hpsa_scan_start(h->scsi_host);
edd16368
SC		 3882 return 0;
3883 case CCISS_GETPCIINFO:
3884 return hpsa_getpciinfo_ioctl(h, argp);
3885 case CCISS_GETDRIVVER:
3886 return hpsa_getdrivver_ioctl(h, argp);
3887 case CCISS_PASSTHRU:
0390f0c0
SC		 3888 if (increment_passthru_count(h))
3889 return -EAGAIN;
3890 rc = hpsa_passthru_ioctl(h, argp);
3891 decrement_passthru_count(h);
3892 return rc;
edd16368 3893 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 3894 if (increment_passthru_count(h))
3895 return -EAGAIN;
3896 rc = hpsa_big_passthru_ioctl(h, argp);
3897 decrement_passthru_count(h);
3898 return rc;
edd16368
SC		 3899 default:
3900 return -ENOTTY;
3901 }
3902}
3903
6f039790
GKH		 3904static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
3905 u8 reset_type)
64670ac8
SC		 3906{
3907 struct CommandList *c;
3908
3909 c = cmd_alloc(h);
3910 if (!c)
3911 return -ENOMEM;
a2dac136
SC		 3912 /* fill_cmd can't fail here, no data buffer to map */
3913 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 3914 RAID_CTLR_LUNID, TYPE_MSG);
3915 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
3916 c->waiting = NULL;
3917 enqueue_cmd_and_start_io(h, c);
3918 /* Don't wait for completion, the reset won't complete. Don't free
3919 * the command either. This is the last command we will send before
3920 * re-initializing everything, so it doesn't matter and won't leak.
3921 */
3922 return 0;
3923}
3924
a2dac136 3925static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
01a02ffc 3926 void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
edd16368
SC		 3927 int cmd_type)
3928{
3929 int pci_dir = XFER_NONE;
75167d2c 3930 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 3931
3932 c->cmd_type = CMD_IOCTL_PEND;
3933 c->Header.ReplyQueue = 0;
3934 if (buff != NULL && size > 0) {
3935 c->Header.SGList = 1;
3936 c->Header.SGTotal = 1;
3937 } else {
3938 c->Header.SGList = 0;
3939 c->Header.SGTotal = 0;
3940 }
3941 c->Header.Tag.lower = c->busaddr;
3942 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
3943
3944 c->Request.Type.Type = cmd_type;
3945 if (cmd_type == TYPE_CMD) {
3946 switch (cmd) {
3947 case HPSA_INQUIRY:
3948 /* are we trying to read a vital product page */
3949 if (page_code != 0) {
3950 c->Request.CDB[1] = 0x01;
3951 c->Request.CDB[2] = page_code;
3952 }
3953 c->Request.CDBLen = 6;
3954 c->Request.Type.Attribute = ATTR_SIMPLE;
3955 c->Request.Type.Direction = XFER_READ;
3956 c->Request.Timeout = 0;
3957 c->Request.CDB[0] = HPSA_INQUIRY;
3958 c->Request.CDB[4] = size & 0xFF;
3959 break;
3960 case HPSA_REPORT_LOG:
3961 case HPSA_REPORT_PHYS:
3962 /* Talking to controller so It's a physical command
3963 mode = 00 target = 0. Nothing to write.
3964 */
3965 c->Request.CDBLen = 12;
3966 c->Request.Type.Attribute = ATTR_SIMPLE;
3967 c->Request.Type.Direction = XFER_READ;
3968 c->Request.Timeout = 0;
3969 c->Request.CDB[0] = cmd;
3970 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
3971 c->Request.CDB[7] = (size >> 16) & 0xFF;
3972 c->Request.CDB[8] = (size >> 8) & 0xFF;
3973 c->Request.CDB[9] = size & 0xFF;
3974 break;
edd16368
SC		 3975 case HPSA_CACHE_FLUSH:
3976 c->Request.CDBLen = 12;
3977 c->Request.Type.Attribute = ATTR_SIMPLE;
3978 c->Request.Type.Direction = XFER_WRITE;
3979 c->Request.Timeout = 0;
3980 c->Request.CDB[0] = BMIC_WRITE;
3981 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 3982 c->Request.CDB[7] = (size >> 8) & 0xFF;
3983 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 3984 break;
3985 case TEST_UNIT_READY:
3986 c->Request.CDBLen = 6;
3987 c->Request.Type.Attribute = ATTR_SIMPLE;
3988 c->Request.Type.Direction = XFER_NONE;
3989 c->Request.Timeout = 0;
3990 break;
283b4a9b
SC		 3991 case HPSA_GET_RAID_MAP:
3992 c->Request.CDBLen = 12;
3993 c->Request.Type.Attribute = ATTR_SIMPLE;
3994 c->Request.Type.Direction = XFER_READ;
3995 c->Request.Timeout = 0;
3996 c->Request.CDB[0] = HPSA_CISS_READ;
3997 c->Request.CDB[1] = cmd;
3998 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
3999 c->Request.CDB[7] = (size >> 16) & 0xFF;
4000 c->Request.CDB[8] = (size >> 8) & 0xFF;
4001 c->Request.CDB[9] = size & 0xFF;
4002 break;
edd16368
SC		 4003 default:
4004 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
4005 BUG();
a2dac136 4006 return -1;
edd16368
SC		 4007 }
4008 } else if (cmd_type == TYPE_MSG) {
4009 switch (cmd) {
4010
4011 case HPSA_DEVICE_RESET_MSG:
4012 c->Request.CDBLen = 16;
4013 c->Request.Type.Type = 1; /* It is a MSG not a CMD */
4014 c->Request.Type.Attribute = ATTR_SIMPLE;
4015 c->Request.Type.Direction = XFER_NONE;
4016 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 4017 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
4018 c->Request.CDB[0] = cmd;
21e89afd 4019 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 4020 /* If bytes 4-7 are zero, it means reset the */
4021 /* LunID device */
4022 c->Request.CDB[4] = 0x00;
4023 c->Request.CDB[5] = 0x00;
4024 c->Request.CDB[6] = 0x00;
4025 c->Request.CDB[7] = 0x00;
75167d2c
SC		 4026 break;
4027 case HPSA_ABORT_MSG:
4028 a = buff; /* point to command to be aborted */
4029 dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n",
4030 a->Header.Tag.upper, a->Header.Tag.lower,
4031 c->Header.Tag.upper, c->Header.Tag.lower);
4032 c->Request.CDBLen = 16;
4033 c->Request.Type.Type = TYPE_MSG;
4034 c->Request.Type.Attribute = ATTR_SIMPLE;
4035 c->Request.Type.Direction = XFER_WRITE;
4036 c->Request.Timeout = 0; /* Don't time out */
4037 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
4038 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
4039 c->Request.CDB[2] = 0x00; /* reserved */
4040 c->Request.CDB[3] = 0x00; /* reserved */
4041 /* Tag to abort goes in CDB[4]-CDB[11] */
4042 c->Request.CDB[4] = a->Header.Tag.lower & 0xFF;
4043 c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF;
4044 c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF;
4045 c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF;
4046 c->Request.CDB[8] = a->Header.Tag.upper & 0xFF;
4047 c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF;
4048 c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF;
4049 c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF;
4050 c->Request.CDB[12] = 0x00; /* reserved */
4051 c->Request.CDB[13] = 0x00; /* reserved */
4052 c->Request.CDB[14] = 0x00; /* reserved */
4053 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 4054 break;
edd16368
SC		 4055 default:
4056 dev_warn(&h->pdev->dev, "unknown message type %d\n",
4057 cmd);
4058 BUG();
4059 }
4060 } else {
4061 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
4062 BUG();
4063 }
4064
4065 switch (c->Request.Type.Direction) {
4066 case XFER_READ:
4067 pci_dir = PCI_DMA_FROMDEVICE;
4068 break;
4069 case XFER_WRITE:
4070 pci_dir = PCI_DMA_TODEVICE;
4071 break;
4072 case XFER_NONE:
4073 pci_dir = PCI_DMA_NONE;
4074 break;
4075 default:
4076 pci_dir = PCI_DMA_BIDIRECTIONAL;
4077 }
a2dac136
SC		 4078 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
4079 return -1;
4080 return 0;
edd16368
SC		 4081}
4082
4083/*
4084 * Map (physical) PCI mem into (virtual) kernel space
4085 */
4086static void __iomem *remap_pci_mem(ulong base, ulong size)
4087{
4088 ulong page_base = ((ulong) base) & PAGE_MASK;
4089 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 4090 void __iomem *page_remapped = ioremap_nocache(page_base,
4091 page_offs + size);
edd16368
SC		 4092
4093 return page_remapped ? (page_remapped + page_offs) : NULL;
4094}
4095
4096/* Takes cmds off the submission queue and sends them to the hardware,
4097 * then puts them on the queue of cmds waiting for completion.
4098 */
4099static void start_io(struct ctlr_info *h)
4100{
4101 struct CommandList *c;
e16a33ad 4102 unsigned long flags;
edd16368 4103
e16a33ad 4104 spin_lock_irqsave(&h->lock, flags);
9e0fc764
SC		 4105 while (!list_empty(&h->reqQ)) {
4106 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 4107 /* can't do anything if fifo is full */
4108 if ((h->access.fifo_full(h))) {
396883e2 4109 h->fifo_recently_full = 1;
edd16368
SC		 4110 dev_warn(&h->pdev->dev, "fifo full\n");
4111 break;
4112 }
396883e2 4113 h->fifo_recently_full = 0;
edd16368
SC		 4114
4115 /* Get the first entry from the Request Q */
4116 removeQ(c);
4117 h->Qdepth--;
4118
edd16368
SC		 4119 /* Put job onto the completed Q */
4120 addQ(&h->cmpQ, c);
e16a33ad
MG		 4121
4122 /* Must increment commands_outstanding before unlocking
4123 * and submitting to avoid race checking for fifo full
4124 * condition.
4125 */
4126 h->commands_outstanding++;
4127 if (h->commands_outstanding > h->max_outstanding)
4128 h->max_outstanding = h->commands_outstanding;
4129
4130 /* Tell the controller execute command */
4131 spin_unlock_irqrestore(&h->lock, flags);
4132 h->access.submit_command(h, c);
4133 spin_lock_irqsave(&h->lock, flags);
edd16368 4134 }
e16a33ad 4135 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4136}
4137
254f796b 4138static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 4139{
254f796b 4140 return h->access.command_completed(h, q);
edd16368
SC		 4141}
4142
900c5440 4143static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 4144{
4145 return h->access.intr_pending(h);
4146}
4147
4148static inline long interrupt_not_for_us(struct ctlr_info *h)
4149{
10f66018
SC		 4150 return (h->access.intr_pending(h) == 0) ||
4151 (h->interrupts_enabled == 0);
edd16368
SC		 4152}
4153
01a02ffc
SC		 4154static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
4155 u32 raw_tag)
edd16368
SC		 4156{
4157 if (unlikely(tag_index >= h->nr_cmds)) {
4158 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
4159 return 1;
4160 }
4161 return 0;
4162}
4163
5a3d16f5 4164static inline void finish_cmd(struct CommandList *c)
edd16368 4165{
e16a33ad 4166 unsigned long flags;
396883e2
SC		 4167 int io_may_be_stalled = 0;
4168 struct ctlr_info *h = c->h;
e16a33ad 4169
396883e2 4170 spin_lock_irqsave(&h->lock, flags);
edd16368 4171 removeQ(c);
396883e2
SC		 4172
4173 /*
4174 * Check for possibly stalled i/o.
4175 *
4176 * If a fifo_full condition is encountered, requests will back up
4177 * in h->reqQ. This queue is only emptied out by start_io which is
4178 * only called when a new i/o request comes in. If no i/o's are
4179 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
4180 * start_io from here if we detect such a danger.
4181 *
4182 * Normally, we shouldn't hit this case, but pounding on the
4183 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
4184 * commands_outstanding is low. We want to avoid calling
4185 * start_io from in here as much as possible, and esp. don't
4186 * want to get in a cycle where we call start_io every time
4187 * through here.
4188 */
4189 if (unlikely(h->fifo_recently_full) &&
4190 h->commands_outstanding < 5)
4191 io_may_be_stalled = 1;
4192
4193 spin_unlock_irqrestore(&h->lock, flags);
4194
e85c5974 4195 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
e1f7de0c 4196 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI))
1fb011fb 4197 complete_scsi_command(c);
edd16368
SC		 4198 else if (c->cmd_type == CMD_IOCTL_PEND)
4199 complete(c->waiting);
396883e2
SC		 4200 if (unlikely(io_may_be_stalled))
4201 start_io(h);
edd16368
SC		 4202}
4203
a104c99f
SC		 4204static inline u32 hpsa_tag_contains_index(u32 tag)
4205{
a104c99f
SC		 4206 return tag & DIRECT_LOOKUP_BIT;
4207}
4208
4209static inline u32 hpsa_tag_to_index(u32 tag)
4210{
a104c99f
SC		 4211 return tag >> DIRECT_LOOKUP_SHIFT;
4212}
4213
a9a3a273
SC		 4214
4215static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 4216{
a9a3a273
SC		 4217#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
4218#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 4219 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 4220 return tag & ~HPSA_SIMPLE_ERROR_BITS;
4221 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 4222}
4223
303932fd 4224/* process completion of an indexed ("direct lookup") command */
1d94f94d 4225static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 4226 u32 raw_tag)
4227{
4228 u32 tag_index;
4229 struct CommandList *c;
4230
4231 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 4232 if (!bad_tag(h, tag_index, raw_tag)) {
4233 c = h->cmd_pool + tag_index;
4234 finish_cmd(c);
4235 }
303932fd
DB		 4236}
4237
4238/* process completion of a non-indexed command */
1d94f94d 4239static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 4240 u32 raw_tag)
4241{
4242 u32 tag;
4243 struct CommandList *c = NULL;
e16a33ad 4244 unsigned long flags;
303932fd 4245
a9a3a273 4246 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 4247 spin_lock_irqsave(&h->lock, flags);
9e0fc764 4248 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 4249 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 4250 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 4251 finish_cmd(c);
1d94f94d 4252 return;
303932fd
DB		 4253 }
4254 }
e16a33ad 4255 spin_unlock_irqrestore(&h->lock, flags);
303932fd 4256 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 4257}
4258
64670ac8
SC		 4259/* Some controllers, like p400, will give us one interrupt
4260 * after a soft reset, even if we turned interrupts off.
4261 * Only need to check for this in the hpsa_xxx_discard_completions
4262 * functions.
4263 */
4264static int ignore_bogus_interrupt(struct ctlr_info *h)
4265{
4266 if (likely(!reset_devices))
4267 return 0;
4268
4269 if (likely(h->interrupts_enabled))
4270 return 0;
4271
4272 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
4273 "(known firmware bug.) Ignoring.\n");
4274
4275 return 1;
4276}
4277
254f796b
MG		 4278/*
4279 * Convert &h->q[x] (passed to interrupt handlers) back to h.
4280 * Relies on (h-q[x] == x) being true for x such that
4281 * 0 <= x < MAX_REPLY_QUEUES.
4282 */
4283static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 4284{
254f796b
MG		 4285 return container_of((queue - *queue), struct ctlr_info, q[0]);
4286}
4287
4288static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
4289{
4290 struct ctlr_info *h = queue_to_hba(queue);
4291 u8 q = *(u8 *) queue;
64670ac8
SC		 4292 u32 raw_tag;
4293
4294 if (ignore_bogus_interrupt(h))
4295 return IRQ_NONE;
4296
4297 if (interrupt_not_for_us(h))
4298 return IRQ_NONE;
a0c12413 4299 h->last_intr_timestamp = get_jiffies_64();
64670ac8 4300 while (interrupt_pending(h)) {
254f796b 4301 raw_tag = get_next_completion(h, q);
64670ac8 4302 while (raw_tag != FIFO_EMPTY)
254f796b 4303 raw_tag = next_command(h, q);
64670ac8 4304 }
64670ac8
SC		 4305 return IRQ_HANDLED;
4306}
4307
254f796b 4308static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 4309{
254f796b 4310 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 4311 u32 raw_tag;
254f796b 4312 u8 q = *(u8 *) queue;
64670ac8
SC		 4313
4314 if (ignore_bogus_interrupt(h))
4315 return IRQ_NONE;
4316
a0c12413 4317 h->last_intr_timestamp = get_jiffies_64();
254f796b 4318 raw_tag = get_next_completion(h, q);
64670ac8 4319 while (raw_tag != FIFO_EMPTY)
254f796b 4320 raw_tag = next_command(h, q);
64670ac8
SC		 4321 return IRQ_HANDLED;
4322}
4323
254f796b 4324static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 4325{
254f796b 4326 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 4327 u32 raw_tag;
254f796b 4328 u8 q = *(u8 *) queue;
edd16368
SC		 4329
4330 if (interrupt_not_for_us(h))
4331 return IRQ_NONE;
a0c12413 4332 h->last_intr_timestamp = get_jiffies_64();
10f66018 4333 while (interrupt_pending(h)) {
254f796b 4334 raw_tag = get_next_completion(h, q);
10f66018 4335 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 4336 if (likely(hpsa_tag_contains_index(raw_tag)))
4337 process_indexed_cmd(h, raw_tag);
10f66018 4338 else
1d94f94d 4339 process_nonindexed_cmd(h, raw_tag);
254f796b 4340 raw_tag = next_command(h, q);
10f66018
SC		 4341 }
4342 }
10f66018
SC		 4343 return IRQ_HANDLED;
4344}
4345
254f796b 4346static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 4347{
254f796b 4348 struct ctlr_info *h = queue_to_hba(queue);
10f66018 4349 u32 raw_tag;
254f796b 4350 u8 q = *(u8 *) queue;
10f66018 4351
a0c12413 4352 h->last_intr_timestamp = get_jiffies_64();
254f796b 4353 raw_tag = get_next_completion(h, q);
303932fd 4354 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 4355 if (likely(hpsa_tag_contains_index(raw_tag)))
4356 process_indexed_cmd(h, raw_tag);
303932fd 4357 else
1d94f94d 4358 process_nonindexed_cmd(h, raw_tag);
254f796b 4359 raw_tag = next_command(h, q);
edd16368 4360 }
edd16368
SC		 4361 return IRQ_HANDLED;
4362}
4363
a9a3a273
SC		 4364/* Send a message CDB to the firmware. Careful, this only works
4365 * in simple mode, not performant mode due to the tag lookup.
4366 * We only ever use this immediately after a controller reset.
4367 */
6f039790
GKH		 4368static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
4369 unsigned char type)
edd16368
SC		 4370{
4371 struct Command {
4372 struct CommandListHeader CommandHeader;
4373 struct RequestBlock Request;
4374 struct ErrDescriptor ErrorDescriptor;
4375 };
4376 struct Command *cmd;
4377 static const size_t cmd_sz = sizeof(*cmd) +
4378 sizeof(cmd->ErrorDescriptor);
4379 dma_addr_t paddr64;
4380 uint32_t paddr32, tag;
4381 void __iomem *vaddr;
4382 int i, err;
4383
4384 vaddr = pci_ioremap_bar(pdev, 0);
4385 if (vaddr == NULL)
4386 return -ENOMEM;
4387
4388 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
4389 * CCISS commands, so they must be allocated from the lower 4GiB of
4390 * memory.
4391 */
4392 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4393 if (err) {
4394 iounmap(vaddr);
4395 return -ENOMEM;
4396 }
4397
4398 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
4399 if (cmd == NULL) {
4400 iounmap(vaddr);
4401 return -ENOMEM;
4402 }
4403
4404 /* This must fit, because of the 32-bit consistent DMA mask. Also,
4405 * although there's no guarantee, we assume that the address is at
4406 * least 4-byte aligned (most likely, it's page-aligned).
4407 */
4408 paddr32 = paddr64;
4409
4410 cmd->CommandHeader.ReplyQueue = 0;
4411 cmd->CommandHeader.SGList = 0;
4412 cmd->CommandHeader.SGTotal = 0;
4413 cmd->CommandHeader.Tag.lower = paddr32;
4414 cmd->CommandHeader.Tag.upper = 0;
4415 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
4416
4417 cmd->Request.CDBLen = 16;
4418 cmd->Request.Type.Type = TYPE_MSG;
4419 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
4420 cmd->Request.Type.Direction = XFER_NONE;
4421 cmd->Request.Timeout = 0; /* Don't time out */
4422 cmd->Request.CDB[0] = opcode;
4423 cmd->Request.CDB[1] = type;
4424 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
4425 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
4426 cmd->ErrorDescriptor.Addr.upper = 0;
4427 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
4428
4429 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
4430
4431 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
4432 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
a9a3a273 4433 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
edd16368
SC		 4434 break;
4435 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
4436 }
4437
4438 iounmap(vaddr);
4439
4440 /* we leak the DMA buffer here ... no choice since the controller could
4441 * still complete the command.
4442 */
4443 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
4444 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
4445 opcode, type);
4446 return -ETIMEDOUT;
4447 }
4448
4449 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
4450
4451 if (tag & HPSA_ERROR_BIT) {
4452 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
4453 opcode, type);
4454 return -EIO;
4455 }
4456
4457 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
4458 opcode, type);
4459 return 0;
4460}
4461
edd16368
SC		 4462#define hpsa_noop(p) hpsa_message(p, 3, 0)
4463
1df8552a 4464static int hpsa_controller_hard_reset(struct pci_dev *pdev,
cf0b08d0 4465 void * __iomem vaddr, u32 use_doorbell)
1df8552a
SC		 4466{
4467 u16 pmcsr;
4468 int pos;
4469
4470 if (use_doorbell) {
4471 /* For everything after the P600, the PCI power state method
4472 * of resetting the controller doesn't work, so we have this
4473 * other way using the doorbell register.
4474 */
4475 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 4476 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239
SC		 4477
4478 /* PMC hardware guys tell us we need a 5 second delay after
4479 * doorbell reset and before any attempt to talk to the board
4480 * at all to ensure that this actually works and doesn't fall
4481 * over in some weird corner cases.
4482 */
4483 msleep(5000);
1df8552a
SC		 4484 } else { /* Try to do it the PCI power state way */
4485
4486 /* Quoting from the Open CISS Specification: "The Power
4487 * Management Control/Status Register (CSR) controls the power
4488 * state of the device. The normal operating state is D0,
4489 * CSR=00h. The software off state is D3, CSR=03h. To reset
4490 * the controller, place the interface device in D3 then to D0,
4491 * this causes a secondary PCI reset which will reset the
4492 * controller." */
4493
4494 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
4495 if (pos == 0) {
4496 dev_err(&pdev->dev,
4497 "hpsa_reset_controller: "
4498 "PCI PM not supported\n");
4499 return -ENODEV;
4500 }
4501 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
4502 /* enter the D3hot power management state */
4503 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
4504 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4505 pmcsr |= PCI_D3hot;
4506 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
4507
4508 msleep(500);
4509
4510 /* enter the D0 power management state */
4511 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4512 pmcsr |= PCI_D0;
4513 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
c4853efe
MM		 4514
4515 /*
4516 * The P600 requires a small delay when changing states.
4517 * Otherwise we may think the board did not reset and we bail.
4518 * This for kdump only and is particular to the P600.
4519 */
4520 msleep(500);
1df8552a
SC		 4521 }
4522 return 0;
4523}
4524
6f039790 4525static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 4526{
4527 memset(driver_version, 0, len);
f79cfec6 4528 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 4529}
4530
6f039790 4531static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 4532{
4533 char *driver_version;
4534 int i, size = sizeof(cfgtable->driver_version);
4535
4536 driver_version = kmalloc(size, GFP_KERNEL);
4537 if (!driver_version)
4538 return -ENOMEM;
4539
4540 init_driver_version(driver_version, size);
4541 for (i = 0; i < size; i++)
4542 writeb(driver_version[i], &cfgtable->driver_version[i]);
4543 kfree(driver_version);
4544 return 0;
4545}
4546
6f039790
GKH		 4547static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
4548 unsigned char *driver_ver)
580ada3c
SC		 4549{
4550 int i;
4551
4552 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
4553 driver_ver[i] = readb(&cfgtable->driver_version[i]);
4554}
4555
6f039790 4556static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 4557{
4558
4559 char *driver_ver, *old_driver_ver;
4560 int rc, size = sizeof(cfgtable->driver_version);
4561
4562 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
4563 if (!old_driver_ver)
4564 return -ENOMEM;
4565 driver_ver = old_driver_ver + size;
4566
4567 /* After a reset, the 32 bytes of "driver version" in the cfgtable
4568 * should have been changed, otherwise we know the reset failed.
4569 */
4570 init_driver_version(old_driver_ver, size);
4571 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
4572 rc = !memcmp(driver_ver, old_driver_ver, size);
4573 kfree(old_driver_ver);
4574 return rc;
4575}
edd16368 4576/* This does a hard reset of the controller using PCI power management
1df8552a 4577 * states or the using the doorbell register.
edd16368 4578 */
6f039790 4579static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 4580{
1df8552a
SC		 4581 u64 cfg_offset;
4582 u32 cfg_base_addr;
4583 u64 cfg_base_addr_index;
4584 void __iomem *vaddr;
4585 unsigned long paddr;
580ada3c 4586 u32 misc_fw_support;
270d05de 4587 int rc;
1df8552a 4588 struct CfgTable __iomem *cfgtable;
cf0b08d0 4589 u32 use_doorbell;
18867659 4590 u32 board_id;
270d05de 4591 u16 command_register;
edd16368 4592
1df8552a
SC		 4593 /* For controllers as old as the P600, this is very nearly
4594 * the same thing as
edd16368
SC		 4595 *
4596 * pci_save_state(pci_dev);
4597 * pci_set_power_state(pci_dev, PCI_D3hot);
4598 * pci_set_power_state(pci_dev, PCI_D0);
4599 * pci_restore_state(pci_dev);
4600 *
1df8552a
SC		 4601 * For controllers newer than the P600, the pci power state
4602 * method of resetting doesn't work so we have another way
4603 * using the doorbell register.
edd16368 4604 */
18867659 4605
25c1e56a 4606 rc = hpsa_lookup_board_id(pdev, &board_id);
46380786 4607 if (rc < 0 || !ctlr_is_resettable(board_id)) {
25c1e56a
SC		 4608 dev_warn(&pdev->dev, "Not resetting device.\n");
4609 return -ENODEV;
4610 }
46380786
SC		 4611
4612 /* if controller is soft- but not hard resettable... */
4613 if (!ctlr_is_hard_resettable(board_id))
4614 return -ENOTSUPP; /* try soft reset later. */
18867659 4615
270d05de
SC		 4616 /* Save the PCI command register */
4617 pci_read_config_word(pdev, 4, &command_register);
4618 /* Turn the board off. This is so that later pci_restore_state()
4619 * won't turn the board on before the rest of config space is ready.
4620 */
4621 pci_disable_device(pdev);
4622 pci_save_state(pdev);
edd16368 4623
1df8552a
SC		 4624 /* find the first memory BAR, so we can find the cfg table */
4625 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
4626 if (rc)
4627 return rc;
4628 vaddr = remap_pci_mem(paddr, 0x250);
4629 if (!vaddr)
4630 return -ENOMEM;
edd16368 4631
1df8552a
SC		 4632 /* find cfgtable in order to check if reset via doorbell is supported */
4633 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
4634 &cfg_base_addr_index, &cfg_offset);
4635 if (rc)
4636 goto unmap_vaddr;
4637 cfgtable = remap_pci_mem(pci_resource_start(pdev,
4638 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
4639 if (!cfgtable) {
4640 rc = -ENOMEM;
4641 goto unmap_vaddr;
4642 }
580ada3c
SC		 4643 rc = write_driver_ver_to_cfgtable(cfgtable);
4644 if (rc)
4645 goto unmap_vaddr;
edd16368 4646
cf0b08d0
SC		 4647 /* If reset via doorbell register is supported, use that.
4648 * There are two such methods. Favor the newest method.
4649 */
1df8552a 4650 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 4651 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
4652 if (use_doorbell) {
4653 use_doorbell = DOORBELL_CTLR_RESET2;
4654 } else {
4655 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
4656 if (use_doorbell) {
fba63097
MM		 4657 dev_warn(&pdev->dev, "Soft reset not supported. "
4658 "Firmware update is required.\n");
64670ac8 4659 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 4660 goto unmap_cfgtable;
4661 }
4662 }
edd16368 4663
1df8552a
SC		 4664 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
4665 if (rc)
4666 goto unmap_cfgtable;
edd16368 4667
270d05de
SC		 4668 pci_restore_state(pdev);
4669 rc = pci_enable_device(pdev);
4670 if (rc) {
4671 dev_warn(&pdev->dev, "failed to enable device.\n");
4672 goto unmap_cfgtable;
edd16368 4673 }
270d05de 4674 pci_write_config_word(pdev, 4, command_register);
edd16368 4675
1df8552a
SC		 4676 /* Some devices (notably the HP Smart Array 5i Controller)
4677 need a little pause here */
4678 msleep(HPSA_POST_RESET_PAUSE_MSECS);
4679
fe5389c8
SC		 4680 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
4681 if (rc) {
4682 dev_warn(&pdev->dev,
64670ac8
SC		 4683 "failed waiting for board to become ready "
4684 "after hard reset\n");
fe5389c8
SC		 4685 goto unmap_cfgtable;
4686 }
fe5389c8 4687
580ada3c
SC		 4688 rc = controller_reset_failed(vaddr);
4689 if (rc < 0)
4690 goto unmap_cfgtable;
4691 if (rc) {
64670ac8
SC		 4692 dev_warn(&pdev->dev, "Unable to successfully reset "
4693 "controller. Will try soft reset.\n");
4694 rc = -ENOTSUPP;
580ada3c 4695 } else {
64670ac8 4696 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 4697 }
4698
4699unmap_cfgtable:
4700 iounmap(cfgtable);
4701
4702unmap_vaddr:
4703 iounmap(vaddr);
4704 return rc;
edd16368
SC		 4705}
4706
4707/*
4708 * We cannot read the structure directly, for portability we must use
4709 * the io functions.
4710 * This is for debug only.
4711 */
edd16368
SC		 4712static void print_cfg_table(struct device *dev, struct CfgTable *tb)
4713{
58f8665c 4714#ifdef HPSA_DEBUG
edd16368
SC		 4715 int i;
4716 char temp_name[17];
4717
4718 dev_info(dev, "Controller Configuration information\n");
4719 dev_info(dev, "------------------------------------\n");
4720 for (i = 0; i < 4; i++)
4721 temp_name[i] = readb(&(tb->Signature[i]));
4722 temp_name[4] = '\0';
4723 dev_info(dev, " Signature = %s\n", temp_name);
4724 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
4725 dev_info(dev, " Transport methods supported = 0x%x\n",
4726 readl(&(tb->TransportSupport)));
4727 dev_info(dev, " Transport methods active = 0x%x\n",
4728 readl(&(tb->TransportActive)));
4729 dev_info(dev, " Requested transport Method = 0x%x\n",
4730 readl(&(tb->HostWrite.TransportRequest)));
4731 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
4732 readl(&(tb->HostWrite.CoalIntDelay)));
4733 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
4734 readl(&(tb->HostWrite.CoalIntCount)));
4735 dev_info(dev, " Max outstanding commands = 0x%d\n",
4736 readl(&(tb->CmdsOutMax)));
4737 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
4738 for (i = 0; i < 16; i++)
4739 temp_name[i] = readb(&(tb->ServerName[i]));
4740 temp_name[16] = '\0';
4741 dev_info(dev, " Server Name = %s\n", temp_name);
4742 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
4743 readl(&(tb->HeartBeat)));
edd16368 4744#endif /* HPSA_DEBUG */
58f8665c 4745}
edd16368
SC		 4746
4747static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
4748{
4749 int i, offset, mem_type, bar_type;
4750
4751 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
4752 return 0;
4753 offset = 0;
4754 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4755 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
4756 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
4757 offset += 4;
4758 else {
4759 mem_type = pci_resource_flags(pdev, i) &
4760 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
4761 switch (mem_type) {
4762 case PCI_BASE_ADDRESS_MEM_TYPE_32:
4763 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
4764 offset += 4; /* 32 bit */
4765 break;
4766 case PCI_BASE_ADDRESS_MEM_TYPE_64:
4767 offset += 8;
4768 break;
4769 default: /* reserved in PCI 2.2 */
4770 dev_warn(&pdev->dev,
4771 "base address is invalid\n");
4772 return -1;
4773 break;
4774 }
4775 }
4776 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
4777 return i + 1;
4778 }
4779 return -1;
4780}
4781
4782/* If MSI/MSI-X is supported by the kernel we will try to enable it on
4783 * controllers that are capable. If not, we use IO-APIC mode.
4784 */
4785
6f039790 4786static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 4787{
4788#ifdef CONFIG_PCI_MSI
254f796b
MG		 4789 int err, i;
4790 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
4791
4792 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
4793 hpsa_msix_entries[i].vector = 0;
4794 hpsa_msix_entries[i].entry = i;
4795 }
edd16368
SC		 4796
4797 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 4798 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
4799 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 4800 goto default_int_mode;
55c06c71
SC		 4801 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
4802 dev_info(&h->pdev->dev, "MSIX\n");
eee0f03a 4803 h->msix_vector = MAX_REPLY_QUEUES;
254f796b 4804 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
eee0f03a 4805 h->msix_vector);
edd16368 4806 if (err > 0) {
55c06c71 4807 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 4808 "available\n", err);
eee0f03a
HR		 4809 h->msix_vector = err;
4810 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
4811 h->msix_vector);
4812 }
4813 if (!err) {
4814 for (i = 0; i < h->msix_vector; i++)
4815 h->intr[i] = hpsa_msix_entries[i].vector;
4816 return;
edd16368 4817 } else {
55c06c71 4818 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
edd16368 4819 err);
eee0f03a 4820 h->msix_vector = 0;
edd16368
SC		 4821 goto default_int_mode;
4822 }
4823 }
55c06c71
SC		 4824 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
4825 dev_info(&h->pdev->dev, "MSI\n");
4826 if (!pci_enable_msi(h->pdev))
edd16368
SC		 4827 h->msi_vector = 1;
4828 else
55c06c71 4829 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 4830 }
4831default_int_mode:
4832#endif /* CONFIG_PCI_MSI */
4833 /* if we get here we're going to use the default interrupt mode */
a9a3a273 4834 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 4835}
4836
6f039790 4837static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 4838{
4839 int i;
4840 u32 subsystem_vendor_id, subsystem_device_id;
4841
4842 subsystem_vendor_id = pdev->subsystem_vendor;
4843 subsystem_device_id = pdev->subsystem_device;
4844 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
4845 subsystem_vendor_id;
4846
4847 for (i = 0; i < ARRAY_SIZE(products); i++)
4848 if (*board_id == products[i].board_id)
4849 return i;
4850
6798cc0a
SC		 4851 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
4852 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
4853 !hpsa_allow_any) {
e5c880d1
SC		 4854 dev_warn(&pdev->dev, "unrecognized board ID: "
4855 "0x%08x, ignoring.\n", *board_id);
4856 return -ENODEV;
4857 }
4858 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
4859}
4860
6f039790
GKH		 4861static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
4862 unsigned long *memory_bar)
3a7774ce
SC		 4863{
4864 int i;
4865
4866 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 4867 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 4868 /* addressing mode bits already removed */
12d2cd47
SC		 4869 *memory_bar = pci_resource_start(pdev, i);
4870 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 4871 *memory_bar);
4872 return 0;
4873 }
12d2cd47 4874 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 4875 return -ENODEV;
4876}
4877
6f039790
GKH		 4878static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
4879 int wait_for_ready)
2c4c8c8b 4880{
fe5389c8 4881 int i, iterations;
2c4c8c8b 4882 u32 scratchpad;
fe5389c8
SC		 4883 if (wait_for_ready)
4884 iterations = HPSA_BOARD_READY_ITERATIONS;
4885 else
4886 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 4887
fe5389c8
SC		 4888 for (i = 0; i < iterations; i++) {
4889 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
4890 if (wait_for_ready) {
4891 if (scratchpad == HPSA_FIRMWARE_READY)
4892 return 0;
4893 } else {
4894 if (scratchpad != HPSA_FIRMWARE_READY)
4895 return 0;
4896 }
2c4c8c8b
SC		 4897 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
4898 }
fe5389c8 4899 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 4900 return -ENODEV;
4901}
4902
6f039790
GKH		 4903static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
4904 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
4905 u64 *cfg_offset)
a51fd47f
SC		 4906{
4907 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
4908 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
4909 *cfg_base_addr &= (u32) 0x0000ffff;
4910 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
4911 if (*cfg_base_addr_index == -1) {
4912 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
4913 return -ENODEV;
4914 }
4915 return 0;
4916}
4917
6f039790 4918static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 4919{
01a02ffc
SC		 4920 u64 cfg_offset;
4921 u32 cfg_base_addr;
4922 u64 cfg_base_addr_index;
303932fd 4923 u32 trans_offset;
a51fd47f 4924 int rc;
77c4495c 4925
a51fd47f
SC		 4926 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
4927 &cfg_base_addr_index, &cfg_offset);
4928 if (rc)
4929 return rc;
77c4495c 4930 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 4931 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
77c4495c
SC		 4932 if (!h->cfgtable)
4933 return -ENOMEM;
580ada3c
SC		 4934 rc = write_driver_ver_to_cfgtable(h->cfgtable);
4935 if (rc)
4936 return rc;
77c4495c 4937 /* Find performant mode table. */
a51fd47f 4938 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 4939 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
4940 cfg_base_addr_index)+cfg_offset+trans_offset,
4941 sizeof(*h->transtable));
4942 if (!h->transtable)
4943 return -ENOMEM;
4944 return 0;
4945}
4946
6f039790 4947static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 4948{
4949 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 4950
4951 /* Limit commands in memory limited kdump scenario. */
4952 if (reset_devices && h->max_commands > 32)
4953 h->max_commands = 32;
4954
cba3d38b
SC		 4955 if (h->max_commands < 16) {
4956 dev_warn(&h->pdev->dev, "Controller reports "
4957 "max supported commands of %d, an obvious lie. "
4958 "Using 16. Ensure that firmware is up to date.\n",
4959 h->max_commands);
4960 h->max_commands = 16;
4961 }
4962}
4963
b93d7536
SC		 4964/* Interrogate the hardware for some limits:
4965 * max commands, max SG elements without chaining, and with chaining,
4966 * SG chain block size, etc.
4967 */
6f039790 4968static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 4969{
cba3d38b 4970 hpsa_get_max_perf_mode_cmds(h);
b93d7536
SC		 4971 h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
4972 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 4973 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
b93d7536
SC		 4974 /*
4975 * Limit in-command s/g elements to 32 save dma'able memory.
4976 * Howvever spec says if 0, use 31
4977 */
4978 h->max_cmd_sg_entries = 31;
4979 if (h->maxsgentries > 512) {
4980 h->max_cmd_sg_entries = 32;
4981 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
4982 h->maxsgentries--; /* save one for chain pointer */
4983 } else {
4984 h->maxsgentries = 31; /* default to traditional values */
4985 h->chainsize = 0;
4986 }
75167d2c
SC		 4987
4988 /* Find out what task management functions are supported and cache */
4989 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
b93d7536
SC		 4990}
4991
76c46e49
SC		 4992static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
4993{
0fc9fd40 4994 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
76c46e49
SC		 4995 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
4996 return false;
4997 }
4998 return true;
4999}
5000
97a5e98c 5001static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 5002{
97a5e98c 5003 u32 driver_support;
f7c39101 5004
28e13446
SC		 5005#ifdef CONFIG_X86
5006 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
97a5e98c
SC		 5007 driver_support = readl(&(h->cfgtable->driver_support));
5008 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 5009#endif
28e13446
SC		 5010 driver_support |= ENABLE_UNIT_ATTN;
5011 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 5012}
5013
3d0eab67
SC		 5014/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
5015 * in a prefetch beyond physical memory.
5016 */
5017static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
5018{
5019 u32 dma_prefetch;
5020
5021 if (h->board_id != 0x3225103C)
5022 return;
5023 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
5024 dma_prefetch |= 0x8000;
5025 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
5026}
5027
6f039790 5028static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 5029{
5030 int i;
6eaf46fd
SC		 5031 u32 doorbell_value;
5032 unsigned long flags;
eb6b2ae9
SC		 5033
5034 /* under certain very rare conditions, this can take awhile.
5035 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
5036 * as we enter this code.)
5037 */
5038 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 5039 spin_lock_irqsave(&h->lock, flags);
5040 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
5041 spin_unlock_irqrestore(&h->lock, flags);
382be668 5042 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 5043 break;
5044 /* delay and try again */
60d3f5b0 5045 usleep_range(10000, 20000);
eb6b2ae9 5046 }
3f4336f3
SC		 5047}
5048
6f039790 5049static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 5050{
5051 u32 trans_support;
5052
5053 trans_support = readl(&(h->cfgtable->TransportSupport));
5054 if (!(trans_support & SIMPLE_MODE))
5055 return -ENOTSUPP;
5056
5057 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 5058
3f4336f3
SC		 5059 /* Update the field, and then ring the doorbell */
5060 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
5061 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
5062 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 5063 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 5064 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
5065 goto error;
960a30e7 5066 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 5067 return 0;
283b4a9b
SC		 5068error:
5069 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
5070 return -ENODEV;
eb6b2ae9
SC		 5071}
5072
6f039790 5073static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 5074{
eb6b2ae9 5075 int prod_index, err;
edd16368 5076
e5c880d1
SC		 5077 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
5078 if (prod_index < 0)
5079 return -ENODEV;
5080 h->product_name = products[prod_index].product_name;
5081 h->access = *(products[prod_index].access);
edd16368 5082
e5a44df8
MG		 5083 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
5084 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
5085
55c06c71 5086 err = pci_enable_device(h->pdev);
edd16368 5087 if (err) {
55c06c71 5088 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 5089 return err;
5090 }
5091
5cb460a6
SC		 5092 /* Enable bus mastering (pci_disable_device may disable this) */
5093 pci_set_master(h->pdev);
5094
f79cfec6 5095 err = pci_request_regions(h->pdev, HPSA);
edd16368 5096 if (err) {
55c06c71
SC		 5097 dev_err(&h->pdev->dev,
5098 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 5099 return err;
5100 }
6b3f4c52 5101 hpsa_interrupt_mode(h);
12d2cd47 5102 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 5103 if (err)
edd16368 5104 goto err_out_free_res;
edd16368 5105 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 5106 if (!h->vaddr) {
5107 err = -ENOMEM;
5108 goto err_out_free_res;
5109 }
fe5389c8 5110 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 5111 if (err)
edd16368 5112 goto err_out_free_res;
77c4495c
SC		 5113 err = hpsa_find_cfgtables(h);
5114 if (err)
edd16368 5115 goto err_out_free_res;
b93d7536 5116 hpsa_find_board_params(h);
edd16368 5117
76c46e49 5118 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 5119 err = -ENODEV;
5120 goto err_out_free_res;
5121 }
97a5e98c 5122 hpsa_set_driver_support_bits(h);
3d0eab67 5123 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 5124 err = hpsa_enter_simple_mode(h);
5125 if (err)
edd16368 5126 goto err_out_free_res;
edd16368
SC		 5127 return 0;
5128
5129err_out_free_res:
204892e9
SC		 5130 if (h->transtable)
5131 iounmap(h->transtable);
5132 if (h->cfgtable)
5133 iounmap(h->cfgtable);
5134 if (h->vaddr)
5135 iounmap(h->vaddr);
f0bd0b68 5136 pci_disable_device(h->pdev);
55c06c71 5137 pci_release_regions(h->pdev);
edd16368
SC		 5138 return err;
5139}
5140
6f039790 5141static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 5142{
5143 int rc;
5144
5145#define HBA_INQUIRY_BYTE_COUNT 64
5146 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
5147 if (!h->hba_inquiry_data)
5148 return;
5149 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
5150 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
5151 if (rc != 0) {
5152 kfree(h->hba_inquiry_data);
5153 h->hba_inquiry_data = NULL;
5154 }
5155}
5156
6f039790 5157static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 5158{
1df8552a 5159 int rc, i;
4c2a8c40
SC		 5160
5161 if (!reset_devices)
5162 return 0;
5163
1df8552a
SC		 5164 /* Reset the controller with a PCI power-cycle or via doorbell */
5165 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 5166
1df8552a
SC		 5167 /* -ENOTSUPP here means we cannot reset the controller
5168 * but it's already (and still) up and running in
18867659
SC		 5169 * "performant mode". Or, it might be 640x, which can't reset
5170 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a
SC		 5171 */
5172 if (rc == -ENOTSUPP)
64670ac8 5173 return rc; /* just try to do the kdump anyhow. */
1df8552a
SC		 5174 if (rc)
5175 return -ENODEV;
4c2a8c40
SC		 5176
5177 /* Now try to get the controller to respond to a no-op */
2b870cb3 5178 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 5179 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
5180 if (hpsa_noop(pdev) == 0)
5181 break;
5182 else
5183 dev_warn(&pdev->dev, "no-op failed%s\n",
5184 (i < 11 ? "; re-trying" : ""));
5185 }
5186 return 0;
5187}
5188
6f039790 5189static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 5190{
5191 h->cmd_pool_bits = kzalloc(
5192 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
5193 sizeof(unsigned long), GFP_KERNEL);
5194 h->cmd_pool = pci_alloc_consistent(h->pdev,
5195 h->nr_cmds * sizeof(*h->cmd_pool),
5196 &(h->cmd_pool_dhandle));
5197 h->errinfo_pool = pci_alloc_consistent(h->pdev,
5198 h->nr_cmds * sizeof(*h->errinfo_pool),
5199 &(h->errinfo_pool_dhandle));
5200 if ((h->cmd_pool_bits == NULL)
5201 || (h->cmd_pool == NULL)
5202 || (h->errinfo_pool == NULL)) {
5203 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
5204 return -ENOMEM;
5205 }
5206 return 0;
5207}
5208
5209static void hpsa_free_cmd_pool(struct ctlr_info *h)
5210{
5211 kfree(h->cmd_pool_bits);
5212 if (h->cmd_pool)
5213 pci_free_consistent(h->pdev,
5214 h->nr_cmds * sizeof(struct CommandList),
5215 h->cmd_pool, h->cmd_pool_dhandle);
5216 if (h->errinfo_pool)
5217 pci_free_consistent(h->pdev,
5218 h->nr_cmds * sizeof(struct ErrorInfo),
5219 h->errinfo_pool,
5220 h->errinfo_pool_dhandle);
e1f7de0c
MG		 5221 if (h->ioaccel_cmd_pool)
5222 pci_free_consistent(h->pdev,
5223 h->nr_cmds * sizeof(struct io_accel1_cmd),
5224 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 5225}
5226
0ae01a32
SC		 5227static int hpsa_request_irq(struct ctlr_info *h,
5228 irqreturn_t (*msixhandler)(int, void *),
5229 irqreturn_t (*intxhandler)(int, void *))
5230{
254f796b 5231 int rc, i;
0ae01a32 5232
254f796b
MG		 5233 /*
5234 * initialize h->q[x] = x so that interrupt handlers know which
5235 * queue to process.
5236 */
5237 for (i = 0; i < MAX_REPLY_QUEUES; i++)
5238 h->q[i] = (u8) i;
5239
eee0f03a 5240 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 5241 /* If performant mode and MSI-X, use multiple reply queues */
eee0f03a 5242 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 5243 rc = request_irq(h->intr[i], msixhandler,
5244 0, h->devname,
5245 &h->q[i]);
5246 } else {
5247 /* Use single reply pool */
eee0f03a 5248 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 5249 rc = request_irq(h->intr[h->intr_mode],
5250 msixhandler, 0, h->devname,
5251 &h->q[h->intr_mode]);
5252 } else {
5253 rc = request_irq(h->intr[h->intr_mode],
5254 intxhandler, IRQF_SHARED, h->devname,
5255 &h->q[h->intr_mode]);
5256 }
5257 }
0ae01a32
SC		 5258 if (rc) {
5259 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
5260 h->intr[h->intr_mode], h->devname);
5261 return -ENODEV;
5262 }
5263 return 0;
5264}
5265
6f039790 5266static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 5267{
5268 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
5269 HPSA_RESET_TYPE_CONTROLLER)) {
5270 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
5271 return -EIO;
5272 }
5273
5274 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
5275 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
5276 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
5277 return -1;
5278 }
5279
5280 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
5281 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
5282 dev_warn(&h->pdev->dev, "Board failed to become ready "
5283 "after soft reset.\n");
5284 return -1;
5285 }
5286
5287 return 0;
5288}
5289
254f796b
MG		 5290static void free_irqs(struct ctlr_info *h)
5291{
5292 int i;
5293
5294 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
5295 /* Single reply queue, only one irq to free */
5296 i = h->intr_mode;
5297 free_irq(h->intr[i], &h->q[i]);
5298 return;
5299 }
5300
eee0f03a 5301 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 5302 free_irq(h->intr[i], &h->q[i]);
5303}
5304
0097f0f4 5305static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 5306{
254f796b 5307 free_irqs(h);
64670ac8 5308#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 5309 if (h->msix_vector) {
5310 if (h->pdev->msix_enabled)
5311 pci_disable_msix(h->pdev);
5312 } else if (h->msi_vector) {
5313 if (h->pdev->msi_enabled)
5314 pci_disable_msi(h->pdev);
5315 }
64670ac8 5316#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 5317}
5318
5319static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
5320{
5321 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 5322 hpsa_free_sg_chain_blocks(h);
5323 hpsa_free_cmd_pool(h);
e1f7de0c 5324 kfree(h->ioaccel1_blockFetchTable);
64670ac8
SC		 5325 kfree(h->blockFetchTable);
5326 pci_free_consistent(h->pdev, h->reply_pool_size,
5327 h->reply_pool, h->reply_pool_dhandle);
5328 if (h->vaddr)
5329 iounmap(h->vaddr);
5330 if (h->transtable)
5331 iounmap(h->transtable);
5332 if (h->cfgtable)
5333 iounmap(h->cfgtable);
5334 pci_release_regions(h->pdev);
5335 kfree(h);
5336}
5337
a0c12413
SC		 5338/* Called when controller lockup detected. */
5339static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
5340{
5341 struct CommandList *c = NULL;
5342
5343 assert_spin_locked(&h->lock);
5344 /* Mark all outstanding commands as failed and complete them. */
5345 while (!list_empty(list)) {
5346 c = list_entry(list->next, struct CommandList, list);
5347 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 5348 finish_cmd(c);
a0c12413
SC		 5349 }
5350}
5351
5352static void controller_lockup_detected(struct ctlr_info *h)
5353{
5354 unsigned long flags;
5355
a0c12413
SC		 5356 h->access.set_intr_mask(h, HPSA_INTR_OFF);
5357 spin_lock_irqsave(&h->lock, flags);
5358 h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
5359 spin_unlock_irqrestore(&h->lock, flags);
5360 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
5361 h->lockup_detected);
5362 pci_disable_device(h->pdev);
5363 spin_lock_irqsave(&h->lock, flags);
5364 fail_all_cmds_on_list(h, &h->cmpQ);
5365 fail_all_cmds_on_list(h, &h->reqQ);
5366 spin_unlock_irqrestore(&h->lock, flags);
5367}
5368
a0c12413
SC		 5369static void detect_controller_lockup(struct ctlr_info *h)
5370{
5371 u64 now;
5372 u32 heartbeat;
5373 unsigned long flags;
5374
a0c12413
SC		 5375 now = get_jiffies_64();
5376 /* If we've received an interrupt recently, we're ok. */
5377 if (time_after64(h->last_intr_timestamp +
e85c5974 5378 (h->heartbeat_sample_interval), now))
a0c12413
SC		 5379 return;
5380
5381 /*
5382 * If we've already checked the heartbeat recently, we're ok.
5383 * This could happen if someone sends us a signal. We
5384 * otherwise don't care about signals in this thread.
5385 */
5386 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 5387 (h->heartbeat_sample_interval), now))
a0c12413
SC		 5388 return;
5389
5390 /* If heartbeat has not changed since we last looked, we're not ok. */
5391 spin_lock_irqsave(&h->lock, flags);
5392 heartbeat = readl(&h->cfgtable->HeartBeat);
5393 spin_unlock_irqrestore(&h->lock, flags);
5394 if (h->last_heartbeat == heartbeat) {
5395 controller_lockup_detected(h);
5396 return;
5397 }
5398
5399 /* We're ok. */
5400 h->last_heartbeat = heartbeat;
5401 h->last_heartbeat_timestamp = now;
5402}
5403
8a98db73 5404static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 5405{
5406 unsigned long flags;
8a98db73
SC		 5407 struct ctlr_info *h = container_of(to_delayed_work(work),
5408 struct ctlr_info, monitor_ctlr_work);
5409 detect_controller_lockup(h);
5410 if (h->lockup_detected)
5411 return;
5412 spin_lock_irqsave(&h->lock, flags);
5413 if (h->remove_in_progress) {
5414 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 5415 return;
5416 }
8a98db73
SC		 5417 schedule_delayed_work(&h->monitor_ctlr_work,
5418 h->heartbeat_sample_interval);
5419 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 5420}
5421
6f039790 5422static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 5423{
4c2a8c40 5424 int dac, rc;
edd16368 5425 struct ctlr_info *h;
64670ac8
SC		 5426 int try_soft_reset = 0;
5427 unsigned long flags;
edd16368
SC		 5428
5429 if (number_of_controllers == 0)
5430 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 5431
4c2a8c40 5432 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 5433 if (rc) {
5434 if (rc != -ENOTSUPP)
5435 return rc;
5436 /* If the reset fails in a particular way (it has no way to do
5437 * a proper hard reset, so returns -ENOTSUPP) we can try to do
5438 * a soft reset once we get the controller configured up to the
5439 * point that it can accept a command.
5440 */
5441 try_soft_reset = 1;
5442 rc = 0;
5443 }
5444
5445reinit_after_soft_reset:
edd16368 5446
303932fd
DB		 5447 /* Command structures must be aligned on a 32-byte boundary because
5448 * the 5 lower bits of the address are used by the hardware. and by
5449 * the driver. See comments in hpsa.h for more info.
5450 */
283b4a9b 5451#define COMMANDLIST_ALIGNMENT 128
303932fd 5452 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 5453 h = kzalloc(sizeof(*h), GFP_KERNEL);
5454 if (!h)
ecd9aad4 5455 return -ENOMEM;
edd16368 5456
55c06c71 5457 h->pdev = pdev;
a9a3a273 5458 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 5459 INIT_LIST_HEAD(&h->cmpQ);
5460 INIT_LIST_HEAD(&h->reqQ);
6eaf46fd
SC		 5461 spin_lock_init(&h->lock);
5462 spin_lock_init(&h->scan_lock);
0390f0c0 5463 spin_lock_init(&h->passthru_count_lock);
55c06c71 5464 rc = hpsa_pci_init(h);
ecd9aad4 5465 if (rc != 0)
edd16368
SC		 5466 goto clean1;
5467
f79cfec6 5468 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 5469 h->ctlr = number_of_controllers;
5470 number_of_controllers++;
edd16368
SC		 5471
5472 /* configure PCI DMA stuff */
ecd9aad4
SC		 5473 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
5474 if (rc == 0) {
edd16368 5475 dac = 1;
ecd9aad4
SC		 5476 } else {
5477 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5478 if (rc == 0) {
5479 dac = 0;
5480 } else {
5481 dev_err(&pdev->dev, "no suitable DMA available\n");
5482 goto clean1;
5483 }
edd16368
SC		 5484 }
5485
5486 /* make sure the board interrupts are off */
5487 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 5488
0ae01a32 5489 if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 5490 goto clean2;
303932fd
DB		 5491 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
5492 h->devname, pdev->device,
a9a3a273 5493 h->intr[h->intr_mode], dac ? "" : " not");
2e9d1b36 5494 if (hpsa_allocate_cmd_pool(h))
edd16368 5495 goto clean4;
33a2ffce
SC		 5496 if (hpsa_allocate_sg_chain_blocks(h))
5497 goto clean4;
a08a8471
SC		 5498 init_waitqueue_head(&h->scan_wait_queue);
5499 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 5500
5501 pci_set_drvdata(pdev, h);
9a41338e
SC		 5502 h->ndevices = 0;
5503 h->scsi_host = NULL;
5504 spin_lock_init(&h->devlock);
64670ac8
SC		 5505 hpsa_put_ctlr_into_performant_mode(h);
5506
5507 /* At this point, the controller is ready to take commands.
5508 * Now, if reset_devices and the hard reset didn't work, try
5509 * the soft reset and see if that works.
5510 */
5511 if (try_soft_reset) {
5512
5513 /* This is kind of gross. We may or may not get a completion
5514 * from the soft reset command, and if we do, then the value
5515 * from the fifo may or may not be valid. So, we wait 10 secs
5516 * after the reset throwing away any completions we get during
5517 * that time. Unregister the interrupt handler and register
5518 * fake ones to scoop up any residual completions.
5519 */
5520 spin_lock_irqsave(&h->lock, flags);
5521 h->access.set_intr_mask(h, HPSA_INTR_OFF);
5522 spin_unlock_irqrestore(&h->lock, flags);
254f796b 5523 free_irqs(h);
64670ac8
SC		 5524 rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
5525 hpsa_intx_discard_completions);
5526 if (rc) {
5527 dev_warn(&h->pdev->dev, "Failed to request_irq after "
5528 "soft reset.\n");
5529 goto clean4;
5530 }
5531
5532 rc = hpsa_kdump_soft_reset(h);
5533 if (rc)
5534 /* Neither hard nor soft reset worked, we're hosed. */
5535 goto clean4;
5536
5537 dev_info(&h->pdev->dev, "Board READY.\n");
5538 dev_info(&h->pdev->dev,
5539 "Waiting for stale completions to drain.\n");
5540 h->access.set_intr_mask(h, HPSA_INTR_ON);
5541 msleep(10000);
5542 h->access.set_intr_mask(h, HPSA_INTR_OFF);
5543
5544 rc = controller_reset_failed(h->cfgtable);
5545 if (rc)
5546 dev_info(&h->pdev->dev,
5547 "Soft reset appears to have failed.\n");
5548
5549 /* since the controller's reset, we have to go back and re-init
5550 * everything. Easiest to just forget what we've done and do it
5551 * all over again.
5552 */
5553 hpsa_undo_allocations_after_kdump_soft_reset(h);
5554 try_soft_reset = 0;
5555 if (rc)
5556 /* don't go to clean4, we already unallocated */
5557 return -ENODEV;
5558
5559 goto reinit_after_soft_reset;
5560 }
edd16368
SC		 5561
5562 /* Turn the interrupts on so we can service requests */
5563 h->access.set_intr_mask(h, HPSA_INTR_ON);
5564
339b2b14 5565 hpsa_hba_inquiry(h);
edd16368 5566 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 5567
5568 /* Monitor the controller for firmware lockups */
5569 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
5570 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
5571 schedule_delayed_work(&h->monitor_ctlr_work,
5572 h->heartbeat_sample_interval);
88bf6d62 5573 return 0;
edd16368
SC		 5574
5575clean4:
33a2ffce 5576 hpsa_free_sg_chain_blocks(h);
2e9d1b36 5577 hpsa_free_cmd_pool(h);
254f796b 5578 free_irqs(h);
edd16368
SC		 5579clean2:
5580clean1:
edd16368 5581 kfree(h);
ecd9aad4 5582 return rc;
edd16368
SC		 5583}
5584
5585static void hpsa_flush_cache(struct ctlr_info *h)
5586{
5587 char *flush_buf;
5588 struct CommandList *c;
702890e3
SC		 5589 unsigned long flags;
5590
5591 /* Don't bother trying to flush the cache if locked up */
5592 spin_lock_irqsave(&h->lock, flags);
5593 if (unlikely(h->lockup_detected)) {
5594 spin_unlock_irqrestore(&h->lock, flags);
5595 return;
5596 }
5597 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 5598
5599 flush_buf = kzalloc(4, GFP_KERNEL);
5600 if (!flush_buf)
5601 return;
5602
5603 c = cmd_special_alloc(h);
5604 if (!c) {
5605 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
5606 goto out_of_memory;
5607 }
a2dac136
SC		 5608 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
5609 RAID_CTLR_LUNID, TYPE_CMD)) {
5610 goto out;
5611 }
edd16368
SC		 5612 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
5613 if (c->err_info->CommandStatus != 0)
a2dac136 5614out:
edd16368
SC		 5615 dev_warn(&h->pdev->dev,
5616 "error flushing cache on controller\n");
5617 cmd_special_free(h, c);
5618out_of_memory:
5619 kfree(flush_buf);
5620}
5621
5622static void hpsa_shutdown(struct pci_dev *pdev)
5623{
5624 struct ctlr_info *h;
5625
5626 h = pci_get_drvdata(pdev);
5627 /* Turn board interrupts off and send the flush cache command
5628 * sendcmd will turn off interrupt, and send the flush...
5629 * To write all data in the battery backed cache to disks
5630 */
5631 hpsa_flush_cache(h);
5632 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 5633 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 5634}
5635
6f039790 5636static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 5637{
5638 int i;
5639
5640 for (i = 0; i < h->ndevices; i++)
5641 kfree(h->dev[i]);
5642}
5643
6f039790 5644static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 5645{
5646 struct ctlr_info *h;
8a98db73 5647 unsigned long flags;
edd16368
SC		 5648
5649 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 5650 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 5651 return;
5652 }
5653 h = pci_get_drvdata(pdev);
8a98db73
SC		 5654
5655 /* Get rid of any controller monitoring work items */
5656 spin_lock_irqsave(&h->lock, flags);
5657 h->remove_in_progress = 1;
5658 cancel_delayed_work(&h->monitor_ctlr_work);
5659 spin_unlock_irqrestore(&h->lock, flags);
5660
edd16368
SC		 5661 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
5662 hpsa_shutdown(pdev);
5663 iounmap(h->vaddr);
204892e9
SC		 5664 iounmap(h->transtable);
5665 iounmap(h->cfgtable);
55e14e76 5666 hpsa_free_device_info(h);
33a2ffce 5667 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 5668 pci_free_consistent(h->pdev,
5669 h->nr_cmds * sizeof(struct CommandList),
5670 h->cmd_pool, h->cmd_pool_dhandle);
5671 pci_free_consistent(h->pdev,
5672 h->nr_cmds * sizeof(struct ErrorInfo),
5673 h->errinfo_pool, h->errinfo_pool_dhandle);
303932fd
DB		 5674 pci_free_consistent(h->pdev, h->reply_pool_size,
5675 h->reply_pool, h->reply_pool_dhandle);
edd16368 5676 kfree(h->cmd_pool_bits);
303932fd 5677 kfree(h->blockFetchTable);
e1f7de0c 5678 kfree(h->ioaccel1_blockFetchTable);
339b2b14 5679 kfree(h->hba_inquiry_data);
f0bd0b68 5680 pci_disable_device(pdev);
edd16368 5681 pci_release_regions(pdev);
edd16368
SC		 5682 kfree(h);
5683}
5684
5685static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
5686 __attribute__((unused)) pm_message_t state)
5687{
5688 return -ENOSYS;
5689}
5690
5691static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
5692{
5693 return -ENOSYS;
5694}
5695
5696static struct pci_driver hpsa_pci_driver = {
f79cfec6 5697 .name = HPSA,
edd16368 5698 .probe = hpsa_init_one,
6f039790 5699 .remove = hpsa_remove_one,
edd16368
SC		 5700 .id_table = hpsa_pci_device_id, /* id_table */
5701 .shutdown = hpsa_shutdown,
5702 .suspend = hpsa_suspend,
5703 .resume = hpsa_resume,
5704};
5705
303932fd
DB		 5706/* Fill in bucket_map[], given nsgs (the max number of
5707 * scatter gather elements supported) and bucket[],
5708 * which is an array of 8 integers. The bucket[] array
5709 * contains 8 different DMA transfer sizes (in 16
5710 * byte increments) which the controller uses to fetch
5711 * commands. This function fills in bucket_map[], which
5712 * maps a given number of scatter gather elements to one of
5713 * the 8 DMA transfer sizes. The point of it is to allow the
5714 * controller to only do as much DMA as needed to fetch the
5715 * command, with the DMA transfer size encoded in the lower
5716 * bits of the command address.
5717 */
5718static void calc_bucket_map(int bucket[], int num_buckets,
e1f7de0c 5719 int nsgs, int min_blocks, int *bucket_map)
303932fd
DB		 5720{
5721 int i, j, b, size;
5722
303932fd
DB		 5723 /* Note, bucket_map must have nsgs+1 entries. */
5724 for (i = 0; i <= nsgs; i++) {
5725 /* Compute size of a command with i SG entries */
e1f7de0c 5726 size = i + min_blocks;
303932fd
DB		 5727 b = num_buckets; /* Assume the biggest bucket */
5728 /* Find the bucket that is just big enough */
e1f7de0c 5729 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 5730 if (bucket[j] >= size) {
5731 b = j;
5732 break;
5733 }
5734 }
5735 /* for a command with i SG entries, use bucket b. */
5736 bucket_map[i] = b;
5737 }
5738}
5739
e1f7de0c 5740static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 5741{
6c311b57
SC		 5742 int i;
5743 unsigned long register_value;
e1f7de0c
MG		 5744 unsigned long transMethod = CFGTBL_Trans_Performant |
5745 (trans_support & CFGTBL_Trans_use_short_tags) |
5746 CFGTBL_Trans_enable_directed_msix |
5747 (trans_support & CFGTBL_Trans_io_accel1);
5748
5749 struct access_method access = SA5_performant_access;
def342bd
SC		 5750
5751 /* This is a bit complicated. There are 8 registers on
5752 * the controller which we write to to tell it 8 different
5753 * sizes of commands which there may be. It's a way of
5754 * reducing the DMA done to fetch each command. Encoded into
5755 * each command's tag are 3 bits which communicate to the controller
5756 * which of the eight sizes that command fits within. The size of
5757 * each command depends on how many scatter gather entries there are.
5758 * Each SG entry requires 16 bytes. The eight registers are programmed
5759 * with the number of 16-byte blocks a command of that size requires.
5760 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 5761 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 5762 * blocks. Note, this only extends to the SG entries contained
5763 * within the command block, and does not extend to chained blocks
5764 * of SG elements. bft[] contains the eight values we write to
5765 * the registers. They are not evenly distributed, but have more
5766 * sizes for small commands, and fewer sizes for larger commands.
5767 */
d66ae08b
SC		 5768 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
5769 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 5770 /* 5 = 1 s/g entry or 4k
5771 * 6 = 2 s/g entry or 8k
5772 * 8 = 4 s/g entry or 16k
5773 * 10 = 6 s/g entry or 24k
5774 */
303932fd 5775
303932fd
DB		 5776 /* Controller spec: zero out this buffer. */
5777 memset(h->reply_pool, 0, h->reply_pool_size);
303932fd 5778
d66ae08b
SC		 5779 bft[7] = SG_ENTRIES_IN_CMD + 4;
5780 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 5781 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 5782 for (i = 0; i < 8; i++)
5783 writel(bft[i], &h->transtable->BlockFetch[i]);
5784
5785 /* size of controller ring buffer */
5786 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 5787 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 5788 writel(0, &h->transtable->RepQCtrAddrLow32);
5789 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 5790
5791 for (i = 0; i < h->nreply_queues; i++) {
5792 writel(0, &h->transtable->RepQAddr[i].upper);
5793 writel(h->reply_pool_dhandle +
5794 (h->max_commands * sizeof(u64) * i),
5795 &h->transtable->RepQAddr[i].lower);
5796 }
5797
e1f7de0c
MG		 5798 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
5799 /*
5800 * enable outbound interrupt coalescing in accelerator mode;
5801 */
5802 if (trans_support & CFGTBL_Trans_io_accel1) {
5803 access = SA5_ioaccel_mode1_access;
5804 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
5805 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
5806 }
303932fd 5807 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 5808 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 5809 register_value = readl(&(h->cfgtable->TransportActive));
5810 if (!(register_value & CFGTBL_Trans_Performant)) {
5811 dev_warn(&h->pdev->dev, "unable to get board into"
5812 " performant mode\n");
5813 return;
5814 }
960a30e7 5815 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 5816 h->access = access;
5817 h->transMethod = transMethod;
5818
5819 if (!(trans_support & CFGTBL_Trans_io_accel1))
5820 return;
5821
5822 /* Set up I/O accelerator mode */
5823 for (i = 0; i < h->nreply_queues; i++) {
5824 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
5825 h->reply_queue[i].current_entry =
5826 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
5827 }
283b4a9b
SC		 5828 bft[7] = h->ioaccel_maxsg + 8;
5829 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
e1f7de0c
MG		 5830 h->ioaccel1_blockFetchTable);
5831
5832 /* initialize all reply queue entries to unused */
5833 memset(h->reply_pool, (u8) IOACCEL_MODE1_REPLY_UNUSED,
5834 h->reply_pool_size);
5835
5836 /* set all the constant fields in the accelerator command
5837 * frames once at init time to save CPU cycles later.
5838 */
5839 for (i = 0; i < h->nr_cmds; i++) {
5840 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
5841
5842 cp->function = IOACCEL1_FUNCTION_SCSIIO;
5843 cp->err_info = (u32) (h->errinfo_pool_dhandle +
5844 (i * sizeof(struct ErrorInfo)));
5845 cp->err_info_len = sizeof(struct ErrorInfo);
5846 cp->sgl_offset = IOACCEL1_SGLOFFSET;
5847 cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT;
5848 cp->timeout_sec = 0;
5849 cp->ReplyQueue = 0;
5850 cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) | DIRECT_LOOKUP_BIT;
5851 cp->Tag.upper = 0;
5852 cp->host_addr.lower = (u32) (h->ioaccel_cmd_pool_dhandle +
5853 (i * sizeof(struct io_accel1_cmd)));
5854 cp->host_addr.upper = 0;
5855 }
5856}
5857
5858static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
5859{
283b4a9b
SC		 5860 h->ioaccel_maxsg =
5861 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
5862 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
5863 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
5864
e1f7de0c
MG		 5865 /* Command structures must be aligned on a 128-byte boundary
5866 * because the 7 lower bits of the address are used by the
5867 * hardware.
5868 */
5869#define IOACCEL1_COMMANDLIST_ALIGNMENT 128
5870 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
5871 IOACCEL1_COMMANDLIST_ALIGNMENT);
5872 h->ioaccel_cmd_pool =
5873 pci_alloc_consistent(h->pdev,
5874 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
5875 &(h->ioaccel_cmd_pool_dhandle));
5876
5877 h->ioaccel1_blockFetchTable =
283b4a9b 5878 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 5879 sizeof(u32)), GFP_KERNEL);
5880
5881 if ((h->ioaccel_cmd_pool == NULL) ||
5882 (h->ioaccel1_blockFetchTable == NULL))
5883 goto clean_up;
5884
5885 memset(h->ioaccel_cmd_pool, 0,
5886 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
5887 return 0;
5888
5889clean_up:
5890 if (h->ioaccel_cmd_pool)
5891 pci_free_consistent(h->pdev,
5892 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
5893 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
5894 kfree(h->ioaccel1_blockFetchTable);
5895 return 1;
6c311b57
SC		 5896}
5897
6f039790 5898static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 5899{
5900 u32 trans_support;
e1f7de0c
MG		 5901 unsigned long transMethod = CFGTBL_Trans_Performant |
5902 CFGTBL_Trans_use_short_tags;
254f796b 5903 int i;
6c311b57 5904
02ec19c8
SC		 5905 if (hpsa_simple_mode)
5906 return;
5907
e1f7de0c
MG		 5908 /* Check for I/O accelerator mode support */
5909 if (trans_support & CFGTBL_Trans_io_accel1) {
5910 transMethod |= CFGTBL_Trans_io_accel1 |
5911 CFGTBL_Trans_enable_directed_msix;
5912 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
5913 goto clean_up;
5914 }
5915
5916 /* TODO, check that this next line h->nreply_queues is correct */
6c311b57
SC		 5917 trans_support = readl(&(h->cfgtable->TransportSupport));
5918 if (!(trans_support & PERFORMANT_MODE))
5919 return;
5920
eee0f03a 5921 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 5922 hpsa_get_max_perf_mode_cmds(h);
6c311b57 5923 /* Performant mode ring buffer and supporting data structures */
254f796b 5924 h->reply_pool_size = h->max_commands * sizeof(u64) * h->nreply_queues;
6c311b57
SC		 5925 h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
5926 &(h->reply_pool_dhandle));
5927
254f796b
MG		 5928 for (i = 0; i < h->nreply_queues; i++) {
5929 h->reply_queue[i].head = &h->reply_pool[h->max_commands * i];
5930 h->reply_queue[i].size = h->max_commands;
5931 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
5932 h->reply_queue[i].current_entry = 0;
5933 }
5934
6c311b57 5935 /* Need a block fetch table for performant mode */
d66ae08b 5936 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57
SC		 5937 sizeof(u32)), GFP_KERNEL);
5938
5939 if ((h->reply_pool == NULL)
5940 || (h->blockFetchTable == NULL))
5941 goto clean_up;
5942
e1f7de0c 5943 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 5944 return;
5945
5946clean_up:
5947 if (h->reply_pool)
5948 pci_free_consistent(h->pdev, h->reply_pool_size,
5949 h->reply_pool, h->reply_pool_dhandle);
5950 kfree(h->blockFetchTable);
5951}
5952
edd16368
SC		 5953/*
5954 * This is it. Register the PCI driver information for the cards we control
5955 * the OS will call our registered routines when it finds one of our cards.
5956 */
5957static int __init hpsa_init(void)
5958{
31468401 5959 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 5960}
5961
5962static void __exit hpsa_cleanup(void)
5963{
5964 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 5965}
5966
e1f7de0c
MG		 5967static void __attribute__((unused)) verify_offsets(void)
5968{
5969#define VERIFY_OFFSET(member, offset) \
5970 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
5971
5972 VERIFY_OFFSET(dev_handle, 0x00);
5973 VERIFY_OFFSET(reserved1, 0x02);
5974 VERIFY_OFFSET(function, 0x03);
5975 VERIFY_OFFSET(reserved2, 0x04);
5976 VERIFY_OFFSET(err_info, 0x0C);
5977 VERIFY_OFFSET(reserved3, 0x10);
5978 VERIFY_OFFSET(err_info_len, 0x12);
5979 VERIFY_OFFSET(reserved4, 0x13);
5980 VERIFY_OFFSET(sgl_offset, 0x14);
5981 VERIFY_OFFSET(reserved5, 0x15);
5982 VERIFY_OFFSET(transfer_len, 0x1C);
5983 VERIFY_OFFSET(reserved6, 0x20);
5984 VERIFY_OFFSET(io_flags, 0x24);
5985 VERIFY_OFFSET(reserved7, 0x26);
5986 VERIFY_OFFSET(LUN, 0x34);
5987 VERIFY_OFFSET(control, 0x3C);
5988 VERIFY_OFFSET(CDB, 0x40);
5989 VERIFY_OFFSET(reserved8, 0x50);
5990 VERIFY_OFFSET(host_context_flags, 0x60);
5991 VERIFY_OFFSET(timeout_sec, 0x62);
5992 VERIFY_OFFSET(ReplyQueue, 0x64);
5993 VERIFY_OFFSET(reserved9, 0x65);
5994 VERIFY_OFFSET(Tag, 0x68);
5995 VERIFY_OFFSET(host_addr, 0x70);
5996 VERIFY_OFFSET(CISS_LUN, 0x78);
5997 VERIFY_OFFSET(SG, 0x78 + 8);
5998#undef VERIFY_OFFSET
5999}
6000
edd16368
SC		 6001module_init(hpsa_init);
6002module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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