projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
hpsa: add in new offline mode
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
1358f6dc
DB		 3 * Copyright 2014-2015 PMC-Sierra, Inc.
4 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
edd16368
SC		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
1358f6dc 15 * Questions/Comments/Bugfixes to storagedev@pmcs.com
edd16368
SC		 16 *
17 */
18
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/types.h>
22#include <linux/pci.h>
e5a44df8 23#include <linux/pci-aspm.h>
edd16368
SC		 24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/fs.h>
28#include <linux/timer.h>
edd16368
SC		 29#include <linux/init.h>
30#include <linux/spinlock.h>
edd16368
SC		 31#include <linux/compat.h>
32#include <linux/blktrace_api.h>
33#include <linux/uaccess.h>
34#include <linux/io.h>
35#include <linux/dma-mapping.h>
36#include <linux/completion.h>
37#include <linux/moduleparam.h>
38#include <scsi/scsi.h>
39#include <scsi/scsi_cmnd.h>
40#include <scsi/scsi_device.h>
41#include <scsi/scsi_host.h>
667e23d4 42#include <scsi/scsi_tcq.h>
9437ac43 43#include <scsi/scsi_eh.h>
73153fe5 44#include <scsi/scsi_dbg.h>
edd16368
SC		 45#include <linux/cciss_ioctl.h>
46#include <linux/string.h>
47#include <linux/bitmap.h>
60063497 48#include <linux/atomic.h>
a0c12413 49#include <linux/jiffies.h>
42a91641 50#include <linux/percpu-defs.h>
094963da 51#include <linux/percpu.h>
2b08b3e9 52#include <asm/unaligned.h>
283b4a9b 53#include <asm/div64.h>
edd16368
SC		 54#include "hpsa_cmd.h"
55#include "hpsa.h"
56
57/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
f532a3f9 58#define HPSA_DRIVER_VERSION "3.4.10-0"
edd16368 59#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 60#define HPSA "hpsa"
edd16368 61
007e7aa9
RE		 62/* How long to wait for CISS doorbell communication */
63#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
64#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
65#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
66#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 67#define MAX_IOCTL_CONFIG_WAIT 1000
68
69/*define how many times we will try a command because of bus resets */
70#define MAX_CMD_RETRIES 3
71
72/* Embedded module documentation macros - see modules.h */
73MODULE_AUTHOR("Hewlett-Packard Company");
74MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
75 HPSA_DRIVER_VERSION);
76MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
77MODULE_VERSION(HPSA_DRIVER_VERSION);
78MODULE_LICENSE("GPL");
79
80static int hpsa_allow_any;
81module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_allow_any,
83 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 84static int hpsa_simple_mode;
85module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
86MODULE_PARM_DESC(hpsa_simple_mode,
87 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 88
89/* define the PCI info for the cards we can control */
90static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
fdfa4b6d 131 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
cbb47dcb
DB		 132 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
133 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
134 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
135 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
8e616a5e
SC		 137 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
138 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
139 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
140 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
141 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 142 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 143 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 144 {0,}
145};
146
147MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
148
149/* board_id = Subsystem Device ID & Vendor ID
150 * product = Marketing Name for the board
151 * access = Address of the struct of function pointers
152 */
153static struct board_type products[] = {
edd16368
SC		 154 {0x3241103C, "Smart Array P212", &SA5_access},
155 {0x3243103C, "Smart Array P410", &SA5_access},
156 {0x3245103C, "Smart Array P410i", &SA5_access},
157 {0x3247103C, "Smart Array P411", &SA5_access},
158 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 159 {0x324A103C, "Smart Array P712m", &SA5_access},
160 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 161 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 162 {0x3350103C, "Smart Array P222", &SA5_access},
163 {0x3351103C, "Smart Array P420", &SA5_access},
164 {0x3352103C, "Smart Array P421", &SA5_access},
165 {0x3353103C, "Smart Array P822", &SA5_access},
166 {0x3354103C, "Smart Array P420i", &SA5_access},
167 {0x3355103C, "Smart Array P220i", &SA5_access},
168 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 169 {0x1921103C, "Smart Array P830i", &SA5_access},
170 {0x1922103C, "Smart Array P430", &SA5_access},
171 {0x1923103C, "Smart Array P431", &SA5_access},
172 {0x1924103C, "Smart Array P830", &SA5_access},
173 {0x1926103C, "Smart Array P731m", &SA5_access},
174 {0x1928103C, "Smart Array P230i", &SA5_access},
175 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 176 {0x21BD103C, "Smart Array P244br", &SA5_access},
177 {0x21BE103C, "Smart Array P741m", &SA5_access},
178 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
179 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 180 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 181 {0x21C2103C, "Smart Array P440", &SA5_access},
182 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 183 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 184 {0x21C5103C, "Smart Array P841", &SA5_access},
185 {0x21C6103C, "Smart HBA H244br", &SA5_access},
186 {0x21C7103C, "Smart HBA H240", &SA5_access},
187 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 188 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 189 {0x21CA103C, "Smart Array P246br", &SA5_access},
190 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 191 {0x21CC103C, "Smart Array", &SA5_access},
192 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 193 {0x21CE103C, "Smart HBA", &SA5_access},
fdfa4b6d 194 {0x05809005, "SmartHBA-SA", &SA5_access},
cbb47dcb
DB		 195 {0x05819005, "SmartHBA-SA 8i", &SA5_access},
196 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
197 {0x05839005, "SmartHBA-SA 8e", &SA5_access},
198 {0x05849005, "SmartHBA-SA 16i", &SA5_access},
199 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
8e616a5e
SC		 200 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
201 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
202 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
203 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
204 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 205 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
206};
207
a58e7e53
WS		 208#define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
209static const struct scsi_cmnd hpsa_cmd_busy;
210#define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
211static const struct scsi_cmnd hpsa_cmd_idle;
edd16368
SC		 212static int number_of_controllers;
213
10f66018
SC		 214static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
215static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 216static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 217
218#ifdef CONFIG_COMPAT
42a91641
DB		 219static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
220 void __user *arg);
edd16368
SC		 221#endif
222
223static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 224static struct CommandList *cmd_alloc(struct ctlr_info *h);
73153fe5
WS		 225static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
226static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
227 struct scsi_cmnd *scmd);
a2dac136 228static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 229 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 230 int cmd_type);
2c143342 231static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 232#define VPD_PAGE (1 << 8)
edd16368 233
f281233d 234static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 235static void hpsa_scan_start(struct Scsi_Host *);
236static int hpsa_scan_finished(struct Scsi_Host *sh,
237 unsigned long elapsed_time);
7c0a0229 238static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 239
240static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 241static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 242static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 243static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 244static void hpsa_slave_destroy(struct scsi_device *sdev);
245
edd16368 246static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 247static int check_for_unit_attention(struct ctlr_info *h,
248 struct CommandList *c);
249static void check_ioctl_unit_attention(struct ctlr_info *h,
250 struct CommandList *c);
303932fd
DB		 251/* performant mode helper functions */
252static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 253 int nsgs, int min_blocks, u32 *bucket_map);
105a3dbc
RE		 254static void hpsa_free_performant_mode(struct ctlr_info *h);
255static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 256static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 257static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
258 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
259 u64 *cfg_offset);
260static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
261 unsigned long *memory_bar);
262static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
263static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
264 int wait_for_ready);
75167d2c 265static inline void finish_cmd(struct CommandList *c);
c706a795 266static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 267#define BOARD_NOT_READY 0
268#define BOARD_READY 1
23100dd9 269static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 270static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 271static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
272 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 273 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 274static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 275static u32 lockup_detected(struct ctlr_info *h);
276static int detect_controller_lockup(struct ctlr_info *h);
8270b862 277static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device);
edd16368 278
edd16368
SC		 279static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
280{
281 unsigned long *priv = shost_priv(sdev->host);
282 return (struct ctlr_info *) *priv;
283}
284
a23513e8
SC		 285static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
286{
287 unsigned long *priv = shost_priv(sh);
288 return (struct ctlr_info *) *priv;
289}
290
a58e7e53
WS		 291static inline bool hpsa_is_cmd_idle(struct CommandList *c)
292{
293 return c->scsi_cmd == SCSI_CMD_IDLE;
294}
295
d604f533
WS		 296static inline bool hpsa_is_pending_event(struct CommandList *c)
297{
298 return c->abort_pending || c->reset_pending;
299}
300
9437ac43
SC		 301/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
302static void decode_sense_data(const u8 *sense_data, int sense_data_len,
303 u8 *sense_key, u8 *asc, u8 *ascq)
304{
305 struct scsi_sense_hdr sshdr;
306 bool rc;
307
308 *sense_key = -1;
309 *asc = -1;
310 *ascq = -1;
311
312 if (sense_data_len < 1)
313 return;
314
315 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
316 if (rc) {
317 *sense_key = sshdr.sense_key;
318 *asc = sshdr.asc;
319 *ascq = sshdr.ascq;
320 }
321}
322
edd16368
SC		 323static int check_for_unit_attention(struct ctlr_info *h,
324 struct CommandList *c)
325{
9437ac43
SC		 326 u8 sense_key, asc, ascq;
327 int sense_len;
328
329 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
330 sense_len = sizeof(c->err_info->SenseInfo);
331 else
332 sense_len = c->err_info->SenseLen;
333
334 decode_sense_data(c->err_info->SenseInfo, sense_len,
335 &sense_key, &asc, &ascq);
81c27557 336 if (sense_key != UNIT_ATTENTION || asc == 0xff)
edd16368
SC		 337 return 0;
338
9437ac43 339 switch (asc) {
edd16368 340 case STATE_CHANGED:
9437ac43 341 dev_warn(&h->pdev->dev,
2946e82b
RE		 342 "%s: a state change detected, command retried\n",
343 h->devname);
edd16368
SC		 344 break;
345 case LUN_FAILED:
7f73695a 346 dev_warn(&h->pdev->dev,
2946e82b 347 "%s: LUN failure detected\n", h->devname);
edd16368
SC		 348 break;
349 case REPORT_LUNS_CHANGED:
7f73695a 350 dev_warn(&h->pdev->dev,
2946e82b 351 "%s: report LUN data changed\n", h->devname);
edd16368 352 /*
4f4eb9f1
ST		 353 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
354 * target (array) devices.
edd16368
SC		 355 */
356 break;
357 case POWER_OR_RESET:
2946e82b
RE		 358 dev_warn(&h->pdev->dev,
359 "%s: a power on or device reset detected\n",
360 h->devname);
edd16368
SC		 361 break;
362 case UNIT_ATTENTION_CLEARED:
2946e82b
RE		 363 dev_warn(&h->pdev->dev,
364 "%s: unit attention cleared by another initiator\n",
365 h->devname);
edd16368
SC		 366 break;
367 default:
2946e82b
RE		 368 dev_warn(&h->pdev->dev,
369 "%s: unknown unit attention detected\n",
370 h->devname);
edd16368
SC		 371 break;
372 }
373 return 1;
374}
375
852af20a
MB		 376static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
377{
378 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
379 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
380 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
381 return 0;
382 dev_warn(&h->pdev->dev, HPSA "device busy");
383 return 1;
384}
385
e985c58f
SC		 386static u32 lockup_detected(struct ctlr_info *h);
387static ssize_t host_show_lockup_detected(struct device *dev,
388 struct device_attribute *attr, char *buf)
389{
390 int ld;
391 struct ctlr_info *h;
392 struct Scsi_Host *shost = class_to_shost(dev);
393
394 h = shost_to_hba(shost);
395 ld = lockup_detected(h);
396
397 return sprintf(buf, "ld=%d\n", ld);
398}
399
da0697bd
ST		 400static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
401 struct device_attribute *attr,
402 const char *buf, size_t count)
403{
404 int status, len;
405 struct ctlr_info *h;
406 struct Scsi_Host *shost = class_to_shost(dev);
407 char tmpbuf[10];
408
409 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
410 return -EACCES;
411 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
412 strncpy(tmpbuf, buf, len);
413 tmpbuf[len] = '\0';
414 if (sscanf(tmpbuf, "%d", &status) != 1)
415 return -EINVAL;
416 h = shost_to_hba(shost);
417 h->acciopath_status = !!status;
418 dev_warn(&h->pdev->dev,
419 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
420 h->acciopath_status ? "enabled" : "disabled");
421 return count;
422}
423
2ba8bfc8
SC		 424static ssize_t host_store_raid_offload_debug(struct device *dev,
425 struct device_attribute *attr,
426 const char *buf, size_t count)
427{
428 int debug_level, len;
429 struct ctlr_info *h;
430 struct Scsi_Host *shost = class_to_shost(dev);
431 char tmpbuf[10];
432
433 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
434 return -EACCES;
435 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
436 strncpy(tmpbuf, buf, len);
437 tmpbuf[len] = '\0';
438 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
439 return -EINVAL;
440 if (debug_level < 0)
441 debug_level = 0;
442 h = shost_to_hba(shost);
443 h->raid_offload_debug = debug_level;
444 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
445 h->raid_offload_debug);
446 return count;
447}
448
edd16368
SC		 449static ssize_t host_store_rescan(struct device *dev,
450 struct device_attribute *attr,
451 const char *buf, size_t count)
452{
453 struct ctlr_info *h;
454 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 455 h = shost_to_hba(shost);
31468401 456 hpsa_scan_start(h->scsi_host);
edd16368
SC		 457 return count;
458}
459
d28ce020
SC		 460static ssize_t host_show_firmware_revision(struct device *dev,
461 struct device_attribute *attr, char *buf)
462{
463 struct ctlr_info *h;
464 struct Scsi_Host *shost = class_to_shost(dev);
465 unsigned char *fwrev;
466
467 h = shost_to_hba(shost);
468 if (!h->hba_inquiry_data)
469 return 0;
470 fwrev = &h->hba_inquiry_data[32];
471 return snprintf(buf, 20, "%c%c%c%c\n",
472 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
473}
474
94a13649
SC		 475static ssize_t host_show_commands_outstanding(struct device *dev,
476 struct device_attribute *attr, char *buf)
477{
478 struct Scsi_Host *shost = class_to_shost(dev);
479 struct ctlr_info *h = shost_to_hba(shost);
480
0cbf768e
SC		 481 return snprintf(buf, 20, "%d\n",
482 atomic_read(&h->commands_outstanding));
94a13649
SC		 483}
484
745a7a25
SC		 485static ssize_t host_show_transport_mode(struct device *dev,
486 struct device_attribute *attr, char *buf)
487{
488 struct ctlr_info *h;
489 struct Scsi_Host *shost = class_to_shost(dev);
490
491 h = shost_to_hba(shost);
492 return snprintf(buf, 20, "%s\n",
960a30e7 493 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 494 "performant" : "simple");
495}
496
da0697bd
ST		 497static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
498 struct device_attribute *attr, char *buf)
499{
500 struct ctlr_info *h;
501 struct Scsi_Host *shost = class_to_shost(dev);
502
503 h = shost_to_hba(shost);
504 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
505 (h->acciopath_status == 1) ? "enabled" : "disabled");
506}
507
46380786 508/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 509static u32 unresettable_controller[] = {
510 0x324a103C, /* Smart Array P712m */
9b5c48c2 511 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 512 0x3223103C, /* Smart Array P800 */
513 0x3234103C, /* Smart Array P400 */
514 0x3235103C, /* Smart Array P400i */
515 0x3211103C, /* Smart Array E200i */
516 0x3212103C, /* Smart Array E200 */
517 0x3213103C, /* Smart Array E200i */
518 0x3214103C, /* Smart Array E200i */
519 0x3215103C, /* Smart Array E200i */
520 0x3237103C, /* Smart Array E500 */
521 0x323D103C, /* Smart Array P700m */
7af0abbc 522 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 523 0x409C0E11, /* Smart Array 6400 */
524 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 525 0x40700E11, /* Smart Array 5300 */
526 0x40820E11, /* Smart Array 532 */
527 0x40830E11, /* Smart Array 5312 */
528 0x409A0E11, /* Smart Array 641 */
529 0x409B0E11, /* Smart Array 642 */
530 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 531};
532
46380786
SC		 533/* List of controllers which cannot even be soft reset */
534static u32 soft_unresettable_controller[] = {
7af0abbc 535 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 536 0x40700E11, /* Smart Array 5300 */
537 0x40820E11, /* Smart Array 532 */
538 0x40830E11, /* Smart Array 5312 */
539 0x409A0E11, /* Smart Array 641 */
540 0x409B0E11, /* Smart Array 642 */
541 0x40910E11, /* Smart Array 6i */
46380786
SC		 542 /* Exclude 640x boards. These are two pci devices in one slot
543 * which share a battery backed cache module. One controls the
544 * cache, the other accesses the cache through the one that controls
545 * it. If we reset the one controlling the cache, the other will
546 * likely not be happy. Just forbid resetting this conjoined mess.
547 * The 640x isn't really supported by hpsa anyway.
548 */
549 0x409C0E11, /* Smart Array 6400 */
550 0x409D0E11, /* Smart Array 6400 EM */
551};
552
9b5c48c2
SC		 553static u32 needs_abort_tags_swizzled[] = {
554 0x323D103C, /* Smart Array P700m */
555 0x324a103C, /* Smart Array P712m */
556 0x324b103C, /* SmartArray P711m */
557};
558
559static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 560{
561 int i;
562
9b5c48c2
SC		 563 for (i = 0; i < nelems; i++)
564 if (a[i] == board_id)
565 return 1;
566 return 0;
46380786
SC		 567}
568
9b5c48c2 569static int ctlr_is_hard_resettable(u32 board_id)
46380786 570{
9b5c48c2
SC		 571 return !board_id_in_array(unresettable_controller,
572 ARRAY_SIZE(unresettable_controller), board_id);
573}
46380786 574
9b5c48c2
SC		 575static int ctlr_is_soft_resettable(u32 board_id)
576{
577 return !board_id_in_array(soft_unresettable_controller,
578 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 579}
580
46380786
SC		 581static int ctlr_is_resettable(u32 board_id)
582{
583 return ctlr_is_hard_resettable(board_id) ||
584 ctlr_is_soft_resettable(board_id);
585}
586
9b5c48c2
SC		 587static int ctlr_needs_abort_tags_swizzled(u32 board_id)
588{
589 return board_id_in_array(needs_abort_tags_swizzled,
590 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
591}
592
941b1cda
SC		 593static ssize_t host_show_resettable(struct device *dev,
594 struct device_attribute *attr, char *buf)
595{
596 struct ctlr_info *h;
597 struct Scsi_Host *shost = class_to_shost(dev);
598
599 h = shost_to_hba(shost);
46380786 600 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 601}
602
edd16368
SC		 603static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
604{
605 return (scsi3addr[3] & 0xC0) == 0x40;
606}
607
f2ef0ce7
RE		 608static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
609 "1(+0)ADM", "UNKNOWN"
edd16368 610};
6b80b18f
ST		 611#define HPSA_RAID_0 0
612#define HPSA_RAID_4 1
613#define HPSA_RAID_1 2 /* also used for RAID 10 */
614#define HPSA_RAID_5 3 /* also used for RAID 50 */
615#define HPSA_RAID_51 4
616#define HPSA_RAID_6 5 /* also used for RAID 60 */
617#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 618#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
619
620static ssize_t raid_level_show(struct device *dev,
621 struct device_attribute *attr, char *buf)
622{
623 ssize_t l = 0;
82a72c0a 624 unsigned char rlevel;
edd16368
SC		 625 struct ctlr_info *h;
626 struct scsi_device *sdev;
627 struct hpsa_scsi_dev_t *hdev;
628 unsigned long flags;
629
630 sdev = to_scsi_device(dev);
631 h = sdev_to_hba(sdev);
632 spin_lock_irqsave(&h->lock, flags);
633 hdev = sdev->hostdata;
634 if (!hdev) {
635 spin_unlock_irqrestore(&h->lock, flags);
636 return -ENODEV;
637 }
638
639 /* Is this even a logical drive? */
640 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
641 spin_unlock_irqrestore(&h->lock, flags);
642 l = snprintf(buf, PAGE_SIZE, "N/A\n");
643 return l;
644 }
645
646 rlevel = hdev->raid_level;
647 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 648 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 649 rlevel = RAID_UNKNOWN;
650 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
651 return l;
652}
653
654static ssize_t lunid_show(struct device *dev,
655 struct device_attribute *attr, char *buf)
656{
657 struct ctlr_info *h;
658 struct scsi_device *sdev;
659 struct hpsa_scsi_dev_t *hdev;
660 unsigned long flags;
661 unsigned char lunid[8];
662
663 sdev = to_scsi_device(dev);
664 h = sdev_to_hba(sdev);
665 spin_lock_irqsave(&h->lock, flags);
666 hdev = sdev->hostdata;
667 if (!hdev) {
668 spin_unlock_irqrestore(&h->lock, flags);
669 return -ENODEV;
670 }
671 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
672 spin_unlock_irqrestore(&h->lock, flags);
673 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
674 lunid[0], lunid[1], lunid[2], lunid[3],
675 lunid[4], lunid[5], lunid[6], lunid[7]);
676}
677
678static ssize_t unique_id_show(struct device *dev,
679 struct device_attribute *attr, char *buf)
680{
681 struct ctlr_info *h;
682 struct scsi_device *sdev;
683 struct hpsa_scsi_dev_t *hdev;
684 unsigned long flags;
685 unsigned char sn[16];
686
687 sdev = to_scsi_device(dev);
688 h = sdev_to_hba(sdev);
689 spin_lock_irqsave(&h->lock, flags);
690 hdev = sdev->hostdata;
691 if (!hdev) {
692 spin_unlock_irqrestore(&h->lock, flags);
693 return -ENODEV;
694 }
695 memcpy(sn, hdev->device_id, sizeof(sn));
696 spin_unlock_irqrestore(&h->lock, flags);
697 return snprintf(buf, 16 * 2 + 2,
698 "%02X%02X%02X%02X%02X%02X%02X%02X"
699 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
700 sn[0], sn[1], sn[2], sn[3],
701 sn[4], sn[5], sn[6], sn[7],
702 sn[8], sn[9], sn[10], sn[11],
703 sn[12], sn[13], sn[14], sn[15]);
704}
705
c1988684
ST		 706static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
707 struct device_attribute *attr, char *buf)
708{
709 struct ctlr_info *h;
710 struct scsi_device *sdev;
711 struct hpsa_scsi_dev_t *hdev;
712 unsigned long flags;
713 int offload_enabled;
714
715 sdev = to_scsi_device(dev);
716 h = sdev_to_hba(sdev);
717 spin_lock_irqsave(&h->lock, flags);
718 hdev = sdev->hostdata;
719 if (!hdev) {
720 spin_unlock_irqrestore(&h->lock, flags);
721 return -ENODEV;
722 }
723 offload_enabled = hdev->offload_enabled;
724 spin_unlock_irqrestore(&h->lock, flags);
725 return snprintf(buf, 20, "%d\n", offload_enabled);
726}
727
8270b862
JH		 728#define MAX_PATHS 8
729#define PATH_STRING_LEN 50
730
731static ssize_t path_info_show(struct device *dev,
732 struct device_attribute *attr, char *buf)
733{
734 struct ctlr_info *h;
735 struct scsi_device *sdev;
736 struct hpsa_scsi_dev_t *hdev;
737 unsigned long flags;
738 int i;
739 int output_len = 0;
740 u8 box;
741 u8 bay;
742 u8 path_map_index = 0;
743 char *active;
744 unsigned char phys_connector[2];
745 unsigned char path[MAX_PATHS][PATH_STRING_LEN];
746
747 memset(path, 0, MAX_PATHS * PATH_STRING_LEN);
748 sdev = to_scsi_device(dev);
749 h = sdev_to_hba(sdev);
750 spin_lock_irqsave(&h->devlock, flags);
751 hdev = sdev->hostdata;
752 if (!hdev) {
753 spin_unlock_irqrestore(&h->devlock, flags);
754 return -ENODEV;
755 }
756
757 bay = hdev->bay;
758 for (i = 0; i < MAX_PATHS; i++) {
759 path_map_index = 1<<i;
760 if (i == hdev->active_path_index)
761 active = "Active";
762 else if (hdev->path_map & path_map_index)
763 active = "Inactive";
764 else
765 continue;
766
767 output_len = snprintf(path[i],
768 PATH_STRING_LEN, "[%d:%d:%d:%d] %20.20s ",
769 h->scsi_host->host_no,
770 hdev->bus, hdev->target, hdev->lun,
771 scsi_device_type(hdev->devtype));
772
773 if (is_ext_target(h, hdev) ||
774 (hdev->devtype == TYPE_RAID) ||
775 is_logical_dev_addr_mode(hdev->scsi3addr)) {
776 output_len += snprintf(path[i] + output_len,
777 PATH_STRING_LEN, "%s\n",
778 active);
779 continue;
780 }
781
782 box = hdev->box[i];
783 memcpy(&phys_connector, &hdev->phys_connector[i],
784 sizeof(phys_connector));
785 if (phys_connector[0] < '0')
786 phys_connector[0] = '0';
787 if (phys_connector[1] < '0')
788 phys_connector[1] = '0';
789 if (hdev->phys_connector[i] > 0)
790 output_len += snprintf(path[i] + output_len,
791 PATH_STRING_LEN,
792 "PORT: %.2s ",
793 phys_connector);
b9092b79
KB		 794 if (hdev->devtype == TYPE_DISK &&
795 hdev->expose_state != HPSA_DO_NOT_EXPOSE) {
8270b862
JH		 796 if (box == 0 || box == 0xFF) {
797 output_len += snprintf(path[i] + output_len,
798 PATH_STRING_LEN,
799 "BAY: %hhu %s\n",
800 bay, active);
801 } else {
802 output_len += snprintf(path[i] + output_len,
803 PATH_STRING_LEN,
804 "BOX: %hhu BAY: %hhu %s\n",
805 box, bay, active);
806 }
807 } else if (box != 0 && box != 0xFF) {
808 output_len += snprintf(path[i] + output_len,
809 PATH_STRING_LEN, "BOX: %hhu %s\n",
810 box, active);
811 } else
812 output_len += snprintf(path[i] + output_len,
813 PATH_STRING_LEN, "%s\n", active);
814 }
815
816 spin_unlock_irqrestore(&h->devlock, flags);
817 return snprintf(buf, output_len+1, "%s%s%s%s%s%s%s%s",
818 path[0], path[1], path[2], path[3],
819 path[4], path[5], path[6], path[7]);
820}
821
3f5eac3a
SC		 822static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
823static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
824static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
825static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 826static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
827 host_show_hp_ssd_smart_path_enabled, NULL);
8270b862 828static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
da0697bd
ST		 829static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
830 host_show_hp_ssd_smart_path_status,
831 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 832static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
833 host_store_raid_offload_debug);
3f5eac3a
SC		 834static DEVICE_ATTR(firmware_revision, S_IRUGO,
835 host_show_firmware_revision, NULL);
836static DEVICE_ATTR(commands_outstanding, S_IRUGO,
837 host_show_commands_outstanding, NULL);
838static DEVICE_ATTR(transport_mode, S_IRUGO,
839 host_show_transport_mode, NULL);
941b1cda
SC		 840static DEVICE_ATTR(resettable, S_IRUGO,
841 host_show_resettable, NULL);
e985c58f
SC		 842static DEVICE_ATTR(lockup_detected, S_IRUGO,
843 host_show_lockup_detected, NULL);
3f5eac3a
SC		 844
845static struct device_attribute *hpsa_sdev_attrs[] = {
846 &dev_attr_raid_level,
847 &dev_attr_lunid,
848 &dev_attr_unique_id,
c1988684 849 &dev_attr_hp_ssd_smart_path_enabled,
8270b862 850 &dev_attr_path_info,
e985c58f 851 &dev_attr_lockup_detected,
3f5eac3a
SC		 852 NULL,
853};
854
855static struct device_attribute *hpsa_shost_attrs[] = {
856 &dev_attr_rescan,
857 &dev_attr_firmware_revision,
858 &dev_attr_commands_outstanding,
859 &dev_attr_transport_mode,
941b1cda 860 &dev_attr_resettable,
da0697bd 861 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 862 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 863 NULL,
864};
865
41ce4c35
SC		 866#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
867 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
868
3f5eac3a
SC		 869static struct scsi_host_template hpsa_driver_template = {
870 .module = THIS_MODULE,
f79cfec6
SC		 871 .name = HPSA,
872 .proc_name = HPSA,
3f5eac3a
SC		 873 .queuecommand = hpsa_scsi_queue_command,
874 .scan_start = hpsa_scan_start,
875 .scan_finished = hpsa_scan_finished,
7c0a0229 876 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 877 .this_id = -1,
878 .use_clustering = ENABLE_CLUSTERING,
75167d2c 879 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 880 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
881 .ioctl = hpsa_ioctl,
882 .slave_alloc = hpsa_slave_alloc,
41ce4c35 883 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 884 .slave_destroy = hpsa_slave_destroy,
885#ifdef CONFIG_COMPAT
886 .compat_ioctl = hpsa_compat_ioctl,
887#endif
888 .sdev_attrs = hpsa_sdev_attrs,
889 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 890 .max_sectors = 8192,
54b2b50c 891 .no_write_same = 1,
3f5eac3a
SC		 892};
893
254f796b 894static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 895{
896 u32 a;
072b0518 897 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 898
e1f7de0c
MG		 899 if (h->transMethod & CFGTBL_Trans_io_accel1)
900 return h->access.command_completed(h, q);
901
3f5eac3a 902 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 903 return h->access.command_completed(h, q);
3f5eac3a 904
254f796b
MG		 905 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
906 a = rq->head[rq->current_entry];
907 rq->current_entry++;
0cbf768e 908 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 909 } else {
910 a = FIFO_EMPTY;
911 }
912 /* Check for wraparound */
254f796b
MG		 913 if (rq->current_entry == h->max_commands) {
914 rq->current_entry = 0;
915 rq->wraparound ^= 1;
3f5eac3a
SC		 916 }
917 return a;
918}
919
c349775e
ST		 920/*
921 * There are some special bits in the bus address of the
922 * command that we have to set for the controller to know
923 * how to process the command:
924 *
925 * Normal performant mode:
926 * bit 0: 1 means performant mode, 0 means simple mode.
927 * bits 1-3 = block fetch table entry
928 * bits 4-6 = command type (== 0)
929 *
930 * ioaccel1 mode:
931 * bit 0 = "performant mode" bit.
932 * bits 1-3 = block fetch table entry
933 * bits 4-6 = command type (== 110)
934 * (command type is needed because ioaccel1 mode
935 * commands are submitted through the same register as normal
936 * mode commands, so this is how the controller knows whether
937 * the command is normal mode or ioaccel1 mode.)
938 *
939 * ioaccel2 mode:
940 * bit 0 = "performant mode" bit.
941 * bits 1-4 = block fetch table entry (note extra bit)
942 * bits 4-6 = not needed, because ioaccel2 mode has
943 * a separate special register for submitting commands.
944 */
945
25163bd5
WS		 946/*
947 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 948 * set bit 0 for pull model, bits 3-1 for block fetch
949 * register number
950 */
25163bd5
WS		 951#define DEFAULT_REPLY_QUEUE (-1)
952static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
953 int reply_queue)
3f5eac3a 954{
254f796b 955 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 956 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 957 if (unlikely(!h->msix_vector))
958 return;
959 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 960 c->Header.ReplyQueue =
804a5cb5 961 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 962 else
963 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 964 }
3f5eac3a
SC		 965}
966
c349775e 967static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 968 struct CommandList *c,
969 int reply_queue)
c349775e
ST		 970{
971 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
972
25163bd5
WS		 973 /*
974 * Tell the controller to post the reply to the queue for this
c349775e
ST		 975 * processor. This seems to give the best I/O throughput.
976 */
25163bd5
WS		 977 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
978 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
979 else
980 cp->ReplyQueue = reply_queue % h->nreply_queues;
981 /*
982 * Set the bits in the address sent down to include:
c349775e
ST		 983 * - performant mode bit (bit 0)
984 * - pull count (bits 1-3)
985 * - command type (bits 4-6)
986 */
987 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
988 IOACCEL1_BUSADDR_CMDTYPE;
989}
990
8be986cc
SC		 991static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
992 struct CommandList *c,
993 int reply_queue)
994{
995 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
996 &h->ioaccel2_cmd_pool[c->cmdindex];
997
998 /* Tell the controller to post the reply to the queue for this
999 * processor. This seems to give the best I/O throughput.
1000 */
1001 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1002 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1003 else
1004 cp->reply_queue = reply_queue % h->nreply_queues;
1005 /* Set the bits in the address sent down to include:
1006 * - performant mode bit not used in ioaccel mode 2
1007 * - pull count (bits 0-3)
1008 * - command type isn't needed for ioaccel2
1009 */
1010 c->busaddr |= h->ioaccel2_blockFetchTable[0];
1011}
1012
c349775e 1013static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1014 struct CommandList *c,
1015 int reply_queue)
c349775e
ST		 1016{
1017 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
1018
25163bd5
WS		 1019 /*
1020 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1021 * processor. This seems to give the best I/O throughput.
1022 */
25163bd5
WS		 1023 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1024 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1025 else
1026 cp->reply_queue = reply_queue % h->nreply_queues;
1027 /*
1028 * Set the bits in the address sent down to include:
c349775e
ST		 1029 * - performant mode bit not used in ioaccel mode 2
1030 * - pull count (bits 0-3)
1031 * - command type isn't needed for ioaccel2
1032 */
1033 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
1034}
1035
e85c5974
SC		 1036static int is_firmware_flash_cmd(u8 *cdb)
1037{
1038 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
1039}
1040
1041/*
1042 * During firmware flash, the heartbeat register may not update as frequently
1043 * as it should. So we dial down lockup detection during firmware flash. and
1044 * dial it back up when firmware flash completes.
1045 */
1046#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
1047#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
1048static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
1049 struct CommandList *c)
1050{
1051 if (!is_firmware_flash_cmd(c->Request.CDB))
1052 return;
1053 atomic_inc(&h->firmware_flash_in_progress);
1054 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
1055}
1056
1057static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
1058 struct CommandList *c)
1059{
1060 if (is_firmware_flash_cmd(c->Request.CDB) &&
1061 atomic_dec_and_test(&h->firmware_flash_in_progress))
1062 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
1063}
1064
25163bd5
WS		 1065static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
1066 struct CommandList *c, int reply_queue)
3f5eac3a 1067{
c05e8866
SC		 1068 dial_down_lockup_detection_during_fw_flash(h, c);
1069 atomic_inc(&h->commands_outstanding);
c349775e
ST		 1070 switch (c->cmd_type) {
1071 case CMD_IOACCEL1:
25163bd5 1072 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 1073 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 1074 break;
1075 case CMD_IOACCEL2:
25163bd5 1076 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 1077 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e 1078 break;
8be986cc
SC		 1079 case IOACCEL2_TMF:
1080 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
1081 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1082 break;
c349775e 1083 default:
25163bd5 1084 set_performant_mode(h, c, reply_queue);
c05e8866 1085 h->access.submit_command(h, c);
c349775e 1086 }
3f5eac3a
SC		 1087}
1088
a58e7e53 1089static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
25163bd5 1090{
d604f533 1091 if (unlikely(hpsa_is_pending_event(c)))
a58e7e53
WS		 1092 return finish_cmd(c);
1093
25163bd5
WS		 1094 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
1095}
1096
3f5eac3a
SC		 1097static inline int is_hba_lunid(unsigned char scsi3addr[])
1098{
1099 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
1100}
1101
1102static inline int is_scsi_rev_5(struct ctlr_info *h)
1103{
1104 if (!h->hba_inquiry_data)
1105 return 0;
1106 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1107 return 1;
1108 return 0;
1109}
1110
edd16368
SC		 1111static int hpsa_find_target_lun(struct ctlr_info *h,
1112 unsigned char scsi3addr[], int bus, int *target, int *lun)
1113{
1114 /* finds an unused bus, target, lun for a new physical device
1115 * assumes h->devlock is held
1116 */
1117 int i, found = 0;
cfe5badc 1118 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 1119
263d9401 1120 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 1121
1122 for (i = 0; i < h->ndevices; i++) {
1123 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 1124 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 1125 }
1126
263d9401
AM		 1127 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1128 if (i < HPSA_MAX_DEVICES) {
1129 /* *bus = 1; */
1130 *target = i;
1131 *lun = 0;
1132 found = 1;
edd16368
SC		 1133 }
1134 return !found;
1135}
1136
0d96ef5f
WS		 1137static inline void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
1138 struct hpsa_scsi_dev_t *dev, char *description)
1139{
1140 dev_printk(level, &h->pdev->dev,
1141 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
1142 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1143 description,
1144 scsi_device_type(dev->devtype),
1145 dev->vendor,
1146 dev->model,
1147 dev->raid_level > RAID_UNKNOWN ?
1148 "RAID-?" : raid_label[dev->raid_level],
1149 dev->offload_config ? '+' : '-',
1150 dev->offload_enabled ? '+' : '-',
1151 dev->expose_state);
1152}
1153
edd16368
SC		 1154/* Add an entry into h->dev[] array. */
1155static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
1156 struct hpsa_scsi_dev_t *device,
1157 struct hpsa_scsi_dev_t *added[], int *nadded)
1158{
1159 /* assumes h->devlock is held */
1160 int n = h->ndevices;
1161 int i;
1162 unsigned char addr1[8], addr2[8];
1163 struct hpsa_scsi_dev_t *sd;
1164
cfe5badc 1165 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1166 dev_err(&h->pdev->dev, "too many devices, some will be "
1167 "inaccessible.\n");
1168 return -1;
1169 }
1170
1171 /* physical devices do not have lun or target assigned until now. */
1172 if (device->lun != -1)
1173 /* Logical device, lun is already assigned. */
1174 goto lun_assigned;
1175
1176 /* If this device a non-zero lun of a multi-lun device
1177 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1178 * unit no, zero otherwise.
edd16368
SC		 1179 */
1180 if (device->scsi3addr[4] == 0) {
1181 /* This is not a non-zero lun of a multi-lun device */
1182 if (hpsa_find_target_lun(h, device->scsi3addr,
1183 device->bus, &device->target, &device->lun) != 0)
1184 return -1;
1185 goto lun_assigned;
1186 }
1187
1188 /* This is a non-zero lun of a multi-lun device.
1189 * Search through our list and find the device which
1190 * has the same 8 byte LUN address, excepting byte 4.
1191 * Assign the same bus and target for this new LUN.
1192 * Use the logical unit number from the firmware.
1193 */
1194 memcpy(addr1, device->scsi3addr, 8);
1195 addr1[4] = 0;
1196 for (i = 0; i < n; i++) {
1197 sd = h->dev[i];
1198 memcpy(addr2, sd->scsi3addr, 8);
1199 addr2[4] = 0;
1200 /* differ only in byte 4? */
1201 if (memcmp(addr1, addr2, 8) == 0) {
1202 device->bus = sd->bus;
1203 device->target = sd->target;
1204 device->lun = device->scsi3addr[4];
1205 break;
1206 }
1207 }
1208 if (device->lun == -1) {
1209 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1210 " suspect firmware bug or unsupported hardware "
1211 "configuration.\n");
1212 return -1;
1213 }
1214
1215lun_assigned:
1216
1217 h->dev[n] = device;
1218 h->ndevices++;
1219 added[*nadded] = device;
1220 (*nadded)++;
0d96ef5f
WS		 1221 hpsa_show_dev_msg(KERN_INFO, h, device,
1222 device->expose_state & HPSA_SCSI_ADD ? "added" : "masked");
a473d86c
RE		 1223 device->offload_to_be_enabled = device->offload_enabled;
1224 device->offload_enabled = 0;
edd16368
SC		 1225 return 0;
1226}
1227
bd9244f7
ST		 1228/* Update an entry in h->dev[] array. */
1229static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
1230 int entry, struct hpsa_scsi_dev_t *new_entry)
1231{
a473d86c 1232 int offload_enabled;
bd9244f7
ST		 1233 /* assumes h->devlock is held */
1234 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1235
1236 /* Raid level changed. */
1237 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1238
03383736
DB		 1239 /* Raid offload parameters changed. Careful about the ordering. */
1240 if (new_entry->offload_config && new_entry->offload_enabled) {
1241 /*
1242 * if drive is newly offload_enabled, we want to copy the
1243 * raid map data first. If previously offload_enabled and
1244 * offload_config were set, raid map data had better be
1245 * the same as it was before. if raid map data is changed
1246 * then it had better be the case that
1247 * h->dev[entry]->offload_enabled is currently 0.
1248 */
1249 h->dev[entry]->raid_map = new_entry->raid_map;
1250 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1251 }
a3144e0b
JH		 1252 if (new_entry->hba_ioaccel_enabled) {
1253 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1254 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1255 }
1256 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1257 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1258 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1259 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1260
41ce4c35
SC		 1261 /*
1262 * We can turn off ioaccel offload now, but need to delay turning
1263 * it on until we can update h->dev[entry]->phys_disk[], but we
1264 * can't do that until all the devices are updated.
1265 */
1266 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1267 if (!new_entry->offload_enabled)
1268 h->dev[entry]->offload_enabled = 0;
1269
a473d86c
RE		 1270 offload_enabled = h->dev[entry]->offload_enabled;
1271 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1272 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1273 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1274}
1275
2a8ccf31
SC		 1276/* Replace an entry from h->dev[] array. */
1277static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
1278 int entry, struct hpsa_scsi_dev_t *new_entry,
1279 struct hpsa_scsi_dev_t *added[], int *nadded,
1280 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1281{
1282 /* assumes h->devlock is held */
cfe5badc 1283 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1284 removed[*nremoved] = h->dev[entry];
1285 (*nremoved)++;
01350d05
SC		 1286
1287 /*
1288 * New physical devices won't have target/lun assigned yet
1289 * so we need to preserve the values in the slot we are replacing.
1290 */
1291 if (new_entry->target == -1) {
1292 new_entry->target = h->dev[entry]->target;
1293 new_entry->lun = h->dev[entry]->lun;
1294 }
1295
2a8ccf31
SC		 1296 h->dev[entry] = new_entry;
1297 added[*nadded] = new_entry;
1298 (*nadded)++;
0d96ef5f 1299 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1300 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1301 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1302}
1303
edd16368
SC		 1304/* Remove an entry from h->dev[] array. */
1305static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1306 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1307{
1308 /* assumes h->devlock is held */
1309 int i;
1310 struct hpsa_scsi_dev_t *sd;
1311
cfe5badc 1312 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1313
1314 sd = h->dev[entry];
1315 removed[*nremoved] = h->dev[entry];
1316 (*nremoved)++;
1317
1318 for (i = entry; i < h->ndevices-1; i++)
1319 h->dev[i] = h->dev[i+1];
1320 h->ndevices--;
0d96ef5f 1321 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1322}
1323
1324#define SCSI3ADDR_EQ(a, b) ( \
1325 (a)[7] == (b)[7] && \
1326 (a)[6] == (b)[6] && \
1327 (a)[5] == (b)[5] && \
1328 (a)[4] == (b)[4] && \
1329 (a)[3] == (b)[3] && \
1330 (a)[2] == (b)[2] && \
1331 (a)[1] == (b)[1] && \
1332 (a)[0] == (b)[0])
1333
1334static void fixup_botched_add(struct ctlr_info *h,
1335 struct hpsa_scsi_dev_t *added)
1336{
1337 /* called when scsi_add_device fails in order to re-adjust
1338 * h->dev[] to match the mid layer's view.
1339 */
1340 unsigned long flags;
1341 int i, j;
1342
1343 spin_lock_irqsave(&h->lock, flags);
1344 for (i = 0; i < h->ndevices; i++) {
1345 if (h->dev[i] == added) {
1346 for (j = i; j < h->ndevices-1; j++)
1347 h->dev[j] = h->dev[j+1];
1348 h->ndevices--;
1349 break;
1350 }
1351 }
1352 spin_unlock_irqrestore(&h->lock, flags);
1353 kfree(added);
1354}
1355
1356static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1357 struct hpsa_scsi_dev_t *dev2)
1358{
edd16368
SC		 1359 /* we compare everything except lun and target as these
1360 * are not yet assigned. Compare parts likely
1361 * to differ first
1362 */
1363 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1364 sizeof(dev1->scsi3addr)) != 0)
1365 return 0;
1366 if (memcmp(dev1->device_id, dev2->device_id,
1367 sizeof(dev1->device_id)) != 0)
1368 return 0;
1369 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1370 return 0;
1371 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1372 return 0;
edd16368
SC		 1373 if (dev1->devtype != dev2->devtype)
1374 return 0;
edd16368
SC		 1375 if (dev1->bus != dev2->bus)
1376 return 0;
1377 return 1;
1378}
1379
bd9244f7
ST		 1380static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1381 struct hpsa_scsi_dev_t *dev2)
1382{
1383 /* Device attributes that can change, but don't mean
1384 * that the device is a different device, nor that the OS
1385 * needs to be told anything about the change.
1386 */
1387 if (dev1->raid_level != dev2->raid_level)
1388 return 1;
250fb125
SC		 1389 if (dev1->offload_config != dev2->offload_config)
1390 return 1;
1391 if (dev1->offload_enabled != dev2->offload_enabled)
1392 return 1;
93849508
DB		 1393 if (!is_logical_dev_addr_mode(dev1->scsi3addr))
1394 if (dev1->queue_depth != dev2->queue_depth)
1395 return 1;
bd9244f7
ST		 1396 return 0;
1397}
1398
edd16368
SC		 1399/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1400 * and return needle location in *index. If scsi3addr matches, but not
1401 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1402 * location in *index.
1403 * In the case of a minor device attribute change, such as RAID level, just
1404 * return DEVICE_UPDATED, along with the updated device's location in index.
1405 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1406 */
1407static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1408 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1409 int *index)
1410{
1411 int i;
1412#define DEVICE_NOT_FOUND 0
1413#define DEVICE_CHANGED 1
1414#define DEVICE_SAME 2
bd9244f7 1415#define DEVICE_UPDATED 3
edd16368 1416 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1417 if (haystack[i] == NULL) /* previously removed. */
1418 continue;
edd16368
SC		 1419 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1420 *index = i;
bd9244f7
ST		 1421 if (device_is_the_same(needle, haystack[i])) {
1422 if (device_updated(needle, haystack[i]))
1423 return DEVICE_UPDATED;
edd16368 1424 return DEVICE_SAME;
bd9244f7 1425 } else {
9846590e
SC		 1426 /* Keep offline devices offline */
1427 if (needle->volume_offline)
1428 return DEVICE_NOT_FOUND;
edd16368 1429 return DEVICE_CHANGED;
bd9244f7 1430 }
edd16368
SC		 1431 }
1432 }
1433 *index = -1;
1434 return DEVICE_NOT_FOUND;
1435}
1436
9846590e
SC		 1437static void hpsa_monitor_offline_device(struct ctlr_info *h,
1438 unsigned char scsi3addr[])
1439{
1440 struct offline_device_entry *device;
1441 unsigned long flags;
1442
1443 /* Check to see if device is already on the list */
1444 spin_lock_irqsave(&h->offline_device_lock, flags);
1445 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1446 if (memcmp(device->scsi3addr, scsi3addr,
1447 sizeof(device->scsi3addr)) == 0) {
1448 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1449 return;
1450 }
1451 }
1452 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1453
1454 /* Device is not on the list, add it. */
1455 device = kmalloc(sizeof(*device), GFP_KERNEL);
1456 if (!device) {
1457 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1458 return;
1459 }
1460 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1461 spin_lock_irqsave(&h->offline_device_lock, flags);
1462 list_add_tail(&device->offline_list, &h->offline_device_list);
1463 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1464}
1465
1466/* Print a message explaining various offline volume states */
1467static void hpsa_show_volume_status(struct ctlr_info *h,
1468 struct hpsa_scsi_dev_t *sd)
1469{
1470 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1471 dev_info(&h->pdev->dev,
1472 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1473 h->scsi_host->host_no,
1474 sd->bus, sd->target, sd->lun);
1475 switch (sd->volume_offline) {
1476 case HPSA_LV_OK:
1477 break;
1478 case HPSA_LV_UNDERGOING_ERASE:
1479 dev_info(&h->pdev->dev,
1480 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1481 h->scsi_host->host_no,
1482 sd->bus, sd->target, sd->lun);
1483 break;
5ca01204
SB		 1484 case HPSA_LV_NOT_AVAILABLE:
1485 dev_info(&h->pdev->dev,
1486 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
1487 h->scsi_host->host_no,
1488 sd->bus, sd->target, sd->lun);
1489 break;
9846590e
SC		 1490 case HPSA_LV_UNDERGOING_RPI:
1491 dev_info(&h->pdev->dev,
5ca01204 1492 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
9846590e
SC		 1493 h->scsi_host->host_no,
1494 sd->bus, sd->target, sd->lun);
1495 break;
1496 case HPSA_LV_PENDING_RPI:
1497 dev_info(&h->pdev->dev,
5ca01204
SB		 1498 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1499 h->scsi_host->host_no,
1500 sd->bus, sd->target, sd->lun);
9846590e
SC		 1501 break;
1502 case HPSA_LV_ENCRYPTED_NO_KEY:
1503 dev_info(&h->pdev->dev,
1504 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1505 h->scsi_host->host_no,
1506 sd->bus, sd->target, sd->lun);
1507 break;
1508 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1509 dev_info(&h->pdev->dev,
1510 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1511 h->scsi_host->host_no,
1512 sd->bus, sd->target, sd->lun);
1513 break;
1514 case HPSA_LV_UNDERGOING_ENCRYPTION:
1515 dev_info(&h->pdev->dev,
1516 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1517 h->scsi_host->host_no,
1518 sd->bus, sd->target, sd->lun);
1519 break;
1520 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1521 dev_info(&h->pdev->dev,
1522 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1523 h->scsi_host->host_no,
1524 sd->bus, sd->target, sd->lun);
1525 break;
1526 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1527 dev_info(&h->pdev->dev,
1528 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1529 h->scsi_host->host_no,
1530 sd->bus, sd->target, sd->lun);
1531 break;
1532 case HPSA_LV_PENDING_ENCRYPTION:
1533 dev_info(&h->pdev->dev,
1534 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1535 h->scsi_host->host_no,
1536 sd->bus, sd->target, sd->lun);
1537 break;
1538 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1539 dev_info(&h->pdev->dev,
1540 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1541 h->scsi_host->host_no,
1542 sd->bus, sd->target, sd->lun);
1543 break;
1544 }
1545}
1546
03383736
DB		 1547/*
1548 * Figure the list of physical drive pointers for a logical drive with
1549 * raid offload configured.
1550 */
1551static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1552 struct hpsa_scsi_dev_t *dev[], int ndevices,
1553 struct hpsa_scsi_dev_t *logical_drive)
1554{
1555 struct raid_map_data *map = &logical_drive->raid_map;
1556 struct raid_map_disk_data *dd = &map->data[0];
1557 int i, j;
1558 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1559 le16_to_cpu(map->metadata_disks_per_row);
1560 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1561 le16_to_cpu(map->layout_map_count) *
1562 total_disks_per_row;
1563 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1564 total_disks_per_row;
1565 int qdepth;
1566
1567 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1568 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1569
d604f533
WS		 1570 logical_drive->nphysical_disks = nraid_map_entries;
1571
03383736
DB		 1572 qdepth = 0;
1573 for (i = 0; i < nraid_map_entries; i++) {
1574 logical_drive->phys_disk[i] = NULL;
1575 if (!logical_drive->offload_config)
1576 continue;
1577 for (j = 0; j < ndevices; j++) {
1578 if (dev[j]->devtype != TYPE_DISK)
1579 continue;
1580 if (is_logical_dev_addr_mode(dev[j]->scsi3addr))
1581 continue;
1582 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1583 continue;
1584
1585 logical_drive->phys_disk[i] = dev[j];
1586 if (i < nphys_disk)
1587 qdepth = min(h->nr_cmds, qdepth +
1588 logical_drive->phys_disk[i]->queue_depth);
1589 break;
1590 }
1591
1592 /*
1593 * This can happen if a physical drive is removed and
1594 * the logical drive is degraded. In that case, the RAID
1595 * map data will refer to a physical disk which isn't actually
1596 * present. And in that case offload_enabled should already
1597 * be 0, but we'll turn it off here just in case
1598 */
1599 if (!logical_drive->phys_disk[i]) {
1600 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1601 logical_drive->offload_to_be_enabled = 0;
1602 logical_drive->queue_depth = 8;
03383736
DB		 1603 }
1604 }
1605 if (nraid_map_entries)
1606 /*
1607 * This is correct for reads, too high for full stripe writes,
1608 * way too high for partial stripe writes
1609 */
1610 logical_drive->queue_depth = qdepth;
1611 else
1612 logical_drive->queue_depth = h->nr_cmds;
1613}
1614
1615static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1616 struct hpsa_scsi_dev_t *dev[], int ndevices)
1617{
1618 int i;
1619
1620 for (i = 0; i < ndevices; i++) {
1621 if (dev[i]->devtype != TYPE_DISK)
1622 continue;
1623 if (!is_logical_dev_addr_mode(dev[i]->scsi3addr))
1624 continue;
41ce4c35
SC		 1625
1626 /*
1627 * If offload is currently enabled, the RAID map and
1628 * phys_disk[] assignment *better* not be changing
1629 * and since it isn't changing, we do not need to
1630 * update it.
1631 */
1632 if (dev[i]->offload_enabled)
1633 continue;
1634
03383736
DB		 1635 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1636 }
1637}
1638
4967bd3e 1639static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1640 struct hpsa_scsi_dev_t *sd[], int nsds)
1641{
1642 /* sd contains scsi3 addresses and devtypes, and inquiry
1643 * data. This function takes what's in sd to be the current
1644 * reality and updates h->dev[] to reflect that reality.
1645 */
1646 int i, entry, device_change, changes = 0;
1647 struct hpsa_scsi_dev_t *csd;
1648 unsigned long flags;
1649 struct hpsa_scsi_dev_t **added, **removed;
1650 int nadded, nremoved;
1651 struct Scsi_Host *sh = NULL;
1652
cfe5badc
ST		 1653 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1654 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1655
1656 if (!added || !removed) {
1657 dev_warn(&h->pdev->dev, "out of memory in "
1658 "adjust_hpsa_scsi_table\n");
1659 goto free_and_out;
1660 }
1661
1662 spin_lock_irqsave(&h->devlock, flags);
1663
1664 /* find any devices in h->dev[] that are not in
1665 * sd[] and remove them from h->dev[], and for any
1666 * devices which have changed, remove the old device
1667 * info and add the new device info.
bd9244f7
ST		 1668 * If minor device attributes change, just update
1669 * the existing device structure.
edd16368
SC		 1670 */
1671 i = 0;
1672 nremoved = 0;
1673 nadded = 0;
1674 while (i < h->ndevices) {
1675 csd = h->dev[i];
1676 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1677 if (device_change == DEVICE_NOT_FOUND) {
1678 changes++;
1679 hpsa_scsi_remove_entry(h, hostno, i,
1680 removed, &nremoved);
1681 continue; /* remove ^^^, hence i not incremented */
1682 } else if (device_change == DEVICE_CHANGED) {
1683 changes++;
2a8ccf31
SC		 1684 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1685 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1686 /* Set it to NULL to prevent it from being freed
1687 * at the bottom of hpsa_update_scsi_devices()
1688 */
1689 sd[entry] = NULL;
bd9244f7
ST		 1690 } else if (device_change == DEVICE_UPDATED) {
1691 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1692 }
1693 i++;
1694 }
1695
1696 /* Now, make sure every device listed in sd[] is also
1697 * listed in h->dev[], adding them if they aren't found
1698 */
1699
1700 for (i = 0; i < nsds; i++) {
1701 if (!sd[i]) /* if already added above. */
1702 continue;
9846590e
SC		 1703
1704 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1705 * as the SCSI mid-layer does not handle such devices well.
1706 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1707 * at 160Hz, and prevents the system from coming up.
1708 */
1709 if (sd[i]->volume_offline) {
1710 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1711 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1712 continue;
1713 }
1714
edd16368
SC		 1715 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1716 h->ndevices, &entry);
1717 if (device_change == DEVICE_NOT_FOUND) {
1718 changes++;
1719 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1720 added, &nadded) != 0)
1721 break;
1722 sd[i] = NULL; /* prevent from being freed later. */
1723 } else if (device_change == DEVICE_CHANGED) {
1724 /* should never happen... */
1725 changes++;
1726 dev_warn(&h->pdev->dev,
1727 "device unexpectedly changed.\n");
1728 /* but if it does happen, we just ignore that device */
1729 }
1730 }
41ce4c35
SC		 1731 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1732
1733 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1734 * any logical drives that need it enabled.
1735 */
1736 for (i = 0; i < h->ndevices; i++)
1737 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1738
edd16368
SC		 1739 spin_unlock_irqrestore(&h->devlock, flags);
1740
9846590e
SC		 1741 /* Monitor devices which are in one of several NOT READY states to be
1742 * brought online later. This must be done without holding h->devlock,
1743 * so don't touch h->dev[]
1744 */
1745 for (i = 0; i < nsds; i++) {
1746 if (!sd[i]) /* if already added above. */
1747 continue;
1748 if (sd[i]->volume_offline)
1749 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1750 }
1751
edd16368
SC		 1752 /* Don't notify scsi mid layer of any changes the first time through
1753 * (or if there are no changes) scsi_scan_host will do it later the
1754 * first time through.
1755 */
1756 if (hostno == -1 || !changes)
1757 goto free_and_out;
1758
1759 sh = h->scsi_host;
1760 /* Notify scsi mid layer of any removed devices */
1761 for (i = 0; i < nremoved; i++) {
41ce4c35
SC		 1762 if (removed[i]->expose_state & HPSA_SCSI_ADD) {
1763 struct scsi_device *sdev =
1764 scsi_device_lookup(sh, removed[i]->bus,
1765 removed[i]->target, removed[i]->lun);
1766 if (sdev != NULL) {
1767 scsi_remove_device(sdev);
1768 scsi_device_put(sdev);
1769 } else {
1770 /*
1771 * We don't expect to get here.
1772 * future cmds to this device will get selection
1773 * timeout as if the device was gone.
1774 */
0d96ef5f
WS		 1775 hpsa_show_dev_msg(KERN_WARNING, h, removed[i],
1776 "didn't find device for removal.");
41ce4c35 1777 }
edd16368
SC		 1778 }
1779 kfree(removed[i]);
1780 removed[i] = NULL;
1781 }
1782
1783 /* Notify scsi mid layer of any added devices */
1784 for (i = 0; i < nadded; i++) {
41ce4c35
SC		 1785 if (!(added[i]->expose_state & HPSA_SCSI_ADD))
1786 continue;
edd16368
SC		 1787 if (scsi_add_device(sh, added[i]->bus,
1788 added[i]->target, added[i]->lun) == 0)
1789 continue;
0d96ef5f
WS		 1790 hpsa_show_dev_msg(KERN_WARNING, h, added[i],
1791 "addition failed, device not added.");
edd16368
SC		 1792 /* now we have to remove it from h->dev,
1793 * since it didn't get added to scsi mid layer
1794 */
1795 fixup_botched_add(h, added[i]);
105a3dbc 1796 added[i] = NULL;
edd16368
SC		 1797 }
1798
1799free_and_out:
1800 kfree(added);
1801 kfree(removed);
edd16368
SC		 1802}
1803
1804/*
9e03aa2f 1805 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1806 * Assume's h->devlock is held.
1807 */
1808static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1809 int bus, int target, int lun)
1810{
1811 int i;
1812 struct hpsa_scsi_dev_t *sd;
1813
1814 for (i = 0; i < h->ndevices; i++) {
1815 sd = h->dev[i];
1816 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1817 return sd;
1818 }
1819 return NULL;
1820}
1821
edd16368
SC		 1822static int hpsa_slave_alloc(struct scsi_device *sdev)
1823{
1824 struct hpsa_scsi_dev_t *sd;
1825 unsigned long flags;
1826 struct ctlr_info *h;
1827
1828 h = sdev_to_hba(sdev);
1829 spin_lock_irqsave(&h->devlock, flags);
1830 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1831 sdev_id(sdev), sdev->lun);
41ce4c35 1832 if (likely(sd)) {
03383736 1833 atomic_set(&sd->ioaccel_cmds_out, 0);
41ce4c35
SC		 1834 sdev->hostdata = (sd->expose_state & HPSA_SCSI_ADD) ? sd : NULL;
1835 } else
1836 sdev->hostdata = NULL;
edd16368
SC		 1837 spin_unlock_irqrestore(&h->devlock, flags);
1838 return 0;
1839}
1840
41ce4c35
SC		 1841/* configure scsi device based on internal per-device structure */
1842static int hpsa_slave_configure(struct scsi_device *sdev)
1843{
1844 struct hpsa_scsi_dev_t *sd;
1845 int queue_depth;
1846
1847 sd = sdev->hostdata;
1848 sdev->no_uld_attach = !sd || !(sd->expose_state & HPSA_ULD_ATTACH);
1849
1850 if (sd)
1851 queue_depth = sd->queue_depth != 0 ?
1852 sd->queue_depth : sdev->host->can_queue;
1853 else
1854 queue_depth = sdev->host->can_queue;
1855
1856 scsi_change_queue_depth(sdev, queue_depth);
1857
1858 return 0;
1859}
1860
edd16368
SC		 1861static void hpsa_slave_destroy(struct scsi_device *sdev)
1862{
bcc44255 1863 /* nothing to do. */
edd16368
SC		 1864}
1865
d9a729f3
WS		 1866static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1867{
1868 int i;
1869
1870 if (!h->ioaccel2_cmd_sg_list)
1871 return;
1872 for (i = 0; i < h->nr_cmds; i++) {
1873 kfree(h->ioaccel2_cmd_sg_list[i]);
1874 h->ioaccel2_cmd_sg_list[i] = NULL;
1875 }
1876 kfree(h->ioaccel2_cmd_sg_list);
1877 h->ioaccel2_cmd_sg_list = NULL;
1878}
1879
1880static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1881{
1882 int i;
1883
1884 if (h->chainsize <= 0)
1885 return 0;
1886
1887 h->ioaccel2_cmd_sg_list =
1888 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
1889 GFP_KERNEL);
1890 if (!h->ioaccel2_cmd_sg_list)
1891 return -ENOMEM;
1892 for (i = 0; i < h->nr_cmds; i++) {
1893 h->ioaccel2_cmd_sg_list[i] =
1894 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
1895 h->maxsgentries, GFP_KERNEL);
1896 if (!h->ioaccel2_cmd_sg_list[i])
1897 goto clean;
1898 }
1899 return 0;
1900
1901clean:
1902 hpsa_free_ioaccel2_sg_chain_blocks(h);
1903 return -ENOMEM;
1904}
1905
33a2ffce
SC		 1906static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1907{
1908 int i;
1909
1910 if (!h->cmd_sg_list)
1911 return;
1912 for (i = 0; i < h->nr_cmds; i++) {
1913 kfree(h->cmd_sg_list[i]);
1914 h->cmd_sg_list[i] = NULL;
1915 }
1916 kfree(h->cmd_sg_list);
1917 h->cmd_sg_list = NULL;
1918}
1919
105a3dbc 1920static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
33a2ffce
SC		 1921{
1922 int i;
1923
1924 if (h->chainsize <= 0)
1925 return 0;
1926
1927 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1928 GFP_KERNEL);
3d4e6af8
RE		 1929 if (!h->cmd_sg_list) {
1930 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1931 return -ENOMEM;
3d4e6af8 1932 }
33a2ffce
SC		 1933 for (i = 0; i < h->nr_cmds; i++) {
1934 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1935 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1936 if (!h->cmd_sg_list[i]) {
1937 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1938 goto clean;
3d4e6af8 1939 }
33a2ffce
SC		 1940 }
1941 return 0;
1942
1943clean:
1944 hpsa_free_sg_chain_blocks(h);
1945 return -ENOMEM;
1946}
1947
d9a729f3
WS		 1948static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
1949 struct io_accel2_cmd *cp, struct CommandList *c)
1950{
1951 struct ioaccel2_sg_element *chain_block;
1952 u64 temp64;
1953 u32 chain_size;
1954
1955 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
1956 chain_size = le32_to_cpu(cp->data_len);
1957 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
1958 PCI_DMA_TODEVICE);
1959 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1960 /* prevent subsequent unmapping */
1961 cp->sg->address = 0;
1962 return -1;
1963 }
1964 cp->sg->address = cpu_to_le64(temp64);
1965 return 0;
1966}
1967
1968static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
1969 struct io_accel2_cmd *cp)
1970{
1971 struct ioaccel2_sg_element *chain_sg;
1972 u64 temp64;
1973 u32 chain_size;
1974
1975 chain_sg = cp->sg;
1976 temp64 = le64_to_cpu(chain_sg->address);
1977 chain_size = le32_to_cpu(cp->data_len);
1978 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
1979}
1980
e2bea6df 1981static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1982 struct CommandList *c)
1983{
1984 struct SGDescriptor *chain_sg, *chain_block;
1985 u64 temp64;
50a0decf 1986 u32 chain_len;
33a2ffce
SC		 1987
1988 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1989 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 1990 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1991 chain_len = sizeof(*chain_sg) *
2b08b3e9 1992 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 1993 chain_sg->Len = cpu_to_le32(chain_len);
1994 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 1995 PCI_DMA_TODEVICE);
e2bea6df
SC		 1996 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1997 /* prevent subsequent unmapping */
50a0decf 1998 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 1999 return -1;
2000 }
50a0decf 2001 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 2002 return 0;
33a2ffce
SC		 2003}
2004
2005static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
2006 struct CommandList *c)
2007{
2008 struct SGDescriptor *chain_sg;
33a2ffce 2009
50a0decf 2010 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 2011 return;
2012
2013 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 2014 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
2015 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 2016}
2017
a09c1441
ST		 2018
2019/* Decode the various types of errors on ioaccel2 path.
2020 * Return 1 for any error that should generate a RAID path retry.
2021 * Return 0 for errors that don't require a RAID path retry.
2022 */
2023static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 2024 struct CommandList *c,
2025 struct scsi_cmnd *cmd,
2026 struct io_accel2_cmd *c2)
2027{
2028 int data_len;
a09c1441 2029 int retry = 0;
c40820d5 2030 u32 ioaccel2_resid = 0;
c349775e
ST		 2031
2032 switch (c2->error_data.serv_response) {
2033 case IOACCEL2_SERV_RESPONSE_COMPLETE:
2034 switch (c2->error_data.status) {
2035 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
2036 break;
2037 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
ee6b1889 2038 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 2039 if (c2->error_data.data_present !=
ee6b1889
SC		 2040 IOACCEL2_SENSE_DATA_PRESENT) {
2041 memset(cmd->sense_buffer, 0,
2042 SCSI_SENSE_BUFFERSIZE);
c349775e 2043 break;
ee6b1889 2044 }
c349775e
ST		 2045 /* copy the sense data */
2046 data_len = c2->error_data.sense_data_len;
2047 if (data_len > SCSI_SENSE_BUFFERSIZE)
2048 data_len = SCSI_SENSE_BUFFERSIZE;
2049 if (data_len > sizeof(c2->error_data.sense_data_buff))
2050 data_len =
2051 sizeof(c2->error_data.sense_data_buff);
2052 memcpy(cmd->sense_buffer,
2053 c2->error_data.sense_data_buff, data_len);
a09c1441 2054 retry = 1;
c349775e
ST		 2055 break;
2056 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
a09c1441 2057 retry = 1;
c349775e
ST		 2058 break;
2059 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
a09c1441 2060 retry = 1;
c349775e
ST		 2061 break;
2062 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 2063 retry = 1;
c349775e
ST		 2064 break;
2065 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
a09c1441 2066 retry = 1;
c349775e
ST		 2067 break;
2068 default:
a09c1441 2069 retry = 1;
c349775e
ST		 2070 break;
2071 }
2072 break;
2073 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 2074 switch (c2->error_data.status) {
2075 case IOACCEL2_STATUS_SR_IO_ERROR:
2076 case IOACCEL2_STATUS_SR_IO_ABORTED:
2077 case IOACCEL2_STATUS_SR_OVERRUN:
2078 retry = 1;
2079 break;
2080 case IOACCEL2_STATUS_SR_UNDERRUN:
2081 cmd->result = (DID_OK << 16); /* host byte */
2082 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2083 ioaccel2_resid = get_unaligned_le32(
2084 &c2->error_data.resid_cnt[0]);
2085 scsi_set_resid(cmd, ioaccel2_resid);
2086 break;
2087 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
2088 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
2089 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
2090 /* We will get an event from ctlr to trigger rescan */
2091 retry = 1;
2092 break;
2093 default:
2094 retry = 1;
c40820d5 2095 }
c349775e
ST		 2096 break;
2097 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
2098 break;
2099 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
2100 break;
2101 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
a09c1441 2102 retry = 1;
c349775e
ST		 2103 break;
2104 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
c349775e
ST		 2105 break;
2106 default:
a09c1441 2107 retry = 1;
c349775e
ST		 2108 break;
2109 }
a09c1441
ST		 2110
2111 return retry; /* retry on raid path? */
c349775e
ST		 2112}
2113
a58e7e53
WS		 2114static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2115 struct CommandList *c)
2116{
d604f533
WS		 2117 bool do_wake = false;
2118
a58e7e53
WS		 2119 /*
2120 * Prevent the following race in the abort handler:
2121 *
2122 * 1. LLD is requested to abort a SCSI command
2123 * 2. The SCSI command completes
2124 * 3. The struct CommandList associated with step 2 is made available
2125 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2126 * 5. Abort handler follows scsi_cmnd->host_scribble and
2127 * finds struct CommandList and tries to aborts it
2128 * Now we have aborted the wrong command.
2129 *
d604f533
WS		 2130 * Reset c->scsi_cmd here so that the abort or reset handler will know
2131 * this command has completed. Then, check to see if the handler is
a58e7e53
WS		 2132 * waiting for this command, and, if so, wake it.
2133 */
2134 c->scsi_cmd = SCSI_CMD_IDLE;
d604f533 2135 mb(); /* Declare command idle before checking for pending events. */
a58e7e53 2136 if (c->abort_pending) {
d604f533 2137 do_wake = true;
a58e7e53 2138 c->abort_pending = false;
a58e7e53 2139 }
d604f533
WS		 2140 if (c->reset_pending) {
2141 unsigned long flags;
2142 struct hpsa_scsi_dev_t *dev;
2143
2144 /*
2145 * There appears to be a reset pending; lock the lock and
2146 * reconfirm. If so, then decrement the count of outstanding
2147 * commands and wake the reset command if this is the last one.
2148 */
2149 spin_lock_irqsave(&h->lock, flags);
2150 dev = c->reset_pending; /* Re-fetch under the lock. */
2151 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2152 do_wake = true;
2153 c->reset_pending = NULL;
2154 spin_unlock_irqrestore(&h->lock, flags);
2155 }
2156
2157 if (do_wake)
2158 wake_up_all(&h->event_sync_wait_queue);
a58e7e53
WS		 2159}
2160
73153fe5
WS		 2161static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2162 struct CommandList *c)
2163{
2164 hpsa_cmd_resolve_events(h, c);
2165 cmd_tagged_free(h, c);
2166}
2167
8a0ff92c
WS		 2168static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2169 struct CommandList *c, struct scsi_cmnd *cmd)
2170{
73153fe5 2171 hpsa_cmd_resolve_and_free(h, c);
8a0ff92c
WS		 2172 cmd->scsi_done(cmd);
2173}
2174
2175static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2176{
2177 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2178 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2179}
2180
a58e7e53
WS		 2181static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2182{
2183 cmd->result = DID_ABORT << 16;
2184}
2185
2186static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2187 struct scsi_cmnd *cmd)
2188{
2189 hpsa_set_scsi_cmd_aborted(cmd);
2190 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2191 c->Request.CDB, c->err_info->ScsiStatus);
73153fe5 2192 hpsa_cmd_resolve_and_free(h, c);
a58e7e53
WS		 2193}
2194
c349775e
ST		 2195static void process_ioaccel2_completion(struct ctlr_info *h,
2196 struct CommandList *c, struct scsi_cmnd *cmd,
2197 struct hpsa_scsi_dev_t *dev)
2198{
2199 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2200
2201 /* check for good status */
2202 if (likely(c2->error_data.serv_response == 0 &&
8a0ff92c
WS		 2203 c2->error_data.status == 0))
2204 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e 2205
8a0ff92c
WS		 2206 /*
2207 * Any RAID offload error results in retry which will use
c349775e
ST		 2208 * the normal I/O path so the controller can handle whatever's
2209 * wrong.
2210 */
2211 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
2212 c2->error_data.serv_response ==
2213 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 2214 if (c2->error_data.status ==
2215 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
2216 dev->offload_enabled = 0;
8a0ff92c
WS		 2217
2218 return hpsa_retry_cmd(h, c);
a09c1441 2219 }
080ef1cc
DB		 2220
2221 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
8a0ff92c 2222 return hpsa_retry_cmd(h, c);
080ef1cc 2223
8a0ff92c 2224 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e
ST		 2225}
2226
9437ac43
SC		 2227/* Returns 0 on success, < 0 otherwise. */
2228static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2229 struct CommandList *cp)
2230{
2231 u8 tmf_status = cp->err_info->ScsiStatus;
2232
2233 switch (tmf_status) {
2234 case CISS_TMF_COMPLETE:
2235 /*
2236 * CISS_TMF_COMPLETE never happens, instead,
2237 * ei->CommandStatus == 0 for this case.
2238 */
2239 case CISS_TMF_SUCCESS:
2240 return 0;
2241 case CISS_TMF_INVALID_FRAME:
2242 case CISS_TMF_NOT_SUPPORTED:
2243 case CISS_TMF_FAILED:
2244 case CISS_TMF_WRONG_LUN:
2245 case CISS_TMF_OVERLAPPED_TAG:
2246 break;
2247 default:
2248 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2249 tmf_status);
2250 break;
2251 }
2252 return -tmf_status;
2253}
2254
1fb011fb 2255static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2256{
2257 struct scsi_cmnd *cmd;
2258 struct ctlr_info *h;
2259 struct ErrorInfo *ei;
283b4a9b 2260 struct hpsa_scsi_dev_t *dev;
d9a729f3 2261 struct io_accel2_cmd *c2;
edd16368 2262
9437ac43
SC		 2263 u8 sense_key;
2264 u8 asc; /* additional sense code */
2265 u8 ascq; /* additional sense code qualifier */
db111e18 2266 unsigned long sense_data_size;
edd16368
SC		 2267
2268 ei = cp->err_info;
7fa3030c 2269 cmd = cp->scsi_cmd;
edd16368 2270 h = cp->h;
283b4a9b 2271 dev = cmd->device->hostdata;
d9a729f3 2272 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2273
2274 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2275 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2276 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2277 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2278
d9a729f3
WS		 2279 if ((cp->cmd_type == CMD_IOACCEL2) &&
2280 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2281 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2282
edd16368
SC		 2283 cmd->result = (DID_OK << 16); /* host byte */
2284 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2285
03383736
DB		 2286 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2287 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2288
25163bd5
WS		 2289 /*
2290 * We check for lockup status here as it may be set for
2291 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2292 * fail_all_oustanding_cmds()
2293 */
2294 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2295 /* DID_NO_CONNECT will prevent a retry */
2296 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 2297 return hpsa_cmd_free_and_done(h, cp, cmd);
25163bd5
WS		 2298 }
2299
d604f533
WS		 2300 if ((unlikely(hpsa_is_pending_event(cp)))) {
2301 if (cp->reset_pending)
2302 return hpsa_cmd_resolve_and_free(h, cp);
2303 if (cp->abort_pending)
2304 return hpsa_cmd_abort_and_free(h, cp, cmd);
2305 }
2306
c349775e
ST		 2307 if (cp->cmd_type == CMD_IOACCEL2)
2308 return process_ioaccel2_completion(h, cp, cmd, dev);
2309
6aa4c361 2310 scsi_set_resid(cmd, ei->ResidualCnt);
8a0ff92c
WS		 2311 if (ei->CommandStatus == 0)
2312 return hpsa_cmd_free_and_done(h, cp, cmd);
6aa4c361 2313
e1f7de0c
MG		 2314 /* For I/O accelerator commands, copy over some fields to the normal
2315 * CISS header used below for error handling.
2316 */
2317 if (cp->cmd_type == CMD_IOACCEL1) {
2318 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2319 cp->Header.SGList = scsi_sg_count(cmd);
2320 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2321 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2322 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2323 cp->Header.tag = c->tag;
e1f7de0c
MG		 2324 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2325 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2326
2327 /* Any RAID offload error results in retry which will use
2328 * the normal I/O path so the controller can handle whatever's
2329 * wrong.
2330 */
2331 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
2332 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2333 dev->offload_enabled = 0;
d604f533 2334 return hpsa_retry_cmd(h, cp);
283b4a9b 2335 }
e1f7de0c
MG		 2336 }
2337
edd16368
SC		 2338 /* an error has occurred */
2339 switch (ei->CommandStatus) {
2340
2341 case CMD_TARGET_STATUS:
9437ac43
SC		 2342 cmd->result |= ei->ScsiStatus;
2343 /* copy the sense data */
2344 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2345 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2346 else
2347 sense_data_size = sizeof(ei->SenseInfo);
2348 if (ei->SenseLen < sense_data_size)
2349 sense_data_size = ei->SenseLen;
2350 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2351 if (ei->ScsiStatus)
2352 decode_sense_data(ei->SenseInfo, sense_data_size,
2353 &sense_key, &asc, &ascq);
edd16368 2354 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2355 if (sense_key == ABORTED_COMMAND) {
2e311fba 2356 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2357 break;
2358 }
edd16368
SC		 2359 break;
2360 }
edd16368
SC		 2361 /* Problem was not a check condition
2362 * Pass it up to the upper layers...
2363 */
2364 if (ei->ScsiStatus) {
2365 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2366 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2367 "Returning result: 0x%x\n",
2368 cp, ei->ScsiStatus,
2369 sense_key, asc, ascq,
2370 cmd->result);
2371 } else { /* scsi status is zero??? How??? */
2372 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2373 "Returning no connection.\n", cp),
2374
2375 /* Ordinarily, this case should never happen,
2376 * but there is a bug in some released firmware
2377 * revisions that allows it to happen if, for
2378 * example, a 4100 backplane loses power and
2379 * the tape drive is in it. We assume that
2380 * it's a fatal error of some kind because we
2381 * can't show that it wasn't. We will make it
2382 * look like selection timeout since that is
2383 * the most common reason for this to occur,
2384 * and it's severe enough.
2385 */
2386
2387 cmd->result = DID_NO_CONNECT << 16;
2388 }
2389 break;
2390
2391 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2392 break;
2393 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2394 dev_warn(&h->pdev->dev,
2395 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2396 break;
2397 case CMD_INVALID: {
2398 /* print_bytes(cp, sizeof(*cp), 1, 0);
2399 print_cmd(cp); */
2400 /* We get CMD_INVALID if you address a non-existent device
2401 * instead of a selection timeout (no response). You will
2402 * see this if you yank out a drive, then try to access it.
2403 * This is kind of a shame because it means that any other
2404 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2405 * missing target. */
2406 cmd->result = DID_NO_CONNECT << 16;
2407 }
2408 break;
2409 case CMD_PROTOCOL_ERR:
256d0eaa 2410 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2411 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2412 cp->Request.CDB);
edd16368
SC		 2413 break;
2414 case CMD_HARDWARE_ERR:
2415 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2416 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2417 cp->Request.CDB);
edd16368
SC		 2418 break;
2419 case CMD_CONNECTION_LOST:
2420 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2421 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2422 cp->Request.CDB);
edd16368
SC		 2423 break;
2424 case CMD_ABORTED:
a58e7e53
WS		 2425 /* Return now to avoid calling scsi_done(). */
2426 return hpsa_cmd_abort_and_free(h, cp, cmd);
edd16368
SC		 2427 case CMD_ABORT_FAILED:
2428 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2429 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2430 cp->Request.CDB);
edd16368
SC		 2431 break;
2432 case CMD_UNSOLICITED_ABORT:
f6e76055 2433 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2434 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2435 cp->Request.CDB);
edd16368
SC		 2436 break;
2437 case CMD_TIMEOUT:
2438 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2439 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2440 cp->Request.CDB);
edd16368 2441 break;
1d5e2ed0
SC		 2442 case CMD_UNABORTABLE:
2443 cmd->result = DID_ERROR << 16;
2444 dev_warn(&h->pdev->dev, "Command unabortable\n");
2445 break;
9437ac43
SC		 2446 case CMD_TMF_STATUS:
2447 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2448 cmd->result = DID_ERROR << 16;
2449 break;
283b4a9b
SC		 2450 case CMD_IOACCEL_DISABLED:
2451 /* This only handles the direct pass-through case since RAID
2452 * offload is handled above. Just attempt a retry.
2453 */
2454 cmd->result = DID_SOFT_ERROR << 16;
2455 dev_warn(&h->pdev->dev,
2456 "cp %p had HP SSD Smart Path error\n", cp);
2457 break;
edd16368
SC		 2458 default:
2459 cmd->result = DID_ERROR << 16;
2460 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2461 cp, ei->CommandStatus);
2462 }
8a0ff92c
WS		 2463
2464 return hpsa_cmd_free_and_done(h, cp, cmd);
edd16368
SC		 2465}
2466
edd16368
SC		 2467static void hpsa_pci_unmap(struct pci_dev *pdev,
2468 struct CommandList *c, int sg_used, int data_direction)
2469{
2470 int i;
edd16368 2471
50a0decf
SC		 2472 for (i = 0; i < sg_used; i++)
2473 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2474 le32_to_cpu(c->SG[i].Len),
2475 data_direction);
edd16368
SC		 2476}
2477
a2dac136 2478static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2479 struct CommandList *cp,
2480 unsigned char *buf,
2481 size_t buflen,
2482 int data_direction)
2483{
01a02ffc 2484 u64 addr64;
edd16368
SC		 2485
2486 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2487 cp->Header.SGList = 0;
50a0decf 2488 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2489 return 0;
edd16368
SC		 2490 }
2491
50a0decf 2492 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2493 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2494 /* Prevent subsequent unmap of something never mapped */
eceaae18 2495 cp->Header.SGList = 0;
50a0decf 2496 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2497 return -1;
eceaae18 2498 }
50a0decf
SC		 2499 cp->SG[0].Addr = cpu_to_le64(addr64);
2500 cp->SG[0].Len = cpu_to_le32(buflen);
2501 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2502 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2503 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2504 return 0;
edd16368
SC		 2505}
2506
25163bd5
WS		 2507#define NO_TIMEOUT ((unsigned long) -1)
2508#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2509static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2510 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2511{
2512 DECLARE_COMPLETION_ONSTACK(wait);
2513
2514 c->waiting = &wait;
25163bd5
WS		 2515 __enqueue_cmd_and_start_io(h, c, reply_queue);
2516 if (timeout_msecs == NO_TIMEOUT) {
2517 /* TODO: get rid of this no-timeout thing */
2518 wait_for_completion_io(&wait);
2519 return IO_OK;
2520 }
2521 if (!wait_for_completion_io_timeout(&wait,
2522 msecs_to_jiffies(timeout_msecs))) {
2523 dev_warn(&h->pdev->dev, "Command timed out.\n");
2524 return -ETIMEDOUT;
2525 }
2526 return IO_OK;
2527}
2528
2529static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2530 int reply_queue, unsigned long timeout_msecs)
2531{
2532 if (unlikely(lockup_detected(h))) {
2533 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2534 return IO_OK;
2535 }
2536 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2537}
2538
094963da
SC		 2539static u32 lockup_detected(struct ctlr_info *h)
2540{
2541 int cpu;
2542 u32 rc, *lockup_detected;
2543
2544 cpu = get_cpu();
2545 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2546 rc = *lockup_detected;
2547 put_cpu();
2548 return rc;
2549}
2550
9c2fc160 2551#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2552static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2553 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2554{
9c2fc160 2555 int backoff_time = 10, retry_count = 0;
25163bd5 2556 int rc;
edd16368
SC		 2557
2558 do {
7630abd0 2559 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2560 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2561 timeout_msecs);
2562 if (rc)
2563 break;
edd16368 2564 retry_count++;
9c2fc160
SC		 2565 if (retry_count > 3) {
2566 msleep(backoff_time);
2567 if (backoff_time < 1000)
2568 backoff_time *= 2;
2569 }
852af20a 2570 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2571 check_for_busy(h, c)) &&
2572 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2573 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2574 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2575 rc = -EIO;
2576 return rc;
edd16368
SC		 2577}
2578
d1e8beac
SC		 2579static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2580 struct CommandList *c)
edd16368 2581{
d1e8beac
SC		 2582 const u8 *cdb = c->Request.CDB;
2583 const u8 *lun = c->Header.LUN.LunAddrBytes;
2584
2585 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2586 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2587 txt, lun[0], lun[1], lun[2], lun[3],
2588 lun[4], lun[5], lun[6], lun[7],
2589 cdb[0], cdb[1], cdb[2], cdb[3],
2590 cdb[4], cdb[5], cdb[6], cdb[7],
2591 cdb[8], cdb[9], cdb[10], cdb[11],
2592 cdb[12], cdb[13], cdb[14], cdb[15]);
2593}
2594
2595static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2596 struct CommandList *cp)
2597{
2598 const struct ErrorInfo *ei = cp->err_info;
edd16368 2599 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2600 u8 sense_key, asc, ascq;
2601 int sense_len;
edd16368 2602
edd16368
SC		 2603 switch (ei->CommandStatus) {
2604 case CMD_TARGET_STATUS:
9437ac43
SC		 2605 if (ei->SenseLen > sizeof(ei->SenseInfo))
2606 sense_len = sizeof(ei->SenseInfo);
2607 else
2608 sense_len = ei->SenseLen;
2609 decode_sense_data(ei->SenseInfo, sense_len,
2610 &sense_key, &asc, &ascq);
d1e8beac
SC		 2611 hpsa_print_cmd(h, "SCSI status", cp);
2612 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2613 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2614 sense_key, asc, ascq);
d1e8beac 2615 else
9437ac43 2616 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2617 if (ei->ScsiStatus == 0)
2618 dev_warn(d, "SCSI status is abnormally zero. "
2619 "(probably indicates selection timeout "
2620 "reported incorrectly due to a known "
2621 "firmware bug, circa July, 2001.)\n");
2622 break;
2623 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2624 break;
2625 case CMD_DATA_OVERRUN:
d1e8beac 2626 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2627 break;
2628 case CMD_INVALID: {
2629 /* controller unfortunately reports SCSI passthru's
2630 * to non-existent targets as invalid commands.
2631 */
d1e8beac
SC		 2632 hpsa_print_cmd(h, "invalid command", cp);
2633 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2634 }
2635 break;
2636 case CMD_PROTOCOL_ERR:
d1e8beac 2637 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2638 break;
2639 case CMD_HARDWARE_ERR:
d1e8beac 2640 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2641 break;
2642 case CMD_CONNECTION_LOST:
d1e8beac 2643 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2644 break;
2645 case CMD_ABORTED:
d1e8beac 2646 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2647 break;
2648 case CMD_ABORT_FAILED:
d1e8beac 2649 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2650 break;
2651 case CMD_UNSOLICITED_ABORT:
d1e8beac 2652 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2653 break;
2654 case CMD_TIMEOUT:
d1e8beac 2655 hpsa_print_cmd(h, "timed out", cp);
edd16368 2656 break;
1d5e2ed0 2657 case CMD_UNABORTABLE:
d1e8beac 2658 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2659 break;
25163bd5
WS		 2660 case CMD_CTLR_LOCKUP:
2661 hpsa_print_cmd(h, "controller lockup detected", cp);
2662 break;
edd16368 2663 default:
d1e8beac
SC		 2664 hpsa_print_cmd(h, "unknown status", cp);
2665 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2666 ei->CommandStatus);
2667 }
2668}
2669
2670static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2671 u16 page, unsigned char *buf,
edd16368
SC		 2672 unsigned char bufsize)
2673{
2674 int rc = IO_OK;
2675 struct CommandList *c;
2676 struct ErrorInfo *ei;
2677
45fcb86e 2678 c = cmd_alloc(h);
edd16368 2679
a2dac136
SC		 2680 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2681 page, scsi3addr, TYPE_CMD)) {
2682 rc = -1;
2683 goto out;
2684 }
25163bd5
WS		 2685 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2686 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2687 if (rc)
2688 goto out;
edd16368
SC		 2689 ei = c->err_info;
2690 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2691 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2692 rc = -1;
2693 }
a2dac136 2694out:
45fcb86e 2695 cmd_free(h, c);
edd16368
SC		 2696 return rc;
2697}
2698
bf711ac6 2699static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2700 u8 reset_type, int reply_queue)
edd16368
SC		 2701{
2702 int rc = IO_OK;
2703 struct CommandList *c;
2704 struct ErrorInfo *ei;
2705
45fcb86e 2706 c = cmd_alloc(h);
edd16368 2707
edd16368 2708
a2dac136 2709 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2710 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2711 scsi3addr, TYPE_MSG);
2712 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
25163bd5
WS		 2713 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2714 if (rc) {
2715 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2716 goto out;
2717 }
edd16368
SC		 2718 /* no unmap needed here because no data xfer. */
2719
2720 ei = c->err_info;
2721 if (ei->CommandStatus != 0) {
d1e8beac 2722 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2723 rc = -1;
2724 }
25163bd5 2725out:
45fcb86e 2726 cmd_free(h, c);
edd16368
SC		 2727 return rc;
2728}
2729
d604f533
WS		 2730static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2731 struct hpsa_scsi_dev_t *dev,
2732 unsigned char *scsi3addr)
2733{
2734 int i;
2735 bool match = false;
2736 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2737 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2738
2739 if (hpsa_is_cmd_idle(c))
2740 return false;
2741
2742 switch (c->cmd_type) {
2743 case CMD_SCSI:
2744 case CMD_IOCTL_PEND:
2745 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2746 sizeof(c->Header.LUN.LunAddrBytes));
2747 break;
2748
2749 case CMD_IOACCEL1:
2750 case CMD_IOACCEL2:
2751 if (c->phys_disk == dev) {
2752 /* HBA mode match */
2753 match = true;
2754 } else {
2755 /* Possible RAID mode -- check each phys dev. */
2756 /* FIXME: Do we need to take out a lock here? If
2757 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2758 * instead. */
2759 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2760 /* FIXME: an alternate test might be
2761 *
2762 * match = dev->phys_disk[i]->ioaccel_handle
2763 * == c2->scsi_nexus; */
2764 match = dev->phys_disk[i] == c->phys_disk;
2765 }
2766 }
2767 break;
2768
2769 case IOACCEL2_TMF:
2770 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2771 match = dev->phys_disk[i]->ioaccel_handle ==
2772 le32_to_cpu(ac->it_nexus);
2773 }
2774 break;
2775
2776 case 0: /* The command is in the middle of being initialized. */
2777 match = false;
2778 break;
2779
2780 default:
2781 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
2782 c->cmd_type);
2783 BUG();
2784 }
2785
2786 return match;
2787}
2788
2789static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
2790 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
2791{
2792 int i;
2793 int rc = 0;
2794
2795 /* We can really only handle one reset at a time */
2796 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
2797 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
2798 return -EINTR;
2799 }
2800
2801 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
2802
2803 for (i = 0; i < h->nr_cmds; i++) {
2804 struct CommandList *c = h->cmd_pool + i;
2805 int refcount = atomic_inc_return(&c->refcount);
2806
2807 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
2808 unsigned long flags;
2809
2810 /*
2811 * Mark the target command as having a reset pending,
2812 * then lock a lock so that the command cannot complete
2813 * while we're considering it. If the command is not
2814 * idle then count it; otherwise revoke the event.
2815 */
2816 c->reset_pending = dev;
2817 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
2818 if (!hpsa_is_cmd_idle(c))
2819 atomic_inc(&dev->reset_cmds_out);
2820 else
2821 c->reset_pending = NULL;
2822 spin_unlock_irqrestore(&h->lock, flags);
2823 }
2824
2825 cmd_free(h, c);
2826 }
2827
2828 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
2829 if (!rc)
2830 wait_event(h->event_sync_wait_queue,
2831 atomic_read(&dev->reset_cmds_out) == 0 ||
2832 lockup_detected(h));
2833
2834 if (unlikely(lockup_detected(h))) {
77678d3a
DB		 2835 dev_warn(&h->pdev->dev,
2836 "Controller lockup detected during reset wait\n");
2837 rc = -ENODEV;
2838 }
d604f533
WS		 2839
2840 if (unlikely(rc))
2841 atomic_set(&dev->reset_cmds_out, 0);
2842
2843 mutex_unlock(&h->reset_mutex);
2844 return rc;
2845}
2846
edd16368
SC		 2847static void hpsa_get_raid_level(struct ctlr_info *h,
2848 unsigned char *scsi3addr, unsigned char *raid_level)
2849{
2850 int rc;
2851 unsigned char *buf;
2852
2853 *raid_level = RAID_UNKNOWN;
2854 buf = kzalloc(64, GFP_KERNEL);
2855 if (!buf)
2856 return;
b7bb24eb 2857 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2858 if (rc == 0)
2859 *raid_level = buf[8];
2860 if (*raid_level > RAID_UNKNOWN)
2861 *raid_level = RAID_UNKNOWN;
2862 kfree(buf);
2863 return;
2864}
2865
283b4a9b
SC		 2866#define HPSA_MAP_DEBUG
2867#ifdef HPSA_MAP_DEBUG
2868static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2869 struct raid_map_data *map_buff)
2870{
2871 struct raid_map_disk_data *dd = &map_buff->data[0];
2872 int map, row, col;
2873 u16 map_cnt, row_cnt, disks_per_row;
2874
2875 if (rc != 0)
2876 return;
2877
2ba8bfc8
SC		 2878 /* Show details only if debugging has been activated. */
2879 if (h->raid_offload_debug < 2)
2880 return;
2881
283b4a9b
SC		 2882 dev_info(&h->pdev->dev, "structure_size = %u\n",
2883 le32_to_cpu(map_buff->structure_size));
2884 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2885 le32_to_cpu(map_buff->volume_blk_size));
2886 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2887 le64_to_cpu(map_buff->volume_blk_cnt));
2888 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2889 map_buff->phys_blk_shift);
2890 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2891 map_buff->parity_rotation_shift);
2892 dev_info(&h->pdev->dev, "strip_size = %u\n",
2893 le16_to_cpu(map_buff->strip_size));
2894 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2895 le64_to_cpu(map_buff->disk_starting_blk));
2896 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2897 le64_to_cpu(map_buff->disk_blk_cnt));
2898 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2899 le16_to_cpu(map_buff->data_disks_per_row));
2900 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2901 le16_to_cpu(map_buff->metadata_disks_per_row));
2902 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2903 le16_to_cpu(map_buff->row_cnt));
2904 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2905 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2906 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2907 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2908 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2909 le16_to_cpu(map_buff->flags) &
2910 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2911 dev_info(&h->pdev->dev, "dekindex = %u\n",
2912 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2913 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2914 for (map = 0; map < map_cnt; map++) {
2915 dev_info(&h->pdev->dev, "Map%u:\n", map);
2916 row_cnt = le16_to_cpu(map_buff->row_cnt);
2917 for (row = 0; row < row_cnt; row++) {
2918 dev_info(&h->pdev->dev, " Row%u:\n", row);
2919 disks_per_row =
2920 le16_to_cpu(map_buff->data_disks_per_row);
2921 for (col = 0; col < disks_per_row; col++, dd++)
2922 dev_info(&h->pdev->dev,
2923 " D%02u: h=0x%04x xor=%u,%u\n",
2924 col, dd->ioaccel_handle,
2925 dd->xor_mult[0], dd->xor_mult[1]);
2926 disks_per_row =
2927 le16_to_cpu(map_buff->metadata_disks_per_row);
2928 for (col = 0; col < disks_per_row; col++, dd++)
2929 dev_info(&h->pdev->dev,
2930 " M%02u: h=0x%04x xor=%u,%u\n",
2931 col, dd->ioaccel_handle,
2932 dd->xor_mult[0], dd->xor_mult[1]);
2933 }
2934 }
2935}
2936#else
2937static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2938 __attribute__((unused)) int rc,
2939 __attribute__((unused)) struct raid_map_data *map_buff)
2940{
2941}
2942#endif
2943
2944static int hpsa_get_raid_map(struct ctlr_info *h,
2945 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2946{
2947 int rc = 0;
2948 struct CommandList *c;
2949 struct ErrorInfo *ei;
2950
45fcb86e 2951 c = cmd_alloc(h);
bf43caf3 2952
283b4a9b
SC		 2953 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2954 sizeof(this_device->raid_map), 0,
2955 scsi3addr, TYPE_CMD)) {
2dd02d74
RE		 2956 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
2957 cmd_free(h, c);
2958 return -1;
283b4a9b 2959 }
25163bd5
WS		 2960 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2961 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2962 if (rc)
2963 goto out;
283b4a9b
SC		 2964 ei = c->err_info;
2965 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2966 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 2967 rc = -1;
2968 goto out;
283b4a9b 2969 }
45fcb86e 2970 cmd_free(h, c);
283b4a9b
SC		 2971
2972 /* @todo in the future, dynamically allocate RAID map memory */
2973 if (le32_to_cpu(this_device->raid_map.structure_size) >
2974 sizeof(this_device->raid_map)) {
2975 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2976 rc = -1;
2977 }
2978 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2979 return rc;
25163bd5
WS		 2980out:
2981 cmd_free(h, c);
2982 return rc;
283b4a9b
SC		 2983}
2984
03383736
DB		 2985static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
2986 unsigned char scsi3addr[], u16 bmic_device_index,
2987 struct bmic_identify_physical_device *buf, size_t bufsize)
2988{
2989 int rc = IO_OK;
2990 struct CommandList *c;
2991 struct ErrorInfo *ei;
2992
2993 c = cmd_alloc(h);
2994 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
2995 0, RAID_CTLR_LUNID, TYPE_CMD);
2996 if (rc)
2997 goto out;
2998
2999 c->Request.CDB[2] = bmic_device_index & 0xff;
3000 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3001
25163bd5
WS		 3002 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
3003 NO_TIMEOUT);
03383736
DB		 3004 ei = c->err_info;
3005 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3006 hpsa_scsi_interpret_error(h, c);
3007 rc = -1;
3008 }
3009out:
3010 cmd_free(h, c);
3011 return rc;
3012}
3013
1b70150a
SC		 3014static int hpsa_vpd_page_supported(struct ctlr_info *h,
3015 unsigned char scsi3addr[], u8 page)
3016{
3017 int rc;
3018 int i;
3019 int pages;
3020 unsigned char *buf, bufsize;
3021
3022 buf = kzalloc(256, GFP_KERNEL);
3023 if (!buf)
3024 return 0;
3025
3026 /* Get the size of the page list first */
3027 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3028 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3029 buf, HPSA_VPD_HEADER_SZ);
3030 if (rc != 0)
3031 goto exit_unsupported;
3032 pages = buf[3];
3033 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3034 bufsize = pages + HPSA_VPD_HEADER_SZ;
3035 else
3036 bufsize = 255;
3037
3038 /* Get the whole VPD page list */
3039 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3040 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3041 buf, bufsize);
3042 if (rc != 0)
3043 goto exit_unsupported;
3044
3045 pages = buf[3];
3046 for (i = 1; i <= pages; i++)
3047 if (buf[3 + i] == page)
3048 goto exit_supported;
3049exit_unsupported:
3050 kfree(buf);
3051 return 0;
3052exit_supported:
3053 kfree(buf);
3054 return 1;
3055}
3056
283b4a9b
SC		 3057static void hpsa_get_ioaccel_status(struct ctlr_info *h,
3058 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3059{
3060 int rc;
3061 unsigned char *buf;
3062 u8 ioaccel_status;
3063
3064 this_device->offload_config = 0;
3065 this_device->offload_enabled = 0;
41ce4c35 3066 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 3067
3068 buf = kzalloc(64, GFP_KERNEL);
3069 if (!buf)
3070 return;
1b70150a
SC		 3071 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
3072 goto out;
283b4a9b 3073 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 3074 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 3075 if (rc != 0)
3076 goto out;
3077
3078#define IOACCEL_STATUS_BYTE 4
3079#define OFFLOAD_CONFIGURED_BIT 0x01
3080#define OFFLOAD_ENABLED_BIT 0x02
3081 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
3082 this_device->offload_config =
3083 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3084 if (this_device->offload_config) {
3085 this_device->offload_enabled =
3086 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3087 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3088 this_device->offload_enabled = 0;
3089 }
41ce4c35 3090 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 3091out:
3092 kfree(buf);
3093 return;
3094}
3095
edd16368
SC		 3096/* Get the device id from inquiry page 0x83 */
3097static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
3098 unsigned char *device_id, int buflen)
3099{
3100 int rc;
3101 unsigned char *buf;
3102
3103 if (buflen > 16)
3104 buflen = 16;
3105 buf = kzalloc(64, GFP_KERNEL);
3106 if (!buf)
a84d794d 3107 return -ENOMEM;
b7bb24eb 3108 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 3109 if (rc == 0)
3110 memcpy(device_id, &buf[8], buflen);
3111 kfree(buf);
3112 return rc != 0;
3113}
3114
3115static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 3116 void *buf, int bufsize,
edd16368
SC		 3117 int extended_response)
3118{
3119 int rc = IO_OK;
3120 struct CommandList *c;
3121 unsigned char scsi3addr[8];
3122 struct ErrorInfo *ei;
3123
45fcb86e 3124 c = cmd_alloc(h);
bf43caf3 3125
e89c0ae7
SC		 3126 /* address the controller */
3127 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 3128 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3129 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3130 rc = -1;
3131 goto out;
3132 }
edd16368
SC		 3133 if (extended_response)
3134 c->Request.CDB[1] = extended_response;
25163bd5
WS		 3135 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3136 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3137 if (rc)
3138 goto out;
edd16368
SC		 3139 ei = c->err_info;
3140 if (ei->CommandStatus != 0 &&
3141 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3142 hpsa_scsi_interpret_error(h, c);
edd16368 3143 rc = -1;
283b4a9b 3144 } else {
03383736
DB		 3145 struct ReportLUNdata *rld = buf;
3146
3147 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 3148 dev_err(&h->pdev->dev,
3149 "report luns requested format %u, got %u\n",
3150 extended_response,
03383736 3151 rld->extended_response_flag);
283b4a9b
SC		 3152 rc = -1;
3153 }
edd16368 3154 }
a2dac136 3155out:
45fcb86e 3156 cmd_free(h, c);
edd16368
SC		 3157 return rc;
3158}
3159
3160static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 3161 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 3162{
03383736
DB		 3163 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3164 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 3165}
3166
3167static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3168 struct ReportLUNdata *buf, int bufsize)
3169{
3170 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3171}
3172
3173static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3174 int bus, int target, int lun)
3175{
3176 device->bus = bus;
3177 device->target = target;
3178 device->lun = lun;
3179}
3180
9846590e
SC		 3181/* Use VPD inquiry to get details of volume status */
3182static int hpsa_get_volume_status(struct ctlr_info *h,
3183 unsigned char scsi3addr[])
3184{
3185 int rc;
3186 int status;
3187 int size;
3188 unsigned char *buf;
3189
3190 buf = kzalloc(64, GFP_KERNEL);
3191 if (!buf)
3192 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3193
3194 /* Does controller have VPD for logical volume status? */
24a4b078 3195 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 3196 goto exit_failed;
9846590e
SC		 3197
3198 /* Get the size of the VPD return buffer */
3199 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3200 buf, HPSA_VPD_HEADER_SZ);
24a4b078 3201 if (rc != 0)
9846590e 3202 goto exit_failed;
9846590e
SC		 3203 size = buf[3];
3204
3205 /* Now get the whole VPD buffer */
3206 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3207 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 3208 if (rc != 0)
9846590e 3209 goto exit_failed;
9846590e
SC		 3210 status = buf[4]; /* status byte */
3211
3212 kfree(buf);
3213 return status;
3214exit_failed:
3215 kfree(buf);
3216 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3217}
3218
3219/* Determine offline status of a volume.
3220 * Return either:
3221 * 0 (not offline)
67955ba3 3222 * 0xff (offline for unknown reasons)
9846590e
SC		 3223 * # (integer code indicating one of several NOT READY states
3224 * describing why a volume is to be kept offline)
3225 */
67955ba3 3226static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 3227 unsigned char scsi3addr[])
3228{
3229 struct CommandList *c;
9437ac43
SC		 3230 unsigned char *sense;
3231 u8 sense_key, asc, ascq;
3232 int sense_len;
25163bd5 3233 int rc, ldstat = 0;
9846590e
SC		 3234 u16 cmd_status;
3235 u8 scsi_status;
3236#define ASC_LUN_NOT_READY 0x04
3237#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3238#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3239
3240 c = cmd_alloc(h);
bf43caf3 3241
9846590e 3242 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
25163bd5
WS		 3243 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3244 if (rc) {
3245 cmd_free(h, c);
3246 return 0;
3247 }
9846590e 3248 sense = c->err_info->SenseInfo;
9437ac43
SC		 3249 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3250 sense_len = sizeof(c->err_info->SenseInfo);
3251 else
3252 sense_len = c->err_info->SenseLen;
3253 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 3254 cmd_status = c->err_info->CommandStatus;
3255 scsi_status = c->err_info->ScsiStatus;
3256 cmd_free(h, c);
3257 /* Is the volume 'not ready'? */
3258 if (cmd_status != CMD_TARGET_STATUS ||
3259 scsi_status != SAM_STAT_CHECK_CONDITION ||
3260 sense_key != NOT_READY ||
3261 asc != ASC_LUN_NOT_READY) {
3262 return 0;
3263 }
3264
3265 /* Determine the reason for not ready state */
3266 ldstat = hpsa_get_volume_status(h, scsi3addr);
3267
3268 /* Keep volume offline in certain cases: */
3269 switch (ldstat) {
3270 case HPSA_LV_UNDERGOING_ERASE:
5ca01204 3271 case HPSA_LV_NOT_AVAILABLE:
9846590e
SC		 3272 case HPSA_LV_UNDERGOING_RPI:
3273 case HPSA_LV_PENDING_RPI:
3274 case HPSA_LV_ENCRYPTED_NO_KEY:
3275 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3276 case HPSA_LV_UNDERGOING_ENCRYPTION:
3277 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3278 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3279 return ldstat;
3280 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3281 /* If VPD status page isn't available,
3282 * use ASC/ASCQ to determine state
3283 */
3284 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3285 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3286 return ldstat;
3287 break;
3288 default:
3289 break;
3290 }
3291 return 0;
3292}
3293
9b5c48c2
SC		 3294/*
3295 * Find out if a logical device supports aborts by simply trying one.
3296 * Smart Array may claim not to support aborts on logical drives, but
3297 * if a MSA2000 * is connected, the drives on that will be presented
3298 * by the Smart Array as logical drives, and aborts may be sent to
3299 * those devices successfully. So the simplest way to find out is
3300 * to simply try an abort and see how the device responds.
3301 */
3302static int hpsa_device_supports_aborts(struct ctlr_info *h,
3303 unsigned char *scsi3addr)
3304{
3305 struct CommandList *c;
3306 struct ErrorInfo *ei;
3307 int rc = 0;
3308
3309 u64 tag = (u64) -1; /* bogus tag */
3310
3311 /* Assume that physical devices support aborts */
3312 if (!is_logical_dev_addr_mode(scsi3addr))
3313 return 1;
3314
3315 c = cmd_alloc(h);
bf43caf3 3316
9b5c48c2
SC		 3317 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
3318 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3319 /* no unmap needed here because no data xfer. */
3320 ei = c->err_info;
3321 switch (ei->CommandStatus) {
3322 case CMD_INVALID:
3323 rc = 0;
3324 break;
3325 case CMD_UNABORTABLE:
3326 case CMD_ABORT_FAILED:
3327 rc = 1;
3328 break;
9437ac43
SC		 3329 case CMD_TMF_STATUS:
3330 rc = hpsa_evaluate_tmf_status(h, c);
3331 break;
9b5c48c2
SC		 3332 default:
3333 rc = 0;
3334 break;
3335 }
3336 cmd_free(h, c);
3337 return rc;
3338}
3339
edd16368 3340static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3341 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3342 unsigned char *is_OBDR_device)
edd16368 3343{
0b0e1d6c
SC		 3344
3345#define OBDR_SIG_OFFSET 43
3346#define OBDR_TAPE_SIG "$DR-10"
3347#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3348#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3349
ea6d3bc3 3350 unsigned char *inq_buff;
0b0e1d6c 3351 unsigned char *obdr_sig;
edd16368 3352
ea6d3bc3 3353 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 3354 if (!inq_buff)
3355 goto bail_out;
3356
edd16368
SC		 3357 /* Do an inquiry to the device to see what it is. */
3358 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3359 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3360 /* Inquiry failed (msg printed already) */
3361 dev_err(&h->pdev->dev,
3362 "hpsa_update_device_info: inquiry failed\n");
3363 goto bail_out;
3364 }
3365
edd16368
SC		 3366 this_device->devtype = (inq_buff[0] & 0x1f);
3367 memcpy(this_device->scsi3addr, scsi3addr, 8);
3368 memcpy(this_device->vendor, &inq_buff[8],
3369 sizeof(this_device->vendor));
3370 memcpy(this_device->model, &inq_buff[16],
3371 sizeof(this_device->model));
edd16368
SC		 3372 memset(this_device->device_id, 0,
3373 sizeof(this_device->device_id));
3374 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
3375 sizeof(this_device->device_id));
3376
3377 if (this_device->devtype == TYPE_DISK &&
283b4a9b 3378 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3379 int volume_offline;
3380
edd16368 3381 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3382 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3383 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3384 volume_offline = hpsa_volume_offline(h, scsi3addr);
3385 if (volume_offline < 0 || volume_offline > 0xff)
3386 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3387 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3388 } else {
edd16368 3389 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3390 this_device->offload_config = 0;
3391 this_device->offload_enabled = 0;
41ce4c35 3392 this_device->offload_to_be_enabled = 0;
a3144e0b 3393 this_device->hba_ioaccel_enabled = 0;
9846590e 3394 this_device->volume_offline = 0;
03383736 3395 this_device->queue_depth = h->nr_cmds;
283b4a9b 3396 }
edd16368 3397
0b0e1d6c
SC		 3398 if (is_OBDR_device) {
3399 /* See if this is a One-Button-Disaster-Recovery device
3400 * by looking for "$DR-10" at offset 43 in inquiry data.
3401 */
3402 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3403 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3404 strncmp(obdr_sig, OBDR_TAPE_SIG,
3405 OBDR_SIG_LEN) == 0);
3406 }
edd16368
SC		 3407 kfree(inq_buff);
3408 return 0;
3409
3410bail_out:
3411 kfree(inq_buff);
3412 return 1;
3413}
3414
9b5c48c2
SC		 3415static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3416 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3417{
3418 unsigned long flags;
3419 int rc, entry;
3420 /*
3421 * See if this device supports aborts. If we already know
3422 * the device, we already know if it supports aborts, otherwise
3423 * we have to find out if it supports aborts by trying one.
3424 */
3425 spin_lock_irqsave(&h->devlock, flags);
3426 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3427 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3428 entry >= 0 && entry < h->ndevices) {
3429 dev->supports_aborts = h->dev[entry]->supports_aborts;
3430 spin_unlock_irqrestore(&h->devlock, flags);
3431 } else {
3432 spin_unlock_irqrestore(&h->devlock, flags);
3433 dev->supports_aborts =
3434 hpsa_device_supports_aborts(h, scsi3addr);
3435 if (dev->supports_aborts < 0)
3436 dev->supports_aborts = 0;
3437 }
3438}
3439
4f4eb9f1 3440static unsigned char *ext_target_model[] = {
edd16368
SC		 3441 "MSA2012",
3442 "MSA2024",
3443 "MSA2312",
3444 "MSA2324",
fda38518 3445 "P2000 G3 SAS",
e06c8e5c 3446 "MSA 2040 SAS",
edd16368
SC		 3447 NULL,
3448};
3449
4f4eb9f1 3450static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 3451{
3452 int i;
3453
4f4eb9f1
ST		 3454 for (i = 0; ext_target_model[i]; i++)
3455 if (strncmp(device->model, ext_target_model[i],
3456 strlen(ext_target_model[i])) == 0)
edd16368
SC		 3457 return 1;
3458 return 0;
3459}
3460
3461/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 3462 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 3463 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
3464 * Logical drive target and lun are assigned at this time, but
3465 * physical device lun and target assignment are deferred (assigned
3466 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
3467 */
3468static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3469 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3470{
1f310bde
SC		 3471 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
3472
3473 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3474 /* physical device, target and lun filled in later */
edd16368 3475 if (is_hba_lunid(lunaddrbytes))
1f310bde 3476 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 3477 else
1f310bde
SC		 3478 /* defer target, lun assignment for physical devices */
3479 hpsa_set_bus_target_lun(device, 2, -1, -1);
3480 return;
3481 }
3482 /* It's a logical device */
4f4eb9f1
ST		 3483 if (is_ext_target(h, device)) {
3484 /* external target way, put logicals on bus 1
1f310bde
SC		 3485 * and match target/lun numbers box
3486 * reports, other smart array, bus 0, target 0, match lunid
3487 */
3488 hpsa_set_bus_target_lun(device,
3489 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
3490 return;
edd16368 3491 }
1f310bde 3492 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 3493}
3494
3495/*
3496 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 3497 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 3498 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
3499 * it for some reason. *tmpdevice is the target we're adding,
3500 * this_device is a pointer into the current element of currentsd[]
3501 * that we're building up in update_scsi_devices(), below.
3502 * lunzerobits is a bitmap that tracks which targets already have a
3503 * lun 0 assigned.
3504 * Returns 1 if an enclosure was added, 0 if not.
3505 */
4f4eb9f1 3506static int add_ext_target_dev(struct ctlr_info *h,
edd16368 3507 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 3508 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 3509 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 3510{
3511 unsigned char scsi3addr[8];
3512
1f310bde 3513 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 3514 return 0; /* There is already a lun 0 on this target. */
3515
3516 if (!is_logical_dev_addr_mode(lunaddrbytes))
3517 return 0; /* It's the logical targets that may lack lun 0. */
3518
4f4eb9f1
ST		 3519 if (!is_ext_target(h, tmpdevice))
3520 return 0; /* Only external target devices have this problem. */
edd16368 3521
1f310bde 3522 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 3523 return 0;
3524
c4f8a299 3525 memset(scsi3addr, 0, 8);
1f310bde 3526 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 3527 if (is_hba_lunid(scsi3addr))
3528 return 0; /* Don't add the RAID controller here. */
3529
339b2b14
SC		 3530 if (is_scsi_rev_5(h))
3531 return 0; /* p1210m doesn't need to do this. */
3532
4f4eb9f1 3533 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 3534 dev_warn(&h->pdev->dev, "Maximum number of external "
3535 "target devices exceeded. Check your hardware "
edd16368
SC		 3536 "configuration.");
3537 return 0;
3538 }
3539
0b0e1d6c 3540 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 3541 return 0;
4f4eb9f1 3542 (*n_ext_target_devs)++;
1f310bde
SC		 3543 hpsa_set_bus_target_lun(this_device,
3544 tmpdevice->bus, tmpdevice->target, 0);
9b5c48c2 3545 hpsa_update_device_supports_aborts(h, this_device, scsi3addr);
1f310bde 3546 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 3547 return 1;
3548}
3549
54b6e9e9
ST		 3550/*
3551 * Get address of physical disk used for an ioaccel2 mode command:
3552 * 1. Extract ioaccel2 handle from the command.
3553 * 2. Find a matching ioaccel2 handle from list of physical disks.
3554 * 3. Return:
3555 * 1 and set scsi3addr to address of matching physical
3556 * 0 if no matching physical disk was found.
3557 */
3558static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3559 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3560{
41ce4c35
SC		 3561 struct io_accel2_cmd *c2 =
3562 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3563 unsigned long flags;
54b6e9e9 3564 int i;
54b6e9e9 3565
41ce4c35
SC		 3566 spin_lock_irqsave(&h->devlock, flags);
3567 for (i = 0; i < h->ndevices; i++)
3568 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3569 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3570 sizeof(h->dev[i]->scsi3addr));
3571 spin_unlock_irqrestore(&h->devlock, flags);
3572 return 1;
3573 }
3574 spin_unlock_irqrestore(&h->devlock, flags);
3575 return 0;
54b6e9e9 3576}
41ce4c35 3577
edd16368
SC		 3578/*
3579 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3580 * logdev. The number of luns in physdev and logdev are returned in
3581 * *nphysicals and *nlogicals, respectively.
3582 * Returns 0 on success, -1 otherwise.
3583 */
3584static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3585 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3586 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3587{
03383736 3588 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3589 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3590 return -1;
3591 }
03383736 3592 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3593 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3594 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3595 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3596 *nphysicals = HPSA_MAX_PHYS_LUN;
3597 }
03383736 3598 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3599 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3600 return -1;
3601 }
6df1e954 3602 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3603 /* Reject Logicals in excess of our max capability. */
3604 if (*nlogicals > HPSA_MAX_LUN) {
3605 dev_warn(&h->pdev->dev,
3606 "maximum logical LUNs (%d) exceeded. "
3607 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3608 *nlogicals - HPSA_MAX_LUN);
3609 *nlogicals = HPSA_MAX_LUN;
3610 }
3611 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3612 dev_warn(&h->pdev->dev,
3613 "maximum logical + physical LUNs (%d) exceeded. "
3614 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3615 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3616 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3617 }
3618 return 0;
3619}
3620
42a91641
DB		 3621static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3622 int i, int nphysicals, int nlogicals,
a93aa1fe 3623 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3624 struct ReportLUNdata *logdev_list)
3625{
3626 /* Helper function, figure out where the LUN ID info is coming from
3627 * given index i, lists of physical and logical devices, where in
3628 * the list the raid controller is supposed to appear (first or last)
3629 */
3630
3631 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3632 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3633
3634 if (i == raid_ctlr_position)
3635 return RAID_CTLR_LUNID;
3636
3637 if (i < logicals_start)
d5b5d964
SC		 3638 return &physdev_list->LUN[i -
3639 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3640
3641 if (i < last_device)
3642 return &logdev_list->LUN[i - nphysicals -
3643 (raid_ctlr_position == 0)][0];
3644 BUG();
3645 return NULL;
3646}
3647
03383736
DB		 3648/* get physical drive ioaccel handle and queue depth */
3649static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3650 struct hpsa_scsi_dev_t *dev,
3651 u8 *lunaddrbytes,
3652 struct bmic_identify_physical_device *id_phys)
3653{
3654 int rc;
3655 struct ext_report_lun_entry *rle =
3656 (struct ext_report_lun_entry *) lunaddrbytes;
3657
3658 dev->ioaccel_handle = rle->ioaccel_handle;
a3144e0b
JH		 3659 if (PHYS_IOACCEL(lunaddrbytes) && dev->ioaccel_handle)
3660 dev->hba_ioaccel_enabled = 1;
03383736
DB		 3661 memset(id_phys, 0, sizeof(*id_phys));
3662 rc = hpsa_bmic_id_physical_device(h, lunaddrbytes,
3663 GET_BMIC_DRIVE_NUMBER(lunaddrbytes), id_phys,
3664 sizeof(*id_phys));
3665 if (!rc)
3666 /* Reserve space for FW operations */
3667#define DRIVE_CMDS_RESERVED_FOR_FW 2
3668#define DRIVE_QUEUE_DEPTH 7
3669 dev->queue_depth =
3670 le16_to_cpu(id_phys->current_queue_depth_limit) -
3671 DRIVE_CMDS_RESERVED_FOR_FW;
3672 else
3673 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
3674 atomic_set(&dev->ioaccel_cmds_out, 0);
d604f533 3675 atomic_set(&dev->reset_cmds_out, 0);
03383736
DB		 3676}
3677
8270b862
JH		 3678static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
3679 u8 *lunaddrbytes,
3680 struct bmic_identify_physical_device *id_phys)
3681{
3682 if (PHYS_IOACCEL(lunaddrbytes)
3683 && this_device->ioaccel_handle)
3684 this_device->hba_ioaccel_enabled = 1;
3685
3686 memcpy(&this_device->active_path_index,
3687 &id_phys->active_path_number,
3688 sizeof(this_device->active_path_index));
3689 memcpy(&this_device->path_map,
3690 &id_phys->redundant_path_present_map,
3691 sizeof(this_device->path_map));
3692 memcpy(&this_device->box,
3693 &id_phys->alternate_paths_phys_box_on_port,
3694 sizeof(this_device->box));
3695 memcpy(&this_device->phys_connector,
3696 &id_phys->alternate_paths_phys_connector,
3697 sizeof(this_device->phys_connector));
3698 memcpy(&this_device->bay,
3699 &id_phys->phys_bay_in_box,
3700 sizeof(this_device->bay));
3701}
3702
edd16368
SC		 3703static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
3704{
3705 /* the idea here is we could get notified
3706 * that some devices have changed, so we do a report
3707 * physical luns and report logical luns cmd, and adjust
3708 * our list of devices accordingly.
3709 *
3710 * The scsi3addr's of devices won't change so long as the
3711 * adapter is not reset. That means we can rescan and
3712 * tell which devices we already know about, vs. new
3713 * devices, vs. disappearing devices.
3714 */
a93aa1fe 3715 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3716 struct ReportLUNdata *logdev_list = NULL;
03383736 3717 struct bmic_identify_physical_device *id_phys = NULL;
01a02ffc
SC		 3718 u32 nphysicals = 0;
3719 u32 nlogicals = 0;
3720 u32 ndev_allocated = 0;
edd16368
SC		 3721 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3722 int ncurrent = 0;
4f4eb9f1 3723 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3724 int raid_ctlr_position;
aca4a520 3725 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3726
cfe5badc 3727 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 3728 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3729 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 3730 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 3731 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
edd16368 3732
03383736
DB		 3733 if (!currentsd || !physdev_list || !logdev_list ||
3734 !tmpdevice || !id_phys) {
edd16368
SC		 3735 dev_err(&h->pdev->dev, "out of memory\n");
3736 goto out;
3737 }
3738 memset(lunzerobits, 0, sizeof(lunzerobits));
3739
03383736
DB		 3740 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
3741 logdev_list, &nlogicals))
edd16368
SC		 3742 goto out;
3743
aca4a520
ST		 3744 /* We might see up to the maximum number of logical and physical disks
3745 * plus external target devices, and a device for the local RAID
3746 * controller.
edd16368 3747 */
aca4a520 3748 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3749
3750 /* Allocate the per device structures */
3751 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3752 if (i >= HPSA_MAX_DEVICES) {
3753 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3754 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3755 ndevs_to_allocate - HPSA_MAX_DEVICES);
3756 break;
3757 }
3758
edd16368
SC		 3759 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3760 if (!currentsd[i]) {
3761 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3762 __FILE__, __LINE__);
3763 goto out;
3764 }
3765 ndev_allocated++;
3766 }
3767
8645291b 3768 if (is_scsi_rev_5(h))
339b2b14
SC		 3769 raid_ctlr_position = 0;
3770 else
3771 raid_ctlr_position = nphysicals + nlogicals;
3772
edd16368 3773 /* adjust our table of devices */
4f4eb9f1 3774 n_ext_target_devs = 0;
edd16368 3775 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3776 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3777
3778 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3779 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3780 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 3781
3782 /* skip masked non-disk devices */
3783 if (MASKED_DEVICE(lunaddrbytes))
3784 if (i < nphysicals + (raid_ctlr_position == 0) &&
3785 NON_DISK_PHYS_DEV(lunaddrbytes))
3786 continue;
edd16368
SC		 3787
3788 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3789 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3790 &is_OBDR))
edd16368 3791 continue; /* skip it if we can't talk to it. */
1f310bde 3792 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 3793 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 3794 this_device = currentsd[ncurrent];
3795
3796 /*
4f4eb9f1 3797 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3798 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3799 * is nonetheless an enclosure device there. We have to
3800 * present that otherwise linux won't find anything if
3801 * there is no lun 0.
3802 */
4f4eb9f1 3803 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3804 lunaddrbytes, lunzerobits,
4f4eb9f1 3805 &n_ext_target_devs)) {
edd16368
SC		 3806 ncurrent++;
3807 this_device = currentsd[ncurrent];
3808 }
3809
3810 *this_device = *tmpdevice;
edd16368 3811
41ce4c35
SC		 3812 /* do not expose masked devices */
3813 if (MASKED_DEVICE(lunaddrbytes) &&
3814 i < nphysicals + (raid_ctlr_position == 0)) {
41ce4c35
SC		 3815 this_device->expose_state = HPSA_DO_NOT_EXPOSE;
3816 } else {
3817 this_device->expose_state =
3818 HPSA_SG_ATTACH | HPSA_ULD_ATTACH;
3819 }
3820
edd16368 3821 switch (this_device->devtype) {
0b0e1d6c 3822 case TYPE_ROM:
edd16368
SC		 3823 /* We don't *really* support actual CD-ROM devices,
3824 * just "One Button Disaster Recovery" tape drive
3825 * which temporarily pretends to be a CD-ROM drive.
3826 * So we check that the device is really an OBDR tape
3827 * device by checking for "$DR-10" in bytes 43-48 of
3828 * the inquiry data.
3829 */
0b0e1d6c
SC		 3830 if (is_OBDR)
3831 ncurrent++;
edd16368
SC		 3832 break;
3833 case TYPE_DISK:
b9092b79
KB		 3834 if (i < nphysicals + (raid_ctlr_position == 0)) {
3835 /* The disk is in HBA mode. */
3836 /* Never use RAID mapper in HBA mode. */
ecf418d1 3837 this_device->offload_enabled = 0;
b9092b79
KB		 3838 hpsa_get_ioaccel_drive_info(h, this_device,
3839 lunaddrbytes, id_phys);
3840 hpsa_get_path_info(this_device, lunaddrbytes,
3841 id_phys);
3842 }
ecf418d1 3843 ncurrent++;
edd16368
SC		 3844 break;
3845 case TYPE_TAPE:
3846 case TYPE_MEDIUM_CHANGER:
41ce4c35 3847 case TYPE_ENCLOSURE:
b9092b79 3848 ncurrent++;
41ce4c35 3849 break;
edd16368
SC		 3850 case TYPE_RAID:
3851 /* Only present the Smartarray HBA as a RAID controller.
3852 * If it's a RAID controller other than the HBA itself
3853 * (an external RAID controller, MSA500 or similar)
3854 * don't present it.
3855 */
3856 if (!is_hba_lunid(lunaddrbytes))
3857 break;
3858 ncurrent++;
3859 break;
3860 default:
3861 break;
3862 }
cfe5badc 3863 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3864 break;
3865 }
3866 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3867out:
3868 kfree(tmpdevice);
3869 for (i = 0; i < ndev_allocated; i++)
3870 kfree(currentsd[i]);
3871 kfree(currentsd);
edd16368
SC		 3872 kfree(physdev_list);
3873 kfree(logdev_list);
03383736 3874 kfree(id_phys);
edd16368
SC		 3875}
3876
ec5cbf04
WS		 3877static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3878 struct scatterlist *sg)
3879{
3880 u64 addr64 = (u64) sg_dma_address(sg);
3881 unsigned int len = sg_dma_len(sg);
3882
3883 desc->Addr = cpu_to_le64(addr64);
3884 desc->Len = cpu_to_le32(len);
3885 desc->Ext = 0;
3886}
3887
c7ee65b3
WS		 3888/*
3889 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3890 * dma mapping and fills in the scatter gather entries of the
3891 * hpsa command, cp.
3892 */
33a2ffce 3893static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3894 struct CommandList *cp,
3895 struct scsi_cmnd *cmd)
3896{
edd16368 3897 struct scatterlist *sg;
b3a7ba7c 3898 int use_sg, i, sg_limit, chained, last_sg;
33a2ffce 3899 struct SGDescriptor *curr_sg;
edd16368 3900
33a2ffce 3901 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3902
3903 use_sg = scsi_dma_map(cmd);
3904 if (use_sg < 0)
3905 return use_sg;
3906
3907 if (!use_sg)
3908 goto sglist_finished;
3909
b3a7ba7c
WS		 3910 /*
3911 * If the number of entries is greater than the max for a single list,
3912 * then we have a chained list; we will set up all but one entry in the
3913 * first list (the last entry is saved for link information);
3914 * otherwise, we don't have a chained list and we'll set up at each of
3915 * the entries in the one list.
3916 */
33a2ffce 3917 curr_sg = cp->SG;
b3a7ba7c
WS		 3918 chained = use_sg > h->max_cmd_sg_entries;
3919 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
3920 last_sg = scsi_sg_count(cmd) - 1;
3921 scsi_for_each_sg(cmd, sg, sg_limit, i) {
ec5cbf04 3922 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 3923 curr_sg++;
3924 }
ec5cbf04 3925
b3a7ba7c
WS		 3926 if (chained) {
3927 /*
3928 * Continue with the chained list. Set curr_sg to the chained
3929 * list. Modify the limit to the total count less the entries
3930 * we've already set up. Resume the scan at the list entry
3931 * where the previous loop left off.
3932 */
3933 curr_sg = h->cmd_sg_list[cp->cmdindex];
3934 sg_limit = use_sg - sg_limit;
3935 for_each_sg(sg, sg, sg_limit, i) {
3936 hpsa_set_sg_descriptor(curr_sg, sg);
3937 curr_sg++;
3938 }
3939 }
3940
ec5cbf04 3941 /* Back the pointer up to the last entry and mark it as "last". */
b3a7ba7c 3942 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3943
3944 if (use_sg + chained > h->maxSG)
3945 h->maxSG = use_sg + chained;
3946
3947 if (chained) {
3948 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3949 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3950 if (hpsa_map_sg_chain_block(h, cp)) {
3951 scsi_dma_unmap(cmd);
3952 return -1;
3953 }
33a2ffce 3954 return 0;
edd16368
SC		 3955 }
3956
3957sglist_finished:
3958
01a02ffc 3959 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 3960 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 3961 return 0;
3962}
3963
283b4a9b
SC		 3964#define IO_ACCEL_INELIGIBLE (1)
3965static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3966{
3967 int is_write = 0;
3968 u32 block;
3969 u32 block_cnt;
3970
3971 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3972 switch (cdb[0]) {
3973 case WRITE_6:
3974 case WRITE_12:
3975 is_write = 1;
3976 case READ_6:
3977 case READ_12:
3978 if (*cdb_len == 6) {
3979 block = (((u32) cdb[2]) << 8) | cdb[3];
3980 block_cnt = cdb[4];
3981 } else {
3982 BUG_ON(*cdb_len != 12);
3983 block = (((u32) cdb[2]) << 24) |
3984 (((u32) cdb[3]) << 16) |
3985 (((u32) cdb[4]) << 8) |
3986 cdb[5];
3987 block_cnt =
3988 (((u32) cdb[6]) << 24) |
3989 (((u32) cdb[7]) << 16) |
3990 (((u32) cdb[8]) << 8) |
3991 cdb[9];
3992 }
3993 if (block_cnt > 0xffff)
3994 return IO_ACCEL_INELIGIBLE;
3995
3996 cdb[0] = is_write ? WRITE_10 : READ_10;
3997 cdb[1] = 0;
3998 cdb[2] = (u8) (block >> 24);
3999 cdb[3] = (u8) (block >> 16);
4000 cdb[4] = (u8) (block >> 8);
4001 cdb[5] = (u8) (block);
4002 cdb[6] = 0;
4003 cdb[7] = (u8) (block_cnt >> 8);
4004 cdb[8] = (u8) (block_cnt);
4005 cdb[9] = 0;
4006 *cdb_len = 10;
4007 break;
4008 }
4009 return 0;
4010}
4011
c349775e 4012static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 4013 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4014 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 4015{
4016 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 4017 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
4018 unsigned int len;
4019 unsigned int total_len = 0;
4020 struct scatterlist *sg;
4021 u64 addr64;
4022 int use_sg, i;
4023 struct SGDescriptor *curr_sg;
4024 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
4025
283b4a9b 4026 /* TODO: implement chaining support */
03383736
DB		 4027 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
4028 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4029 return IO_ACCEL_INELIGIBLE;
03383736 4030 }
283b4a9b 4031
e1f7de0c
MG		 4032 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
4033
03383736
DB		 4034 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4035 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4036 return IO_ACCEL_INELIGIBLE;
03383736 4037 }
283b4a9b 4038
e1f7de0c
MG		 4039 c->cmd_type = CMD_IOACCEL1;
4040
4041 /* Adjust the DMA address to point to the accelerated command buffer */
4042 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
4043 (c->cmdindex * sizeof(*cp));
4044 BUG_ON(c->busaddr & 0x0000007F);
4045
4046 use_sg = scsi_dma_map(cmd);
03383736
DB		 4047 if (use_sg < 0) {
4048 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 4049 return use_sg;
03383736 4050 }
e1f7de0c
MG		 4051
4052 if (use_sg) {
4053 curr_sg = cp->SG;
4054 scsi_for_each_sg(cmd, sg, use_sg, i) {
4055 addr64 = (u64) sg_dma_address(sg);
4056 len = sg_dma_len(sg);
4057 total_len += len;
50a0decf
SC		 4058 curr_sg->Addr = cpu_to_le64(addr64);
4059 curr_sg->Len = cpu_to_le32(len);
4060 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 4061 curr_sg++;
4062 }
50a0decf 4063 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 4064
4065 switch (cmd->sc_data_direction) {
4066 case DMA_TO_DEVICE:
4067 control |= IOACCEL1_CONTROL_DATA_OUT;
4068 break;
4069 case DMA_FROM_DEVICE:
4070 control |= IOACCEL1_CONTROL_DATA_IN;
4071 break;
4072 case DMA_NONE:
4073 control |= IOACCEL1_CONTROL_NODATAXFER;
4074 break;
4075 default:
4076 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4077 cmd->sc_data_direction);
4078 BUG();
4079 break;
4080 }
4081 } else {
4082 control |= IOACCEL1_CONTROL_NODATAXFER;
4083 }
4084
c349775e 4085 c->Header.SGList = use_sg;
e1f7de0c 4086 /* Fill out the command structure to submit */
2b08b3e9
DB		 4087 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4088 cp->transfer_len = cpu_to_le32(total_len);
4089 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4090 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4091 cp->control = cpu_to_le32(control);
283b4a9b
SC		 4092 memcpy(cp->CDB, cdb, cdb_len);
4093 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 4094 /* Tag was already set at init time. */
283b4a9b 4095 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 4096 return 0;
4097}
edd16368 4098
283b4a9b
SC		 4099/*
4100 * Queue a command directly to a device behind the controller using the
4101 * I/O accelerator path.
4102 */
4103static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4104 struct CommandList *c)
4105{
4106 struct scsi_cmnd *cmd = c->scsi_cmd;
4107 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4108
03383736
DB		 4109 c->phys_disk = dev;
4110
283b4a9b 4111 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 4112 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 4113}
4114
dd0e19f3
ST		 4115/*
4116 * Set encryption parameters for the ioaccel2 request
4117 */
4118static void set_encrypt_ioaccel2(struct ctlr_info *h,
4119 struct CommandList *c, struct io_accel2_cmd *cp)
4120{
4121 struct scsi_cmnd *cmd = c->scsi_cmd;
4122 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4123 struct raid_map_data *map = &dev->raid_map;
4124 u64 first_block;
4125
dd0e19f3 4126 /* Are we doing encryption on this device */
2b08b3e9 4127 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 4128 return;
4129 /* Set the data encryption key index. */
4130 cp->dekindex = map->dekindex;
4131
4132 /* Set the encryption enable flag, encoded into direction field. */
4133 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4134
4135 /* Set encryption tweak values based on logical block address
4136 * If block size is 512, tweak value is LBA.
4137 * For other block sizes, tweak is (LBA * block size)/ 512)
4138 */
4139 switch (cmd->cmnd[0]) {
4140 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
4141 case WRITE_6:
4142 case READ_6:
2b08b3e9 4143 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 4144 break;
4145 case WRITE_10:
4146 case READ_10:
dd0e19f3
ST		 4147 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4148 case WRITE_12:
4149 case READ_12:
2b08b3e9 4150 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 4151 break;
4152 case WRITE_16:
4153 case READ_16:
2b08b3e9 4154 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 4155 break;
4156 default:
4157 dev_err(&h->pdev->dev,
2b08b3e9
DB		 4158 "ERROR: %s: size (0x%x) not supported for encryption\n",
4159 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 4160 BUG();
4161 break;
4162 }
2b08b3e9
DB		 4163
4164 if (le32_to_cpu(map->volume_blk_size) != 512)
4165 first_block = first_block *
4166 le32_to_cpu(map->volume_blk_size)/512;
4167
4168 cp->tweak_lower = cpu_to_le32(first_block);
4169 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 4170}
4171
c349775e
ST		 4172static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4173 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4174 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 4175{
4176 struct scsi_cmnd *cmd = c->scsi_cmd;
4177 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4178 struct ioaccel2_sg_element *curr_sg;
4179 int use_sg, i;
4180 struct scatterlist *sg;
4181 u64 addr64;
4182 u32 len;
4183 u32 total_len = 0;
4184
d9a729f3 4185 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 4186
03383736
DB		 4187 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4188 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4189 return IO_ACCEL_INELIGIBLE;
03383736
DB		 4190 }
4191
c349775e
ST		 4192 c->cmd_type = CMD_IOACCEL2;
4193 /* Adjust the DMA address to point to the accelerated command buffer */
4194 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4195 (c->cmdindex * sizeof(*cp));
4196 BUG_ON(c->busaddr & 0x0000007F);
4197
4198 memset(cp, 0, sizeof(*cp));
4199 cp->IU_type = IOACCEL2_IU_TYPE;
4200
4201 use_sg = scsi_dma_map(cmd);
03383736
DB		 4202 if (use_sg < 0) {
4203 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4204 return use_sg;
03383736 4205 }
c349775e
ST		 4206
4207 if (use_sg) {
c349775e 4208 curr_sg = cp->sg;
d9a729f3
WS		 4209 if (use_sg > h->ioaccel_maxsg) {
4210 addr64 = le64_to_cpu(
4211 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4212 curr_sg->address = cpu_to_le64(addr64);
4213 curr_sg->length = 0;
4214 curr_sg->reserved[0] = 0;
4215 curr_sg->reserved[1] = 0;
4216 curr_sg->reserved[2] = 0;
4217 curr_sg->chain_indicator = 0x80;
4218
4219 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4220 }
c349775e
ST		 4221 scsi_for_each_sg(cmd, sg, use_sg, i) {
4222 addr64 = (u64) sg_dma_address(sg);
4223 len = sg_dma_len(sg);
4224 total_len += len;
4225 curr_sg->address = cpu_to_le64(addr64);
4226 curr_sg->length = cpu_to_le32(len);
4227 curr_sg->reserved[0] = 0;
4228 curr_sg->reserved[1] = 0;
4229 curr_sg->reserved[2] = 0;
4230 curr_sg->chain_indicator = 0;
4231 curr_sg++;
4232 }
4233
4234 switch (cmd->sc_data_direction) {
4235 case DMA_TO_DEVICE:
dd0e19f3
ST		 4236 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4237 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 4238 break;
4239 case DMA_FROM_DEVICE:
dd0e19f3
ST		 4240 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4241 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 4242 break;
4243 case DMA_NONE:
dd0e19f3
ST		 4244 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4245 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 4246 break;
4247 default:
4248 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4249 cmd->sc_data_direction);
4250 BUG();
4251 break;
4252 }
4253 } else {
dd0e19f3
ST		 4254 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4255 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 4256 }
dd0e19f3
ST		 4257
4258 /* Set encryption parameters, if necessary */
4259 set_encrypt_ioaccel2(h, c, cp);
4260
2b08b3e9 4261 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 4262 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 4263 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 4264
c349775e
ST		 4265 cp->data_len = cpu_to_le32(total_len);
4266 cp->err_ptr = cpu_to_le64(c->busaddr +
4267 offsetof(struct io_accel2_cmd, error_data));
50a0decf 4268 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 4269
d9a729f3
WS		 4270 /* fill in sg elements */
4271 if (use_sg > h->ioaccel_maxsg) {
4272 cp->sg_count = 1;
4273 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4274 atomic_dec(&phys_disk->ioaccel_cmds_out);
4275 scsi_dma_unmap(cmd);
4276 return -1;
4277 }
4278 } else
4279 cp->sg_count = (u8) use_sg;
4280
c349775e
ST		 4281 enqueue_cmd_and_start_io(h, c);
4282 return 0;
4283}
4284
4285/*
4286 * Queue a command to the correct I/O accelerator path.
4287 */
4288static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4289 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4290 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 4291{
03383736
DB		 4292 /* Try to honor the device's queue depth */
4293 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4294 phys_disk->queue_depth) {
4295 atomic_dec(&phys_disk->ioaccel_cmds_out);
4296 return IO_ACCEL_INELIGIBLE;
4297 }
c349775e
ST		 4298 if (h->transMethod & CFGTBL_Trans_io_accel1)
4299 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4300 cdb, cdb_len, scsi3addr,
4301 phys_disk);
c349775e
ST		 4302 else
4303 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4304 cdb, cdb_len, scsi3addr,
4305 phys_disk);
c349775e
ST		 4306}
4307
6b80b18f
ST		 4308static void raid_map_helper(struct raid_map_data *map,
4309 int offload_to_mirror, u32 *map_index, u32 *current_group)
4310{
4311 if (offload_to_mirror == 0) {
4312 /* use physical disk in the first mirrored group. */
2b08b3e9 4313 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4314 return;
4315 }
4316 do {
4317 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4318 *current_group = *map_index /
4319 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4320 if (offload_to_mirror == *current_group)
4321 continue;
2b08b3e9 4322 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4323 /* select map index from next group */
2b08b3e9 4324 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4325 (*current_group)++;
4326 } else {
4327 /* select map index from first group */
2b08b3e9 4328 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4329 *current_group = 0;
4330 }
4331 } while (offload_to_mirror != *current_group);
4332}
4333
283b4a9b
SC		 4334/*
4335 * Attempt to perform offload RAID mapping for a logical volume I/O.
4336 */
4337static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4338 struct CommandList *c)
4339{
4340 struct scsi_cmnd *cmd = c->scsi_cmd;
4341 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4342 struct raid_map_data *map = &dev->raid_map;
4343 struct raid_map_disk_data *dd = &map->data[0];
4344 int is_write = 0;
4345 u32 map_index;
4346 u64 first_block, last_block;
4347 u32 block_cnt;
4348 u32 blocks_per_row;
4349 u64 first_row, last_row;
4350 u32 first_row_offset, last_row_offset;
4351 u32 first_column, last_column;
6b80b18f
ST		 4352 u64 r0_first_row, r0_last_row;
4353 u32 r5or6_blocks_per_row;
4354 u64 r5or6_first_row, r5or6_last_row;
4355 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4356 u32 r5or6_first_column, r5or6_last_column;
4357 u32 total_disks_per_row;
4358 u32 stripesize;
4359 u32 first_group, last_group, current_group;
283b4a9b
SC		 4360 u32 map_row;
4361 u32 disk_handle;
4362 u64 disk_block;
4363 u32 disk_block_cnt;
4364 u8 cdb[16];
4365 u8 cdb_len;
2b08b3e9 4366 u16 strip_size;
283b4a9b
SC		 4367#if BITS_PER_LONG == 32
4368 u64 tmpdiv;
4369#endif
6b80b18f 4370 int offload_to_mirror;
283b4a9b 4371
283b4a9b
SC		 4372 /* check for valid opcode, get LBA and block count */
4373 switch (cmd->cmnd[0]) {
4374 case WRITE_6:
4375 is_write = 1;
4376 case READ_6:
4377 first_block =
4378 (((u64) cmd->cmnd[2]) << 8) |
4379 cmd->cmnd[3];
4380 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4381 if (block_cnt == 0)
4382 block_cnt = 256;
283b4a9b
SC		 4383 break;
4384 case WRITE_10:
4385 is_write = 1;
4386 case READ_10:
4387 first_block =
4388 (((u64) cmd->cmnd[2]) << 24) |
4389 (((u64) cmd->cmnd[3]) << 16) |
4390 (((u64) cmd->cmnd[4]) << 8) |
4391 cmd->cmnd[5];
4392 block_cnt =
4393 (((u32) cmd->cmnd[7]) << 8) |
4394 cmd->cmnd[8];
4395 break;
4396 case WRITE_12:
4397 is_write = 1;
4398 case READ_12:
4399 first_block =
4400 (((u64) cmd->cmnd[2]) << 24) |
4401 (((u64) cmd->cmnd[3]) << 16) |
4402 (((u64) cmd->cmnd[4]) << 8) |
4403 cmd->cmnd[5];
4404 block_cnt =
4405 (((u32) cmd->cmnd[6]) << 24) |
4406 (((u32) cmd->cmnd[7]) << 16) |
4407 (((u32) cmd->cmnd[8]) << 8) |
4408 cmd->cmnd[9];
4409 break;
4410 case WRITE_16:
4411 is_write = 1;
4412 case READ_16:
4413 first_block =
4414 (((u64) cmd->cmnd[2]) << 56) |
4415 (((u64) cmd->cmnd[3]) << 48) |
4416 (((u64) cmd->cmnd[4]) << 40) |
4417 (((u64) cmd->cmnd[5]) << 32) |
4418 (((u64) cmd->cmnd[6]) << 24) |
4419 (((u64) cmd->cmnd[7]) << 16) |
4420 (((u64) cmd->cmnd[8]) << 8) |
4421 cmd->cmnd[9];
4422 block_cnt =
4423 (((u32) cmd->cmnd[10]) << 24) |
4424 (((u32) cmd->cmnd[11]) << 16) |
4425 (((u32) cmd->cmnd[12]) << 8) |
4426 cmd->cmnd[13];
4427 break;
4428 default:
4429 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4430 }
283b4a9b
SC		 4431 last_block = first_block + block_cnt - 1;
4432
4433 /* check for write to non-RAID-0 */
4434 if (is_write && dev->raid_level != 0)
4435 return IO_ACCEL_INELIGIBLE;
4436
4437 /* check for invalid block or wraparound */
2b08b3e9
DB		 4438 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4439 last_block < first_block)
283b4a9b
SC		 4440 return IO_ACCEL_INELIGIBLE;
4441
4442 /* calculate stripe information for the request */
2b08b3e9
DB		 4443 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4444 le16_to_cpu(map->strip_size);
4445 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4446#if BITS_PER_LONG == 32
4447 tmpdiv = first_block;
4448 (void) do_div(tmpdiv, blocks_per_row);
4449 first_row = tmpdiv;
4450 tmpdiv = last_block;
4451 (void) do_div(tmpdiv, blocks_per_row);
4452 last_row = tmpdiv;
4453 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4454 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4455 tmpdiv = first_row_offset;
2b08b3e9 4456 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4457 first_column = tmpdiv;
4458 tmpdiv = last_row_offset;
2b08b3e9 4459 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4460 last_column = tmpdiv;
4461#else
4462 first_row = first_block / blocks_per_row;
4463 last_row = last_block / blocks_per_row;
4464 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4465 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4466 first_column = first_row_offset / strip_size;
4467 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4468#endif
4469
4470 /* if this isn't a single row/column then give to the controller */
4471 if ((first_row != last_row) || (first_column != last_column))
4472 return IO_ACCEL_INELIGIBLE;
4473
4474 /* proceeding with driver mapping */
2b08b3e9
DB		 4475 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4476 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4477 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4478 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4479 map_index = (map_row * total_disks_per_row) + first_column;
4480
4481 switch (dev->raid_level) {
4482 case HPSA_RAID_0:
4483 break; /* nothing special to do */
4484 case HPSA_RAID_1:
4485 /* Handles load balance across RAID 1 members.
4486 * (2-drive R1 and R10 with even # of drives.)
4487 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4488 */
2b08b3e9 4489 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4490 if (dev->offload_to_mirror)
2b08b3e9 4491 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4492 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4493 break;
4494 case HPSA_RAID_ADM:
4495 /* Handles N-way mirrors (R1-ADM)
4496 * and R10 with # of drives divisible by 3.)
4497 */
2b08b3e9 4498 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4499
4500 offload_to_mirror = dev->offload_to_mirror;
4501 raid_map_helper(map, offload_to_mirror,
4502 &map_index, &current_group);
4503 /* set mirror group to use next time */
4504 offload_to_mirror =
2b08b3e9
DB		 4505 (offload_to_mirror >=
4506 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4507 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4508 dev->offload_to_mirror = offload_to_mirror;
4509 /* Avoid direct use of dev->offload_to_mirror within this
4510 * function since multiple threads might simultaneously
4511 * increment it beyond the range of dev->layout_map_count -1.
4512 */
4513 break;
4514 case HPSA_RAID_5:
4515 case HPSA_RAID_6:
2b08b3e9 4516 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4517 break;
4518
4519 /* Verify first and last block are in same RAID group */
4520 r5or6_blocks_per_row =
2b08b3e9
DB		 4521 le16_to_cpu(map->strip_size) *
4522 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4523 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4524 stripesize = r5or6_blocks_per_row *
4525 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4526#if BITS_PER_LONG == 32
4527 tmpdiv = first_block;
4528 first_group = do_div(tmpdiv, stripesize);
4529 tmpdiv = first_group;
4530 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4531 first_group = tmpdiv;
4532 tmpdiv = last_block;
4533 last_group = do_div(tmpdiv, stripesize);
4534 tmpdiv = last_group;
4535 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4536 last_group = tmpdiv;
4537#else
4538 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4539 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4540#endif
000ff7c2 4541 if (first_group != last_group)
6b80b18f
ST		 4542 return IO_ACCEL_INELIGIBLE;
4543
4544 /* Verify request is in a single row of RAID 5/6 */
4545#if BITS_PER_LONG == 32
4546 tmpdiv = first_block;
4547 (void) do_div(tmpdiv, stripesize);
4548 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4549 tmpdiv = last_block;
4550 (void) do_div(tmpdiv, stripesize);
4551 r5or6_last_row = r0_last_row = tmpdiv;
4552#else
4553 first_row = r5or6_first_row = r0_first_row =
4554 first_block / stripesize;
4555 r5or6_last_row = r0_last_row = last_block / stripesize;
4556#endif
4557 if (r5or6_first_row != r5or6_last_row)
4558 return IO_ACCEL_INELIGIBLE;
4559
4560
4561 /* Verify request is in a single column */
4562#if BITS_PER_LONG == 32
4563 tmpdiv = first_block;
4564 first_row_offset = do_div(tmpdiv, stripesize);
4565 tmpdiv = first_row_offset;
4566 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4567 r5or6_first_row_offset = first_row_offset;
4568 tmpdiv = last_block;
4569 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4570 tmpdiv = r5or6_last_row_offset;
4571 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4572 tmpdiv = r5or6_first_row_offset;
4573 (void) do_div(tmpdiv, map->strip_size);
4574 first_column = r5or6_first_column = tmpdiv;
4575 tmpdiv = r5or6_last_row_offset;
4576 (void) do_div(tmpdiv, map->strip_size);
4577 r5or6_last_column = tmpdiv;
4578#else
4579 first_row_offset = r5or6_first_row_offset =
4580 (u32)((first_block % stripesize) %
4581 r5or6_blocks_per_row);
4582
4583 r5or6_last_row_offset =
4584 (u32)((last_block % stripesize) %
4585 r5or6_blocks_per_row);
4586
4587 first_column = r5or6_first_column =
2b08b3e9 4588 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4589 r5or6_last_column =
2b08b3e9 4590 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4591#endif
4592 if (r5or6_first_column != r5or6_last_column)
4593 return IO_ACCEL_INELIGIBLE;
4594
4595 /* Request is eligible */
4596 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4597 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4598
4599 map_index = (first_group *
2b08b3e9 4600 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4601 (map_row * total_disks_per_row) + first_column;
4602 break;
4603 default:
4604 return IO_ACCEL_INELIGIBLE;
283b4a9b 4605 }
6b80b18f 4606
07543e0c
SC		 4607 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4608 return IO_ACCEL_INELIGIBLE;
4609
03383736
DB		 4610 c->phys_disk = dev->phys_disk[map_index];
4611
283b4a9b 4612 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 4613 disk_block = le64_to_cpu(map->disk_starting_blk) +
4614 first_row * le16_to_cpu(map->strip_size) +
4615 (first_row_offset - first_column *
4616 le16_to_cpu(map->strip_size));
283b4a9b
SC		 4617 disk_block_cnt = block_cnt;
4618
4619 /* handle differing logical/physical block sizes */
4620 if (map->phys_blk_shift) {
4621 disk_block <<= map->phys_blk_shift;
4622 disk_block_cnt <<= map->phys_blk_shift;
4623 }
4624 BUG_ON(disk_block_cnt > 0xffff);
4625
4626 /* build the new CDB for the physical disk I/O */
4627 if (disk_block > 0xffffffff) {
4628 cdb[0] = is_write ? WRITE_16 : READ_16;
4629 cdb[1] = 0;
4630 cdb[2] = (u8) (disk_block >> 56);
4631 cdb[3] = (u8) (disk_block >> 48);
4632 cdb[4] = (u8) (disk_block >> 40);
4633 cdb[5] = (u8) (disk_block >> 32);
4634 cdb[6] = (u8) (disk_block >> 24);
4635 cdb[7] = (u8) (disk_block >> 16);
4636 cdb[8] = (u8) (disk_block >> 8);
4637 cdb[9] = (u8) (disk_block);
4638 cdb[10] = (u8) (disk_block_cnt >> 24);
4639 cdb[11] = (u8) (disk_block_cnt >> 16);
4640 cdb[12] = (u8) (disk_block_cnt >> 8);
4641 cdb[13] = (u8) (disk_block_cnt);
4642 cdb[14] = 0;
4643 cdb[15] = 0;
4644 cdb_len = 16;
4645 } else {
4646 cdb[0] = is_write ? WRITE_10 : READ_10;
4647 cdb[1] = 0;
4648 cdb[2] = (u8) (disk_block >> 24);
4649 cdb[3] = (u8) (disk_block >> 16);
4650 cdb[4] = (u8) (disk_block >> 8);
4651 cdb[5] = (u8) (disk_block);
4652 cdb[6] = 0;
4653 cdb[7] = (u8) (disk_block_cnt >> 8);
4654 cdb[8] = (u8) (disk_block_cnt);
4655 cdb[9] = 0;
4656 cdb_len = 10;
4657 }
4658 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 4659 dev->scsi3addr,
4660 dev->phys_disk[map_index]);
283b4a9b
SC		 4661}
4662
25163bd5
WS		 4663/*
4664 * Submit commands down the "normal" RAID stack path
4665 * All callers to hpsa_ciss_submit must check lockup_detected
4666 * beforehand, before (opt.) and after calling cmd_alloc
4667 */
574f05d3
SC		 4668static int hpsa_ciss_submit(struct ctlr_info *h,
4669 struct CommandList *c, struct scsi_cmnd *cmd,
4670 unsigned char scsi3addr[])
edd16368 4671{
edd16368 4672 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 4673 c->cmd_type = CMD_SCSI;
4674 c->scsi_cmd = cmd;
4675 c->Header.ReplyQueue = 0; /* unused in simple mode */
4676 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 4677 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 4678
4679 /* Fill in the request block... */
4680
4681 c->Request.Timeout = 0;
edd16368
SC		 4682 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4683 c->Request.CDBLen = cmd->cmd_len;
4684 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 4685 switch (cmd->sc_data_direction) {
4686 case DMA_TO_DEVICE:
a505b86f
SC		 4687 c->Request.type_attr_dir =
4688 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 4689 break;
4690 case DMA_FROM_DEVICE:
a505b86f
SC		 4691 c->Request.type_attr_dir =
4692 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 4693 break;
4694 case DMA_NONE:
a505b86f
SC		 4695 c->Request.type_attr_dir =
4696 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 4697 break;
4698 case DMA_BIDIRECTIONAL:
4699 /* This can happen if a buggy application does a scsi passthru
4700 * and sets both inlen and outlen to non-zero. ( see
4701 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4702 */
4703
a505b86f
SC		 4704 c->Request.type_attr_dir =
4705 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 4706 /* This is technically wrong, and hpsa controllers should
4707 * reject it with CMD_INVALID, which is the most correct
4708 * response, but non-fibre backends appear to let it
4709 * slide by, and give the same results as if this field
4710 * were set correctly. Either way is acceptable for
4711 * our purposes here.
4712 */
4713
4714 break;
4715
4716 default:
4717 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4718 cmd->sc_data_direction);
4719 BUG();
4720 break;
4721 }
4722
33a2ffce 4723 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
73153fe5 4724 hpsa_cmd_resolve_and_free(h, c);
edd16368
SC		 4725 return SCSI_MLQUEUE_HOST_BUSY;
4726 }
4727 enqueue_cmd_and_start_io(h, c);
4728 /* the cmd'll come back via intr handler in complete_scsi_command() */
4729 return 0;
4730}
4731
360c73bd
SC		 4732static void hpsa_cmd_init(struct ctlr_info *h, int index,
4733 struct CommandList *c)
4734{
4735 dma_addr_t cmd_dma_handle, err_dma_handle;
4736
4737 /* Zero out all of commandlist except the last field, refcount */
4738 memset(c, 0, offsetof(struct CommandList, refcount));
4739 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
4740 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4741 c->err_info = h->errinfo_pool + index;
4742 memset(c->err_info, 0, sizeof(*c->err_info));
4743 err_dma_handle = h->errinfo_pool_dhandle
4744 + index * sizeof(*c->err_info);
4745 c->cmdindex = index;
4746 c->busaddr = (u32) cmd_dma_handle;
4747 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4748 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
4749 c->h = h;
a58e7e53 4750 c->scsi_cmd = SCSI_CMD_IDLE;
360c73bd
SC		 4751}
4752
4753static void hpsa_preinitialize_commands(struct ctlr_info *h)
4754{
4755 int i;
4756
4757 for (i = 0; i < h->nr_cmds; i++) {
4758 struct CommandList *c = h->cmd_pool + i;
4759
4760 hpsa_cmd_init(h, i, c);
4761 atomic_set(&c->refcount, 0);
4762 }
4763}
4764
4765static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
4766 struct CommandList *c)
4767{
4768 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4769
73153fe5
WS		 4770 BUG_ON(c->cmdindex != index);
4771
360c73bd
SC		 4772 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4773 memset(c->err_info, 0, sizeof(*c->err_info));
4774 c->busaddr = (u32) cmd_dma_handle;
4775}
4776
592a0ad5
WS		 4777static int hpsa_ioaccel_submit(struct ctlr_info *h,
4778 struct CommandList *c, struct scsi_cmnd *cmd,
4779 unsigned char *scsi3addr)
4780{
4781 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4782 int rc = IO_ACCEL_INELIGIBLE;
4783
4784 cmd->host_scribble = (unsigned char *) c;
4785
4786 if (dev->offload_enabled) {
4787 hpsa_cmd_init(h, c->cmdindex, c);
4788 c->cmd_type = CMD_SCSI;
4789 c->scsi_cmd = cmd;
4790 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4791 if (rc < 0) /* scsi_dma_map failed. */
4792 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 4793 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 4794 hpsa_cmd_init(h, c->cmdindex, c);
4795 c->cmd_type = CMD_SCSI;
4796 c->scsi_cmd = cmd;
4797 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4798 if (rc < 0) /* scsi_dma_map failed. */
4799 rc = SCSI_MLQUEUE_HOST_BUSY;
4800 }
4801 return rc;
4802}
4803
080ef1cc
DB		 4804static void hpsa_command_resubmit_worker(struct work_struct *work)
4805{
4806 struct scsi_cmnd *cmd;
4807 struct hpsa_scsi_dev_t *dev;
8a0ff92c 4808 struct CommandList *c = container_of(work, struct CommandList, work);
080ef1cc
DB		 4809
4810 cmd = c->scsi_cmd;
4811 dev = cmd->device->hostdata;
4812 if (!dev) {
4813 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 4814 return hpsa_cmd_free_and_done(c->h, c, cmd);
080ef1cc 4815 }
d604f533
WS		 4816 if (c->reset_pending)
4817 return hpsa_cmd_resolve_and_free(c->h, c);
a58e7e53
WS		 4818 if (c->abort_pending)
4819 return hpsa_cmd_abort_and_free(c->h, c, cmd);
592a0ad5
WS		 4820 if (c->cmd_type == CMD_IOACCEL2) {
4821 struct ctlr_info *h = c->h;
4822 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
4823 int rc;
4824
4825 if (c2->error_data.serv_response ==
4826 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
4827 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
4828 if (rc == 0)
4829 return;
4830 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4831 /*
4832 * If we get here, it means dma mapping failed.
4833 * Try again via scsi mid layer, which will
4834 * then get SCSI_MLQUEUE_HOST_BUSY.
4835 */
4836 cmd->result = DID_IMM_RETRY << 16;
8a0ff92c 4837 return hpsa_cmd_free_and_done(h, c, cmd);
592a0ad5
WS		 4838 }
4839 /* else, fall thru and resubmit down CISS path */
4840 }
4841 }
360c73bd 4842 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 4843 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4844 /*
4845 * If we get here, it means dma mapping failed. Try
4846 * again via scsi mid layer, which will then get
4847 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 4848 *
4849 * hpsa_ciss_submit will have already freed c
4850 * if it encountered a dma mapping failure.
080ef1cc
DB		 4851 */
4852 cmd->result = DID_IMM_RETRY << 16;
4853 cmd->scsi_done(cmd);
4854 }
4855}
4856
574f05d3
SC		 4857/* Running in struct Scsi_Host->host_lock less mode */
4858static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4859{
4860 struct ctlr_info *h;
4861 struct hpsa_scsi_dev_t *dev;
4862 unsigned char scsi3addr[8];
4863 struct CommandList *c;
4864 int rc = 0;
4865
4866 /* Get the ptr to our adapter structure out of cmd->host. */
4867 h = sdev_to_hba(cmd->device);
73153fe5
WS		 4868
4869 BUG_ON(cmd->request->tag < 0);
4870
574f05d3
SC		 4871 dev = cmd->device->hostdata;
4872 if (!dev) {
4873 cmd->result = DID_NO_CONNECT << 16;
4874 cmd->scsi_done(cmd);
4875 return 0;
4876 }
574f05d3 4877
73153fe5 4878 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
bf43caf3 4879
407863cb 4880 if (unlikely(lockup_detected(h))) {
25163bd5 4881 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 4882 cmd->scsi_done(cmd);
4883 return 0;
4884 }
73153fe5 4885 c = cmd_tagged_alloc(h, cmd);
574f05d3 4886
407863cb
SC		 4887 /*
4888 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 4889 * Retries always go down the normal I/O path.
4890 */
4891 if (likely(cmd->retries == 0 &&
4892 cmd->request->cmd_type == REQ_TYPE_FS &&
4893 h->acciopath_status)) {
592a0ad5
WS		 4894 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
4895 if (rc == 0)
4896 return 0;
4897 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
73153fe5 4898 hpsa_cmd_resolve_and_free(h, c);
592a0ad5 4899 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 4900 }
4901 }
4902 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4903}
4904
8ebc9248 4905static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 4906{
4907 unsigned long flags;
4908
8ebc9248
WS		 4909 spin_lock_irqsave(&h->scan_lock, flags);
4910 h->scan_finished = 1;
4911 wake_up_all(&h->scan_wait_queue);
4912 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 4913}
4914
a08a8471
SC		 4915static void hpsa_scan_start(struct Scsi_Host *sh)
4916{
4917 struct ctlr_info *h = shost_to_hba(sh);
4918 unsigned long flags;
4919
8ebc9248
WS		 4920 /*
4921 * Don't let rescans be initiated on a controller known to be locked
4922 * up. If the controller locks up *during* a rescan, that thread is
4923 * probably hosed, but at least we can prevent new rescan threads from
4924 * piling up on a locked up controller.
4925 */
4926 if (unlikely(lockup_detected(h)))
4927 return hpsa_scan_complete(h);
5f389360 4928
a08a8471
SC		 4929 /* wait until any scan already in progress is finished. */
4930 while (1) {
4931 spin_lock_irqsave(&h->scan_lock, flags);
4932 if (h->scan_finished)
4933 break;
4934 spin_unlock_irqrestore(&h->scan_lock, flags);
4935 wait_event(h->scan_wait_queue, h->scan_finished);
4936 /* Note: We don't need to worry about a race between this
4937 * thread and driver unload because the midlayer will
4938 * have incremented the reference count, so unload won't
4939 * happen if we're in here.
4940 */
4941 }
4942 h->scan_finished = 0; /* mark scan as in progress */
4943 spin_unlock_irqrestore(&h->scan_lock, flags);
4944
8ebc9248
WS		 4945 if (unlikely(lockup_detected(h)))
4946 return hpsa_scan_complete(h);
5f389360 4947
a08a8471
SC		 4948 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4949
8ebc9248 4950 hpsa_scan_complete(h);
a08a8471
SC		 4951}
4952
7c0a0229
DB		 4953static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4954{
03383736
DB		 4955 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
4956
4957 if (!logical_drive)
4958 return -ENODEV;
7c0a0229
DB		 4959
4960 if (qdepth < 1)
4961 qdepth = 1;
03383736
DB		 4962 else if (qdepth > logical_drive->queue_depth)
4963 qdepth = logical_drive->queue_depth;
4964
4965 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 4966}
4967
a08a8471
SC		 4968static int hpsa_scan_finished(struct Scsi_Host *sh,
4969 unsigned long elapsed_time)
4970{
4971 struct ctlr_info *h = shost_to_hba(sh);
4972 unsigned long flags;
4973 int finished;
4974
4975 spin_lock_irqsave(&h->scan_lock, flags);
4976 finished = h->scan_finished;
4977 spin_unlock_irqrestore(&h->scan_lock, flags);
4978 return finished;
4979}
4980
2946e82b 4981static int hpsa_scsi_host_alloc(struct ctlr_info *h)
edd16368 4982{
b705690d
SC		 4983 struct Scsi_Host *sh;
4984 int error;
edd16368 4985
b705690d 4986 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2946e82b
RE		 4987 if (sh == NULL) {
4988 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
4989 return -ENOMEM;
4990 }
b705690d
SC		 4991
4992 sh->io_port = 0;
4993 sh->n_io_port = 0;
4994 sh->this_id = -1;
4995 sh->max_channel = 3;
4996 sh->max_cmd_len = MAX_COMMAND_SIZE;
4997 sh->max_lun = HPSA_MAX_LUN;
4998 sh->max_id = HPSA_MAX_LUN;
41ce4c35 4999 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 5000 sh->cmd_per_lun = sh->can_queue;
b705690d 5001 sh->sg_tablesize = h->maxsgentries;
b705690d
SC		 5002 sh->hostdata[0] = (unsigned long) h;
5003 sh->irq = h->intr[h->intr_mode];
5004 sh->unique_id = sh->irq;
73153fe5
WS		 5005 error = scsi_init_shared_tag_map(sh, sh->can_queue);
5006 if (error) {
5007 dev_err(&h->pdev->dev,
5008 "%s: scsi_init_shared_tag_map failed for controller %d\n",
5009 __func__, h->ctlr);
2946e82b
RE		 5010 scsi_host_put(sh);
5011 return error;
73153fe5 5012 }
2946e82b 5013 h->scsi_host = sh;
b705690d 5014 return 0;
2946e82b 5015}
b705690d 5016
2946e82b
RE		 5017static int hpsa_scsi_add_host(struct ctlr_info *h)
5018{
5019 int rv;
5020
5021 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
5022 if (rv) {
5023 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
5024 return rv;
5025 }
5026 scsi_scan_host(h->scsi_host);
5027 return 0;
edd16368
SC		 5028}
5029
73153fe5
WS		 5030/*
5031 * The block layer has already gone to the trouble of picking out a unique,
5032 * small-integer tag for this request. We use an offset from that value as
5033 * an index to select our command block. (The offset allows us to reserve the
5034 * low-numbered entries for our own uses.)
5035 */
5036static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
5037{
5038 int idx = scmd->request->tag;
5039
5040 if (idx < 0)
5041 return idx;
5042
5043 /* Offset to leave space for internal cmds. */
5044 return idx += HPSA_NRESERVED_CMDS;
5045}
5046
b69324ff
WS		 5047/*
5048 * Send a TEST_UNIT_READY command to the specified LUN using the specified
5049 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5050 */
5051static int hpsa_send_test_unit_ready(struct ctlr_info *h,
5052 struct CommandList *c, unsigned char lunaddr[],
5053 int reply_queue)
5054{
5055 int rc;
5056
5057 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
5058 (void) fill_cmd(c, TEST_UNIT_READY, h,
5059 NULL, 0, 0, lunaddr, TYPE_CMD);
5060 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5061 if (rc)
5062 return rc;
5063 /* no unmap needed here because no data xfer. */
5064
5065 /* Check if the unit is already ready. */
5066 if (c->err_info->CommandStatus == CMD_SUCCESS)
5067 return 0;
5068
5069 /*
5070 * The first command sent after reset will receive "unit attention" to
5071 * indicate that the LUN has been reset...this is actually what we're
5072 * looking for (but, success is good too).
5073 */
5074 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5075 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5076 (c->err_info->SenseInfo[2] == NO_SENSE ||
5077 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5078 return 0;
5079
5080 return 1;
5081}
5082
5083/*
5084 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5085 * returns zero when the unit is ready, and non-zero when giving up.
5086 */
5087static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5088 struct CommandList *c,
5089 unsigned char lunaddr[], int reply_queue)
edd16368 5090{
8919358e 5091 int rc;
edd16368
SC		 5092 int count = 0;
5093 int waittime = 1; /* seconds */
edd16368
SC		 5094
5095 /* Send test unit ready until device ready, or give up. */
b69324ff 5096 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
edd16368 5097
b69324ff
WS		 5098 /*
5099 * Wait for a bit. do this first, because if we send
edd16368
SC		 5100 * the TUR right away, the reset will just abort it.
5101 */
5102 msleep(1000 * waittime);
b69324ff
WS		 5103
5104 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5105 if (!rc)
5106 break;
edd16368
SC		 5107
5108 /* Increase wait time with each try, up to a point. */
5109 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
b69324ff 5110 waittime *= 2;
edd16368 5111
b69324ff
WS		 5112 dev_warn(&h->pdev->dev,
5113 "waiting %d secs for device to become ready.\n",
5114 waittime);
5115 }
edd16368 5116
b69324ff
WS		 5117 return rc;
5118}
edd16368 5119
b69324ff
WS		 5120static int wait_for_device_to_become_ready(struct ctlr_info *h,
5121 unsigned char lunaddr[],
5122 int reply_queue)
5123{
5124 int first_queue;
5125 int last_queue;
5126 int rq;
5127 int rc = 0;
5128 struct CommandList *c;
5129
5130 c = cmd_alloc(h);
5131
5132 /*
5133 * If no specific reply queue was requested, then send the TUR
5134 * repeatedly, requesting a reply on each reply queue; otherwise execute
5135 * the loop exactly once using only the specified queue.
5136 */
5137 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5138 first_queue = 0;
5139 last_queue = h->nreply_queues - 1;
5140 } else {
5141 first_queue = reply_queue;
5142 last_queue = reply_queue;
5143 }
5144
5145 for (rq = first_queue; rq <= last_queue; rq++) {
5146 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5147 if (rc)
edd16368 5148 break;
edd16368
SC		 5149 }
5150
5151 if (rc)
5152 dev_warn(&h->pdev->dev, "giving up on device.\n");
5153 else
5154 dev_warn(&h->pdev->dev, "device is ready.\n");
5155
45fcb86e 5156 cmd_free(h, c);
edd16368
SC		 5157 return rc;
5158}
5159
5160/* Need at least one of these error handlers to keep ../scsi/hosts.c from
5161 * complaining. Doing a host- or bus-reset can't do anything good here.
5162 */
5163static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5164{
5165 int rc;
5166 struct ctlr_info *h;
5167 struct hpsa_scsi_dev_t *dev;
2dc127bb 5168 char msg[48];
edd16368
SC		 5169
5170 /* find the controller to which the command to be aborted was sent */
5171 h = sdev_to_hba(scsicmd->device);
5172 if (h == NULL) /* paranoia */
5173 return FAILED;
e345893b
DB		 5174
5175 if (lockup_detected(h))
5176 return FAILED;
5177
edd16368
SC		 5178 dev = scsicmd->device->hostdata;
5179 if (!dev) {
d604f533 5180 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
edd16368
SC		 5181 return FAILED;
5182 }
25163bd5
WS		 5183
5184 /* if controller locked up, we can guarantee command won't complete */
5185 if (lockup_detected(h)) {
2dc127bb
DC		 5186 snprintf(msg, sizeof(msg),
5187 "cmd %d RESET FAILED, lockup detected",
5188 hpsa_get_cmd_index(scsicmd));
73153fe5 5189 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5190 return FAILED;
5191 }
5192
5193 /* this reset request might be the result of a lockup; check */
5194 if (detect_controller_lockup(h)) {
2dc127bb
DC		 5195 snprintf(msg, sizeof(msg),
5196 "cmd %d RESET FAILED, new lockup detected",
5197 hpsa_get_cmd_index(scsicmd));
73153fe5 5198 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5199 return FAILED;
5200 }
5201
d604f533
WS		 5202 /* Do not attempt on controller */
5203 if (is_hba_lunid(dev->scsi3addr))
5204 return SUCCESS;
5205
25163bd5
WS		 5206 hpsa_show_dev_msg(KERN_WARNING, h, dev, "resetting");
5207
edd16368 5208 /* send a reset to the SCSI LUN which the command was sent to */
d604f533
WS		 5209 rc = hpsa_do_reset(h, dev, dev->scsi3addr, HPSA_RESET_TYPE_LUN,
5210 DEFAULT_REPLY_QUEUE);
2dc127bb
DC		 5211 snprintf(msg, sizeof(msg), "reset %s",
5212 rc == 0 ? "completed successfully" : "failed");
d604f533
WS		 5213 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
5214 return rc == 0 ? SUCCESS : FAILED;
edd16368
SC		 5215}
5216
6cba3f19
SC		 5217static void swizzle_abort_tag(u8 *tag)
5218{
5219 u8 original_tag[8];
5220
5221 memcpy(original_tag, tag, 8);
5222 tag[0] = original_tag[3];
5223 tag[1] = original_tag[2];
5224 tag[2] = original_tag[1];
5225 tag[3] = original_tag[0];
5226 tag[4] = original_tag[7];
5227 tag[5] = original_tag[6];
5228 tag[6] = original_tag[5];
5229 tag[7] = original_tag[4];
5230}
5231
17eb87d2 5232static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 5233 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 5234{
2b08b3e9 5235 u64 tag;
17eb87d2
ST		 5236 if (c->cmd_type == CMD_IOACCEL1) {
5237 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5238 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 5239 tag = le64_to_cpu(cm1->tag);
5240 *tagupper = cpu_to_le32(tag >> 32);
5241 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 5242 return;
5243 }
5244 if (c->cmd_type == CMD_IOACCEL2) {
5245 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5246 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 5247 /* upper tag not used in ioaccel2 mode */
5248 memset(tagupper, 0, sizeof(*tagupper));
5249 *taglower = cm2->Tag;
54b6e9e9 5250 return;
17eb87d2 5251 }
2b08b3e9
DB		 5252 tag = le64_to_cpu(c->Header.tag);
5253 *tagupper = cpu_to_le32(tag >> 32);
5254 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 5255}
5256
75167d2c 5257static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 5258 struct CommandList *abort, int reply_queue)
75167d2c
SC		 5259{
5260 int rc = IO_OK;
5261 struct CommandList *c;
5262 struct ErrorInfo *ei;
2b08b3e9 5263 __le32 tagupper, taglower;
75167d2c 5264
45fcb86e 5265 c = cmd_alloc(h);
75167d2c 5266
a2dac136 5267 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 5268 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 5269 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 5270 if (h->needs_abort_tags_swizzled)
6cba3f19 5271 swizzle_abort_tag(&c->Request.CDB[4]);
25163bd5 5272 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
17eb87d2 5273 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5274 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 5275 __func__, tagupper, taglower);
75167d2c
SC		 5276 /* no unmap needed here because no data xfer. */
5277
5278 ei = c->err_info;
5279 switch (ei->CommandStatus) {
5280 case CMD_SUCCESS:
5281 break;
9437ac43
SC		 5282 case CMD_TMF_STATUS:
5283 rc = hpsa_evaluate_tmf_status(h, c);
5284 break;
75167d2c
SC		 5285 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5286 rc = -1;
5287 break;
5288 default:
5289 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 5290 __func__, tagupper, taglower);
d1e8beac 5291 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 5292 rc = -1;
5293 break;
5294 }
45fcb86e 5295 cmd_free(h, c);
dd0e19f3
ST		 5296 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5297 __func__, tagupper, taglower);
75167d2c
SC		 5298 return rc;
5299}
5300
8be986cc
SC		 5301static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5302 struct CommandList *command_to_abort, int reply_queue)
5303{
5304 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5305 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5306 struct io_accel2_cmd *c2a =
5307 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
a58e7e53 5308 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
8be986cc
SC		 5309 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5310
5311 /*
5312 * We're overlaying struct hpsa_tmf_struct on top of something which
5313 * was allocated as a struct io_accel2_cmd, so we better be sure it
5314 * actually fits, and doesn't overrun the error info space.
5315 */
5316 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5317 sizeof(struct io_accel2_cmd));
5318 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5319 offsetof(struct hpsa_tmf_struct, error_len) +
5320 sizeof(ac->error_len));
5321
5322 c->cmd_type = IOACCEL2_TMF;
a58e7e53
WS		 5323 c->scsi_cmd = SCSI_CMD_BUSY;
5324
8be986cc
SC		 5325 /* Adjust the DMA address to point to the accelerated command buffer */
5326 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5327 (c->cmdindex * sizeof(struct io_accel2_cmd));
5328 BUG_ON(c->busaddr & 0x0000007F);
5329
5330 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5331 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5332 ac->reply_queue = reply_queue;
5333 ac->tmf = IOACCEL2_TMF_ABORT;
5334 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5335 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5336 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5337 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5338 ac->error_ptr = cpu_to_le64(c->busaddr +
5339 offsetof(struct io_accel2_cmd, error_data));
5340 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5341}
5342
54b6e9e9
ST		 5343/* ioaccel2 path firmware cannot handle abort task requests.
5344 * Change abort requests to physical target reset, and send to the
5345 * address of the physical disk used for the ioaccel 2 command.
5346 * Return 0 on success (IO_OK)
5347 * -1 on failure
5348 */
5349
5350static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 5351 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 5352{
5353 int rc = IO_OK;
5354 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5355 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5356 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5357 unsigned char *psa = &phys_scsi3addr[0];
5358
5359 /* Get a pointer to the hpsa logical device. */
7fa3030c 5360 scmd = abort->scsi_cmd;
54b6e9e9
ST		 5361 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5362 if (dev == NULL) {
5363 dev_warn(&h->pdev->dev,
5364 "Cannot abort: no device pointer for command.\n");
5365 return -1; /* not abortable */
5366 }
5367
2ba8bfc8
SC		 5368 if (h->raid_offload_debug > 0)
5369 dev_info(&h->pdev->dev,
0d96ef5f 5370 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 5371 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 5372 "Reset as abort",
2ba8bfc8
SC		 5373 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5374 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5375
54b6e9e9
ST		 5376 if (!dev->offload_enabled) {
5377 dev_warn(&h->pdev->dev,
5378 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5379 return -1; /* not abortable */
5380 }
5381
5382 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5383 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5384 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5385 return -1; /* not abortable */
5386 }
5387
5388 /* send the reset */
2ba8bfc8
SC		 5389 if (h->raid_offload_debug > 0)
5390 dev_info(&h->pdev->dev,
5391 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5392 psa[0], psa[1], psa[2], psa[3],
5393 psa[4], psa[5], psa[6], psa[7]);
d604f533 5394 rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 5395 if (rc != 0) {
5396 dev_warn(&h->pdev->dev,
5397 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5398 psa[0], psa[1], psa[2], psa[3],
5399 psa[4], psa[5], psa[6], psa[7]);
5400 return rc; /* failed to reset */
5401 }
5402
5403 /* wait for device to recover */
b69324ff 5404 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
54b6e9e9
ST		 5405 dev_warn(&h->pdev->dev,
5406 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5407 psa[0], psa[1], psa[2], psa[3],
5408 psa[4], psa[5], psa[6], psa[7]);
5409 return -1; /* failed to recover */
5410 }
5411
5412 /* device recovered */
5413 dev_info(&h->pdev->dev,
5414 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5415 psa[0], psa[1], psa[2], psa[3],
5416 psa[4], psa[5], psa[6], psa[7]);
5417
5418 return rc; /* success */
5419}
5420
8be986cc
SC		 5421static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
5422 struct CommandList *abort, int reply_queue)
5423{
5424 int rc = IO_OK;
5425 struct CommandList *c;
5426 __le32 taglower, tagupper;
5427 struct hpsa_scsi_dev_t *dev;
5428 struct io_accel2_cmd *c2;
5429
5430 dev = abort->scsi_cmd->device->hostdata;
5431 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
5432 return -1;
5433
5434 c = cmd_alloc(h);
5435 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
5436 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5437 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5438 hpsa_get_tag(h, abort, &taglower, &tagupper);
5439 dev_dbg(&h->pdev->dev,
5440 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
5441 __func__, tagupper, taglower);
5442 /* no unmap needed here because no data xfer. */
5443
5444 dev_dbg(&h->pdev->dev,
5445 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
5446 __func__, tagupper, taglower, c2->error_data.serv_response);
5447 switch (c2->error_data.serv_response) {
5448 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
5449 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
5450 rc = 0;
5451 break;
5452 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
5453 case IOACCEL2_SERV_RESPONSE_FAILURE:
5454 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
5455 rc = -1;
5456 break;
5457 default:
5458 dev_warn(&h->pdev->dev,
5459 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
5460 __func__, tagupper, taglower,
5461 c2->error_data.serv_response);
5462 rc = -1;
5463 }
5464 cmd_free(h, c);
5465 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
5466 tagupper, taglower);
5467 return rc;
5468}
5469
6cba3f19 5470static int hpsa_send_abort_both_ways(struct ctlr_info *h,
25163bd5 5471 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
6cba3f19 5472{
8be986cc
SC		 5473 /*
5474 * ioccelerator mode 2 commands should be aborted via the
54b6e9e9 5475 * accelerated path, since RAID path is unaware of these commands,
8be986cc
SC		 5476 * but not all underlying firmware can handle abort TMF.
5477 * Change abort to physical device reset when abort TMF is unsupported.
54b6e9e9 5478 */
8be986cc
SC		 5479 if (abort->cmd_type == CMD_IOACCEL2) {
5480 if (HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)
5481 return hpsa_send_abort_ioaccel2(h, abort,
5482 reply_queue);
5483 else
5484 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
25163bd5 5485 abort, reply_queue);
8be986cc 5486 }
9b5c48c2 5487 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
25163bd5 5488}
54b6e9e9 5489
25163bd5
WS		 5490/* Find out which reply queue a command was meant to return on */
5491static int hpsa_extract_reply_queue(struct ctlr_info *h,
5492 struct CommandList *c)
5493{
5494 if (c->cmd_type == CMD_IOACCEL2)
5495 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5496 return c->Header.ReplyQueue;
6cba3f19
SC		 5497}
5498
9b5c48c2
SC		 5499/*
5500 * Limit concurrency of abort commands to prevent
5501 * over-subscription of commands
5502 */
5503static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5504{
5505#define ABORT_CMD_WAIT_MSECS 5000
5506 return !wait_event_timeout(h->abort_cmd_wait_queue,
5507 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5508 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5509}
5510
75167d2c
SC		 5511/* Send an abort for the specified command.
5512 * If the device and controller support it,
5513 * send a task abort request.
5514 */
5515static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5516{
5517
a58e7e53 5518 int rc;
75167d2c
SC		 5519 struct ctlr_info *h;
5520 struct hpsa_scsi_dev_t *dev;
5521 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 5522 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
5523 char msg[256]; /* For debug messaging. */
5524 int ml = 0;
2b08b3e9 5525 __le32 tagupper, taglower;
25163bd5
WS		 5526 int refcount, reply_queue;
5527
5528 if (sc == NULL)
5529 return FAILED;
75167d2c 5530
9b5c48c2
SC		 5531 if (sc->device == NULL)
5532 return FAILED;
5533
75167d2c
SC		 5534 /* Find the controller of the command to be aborted */
5535 h = sdev_to_hba(sc->device);
9b5c48c2 5536 if (h == NULL)
75167d2c
SC		 5537 return FAILED;
5538
25163bd5
WS		 5539 /* Find the device of the command to be aborted */
5540 dev = sc->device->hostdata;
5541 if (!dev) {
5542 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
5543 msg);
e345893b 5544 return FAILED;
25163bd5
WS		 5545 }
5546
5547 /* If controller locked up, we can guarantee command won't complete */
5548 if (lockup_detected(h)) {
5549 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5550 "ABORT FAILED, lockup detected");
5551 return FAILED;
5552 }
5553
5554 /* This is a good time to check if controller lockup has occurred */
5555 if (detect_controller_lockup(h)) {
5556 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5557 "ABORT FAILED, new lockup detected");
5558 return FAILED;
5559 }
e345893b 5560
75167d2c
SC		 5561 /* Check that controller supports some kind of task abort */
5562 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5563 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5564 return FAILED;
5565
5566 memset(msg, 0, sizeof(msg));
4b761557 5567 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
75167d2c 5568 h->scsi_host->host_no, sc->device->channel,
0d96ef5f 5569 sc->device->id, sc->device->lun,
4b761557 5570 "Aborting command", sc);
75167d2c 5571
75167d2c
SC		 5572 /* Get SCSI command to be aborted */
5573 abort = (struct CommandList *) sc->host_scribble;
5574 if (abort == NULL) {
281a7fd0
WS		 5575 /* This can happen if the command already completed. */
5576 return SUCCESS;
5577 }
5578 refcount = atomic_inc_return(&abort->refcount);
5579 if (refcount == 1) { /* Command is done already. */
5580 cmd_free(h, abort);
5581 return SUCCESS;
75167d2c 5582 }
9b5c48c2
SC		 5583
5584 /* Don't bother trying the abort if we know it won't work. */
5585 if (abort->cmd_type != CMD_IOACCEL2 &&
5586 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5587 cmd_free(h, abort);
5588 return FAILED;
5589 }
5590
a58e7e53
WS		 5591 /*
5592 * Check that we're aborting the right command.
5593 * It's possible the CommandList already completed and got re-used.
5594 */
5595 if (abort->scsi_cmd != sc) {
5596 cmd_free(h, abort);
5597 return SUCCESS;
5598 }
5599
5600 abort->abort_pending = true;
17eb87d2 5601 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5602 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 5603 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 5604 as = abort->scsi_cmd;
75167d2c 5605 if (as != NULL)
4b761557
RE		 5606 ml += sprintf(msg+ml,
5607 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
5608 as->cmd_len, as->cmnd[0], as->cmnd[1],
5609 as->serial_number);
5610 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
0d96ef5f 5611 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
4b761557 5612
75167d2c
SC		 5613 /*
5614 * Command is in flight, or possibly already completed
5615 * by the firmware (but not to the scsi mid layer) but we can't
5616 * distinguish which. Send the abort down.
5617 */
9b5c48c2
SC		 5618 if (wait_for_available_abort_cmd(h)) {
5619 dev_warn(&h->pdev->dev,
4b761557
RE		 5620 "%s FAILED, timeout waiting for an abort command to become available.\n",
5621 msg);
9b5c48c2
SC		 5622 cmd_free(h, abort);
5623 return FAILED;
5624 }
25163bd5 5625 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
9b5c48c2
SC		 5626 atomic_inc(&h->abort_cmds_available);
5627 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 5628 if (rc != 0) {
4b761557 5629 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
0d96ef5f 5630 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4b761557 5631 "FAILED to abort command");
281a7fd0 5632 cmd_free(h, abort);
75167d2c
SC		 5633 return FAILED;
5634 }
4b761557 5635 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
d604f533 5636 wait_event(h->event_sync_wait_queue,
a58e7e53 5637 abort->scsi_cmd != sc || lockup_detected(h));
281a7fd0 5638 cmd_free(h, abort);
a58e7e53 5639 return !lockup_detected(h) ? SUCCESS : FAILED;
75167d2c
SC		 5640}
5641
73153fe5
WS		 5642/*
5643 * For operations with an associated SCSI command, a command block is allocated
5644 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
5645 * block request tag as an index into a table of entries. cmd_tagged_free() is
5646 * the complement, although cmd_free() may be called instead.
5647 */
5648static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
5649 struct scsi_cmnd *scmd)
5650{
5651 int idx = hpsa_get_cmd_index(scmd);
5652 struct CommandList *c = h->cmd_pool + idx;
5653
5654 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
5655 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
5656 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
5657 /* The index value comes from the block layer, so if it's out of
5658 * bounds, it's probably not our bug.
5659 */
5660 BUG();
5661 }
5662
5663 atomic_inc(&c->refcount);
5664 if (unlikely(!hpsa_is_cmd_idle(c))) {
5665 /*
5666 * We expect that the SCSI layer will hand us a unique tag
5667 * value. Thus, there should never be a collision here between
5668 * two requests...because if the selected command isn't idle
5669 * then someone is going to be very disappointed.
5670 */
5671 dev_err(&h->pdev->dev,
5672 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
5673 idx);
5674 if (c->scsi_cmd != NULL)
5675 scsi_print_command(c->scsi_cmd);
5676 scsi_print_command(scmd);
5677 }
5678
5679 hpsa_cmd_partial_init(h, idx, c);
5680 return c;
5681}
5682
5683static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
5684{
5685 /*
5686 * Release our reference to the block. We don't need to do anything
5687 * else to free it, because it is accessed by index. (There's no point
5688 * in checking the result of the decrement, since we cannot guarantee
5689 * that there isn't a concurrent abort which is also accessing it.)
5690 */
5691 (void)atomic_dec(&c->refcount);
5692}
5693
edd16368
SC		 5694/*
5695 * For operations that cannot sleep, a command block is allocated at init,
5696 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
5697 * which ones are free or in use. Lock must be held when calling this.
5698 * cmd_free() is the complement.
bf43caf3
RE		 5699 * This function never gives up and returns NULL. If it hangs,
5700 * another thread must call cmd_free() to free some tags.
edd16368 5701 */
281a7fd0 5702
edd16368
SC		 5703static struct CommandList *cmd_alloc(struct ctlr_info *h)
5704{
5705 struct CommandList *c;
360c73bd 5706 int refcount, i;
73153fe5 5707 int offset = 0;
4c413128 5708
33811026
RE		 5709 /*
5710 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 5711 * multiple threads could get in here, and one thread could
5712 * be scanning through the list of bits looking for a free
5713 * one, but the free ones are always behind him, and other
5714 * threads sneak in behind him and eat them before he can
5715 * get to them, so that while there is always a free one, a
5716 * very unlucky thread might be starved anyway, never able to
5717 * beat the other threads. In reality, this happens so
5718 * infrequently as to be indistinguishable from never.
73153fe5
WS		 5719 *
5720 * Note that we start allocating commands before the SCSI host structure
5721 * is initialized. Since the search starts at bit zero, this
5722 * all works, since we have at least one command structure available;
5723 * however, it means that the structures with the low indexes have to be
5724 * reserved for driver-initiated requests, while requests from the block
5725 * layer will use the higher indexes.
4c413128 5726 */
edd16368 5727
281a7fd0 5728 for (;;) {
73153fe5
WS		 5729 i = find_next_zero_bit(h->cmd_pool_bits,
5730 HPSA_NRESERVED_CMDS,
5731 offset);
5732 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
281a7fd0
WS		 5733 offset = 0;
5734 continue;
5735 }
5736 c = h->cmd_pool + i;
5737 refcount = atomic_inc_return(&c->refcount);
5738 if (unlikely(refcount > 1)) {
5739 cmd_free(h, c); /* already in use */
73153fe5 5740 offset = (i + 1) % HPSA_NRESERVED_CMDS;
281a7fd0
WS		 5741 continue;
5742 }
5743 set_bit(i & (BITS_PER_LONG - 1),
5744 h->cmd_pool_bits + (i / BITS_PER_LONG));
5745 break; /* it's ours now. */
5746 }
360c73bd 5747 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 5748 return c;
5749}
5750
73153fe5
WS		 5751/*
5752 * This is the complementary operation to cmd_alloc(). Note, however, in some
5753 * corner cases it may also be used to free blocks allocated by
5754 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
5755 * the clear-bit is harmless.
5756 */
edd16368
SC		 5757static void cmd_free(struct ctlr_info *h, struct CommandList *c)
5758{
281a7fd0
WS		 5759 if (atomic_dec_and_test(&c->refcount)) {
5760 int i;
edd16368 5761
281a7fd0
WS		 5762 i = c - h->cmd_pool;
5763 clear_bit(i & (BITS_PER_LONG - 1),
5764 h->cmd_pool_bits + (i / BITS_PER_LONG));
5765 }
edd16368
SC		 5766}
5767
edd16368
SC		 5768#ifdef CONFIG_COMPAT
5769
42a91641
DB		 5770static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
5771 void __user *arg)
edd16368
SC		 5772{
5773 IOCTL32_Command_struct __user *arg32 =
5774 (IOCTL32_Command_struct __user *) arg;
5775 IOCTL_Command_struct arg64;
5776 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5777 int err;
5778 u32 cp;
5779
938abd84 5780 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5781 err = 0;
5782 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5783 sizeof(arg64.LUN_info));
5784 err |= copy_from_user(&arg64.Request, &arg32->Request,
5785 sizeof(arg64.Request));
5786 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5787 sizeof(arg64.error_info));
5788 err |= get_user(arg64.buf_size, &arg32->buf_size);
5789 err |= get_user(cp, &arg32->buf);
5790 arg64.buf = compat_ptr(cp);
5791 err |= copy_to_user(p, &arg64, sizeof(arg64));
5792
5793 if (err)
5794 return -EFAULT;
5795
42a91641 5796 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 5797 if (err)
5798 return err;
5799 err |= copy_in_user(&arg32->error_info, &p->error_info,
5800 sizeof(arg32->error_info));
5801 if (err)
5802 return -EFAULT;
5803 return err;
5804}
5805
5806static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 5807 int cmd, void __user *arg)
edd16368
SC		 5808{
5809 BIG_IOCTL32_Command_struct __user *arg32 =
5810 (BIG_IOCTL32_Command_struct __user *) arg;
5811 BIG_IOCTL_Command_struct arg64;
5812 BIG_IOCTL_Command_struct __user *p =
5813 compat_alloc_user_space(sizeof(arg64));
5814 int err;
5815 u32 cp;
5816
938abd84 5817 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5818 err = 0;
5819 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5820 sizeof(arg64.LUN_info));
5821 err |= copy_from_user(&arg64.Request, &arg32->Request,
5822 sizeof(arg64.Request));
5823 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5824 sizeof(arg64.error_info));
5825 err |= get_user(arg64.buf_size, &arg32->buf_size);
5826 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5827 err |= get_user(cp, &arg32->buf);
5828 arg64.buf = compat_ptr(cp);
5829 err |= copy_to_user(p, &arg64, sizeof(arg64));
5830
5831 if (err)
5832 return -EFAULT;
5833
42a91641 5834 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 5835 if (err)
5836 return err;
5837 err |= copy_in_user(&arg32->error_info, &p->error_info,
5838 sizeof(arg32->error_info));
5839 if (err)
5840 return -EFAULT;
5841 return err;
5842}
71fe75a7 5843
42a91641 5844static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 5845{
5846 switch (cmd) {
5847 case CCISS_GETPCIINFO:
5848 case CCISS_GETINTINFO:
5849 case CCISS_SETINTINFO:
5850 case CCISS_GETNODENAME:
5851 case CCISS_SETNODENAME:
5852 case CCISS_GETHEARTBEAT:
5853 case CCISS_GETBUSTYPES:
5854 case CCISS_GETFIRMVER:
5855 case CCISS_GETDRIVVER:
5856 case CCISS_REVALIDVOLS:
5857 case CCISS_DEREGDISK:
5858 case CCISS_REGNEWDISK:
5859 case CCISS_REGNEWD:
5860 case CCISS_RESCANDISK:
5861 case CCISS_GETLUNINFO:
5862 return hpsa_ioctl(dev, cmd, arg);
5863
5864 case CCISS_PASSTHRU32:
5865 return hpsa_ioctl32_passthru(dev, cmd, arg);
5866 case CCISS_BIG_PASSTHRU32:
5867 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5868
5869 default:
5870 return -ENOIOCTLCMD;
5871 }
5872}
edd16368
SC		 5873#endif
5874
5875static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5876{
5877 struct hpsa_pci_info pciinfo;
5878
5879 if (!argp)
5880 return -EINVAL;
5881 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5882 pciinfo.bus = h->pdev->bus->number;
5883 pciinfo.dev_fn = h->pdev->devfn;
5884 pciinfo.board_id = h->board_id;
5885 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5886 return -EFAULT;
5887 return 0;
5888}
5889
5890static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
5891{
5892 DriverVer_type DriverVer;
5893 unsigned char vmaj, vmin, vsubmin;
5894 int rc;
5895
5896 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
5897 &vmaj, &vmin, &vsubmin);
5898 if (rc != 3) {
5899 dev_info(&h->pdev->dev, "driver version string '%s' "
5900 "unrecognized.", HPSA_DRIVER_VERSION);
5901 vmaj = 0;
5902 vmin = 0;
5903 vsubmin = 0;
5904 }
5905 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
5906 if (!argp)
5907 return -EINVAL;
5908 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
5909 return -EFAULT;
5910 return 0;
5911}
5912
5913static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5914{
5915 IOCTL_Command_struct iocommand;
5916 struct CommandList *c;
5917 char *buff = NULL;
50a0decf 5918 u64 temp64;
c1f63c8f 5919 int rc = 0;
edd16368
SC		 5920
5921 if (!argp)
5922 return -EINVAL;
5923 if (!capable(CAP_SYS_RAWIO))
5924 return -EPERM;
5925 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
5926 return -EFAULT;
5927 if ((iocommand.buf_size < 1) &&
5928 (iocommand.Request.Type.Direction != XFER_NONE)) {
5929 return -EINVAL;
5930 }
5931 if (iocommand.buf_size > 0) {
5932 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
5933 if (buff == NULL)
2dd02d74 5934 return -ENOMEM;
9233fb10 5935 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 5936 /* Copy the data into the buffer we created */
5937 if (copy_from_user(buff, iocommand.buf,
5938 iocommand.buf_size)) {
c1f63c8f
SC		 5939 rc = -EFAULT;
5940 goto out_kfree;
b03a7771
SC		 5941 }
5942 } else {
5943 memset(buff, 0, iocommand.buf_size);
edd16368 5944 }
b03a7771 5945 }
45fcb86e 5946 c = cmd_alloc(h);
bf43caf3 5947
edd16368
SC		 5948 /* Fill in the command type */
5949 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 5950 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 5951 /* Fill in Command Header */
5952 c->Header.ReplyQueue = 0; /* unused in simple mode */
5953 if (iocommand.buf_size > 0) { /* buffer to fill */
5954 c->Header.SGList = 1;
50a0decf 5955 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5956 } else { /* no buffers to fill */
5957 c->Header.SGList = 0;
50a0decf 5958 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 5959 }
5960 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5961
5962 /* Fill in Request block */
5963 memcpy(&c->Request, &iocommand.Request,
5964 sizeof(c->Request));
5965
5966 /* Fill in the scatter gather information */
5967 if (iocommand.buf_size > 0) {
50a0decf 5968 temp64 = pci_map_single(h->pdev, buff,
edd16368 5969 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5970 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
5971 c->SG[0].Addr = cpu_to_le64(0);
5972 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 5973 rc = -ENOMEM;
5974 goto out;
5975 }
50a0decf
SC		 5976 c->SG[0].Addr = cpu_to_le64(temp64);
5977 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
5978 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 5979 }
25163bd5 5980 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
c2dd32e0
SC		 5981 if (iocommand.buf_size > 0)
5982 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 5983 check_ioctl_unit_attention(h, c);
25163bd5
WS		 5984 if (rc) {
5985 rc = -EIO;
5986 goto out;
5987 }
edd16368
SC		 5988
5989 /* Copy the error information out */
5990 memcpy(&iocommand.error_info, c->err_info,
5991 sizeof(iocommand.error_info));
5992 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 5993 rc = -EFAULT;
5994 goto out;
edd16368 5995 }
9233fb10 5996 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 5997 iocommand.buf_size > 0) {
edd16368
SC		 5998 /* Copy the data out of the buffer we created */
5999 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 6000 rc = -EFAULT;
6001 goto out;
edd16368
SC		 6002 }
6003 }
c1f63c8f 6004out:
45fcb86e 6005 cmd_free(h, c);
c1f63c8f
SC		 6006out_kfree:
6007 kfree(buff);
6008 return rc;
edd16368
SC		 6009}
6010
6011static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6012{
6013 BIG_IOCTL_Command_struct *ioc;
6014 struct CommandList *c;
6015 unsigned char **buff = NULL;
6016 int *buff_size = NULL;
50a0decf 6017 u64 temp64;
edd16368
SC		 6018 BYTE sg_used = 0;
6019 int status = 0;
01a02ffc
SC		 6020 u32 left;
6021 u32 sz;
edd16368
SC		 6022 BYTE __user *data_ptr;
6023
6024 if (!argp)
6025 return -EINVAL;
6026 if (!capable(CAP_SYS_RAWIO))
6027 return -EPERM;
6028 ioc = (BIG_IOCTL_Command_struct *)
6029 kmalloc(sizeof(*ioc), GFP_KERNEL);
6030 if (!ioc) {
6031 status = -ENOMEM;
6032 goto cleanup1;
6033 }
6034 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
6035 status = -EFAULT;
6036 goto cleanup1;
6037 }
6038 if ((ioc->buf_size < 1) &&
6039 (ioc->Request.Type.Direction != XFER_NONE)) {
6040 status = -EINVAL;
6041 goto cleanup1;
6042 }
6043 /* Check kmalloc limits using all SGs */
6044 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
6045 status = -EINVAL;
6046 goto cleanup1;
6047 }
d66ae08b 6048 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 6049 status = -EINVAL;
6050 goto cleanup1;
6051 }
d66ae08b 6052 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 6053 if (!buff) {
6054 status = -ENOMEM;
6055 goto cleanup1;
6056 }
d66ae08b 6057 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 6058 if (!buff_size) {
6059 status = -ENOMEM;
6060 goto cleanup1;
6061 }
6062 left = ioc->buf_size;
6063 data_ptr = ioc->buf;
6064 while (left) {
6065 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6066 buff_size[sg_used] = sz;
6067 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6068 if (buff[sg_used] == NULL) {
6069 status = -ENOMEM;
6070 goto cleanup1;
6071 }
9233fb10 6072 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 6073 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 6074 status = -EFAULT;
edd16368
SC		 6075 goto cleanup1;
6076 }
6077 } else
6078 memset(buff[sg_used], 0, sz);
6079 left -= sz;
6080 data_ptr += sz;
6081 sg_used++;
6082 }
45fcb86e 6083 c = cmd_alloc(h);
bf43caf3 6084
edd16368 6085 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6086 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368 6087 c->Header.ReplyQueue = 0;
50a0decf
SC		 6088 c->Header.SGList = (u8) sg_used;
6089 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 6090 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6091 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6092 if (ioc->buf_size > 0) {
6093 int i;
6094 for (i = 0; i < sg_used; i++) {
50a0decf 6095 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 6096 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6097 if (dma_mapping_error(&h->pdev->dev,
6098 (dma_addr_t) temp64)) {
6099 c->SG[i].Addr = cpu_to_le64(0);
6100 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 6101 hpsa_pci_unmap(h->pdev, c, i,
6102 PCI_DMA_BIDIRECTIONAL);
6103 status = -ENOMEM;
e2d4a1f6 6104 goto cleanup0;
bcc48ffa 6105 }
50a0decf
SC		 6106 c->SG[i].Addr = cpu_to_le64(temp64);
6107 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6108 c->SG[i].Ext = cpu_to_le32(0);
edd16368 6109 }
50a0decf 6110 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 6111 }
25163bd5 6112 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
b03a7771
SC		 6113 if (sg_used)
6114 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 6115 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6116 if (status) {
6117 status = -EIO;
6118 goto cleanup0;
6119 }
6120
edd16368
SC		 6121 /* Copy the error information out */
6122 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6123 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 6124 status = -EFAULT;
e2d4a1f6 6125 goto cleanup0;
edd16368 6126 }
9233fb10 6127 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 6128 int i;
6129
edd16368
SC		 6130 /* Copy the data out of the buffer we created */
6131 BYTE __user *ptr = ioc->buf;
6132 for (i = 0; i < sg_used; i++) {
6133 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 6134 status = -EFAULT;
e2d4a1f6 6135 goto cleanup0;
edd16368
SC		 6136 }
6137 ptr += buff_size[i];
6138 }
6139 }
edd16368 6140 status = 0;
e2d4a1f6 6141cleanup0:
45fcb86e 6142 cmd_free(h, c);
edd16368
SC		 6143cleanup1:
6144 if (buff) {
2b08b3e9
DB		 6145 int i;
6146
edd16368
SC		 6147 for (i = 0; i < sg_used; i++)
6148 kfree(buff[i]);
6149 kfree(buff);
6150 }
6151 kfree(buff_size);
6152 kfree(ioc);
6153 return status;
6154}
6155
6156static void check_ioctl_unit_attention(struct ctlr_info *h,
6157 struct CommandList *c)
6158{
6159 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6160 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6161 (void) check_for_unit_attention(h, c);
6162}
0390f0c0 6163
edd16368
SC		 6164/*
6165 * ioctl
6166 */
42a91641 6167static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 6168{
6169 struct ctlr_info *h;
6170 void __user *argp = (void __user *)arg;
0390f0c0 6171 int rc;
edd16368
SC		 6172
6173 h = sdev_to_hba(dev);
6174
6175 switch (cmd) {
6176 case CCISS_DEREGDISK:
6177 case CCISS_REGNEWDISK:
6178 case CCISS_REGNEWD:
a08a8471 6179 hpsa_scan_start(h->scsi_host);
edd16368
SC		 6180 return 0;
6181 case CCISS_GETPCIINFO:
6182 return hpsa_getpciinfo_ioctl(h, argp);
6183 case CCISS_GETDRIVVER:
6184 return hpsa_getdrivver_ioctl(h, argp);
6185 case CCISS_PASSTHRU:
34f0c627 6186 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6187 return -EAGAIN;
6188 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 6189 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6190 return rc;
edd16368 6191 case CCISS_BIG_PASSTHRU:
34f0c627 6192 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6193 return -EAGAIN;
6194 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 6195 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6196 return rc;
edd16368
SC		 6197 default:
6198 return -ENOTTY;
6199 }
6200}
6201
bf43caf3 6202static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6f039790 6203 u8 reset_type)
64670ac8
SC		 6204{
6205 struct CommandList *c;
6206
6207 c = cmd_alloc(h);
bf43caf3 6208
a2dac136
SC		 6209 /* fill_cmd can't fail here, no data buffer to map */
6210 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 6211 RAID_CTLR_LUNID, TYPE_MSG);
6212 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6213 c->waiting = NULL;
6214 enqueue_cmd_and_start_io(h, c);
6215 /* Don't wait for completion, the reset won't complete. Don't free
6216 * the command either. This is the last command we will send before
6217 * re-initializing everything, so it doesn't matter and won't leak.
6218 */
bf43caf3 6219 return;
64670ac8
SC		 6220}
6221
a2dac136 6222static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 6223 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 6224 int cmd_type)
6225{
6226 int pci_dir = XFER_NONE;
9b5c48c2 6227 u64 tag; /* for commands to be aborted */
edd16368
SC		 6228
6229 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6230 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6231 c->Header.ReplyQueue = 0;
6232 if (buff != NULL && size > 0) {
6233 c->Header.SGList = 1;
50a0decf 6234 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6235 } else {
6236 c->Header.SGList = 0;
50a0decf 6237 c->Header.SGTotal = cpu_to_le16(0);
edd16368 6238 }
edd16368
SC		 6239 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6240
edd16368
SC		 6241 if (cmd_type == TYPE_CMD) {
6242 switch (cmd) {
6243 case HPSA_INQUIRY:
6244 /* are we trying to read a vital product page */
b7bb24eb 6245 if (page_code & VPD_PAGE) {
edd16368 6246 c->Request.CDB[1] = 0x01;
b7bb24eb 6247 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 6248 }
6249 c->Request.CDBLen = 6;
a505b86f
SC		 6250 c->Request.type_attr_dir =
6251 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6252 c->Request.Timeout = 0;
6253 c->Request.CDB[0] = HPSA_INQUIRY;
6254 c->Request.CDB[4] = size & 0xFF;
6255 break;
6256 case HPSA_REPORT_LOG:
6257 case HPSA_REPORT_PHYS:
6258 /* Talking to controller so It's a physical command
6259 mode = 00 target = 0. Nothing to write.
6260 */
6261 c->Request.CDBLen = 12;
a505b86f
SC		 6262 c->Request.type_attr_dir =
6263 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6264 c->Request.Timeout = 0;
6265 c->Request.CDB[0] = cmd;
6266 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6267 c->Request.CDB[7] = (size >> 16) & 0xFF;
6268 c->Request.CDB[8] = (size >> 8) & 0xFF;
6269 c->Request.CDB[9] = size & 0xFF;
6270 break;
edd16368
SC		 6271 case HPSA_CACHE_FLUSH:
6272 c->Request.CDBLen = 12;
a505b86f
SC		 6273 c->Request.type_attr_dir =
6274 TYPE_ATTR_DIR(cmd_type,
6275 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 6276 c->Request.Timeout = 0;
6277 c->Request.CDB[0] = BMIC_WRITE;
6278 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 6279 c->Request.CDB[7] = (size >> 8) & 0xFF;
6280 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 6281 break;
6282 case TEST_UNIT_READY:
6283 c->Request.CDBLen = 6;
a505b86f
SC		 6284 c->Request.type_attr_dir =
6285 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 6286 c->Request.Timeout = 0;
6287 break;
283b4a9b
SC		 6288 case HPSA_GET_RAID_MAP:
6289 c->Request.CDBLen = 12;
a505b86f
SC		 6290 c->Request.type_attr_dir =
6291 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 6292 c->Request.Timeout = 0;
6293 c->Request.CDB[0] = HPSA_CISS_READ;
6294 c->Request.CDB[1] = cmd;
6295 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6296 c->Request.CDB[7] = (size >> 16) & 0xFF;
6297 c->Request.CDB[8] = (size >> 8) & 0xFF;
6298 c->Request.CDB[9] = size & 0xFF;
6299 break;
316b221a
SC		 6300 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6301 c->Request.CDBLen = 10;
a505b86f
SC		 6302 c->Request.type_attr_dir =
6303 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 6304 c->Request.Timeout = 0;
6305 c->Request.CDB[0] = BMIC_READ;
6306 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6307 c->Request.CDB[7] = (size >> 16) & 0xFF;
6308 c->Request.CDB[8] = (size >> 8) & 0xFF;
6309 break;
03383736
DB		 6310 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6311 c->Request.CDBLen = 10;
6312 c->Request.type_attr_dir =
6313 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6314 c->Request.Timeout = 0;
6315 c->Request.CDB[0] = BMIC_READ;
6316 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6317 c->Request.CDB[7] = (size >> 16) & 0xFF;
6318 c->Request.CDB[8] = (size >> 8) & 0XFF;
6319 break;
edd16368
SC		 6320 default:
6321 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6322 BUG();
a2dac136 6323 return -1;
edd16368
SC		 6324 }
6325 } else if (cmd_type == TYPE_MSG) {
6326 switch (cmd) {
6327
6328 case HPSA_DEVICE_RESET_MSG:
6329 c->Request.CDBLen = 16;
a505b86f
SC		 6330 c->Request.type_attr_dir =
6331 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 6332 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 6333 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6334 c->Request.CDB[0] = cmd;
21e89afd 6335 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 6336 /* If bytes 4-7 are zero, it means reset the */
6337 /* LunID device */
6338 c->Request.CDB[4] = 0x00;
6339 c->Request.CDB[5] = 0x00;
6340 c->Request.CDB[6] = 0x00;
6341 c->Request.CDB[7] = 0x00;
75167d2c
SC		 6342 break;
6343 case HPSA_ABORT_MSG:
9b5c48c2 6344 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 6345 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 6346 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
6347 tag, c->Header.tag);
75167d2c 6348 c->Request.CDBLen = 16;
a505b86f
SC		 6349 c->Request.type_attr_dir =
6350 TYPE_ATTR_DIR(cmd_type,
6351 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 6352 c->Request.Timeout = 0; /* Don't time out */
6353 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
6354 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
6355 c->Request.CDB[2] = 0x00; /* reserved */
6356 c->Request.CDB[3] = 0x00; /* reserved */
6357 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 6358 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 6359 c->Request.CDB[12] = 0x00; /* reserved */
6360 c->Request.CDB[13] = 0x00; /* reserved */
6361 c->Request.CDB[14] = 0x00; /* reserved */
6362 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 6363 break;
edd16368
SC		 6364 default:
6365 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6366 cmd);
6367 BUG();
6368 }
6369 } else {
6370 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6371 BUG();
6372 }
6373
a505b86f 6374 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 6375 case XFER_READ:
6376 pci_dir = PCI_DMA_FROMDEVICE;
6377 break;
6378 case XFER_WRITE:
6379 pci_dir = PCI_DMA_TODEVICE;
6380 break;
6381 case XFER_NONE:
6382 pci_dir = PCI_DMA_NONE;
6383 break;
6384 default:
6385 pci_dir = PCI_DMA_BIDIRECTIONAL;
6386 }
a2dac136
SC		 6387 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
6388 return -1;
6389 return 0;
edd16368
SC		 6390}
6391
6392/*
6393 * Map (physical) PCI mem into (virtual) kernel space
6394 */
6395static void __iomem *remap_pci_mem(ulong base, ulong size)
6396{
6397 ulong page_base = ((ulong) base) & PAGE_MASK;
6398 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 6399 void __iomem *page_remapped = ioremap_nocache(page_base,
6400 page_offs + size);
edd16368
SC		 6401
6402 return page_remapped ? (page_remapped + page_offs) : NULL;
6403}
6404
254f796b 6405static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 6406{
254f796b 6407 return h->access.command_completed(h, q);
edd16368
SC		 6408}
6409
900c5440 6410static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 6411{
6412 return h->access.intr_pending(h);
6413}
6414
6415static inline long interrupt_not_for_us(struct ctlr_info *h)
6416{
10f66018
SC		 6417 return (h->access.intr_pending(h) == 0) ||
6418 (h->interrupts_enabled == 0);
edd16368
SC		 6419}
6420
01a02ffc
SC		 6421static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6422 u32 raw_tag)
edd16368
SC		 6423{
6424 if (unlikely(tag_index >= h->nr_cmds)) {
6425 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6426 return 1;
6427 }
6428 return 0;
6429}
6430
5a3d16f5 6431static inline void finish_cmd(struct CommandList *c)
edd16368 6432{
e85c5974 6433 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 6434 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6435 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 6436 complete_scsi_command(c);
8be986cc 6437 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
edd16368 6438 complete(c->waiting);
a104c99f
SC		 6439}
6440
a9a3a273
SC		 6441
6442static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 6443{
a9a3a273
SC		 6444#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
6445#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 6446 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 6447 return tag & ~HPSA_SIMPLE_ERROR_BITS;
6448 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 6449}
6450
303932fd 6451/* process completion of an indexed ("direct lookup") command */
1d94f94d 6452static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 6453 u32 raw_tag)
6454{
6455 u32 tag_index;
6456 struct CommandList *c;
6457
f2405db8 6458 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 6459 if (!bad_tag(h, tag_index, raw_tag)) {
6460 c = h->cmd_pool + tag_index;
6461 finish_cmd(c);
6462 }
303932fd
DB		 6463}
6464
64670ac8
SC		 6465/* Some controllers, like p400, will give us one interrupt
6466 * after a soft reset, even if we turned interrupts off.
6467 * Only need to check for this in the hpsa_xxx_discard_completions
6468 * functions.
6469 */
6470static int ignore_bogus_interrupt(struct ctlr_info *h)
6471{
6472 if (likely(!reset_devices))
6473 return 0;
6474
6475 if (likely(h->interrupts_enabled))
6476 return 0;
6477
6478 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
6479 "(known firmware bug.) Ignoring.\n");
6480
6481 return 1;
6482}
6483
254f796b
MG		 6484/*
6485 * Convert &h->q[x] (passed to interrupt handlers) back to h.
6486 * Relies on (h-q[x] == x) being true for x such that
6487 * 0 <= x < MAX_REPLY_QUEUES.
6488 */
6489static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 6490{
254f796b
MG		 6491 return container_of((queue - *queue), struct ctlr_info, q[0]);
6492}
6493
6494static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6495{
6496 struct ctlr_info *h = queue_to_hba(queue);
6497 u8 q = *(u8 *) queue;
64670ac8
SC		 6498 u32 raw_tag;
6499
6500 if (ignore_bogus_interrupt(h))
6501 return IRQ_NONE;
6502
6503 if (interrupt_not_for_us(h))
6504 return IRQ_NONE;
a0c12413 6505 h->last_intr_timestamp = get_jiffies_64();
64670ac8 6506 while (interrupt_pending(h)) {
254f796b 6507 raw_tag = get_next_completion(h, q);
64670ac8 6508 while (raw_tag != FIFO_EMPTY)
254f796b 6509 raw_tag = next_command(h, q);
64670ac8 6510 }
64670ac8
SC		 6511 return IRQ_HANDLED;
6512}
6513
254f796b 6514static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 6515{
254f796b 6516 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 6517 u32 raw_tag;
254f796b 6518 u8 q = *(u8 *) queue;
64670ac8
SC		 6519
6520 if (ignore_bogus_interrupt(h))
6521 return IRQ_NONE;
6522
a0c12413 6523 h->last_intr_timestamp = get_jiffies_64();
254f796b 6524 raw_tag = get_next_completion(h, q);
64670ac8 6525 while (raw_tag != FIFO_EMPTY)
254f796b 6526 raw_tag = next_command(h, q);
64670ac8
SC		 6527 return IRQ_HANDLED;
6528}
6529
254f796b 6530static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 6531{
254f796b 6532 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 6533 u32 raw_tag;
254f796b 6534 u8 q = *(u8 *) queue;
edd16368
SC		 6535
6536 if (interrupt_not_for_us(h))
6537 return IRQ_NONE;
a0c12413 6538 h->last_intr_timestamp = get_jiffies_64();
10f66018 6539 while (interrupt_pending(h)) {
254f796b 6540 raw_tag = get_next_completion(h, q);
10f66018 6541 while (raw_tag != FIFO_EMPTY) {
f2405db8 6542 process_indexed_cmd(h, raw_tag);
254f796b 6543 raw_tag = next_command(h, q);
10f66018
SC		 6544 }
6545 }
10f66018
SC		 6546 return IRQ_HANDLED;
6547}
6548
254f796b 6549static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 6550{
254f796b 6551 struct ctlr_info *h = queue_to_hba(queue);
10f66018 6552 u32 raw_tag;
254f796b 6553 u8 q = *(u8 *) queue;
10f66018 6554
a0c12413 6555 h->last_intr_timestamp = get_jiffies_64();
254f796b 6556 raw_tag = get_next_completion(h, q);
303932fd 6557 while (raw_tag != FIFO_EMPTY) {
f2405db8 6558 process_indexed_cmd(h, raw_tag);
254f796b 6559 raw_tag = next_command(h, q);
edd16368 6560 }
edd16368
SC		 6561 return IRQ_HANDLED;
6562}
6563
a9a3a273
SC		 6564/* Send a message CDB to the firmware. Careful, this only works
6565 * in simple mode, not performant mode due to the tag lookup.
6566 * We only ever use this immediately after a controller reset.
6567 */
6f039790
GKH		 6568static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
6569 unsigned char type)
edd16368
SC		 6570{
6571 struct Command {
6572 struct CommandListHeader CommandHeader;
6573 struct RequestBlock Request;
6574 struct ErrDescriptor ErrorDescriptor;
6575 };
6576 struct Command *cmd;
6577 static const size_t cmd_sz = sizeof(*cmd) +
6578 sizeof(cmd->ErrorDescriptor);
6579 dma_addr_t paddr64;
2b08b3e9
DB		 6580 __le32 paddr32;
6581 u32 tag;
edd16368
SC		 6582 void __iomem *vaddr;
6583 int i, err;
6584
6585 vaddr = pci_ioremap_bar(pdev, 0);
6586 if (vaddr == NULL)
6587 return -ENOMEM;
6588
6589 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
6590 * CCISS commands, so they must be allocated from the lower 4GiB of
6591 * memory.
6592 */
6593 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6594 if (err) {
6595 iounmap(vaddr);
1eaec8f3 6596 return err;
edd16368
SC		 6597 }
6598
6599 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
6600 if (cmd == NULL) {
6601 iounmap(vaddr);
6602 return -ENOMEM;
6603 }
6604
6605 /* This must fit, because of the 32-bit consistent DMA mask. Also,
6606 * although there's no guarantee, we assume that the address is at
6607 * least 4-byte aligned (most likely, it's page-aligned).
6608 */
2b08b3e9 6609 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 6610
6611 cmd->CommandHeader.ReplyQueue = 0;
6612 cmd->CommandHeader.SGList = 0;
50a0decf 6613 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 6614 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 6615 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
6616
6617 cmd->Request.CDBLen = 16;
a505b86f
SC		 6618 cmd->Request.type_attr_dir =
6619 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 6620 cmd->Request.Timeout = 0; /* Don't time out */
6621 cmd->Request.CDB[0] = opcode;
6622 cmd->Request.CDB[1] = type;
6623 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 6624 cmd->ErrorDescriptor.Addr =
2b08b3e9 6625 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 6626 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 6627
2b08b3e9 6628 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 6629
6630 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
6631 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 6632 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 6633 break;
6634 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
6635 }
6636
6637 iounmap(vaddr);
6638
6639 /* we leak the DMA buffer here ... no choice since the controller could
6640 * still complete the command.
6641 */
6642 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
6643 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
6644 opcode, type);
6645 return -ETIMEDOUT;
6646 }
6647
6648 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
6649
6650 if (tag & HPSA_ERROR_BIT) {
6651 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
6652 opcode, type);
6653 return -EIO;
6654 }
6655
6656 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
6657 opcode, type);
6658 return 0;
6659}
6660
edd16368
SC		 6661#define hpsa_noop(p) hpsa_message(p, 3, 0)
6662
1df8552a 6663static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 6664 void __iomem *vaddr, u32 use_doorbell)
1df8552a 6665{
1df8552a
SC		 6666
6667 if (use_doorbell) {
6668 /* For everything after the P600, the PCI power state method
6669 * of resetting the controller doesn't work, so we have this
6670 * other way using the doorbell register.
6671 */
6672 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 6673 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 6674
00701a96 6675 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 6676 * doorbell reset and before any attempt to talk to the board
6677 * at all to ensure that this actually works and doesn't fall
6678 * over in some weird corner cases.
6679 */
00701a96 6680 msleep(10000);
1df8552a
SC		 6681 } else { /* Try to do it the PCI power state way */
6682
6683 /* Quoting from the Open CISS Specification: "The Power
6684 * Management Control/Status Register (CSR) controls the power
6685 * state of the device. The normal operating state is D0,
6686 * CSR=00h. The software off state is D3, CSR=03h. To reset
6687 * the controller, place the interface device in D3 then to D0,
6688 * this causes a secondary PCI reset which will reset the
6689 * controller." */
2662cab8
DB		 6690
6691 int rc = 0;
6692
1df8552a 6693 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 6694
1df8552a 6695 /* enter the D3hot power management state */
2662cab8
DB		 6696 rc = pci_set_power_state(pdev, PCI_D3hot);
6697 if (rc)
6698 return rc;
1df8552a
SC		 6699
6700 msleep(500);
6701
6702 /* enter the D0 power management state */
2662cab8
DB		 6703 rc = pci_set_power_state(pdev, PCI_D0);
6704 if (rc)
6705 return rc;
c4853efe
MM		 6706
6707 /*
6708 * The P600 requires a small delay when changing states.
6709 * Otherwise we may think the board did not reset and we bail.
6710 * This for kdump only and is particular to the P600.
6711 */
6712 msleep(500);
1df8552a
SC		 6713 }
6714 return 0;
6715}
6716
6f039790 6717static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 6718{
6719 memset(driver_version, 0, len);
f79cfec6 6720 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 6721}
6722
6f039790 6723static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6724{
6725 char *driver_version;
6726 int i, size = sizeof(cfgtable->driver_version);
6727
6728 driver_version = kmalloc(size, GFP_KERNEL);
6729 if (!driver_version)
6730 return -ENOMEM;
6731
6732 init_driver_version(driver_version, size);
6733 for (i = 0; i < size; i++)
6734 writeb(driver_version[i], &cfgtable->driver_version[i]);
6735 kfree(driver_version);
6736 return 0;
6737}
6738
6f039790
GKH		 6739static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
6740 unsigned char *driver_ver)
580ada3c
SC		 6741{
6742 int i;
6743
6744 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
6745 driver_ver[i] = readb(&cfgtable->driver_version[i]);
6746}
6747
6f039790 6748static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6749{
6750
6751 char *driver_ver, *old_driver_ver;
6752 int rc, size = sizeof(cfgtable->driver_version);
6753
6754 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
6755 if (!old_driver_ver)
6756 return -ENOMEM;
6757 driver_ver = old_driver_ver + size;
6758
6759 /* After a reset, the 32 bytes of "driver version" in the cfgtable
6760 * should have been changed, otherwise we know the reset failed.
6761 */
6762 init_driver_version(old_driver_ver, size);
6763 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
6764 rc = !memcmp(driver_ver, old_driver_ver, size);
6765 kfree(old_driver_ver);
6766 return rc;
6767}
edd16368 6768/* This does a hard reset of the controller using PCI power management
1df8552a 6769 * states or the using the doorbell register.
edd16368 6770 */
6b6c1cd7 6771static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 6772{
1df8552a
SC		 6773 u64 cfg_offset;
6774 u32 cfg_base_addr;
6775 u64 cfg_base_addr_index;
6776 void __iomem *vaddr;
6777 unsigned long paddr;
580ada3c 6778 u32 misc_fw_support;
270d05de 6779 int rc;
1df8552a 6780 struct CfgTable __iomem *cfgtable;
cf0b08d0 6781 u32 use_doorbell;
270d05de 6782 u16 command_register;
edd16368 6783
1df8552a
SC		 6784 /* For controllers as old as the P600, this is very nearly
6785 * the same thing as
edd16368
SC		 6786 *
6787 * pci_save_state(pci_dev);
6788 * pci_set_power_state(pci_dev, PCI_D3hot);
6789 * pci_set_power_state(pci_dev, PCI_D0);
6790 * pci_restore_state(pci_dev);
6791 *
1df8552a
SC		 6792 * For controllers newer than the P600, the pci power state
6793 * method of resetting doesn't work so we have another way
6794 * using the doorbell register.
edd16368 6795 */
18867659 6796
60f923b9
RE		 6797 if (!ctlr_is_resettable(board_id)) {
6798 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 6799 return -ENODEV;
6800 }
46380786
SC		 6801
6802 /* if controller is soft- but not hard resettable... */
6803 if (!ctlr_is_hard_resettable(board_id))
6804 return -ENOTSUPP; /* try soft reset later. */
18867659 6805
270d05de
SC		 6806 /* Save the PCI command register */
6807 pci_read_config_word(pdev, 4, &command_register);
270d05de 6808 pci_save_state(pdev);
edd16368 6809
1df8552a
SC		 6810 /* find the first memory BAR, so we can find the cfg table */
6811 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6812 if (rc)
6813 return rc;
6814 vaddr = remap_pci_mem(paddr, 0x250);
6815 if (!vaddr)
6816 return -ENOMEM;
edd16368 6817
1df8552a
SC		 6818 /* find cfgtable in order to check if reset via doorbell is supported */
6819 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6820 &cfg_base_addr_index, &cfg_offset);
6821 if (rc)
6822 goto unmap_vaddr;
6823 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6824 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6825 if (!cfgtable) {
6826 rc = -ENOMEM;
6827 goto unmap_vaddr;
6828 }
580ada3c
SC		 6829 rc = write_driver_ver_to_cfgtable(cfgtable);
6830 if (rc)
03741d95 6831 goto unmap_cfgtable;
edd16368 6832
cf0b08d0
SC		 6833 /* If reset via doorbell register is supported, use that.
6834 * There are two such methods. Favor the newest method.
6835 */
1df8552a 6836 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6837 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6838 if (use_doorbell) {
6839 use_doorbell = DOORBELL_CTLR_RESET2;
6840 } else {
6841 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6842 if (use_doorbell) {
050f7147
SC		 6843 dev_warn(&pdev->dev,
6844 "Soft reset not supported. Firmware update is required.\n");
64670ac8 6845 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6846 goto unmap_cfgtable;
6847 }
6848 }
edd16368 6849
1df8552a
SC		 6850 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6851 if (rc)
6852 goto unmap_cfgtable;
edd16368 6853
270d05de 6854 pci_restore_state(pdev);
270d05de 6855 pci_write_config_word(pdev, 4, command_register);
edd16368 6856
1df8552a
SC		 6857 /* Some devices (notably the HP Smart Array 5i Controller)
6858 need a little pause here */
6859 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6860
fe5389c8
SC		 6861 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6862 if (rc) {
6863 dev_warn(&pdev->dev,
050f7147 6864 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 6865 goto unmap_cfgtable;
6866 }
fe5389c8 6867
580ada3c
SC		 6868 rc = controller_reset_failed(vaddr);
6869 if (rc < 0)
6870 goto unmap_cfgtable;
6871 if (rc) {
64670ac8
SC		 6872 dev_warn(&pdev->dev, "Unable to successfully reset "
6873 "controller. Will try soft reset.\n");
6874 rc = -ENOTSUPP;
580ada3c 6875 } else {
64670ac8 6876 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6877 }
6878
6879unmap_cfgtable:
6880 iounmap(cfgtable);
6881
6882unmap_vaddr:
6883 iounmap(vaddr);
6884 return rc;
edd16368
SC		 6885}
6886
6887/*
6888 * We cannot read the structure directly, for portability we must use
6889 * the io functions.
6890 * This is for debug only.
6891 */
42a91641 6892static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 6893{
58f8665c 6894#ifdef HPSA_DEBUG
edd16368
SC		 6895 int i;
6896 char temp_name[17];
6897
6898 dev_info(dev, "Controller Configuration information\n");
6899 dev_info(dev, "------------------------------------\n");
6900 for (i = 0; i < 4; i++)
6901 temp_name[i] = readb(&(tb->Signature[i]));
6902 temp_name[4] = '\0';
6903 dev_info(dev, " Signature = %s\n", temp_name);
6904 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6905 dev_info(dev, " Transport methods supported = 0x%x\n",
6906 readl(&(tb->TransportSupport)));
6907 dev_info(dev, " Transport methods active = 0x%x\n",
6908 readl(&(tb->TransportActive)));
6909 dev_info(dev, " Requested transport Method = 0x%x\n",
6910 readl(&(tb->HostWrite.TransportRequest)));
6911 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6912 readl(&(tb->HostWrite.CoalIntDelay)));
6913 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6914 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 6915 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 6916 readl(&(tb->CmdsOutMax)));
6917 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6918 for (i = 0; i < 16; i++)
6919 temp_name[i] = readb(&(tb->ServerName[i]));
6920 temp_name[16] = '\0';
6921 dev_info(dev, " Server Name = %s\n", temp_name);
6922 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6923 readl(&(tb->HeartBeat)));
edd16368 6924#endif /* HPSA_DEBUG */
58f8665c 6925}
edd16368
SC		 6926
6927static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6928{
6929 int i, offset, mem_type, bar_type;
6930
6931 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6932 return 0;
6933 offset = 0;
6934 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6935 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6936 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6937 offset += 4;
6938 else {
6939 mem_type = pci_resource_flags(pdev, i) &
6940 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6941 switch (mem_type) {
6942 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6943 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6944 offset += 4; /* 32 bit */
6945 break;
6946 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6947 offset += 8;
6948 break;
6949 default: /* reserved in PCI 2.2 */
6950 dev_warn(&pdev->dev,
6951 "base address is invalid\n");
6952 return -1;
6953 break;
6954 }
6955 }
6956 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6957 return i + 1;
6958 }
6959 return -1;
6960}
6961
cc64c817
RE		 6962static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
6963{
6964 if (h->msix_vector) {
6965 if (h->pdev->msix_enabled)
6966 pci_disable_msix(h->pdev);
105a3dbc 6967 h->msix_vector = 0;
cc64c817
RE		 6968 } else if (h->msi_vector) {
6969 if (h->pdev->msi_enabled)
6970 pci_disable_msi(h->pdev);
105a3dbc 6971 h->msi_vector = 0;
cc64c817
RE		 6972 }
6973}
6974
edd16368 6975/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 6976 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 6977 */
6f039790 6978static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6979{
6980#ifdef CONFIG_PCI_MSI
254f796b
MG		 6981 int err, i;
6982 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6983
6984 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6985 hpsa_msix_entries[i].vector = 0;
6986 hpsa_msix_entries[i].entry = i;
6987 }
edd16368
SC		 6988
6989 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6990 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6991 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6992 goto default_int_mode;
55c06c71 6993 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 6994 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 6995 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 6996 if (h->msix_vector > num_online_cpus())
6997 h->msix_vector = num_online_cpus();
18fce3c4
AG		 6998 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
6999 1, h->msix_vector);
7000 if (err < 0) {
7001 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
7002 h->msix_vector = 0;
7003 goto single_msi_mode;
7004 } else if (err < h->msix_vector) {
55c06c71 7005 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 7006 "available\n", err);
edd16368 7007 }
18fce3c4
AG		 7008 h->msix_vector = err;
7009 for (i = 0; i < h->msix_vector; i++)
7010 h->intr[i] = hpsa_msix_entries[i].vector;
7011 return;
edd16368 7012 }
18fce3c4 7013single_msi_mode:
55c06c71 7014 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 7015 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 7016 if (!pci_enable_msi(h->pdev))
edd16368
SC		 7017 h->msi_vector = 1;
7018 else
55c06c71 7019 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 7020 }
7021default_int_mode:
7022#endif /* CONFIG_PCI_MSI */
7023 /* if we get here we're going to use the default interrupt mode */
a9a3a273 7024 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 7025}
7026
6f039790 7027static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 7028{
7029 int i;
7030 u32 subsystem_vendor_id, subsystem_device_id;
7031
7032 subsystem_vendor_id = pdev->subsystem_vendor;
7033 subsystem_device_id = pdev->subsystem_device;
7034 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
7035 subsystem_vendor_id;
7036
7037 for (i = 0; i < ARRAY_SIZE(products); i++)
7038 if (*board_id == products[i].board_id)
7039 return i;
7040
6798cc0a
SC		 7041 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
7042 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
7043 !hpsa_allow_any) {
e5c880d1
SC		 7044 dev_warn(&pdev->dev, "unrecognized board ID: "
7045 "0x%08x, ignoring.\n", *board_id);
7046 return -ENODEV;
7047 }
7048 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
7049}
7050
6f039790
GKH		 7051static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
7052 unsigned long *memory_bar)
3a7774ce
SC		 7053{
7054 int i;
7055
7056 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 7057 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 7058 /* addressing mode bits already removed */
12d2cd47
SC		 7059 *memory_bar = pci_resource_start(pdev, i);
7060 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 7061 *memory_bar);
7062 return 0;
7063 }
12d2cd47 7064 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 7065 return -ENODEV;
7066}
7067
6f039790
GKH		 7068static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7069 int wait_for_ready)
2c4c8c8b 7070{
fe5389c8 7071 int i, iterations;
2c4c8c8b 7072 u32 scratchpad;
fe5389c8
SC		 7073 if (wait_for_ready)
7074 iterations = HPSA_BOARD_READY_ITERATIONS;
7075 else
7076 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 7077
fe5389c8
SC		 7078 for (i = 0; i < iterations; i++) {
7079 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7080 if (wait_for_ready) {
7081 if (scratchpad == HPSA_FIRMWARE_READY)
7082 return 0;
7083 } else {
7084 if (scratchpad != HPSA_FIRMWARE_READY)
7085 return 0;
7086 }
2c4c8c8b
SC		 7087 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7088 }
fe5389c8 7089 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 7090 return -ENODEV;
7091}
7092
6f039790
GKH		 7093static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7094 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7095 u64 *cfg_offset)
a51fd47f
SC		 7096{
7097 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7098 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7099 *cfg_base_addr &= (u32) 0x0000ffff;
7100 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7101 if (*cfg_base_addr_index == -1) {
7102 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7103 return -ENODEV;
7104 }
7105 return 0;
7106}
7107
195f2c65
RE		 7108static void hpsa_free_cfgtables(struct ctlr_info *h)
7109{
105a3dbc 7110 if (h->transtable) {
195f2c65 7111 iounmap(h->transtable);
105a3dbc
RE		 7112 h->transtable = NULL;
7113 }
7114 if (h->cfgtable) {
195f2c65 7115 iounmap(h->cfgtable);
105a3dbc
RE		 7116 h->cfgtable = NULL;
7117 }
195f2c65
RE		 7118}
7119
7120/* Find and map CISS config table and transfer table
7121+ * several items must be unmapped (freed) later
7122+ * */
6f039790 7123static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 7124{
01a02ffc
SC		 7125 u64 cfg_offset;
7126 u32 cfg_base_addr;
7127 u64 cfg_base_addr_index;
303932fd 7128 u32 trans_offset;
a51fd47f 7129 int rc;
77c4495c 7130
a51fd47f
SC		 7131 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7132 &cfg_base_addr_index, &cfg_offset);
7133 if (rc)
7134 return rc;
77c4495c 7135 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 7136 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 7137 if (!h->cfgtable) {
7138 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 7139 return -ENOMEM;
cd3c81c4 7140 }
580ada3c
SC		 7141 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7142 if (rc)
7143 return rc;
77c4495c 7144 /* Find performant mode table. */
a51fd47f 7145 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 7146 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7147 cfg_base_addr_index)+cfg_offset+trans_offset,
7148 sizeof(*h->transtable));
195f2c65
RE		 7149 if (!h->transtable) {
7150 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7151 hpsa_free_cfgtables(h);
77c4495c 7152 return -ENOMEM;
195f2c65 7153 }
77c4495c
SC		 7154 return 0;
7155}
7156
6f039790 7157static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 7158{
41ce4c35
SC		 7159#define MIN_MAX_COMMANDS 16
7160 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7161
7162 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 7163
7164 /* Limit commands in memory limited kdump scenario. */
7165 if (reset_devices && h->max_commands > 32)
7166 h->max_commands = 32;
7167
41ce4c35
SC		 7168 if (h->max_commands < MIN_MAX_COMMANDS) {
7169 dev_warn(&h->pdev->dev,
7170 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7171 h->max_commands,
7172 MIN_MAX_COMMANDS);
7173 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 7174 }
7175}
7176
c7ee65b3
WS		 7177/* If the controller reports that the total max sg entries is greater than 512,
7178 * then we know that chained SG blocks work. (Original smart arrays did not
7179 * support chained SG blocks and would return zero for max sg entries.)
7180 */
7181static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7182{
7183 return h->maxsgentries > 512;
7184}
7185
b93d7536
SC		 7186/* Interrogate the hardware for some limits:
7187 * max commands, max SG elements without chaining, and with chaining,
7188 * SG chain block size, etc.
7189 */
6f039790 7190static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 7191{
cba3d38b 7192 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 7193 h->nr_cmds = h->max_commands;
b93d7536 7194 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 7195 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 7196 if (hpsa_supports_chained_sg_blocks(h)) {
7197 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 7198 h->max_cmd_sg_entries = 32;
1a63ea6f 7199 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 7200 h->maxsgentries--; /* save one for chain pointer */
7201 } else {
c7ee65b3
WS		 7202 /*
7203 * Original smart arrays supported at most 31 s/g entries
7204 * embedded inline in the command (trying to use more
7205 * would lock up the controller)
7206 */
7207 h->max_cmd_sg_entries = 31;
1a63ea6f 7208 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 7209 h->chainsize = 0;
b93d7536 7210 }
75167d2c
SC		 7211
7212 /* Find out what task management functions are supported and cache */
7213 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 7214 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7215 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7216 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7217 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
8be986cc
SC		 7218 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7219 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
b93d7536
SC		 7220}
7221
76c46e49
SC		 7222static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7223{
0fc9fd40 7224 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 7225 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 7226 return false;
7227 }
7228 return true;
7229}
7230
97a5e98c 7231static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 7232{
97a5e98c 7233 u32 driver_support;
f7c39101 7234
97a5e98c 7235 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 7236 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7237#ifdef CONFIG_X86
97a5e98c 7238 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 7239#endif
28e13446
SC		 7240 driver_support |= ENABLE_UNIT_ATTN;
7241 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 7242}
7243
3d0eab67
SC		 7244/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7245 * in a prefetch beyond physical memory.
7246 */
7247static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7248{
7249 u32 dma_prefetch;
7250
7251 if (h->board_id != 0x3225103C)
7252 return;
7253 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7254 dma_prefetch |= 0x8000;
7255 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7256}
7257
c706a795 7258static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 7259{
7260 int i;
7261 u32 doorbell_value;
7262 unsigned long flags;
7263 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 7264 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 7265 spin_lock_irqsave(&h->lock, flags);
7266 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7267 spin_unlock_irqrestore(&h->lock, flags);
7268 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 7269 goto done;
76438d08 7270 /* delay and try again */
007e7aa9 7271 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 7272 }
c706a795
RE		 7273 return -ENODEV;
7274done:
7275 return 0;
76438d08
SC		 7276}
7277
c706a795 7278static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 7279{
7280 int i;
6eaf46fd
SC		 7281 u32 doorbell_value;
7282 unsigned long flags;
eb6b2ae9
SC		 7283
7284 /* under certain very rare conditions, this can take awhile.
7285 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7286 * as we enter this code.)
7287 */
007e7aa9 7288 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 7289 if (h->remove_in_progress)
7290 goto done;
6eaf46fd
SC		 7291 spin_lock_irqsave(&h->lock, flags);
7292 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7293 spin_unlock_irqrestore(&h->lock, flags);
382be668 7294 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 7295 goto done;
eb6b2ae9 7296 /* delay and try again */
007e7aa9 7297 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 7298 }
c706a795
RE		 7299 return -ENODEV;
7300done:
7301 return 0;
3f4336f3
SC		 7302}
7303
c706a795 7304/* return -ENODEV or other reason on error, 0 on success */
6f039790 7305static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 7306{
7307 u32 trans_support;
7308
7309 trans_support = readl(&(h->cfgtable->TransportSupport));
7310 if (!(trans_support & SIMPLE_MODE))
7311 return -ENOTSUPP;
7312
7313 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 7314
3f4336f3
SC		 7315 /* Update the field, and then ring the doorbell */
7316 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 7317 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 7318 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7319 if (hpsa_wait_for_mode_change_ack(h))
7320 goto error;
eb6b2ae9 7321 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 7322 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7323 goto error;
960a30e7 7324 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 7325 return 0;
283b4a9b 7326error:
050f7147 7327 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 7328 return -ENODEV;
eb6b2ae9
SC		 7329}
7330
195f2c65
RE		 7331/* free items allocated or mapped by hpsa_pci_init */
7332static void hpsa_free_pci_init(struct ctlr_info *h)
7333{
7334 hpsa_free_cfgtables(h); /* pci_init 4 */
7335 iounmap(h->vaddr); /* pci_init 3 */
105a3dbc 7336 h->vaddr = NULL;
195f2c65 7337 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
943a7021
RE		 7338 /*
7339 * call pci_disable_device before pci_release_regions per
7340 * Documentation/PCI/pci.txt
7341 */
195f2c65 7342 pci_disable_device(h->pdev); /* pci_init 1 */
943a7021 7343 pci_release_regions(h->pdev); /* pci_init 2 */
195f2c65
RE		 7344}
7345
7346/* several items must be freed later */
6f039790 7347static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 7348{
eb6b2ae9 7349 int prod_index, err;
edd16368 7350
e5c880d1
SC		 7351 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
7352 if (prod_index < 0)
60f923b9 7353 return prod_index;
e5c880d1
SC		 7354 h->product_name = products[prod_index].product_name;
7355 h->access = *(products[prod_index].access);
edd16368 7356
9b5c48c2
SC		 7357 h->needs_abort_tags_swizzled =
7358 ctlr_needs_abort_tags_swizzled(h->board_id);
7359
e5a44df8
MG		 7360 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7361 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7362
55c06c71 7363 err = pci_enable_device(h->pdev);
edd16368 7364 if (err) {
195f2c65 7365 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
943a7021 7366 pci_disable_device(h->pdev);
edd16368
SC		 7367 return err;
7368 }
7369
f79cfec6 7370 err = pci_request_regions(h->pdev, HPSA);
edd16368 7371 if (err) {
55c06c71 7372 dev_err(&h->pdev->dev,
195f2c65 7373 "failed to obtain PCI resources\n");
943a7021
RE		 7374 pci_disable_device(h->pdev);
7375 return err;
edd16368 7376 }
4fa604e1
RE		 7377
7378 pci_set_master(h->pdev);
7379
6b3f4c52 7380 hpsa_interrupt_mode(h);
12d2cd47 7381 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 7382 if (err)
195f2c65 7383 goto clean2; /* intmode+region, pci */
edd16368 7384 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 7385 if (!h->vaddr) {
195f2c65 7386 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 7387 err = -ENOMEM;
195f2c65 7388 goto clean2; /* intmode+region, pci */
204892e9 7389 }
fe5389c8 7390 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 7391 if (err)
195f2c65 7392 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 7393 err = hpsa_find_cfgtables(h);
7394 if (err)
195f2c65 7395 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 7396 hpsa_find_board_params(h);
edd16368 7397
76c46e49 7398 if (!hpsa_CISS_signature_present(h)) {
edd16368 7399 err = -ENODEV;
195f2c65 7400 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 7401 }
97a5e98c 7402 hpsa_set_driver_support_bits(h);
3d0eab67 7403 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 7404 err = hpsa_enter_simple_mode(h);
7405 if (err)
195f2c65 7406 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 7407 return 0;
7408
195f2c65
RE		 7409clean4: /* cfgtables, vaddr, intmode+region, pci */
7410 hpsa_free_cfgtables(h);
7411clean3: /* vaddr, intmode+region, pci */
7412 iounmap(h->vaddr);
105a3dbc 7413 h->vaddr = NULL;
195f2c65
RE		 7414clean2: /* intmode+region, pci */
7415 hpsa_disable_interrupt_mode(h);
943a7021
RE		 7416 /*
7417 * call pci_disable_device before pci_release_regions per
7418 * Documentation/PCI/pci.txt
7419 */
195f2c65 7420 pci_disable_device(h->pdev);
943a7021 7421 pci_release_regions(h->pdev);
edd16368
SC		 7422 return err;
7423}
7424
6f039790 7425static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 7426{
7427 int rc;
7428
7429#define HBA_INQUIRY_BYTE_COUNT 64
7430 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7431 if (!h->hba_inquiry_data)
7432 return;
7433 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7434 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7435 if (rc != 0) {
7436 kfree(h->hba_inquiry_data);
7437 h->hba_inquiry_data = NULL;
7438 }
7439}
7440
6b6c1cd7 7441static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 7442{
1df8552a 7443 int rc, i;
3b747298 7444 void __iomem *vaddr;
4c2a8c40
SC		 7445
7446 if (!reset_devices)
7447 return 0;
7448
132aa220
TH		 7449 /* kdump kernel is loading, we don't know in which state is
7450 * the pci interface. The dev->enable_cnt is equal zero
7451 * so we call enable+disable, wait a while and switch it on.
7452 */
7453 rc = pci_enable_device(pdev);
7454 if (rc) {
7455 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7456 return -ENODEV;
7457 }
7458 pci_disable_device(pdev);
7459 msleep(260); /* a randomly chosen number */
7460 rc = pci_enable_device(pdev);
7461 if (rc) {
7462 dev_warn(&pdev->dev, "failed to enable device.\n");
7463 return -ENODEV;
7464 }
4fa604e1 7465
859c75ab 7466 pci_set_master(pdev);
4fa604e1 7467
3b747298
TH		 7468 vaddr = pci_ioremap_bar(pdev, 0);
7469 if (vaddr == NULL) {
7470 rc = -ENOMEM;
7471 goto out_disable;
7472 }
7473 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
7474 iounmap(vaddr);
7475
1df8552a 7476 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 7477 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 7478
1df8552a
SC		 7479 /* -ENOTSUPP here means we cannot reset the controller
7480 * but it's already (and still) up and running in
18867659
SC		 7481 * "performant mode". Or, it might be 640x, which can't reset
7482 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 7483 */
adf1b3a3 7484 if (rc)
132aa220 7485 goto out_disable;
4c2a8c40
SC		 7486
7487 /* Now try to get the controller to respond to a no-op */
1ba66c9c 7488 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 7489 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
7490 if (hpsa_noop(pdev) == 0)
7491 break;
7492 else
7493 dev_warn(&pdev->dev, "no-op failed%s\n",
7494 (i < 11 ? "; re-trying" : ""));
7495 }
132aa220
TH		 7496
7497out_disable:
7498
7499 pci_disable_device(pdev);
7500 return rc;
4c2a8c40
SC		 7501}
7502
1fb7c98a
RE		 7503static void hpsa_free_cmd_pool(struct ctlr_info *h)
7504{
7505 kfree(h->cmd_pool_bits);
105a3dbc
RE		 7506 h->cmd_pool_bits = NULL;
7507 if (h->cmd_pool) {
1fb7c98a
RE		 7508 pci_free_consistent(h->pdev,
7509 h->nr_cmds * sizeof(struct CommandList),
7510 h->cmd_pool,
7511 h->cmd_pool_dhandle);
105a3dbc
RE		 7512 h->cmd_pool = NULL;
7513 h->cmd_pool_dhandle = 0;
7514 }
7515 if (h->errinfo_pool) {
1fb7c98a
RE		 7516 pci_free_consistent(h->pdev,
7517 h->nr_cmds * sizeof(struct ErrorInfo),
7518 h->errinfo_pool,
7519 h->errinfo_pool_dhandle);
105a3dbc
RE		 7520 h->errinfo_pool = NULL;
7521 h->errinfo_pool_dhandle = 0;
7522 }
1fb7c98a
RE		 7523}
7524
d37ffbe4 7525static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 7526{
7527 h->cmd_pool_bits = kzalloc(
7528 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
7529 sizeof(unsigned long), GFP_KERNEL);
7530 h->cmd_pool = pci_alloc_consistent(h->pdev,
7531 h->nr_cmds * sizeof(*h->cmd_pool),
7532 &(h->cmd_pool_dhandle));
7533 h->errinfo_pool = pci_alloc_consistent(h->pdev,
7534 h->nr_cmds * sizeof(*h->errinfo_pool),
7535 &(h->errinfo_pool_dhandle));
7536 if ((h->cmd_pool_bits == NULL)
7537 || (h->cmd_pool == NULL)
7538 || (h->errinfo_pool == NULL)) {
7539 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 7540 goto clean_up;
2e9d1b36 7541 }
360c73bd 7542 hpsa_preinitialize_commands(h);
2e9d1b36 7543 return 0;
2c143342
RE		 7544clean_up:
7545 hpsa_free_cmd_pool(h);
7546 return -ENOMEM;
2e9d1b36
SC		 7547}
7548
41b3cf08
SC		 7549static void hpsa_irq_affinity_hints(struct ctlr_info *h)
7550{
ec429952 7551 int i, cpu;
41b3cf08
SC		 7552
7553 cpu = cpumask_first(cpu_online_mask);
7554 for (i = 0; i < h->msix_vector; i++) {
ec429952 7555 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 7556 cpu = cpumask_next(cpu, cpu_online_mask);
7557 }
7558}
7559
ec501a18
RE		 7560/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
7561static void hpsa_free_irqs(struct ctlr_info *h)
7562{
7563 int i;
7564
7565 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
7566 /* Single reply queue, only one irq to free */
7567 i = h->intr_mode;
7568 irq_set_affinity_hint(h->intr[i], NULL);
7569 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7570 h->q[i] = 0;
ec501a18
RE		 7571 return;
7572 }
7573
7574 for (i = 0; i < h->msix_vector; i++) {
7575 irq_set_affinity_hint(h->intr[i], NULL);
7576 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7577 h->q[i] = 0;
ec501a18 7578 }
a4e17fc1
RE		 7579 for (; i < MAX_REPLY_QUEUES; i++)
7580 h->q[i] = 0;
ec501a18
RE		 7581}
7582
9ee61794
RE		 7583/* returns 0 on success; cleans up and returns -Enn on error */
7584static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 7585 irqreturn_t (*msixhandler)(int, void *),
7586 irqreturn_t (*intxhandler)(int, void *))
7587{
254f796b 7588 int rc, i;
0ae01a32 7589
254f796b
MG		 7590 /*
7591 * initialize h->q[x] = x so that interrupt handlers know which
7592 * queue to process.
7593 */
7594 for (i = 0; i < MAX_REPLY_QUEUES; i++)
7595 h->q[i] = (u8) i;
7596
eee0f03a 7597 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 7598 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 7599 for (i = 0; i < h->msix_vector; i++) {
8b47004a 7600 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
254f796b 7601 rc = request_irq(h->intr[i], msixhandler,
8b47004a 7602 0, h->intrname[i],
254f796b 7603 &h->q[i]);
a4e17fc1
RE		 7604 if (rc) {
7605 int j;
7606
7607 dev_err(&h->pdev->dev,
7608 "failed to get irq %d for %s\n",
7609 h->intr[i], h->devname);
7610 for (j = 0; j < i; j++) {
7611 free_irq(h->intr[j], &h->q[j]);
7612 h->q[j] = 0;
7613 }
7614 for (; j < MAX_REPLY_QUEUES; j++)
7615 h->q[j] = 0;
7616 return rc;
7617 }
7618 }
41b3cf08 7619 hpsa_irq_affinity_hints(h);
254f796b
MG		 7620 } else {
7621 /* Use single reply pool */
eee0f03a 7622 if (h->msix_vector > 0 || h->msi_vector) {
8b47004a
RE		 7623 if (h->msix_vector)
7624 sprintf(h->intrname[h->intr_mode],
7625 "%s-msix", h->devname);
7626 else
7627 sprintf(h->intrname[h->intr_mode],
7628 "%s-msi", h->devname);
254f796b 7629 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7630 msixhandler, 0,
7631 h->intrname[h->intr_mode],
254f796b
MG		 7632 &h->q[h->intr_mode]);
7633 } else {
8b47004a
RE		 7634 sprintf(h->intrname[h->intr_mode],
7635 "%s-intx", h->devname);
254f796b 7636 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7637 intxhandler, IRQF_SHARED,
7638 h->intrname[h->intr_mode],
254f796b
MG		 7639 &h->q[h->intr_mode]);
7640 }
105a3dbc 7641 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
254f796b 7642 }
0ae01a32 7643 if (rc) {
195f2c65 7644 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 7645 h->intr[h->intr_mode], h->devname);
195f2c65 7646 hpsa_free_irqs(h);
0ae01a32
SC		 7647 return -ENODEV;
7648 }
7649 return 0;
7650}
7651
6f039790 7652static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8 7653{
39c53f55 7654 int rc;
bf43caf3 7655 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
64670ac8
SC		 7656
7657 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
39c53f55
RE		 7658 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
7659 if (rc) {
64670ac8 7660 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
39c53f55 7661 return rc;
64670ac8
SC		 7662 }
7663
7664 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
39c53f55
RE		 7665 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
7666 if (rc) {
64670ac8
SC		 7667 dev_warn(&h->pdev->dev, "Board failed to become ready "
7668 "after soft reset.\n");
39c53f55 7669 return rc;
64670ac8
SC		 7670 }
7671
7672 return 0;
7673}
7674
072b0518
SC		 7675static void hpsa_free_reply_queues(struct ctlr_info *h)
7676{
7677 int i;
7678
7679 for (i = 0; i < h->nreply_queues; i++) {
7680 if (!h->reply_queue[i].head)
7681 continue;
1fb7c98a
RE		 7682 pci_free_consistent(h->pdev,
7683 h->reply_queue_size,
7684 h->reply_queue[i].head,
7685 h->reply_queue[i].busaddr);
072b0518
SC		 7686 h->reply_queue[i].head = NULL;
7687 h->reply_queue[i].busaddr = 0;
7688 }
105a3dbc 7689 h->reply_queue_size = 0;
072b0518
SC		 7690}
7691
0097f0f4
SC		 7692static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
7693{
105a3dbc
RE		 7694 hpsa_free_performant_mode(h); /* init_one 7 */
7695 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
7696 hpsa_free_cmd_pool(h); /* init_one 5 */
7697 hpsa_free_irqs(h); /* init_one 4 */
2946e82b
RE		 7698 scsi_host_put(h->scsi_host); /* init_one 3 */
7699 h->scsi_host = NULL; /* init_one 3 */
7700 hpsa_free_pci_init(h); /* init_one 2_5 */
9ecd953a
RE		 7701 free_percpu(h->lockup_detected); /* init_one 2 */
7702 h->lockup_detected = NULL; /* init_one 2 */
7703 if (h->resubmit_wq) {
7704 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
7705 h->resubmit_wq = NULL;
7706 }
7707 if (h->rescan_ctlr_wq) {
7708 destroy_workqueue(h->rescan_ctlr_wq);
7709 h->rescan_ctlr_wq = NULL;
7710 }
105a3dbc 7711 kfree(h); /* init_one 1 */
64670ac8
SC		 7712}
7713
a0c12413 7714/* Called when controller lockup detected. */
f2405db8 7715static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 7716{
281a7fd0
WS		 7717 int i, refcount;
7718 struct CommandList *c;
25163bd5 7719 int failcount = 0;
a0c12413 7720
080ef1cc 7721 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 7722 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7723 c = h->cmd_pool + i;
281a7fd0
WS		 7724 refcount = atomic_inc_return(&c->refcount);
7725 if (refcount > 1) {
25163bd5 7726 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 7727 finish_cmd(c);
433b5f4d 7728 atomic_dec(&h->commands_outstanding);
25163bd5 7729 failcount++;
281a7fd0
WS		 7730 }
7731 cmd_free(h, c);
a0c12413 7732 }
25163bd5
WS		 7733 dev_warn(&h->pdev->dev,
7734 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 7735}
7736
094963da
SC		 7737static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
7738{
c8ed0010 7739 int cpu;
094963da 7740
c8ed0010 7741 for_each_online_cpu(cpu) {
094963da
SC		 7742 u32 *lockup_detected;
7743 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
7744 *lockup_detected = value;
094963da
SC		 7745 }
7746 wmb(); /* be sure the per-cpu variables are out to memory */
7747}
7748
a0c12413
SC		 7749static void controller_lockup_detected(struct ctlr_info *h)
7750{
7751 unsigned long flags;
094963da 7752 u32 lockup_detected;
a0c12413 7753
a0c12413
SC		 7754 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7755 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 7756 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
7757 if (!lockup_detected) {
7758 /* no heartbeat, but controller gave us a zero. */
7759 dev_warn(&h->pdev->dev,
25163bd5
WS		 7760 "lockup detected after %d but scratchpad register is zero\n",
7761 h->heartbeat_sample_interval / HZ);
094963da
SC		 7762 lockup_detected = 0xffffffff;
7763 }
7764 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 7765 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 7766 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
7767 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 7768 pci_disable_device(h->pdev);
f2405db8 7769 fail_all_outstanding_cmds(h);
a0c12413
SC		 7770}
7771
25163bd5 7772static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 7773{
7774 u64 now;
7775 u32 heartbeat;
7776 unsigned long flags;
7777
a0c12413
SC		 7778 now = get_jiffies_64();
7779 /* If we've received an interrupt recently, we're ok. */
7780 if (time_after64(h->last_intr_timestamp +
e85c5974 7781 (h->heartbeat_sample_interval), now))
25163bd5 7782 return false;
a0c12413
SC		 7783
7784 /*
7785 * If we've already checked the heartbeat recently, we're ok.
7786 * This could happen if someone sends us a signal. We
7787 * otherwise don't care about signals in this thread.
7788 */
7789 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 7790 (h->heartbeat_sample_interval), now))
25163bd5 7791 return false;
a0c12413
SC		 7792
7793 /* If heartbeat has not changed since we last looked, we're not ok. */
7794 spin_lock_irqsave(&h->lock, flags);
7795 heartbeat = readl(&h->cfgtable->HeartBeat);
7796 spin_unlock_irqrestore(&h->lock, flags);
7797 if (h->last_heartbeat == heartbeat) {
7798 controller_lockup_detected(h);
25163bd5 7799 return true;
a0c12413
SC		 7800 }
7801
7802 /* We're ok. */
7803 h->last_heartbeat = heartbeat;
7804 h->last_heartbeat_timestamp = now;
25163bd5 7805 return false;
a0c12413
SC		 7806}
7807
9846590e 7808static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 7809{
7810 int i;
7811 char *event_type;
7812
e4aa3e6a
SC		 7813 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7814 return;
7815
76438d08 7816 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 7817 if ((h->transMethod & (CFGTBL_Trans_io_accel1
7818 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 7819 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
7820 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
7821
7822 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
7823 event_type = "state change";
7824 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
7825 event_type = "configuration change";
7826 /* Stop sending new RAID offload reqs via the IO accelerator */
7827 scsi_block_requests(h->scsi_host);
7828 for (i = 0; i < h->ndevices; i++)
7829 h->dev[i]->offload_enabled = 0;
23100dd9 7830 hpsa_drain_accel_commands(h);
76438d08
SC		 7831 /* Set 'accelerator path config change' bit */
7832 dev_warn(&h->pdev->dev,
7833 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7834 h->events, event_type);
7835 writel(h->events, &(h->cfgtable->clear_event_notify));
7836 /* Set the "clear event notify field update" bit 6 */
7837 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7838 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7839 hpsa_wait_for_clear_event_notify_ack(h);
7840 scsi_unblock_requests(h->scsi_host);
7841 } else {
7842 /* Acknowledge controller notification events. */
7843 writel(h->events, &(h->cfgtable->clear_event_notify));
7844 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7845 hpsa_wait_for_clear_event_notify_ack(h);
7846#if 0
7847 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7848 hpsa_wait_for_mode_change_ack(h);
7849#endif
7850 }
9846590e 7851 return;
76438d08
SC		 7852}
7853
7854/* Check a register on the controller to see if there are configuration
7855 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 7856 * we should rescan the controller for devices.
7857 * Also check flag for driver-initiated rescan.
76438d08 7858 */
9846590e 7859static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08
SC		 7860{
7861 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 7862 return 0;
76438d08
SC		 7863
7864 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 7865 return h->events & RESCAN_REQUIRED_EVENT_BITS;
7866}
76438d08 7867
9846590e
SC		 7868/*
7869 * Check if any of the offline devices have become ready
7870 */
7871static int hpsa_offline_devices_ready(struct ctlr_info *h)
7872{
7873 unsigned long flags;
7874 struct offline_device_entry *d;
7875 struct list_head *this, *tmp;
7876
7877 spin_lock_irqsave(&h->offline_device_lock, flags);
7878 list_for_each_safe(this, tmp, &h->offline_device_list) {
7879 d = list_entry(this, struct offline_device_entry,
7880 offline_list);
7881 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 7882 if (!hpsa_volume_offline(h, d->scsi3addr)) {
7883 spin_lock_irqsave(&h->offline_device_lock, flags);
7884 list_del(&d->offline_list);
7885 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 7886 return 1;
d1fea47c 7887 }
9846590e
SC		 7888 spin_lock_irqsave(&h->offline_device_lock, flags);
7889 }
7890 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7891 return 0;
76438d08
SC		 7892}
7893
6636e7f4 7894static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 7895{
7896 unsigned long flags;
8a98db73 7897 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 7898 struct ctlr_info, rescan_ctlr_work);
7899
7900
7901 if (h->remove_in_progress)
8a98db73 7902 return;
9846590e
SC		 7903
7904 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
7905 scsi_host_get(h->scsi_host);
9846590e
SC		 7906 hpsa_ack_ctlr_events(h);
7907 hpsa_scan_start(h->scsi_host);
7908 scsi_host_put(h->scsi_host);
7909 }
8a98db73 7910 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 7911 if (!h->remove_in_progress)
7912 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7913 h->heartbeat_sample_interval);
7914 spin_unlock_irqrestore(&h->lock, flags);
7915}
7916
7917static void hpsa_monitor_ctlr_worker(struct work_struct *work)
7918{
7919 unsigned long flags;
7920 struct ctlr_info *h = container_of(to_delayed_work(work),
7921 struct ctlr_info, monitor_ctlr_work);
7922
7923 detect_controller_lockup(h);
7924 if (lockup_detected(h))
a0c12413 7925 return;
6636e7f4
DB		 7926
7927 spin_lock_irqsave(&h->lock, flags);
7928 if (!h->remove_in_progress)
7929 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 7930 h->heartbeat_sample_interval);
7931 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 7932}
7933
6636e7f4
DB		 7934static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
7935 char *name)
7936{
7937 struct workqueue_struct *wq = NULL;
6636e7f4 7938
397ea9cb 7939 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 7940 if (!wq)
7941 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
7942
7943 return wq;
7944}
7945
6f039790 7946static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 7947{
4c2a8c40 7948 int dac, rc;
edd16368 7949 struct ctlr_info *h;
64670ac8
SC		 7950 int try_soft_reset = 0;
7951 unsigned long flags;
6b6c1cd7 7952 u32 board_id;
edd16368
SC		 7953
7954 if (number_of_controllers == 0)
7955 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 7956
6b6c1cd7
TH		 7957 rc = hpsa_lookup_board_id(pdev, &board_id);
7958 if (rc < 0) {
7959 dev_warn(&pdev->dev, "Board ID not found\n");
7960 return rc;
7961 }
7962
7963 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 7964 if (rc) {
7965 if (rc != -ENOTSUPP)
7966 return rc;
7967 /* If the reset fails in a particular way (it has no way to do
7968 * a proper hard reset, so returns -ENOTSUPP) we can try to do
7969 * a soft reset once we get the controller configured up to the
7970 * point that it can accept a command.
7971 */
7972 try_soft_reset = 1;
7973 rc = 0;
7974 }
7975
7976reinit_after_soft_reset:
edd16368 7977
303932fd
DB		 7978 /* Command structures must be aligned on a 32-byte boundary because
7979 * the 5 lower bits of the address are used by the hardware. and by
7980 * the driver. See comments in hpsa.h for more info.
7981 */
303932fd 7982 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368 7983 h = kzalloc(sizeof(*h), GFP_KERNEL);
105a3dbc
RE		 7984 if (!h) {
7985 dev_err(&pdev->dev, "Failed to allocate controller head\n");
ecd9aad4 7986 return -ENOMEM;
105a3dbc 7987 }
edd16368 7988
55c06c71 7989 h->pdev = pdev;
105a3dbc 7990
a9a3a273 7991 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 7992 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 7993 spin_lock_init(&h->lock);
9846590e 7994 spin_lock_init(&h->offline_device_lock);
6eaf46fd 7995 spin_lock_init(&h->scan_lock);
34f0c627 7996 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 7997 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da
SC		 7998
7999 /* Allocate and clear per-cpu variable lockup_detected */
8000 h->lockup_detected = alloc_percpu(u32);
2a5ac326 8001 if (!h->lockup_detected) {
105a3dbc 8002 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
2a5ac326 8003 rc = -ENOMEM;
2efa5929 8004 goto clean1; /* aer/h */
2a5ac326 8005 }
094963da
SC		 8006 set_lockup_detected_for_all_cpus(h, 0);
8007
55c06c71 8008 rc = hpsa_pci_init(h);
105a3dbc 8009 if (rc)
2946e82b
RE		 8010 goto clean2; /* lu, aer/h */
8011
8012 /* relies on h-> settings made by hpsa_pci_init, including
8013 * interrupt_mode h->intr */
8014 rc = hpsa_scsi_host_alloc(h);
8015 if (rc)
8016 goto clean2_5; /* pci, lu, aer/h */
edd16368 8017
2946e82b 8018 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
edd16368
SC		 8019 h->ctlr = number_of_controllers;
8020 number_of_controllers++;
edd16368
SC		 8021
8022 /* configure PCI DMA stuff */
ecd9aad4
SC		 8023 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
8024 if (rc == 0) {
edd16368 8025 dac = 1;
ecd9aad4
SC		 8026 } else {
8027 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8028 if (rc == 0) {
8029 dac = 0;
8030 } else {
8031 dev_err(&pdev->dev, "no suitable DMA available\n");
2946e82b 8032 goto clean3; /* shost, pci, lu, aer/h */
ecd9aad4 8033 }
edd16368
SC		 8034 }
8035
8036 /* make sure the board interrupts are off */
8037 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 8038
105a3dbc
RE		 8039 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
8040 if (rc)
2946e82b 8041 goto clean3; /* shost, pci, lu, aer/h */
d37ffbe4 8042 rc = hpsa_alloc_cmd_pool(h);
8947fd10 8043 if (rc)
2946e82b 8044 goto clean4; /* irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8045 rc = hpsa_alloc_sg_chain_blocks(h);
8046 if (rc)
2946e82b 8047 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
a08a8471 8048 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 8049 init_waitqueue_head(&h->abort_cmd_wait_queue);
d604f533
WS		 8050 init_waitqueue_head(&h->event_sync_wait_queue);
8051 mutex_init(&h->reset_mutex);
a08a8471 8052 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 8053
8054 pci_set_drvdata(pdev, h);
9a41338e 8055 h->ndevices = 0;
2946e82b 8056
9a41338e 8057 spin_lock_init(&h->devlock);
105a3dbc
RE		 8058 rc = hpsa_put_ctlr_into_performant_mode(h);
8059 if (rc)
2946e82b
RE		 8060 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8061
8062 /* hook into SCSI subsystem */
8063 rc = hpsa_scsi_add_host(h);
8064 if (rc)
8065 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
2efa5929
RE		 8066
8067 /* create the resubmit workqueue */
8068 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8069 if (!h->rescan_ctlr_wq) {
8070 rc = -ENOMEM;
8071 goto clean7;
8072 }
8073
8074 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8075 if (!h->resubmit_wq) {
8076 rc = -ENOMEM;
8077 goto clean7; /* aer/h */
8078 }
64670ac8 8079
105a3dbc
RE		 8080 /*
8081 * At this point, the controller is ready to take commands.
64670ac8
SC		 8082 * Now, if reset_devices and the hard reset didn't work, try
8083 * the soft reset and see if that works.
8084 */
8085 if (try_soft_reset) {
8086
8087 /* This is kind of gross. We may or may not get a completion
8088 * from the soft reset command, and if we do, then the value
8089 * from the fifo may or may not be valid. So, we wait 10 secs
8090 * after the reset throwing away any completions we get during
8091 * that time. Unregister the interrupt handler and register
8092 * fake ones to scoop up any residual completions.
8093 */
8094 spin_lock_irqsave(&h->lock, flags);
8095 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8096 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 8097 hpsa_free_irqs(h);
9ee61794 8098 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 8099 hpsa_intx_discard_completions);
8100 if (rc) {
9ee61794
RE		 8101 dev_warn(&h->pdev->dev,
8102 "Failed to request_irq after soft reset.\n");
d498757c 8103 /*
b2ef480c
RE		 8104 * cannot goto clean7 or free_irqs will be called
8105 * again. Instead, do its work
8106 */
8107 hpsa_free_performant_mode(h); /* clean7 */
8108 hpsa_free_sg_chain_blocks(h); /* clean6 */
8109 hpsa_free_cmd_pool(h); /* clean5 */
8110 /*
8111 * skip hpsa_free_irqs(h) clean4 since that
8112 * was just called before request_irqs failed
d498757c
RE		 8113 */
8114 goto clean3;
64670ac8
SC		 8115 }
8116
8117 rc = hpsa_kdump_soft_reset(h);
8118 if (rc)
8119 /* Neither hard nor soft reset worked, we're hosed. */
7ef7323f 8120 goto clean7;
64670ac8
SC		 8121
8122 dev_info(&h->pdev->dev, "Board READY.\n");
8123 dev_info(&h->pdev->dev,
8124 "Waiting for stale completions to drain.\n");
8125 h->access.set_intr_mask(h, HPSA_INTR_ON);
8126 msleep(10000);
8127 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8128
8129 rc = controller_reset_failed(h->cfgtable);
8130 if (rc)
8131 dev_info(&h->pdev->dev,
8132 "Soft reset appears to have failed.\n");
8133
8134 /* since the controller's reset, we have to go back and re-init
8135 * everything. Easiest to just forget what we've done and do it
8136 * all over again.
8137 */
8138 hpsa_undo_allocations_after_kdump_soft_reset(h);
8139 try_soft_reset = 0;
8140 if (rc)
b2ef480c 8141 /* don't goto clean, we already unallocated */
64670ac8
SC		 8142 return -ENODEV;
8143
8144 goto reinit_after_soft_reset;
8145 }
edd16368 8146
105a3dbc
RE		 8147 /* Enable Accelerated IO path at driver layer */
8148 h->acciopath_status = 1;
da0697bd 8149
e863d68e 8150
edd16368
SC		 8151 /* Turn the interrupts on so we can service requests */
8152 h->access.set_intr_mask(h, HPSA_INTR_ON);
8153
339b2b14 8154 hpsa_hba_inquiry(h);
8a98db73
SC		 8155
8156 /* Monitor the controller for firmware lockups */
8157 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8158 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8159 schedule_delayed_work(&h->monitor_ctlr_work,
8160 h->heartbeat_sample_interval);
6636e7f4
DB		 8161 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8162 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8163 h->heartbeat_sample_interval);
88bf6d62 8164 return 0;
edd16368 8165
2946e82b 8166clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8167 hpsa_free_performant_mode(h);
8168 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8169clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
33a2ffce 8170 hpsa_free_sg_chain_blocks(h);
2946e82b 8171clean5: /* cmd, irq, shost, pci, lu, aer/h */
2e9d1b36 8172 hpsa_free_cmd_pool(h);
2946e82b 8173clean4: /* irq, shost, pci, lu, aer/h */
ec501a18 8174 hpsa_free_irqs(h);
2946e82b
RE		 8175clean3: /* shost, pci, lu, aer/h */
8176 scsi_host_put(h->scsi_host);
8177 h->scsi_host = NULL;
8178clean2_5: /* pci, lu, aer/h */
195f2c65 8179 hpsa_free_pci_init(h);
2946e82b 8180clean2: /* lu, aer/h */
105a3dbc
RE		 8181 if (h->lockup_detected) {
8182 free_percpu(h->lockup_detected);
8183 h->lockup_detected = NULL;
8184 }
8185clean1: /* wq/aer/h */
8186 if (h->resubmit_wq) {
080ef1cc 8187 destroy_workqueue(h->resubmit_wq);
105a3dbc
RE		 8188 h->resubmit_wq = NULL;
8189 }
8190 if (h->rescan_ctlr_wq) {
6636e7f4 8191 destroy_workqueue(h->rescan_ctlr_wq);
105a3dbc
RE		 8192 h->rescan_ctlr_wq = NULL;
8193 }
edd16368 8194 kfree(h);
ecd9aad4 8195 return rc;
edd16368
SC		 8196}
8197
8198static void hpsa_flush_cache(struct ctlr_info *h)
8199{
8200 char *flush_buf;
8201 struct CommandList *c;
25163bd5 8202 int rc;
702890e3 8203
094963da 8204 if (unlikely(lockup_detected(h)))
702890e3 8205 return;
edd16368
SC		 8206 flush_buf = kzalloc(4, GFP_KERNEL);
8207 if (!flush_buf)
8208 return;
8209
45fcb86e 8210 c = cmd_alloc(h);
bf43caf3 8211
a2dac136
SC		 8212 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8213 RAID_CTLR_LUNID, TYPE_CMD)) {
8214 goto out;
8215 }
25163bd5
WS		 8216 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8217 PCI_DMA_TODEVICE, NO_TIMEOUT);
8218 if (rc)
8219 goto out;
edd16368 8220 if (c->err_info->CommandStatus != 0)
a2dac136 8221out:
edd16368
SC		 8222 dev_warn(&h->pdev->dev,
8223 "error flushing cache on controller\n");
45fcb86e 8224 cmd_free(h, c);
edd16368
SC		 8225 kfree(flush_buf);
8226}
8227
8228static void hpsa_shutdown(struct pci_dev *pdev)
8229{
8230 struct ctlr_info *h;
8231
8232 h = pci_get_drvdata(pdev);
8233 /* Turn board interrupts off and send the flush cache command
8234 * sendcmd will turn off interrupt, and send the flush...
8235 * To write all data in the battery backed cache to disks
8236 */
8237 hpsa_flush_cache(h);
8238 h->access.set_intr_mask(h, HPSA_INTR_OFF);
105a3dbc 8239 hpsa_free_irqs(h); /* init_one 4 */
cc64c817 8240 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 8241}
8242
6f039790 8243static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 8244{
8245 int i;
8246
105a3dbc 8247 for (i = 0; i < h->ndevices; i++) {
55e14e76 8248 kfree(h->dev[i]);
105a3dbc
RE		 8249 h->dev[i] = NULL;
8250 }
55e14e76
SC		 8251}
8252
6f039790 8253static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 8254{
8255 struct ctlr_info *h;
8a98db73 8256 unsigned long flags;
edd16368
SC		 8257
8258 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 8259 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 8260 return;
8261 }
8262 h = pci_get_drvdata(pdev);
8a98db73
SC		 8263
8264 /* Get rid of any controller monitoring work items */
8265 spin_lock_irqsave(&h->lock, flags);
8266 h->remove_in_progress = 1;
8a98db73 8267 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 8268 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8269 cancel_delayed_work_sync(&h->rescan_ctlr_work);
8270 destroy_workqueue(h->rescan_ctlr_wq);
8271 destroy_workqueue(h->resubmit_wq);
cc64c817 8272
105a3dbc 8273 /* includes hpsa_free_irqs - init_one 4 */
195f2c65 8274 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 8275 hpsa_shutdown(pdev);
cc64c817 8276
105a3dbc
RE		 8277 hpsa_free_device_info(h); /* scan */
8278
2946e82b
RE		 8279 kfree(h->hba_inquiry_data); /* init_one 10 */
8280 h->hba_inquiry_data = NULL; /* init_one 10 */
8281 if (h->scsi_host)
8282 scsi_remove_host(h->scsi_host); /* init_one 8 */
8283 hpsa_free_ioaccel2_sg_chain_blocks(h);
105a3dbc
RE		 8284 hpsa_free_performant_mode(h); /* init_one 7 */
8285 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8286 hpsa_free_cmd_pool(h); /* init_one 5 */
8287
8288 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
195f2c65 8289
2946e82b
RE		 8290 scsi_host_put(h->scsi_host); /* init_one 3 */
8291 h->scsi_host = NULL; /* init_one 3 */
8292
195f2c65 8293 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
2946e82b 8294 hpsa_free_pci_init(h); /* init_one 2.5 */
195f2c65 8295
105a3dbc
RE		 8296 free_percpu(h->lockup_detected); /* init_one 2 */
8297 h->lockup_detected = NULL; /* init_one 2 */
8298 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
8299 kfree(h); /* init_one 1 */
edd16368
SC		 8300}
8301
8302static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8303 __attribute__((unused)) pm_message_t state)
8304{
8305 return -ENOSYS;
8306}
8307
8308static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8309{
8310 return -ENOSYS;
8311}
8312
8313static struct pci_driver hpsa_pci_driver = {
f79cfec6 8314 .name = HPSA,
edd16368 8315 .probe = hpsa_init_one,
6f039790 8316 .remove = hpsa_remove_one,
edd16368
SC		 8317 .id_table = hpsa_pci_device_id, /* id_table */
8318 .shutdown = hpsa_shutdown,
8319 .suspend = hpsa_suspend,
8320 .resume = hpsa_resume,
8321};
8322
303932fd
DB		 8323/* Fill in bucket_map[], given nsgs (the max number of
8324 * scatter gather elements supported) and bucket[],
8325 * which is an array of 8 integers. The bucket[] array
8326 * contains 8 different DMA transfer sizes (in 16
8327 * byte increments) which the controller uses to fetch
8328 * commands. This function fills in bucket_map[], which
8329 * maps a given number of scatter gather elements to one of
8330 * the 8 DMA transfer sizes. The point of it is to allow the
8331 * controller to only do as much DMA as needed to fetch the
8332 * command, with the DMA transfer size encoded in the lower
8333 * bits of the command address.
8334 */
8335static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 8336 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 8337{
8338 int i, j, b, size;
8339
303932fd
DB		 8340 /* Note, bucket_map must have nsgs+1 entries. */
8341 for (i = 0; i <= nsgs; i++) {
8342 /* Compute size of a command with i SG entries */
e1f7de0c 8343 size = i + min_blocks;
303932fd
DB		 8344 b = num_buckets; /* Assume the biggest bucket */
8345 /* Find the bucket that is just big enough */
e1f7de0c 8346 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 8347 if (bucket[j] >= size) {
8348 b = j;
8349 break;
8350 }
8351 }
8352 /* for a command with i SG entries, use bucket b. */
8353 bucket_map[i] = b;
8354 }
8355}
8356
105a3dbc
RE		 8357/*
8358 * return -ENODEV on err, 0 on success (or no action)
8359 * allocates numerous items that must be freed later
8360 */
c706a795 8361static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 8362{
6c311b57
SC		 8363 int i;
8364 unsigned long register_value;
e1f7de0c
MG		 8365 unsigned long transMethod = CFGTBL_Trans_Performant |
8366 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 8367 CFGTBL_Trans_enable_directed_msix |
8368 (trans_support & (CFGTBL_Trans_io_accel1 |
8369 CFGTBL_Trans_io_accel2));
e1f7de0c 8370 struct access_method access = SA5_performant_access;
def342bd
SC		 8371
8372 /* This is a bit complicated. There are 8 registers on
8373 * the controller which we write to to tell it 8 different
8374 * sizes of commands which there may be. It's a way of
8375 * reducing the DMA done to fetch each command. Encoded into
8376 * each command's tag are 3 bits which communicate to the controller
8377 * which of the eight sizes that command fits within. The size of
8378 * each command depends on how many scatter gather entries there are.
8379 * Each SG entry requires 16 bytes. The eight registers are programmed
8380 * with the number of 16-byte blocks a command of that size requires.
8381 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 8382 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 8383 * blocks. Note, this only extends to the SG entries contained
8384 * within the command block, and does not extend to chained blocks
8385 * of SG elements. bft[] contains the eight values we write to
8386 * the registers. They are not evenly distributed, but have more
8387 * sizes for small commands, and fewer sizes for larger commands.
8388 */
d66ae08b 8389 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 8390#define MIN_IOACCEL2_BFT_ENTRY 5
8391#define HPSA_IOACCEL2_HEADER_SZ 4
8392 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
8393 13, 14, 15, 16, 17, 18, 19,
8394 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
8395 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
8396 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
8397 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
8398 16 * MIN_IOACCEL2_BFT_ENTRY);
8399 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 8400 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 8401 /* 5 = 1 s/g entry or 4k
8402 * 6 = 2 s/g entry or 8k
8403 * 8 = 4 s/g entry or 16k
8404 * 10 = 6 s/g entry or 24k
8405 */
303932fd 8406
b3a52e79
SC		 8407 /* If the controller supports either ioaccel method then
8408 * we can also use the RAID stack submit path that does not
8409 * perform the superfluous readl() after each command submission.
8410 */
8411 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
8412 access = SA5_performant_access_no_read;
8413
303932fd 8414 /* Controller spec: zero out this buffer. */
072b0518
SC		 8415 for (i = 0; i < h->nreply_queues; i++)
8416 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 8417
d66ae08b
SC		 8418 bft[7] = SG_ENTRIES_IN_CMD + 4;
8419 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 8420 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 8421 for (i = 0; i < 8; i++)
8422 writel(bft[i], &h->transtable->BlockFetch[i]);
8423
8424 /* size of controller ring buffer */
8425 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 8426 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 8427 writel(0, &h->transtable->RepQCtrAddrLow32);
8428 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 8429
8430 for (i = 0; i < h->nreply_queues; i++) {
8431 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 8432 writel(h->reply_queue[i].busaddr,
254f796b
MG		 8433 &h->transtable->RepQAddr[i].lower);
8434 }
8435
b9af4937 8436 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 8437 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
8438 /*
8439 * enable outbound interrupt coalescing in accelerator mode;
8440 */
8441 if (trans_support & CFGTBL_Trans_io_accel1) {
8442 access = SA5_ioaccel_mode1_access;
8443 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8444 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 8445 } else {
8446 if (trans_support & CFGTBL_Trans_io_accel2) {
8447 access = SA5_ioaccel_mode2_access;
8448 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8449 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
8450 }
e1f7de0c 8451 }
303932fd 8452 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8453 if (hpsa_wait_for_mode_change_ack(h)) {
8454 dev_err(&h->pdev->dev,
8455 "performant mode problem - doorbell timeout\n");
8456 return -ENODEV;
8457 }
303932fd
DB		 8458 register_value = readl(&(h->cfgtable->TransportActive));
8459 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 8460 dev_err(&h->pdev->dev,
8461 "performant mode problem - transport not active\n");
c706a795 8462 return -ENODEV;
303932fd 8463 }
960a30e7 8464 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 8465 h->access = access;
8466 h->transMethod = transMethod;
8467
b9af4937
SC		 8468 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
8469 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 8470 return 0;
e1f7de0c 8471
b9af4937
SC		 8472 if (trans_support & CFGTBL_Trans_io_accel1) {
8473 /* Set up I/O accelerator mode */
8474 for (i = 0; i < h->nreply_queues; i++) {
8475 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
8476 h->reply_queue[i].current_entry =
8477 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
8478 }
8479 bft[7] = h->ioaccel_maxsg + 8;
8480 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
8481 h->ioaccel1_blockFetchTable);
e1f7de0c 8482
b9af4937 8483 /* initialize all reply queue entries to unused */
072b0518
SC		 8484 for (i = 0; i < h->nreply_queues; i++)
8485 memset(h->reply_queue[i].head,
8486 (u8) IOACCEL_MODE1_REPLY_UNUSED,
8487 h->reply_queue_size);
e1f7de0c 8488
b9af4937
SC		 8489 /* set all the constant fields in the accelerator command
8490 * frames once at init time to save CPU cycles later.
8491 */
8492 for (i = 0; i < h->nr_cmds; i++) {
8493 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
8494
8495 cp->function = IOACCEL1_FUNCTION_SCSIIO;
8496 cp->err_info = (u32) (h->errinfo_pool_dhandle +
8497 (i * sizeof(struct ErrorInfo)));
8498 cp->err_info_len = sizeof(struct ErrorInfo);
8499 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 8500 cp->host_context_flags =
8501 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 8502 cp->timeout_sec = 0;
8503 cp->ReplyQueue = 0;
50a0decf 8504 cp->tag =
f2405db8 8505 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 8506 cp->host_addr =
8507 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 8508 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 8509 }
8510 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8511 u64 cfg_offset, cfg_base_addr_index;
8512 u32 bft2_offset, cfg_base_addr;
8513 int rc;
8514
8515 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
8516 &cfg_base_addr_index, &cfg_offset);
8517 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
8518 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
8519 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
8520 4, h->ioaccel2_blockFetchTable);
8521 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
8522 BUILD_BUG_ON(offsetof(struct CfgTable,
8523 io_accel_request_size_offset) != 0xb8);
8524 h->ioaccel2_bft2_regs =
8525 remap_pci_mem(pci_resource_start(h->pdev,
8526 cfg_base_addr_index) +
8527 cfg_offset + bft2_offset,
8528 ARRAY_SIZE(bft2) *
8529 sizeof(*h->ioaccel2_bft2_regs));
8530 for (i = 0; i < ARRAY_SIZE(bft2); i++)
8531 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 8532 }
b9af4937 8533 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8534 if (hpsa_wait_for_mode_change_ack(h)) {
8535 dev_err(&h->pdev->dev,
8536 "performant mode problem - enabling ioaccel mode\n");
8537 return -ENODEV;
8538 }
8539 return 0;
e1f7de0c
MG		 8540}
8541
1fb7c98a
RE		 8542/* Free ioaccel1 mode command blocks and block fetch table */
8543static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
8544{
105a3dbc 8545 if (h->ioaccel_cmd_pool) {
1fb7c98a
RE		 8546 pci_free_consistent(h->pdev,
8547 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8548 h->ioaccel_cmd_pool,
8549 h->ioaccel_cmd_pool_dhandle);
105a3dbc
RE		 8550 h->ioaccel_cmd_pool = NULL;
8551 h->ioaccel_cmd_pool_dhandle = 0;
8552 }
1fb7c98a 8553 kfree(h->ioaccel1_blockFetchTable);
105a3dbc 8554 h->ioaccel1_blockFetchTable = NULL;
1fb7c98a
RE		 8555}
8556
d37ffbe4
RE		 8557/* Allocate ioaccel1 mode command blocks and block fetch table */
8558static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 8559{
283b4a9b
SC		 8560 h->ioaccel_maxsg =
8561 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8562 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
8563 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
8564
e1f7de0c
MG		 8565 /* Command structures must be aligned on a 128-byte boundary
8566 * because the 7 lower bits of the address are used by the
8567 * hardware.
8568 */
e1f7de0c
MG		 8569 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
8570 IOACCEL1_COMMANDLIST_ALIGNMENT);
8571 h->ioaccel_cmd_pool =
8572 pci_alloc_consistent(h->pdev,
8573 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8574 &(h->ioaccel_cmd_pool_dhandle));
8575
8576 h->ioaccel1_blockFetchTable =
283b4a9b 8577 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 8578 sizeof(u32)), GFP_KERNEL);
8579
8580 if ((h->ioaccel_cmd_pool == NULL) ||
8581 (h->ioaccel1_blockFetchTable == NULL))
8582 goto clean_up;
8583
8584 memset(h->ioaccel_cmd_pool, 0,
8585 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
8586 return 0;
8587
8588clean_up:
1fb7c98a 8589 hpsa_free_ioaccel1_cmd_and_bft(h);
2dd02d74 8590 return -ENOMEM;
6c311b57
SC		 8591}
8592
1fb7c98a
RE		 8593/* Free ioaccel2 mode command blocks and block fetch table */
8594static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
8595{
d9a729f3
WS		 8596 hpsa_free_ioaccel2_sg_chain_blocks(h);
8597
105a3dbc 8598 if (h->ioaccel2_cmd_pool) {
1fb7c98a
RE		 8599 pci_free_consistent(h->pdev,
8600 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8601 h->ioaccel2_cmd_pool,
8602 h->ioaccel2_cmd_pool_dhandle);
105a3dbc
RE		 8603 h->ioaccel2_cmd_pool = NULL;
8604 h->ioaccel2_cmd_pool_dhandle = 0;
8605 }
1fb7c98a 8606 kfree(h->ioaccel2_blockFetchTable);
105a3dbc 8607 h->ioaccel2_blockFetchTable = NULL;
1fb7c98a
RE		 8608}
8609
d37ffbe4
RE		 8610/* Allocate ioaccel2 mode command blocks and block fetch table */
8611static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 8612{
d9a729f3
WS		 8613 int rc;
8614
aca9012a
SC		 8615 /* Allocate ioaccel2 mode command blocks and block fetch table */
8616
8617 h->ioaccel_maxsg =
8618 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8619 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
8620 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
8621
aca9012a
SC		 8622 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
8623 IOACCEL2_COMMANDLIST_ALIGNMENT);
8624 h->ioaccel2_cmd_pool =
8625 pci_alloc_consistent(h->pdev,
8626 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8627 &(h->ioaccel2_cmd_pool_dhandle));
8628
8629 h->ioaccel2_blockFetchTable =
8630 kmalloc(((h->ioaccel_maxsg + 1) *
8631 sizeof(u32)), GFP_KERNEL);
8632
8633 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 8634 (h->ioaccel2_blockFetchTable == NULL)) {
8635 rc = -ENOMEM;
8636 goto clean_up;
8637 }
8638
8639 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
8640 if (rc)
aca9012a
SC		 8641 goto clean_up;
8642
8643 memset(h->ioaccel2_cmd_pool, 0,
8644 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
8645 return 0;
8646
8647clean_up:
1fb7c98a 8648 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 8649 return rc;
aca9012a
SC		 8650}
8651
105a3dbc
RE		 8652/* Free items allocated by hpsa_put_ctlr_into_performant_mode */
8653static void hpsa_free_performant_mode(struct ctlr_info *h)
8654{
8655 kfree(h->blockFetchTable);
8656 h->blockFetchTable = NULL;
8657 hpsa_free_reply_queues(h);
8658 hpsa_free_ioaccel1_cmd_and_bft(h);
8659 hpsa_free_ioaccel2_cmd_and_bft(h);
8660}
8661
8662/* return -ENODEV on error, 0 on success (or no action)
8663 * allocates numerous items that must be freed later
8664 */
8665static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 8666{
8667 u32 trans_support;
e1f7de0c
MG		 8668 unsigned long transMethod = CFGTBL_Trans_Performant |
8669 CFGTBL_Trans_use_short_tags;
105a3dbc 8670 int i, rc;
6c311b57 8671
02ec19c8 8672 if (hpsa_simple_mode)
105a3dbc 8673 return 0;
02ec19c8 8674
67c99a72 8675 trans_support = readl(&(h->cfgtable->TransportSupport));
8676 if (!(trans_support & PERFORMANT_MODE))
105a3dbc 8677 return 0;
67c99a72 8678
e1f7de0c
MG		 8679 /* Check for I/O accelerator mode support */
8680 if (trans_support & CFGTBL_Trans_io_accel1) {
8681 transMethod |= CFGTBL_Trans_io_accel1 |
8682 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8683 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
8684 if (rc)
8685 return rc;
8686 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8687 transMethod |= CFGTBL_Trans_io_accel2 |
aca9012a 8688 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8689 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
8690 if (rc)
8691 return rc;
e1f7de0c
MG		 8692 }
8693
eee0f03a 8694 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 8695 hpsa_get_max_perf_mode_cmds(h);
6c311b57 8696 /* Performant mode ring buffer and supporting data structures */
072b0518 8697 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 8698
254f796b 8699 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 8700 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
8701 h->reply_queue_size,
8702 &(h->reply_queue[i].busaddr));
105a3dbc
RE		 8703 if (!h->reply_queue[i].head) {
8704 rc = -ENOMEM;
8705 goto clean1; /* rq, ioaccel */
8706 }
254f796b
MG		 8707 h->reply_queue[i].size = h->max_commands;
8708 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
8709 h->reply_queue[i].current_entry = 0;
8710 }
8711
6c311b57 8712 /* Need a block fetch table for performant mode */
d66ae08b 8713 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 8714 sizeof(u32)), GFP_KERNEL);
105a3dbc
RE		 8715 if (!h->blockFetchTable) {
8716 rc = -ENOMEM;
8717 goto clean1; /* rq, ioaccel */
8718 }
6c311b57 8719
105a3dbc
RE		 8720 rc = hpsa_enter_performant_mode(h, trans_support);
8721 if (rc)
8722 goto clean2; /* bft, rq, ioaccel */
8723 return 0;
303932fd 8724
105a3dbc 8725clean2: /* bft, rq, ioaccel */
303932fd 8726 kfree(h->blockFetchTable);
105a3dbc
RE		 8727 h->blockFetchTable = NULL;
8728clean1: /* rq, ioaccel */
8729 hpsa_free_reply_queues(h);
8730 hpsa_free_ioaccel1_cmd_and_bft(h);
8731 hpsa_free_ioaccel2_cmd_and_bft(h);
8732 return rc;
303932fd
DB		 8733}
8734
23100dd9 8735static int is_accelerated_cmd(struct CommandList *c)
76438d08 8736{
23100dd9
SC		 8737 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
8738}
8739
8740static void hpsa_drain_accel_commands(struct ctlr_info *h)
8741{
8742 struct CommandList *c = NULL;
f2405db8 8743 int i, accel_cmds_out;
281a7fd0 8744 int refcount;
76438d08 8745
f2405db8 8746 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 8747 accel_cmds_out = 0;
f2405db8 8748 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8749 c = h->cmd_pool + i;
281a7fd0
WS		 8750 refcount = atomic_inc_return(&c->refcount);
8751 if (refcount > 1) /* Command is allocated */
8752 accel_cmds_out += is_accelerated_cmd(c);
8753 cmd_free(h, c);
f2405db8 8754 }
23100dd9 8755 if (accel_cmds_out <= 0)
281a7fd0 8756 break;
76438d08
SC		 8757 msleep(100);
8758 } while (1);
8759}
8760
edd16368
SC		 8761/*
8762 * This is it. Register the PCI driver information for the cards we control
8763 * the OS will call our registered routines when it finds one of our cards.
8764 */
8765static int __init hpsa_init(void)
8766{
31468401 8767 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 8768}
8769
8770static void __exit hpsa_cleanup(void)
8771{
8772 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 8773}
8774
e1f7de0c
MG		 8775static void __attribute__((unused)) verify_offsets(void)
8776{
dd0e19f3
ST		 8777#define VERIFY_OFFSET(member, offset) \
8778 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
8779
8780 VERIFY_OFFSET(structure_size, 0);
8781 VERIFY_OFFSET(volume_blk_size, 4);
8782 VERIFY_OFFSET(volume_blk_cnt, 8);
8783 VERIFY_OFFSET(phys_blk_shift, 16);
8784 VERIFY_OFFSET(parity_rotation_shift, 17);
8785 VERIFY_OFFSET(strip_size, 18);
8786 VERIFY_OFFSET(disk_starting_blk, 20);
8787 VERIFY_OFFSET(disk_blk_cnt, 28);
8788 VERIFY_OFFSET(data_disks_per_row, 36);
8789 VERIFY_OFFSET(metadata_disks_per_row, 38);
8790 VERIFY_OFFSET(row_cnt, 40);
8791 VERIFY_OFFSET(layout_map_count, 42);
8792 VERIFY_OFFSET(flags, 44);
8793 VERIFY_OFFSET(dekindex, 46);
8794 /* VERIFY_OFFSET(reserved, 48 */
8795 VERIFY_OFFSET(data, 64);
8796
8797#undef VERIFY_OFFSET
8798
b66cc250
MM		 8799#define VERIFY_OFFSET(member, offset) \
8800 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
8801
8802 VERIFY_OFFSET(IU_type, 0);
8803 VERIFY_OFFSET(direction, 1);
8804 VERIFY_OFFSET(reply_queue, 2);
8805 /* VERIFY_OFFSET(reserved1, 3); */
8806 VERIFY_OFFSET(scsi_nexus, 4);
8807 VERIFY_OFFSET(Tag, 8);
8808 VERIFY_OFFSET(cdb, 16);
8809 VERIFY_OFFSET(cciss_lun, 32);
8810 VERIFY_OFFSET(data_len, 40);
8811 VERIFY_OFFSET(cmd_priority_task_attr, 44);
8812 VERIFY_OFFSET(sg_count, 45);
8813 /* VERIFY_OFFSET(reserved3 */
8814 VERIFY_OFFSET(err_ptr, 48);
8815 VERIFY_OFFSET(err_len, 56);
8816 /* VERIFY_OFFSET(reserved4 */
8817 VERIFY_OFFSET(sg, 64);
8818
8819#undef VERIFY_OFFSET
8820
e1f7de0c
MG		 8821#define VERIFY_OFFSET(member, offset) \
8822 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
8823
8824 VERIFY_OFFSET(dev_handle, 0x00);
8825 VERIFY_OFFSET(reserved1, 0x02);
8826 VERIFY_OFFSET(function, 0x03);
8827 VERIFY_OFFSET(reserved2, 0x04);
8828 VERIFY_OFFSET(err_info, 0x0C);
8829 VERIFY_OFFSET(reserved3, 0x10);
8830 VERIFY_OFFSET(err_info_len, 0x12);
8831 VERIFY_OFFSET(reserved4, 0x13);
8832 VERIFY_OFFSET(sgl_offset, 0x14);
8833 VERIFY_OFFSET(reserved5, 0x15);
8834 VERIFY_OFFSET(transfer_len, 0x1C);
8835 VERIFY_OFFSET(reserved6, 0x20);
8836 VERIFY_OFFSET(io_flags, 0x24);
8837 VERIFY_OFFSET(reserved7, 0x26);
8838 VERIFY_OFFSET(LUN, 0x34);
8839 VERIFY_OFFSET(control, 0x3C);
8840 VERIFY_OFFSET(CDB, 0x40);
8841 VERIFY_OFFSET(reserved8, 0x50);
8842 VERIFY_OFFSET(host_context_flags, 0x60);
8843 VERIFY_OFFSET(timeout_sec, 0x62);
8844 VERIFY_OFFSET(ReplyQueue, 0x64);
8845 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 8846 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 8847 VERIFY_OFFSET(host_addr, 0x70);
8848 VERIFY_OFFSET(CISS_LUN, 0x78);
8849 VERIFY_OFFSET(SG, 0x78 + 8);
8850#undef VERIFY_OFFSET
8851}
8852
edd16368
SC		 8853module_init(hpsa_init);
8854module_exit(hpsa_cleanup);
Linux kernel - Deliverables
This page took 0.968215 seconds and 5 git commands to generate.