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hpsa: allow driver requested rescans
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
1358f6dc
DB		 3 * Copyright 2014-2015 PMC-Sierra, Inc.
4 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
edd16368
SC		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
1358f6dc 15 * Questions/Comments/Bugfixes to storagedev@pmcs.com
edd16368
SC		 16 *
17 */
18
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/types.h>
22#include <linux/pci.h>
e5a44df8 23#include <linux/pci-aspm.h>
edd16368
SC		 24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/fs.h>
28#include <linux/timer.h>
edd16368
SC		 29#include <linux/init.h>
30#include <linux/spinlock.h>
edd16368
SC		 31#include <linux/compat.h>
32#include <linux/blktrace_api.h>
33#include <linux/uaccess.h>
34#include <linux/io.h>
35#include <linux/dma-mapping.h>
36#include <linux/completion.h>
37#include <linux/moduleparam.h>
38#include <scsi/scsi.h>
39#include <scsi/scsi_cmnd.h>
40#include <scsi/scsi_device.h>
41#include <scsi/scsi_host.h>
667e23d4 42#include <scsi/scsi_tcq.h>
9437ac43 43#include <scsi/scsi_eh.h>
73153fe5 44#include <scsi/scsi_dbg.h>
edd16368
SC		 45#include <linux/cciss_ioctl.h>
46#include <linux/string.h>
47#include <linux/bitmap.h>
60063497 48#include <linux/atomic.h>
a0c12413 49#include <linux/jiffies.h>
42a91641 50#include <linux/percpu-defs.h>
094963da 51#include <linux/percpu.h>
2b08b3e9 52#include <asm/unaligned.h>
283b4a9b 53#include <asm/div64.h>
edd16368
SC		 54#include "hpsa_cmd.h"
55#include "hpsa.h"
56
57/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
f532a3f9 58#define HPSA_DRIVER_VERSION "3.4.10-0"
edd16368 59#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 60#define HPSA "hpsa"
edd16368 61
007e7aa9
RE		 62/* How long to wait for CISS doorbell communication */
63#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
64#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
65#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
66#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 67#define MAX_IOCTL_CONFIG_WAIT 1000
68
69/*define how many times we will try a command because of bus resets */
70#define MAX_CMD_RETRIES 3
71
72/* Embedded module documentation macros - see modules.h */
73MODULE_AUTHOR("Hewlett-Packard Company");
74MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
75 HPSA_DRIVER_VERSION);
76MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
77MODULE_VERSION(HPSA_DRIVER_VERSION);
78MODULE_LICENSE("GPL");
79
80static int hpsa_allow_any;
81module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_allow_any,
83 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 84static int hpsa_simple_mode;
85module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
86MODULE_PARM_DESC(hpsa_simple_mode,
87 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 88
89/* define the PCI info for the cards we can control */
90static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
fdfa4b6d 131 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
cbb47dcb
DB		 132 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
133 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
134 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
135 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
8e616a5e
SC		 137 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
138 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
139 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
140 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
141 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 142 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 143 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 144 {0,}
145};
146
147MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
148
149/* board_id = Subsystem Device ID & Vendor ID
150 * product = Marketing Name for the board
151 * access = Address of the struct of function pointers
152 */
153static struct board_type products[] = {
edd16368
SC		 154 {0x3241103C, "Smart Array P212", &SA5_access},
155 {0x3243103C, "Smart Array P410", &SA5_access},
156 {0x3245103C, "Smart Array P410i", &SA5_access},
157 {0x3247103C, "Smart Array P411", &SA5_access},
158 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 159 {0x324A103C, "Smart Array P712m", &SA5_access},
160 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 161 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 162 {0x3350103C, "Smart Array P222", &SA5_access},
163 {0x3351103C, "Smart Array P420", &SA5_access},
164 {0x3352103C, "Smart Array P421", &SA5_access},
165 {0x3353103C, "Smart Array P822", &SA5_access},
166 {0x3354103C, "Smart Array P420i", &SA5_access},
167 {0x3355103C, "Smart Array P220i", &SA5_access},
168 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 169 {0x1921103C, "Smart Array P830i", &SA5_access},
170 {0x1922103C, "Smart Array P430", &SA5_access},
171 {0x1923103C, "Smart Array P431", &SA5_access},
172 {0x1924103C, "Smart Array P830", &SA5_access},
173 {0x1926103C, "Smart Array P731m", &SA5_access},
174 {0x1928103C, "Smart Array P230i", &SA5_access},
175 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 176 {0x21BD103C, "Smart Array P244br", &SA5_access},
177 {0x21BE103C, "Smart Array P741m", &SA5_access},
178 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
179 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 180 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 181 {0x21C2103C, "Smart Array P440", &SA5_access},
182 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 183 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 184 {0x21C5103C, "Smart Array P841", &SA5_access},
185 {0x21C6103C, "Smart HBA H244br", &SA5_access},
186 {0x21C7103C, "Smart HBA H240", &SA5_access},
187 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 188 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 189 {0x21CA103C, "Smart Array P246br", &SA5_access},
190 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 191 {0x21CC103C, "Smart Array", &SA5_access},
192 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 193 {0x21CE103C, "Smart HBA", &SA5_access},
fdfa4b6d 194 {0x05809005, "SmartHBA-SA", &SA5_access},
cbb47dcb
DB		 195 {0x05819005, "SmartHBA-SA 8i", &SA5_access},
196 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
197 {0x05839005, "SmartHBA-SA 8e", &SA5_access},
198 {0x05849005, "SmartHBA-SA 16i", &SA5_access},
199 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
8e616a5e
SC		 200 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
201 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
202 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
203 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
204 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 205 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
206};
207
a58e7e53
WS		 208#define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
209static const struct scsi_cmnd hpsa_cmd_busy;
210#define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
211static const struct scsi_cmnd hpsa_cmd_idle;
edd16368
SC		 212static int number_of_controllers;
213
10f66018
SC		 214static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
215static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 216static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 217
218#ifdef CONFIG_COMPAT
42a91641
DB		 219static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
220 void __user *arg);
edd16368
SC		 221#endif
222
223static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 224static struct CommandList *cmd_alloc(struct ctlr_info *h);
73153fe5
WS		 225static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
226static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
227 struct scsi_cmnd *scmd);
a2dac136 228static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 229 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 230 int cmd_type);
2c143342 231static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 232#define VPD_PAGE (1 << 8)
b48d9804 233#define HPSA_SIMPLE_ERROR_BITS 0x03
edd16368 234
f281233d 235static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 236static void hpsa_scan_start(struct Scsi_Host *);
237static int hpsa_scan_finished(struct Scsi_Host *sh,
238 unsigned long elapsed_time);
7c0a0229 239static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 240
241static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 242static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 243static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 244static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 245static void hpsa_slave_destroy(struct scsi_device *sdev);
246
8aa60681 247static void hpsa_update_scsi_devices(struct ctlr_info *h);
edd16368
SC		 248static int check_for_unit_attention(struct ctlr_info *h,
249 struct CommandList *c);
250static void check_ioctl_unit_attention(struct ctlr_info *h,
251 struct CommandList *c);
303932fd
DB		 252/* performant mode helper functions */
253static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 254 int nsgs, int min_blocks, u32 *bucket_map);
105a3dbc
RE		 255static void hpsa_free_performant_mode(struct ctlr_info *h);
256static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 257static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 258static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
259 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
260 u64 *cfg_offset);
261static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
262 unsigned long *memory_bar);
263static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
264static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
265 int wait_for_ready);
75167d2c 266static inline void finish_cmd(struct CommandList *c);
c706a795 267static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 268#define BOARD_NOT_READY 0
269#define BOARD_READY 1
23100dd9 270static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 271static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 272static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
273 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 274 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 275static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 276static u32 lockup_detected(struct ctlr_info *h);
277static int detect_controller_lockup(struct ctlr_info *h);
8270b862 278static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device);
edd16368 279
edd16368
SC		 280static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
281{
282 unsigned long *priv = shost_priv(sdev->host);
283 return (struct ctlr_info *) *priv;
284}
285
a23513e8
SC		 286static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
287{
288 unsigned long *priv = shost_priv(sh);
289 return (struct ctlr_info *) *priv;
290}
291
a58e7e53
WS		 292static inline bool hpsa_is_cmd_idle(struct CommandList *c)
293{
294 return c->scsi_cmd == SCSI_CMD_IDLE;
295}
296
d604f533
WS		 297static inline bool hpsa_is_pending_event(struct CommandList *c)
298{
299 return c->abort_pending || c->reset_pending;
300}
301
9437ac43
SC		 302/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
303static void decode_sense_data(const u8 *sense_data, int sense_data_len,
304 u8 *sense_key, u8 *asc, u8 *ascq)
305{
306 struct scsi_sense_hdr sshdr;
307 bool rc;
308
309 *sense_key = -1;
310 *asc = -1;
311 *ascq = -1;
312
313 if (sense_data_len < 1)
314 return;
315
316 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
317 if (rc) {
318 *sense_key = sshdr.sense_key;
319 *asc = sshdr.asc;
320 *ascq = sshdr.ascq;
321 }
322}
323
edd16368
SC		 324static int check_for_unit_attention(struct ctlr_info *h,
325 struct CommandList *c)
326{
9437ac43
SC		 327 u8 sense_key, asc, ascq;
328 int sense_len;
329
330 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
331 sense_len = sizeof(c->err_info->SenseInfo);
332 else
333 sense_len = c->err_info->SenseLen;
334
335 decode_sense_data(c->err_info->SenseInfo, sense_len,
336 &sense_key, &asc, &ascq);
81c27557 337 if (sense_key != UNIT_ATTENTION || asc == 0xff)
edd16368
SC		 338 return 0;
339
9437ac43 340 switch (asc) {
edd16368 341 case STATE_CHANGED:
9437ac43 342 dev_warn(&h->pdev->dev,
2946e82b
RE		 343 "%s: a state change detected, command retried\n",
344 h->devname);
edd16368
SC		 345 break;
346 case LUN_FAILED:
7f73695a 347 dev_warn(&h->pdev->dev,
2946e82b 348 "%s: LUN failure detected\n", h->devname);
edd16368
SC		 349 break;
350 case REPORT_LUNS_CHANGED:
7f73695a 351 dev_warn(&h->pdev->dev,
2946e82b 352 "%s: report LUN data changed\n", h->devname);
edd16368 353 /*
4f4eb9f1
ST		 354 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
355 * target (array) devices.
edd16368
SC		 356 */
357 break;
358 case POWER_OR_RESET:
2946e82b
RE		 359 dev_warn(&h->pdev->dev,
360 "%s: a power on or device reset detected\n",
361 h->devname);
edd16368
SC		 362 break;
363 case UNIT_ATTENTION_CLEARED:
2946e82b
RE		 364 dev_warn(&h->pdev->dev,
365 "%s: unit attention cleared by another initiator\n",
366 h->devname);
edd16368
SC		 367 break;
368 default:
2946e82b
RE		 369 dev_warn(&h->pdev->dev,
370 "%s: unknown unit attention detected\n",
371 h->devname);
edd16368
SC		 372 break;
373 }
374 return 1;
375}
376
852af20a
MB		 377static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
378{
379 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
380 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
381 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
382 return 0;
383 dev_warn(&h->pdev->dev, HPSA "device busy");
384 return 1;
385}
386
e985c58f
SC		 387static u32 lockup_detected(struct ctlr_info *h);
388static ssize_t host_show_lockup_detected(struct device *dev,
389 struct device_attribute *attr, char *buf)
390{
391 int ld;
392 struct ctlr_info *h;
393 struct Scsi_Host *shost = class_to_shost(dev);
394
395 h = shost_to_hba(shost);
396 ld = lockup_detected(h);
397
398 return sprintf(buf, "ld=%d\n", ld);
399}
400
da0697bd
ST		 401static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
402 struct device_attribute *attr,
403 const char *buf, size_t count)
404{
405 int status, len;
406 struct ctlr_info *h;
407 struct Scsi_Host *shost = class_to_shost(dev);
408 char tmpbuf[10];
409
410 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
411 return -EACCES;
412 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
413 strncpy(tmpbuf, buf, len);
414 tmpbuf[len] = '\0';
415 if (sscanf(tmpbuf, "%d", &status) != 1)
416 return -EINVAL;
417 h = shost_to_hba(shost);
418 h->acciopath_status = !!status;
419 dev_warn(&h->pdev->dev,
420 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
421 h->acciopath_status ? "enabled" : "disabled");
422 return count;
423}
424
2ba8bfc8
SC		 425static ssize_t host_store_raid_offload_debug(struct device *dev,
426 struct device_attribute *attr,
427 const char *buf, size_t count)
428{
429 int debug_level, len;
430 struct ctlr_info *h;
431 struct Scsi_Host *shost = class_to_shost(dev);
432 char tmpbuf[10];
433
434 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
435 return -EACCES;
436 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
437 strncpy(tmpbuf, buf, len);
438 tmpbuf[len] = '\0';
439 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
440 return -EINVAL;
441 if (debug_level < 0)
442 debug_level = 0;
443 h = shost_to_hba(shost);
444 h->raid_offload_debug = debug_level;
445 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
446 h->raid_offload_debug);
447 return count;
448}
449
edd16368
SC		 450static ssize_t host_store_rescan(struct device *dev,
451 struct device_attribute *attr,
452 const char *buf, size_t count)
453{
454 struct ctlr_info *h;
455 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 456 h = shost_to_hba(shost);
31468401 457 hpsa_scan_start(h->scsi_host);
edd16368
SC		 458 return count;
459}
460
d28ce020
SC		 461static ssize_t host_show_firmware_revision(struct device *dev,
462 struct device_attribute *attr, char *buf)
463{
464 struct ctlr_info *h;
465 struct Scsi_Host *shost = class_to_shost(dev);
466 unsigned char *fwrev;
467
468 h = shost_to_hba(shost);
469 if (!h->hba_inquiry_data)
470 return 0;
471 fwrev = &h->hba_inquiry_data[32];
472 return snprintf(buf, 20, "%c%c%c%c\n",
473 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
474}
475
94a13649
SC		 476static ssize_t host_show_commands_outstanding(struct device *dev,
477 struct device_attribute *attr, char *buf)
478{
479 struct Scsi_Host *shost = class_to_shost(dev);
480 struct ctlr_info *h = shost_to_hba(shost);
481
0cbf768e
SC		 482 return snprintf(buf, 20, "%d\n",
483 atomic_read(&h->commands_outstanding));
94a13649
SC		 484}
485
745a7a25
SC		 486static ssize_t host_show_transport_mode(struct device *dev,
487 struct device_attribute *attr, char *buf)
488{
489 struct ctlr_info *h;
490 struct Scsi_Host *shost = class_to_shost(dev);
491
492 h = shost_to_hba(shost);
493 return snprintf(buf, 20, "%s\n",
960a30e7 494 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 495 "performant" : "simple");
496}
497
da0697bd
ST		 498static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
499 struct device_attribute *attr, char *buf)
500{
501 struct ctlr_info *h;
502 struct Scsi_Host *shost = class_to_shost(dev);
503
504 h = shost_to_hba(shost);
505 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
506 (h->acciopath_status == 1) ? "enabled" : "disabled");
507}
508
46380786 509/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 510static u32 unresettable_controller[] = {
511 0x324a103C, /* Smart Array P712m */
9b5c48c2 512 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 513 0x3223103C, /* Smart Array P800 */
514 0x3234103C, /* Smart Array P400 */
515 0x3235103C, /* Smart Array P400i */
516 0x3211103C, /* Smart Array E200i */
517 0x3212103C, /* Smart Array E200 */
518 0x3213103C, /* Smart Array E200i */
519 0x3214103C, /* Smart Array E200i */
520 0x3215103C, /* Smart Array E200i */
521 0x3237103C, /* Smart Array E500 */
522 0x323D103C, /* Smart Array P700m */
7af0abbc 523 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 524 0x409C0E11, /* Smart Array 6400 */
525 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 526 0x40700E11, /* Smart Array 5300 */
527 0x40820E11, /* Smart Array 532 */
528 0x40830E11, /* Smart Array 5312 */
529 0x409A0E11, /* Smart Array 641 */
530 0x409B0E11, /* Smart Array 642 */
531 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 532};
533
46380786
SC		 534/* List of controllers which cannot even be soft reset */
535static u32 soft_unresettable_controller[] = {
7af0abbc 536 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 537 0x40700E11, /* Smart Array 5300 */
538 0x40820E11, /* Smart Array 532 */
539 0x40830E11, /* Smart Array 5312 */
540 0x409A0E11, /* Smart Array 641 */
541 0x409B0E11, /* Smart Array 642 */
542 0x40910E11, /* Smart Array 6i */
46380786
SC		 543 /* Exclude 640x boards. These are two pci devices in one slot
544 * which share a battery backed cache module. One controls the
545 * cache, the other accesses the cache through the one that controls
546 * it. If we reset the one controlling the cache, the other will
547 * likely not be happy. Just forbid resetting this conjoined mess.
548 * The 640x isn't really supported by hpsa anyway.
549 */
550 0x409C0E11, /* Smart Array 6400 */
551 0x409D0E11, /* Smart Array 6400 EM */
552};
553
9b5c48c2
SC		 554static u32 needs_abort_tags_swizzled[] = {
555 0x323D103C, /* Smart Array P700m */
556 0x324a103C, /* Smart Array P712m */
557 0x324b103C, /* SmartArray P711m */
558};
559
560static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 561{
562 int i;
563
9b5c48c2
SC		 564 for (i = 0; i < nelems; i++)
565 if (a[i] == board_id)
566 return 1;
567 return 0;
46380786
SC		 568}
569
9b5c48c2 570static int ctlr_is_hard_resettable(u32 board_id)
46380786 571{
9b5c48c2
SC		 572 return !board_id_in_array(unresettable_controller,
573 ARRAY_SIZE(unresettable_controller), board_id);
574}
46380786 575
9b5c48c2
SC		 576static int ctlr_is_soft_resettable(u32 board_id)
577{
578 return !board_id_in_array(soft_unresettable_controller,
579 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 580}
581
46380786
SC		 582static int ctlr_is_resettable(u32 board_id)
583{
584 return ctlr_is_hard_resettable(board_id) ||
585 ctlr_is_soft_resettable(board_id);
586}
587
9b5c48c2
SC		 588static int ctlr_needs_abort_tags_swizzled(u32 board_id)
589{
590 return board_id_in_array(needs_abort_tags_swizzled,
591 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
592}
593
941b1cda
SC		 594static ssize_t host_show_resettable(struct device *dev,
595 struct device_attribute *attr, char *buf)
596{
597 struct ctlr_info *h;
598 struct Scsi_Host *shost = class_to_shost(dev);
599
600 h = shost_to_hba(shost);
46380786 601 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 602}
603
edd16368
SC		 604static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
605{
606 return (scsi3addr[3] & 0xC0) == 0x40;
607}
608
f2ef0ce7
RE		 609static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
610 "1(+0)ADM", "UNKNOWN"
edd16368 611};
6b80b18f
ST		 612#define HPSA_RAID_0 0
613#define HPSA_RAID_4 1
614#define HPSA_RAID_1 2 /* also used for RAID 10 */
615#define HPSA_RAID_5 3 /* also used for RAID 50 */
616#define HPSA_RAID_51 4
617#define HPSA_RAID_6 5 /* also used for RAID 60 */
618#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 619#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
620
621static ssize_t raid_level_show(struct device *dev,
622 struct device_attribute *attr, char *buf)
623{
624 ssize_t l = 0;
82a72c0a 625 unsigned char rlevel;
edd16368
SC		 626 struct ctlr_info *h;
627 struct scsi_device *sdev;
628 struct hpsa_scsi_dev_t *hdev;
629 unsigned long flags;
630
631 sdev = to_scsi_device(dev);
632 h = sdev_to_hba(sdev);
633 spin_lock_irqsave(&h->lock, flags);
634 hdev = sdev->hostdata;
635 if (!hdev) {
636 spin_unlock_irqrestore(&h->lock, flags);
637 return -ENODEV;
638 }
639
640 /* Is this even a logical drive? */
641 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
642 spin_unlock_irqrestore(&h->lock, flags);
643 l = snprintf(buf, PAGE_SIZE, "N/A\n");
644 return l;
645 }
646
647 rlevel = hdev->raid_level;
648 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 649 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 650 rlevel = RAID_UNKNOWN;
651 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
652 return l;
653}
654
655static ssize_t lunid_show(struct device *dev,
656 struct device_attribute *attr, char *buf)
657{
658 struct ctlr_info *h;
659 struct scsi_device *sdev;
660 struct hpsa_scsi_dev_t *hdev;
661 unsigned long flags;
662 unsigned char lunid[8];
663
664 sdev = to_scsi_device(dev);
665 h = sdev_to_hba(sdev);
666 spin_lock_irqsave(&h->lock, flags);
667 hdev = sdev->hostdata;
668 if (!hdev) {
669 spin_unlock_irqrestore(&h->lock, flags);
670 return -ENODEV;
671 }
672 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
673 spin_unlock_irqrestore(&h->lock, flags);
674 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
675 lunid[0], lunid[1], lunid[2], lunid[3],
676 lunid[4], lunid[5], lunid[6], lunid[7]);
677}
678
679static ssize_t unique_id_show(struct device *dev,
680 struct device_attribute *attr, char *buf)
681{
682 struct ctlr_info *h;
683 struct scsi_device *sdev;
684 struct hpsa_scsi_dev_t *hdev;
685 unsigned long flags;
686 unsigned char sn[16];
687
688 sdev = to_scsi_device(dev);
689 h = sdev_to_hba(sdev);
690 spin_lock_irqsave(&h->lock, flags);
691 hdev = sdev->hostdata;
692 if (!hdev) {
693 spin_unlock_irqrestore(&h->lock, flags);
694 return -ENODEV;
695 }
696 memcpy(sn, hdev->device_id, sizeof(sn));
697 spin_unlock_irqrestore(&h->lock, flags);
698 return snprintf(buf, 16 * 2 + 2,
699 "%02X%02X%02X%02X%02X%02X%02X%02X"
700 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
701 sn[0], sn[1], sn[2], sn[3],
702 sn[4], sn[5], sn[6], sn[7],
703 sn[8], sn[9], sn[10], sn[11],
704 sn[12], sn[13], sn[14], sn[15]);
705}
706
c1988684
ST		 707static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
708 struct device_attribute *attr, char *buf)
709{
710 struct ctlr_info *h;
711 struct scsi_device *sdev;
712 struct hpsa_scsi_dev_t *hdev;
713 unsigned long flags;
714 int offload_enabled;
715
716 sdev = to_scsi_device(dev);
717 h = sdev_to_hba(sdev);
718 spin_lock_irqsave(&h->lock, flags);
719 hdev = sdev->hostdata;
720 if (!hdev) {
721 spin_unlock_irqrestore(&h->lock, flags);
722 return -ENODEV;
723 }
724 offload_enabled = hdev->offload_enabled;
725 spin_unlock_irqrestore(&h->lock, flags);
726 return snprintf(buf, 20, "%d\n", offload_enabled);
727}
728
8270b862
JH		 729#define MAX_PATHS 8
730#define PATH_STRING_LEN 50
731
732static ssize_t path_info_show(struct device *dev,
733 struct device_attribute *attr, char *buf)
734{
735 struct ctlr_info *h;
736 struct scsi_device *sdev;
737 struct hpsa_scsi_dev_t *hdev;
738 unsigned long flags;
739 int i;
740 int output_len = 0;
741 u8 box;
742 u8 bay;
743 u8 path_map_index = 0;
744 char *active;
745 unsigned char phys_connector[2];
746 unsigned char path[MAX_PATHS][PATH_STRING_LEN];
747
748 memset(path, 0, MAX_PATHS * PATH_STRING_LEN);
749 sdev = to_scsi_device(dev);
750 h = sdev_to_hba(sdev);
751 spin_lock_irqsave(&h->devlock, flags);
752 hdev = sdev->hostdata;
753 if (!hdev) {
754 spin_unlock_irqrestore(&h->devlock, flags);
755 return -ENODEV;
756 }
757
758 bay = hdev->bay;
759 for (i = 0; i < MAX_PATHS; i++) {
760 path_map_index = 1<<i;
761 if (i == hdev->active_path_index)
762 active = "Active";
763 else if (hdev->path_map & path_map_index)
764 active = "Inactive";
765 else
766 continue;
767
768 output_len = snprintf(path[i],
769 PATH_STRING_LEN, "[%d:%d:%d:%d] %20.20s ",
770 h->scsi_host->host_no,
771 hdev->bus, hdev->target, hdev->lun,
772 scsi_device_type(hdev->devtype));
773
774 if (is_ext_target(h, hdev) ||
775 (hdev->devtype == TYPE_RAID) ||
776 is_logical_dev_addr_mode(hdev->scsi3addr)) {
777 output_len += snprintf(path[i] + output_len,
778 PATH_STRING_LEN, "%s\n",
779 active);
780 continue;
781 }
782
783 box = hdev->box[i];
784 memcpy(&phys_connector, &hdev->phys_connector[i],
785 sizeof(phys_connector));
786 if (phys_connector[0] < '0')
787 phys_connector[0] = '0';
788 if (phys_connector[1] < '0')
789 phys_connector[1] = '0';
790 if (hdev->phys_connector[i] > 0)
791 output_len += snprintf(path[i] + output_len,
792 PATH_STRING_LEN,
793 "PORT: %.2s ",
794 phys_connector);
b9092b79
KB		 795 if (hdev->devtype == TYPE_DISK &&
796 hdev->expose_state != HPSA_DO_NOT_EXPOSE) {
8270b862
JH		 797 if (box == 0 || box == 0xFF) {
798 output_len += snprintf(path[i] + output_len,
799 PATH_STRING_LEN,
800 "BAY: %hhu %s\n",
801 bay, active);
802 } else {
803 output_len += snprintf(path[i] + output_len,
804 PATH_STRING_LEN,
805 "BOX: %hhu BAY: %hhu %s\n",
806 box, bay, active);
807 }
808 } else if (box != 0 && box != 0xFF) {
809 output_len += snprintf(path[i] + output_len,
810 PATH_STRING_LEN, "BOX: %hhu %s\n",
811 box, active);
812 } else
813 output_len += snprintf(path[i] + output_len,
814 PATH_STRING_LEN, "%s\n", active);
815 }
816
817 spin_unlock_irqrestore(&h->devlock, flags);
818 return snprintf(buf, output_len+1, "%s%s%s%s%s%s%s%s",
819 path[0], path[1], path[2], path[3],
820 path[4], path[5], path[6], path[7]);
821}
822
3f5eac3a
SC		 823static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
824static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
825static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
826static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 827static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
828 host_show_hp_ssd_smart_path_enabled, NULL);
8270b862 829static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
da0697bd
ST		 830static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
831 host_show_hp_ssd_smart_path_status,
832 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 833static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
834 host_store_raid_offload_debug);
3f5eac3a
SC		 835static DEVICE_ATTR(firmware_revision, S_IRUGO,
836 host_show_firmware_revision, NULL);
837static DEVICE_ATTR(commands_outstanding, S_IRUGO,
838 host_show_commands_outstanding, NULL);
839static DEVICE_ATTR(transport_mode, S_IRUGO,
840 host_show_transport_mode, NULL);
941b1cda
SC		 841static DEVICE_ATTR(resettable, S_IRUGO,
842 host_show_resettable, NULL);
e985c58f
SC		 843static DEVICE_ATTR(lockup_detected, S_IRUGO,
844 host_show_lockup_detected, NULL);
3f5eac3a
SC		 845
846static struct device_attribute *hpsa_sdev_attrs[] = {
847 &dev_attr_raid_level,
848 &dev_attr_lunid,
849 &dev_attr_unique_id,
c1988684 850 &dev_attr_hp_ssd_smart_path_enabled,
8270b862 851 &dev_attr_path_info,
e985c58f 852 &dev_attr_lockup_detected,
3f5eac3a
SC		 853 NULL,
854};
855
856static struct device_attribute *hpsa_shost_attrs[] = {
857 &dev_attr_rescan,
858 &dev_attr_firmware_revision,
859 &dev_attr_commands_outstanding,
860 &dev_attr_transport_mode,
941b1cda 861 &dev_attr_resettable,
da0697bd 862 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 863 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 864 NULL,
865};
866
41ce4c35
SC		 867#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
868 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
869
3f5eac3a
SC		 870static struct scsi_host_template hpsa_driver_template = {
871 .module = THIS_MODULE,
f79cfec6
SC		 872 .name = HPSA,
873 .proc_name = HPSA,
3f5eac3a
SC		 874 .queuecommand = hpsa_scsi_queue_command,
875 .scan_start = hpsa_scan_start,
876 .scan_finished = hpsa_scan_finished,
7c0a0229 877 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 878 .this_id = -1,
879 .use_clustering = ENABLE_CLUSTERING,
75167d2c 880 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 881 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
882 .ioctl = hpsa_ioctl,
883 .slave_alloc = hpsa_slave_alloc,
41ce4c35 884 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 885 .slave_destroy = hpsa_slave_destroy,
886#ifdef CONFIG_COMPAT
887 .compat_ioctl = hpsa_compat_ioctl,
888#endif
889 .sdev_attrs = hpsa_sdev_attrs,
890 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 891 .max_sectors = 8192,
54b2b50c 892 .no_write_same = 1,
3f5eac3a
SC		 893};
894
254f796b 895static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 896{
897 u32 a;
072b0518 898 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 899
e1f7de0c
MG		 900 if (h->transMethod & CFGTBL_Trans_io_accel1)
901 return h->access.command_completed(h, q);
902
3f5eac3a 903 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 904 return h->access.command_completed(h, q);
3f5eac3a 905
254f796b
MG		 906 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
907 a = rq->head[rq->current_entry];
908 rq->current_entry++;
0cbf768e 909 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 910 } else {
911 a = FIFO_EMPTY;
912 }
913 /* Check for wraparound */
254f796b
MG		 914 if (rq->current_entry == h->max_commands) {
915 rq->current_entry = 0;
916 rq->wraparound ^= 1;
3f5eac3a
SC		 917 }
918 return a;
919}
920
c349775e
ST		 921/*
922 * There are some special bits in the bus address of the
923 * command that we have to set for the controller to know
924 * how to process the command:
925 *
926 * Normal performant mode:
927 * bit 0: 1 means performant mode, 0 means simple mode.
928 * bits 1-3 = block fetch table entry
929 * bits 4-6 = command type (== 0)
930 *
931 * ioaccel1 mode:
932 * bit 0 = "performant mode" bit.
933 * bits 1-3 = block fetch table entry
934 * bits 4-6 = command type (== 110)
935 * (command type is needed because ioaccel1 mode
936 * commands are submitted through the same register as normal
937 * mode commands, so this is how the controller knows whether
938 * the command is normal mode or ioaccel1 mode.)
939 *
940 * ioaccel2 mode:
941 * bit 0 = "performant mode" bit.
942 * bits 1-4 = block fetch table entry (note extra bit)
943 * bits 4-6 = not needed, because ioaccel2 mode has
944 * a separate special register for submitting commands.
945 */
946
25163bd5
WS		 947/*
948 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 949 * set bit 0 for pull model, bits 3-1 for block fetch
950 * register number
951 */
25163bd5
WS		 952#define DEFAULT_REPLY_QUEUE (-1)
953static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
954 int reply_queue)
3f5eac3a 955{
254f796b 956 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 957 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 958 if (unlikely(!h->msix_vector))
959 return;
960 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 961 c->Header.ReplyQueue =
804a5cb5 962 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 963 else
964 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 965 }
3f5eac3a
SC		 966}
967
c349775e 968static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 969 struct CommandList *c,
970 int reply_queue)
c349775e
ST		 971{
972 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
973
25163bd5
WS		 974 /*
975 * Tell the controller to post the reply to the queue for this
c349775e
ST		 976 * processor. This seems to give the best I/O throughput.
977 */
25163bd5
WS		 978 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
979 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
980 else
981 cp->ReplyQueue = reply_queue % h->nreply_queues;
982 /*
983 * Set the bits in the address sent down to include:
c349775e
ST		 984 * - performant mode bit (bit 0)
985 * - pull count (bits 1-3)
986 * - command type (bits 4-6)
987 */
988 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
989 IOACCEL1_BUSADDR_CMDTYPE;
990}
991
8be986cc
SC		 992static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
993 struct CommandList *c,
994 int reply_queue)
995{
996 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
997 &h->ioaccel2_cmd_pool[c->cmdindex];
998
999 /* Tell the controller to post the reply to the queue for this
1000 * processor. This seems to give the best I/O throughput.
1001 */
1002 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1003 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1004 else
1005 cp->reply_queue = reply_queue % h->nreply_queues;
1006 /* Set the bits in the address sent down to include:
1007 * - performant mode bit not used in ioaccel mode 2
1008 * - pull count (bits 0-3)
1009 * - command type isn't needed for ioaccel2
1010 */
1011 c->busaddr |= h->ioaccel2_blockFetchTable[0];
1012}
1013
c349775e 1014static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1015 struct CommandList *c,
1016 int reply_queue)
c349775e
ST		 1017{
1018 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
1019
25163bd5
WS		 1020 /*
1021 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1022 * processor. This seems to give the best I/O throughput.
1023 */
25163bd5
WS		 1024 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1025 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1026 else
1027 cp->reply_queue = reply_queue % h->nreply_queues;
1028 /*
1029 * Set the bits in the address sent down to include:
c349775e
ST		 1030 * - performant mode bit not used in ioaccel mode 2
1031 * - pull count (bits 0-3)
1032 * - command type isn't needed for ioaccel2
1033 */
1034 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
1035}
1036
e85c5974
SC		 1037static int is_firmware_flash_cmd(u8 *cdb)
1038{
1039 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
1040}
1041
1042/*
1043 * During firmware flash, the heartbeat register may not update as frequently
1044 * as it should. So we dial down lockup detection during firmware flash. and
1045 * dial it back up when firmware flash completes.
1046 */
1047#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
1048#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
1049static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
1050 struct CommandList *c)
1051{
1052 if (!is_firmware_flash_cmd(c->Request.CDB))
1053 return;
1054 atomic_inc(&h->firmware_flash_in_progress);
1055 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
1056}
1057
1058static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
1059 struct CommandList *c)
1060{
1061 if (is_firmware_flash_cmd(c->Request.CDB) &&
1062 atomic_dec_and_test(&h->firmware_flash_in_progress))
1063 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
1064}
1065
25163bd5
WS		 1066static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
1067 struct CommandList *c, int reply_queue)
3f5eac3a 1068{
c05e8866
SC		 1069 dial_down_lockup_detection_during_fw_flash(h, c);
1070 atomic_inc(&h->commands_outstanding);
c349775e
ST		 1071 switch (c->cmd_type) {
1072 case CMD_IOACCEL1:
25163bd5 1073 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 1074 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 1075 break;
1076 case CMD_IOACCEL2:
25163bd5 1077 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 1078 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e 1079 break;
8be986cc
SC		 1080 case IOACCEL2_TMF:
1081 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
1082 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1083 break;
c349775e 1084 default:
25163bd5 1085 set_performant_mode(h, c, reply_queue);
c05e8866 1086 h->access.submit_command(h, c);
c349775e 1087 }
3f5eac3a
SC		 1088}
1089
a58e7e53 1090static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
25163bd5 1091{
d604f533 1092 if (unlikely(hpsa_is_pending_event(c)))
a58e7e53
WS		 1093 return finish_cmd(c);
1094
25163bd5
WS		 1095 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
1096}
1097
3f5eac3a
SC		 1098static inline int is_hba_lunid(unsigned char scsi3addr[])
1099{
1100 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
1101}
1102
1103static inline int is_scsi_rev_5(struct ctlr_info *h)
1104{
1105 if (!h->hba_inquiry_data)
1106 return 0;
1107 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1108 return 1;
1109 return 0;
1110}
1111
edd16368
SC		 1112static int hpsa_find_target_lun(struct ctlr_info *h,
1113 unsigned char scsi3addr[], int bus, int *target, int *lun)
1114{
1115 /* finds an unused bus, target, lun for a new physical device
1116 * assumes h->devlock is held
1117 */
1118 int i, found = 0;
cfe5badc 1119 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 1120
263d9401 1121 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 1122
1123 for (i = 0; i < h->ndevices; i++) {
1124 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 1125 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 1126 }
1127
263d9401
AM		 1128 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1129 if (i < HPSA_MAX_DEVICES) {
1130 /* *bus = 1; */
1131 *target = i;
1132 *lun = 0;
1133 found = 1;
edd16368
SC		 1134 }
1135 return !found;
1136}
1137
1d33d85d 1138static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
0d96ef5f
WS		 1139 struct hpsa_scsi_dev_t *dev, char *description)
1140{
9975ec9d
DB		 1141 if (h == NULL || h->pdev == NULL || h->scsi_host == NULL)
1142 return;
1143
0d96ef5f
WS		 1144 dev_printk(level, &h->pdev->dev,
1145 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
1146 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1147 description,
1148 scsi_device_type(dev->devtype),
1149 dev->vendor,
1150 dev->model,
1151 dev->raid_level > RAID_UNKNOWN ?
1152 "RAID-?" : raid_label[dev->raid_level],
1153 dev->offload_config ? '+' : '-',
1154 dev->offload_enabled ? '+' : '-',
1155 dev->expose_state);
1156}
1157
edd16368 1158/* Add an entry into h->dev[] array. */
8aa60681 1159static int hpsa_scsi_add_entry(struct ctlr_info *h,
edd16368
SC		 1160 struct hpsa_scsi_dev_t *device,
1161 struct hpsa_scsi_dev_t *added[], int *nadded)
1162{
1163 /* assumes h->devlock is held */
1164 int n = h->ndevices;
1165 int i;
1166 unsigned char addr1[8], addr2[8];
1167 struct hpsa_scsi_dev_t *sd;
1168
cfe5badc 1169 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1170 dev_err(&h->pdev->dev, "too many devices, some will be "
1171 "inaccessible.\n");
1172 return -1;
1173 }
1174
1175 /* physical devices do not have lun or target assigned until now. */
1176 if (device->lun != -1)
1177 /* Logical device, lun is already assigned. */
1178 goto lun_assigned;
1179
1180 /* If this device a non-zero lun of a multi-lun device
1181 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1182 * unit no, zero otherwise.
edd16368
SC		 1183 */
1184 if (device->scsi3addr[4] == 0) {
1185 /* This is not a non-zero lun of a multi-lun device */
1186 if (hpsa_find_target_lun(h, device->scsi3addr,
1187 device->bus, &device->target, &device->lun) != 0)
1188 return -1;
1189 goto lun_assigned;
1190 }
1191
1192 /* This is a non-zero lun of a multi-lun device.
1193 * Search through our list and find the device which
9a4178b7 1194 * has the same 8 byte LUN address, excepting byte 4 and 5.
edd16368
SC		 1195 * Assign the same bus and target for this new LUN.
1196 * Use the logical unit number from the firmware.
1197 */
1198 memcpy(addr1, device->scsi3addr, 8);
1199 addr1[4] = 0;
9a4178b7 1200 addr1[5] = 0;
edd16368
SC		 1201 for (i = 0; i < n; i++) {
1202 sd = h->dev[i];
1203 memcpy(addr2, sd->scsi3addr, 8);
1204 addr2[4] = 0;
9a4178b7 1205 addr2[5] = 0;
1206 /* differ only in byte 4 and 5? */
edd16368
SC		 1207 if (memcmp(addr1, addr2, 8) == 0) {
1208 device->bus = sd->bus;
1209 device->target = sd->target;
1210 device->lun = device->scsi3addr[4];
1211 break;
1212 }
1213 }
1214 if (device->lun == -1) {
1215 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1216 " suspect firmware bug or unsupported hardware "
1217 "configuration.\n");
1218 return -1;
1219 }
1220
1221lun_assigned:
1222
1223 h->dev[n] = device;
1224 h->ndevices++;
1225 added[*nadded] = device;
1226 (*nadded)++;
0d96ef5f
WS		 1227 hpsa_show_dev_msg(KERN_INFO, h, device,
1228 device->expose_state & HPSA_SCSI_ADD ? "added" : "masked");
a473d86c
RE		 1229 device->offload_to_be_enabled = device->offload_enabled;
1230 device->offload_enabled = 0;
edd16368
SC		 1231 return 0;
1232}
1233
bd9244f7 1234/* Update an entry in h->dev[] array. */
8aa60681 1235static void hpsa_scsi_update_entry(struct ctlr_info *h,
bd9244f7
ST		 1236 int entry, struct hpsa_scsi_dev_t *new_entry)
1237{
a473d86c 1238 int offload_enabled;
bd9244f7
ST		 1239 /* assumes h->devlock is held */
1240 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1241
1242 /* Raid level changed. */
1243 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1244
03383736
DB		 1245 /* Raid offload parameters changed. Careful about the ordering. */
1246 if (new_entry->offload_config && new_entry->offload_enabled) {
1247 /*
1248 * if drive is newly offload_enabled, we want to copy the
1249 * raid map data first. If previously offload_enabled and
1250 * offload_config were set, raid map data had better be
1251 * the same as it was before. if raid map data is changed
1252 * then it had better be the case that
1253 * h->dev[entry]->offload_enabled is currently 0.
1254 */
1255 h->dev[entry]->raid_map = new_entry->raid_map;
1256 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1257 }
a3144e0b
JH		 1258 if (new_entry->hba_ioaccel_enabled) {
1259 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1260 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1261 }
1262 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1263 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1264 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1265 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1266
41ce4c35
SC		 1267 /*
1268 * We can turn off ioaccel offload now, but need to delay turning
1269 * it on until we can update h->dev[entry]->phys_disk[], but we
1270 * can't do that until all the devices are updated.
1271 */
1272 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1273 if (!new_entry->offload_enabled)
1274 h->dev[entry]->offload_enabled = 0;
1275
a473d86c
RE		 1276 offload_enabled = h->dev[entry]->offload_enabled;
1277 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1278 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1279 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1280}
1281
2a8ccf31 1282/* Replace an entry from h->dev[] array. */
8aa60681 1283static void hpsa_scsi_replace_entry(struct ctlr_info *h,
2a8ccf31
SC		 1284 int entry, struct hpsa_scsi_dev_t *new_entry,
1285 struct hpsa_scsi_dev_t *added[], int *nadded,
1286 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1287{
1288 /* assumes h->devlock is held */
cfe5badc 1289 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1290 removed[*nremoved] = h->dev[entry];
1291 (*nremoved)++;
01350d05
SC		 1292
1293 /*
1294 * New physical devices won't have target/lun assigned yet
1295 * so we need to preserve the values in the slot we are replacing.
1296 */
1297 if (new_entry->target == -1) {
1298 new_entry->target = h->dev[entry]->target;
1299 new_entry->lun = h->dev[entry]->lun;
1300 }
1301
2a8ccf31
SC		 1302 h->dev[entry] = new_entry;
1303 added[*nadded] = new_entry;
1304 (*nadded)++;
0d96ef5f 1305 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1306 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1307 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1308}
1309
edd16368 1310/* Remove an entry from h->dev[] array. */
8aa60681 1311static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
edd16368
SC		 1312 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1313{
1314 /* assumes h->devlock is held */
1315 int i;
1316 struct hpsa_scsi_dev_t *sd;
1317
cfe5badc 1318 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1319
1320 sd = h->dev[entry];
1321 removed[*nremoved] = h->dev[entry];
1322 (*nremoved)++;
1323
1324 for (i = entry; i < h->ndevices-1; i++)
1325 h->dev[i] = h->dev[i+1];
1326 h->ndevices--;
0d96ef5f 1327 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1328}
1329
1330#define SCSI3ADDR_EQ(a, b) ( \
1331 (a)[7] == (b)[7] && \
1332 (a)[6] == (b)[6] && \
1333 (a)[5] == (b)[5] && \
1334 (a)[4] == (b)[4] && \
1335 (a)[3] == (b)[3] && \
1336 (a)[2] == (b)[2] && \
1337 (a)[1] == (b)[1] && \
1338 (a)[0] == (b)[0])
1339
1340static void fixup_botched_add(struct ctlr_info *h,
1341 struct hpsa_scsi_dev_t *added)
1342{
1343 /* called when scsi_add_device fails in order to re-adjust
1344 * h->dev[] to match the mid layer's view.
1345 */
1346 unsigned long flags;
1347 int i, j;
1348
1349 spin_lock_irqsave(&h->lock, flags);
1350 for (i = 0; i < h->ndevices; i++) {
1351 if (h->dev[i] == added) {
1352 for (j = i; j < h->ndevices-1; j++)
1353 h->dev[j] = h->dev[j+1];
1354 h->ndevices--;
1355 break;
1356 }
1357 }
1358 spin_unlock_irqrestore(&h->lock, flags);
1359 kfree(added);
1360}
1361
1362static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1363 struct hpsa_scsi_dev_t *dev2)
1364{
edd16368
SC		 1365 /* we compare everything except lun and target as these
1366 * are not yet assigned. Compare parts likely
1367 * to differ first
1368 */
1369 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1370 sizeof(dev1->scsi3addr)) != 0)
1371 return 0;
1372 if (memcmp(dev1->device_id, dev2->device_id,
1373 sizeof(dev1->device_id)) != 0)
1374 return 0;
1375 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1376 return 0;
1377 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1378 return 0;
edd16368
SC		 1379 if (dev1->devtype != dev2->devtype)
1380 return 0;
edd16368
SC		 1381 if (dev1->bus != dev2->bus)
1382 return 0;
1383 return 1;
1384}
1385
bd9244f7
ST		 1386static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1387 struct hpsa_scsi_dev_t *dev2)
1388{
1389 /* Device attributes that can change, but don't mean
1390 * that the device is a different device, nor that the OS
1391 * needs to be told anything about the change.
1392 */
1393 if (dev1->raid_level != dev2->raid_level)
1394 return 1;
250fb125
SC		 1395 if (dev1->offload_config != dev2->offload_config)
1396 return 1;
1397 if (dev1->offload_enabled != dev2->offload_enabled)
1398 return 1;
93849508
DB		 1399 if (!is_logical_dev_addr_mode(dev1->scsi3addr))
1400 if (dev1->queue_depth != dev2->queue_depth)
1401 return 1;
bd9244f7
ST		 1402 return 0;
1403}
1404
edd16368
SC		 1405/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1406 * and return needle location in *index. If scsi3addr matches, but not
1407 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1408 * location in *index.
1409 * In the case of a minor device attribute change, such as RAID level, just
1410 * return DEVICE_UPDATED, along with the updated device's location in index.
1411 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1412 */
1413static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1414 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1415 int *index)
1416{
1417 int i;
1418#define DEVICE_NOT_FOUND 0
1419#define DEVICE_CHANGED 1
1420#define DEVICE_SAME 2
bd9244f7 1421#define DEVICE_UPDATED 3
1d33d85d
DB		 1422 if (needle == NULL)
1423 return DEVICE_NOT_FOUND;
1424
edd16368 1425 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1426 if (haystack[i] == NULL) /* previously removed. */
1427 continue;
edd16368
SC		 1428 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1429 *index = i;
bd9244f7
ST		 1430 if (device_is_the_same(needle, haystack[i])) {
1431 if (device_updated(needle, haystack[i]))
1432 return DEVICE_UPDATED;
edd16368 1433 return DEVICE_SAME;
bd9244f7 1434 } else {
9846590e
SC		 1435 /* Keep offline devices offline */
1436 if (needle->volume_offline)
1437 return DEVICE_NOT_FOUND;
edd16368 1438 return DEVICE_CHANGED;
bd9244f7 1439 }
edd16368
SC		 1440 }
1441 }
1442 *index = -1;
1443 return DEVICE_NOT_FOUND;
1444}
1445
9846590e
SC		 1446static void hpsa_monitor_offline_device(struct ctlr_info *h,
1447 unsigned char scsi3addr[])
1448{
1449 struct offline_device_entry *device;
1450 unsigned long flags;
1451
1452 /* Check to see if device is already on the list */
1453 spin_lock_irqsave(&h->offline_device_lock, flags);
1454 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1455 if (memcmp(device->scsi3addr, scsi3addr,
1456 sizeof(device->scsi3addr)) == 0) {
1457 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1458 return;
1459 }
1460 }
1461 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1462
1463 /* Device is not on the list, add it. */
1464 device = kmalloc(sizeof(*device), GFP_KERNEL);
1465 if (!device) {
1466 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1467 return;
1468 }
1469 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1470 spin_lock_irqsave(&h->offline_device_lock, flags);
1471 list_add_tail(&device->offline_list, &h->offline_device_list);
1472 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1473}
1474
1475/* Print a message explaining various offline volume states */
1476static void hpsa_show_volume_status(struct ctlr_info *h,
1477 struct hpsa_scsi_dev_t *sd)
1478{
1479 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1480 dev_info(&h->pdev->dev,
1481 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1482 h->scsi_host->host_no,
1483 sd->bus, sd->target, sd->lun);
1484 switch (sd->volume_offline) {
1485 case HPSA_LV_OK:
1486 break;
1487 case HPSA_LV_UNDERGOING_ERASE:
1488 dev_info(&h->pdev->dev,
1489 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1490 h->scsi_host->host_no,
1491 sd->bus, sd->target, sd->lun);
1492 break;
5ca01204
SB		 1493 case HPSA_LV_NOT_AVAILABLE:
1494 dev_info(&h->pdev->dev,
1495 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
1496 h->scsi_host->host_no,
1497 sd->bus, sd->target, sd->lun);
1498 break;
9846590e
SC		 1499 case HPSA_LV_UNDERGOING_RPI:
1500 dev_info(&h->pdev->dev,
5ca01204 1501 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
9846590e
SC		 1502 h->scsi_host->host_no,
1503 sd->bus, sd->target, sd->lun);
1504 break;
1505 case HPSA_LV_PENDING_RPI:
1506 dev_info(&h->pdev->dev,
5ca01204
SB		 1507 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1508 h->scsi_host->host_no,
1509 sd->bus, sd->target, sd->lun);
9846590e
SC		 1510 break;
1511 case HPSA_LV_ENCRYPTED_NO_KEY:
1512 dev_info(&h->pdev->dev,
1513 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1514 h->scsi_host->host_no,
1515 sd->bus, sd->target, sd->lun);
1516 break;
1517 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1518 dev_info(&h->pdev->dev,
1519 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1520 h->scsi_host->host_no,
1521 sd->bus, sd->target, sd->lun);
1522 break;
1523 case HPSA_LV_UNDERGOING_ENCRYPTION:
1524 dev_info(&h->pdev->dev,
1525 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1526 h->scsi_host->host_no,
1527 sd->bus, sd->target, sd->lun);
1528 break;
1529 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1530 dev_info(&h->pdev->dev,
1531 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1532 h->scsi_host->host_no,
1533 sd->bus, sd->target, sd->lun);
1534 break;
1535 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1536 dev_info(&h->pdev->dev,
1537 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1538 h->scsi_host->host_no,
1539 sd->bus, sd->target, sd->lun);
1540 break;
1541 case HPSA_LV_PENDING_ENCRYPTION:
1542 dev_info(&h->pdev->dev,
1543 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1544 h->scsi_host->host_no,
1545 sd->bus, sd->target, sd->lun);
1546 break;
1547 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1548 dev_info(&h->pdev->dev,
1549 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1550 h->scsi_host->host_no,
1551 sd->bus, sd->target, sd->lun);
1552 break;
1553 }
1554}
1555
03383736
DB		 1556/*
1557 * Figure the list of physical drive pointers for a logical drive with
1558 * raid offload configured.
1559 */
1560static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1561 struct hpsa_scsi_dev_t *dev[], int ndevices,
1562 struct hpsa_scsi_dev_t *logical_drive)
1563{
1564 struct raid_map_data *map = &logical_drive->raid_map;
1565 struct raid_map_disk_data *dd = &map->data[0];
1566 int i, j;
1567 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1568 le16_to_cpu(map->metadata_disks_per_row);
1569 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1570 le16_to_cpu(map->layout_map_count) *
1571 total_disks_per_row;
1572 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1573 total_disks_per_row;
1574 int qdepth;
1575
1576 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1577 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1578
d604f533
WS		 1579 logical_drive->nphysical_disks = nraid_map_entries;
1580
03383736
DB		 1581 qdepth = 0;
1582 for (i = 0; i < nraid_map_entries; i++) {
1583 logical_drive->phys_disk[i] = NULL;
1584 if (!logical_drive->offload_config)
1585 continue;
1586 for (j = 0; j < ndevices; j++) {
1d33d85d
DB		 1587 if (dev[j] == NULL)
1588 continue;
03383736
DB		 1589 if (dev[j]->devtype != TYPE_DISK)
1590 continue;
1591 if (is_logical_dev_addr_mode(dev[j]->scsi3addr))
1592 continue;
1593 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1594 continue;
1595
1596 logical_drive->phys_disk[i] = dev[j];
1597 if (i < nphys_disk)
1598 qdepth = min(h->nr_cmds, qdepth +
1599 logical_drive->phys_disk[i]->queue_depth);
1600 break;
1601 }
1602
1603 /*
1604 * This can happen if a physical drive is removed and
1605 * the logical drive is degraded. In that case, the RAID
1606 * map data will refer to a physical disk which isn't actually
1607 * present. And in that case offload_enabled should already
1608 * be 0, but we'll turn it off here just in case
1609 */
1610 if (!logical_drive->phys_disk[i]) {
1611 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1612 logical_drive->offload_to_be_enabled = 0;
1613 logical_drive->queue_depth = 8;
03383736
DB		 1614 }
1615 }
1616 if (nraid_map_entries)
1617 /*
1618 * This is correct for reads, too high for full stripe writes,
1619 * way too high for partial stripe writes
1620 */
1621 logical_drive->queue_depth = qdepth;
1622 else
1623 logical_drive->queue_depth = h->nr_cmds;
1624}
1625
1626static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1627 struct hpsa_scsi_dev_t *dev[], int ndevices)
1628{
1629 int i;
1630
1631 for (i = 0; i < ndevices; i++) {
1d33d85d
DB		 1632 if (dev[i] == NULL)
1633 continue;
03383736
DB		 1634 if (dev[i]->devtype != TYPE_DISK)
1635 continue;
1636 if (!is_logical_dev_addr_mode(dev[i]->scsi3addr))
1637 continue;
41ce4c35
SC		 1638
1639 /*
1640 * If offload is currently enabled, the RAID map and
1641 * phys_disk[] assignment *better* not be changing
1642 * and since it isn't changing, we do not need to
1643 * update it.
1644 */
1645 if (dev[i]->offload_enabled)
1646 continue;
1647
03383736
DB		 1648 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1649 }
1650}
1651
8aa60681 1652static void adjust_hpsa_scsi_table(struct ctlr_info *h,
edd16368
SC		 1653 struct hpsa_scsi_dev_t *sd[], int nsds)
1654{
1655 /* sd contains scsi3 addresses and devtypes, and inquiry
1656 * data. This function takes what's in sd to be the current
1657 * reality and updates h->dev[] to reflect that reality.
1658 */
1659 int i, entry, device_change, changes = 0;
1660 struct hpsa_scsi_dev_t *csd;
1661 unsigned long flags;
1662 struct hpsa_scsi_dev_t **added, **removed;
1663 int nadded, nremoved;
1664 struct Scsi_Host *sh = NULL;
1665
cfe5badc
ST		 1666 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1667 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1668
1669 if (!added || !removed) {
1670 dev_warn(&h->pdev->dev, "out of memory in "
1671 "adjust_hpsa_scsi_table\n");
1672 goto free_and_out;
1673 }
1674
1675 spin_lock_irqsave(&h->devlock, flags);
1676
1677 /* find any devices in h->dev[] that are not in
1678 * sd[] and remove them from h->dev[], and for any
1679 * devices which have changed, remove the old device
1680 * info and add the new device info.
bd9244f7
ST		 1681 * If minor device attributes change, just update
1682 * the existing device structure.
edd16368
SC		 1683 */
1684 i = 0;
1685 nremoved = 0;
1686 nadded = 0;
1687 while (i < h->ndevices) {
1688 csd = h->dev[i];
1689 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1690 if (device_change == DEVICE_NOT_FOUND) {
1691 changes++;
8aa60681 1692 hpsa_scsi_remove_entry(h, i, removed, &nremoved);
edd16368
SC		 1693 continue; /* remove ^^^, hence i not incremented */
1694 } else if (device_change == DEVICE_CHANGED) {
1695 changes++;
8aa60681 1696 hpsa_scsi_replace_entry(h, i, sd[entry],
2a8ccf31 1697 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1698 /* Set it to NULL to prevent it from being freed
1699 * at the bottom of hpsa_update_scsi_devices()
1700 */
1701 sd[entry] = NULL;
bd9244f7 1702 } else if (device_change == DEVICE_UPDATED) {
8aa60681 1703 hpsa_scsi_update_entry(h, i, sd[entry]);
edd16368
SC		 1704 }
1705 i++;
1706 }
1707
1708 /* Now, make sure every device listed in sd[] is also
1709 * listed in h->dev[], adding them if they aren't found
1710 */
1711
1712 for (i = 0; i < nsds; i++) {
1713 if (!sd[i]) /* if already added above. */
1714 continue;
9846590e
SC		 1715
1716 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1717 * as the SCSI mid-layer does not handle such devices well.
1718 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1719 * at 160Hz, and prevents the system from coming up.
1720 */
1721 if (sd[i]->volume_offline) {
1722 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1723 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1724 continue;
1725 }
1726
edd16368
SC		 1727 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1728 h->ndevices, &entry);
1729 if (device_change == DEVICE_NOT_FOUND) {
1730 changes++;
8aa60681 1731 if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
edd16368
SC		 1732 break;
1733 sd[i] = NULL; /* prevent from being freed later. */
1734 } else if (device_change == DEVICE_CHANGED) {
1735 /* should never happen... */
1736 changes++;
1737 dev_warn(&h->pdev->dev,
1738 "device unexpectedly changed.\n");
1739 /* but if it does happen, we just ignore that device */
1740 }
1741 }
41ce4c35
SC		 1742 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1743
1744 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1745 * any logical drives that need it enabled.
1746 */
1d33d85d
DB		 1747 for (i = 0; i < h->ndevices; i++) {
1748 if (h->dev[i] == NULL)
1749 continue;
41ce4c35 1750 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1d33d85d 1751 }
41ce4c35 1752
edd16368
SC		 1753 spin_unlock_irqrestore(&h->devlock, flags);
1754
9846590e
SC		 1755 /* Monitor devices which are in one of several NOT READY states to be
1756 * brought online later. This must be done without holding h->devlock,
1757 * so don't touch h->dev[]
1758 */
1759 for (i = 0; i < nsds; i++) {
1760 if (!sd[i]) /* if already added above. */
1761 continue;
1762 if (sd[i]->volume_offline)
1763 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1764 }
1765
edd16368
SC		 1766 /* Don't notify scsi mid layer of any changes the first time through
1767 * (or if there are no changes) scsi_scan_host will do it later the
1768 * first time through.
1769 */
8aa60681 1770 if (!changes)
edd16368
SC		 1771 goto free_and_out;
1772
1773 sh = h->scsi_host;
1774 /* Notify scsi mid layer of any removed devices */
1775 for (i = 0; i < nremoved; i++) {
1d33d85d
DB		 1776 if (removed[i] == NULL)
1777 continue;
41ce4c35
SC		 1778 if (removed[i]->expose_state & HPSA_SCSI_ADD) {
1779 struct scsi_device *sdev =
1780 scsi_device_lookup(sh, removed[i]->bus,
1781 removed[i]->target, removed[i]->lun);
1782 if (sdev != NULL) {
1783 scsi_remove_device(sdev);
1784 scsi_device_put(sdev);
1785 } else {
1786 /*
1787 * We don't expect to get here.
1788 * future cmds to this device will get selection
1789 * timeout as if the device was gone.
1790 */
0d96ef5f
WS		 1791 hpsa_show_dev_msg(KERN_WARNING, h, removed[i],
1792 "didn't find device for removal.");
41ce4c35 1793 }
edd16368
SC		 1794 }
1795 kfree(removed[i]);
1796 removed[i] = NULL;
1797 }
1798
1799 /* Notify scsi mid layer of any added devices */
1800 for (i = 0; i < nadded; i++) {
1d33d85d
DB		 1801 if (added[i] == NULL)
1802 continue;
41ce4c35
SC		 1803 if (!(added[i]->expose_state & HPSA_SCSI_ADD))
1804 continue;
edd16368
SC		 1805 if (scsi_add_device(sh, added[i]->bus,
1806 added[i]->target, added[i]->lun) == 0)
1807 continue;
1d33d85d 1808 dev_warn(&h->pdev->dev, "addition failed, device not added.");
edd16368
SC		 1809 /* now we have to remove it from h->dev,
1810 * since it didn't get added to scsi mid layer
1811 */
1812 fixup_botched_add(h, added[i]);
853633e8 1813 h->drv_req_rescan = 1;
edd16368
SC		 1814 }
1815
1816free_and_out:
1817 kfree(added);
1818 kfree(removed);
edd16368
SC		 1819}
1820
1821/*
9e03aa2f 1822 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1823 * Assume's h->devlock is held.
1824 */
1825static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1826 int bus, int target, int lun)
1827{
1828 int i;
1829 struct hpsa_scsi_dev_t *sd;
1830
1831 for (i = 0; i < h->ndevices; i++) {
1832 sd = h->dev[i];
1833 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1834 return sd;
1835 }
1836 return NULL;
1837}
1838
edd16368
SC		 1839static int hpsa_slave_alloc(struct scsi_device *sdev)
1840{
1841 struct hpsa_scsi_dev_t *sd;
1842 unsigned long flags;
1843 struct ctlr_info *h;
1844
1845 h = sdev_to_hba(sdev);
1846 spin_lock_irqsave(&h->devlock, flags);
1847 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1848 sdev_id(sdev), sdev->lun);
41ce4c35 1849 if (likely(sd)) {
03383736 1850 atomic_set(&sd->ioaccel_cmds_out, 0);
41ce4c35
SC		 1851 sdev->hostdata = (sd->expose_state & HPSA_SCSI_ADD) ? sd : NULL;
1852 } else
1853 sdev->hostdata = NULL;
edd16368
SC		 1854 spin_unlock_irqrestore(&h->devlock, flags);
1855 return 0;
1856}
1857
41ce4c35
SC		 1858/* configure scsi device based on internal per-device structure */
1859static int hpsa_slave_configure(struct scsi_device *sdev)
1860{
1861 struct hpsa_scsi_dev_t *sd;
1862 int queue_depth;
1863
1864 sd = sdev->hostdata;
1865 sdev->no_uld_attach = !sd || !(sd->expose_state & HPSA_ULD_ATTACH);
1866
1867 if (sd)
1868 queue_depth = sd->queue_depth != 0 ?
1869 sd->queue_depth : sdev->host->can_queue;
1870 else
1871 queue_depth = sdev->host->can_queue;
1872
1873 scsi_change_queue_depth(sdev, queue_depth);
1874
1875 return 0;
1876}
1877
edd16368
SC		 1878static void hpsa_slave_destroy(struct scsi_device *sdev)
1879{
bcc44255 1880 /* nothing to do. */
edd16368
SC		 1881}
1882
d9a729f3
WS		 1883static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1884{
1885 int i;
1886
1887 if (!h->ioaccel2_cmd_sg_list)
1888 return;
1889 for (i = 0; i < h->nr_cmds; i++) {
1890 kfree(h->ioaccel2_cmd_sg_list[i]);
1891 h->ioaccel2_cmd_sg_list[i] = NULL;
1892 }
1893 kfree(h->ioaccel2_cmd_sg_list);
1894 h->ioaccel2_cmd_sg_list = NULL;
1895}
1896
1897static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1898{
1899 int i;
1900
1901 if (h->chainsize <= 0)
1902 return 0;
1903
1904 h->ioaccel2_cmd_sg_list =
1905 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
1906 GFP_KERNEL);
1907 if (!h->ioaccel2_cmd_sg_list)
1908 return -ENOMEM;
1909 for (i = 0; i < h->nr_cmds; i++) {
1910 h->ioaccel2_cmd_sg_list[i] =
1911 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
1912 h->maxsgentries, GFP_KERNEL);
1913 if (!h->ioaccel2_cmd_sg_list[i])
1914 goto clean;
1915 }
1916 return 0;
1917
1918clean:
1919 hpsa_free_ioaccel2_sg_chain_blocks(h);
1920 return -ENOMEM;
1921}
1922
33a2ffce
SC		 1923static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1924{
1925 int i;
1926
1927 if (!h->cmd_sg_list)
1928 return;
1929 for (i = 0; i < h->nr_cmds; i++) {
1930 kfree(h->cmd_sg_list[i]);
1931 h->cmd_sg_list[i] = NULL;
1932 }
1933 kfree(h->cmd_sg_list);
1934 h->cmd_sg_list = NULL;
1935}
1936
105a3dbc 1937static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
33a2ffce
SC		 1938{
1939 int i;
1940
1941 if (h->chainsize <= 0)
1942 return 0;
1943
1944 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1945 GFP_KERNEL);
3d4e6af8
RE		 1946 if (!h->cmd_sg_list) {
1947 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1948 return -ENOMEM;
3d4e6af8 1949 }
33a2ffce
SC		 1950 for (i = 0; i < h->nr_cmds; i++) {
1951 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1952 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1953 if (!h->cmd_sg_list[i]) {
1954 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1955 goto clean;
3d4e6af8 1956 }
33a2ffce
SC		 1957 }
1958 return 0;
1959
1960clean:
1961 hpsa_free_sg_chain_blocks(h);
1962 return -ENOMEM;
1963}
1964
d9a729f3
WS		 1965static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
1966 struct io_accel2_cmd *cp, struct CommandList *c)
1967{
1968 struct ioaccel2_sg_element *chain_block;
1969 u64 temp64;
1970 u32 chain_size;
1971
1972 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
1973 chain_size = le32_to_cpu(cp->data_len);
1974 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
1975 PCI_DMA_TODEVICE);
1976 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1977 /* prevent subsequent unmapping */
1978 cp->sg->address = 0;
1979 return -1;
1980 }
1981 cp->sg->address = cpu_to_le64(temp64);
1982 return 0;
1983}
1984
1985static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
1986 struct io_accel2_cmd *cp)
1987{
1988 struct ioaccel2_sg_element *chain_sg;
1989 u64 temp64;
1990 u32 chain_size;
1991
1992 chain_sg = cp->sg;
1993 temp64 = le64_to_cpu(chain_sg->address);
1994 chain_size = le32_to_cpu(cp->data_len);
1995 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
1996}
1997
e2bea6df 1998static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1999 struct CommandList *c)
2000{
2001 struct SGDescriptor *chain_sg, *chain_block;
2002 u64 temp64;
50a0decf 2003 u32 chain_len;
33a2ffce
SC		 2004
2005 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
2006 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 2007 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
2008 chain_len = sizeof(*chain_sg) *
2b08b3e9 2009 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 2010 chain_sg->Len = cpu_to_le32(chain_len);
2011 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 2012 PCI_DMA_TODEVICE);
e2bea6df
SC		 2013 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2014 /* prevent subsequent unmapping */
50a0decf 2015 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 2016 return -1;
2017 }
50a0decf 2018 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 2019 return 0;
33a2ffce
SC		 2020}
2021
2022static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
2023 struct CommandList *c)
2024{
2025 struct SGDescriptor *chain_sg;
33a2ffce 2026
50a0decf 2027 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 2028 return;
2029
2030 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 2031 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
2032 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 2033}
2034
a09c1441
ST		 2035
2036/* Decode the various types of errors on ioaccel2 path.
2037 * Return 1 for any error that should generate a RAID path retry.
2038 * Return 0 for errors that don't require a RAID path retry.
2039 */
2040static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 2041 struct CommandList *c,
2042 struct scsi_cmnd *cmd,
2043 struct io_accel2_cmd *c2)
2044{
2045 int data_len;
a09c1441 2046 int retry = 0;
c40820d5 2047 u32 ioaccel2_resid = 0;
c349775e
ST		 2048
2049 switch (c2->error_data.serv_response) {
2050 case IOACCEL2_SERV_RESPONSE_COMPLETE:
2051 switch (c2->error_data.status) {
2052 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
2053 break;
2054 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
ee6b1889 2055 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 2056 if (c2->error_data.data_present !=
ee6b1889
SC		 2057 IOACCEL2_SENSE_DATA_PRESENT) {
2058 memset(cmd->sense_buffer, 0,
2059 SCSI_SENSE_BUFFERSIZE);
c349775e 2060 break;
ee6b1889 2061 }
c349775e
ST		 2062 /* copy the sense data */
2063 data_len = c2->error_data.sense_data_len;
2064 if (data_len > SCSI_SENSE_BUFFERSIZE)
2065 data_len = SCSI_SENSE_BUFFERSIZE;
2066 if (data_len > sizeof(c2->error_data.sense_data_buff))
2067 data_len =
2068 sizeof(c2->error_data.sense_data_buff);
2069 memcpy(cmd->sense_buffer,
2070 c2->error_data.sense_data_buff, data_len);
a09c1441 2071 retry = 1;
c349775e
ST		 2072 break;
2073 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
a09c1441 2074 retry = 1;
c349775e
ST		 2075 break;
2076 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
a09c1441 2077 retry = 1;
c349775e
ST		 2078 break;
2079 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 2080 retry = 1;
c349775e
ST		 2081 break;
2082 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
a09c1441 2083 retry = 1;
c349775e
ST		 2084 break;
2085 default:
a09c1441 2086 retry = 1;
c349775e
ST		 2087 break;
2088 }
2089 break;
2090 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 2091 switch (c2->error_data.status) {
2092 case IOACCEL2_STATUS_SR_IO_ERROR:
2093 case IOACCEL2_STATUS_SR_IO_ABORTED:
2094 case IOACCEL2_STATUS_SR_OVERRUN:
2095 retry = 1;
2096 break;
2097 case IOACCEL2_STATUS_SR_UNDERRUN:
2098 cmd->result = (DID_OK << 16); /* host byte */
2099 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2100 ioaccel2_resid = get_unaligned_le32(
2101 &c2->error_data.resid_cnt[0]);
2102 scsi_set_resid(cmd, ioaccel2_resid);
2103 break;
2104 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
2105 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
2106 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
2107 /* We will get an event from ctlr to trigger rescan */
2108 retry = 1;
2109 break;
2110 default:
2111 retry = 1;
c40820d5 2112 }
c349775e
ST		 2113 break;
2114 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
2115 break;
2116 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
2117 break;
2118 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
a09c1441 2119 retry = 1;
c349775e
ST		 2120 break;
2121 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
c349775e
ST		 2122 break;
2123 default:
a09c1441 2124 retry = 1;
c349775e
ST		 2125 break;
2126 }
a09c1441
ST		 2127
2128 return retry; /* retry on raid path? */
c349775e
ST		 2129}
2130
a58e7e53
WS		 2131static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2132 struct CommandList *c)
2133{
d604f533
WS		 2134 bool do_wake = false;
2135
a58e7e53
WS		 2136 /*
2137 * Prevent the following race in the abort handler:
2138 *
2139 * 1. LLD is requested to abort a SCSI command
2140 * 2. The SCSI command completes
2141 * 3. The struct CommandList associated with step 2 is made available
2142 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2143 * 5. Abort handler follows scsi_cmnd->host_scribble and
2144 * finds struct CommandList and tries to aborts it
2145 * Now we have aborted the wrong command.
2146 *
d604f533
WS		 2147 * Reset c->scsi_cmd here so that the abort or reset handler will know
2148 * this command has completed. Then, check to see if the handler is
a58e7e53
WS		 2149 * waiting for this command, and, if so, wake it.
2150 */
2151 c->scsi_cmd = SCSI_CMD_IDLE;
d604f533 2152 mb(); /* Declare command idle before checking for pending events. */
a58e7e53 2153 if (c->abort_pending) {
d604f533 2154 do_wake = true;
a58e7e53 2155 c->abort_pending = false;
a58e7e53 2156 }
d604f533
WS		 2157 if (c->reset_pending) {
2158 unsigned long flags;
2159 struct hpsa_scsi_dev_t *dev;
2160
2161 /*
2162 * There appears to be a reset pending; lock the lock and
2163 * reconfirm. If so, then decrement the count of outstanding
2164 * commands and wake the reset command if this is the last one.
2165 */
2166 spin_lock_irqsave(&h->lock, flags);
2167 dev = c->reset_pending; /* Re-fetch under the lock. */
2168 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2169 do_wake = true;
2170 c->reset_pending = NULL;
2171 spin_unlock_irqrestore(&h->lock, flags);
2172 }
2173
2174 if (do_wake)
2175 wake_up_all(&h->event_sync_wait_queue);
a58e7e53
WS		 2176}
2177
73153fe5
WS		 2178static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2179 struct CommandList *c)
2180{
2181 hpsa_cmd_resolve_events(h, c);
2182 cmd_tagged_free(h, c);
2183}
2184
8a0ff92c
WS		 2185static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2186 struct CommandList *c, struct scsi_cmnd *cmd)
2187{
73153fe5 2188 hpsa_cmd_resolve_and_free(h, c);
8a0ff92c
WS		 2189 cmd->scsi_done(cmd);
2190}
2191
2192static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2193{
2194 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2195 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2196}
2197
a58e7e53
WS		 2198static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2199{
2200 cmd->result = DID_ABORT << 16;
2201}
2202
2203static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2204 struct scsi_cmnd *cmd)
2205{
2206 hpsa_set_scsi_cmd_aborted(cmd);
2207 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2208 c->Request.CDB, c->err_info->ScsiStatus);
73153fe5 2209 hpsa_cmd_resolve_and_free(h, c);
a58e7e53
WS		 2210}
2211
c349775e
ST		 2212static void process_ioaccel2_completion(struct ctlr_info *h,
2213 struct CommandList *c, struct scsi_cmnd *cmd,
2214 struct hpsa_scsi_dev_t *dev)
2215{
2216 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2217
2218 /* check for good status */
2219 if (likely(c2->error_data.serv_response == 0 &&
8a0ff92c
WS		 2220 c2->error_data.status == 0))
2221 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e 2222
8a0ff92c
WS		 2223 /*
2224 * Any RAID offload error results in retry which will use
c349775e
ST		 2225 * the normal I/O path so the controller can handle whatever's
2226 * wrong.
2227 */
2228 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
2229 c2->error_data.serv_response ==
2230 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 2231 if (c2->error_data.status ==
2232 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
2233 dev->offload_enabled = 0;
8a0ff92c
WS		 2234
2235 return hpsa_retry_cmd(h, c);
a09c1441 2236 }
080ef1cc
DB		 2237
2238 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
8a0ff92c 2239 return hpsa_retry_cmd(h, c);
080ef1cc 2240
8a0ff92c 2241 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e
ST		 2242}
2243
9437ac43
SC		 2244/* Returns 0 on success, < 0 otherwise. */
2245static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2246 struct CommandList *cp)
2247{
2248 u8 tmf_status = cp->err_info->ScsiStatus;
2249
2250 switch (tmf_status) {
2251 case CISS_TMF_COMPLETE:
2252 /*
2253 * CISS_TMF_COMPLETE never happens, instead,
2254 * ei->CommandStatus == 0 for this case.
2255 */
2256 case CISS_TMF_SUCCESS:
2257 return 0;
2258 case CISS_TMF_INVALID_FRAME:
2259 case CISS_TMF_NOT_SUPPORTED:
2260 case CISS_TMF_FAILED:
2261 case CISS_TMF_WRONG_LUN:
2262 case CISS_TMF_OVERLAPPED_TAG:
2263 break;
2264 default:
2265 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2266 tmf_status);
2267 break;
2268 }
2269 return -tmf_status;
2270}
2271
1fb011fb 2272static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2273{
2274 struct scsi_cmnd *cmd;
2275 struct ctlr_info *h;
2276 struct ErrorInfo *ei;
283b4a9b 2277 struct hpsa_scsi_dev_t *dev;
d9a729f3 2278 struct io_accel2_cmd *c2;
edd16368 2279
9437ac43
SC		 2280 u8 sense_key;
2281 u8 asc; /* additional sense code */
2282 u8 ascq; /* additional sense code qualifier */
db111e18 2283 unsigned long sense_data_size;
edd16368
SC		 2284
2285 ei = cp->err_info;
7fa3030c 2286 cmd = cp->scsi_cmd;
edd16368 2287 h = cp->h;
283b4a9b 2288 dev = cmd->device->hostdata;
d9a729f3 2289 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2290
2291 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2292 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2293 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2294 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2295
d9a729f3
WS		 2296 if ((cp->cmd_type == CMD_IOACCEL2) &&
2297 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2298 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2299
edd16368
SC		 2300 cmd->result = (DID_OK << 16); /* host byte */
2301 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2302
03383736
DB		 2303 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2304 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2305
25163bd5
WS		 2306 /*
2307 * We check for lockup status here as it may be set for
2308 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2309 * fail_all_oustanding_cmds()
2310 */
2311 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2312 /* DID_NO_CONNECT will prevent a retry */
2313 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 2314 return hpsa_cmd_free_and_done(h, cp, cmd);
25163bd5
WS		 2315 }
2316
d604f533
WS		 2317 if ((unlikely(hpsa_is_pending_event(cp)))) {
2318 if (cp->reset_pending)
2319 return hpsa_cmd_resolve_and_free(h, cp);
2320 if (cp->abort_pending)
2321 return hpsa_cmd_abort_and_free(h, cp, cmd);
2322 }
2323
c349775e
ST		 2324 if (cp->cmd_type == CMD_IOACCEL2)
2325 return process_ioaccel2_completion(h, cp, cmd, dev);
2326
6aa4c361 2327 scsi_set_resid(cmd, ei->ResidualCnt);
8a0ff92c
WS		 2328 if (ei->CommandStatus == 0)
2329 return hpsa_cmd_free_and_done(h, cp, cmd);
6aa4c361 2330
e1f7de0c
MG		 2331 /* For I/O accelerator commands, copy over some fields to the normal
2332 * CISS header used below for error handling.
2333 */
2334 if (cp->cmd_type == CMD_IOACCEL1) {
2335 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2336 cp->Header.SGList = scsi_sg_count(cmd);
2337 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2338 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2339 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2340 cp->Header.tag = c->tag;
e1f7de0c
MG		 2341 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2342 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2343
2344 /* Any RAID offload error results in retry which will use
2345 * the normal I/O path so the controller can handle whatever's
2346 * wrong.
2347 */
2348 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
2349 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2350 dev->offload_enabled = 0;
d604f533 2351 return hpsa_retry_cmd(h, cp);
283b4a9b 2352 }
e1f7de0c
MG		 2353 }
2354
edd16368
SC		 2355 /* an error has occurred */
2356 switch (ei->CommandStatus) {
2357
2358 case CMD_TARGET_STATUS:
9437ac43
SC		 2359 cmd->result |= ei->ScsiStatus;
2360 /* copy the sense data */
2361 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2362 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2363 else
2364 sense_data_size = sizeof(ei->SenseInfo);
2365 if (ei->SenseLen < sense_data_size)
2366 sense_data_size = ei->SenseLen;
2367 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2368 if (ei->ScsiStatus)
2369 decode_sense_data(ei->SenseInfo, sense_data_size,
2370 &sense_key, &asc, &ascq);
edd16368 2371 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2372 if (sense_key == ABORTED_COMMAND) {
2e311fba 2373 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2374 break;
2375 }
edd16368
SC		 2376 break;
2377 }
edd16368
SC		 2378 /* Problem was not a check condition
2379 * Pass it up to the upper layers...
2380 */
2381 if (ei->ScsiStatus) {
2382 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2383 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2384 "Returning result: 0x%x\n",
2385 cp, ei->ScsiStatus,
2386 sense_key, asc, ascq,
2387 cmd->result);
2388 } else { /* scsi status is zero??? How??? */
2389 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2390 "Returning no connection.\n", cp),
2391
2392 /* Ordinarily, this case should never happen,
2393 * but there is a bug in some released firmware
2394 * revisions that allows it to happen if, for
2395 * example, a 4100 backplane loses power and
2396 * the tape drive is in it. We assume that
2397 * it's a fatal error of some kind because we
2398 * can't show that it wasn't. We will make it
2399 * look like selection timeout since that is
2400 * the most common reason for this to occur,
2401 * and it's severe enough.
2402 */
2403
2404 cmd->result = DID_NO_CONNECT << 16;
2405 }
2406 break;
2407
2408 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2409 break;
2410 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2411 dev_warn(&h->pdev->dev,
2412 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2413 break;
2414 case CMD_INVALID: {
2415 /* print_bytes(cp, sizeof(*cp), 1, 0);
2416 print_cmd(cp); */
2417 /* We get CMD_INVALID if you address a non-existent device
2418 * instead of a selection timeout (no response). You will
2419 * see this if you yank out a drive, then try to access it.
2420 * This is kind of a shame because it means that any other
2421 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2422 * missing target. */
2423 cmd->result = DID_NO_CONNECT << 16;
2424 }
2425 break;
2426 case CMD_PROTOCOL_ERR:
256d0eaa 2427 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2428 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2429 cp->Request.CDB);
edd16368
SC		 2430 break;
2431 case CMD_HARDWARE_ERR:
2432 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2433 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2434 cp->Request.CDB);
edd16368
SC		 2435 break;
2436 case CMD_CONNECTION_LOST:
2437 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2438 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2439 cp->Request.CDB);
edd16368
SC		 2440 break;
2441 case CMD_ABORTED:
a58e7e53
WS		 2442 /* Return now to avoid calling scsi_done(). */
2443 return hpsa_cmd_abort_and_free(h, cp, cmd);
edd16368
SC		 2444 case CMD_ABORT_FAILED:
2445 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2446 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2447 cp->Request.CDB);
edd16368
SC		 2448 break;
2449 case CMD_UNSOLICITED_ABORT:
f6e76055 2450 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2451 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2452 cp->Request.CDB);
edd16368
SC		 2453 break;
2454 case CMD_TIMEOUT:
2455 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2456 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2457 cp->Request.CDB);
edd16368 2458 break;
1d5e2ed0
SC		 2459 case CMD_UNABORTABLE:
2460 cmd->result = DID_ERROR << 16;
2461 dev_warn(&h->pdev->dev, "Command unabortable\n");
2462 break;
9437ac43
SC		 2463 case CMD_TMF_STATUS:
2464 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2465 cmd->result = DID_ERROR << 16;
2466 break;
283b4a9b
SC		 2467 case CMD_IOACCEL_DISABLED:
2468 /* This only handles the direct pass-through case since RAID
2469 * offload is handled above. Just attempt a retry.
2470 */
2471 cmd->result = DID_SOFT_ERROR << 16;
2472 dev_warn(&h->pdev->dev,
2473 "cp %p had HP SSD Smart Path error\n", cp);
2474 break;
edd16368
SC		 2475 default:
2476 cmd->result = DID_ERROR << 16;
2477 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2478 cp, ei->CommandStatus);
2479 }
8a0ff92c
WS		 2480
2481 return hpsa_cmd_free_and_done(h, cp, cmd);
edd16368
SC		 2482}
2483
edd16368
SC		 2484static void hpsa_pci_unmap(struct pci_dev *pdev,
2485 struct CommandList *c, int sg_used, int data_direction)
2486{
2487 int i;
edd16368 2488
50a0decf
SC		 2489 for (i = 0; i < sg_used; i++)
2490 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2491 le32_to_cpu(c->SG[i].Len),
2492 data_direction);
edd16368
SC		 2493}
2494
a2dac136 2495static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2496 struct CommandList *cp,
2497 unsigned char *buf,
2498 size_t buflen,
2499 int data_direction)
2500{
01a02ffc 2501 u64 addr64;
edd16368
SC		 2502
2503 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2504 cp->Header.SGList = 0;
50a0decf 2505 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2506 return 0;
edd16368
SC		 2507 }
2508
50a0decf 2509 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2510 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2511 /* Prevent subsequent unmap of something never mapped */
eceaae18 2512 cp->Header.SGList = 0;
50a0decf 2513 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2514 return -1;
eceaae18 2515 }
50a0decf
SC		 2516 cp->SG[0].Addr = cpu_to_le64(addr64);
2517 cp->SG[0].Len = cpu_to_le32(buflen);
2518 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2519 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2520 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2521 return 0;
edd16368
SC		 2522}
2523
25163bd5
WS		 2524#define NO_TIMEOUT ((unsigned long) -1)
2525#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2526static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2527 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2528{
2529 DECLARE_COMPLETION_ONSTACK(wait);
2530
2531 c->waiting = &wait;
25163bd5
WS		 2532 __enqueue_cmd_and_start_io(h, c, reply_queue);
2533 if (timeout_msecs == NO_TIMEOUT) {
2534 /* TODO: get rid of this no-timeout thing */
2535 wait_for_completion_io(&wait);
2536 return IO_OK;
2537 }
2538 if (!wait_for_completion_io_timeout(&wait,
2539 msecs_to_jiffies(timeout_msecs))) {
2540 dev_warn(&h->pdev->dev, "Command timed out.\n");
2541 return -ETIMEDOUT;
2542 }
2543 return IO_OK;
2544}
2545
2546static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2547 int reply_queue, unsigned long timeout_msecs)
2548{
2549 if (unlikely(lockup_detected(h))) {
2550 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2551 return IO_OK;
2552 }
2553 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2554}
2555
094963da
SC		 2556static u32 lockup_detected(struct ctlr_info *h)
2557{
2558 int cpu;
2559 u32 rc, *lockup_detected;
2560
2561 cpu = get_cpu();
2562 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2563 rc = *lockup_detected;
2564 put_cpu();
2565 return rc;
2566}
2567
9c2fc160 2568#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2569static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2570 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2571{
9c2fc160 2572 int backoff_time = 10, retry_count = 0;
25163bd5 2573 int rc;
edd16368
SC		 2574
2575 do {
7630abd0 2576 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2577 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2578 timeout_msecs);
2579 if (rc)
2580 break;
edd16368 2581 retry_count++;
9c2fc160
SC		 2582 if (retry_count > 3) {
2583 msleep(backoff_time);
2584 if (backoff_time < 1000)
2585 backoff_time *= 2;
2586 }
852af20a 2587 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2588 check_for_busy(h, c)) &&
2589 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2590 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2591 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2592 rc = -EIO;
2593 return rc;
edd16368
SC		 2594}
2595
d1e8beac
SC		 2596static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2597 struct CommandList *c)
edd16368 2598{
d1e8beac
SC		 2599 const u8 *cdb = c->Request.CDB;
2600 const u8 *lun = c->Header.LUN.LunAddrBytes;
2601
2602 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2603 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2604 txt, lun[0], lun[1], lun[2], lun[3],
2605 lun[4], lun[5], lun[6], lun[7],
2606 cdb[0], cdb[1], cdb[2], cdb[3],
2607 cdb[4], cdb[5], cdb[6], cdb[7],
2608 cdb[8], cdb[9], cdb[10], cdb[11],
2609 cdb[12], cdb[13], cdb[14], cdb[15]);
2610}
2611
2612static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2613 struct CommandList *cp)
2614{
2615 const struct ErrorInfo *ei = cp->err_info;
edd16368 2616 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2617 u8 sense_key, asc, ascq;
2618 int sense_len;
edd16368 2619
edd16368
SC		 2620 switch (ei->CommandStatus) {
2621 case CMD_TARGET_STATUS:
9437ac43
SC		 2622 if (ei->SenseLen > sizeof(ei->SenseInfo))
2623 sense_len = sizeof(ei->SenseInfo);
2624 else
2625 sense_len = ei->SenseLen;
2626 decode_sense_data(ei->SenseInfo, sense_len,
2627 &sense_key, &asc, &ascq);
d1e8beac
SC		 2628 hpsa_print_cmd(h, "SCSI status", cp);
2629 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2630 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2631 sense_key, asc, ascq);
d1e8beac 2632 else
9437ac43 2633 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2634 if (ei->ScsiStatus == 0)
2635 dev_warn(d, "SCSI status is abnormally zero. "
2636 "(probably indicates selection timeout "
2637 "reported incorrectly due to a known "
2638 "firmware bug, circa July, 2001.)\n");
2639 break;
2640 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2641 break;
2642 case CMD_DATA_OVERRUN:
d1e8beac 2643 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2644 break;
2645 case CMD_INVALID: {
2646 /* controller unfortunately reports SCSI passthru's
2647 * to non-existent targets as invalid commands.
2648 */
d1e8beac
SC		 2649 hpsa_print_cmd(h, "invalid command", cp);
2650 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2651 }
2652 break;
2653 case CMD_PROTOCOL_ERR:
d1e8beac 2654 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2655 break;
2656 case CMD_HARDWARE_ERR:
d1e8beac 2657 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2658 break;
2659 case CMD_CONNECTION_LOST:
d1e8beac 2660 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2661 break;
2662 case CMD_ABORTED:
d1e8beac 2663 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2664 break;
2665 case CMD_ABORT_FAILED:
d1e8beac 2666 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2667 break;
2668 case CMD_UNSOLICITED_ABORT:
d1e8beac 2669 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2670 break;
2671 case CMD_TIMEOUT:
d1e8beac 2672 hpsa_print_cmd(h, "timed out", cp);
edd16368 2673 break;
1d5e2ed0 2674 case CMD_UNABORTABLE:
d1e8beac 2675 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2676 break;
25163bd5
WS		 2677 case CMD_CTLR_LOCKUP:
2678 hpsa_print_cmd(h, "controller lockup detected", cp);
2679 break;
edd16368 2680 default:
d1e8beac
SC		 2681 hpsa_print_cmd(h, "unknown status", cp);
2682 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2683 ei->CommandStatus);
2684 }
2685}
2686
2687static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2688 u16 page, unsigned char *buf,
edd16368
SC		 2689 unsigned char bufsize)
2690{
2691 int rc = IO_OK;
2692 struct CommandList *c;
2693 struct ErrorInfo *ei;
2694
45fcb86e 2695 c = cmd_alloc(h);
edd16368 2696
a2dac136
SC		 2697 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2698 page, scsi3addr, TYPE_CMD)) {
2699 rc = -1;
2700 goto out;
2701 }
25163bd5
WS		 2702 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2703 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2704 if (rc)
2705 goto out;
edd16368
SC		 2706 ei = c->err_info;
2707 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2708 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2709 rc = -1;
2710 }
a2dac136 2711out:
45fcb86e 2712 cmd_free(h, c);
edd16368
SC		 2713 return rc;
2714}
2715
bf711ac6 2716static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2717 u8 reset_type, int reply_queue)
edd16368
SC		 2718{
2719 int rc = IO_OK;
2720 struct CommandList *c;
2721 struct ErrorInfo *ei;
2722
45fcb86e 2723 c = cmd_alloc(h);
edd16368 2724
edd16368 2725
a2dac136 2726 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2727 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2728 scsi3addr, TYPE_MSG);
2729 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
25163bd5
WS		 2730 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2731 if (rc) {
2732 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2733 goto out;
2734 }
edd16368
SC		 2735 /* no unmap needed here because no data xfer. */
2736
2737 ei = c->err_info;
2738 if (ei->CommandStatus != 0) {
d1e8beac 2739 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2740 rc = -1;
2741 }
25163bd5 2742out:
45fcb86e 2743 cmd_free(h, c);
edd16368
SC		 2744 return rc;
2745}
2746
d604f533
WS		 2747static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2748 struct hpsa_scsi_dev_t *dev,
2749 unsigned char *scsi3addr)
2750{
2751 int i;
2752 bool match = false;
2753 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2754 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2755
2756 if (hpsa_is_cmd_idle(c))
2757 return false;
2758
2759 switch (c->cmd_type) {
2760 case CMD_SCSI:
2761 case CMD_IOCTL_PEND:
2762 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2763 sizeof(c->Header.LUN.LunAddrBytes));
2764 break;
2765
2766 case CMD_IOACCEL1:
2767 case CMD_IOACCEL2:
2768 if (c->phys_disk == dev) {
2769 /* HBA mode match */
2770 match = true;
2771 } else {
2772 /* Possible RAID mode -- check each phys dev. */
2773 /* FIXME: Do we need to take out a lock here? If
2774 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2775 * instead. */
2776 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2777 /* FIXME: an alternate test might be
2778 *
2779 * match = dev->phys_disk[i]->ioaccel_handle
2780 * == c2->scsi_nexus; */
2781 match = dev->phys_disk[i] == c->phys_disk;
2782 }
2783 }
2784 break;
2785
2786 case IOACCEL2_TMF:
2787 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2788 match = dev->phys_disk[i]->ioaccel_handle ==
2789 le32_to_cpu(ac->it_nexus);
2790 }
2791 break;
2792
2793 case 0: /* The command is in the middle of being initialized. */
2794 match = false;
2795 break;
2796
2797 default:
2798 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
2799 c->cmd_type);
2800 BUG();
2801 }
2802
2803 return match;
2804}
2805
2806static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
2807 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
2808{
2809 int i;
2810 int rc = 0;
2811
2812 /* We can really only handle one reset at a time */
2813 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
2814 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
2815 return -EINTR;
2816 }
2817
2818 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
2819
2820 for (i = 0; i < h->nr_cmds; i++) {
2821 struct CommandList *c = h->cmd_pool + i;
2822 int refcount = atomic_inc_return(&c->refcount);
2823
2824 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
2825 unsigned long flags;
2826
2827 /*
2828 * Mark the target command as having a reset pending,
2829 * then lock a lock so that the command cannot complete
2830 * while we're considering it. If the command is not
2831 * idle then count it; otherwise revoke the event.
2832 */
2833 c->reset_pending = dev;
2834 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
2835 if (!hpsa_is_cmd_idle(c))
2836 atomic_inc(&dev->reset_cmds_out);
2837 else
2838 c->reset_pending = NULL;
2839 spin_unlock_irqrestore(&h->lock, flags);
2840 }
2841
2842 cmd_free(h, c);
2843 }
2844
2845 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
2846 if (!rc)
2847 wait_event(h->event_sync_wait_queue,
2848 atomic_read(&dev->reset_cmds_out) == 0 ||
2849 lockup_detected(h));
2850
2851 if (unlikely(lockup_detected(h))) {
77678d3a
DB		 2852 dev_warn(&h->pdev->dev,
2853 "Controller lockup detected during reset wait\n");
2854 rc = -ENODEV;
2855 }
d604f533
WS		 2856
2857 if (unlikely(rc))
2858 atomic_set(&dev->reset_cmds_out, 0);
2859
2860 mutex_unlock(&h->reset_mutex);
2861 return rc;
2862}
2863
edd16368
SC		 2864static void hpsa_get_raid_level(struct ctlr_info *h,
2865 unsigned char *scsi3addr, unsigned char *raid_level)
2866{
2867 int rc;
2868 unsigned char *buf;
2869
2870 *raid_level = RAID_UNKNOWN;
2871 buf = kzalloc(64, GFP_KERNEL);
2872 if (!buf)
2873 return;
b7bb24eb 2874 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2875 if (rc == 0)
2876 *raid_level = buf[8];
2877 if (*raid_level > RAID_UNKNOWN)
2878 *raid_level = RAID_UNKNOWN;
2879 kfree(buf);
2880 return;
2881}
2882
283b4a9b
SC		 2883#define HPSA_MAP_DEBUG
2884#ifdef HPSA_MAP_DEBUG
2885static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2886 struct raid_map_data *map_buff)
2887{
2888 struct raid_map_disk_data *dd = &map_buff->data[0];
2889 int map, row, col;
2890 u16 map_cnt, row_cnt, disks_per_row;
2891
2892 if (rc != 0)
2893 return;
2894
2ba8bfc8
SC		 2895 /* Show details only if debugging has been activated. */
2896 if (h->raid_offload_debug < 2)
2897 return;
2898
283b4a9b
SC		 2899 dev_info(&h->pdev->dev, "structure_size = %u\n",
2900 le32_to_cpu(map_buff->structure_size));
2901 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2902 le32_to_cpu(map_buff->volume_blk_size));
2903 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2904 le64_to_cpu(map_buff->volume_blk_cnt));
2905 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2906 map_buff->phys_blk_shift);
2907 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2908 map_buff->parity_rotation_shift);
2909 dev_info(&h->pdev->dev, "strip_size = %u\n",
2910 le16_to_cpu(map_buff->strip_size));
2911 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2912 le64_to_cpu(map_buff->disk_starting_blk));
2913 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2914 le64_to_cpu(map_buff->disk_blk_cnt));
2915 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2916 le16_to_cpu(map_buff->data_disks_per_row));
2917 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2918 le16_to_cpu(map_buff->metadata_disks_per_row));
2919 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2920 le16_to_cpu(map_buff->row_cnt));
2921 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2922 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2923 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2924 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2925 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2926 le16_to_cpu(map_buff->flags) &
2927 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2928 dev_info(&h->pdev->dev, "dekindex = %u\n",
2929 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2930 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2931 for (map = 0; map < map_cnt; map++) {
2932 dev_info(&h->pdev->dev, "Map%u:\n", map);
2933 row_cnt = le16_to_cpu(map_buff->row_cnt);
2934 for (row = 0; row < row_cnt; row++) {
2935 dev_info(&h->pdev->dev, " Row%u:\n", row);
2936 disks_per_row =
2937 le16_to_cpu(map_buff->data_disks_per_row);
2938 for (col = 0; col < disks_per_row; col++, dd++)
2939 dev_info(&h->pdev->dev,
2940 " D%02u: h=0x%04x xor=%u,%u\n",
2941 col, dd->ioaccel_handle,
2942 dd->xor_mult[0], dd->xor_mult[1]);
2943 disks_per_row =
2944 le16_to_cpu(map_buff->metadata_disks_per_row);
2945 for (col = 0; col < disks_per_row; col++, dd++)
2946 dev_info(&h->pdev->dev,
2947 " M%02u: h=0x%04x xor=%u,%u\n",
2948 col, dd->ioaccel_handle,
2949 dd->xor_mult[0], dd->xor_mult[1]);
2950 }
2951 }
2952}
2953#else
2954static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2955 __attribute__((unused)) int rc,
2956 __attribute__((unused)) struct raid_map_data *map_buff)
2957{
2958}
2959#endif
2960
2961static int hpsa_get_raid_map(struct ctlr_info *h,
2962 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2963{
2964 int rc = 0;
2965 struct CommandList *c;
2966 struct ErrorInfo *ei;
2967
45fcb86e 2968 c = cmd_alloc(h);
bf43caf3 2969
283b4a9b
SC		 2970 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2971 sizeof(this_device->raid_map), 0,
2972 scsi3addr, TYPE_CMD)) {
2dd02d74
RE		 2973 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
2974 cmd_free(h, c);
2975 return -1;
283b4a9b 2976 }
25163bd5
WS		 2977 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2978 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2979 if (rc)
2980 goto out;
283b4a9b
SC		 2981 ei = c->err_info;
2982 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2983 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 2984 rc = -1;
2985 goto out;
283b4a9b 2986 }
45fcb86e 2987 cmd_free(h, c);
283b4a9b
SC		 2988
2989 /* @todo in the future, dynamically allocate RAID map memory */
2990 if (le32_to_cpu(this_device->raid_map.structure_size) >
2991 sizeof(this_device->raid_map)) {
2992 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2993 rc = -1;
2994 }
2995 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2996 return rc;
25163bd5
WS		 2997out:
2998 cmd_free(h, c);
2999 return rc;
283b4a9b
SC		 3000}
3001
03383736
DB		 3002static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
3003 unsigned char scsi3addr[], u16 bmic_device_index,
3004 struct bmic_identify_physical_device *buf, size_t bufsize)
3005{
3006 int rc = IO_OK;
3007 struct CommandList *c;
3008 struct ErrorInfo *ei;
3009
3010 c = cmd_alloc(h);
3011 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
3012 0, RAID_CTLR_LUNID, TYPE_CMD);
3013 if (rc)
3014 goto out;
3015
3016 c->Request.CDB[2] = bmic_device_index & 0xff;
3017 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3018
25163bd5
WS		 3019 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
3020 NO_TIMEOUT);
03383736
DB		 3021 ei = c->err_info;
3022 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3023 hpsa_scsi_interpret_error(h, c);
3024 rc = -1;
3025 }
3026out:
3027 cmd_free(h, c);
3028 return rc;
3029}
3030
1b70150a
SC		 3031static int hpsa_vpd_page_supported(struct ctlr_info *h,
3032 unsigned char scsi3addr[], u8 page)
3033{
3034 int rc;
3035 int i;
3036 int pages;
3037 unsigned char *buf, bufsize;
3038
3039 buf = kzalloc(256, GFP_KERNEL);
3040 if (!buf)
3041 return 0;
3042
3043 /* Get the size of the page list first */
3044 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3045 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3046 buf, HPSA_VPD_HEADER_SZ);
3047 if (rc != 0)
3048 goto exit_unsupported;
3049 pages = buf[3];
3050 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3051 bufsize = pages + HPSA_VPD_HEADER_SZ;
3052 else
3053 bufsize = 255;
3054
3055 /* Get the whole VPD page list */
3056 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3057 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3058 buf, bufsize);
3059 if (rc != 0)
3060 goto exit_unsupported;
3061
3062 pages = buf[3];
3063 for (i = 1; i <= pages; i++)
3064 if (buf[3 + i] == page)
3065 goto exit_supported;
3066exit_unsupported:
3067 kfree(buf);
3068 return 0;
3069exit_supported:
3070 kfree(buf);
3071 return 1;
3072}
3073
283b4a9b
SC		 3074static void hpsa_get_ioaccel_status(struct ctlr_info *h,
3075 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3076{
3077 int rc;
3078 unsigned char *buf;
3079 u8 ioaccel_status;
3080
3081 this_device->offload_config = 0;
3082 this_device->offload_enabled = 0;
41ce4c35 3083 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 3084
3085 buf = kzalloc(64, GFP_KERNEL);
3086 if (!buf)
3087 return;
1b70150a
SC		 3088 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
3089 goto out;
283b4a9b 3090 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 3091 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 3092 if (rc != 0)
3093 goto out;
3094
3095#define IOACCEL_STATUS_BYTE 4
3096#define OFFLOAD_CONFIGURED_BIT 0x01
3097#define OFFLOAD_ENABLED_BIT 0x02
3098 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
3099 this_device->offload_config =
3100 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3101 if (this_device->offload_config) {
3102 this_device->offload_enabled =
3103 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3104 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3105 this_device->offload_enabled = 0;
3106 }
41ce4c35 3107 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 3108out:
3109 kfree(buf);
3110 return;
3111}
3112
edd16368
SC		 3113/* Get the device id from inquiry page 0x83 */
3114static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
3115 unsigned char *device_id, int buflen)
3116{
3117 int rc;
3118 unsigned char *buf;
3119
3120 if (buflen > 16)
3121 buflen = 16;
3122 buf = kzalloc(64, GFP_KERNEL);
3123 if (!buf)
a84d794d 3124 return -ENOMEM;
b7bb24eb 3125 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 3126 if (rc == 0)
3127 memcpy(device_id, &buf[8], buflen);
3128 kfree(buf);
3129 return rc != 0;
3130}
3131
3132static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 3133 void *buf, int bufsize,
edd16368
SC		 3134 int extended_response)
3135{
3136 int rc = IO_OK;
3137 struct CommandList *c;
3138 unsigned char scsi3addr[8];
3139 struct ErrorInfo *ei;
3140
45fcb86e 3141 c = cmd_alloc(h);
bf43caf3 3142
e89c0ae7
SC		 3143 /* address the controller */
3144 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 3145 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3146 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3147 rc = -1;
3148 goto out;
3149 }
edd16368
SC		 3150 if (extended_response)
3151 c->Request.CDB[1] = extended_response;
25163bd5
WS		 3152 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3153 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3154 if (rc)
3155 goto out;
edd16368
SC		 3156 ei = c->err_info;
3157 if (ei->CommandStatus != 0 &&
3158 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3159 hpsa_scsi_interpret_error(h, c);
edd16368 3160 rc = -1;
283b4a9b 3161 } else {
03383736
DB		 3162 struct ReportLUNdata *rld = buf;
3163
3164 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 3165 dev_err(&h->pdev->dev,
3166 "report luns requested format %u, got %u\n",
3167 extended_response,
03383736 3168 rld->extended_response_flag);
283b4a9b
SC		 3169 rc = -1;
3170 }
edd16368 3171 }
a2dac136 3172out:
45fcb86e 3173 cmd_free(h, c);
edd16368
SC		 3174 return rc;
3175}
3176
3177static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 3178 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 3179{
03383736
DB		 3180 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3181 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 3182}
3183
3184static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3185 struct ReportLUNdata *buf, int bufsize)
3186{
3187 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3188}
3189
3190static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3191 int bus, int target, int lun)
3192{
3193 device->bus = bus;
3194 device->target = target;
3195 device->lun = lun;
3196}
3197
9846590e
SC		 3198/* Use VPD inquiry to get details of volume status */
3199static int hpsa_get_volume_status(struct ctlr_info *h,
3200 unsigned char scsi3addr[])
3201{
3202 int rc;
3203 int status;
3204 int size;
3205 unsigned char *buf;
3206
3207 buf = kzalloc(64, GFP_KERNEL);
3208 if (!buf)
3209 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3210
3211 /* Does controller have VPD for logical volume status? */
24a4b078 3212 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 3213 goto exit_failed;
9846590e
SC		 3214
3215 /* Get the size of the VPD return buffer */
3216 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3217 buf, HPSA_VPD_HEADER_SZ);
24a4b078 3218 if (rc != 0)
9846590e 3219 goto exit_failed;
9846590e
SC		 3220 size = buf[3];
3221
3222 /* Now get the whole VPD buffer */
3223 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3224 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 3225 if (rc != 0)
9846590e 3226 goto exit_failed;
9846590e
SC		 3227 status = buf[4]; /* status byte */
3228
3229 kfree(buf);
3230 return status;
3231exit_failed:
3232 kfree(buf);
3233 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3234}
3235
3236/* Determine offline status of a volume.
3237 * Return either:
3238 * 0 (not offline)
67955ba3 3239 * 0xff (offline for unknown reasons)
9846590e
SC		 3240 * # (integer code indicating one of several NOT READY states
3241 * describing why a volume is to be kept offline)
3242 */
67955ba3 3243static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 3244 unsigned char scsi3addr[])
3245{
3246 struct CommandList *c;
9437ac43
SC		 3247 unsigned char *sense;
3248 u8 sense_key, asc, ascq;
3249 int sense_len;
25163bd5 3250 int rc, ldstat = 0;
9846590e
SC		 3251 u16 cmd_status;
3252 u8 scsi_status;
3253#define ASC_LUN_NOT_READY 0x04
3254#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3255#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3256
3257 c = cmd_alloc(h);
bf43caf3 3258
9846590e 3259 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
25163bd5
WS		 3260 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3261 if (rc) {
3262 cmd_free(h, c);
3263 return 0;
3264 }
9846590e 3265 sense = c->err_info->SenseInfo;
9437ac43
SC		 3266 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3267 sense_len = sizeof(c->err_info->SenseInfo);
3268 else
3269 sense_len = c->err_info->SenseLen;
3270 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 3271 cmd_status = c->err_info->CommandStatus;
3272 scsi_status = c->err_info->ScsiStatus;
3273 cmd_free(h, c);
3274 /* Is the volume 'not ready'? */
3275 if (cmd_status != CMD_TARGET_STATUS ||
3276 scsi_status != SAM_STAT_CHECK_CONDITION ||
3277 sense_key != NOT_READY ||
3278 asc != ASC_LUN_NOT_READY) {
3279 return 0;
3280 }
3281
3282 /* Determine the reason for not ready state */
3283 ldstat = hpsa_get_volume_status(h, scsi3addr);
3284
3285 /* Keep volume offline in certain cases: */
3286 switch (ldstat) {
3287 case HPSA_LV_UNDERGOING_ERASE:
5ca01204 3288 case HPSA_LV_NOT_AVAILABLE:
9846590e
SC		 3289 case HPSA_LV_UNDERGOING_RPI:
3290 case HPSA_LV_PENDING_RPI:
3291 case HPSA_LV_ENCRYPTED_NO_KEY:
3292 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3293 case HPSA_LV_UNDERGOING_ENCRYPTION:
3294 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3295 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3296 return ldstat;
3297 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3298 /* If VPD status page isn't available,
3299 * use ASC/ASCQ to determine state
3300 */
3301 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3302 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3303 return ldstat;
3304 break;
3305 default:
3306 break;
3307 }
3308 return 0;
3309}
3310
9b5c48c2
SC		 3311/*
3312 * Find out if a logical device supports aborts by simply trying one.
3313 * Smart Array may claim not to support aborts on logical drives, but
3314 * if a MSA2000 * is connected, the drives on that will be presented
3315 * by the Smart Array as logical drives, and aborts may be sent to
3316 * those devices successfully. So the simplest way to find out is
3317 * to simply try an abort and see how the device responds.
3318 */
3319static int hpsa_device_supports_aborts(struct ctlr_info *h,
3320 unsigned char *scsi3addr)
3321{
3322 struct CommandList *c;
3323 struct ErrorInfo *ei;
3324 int rc = 0;
3325
3326 u64 tag = (u64) -1; /* bogus tag */
3327
3328 /* Assume that physical devices support aborts */
3329 if (!is_logical_dev_addr_mode(scsi3addr))
3330 return 1;
3331
3332 c = cmd_alloc(h);
bf43caf3 3333
9b5c48c2
SC		 3334 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
3335 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3336 /* no unmap needed here because no data xfer. */
3337 ei = c->err_info;
3338 switch (ei->CommandStatus) {
3339 case CMD_INVALID:
3340 rc = 0;
3341 break;
3342 case CMD_UNABORTABLE:
3343 case CMD_ABORT_FAILED:
3344 rc = 1;
3345 break;
9437ac43
SC		 3346 case CMD_TMF_STATUS:
3347 rc = hpsa_evaluate_tmf_status(h, c);
3348 break;
9b5c48c2
SC		 3349 default:
3350 rc = 0;
3351 break;
3352 }
3353 cmd_free(h, c);
3354 return rc;
3355}
3356
edd16368 3357static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3358 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3359 unsigned char *is_OBDR_device)
edd16368 3360{
0b0e1d6c
SC		 3361
3362#define OBDR_SIG_OFFSET 43
3363#define OBDR_TAPE_SIG "$DR-10"
3364#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3365#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3366
ea6d3bc3 3367 unsigned char *inq_buff;
0b0e1d6c 3368 unsigned char *obdr_sig;
edd16368 3369
ea6d3bc3 3370 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 3371 if (!inq_buff)
3372 goto bail_out;
3373
edd16368
SC		 3374 /* Do an inquiry to the device to see what it is. */
3375 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3376 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3377 /* Inquiry failed (msg printed already) */
3378 dev_err(&h->pdev->dev,
3379 "hpsa_update_device_info: inquiry failed\n");
3380 goto bail_out;
3381 }
3382
edd16368
SC		 3383 this_device->devtype = (inq_buff[0] & 0x1f);
3384 memcpy(this_device->scsi3addr, scsi3addr, 8);
3385 memcpy(this_device->vendor, &inq_buff[8],
3386 sizeof(this_device->vendor));
3387 memcpy(this_device->model, &inq_buff[16],
3388 sizeof(this_device->model));
edd16368
SC		 3389 memset(this_device->device_id, 0,
3390 sizeof(this_device->device_id));
3391 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
3392 sizeof(this_device->device_id));
3393
3394 if (this_device->devtype == TYPE_DISK &&
283b4a9b 3395 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3396 int volume_offline;
3397
edd16368 3398 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3399 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3400 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3401 volume_offline = hpsa_volume_offline(h, scsi3addr);
3402 if (volume_offline < 0 || volume_offline > 0xff)
3403 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3404 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3405 } else {
edd16368 3406 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3407 this_device->offload_config = 0;
3408 this_device->offload_enabled = 0;
41ce4c35 3409 this_device->offload_to_be_enabled = 0;
a3144e0b 3410 this_device->hba_ioaccel_enabled = 0;
9846590e 3411 this_device->volume_offline = 0;
03383736 3412 this_device->queue_depth = h->nr_cmds;
283b4a9b 3413 }
edd16368 3414
0b0e1d6c
SC		 3415 if (is_OBDR_device) {
3416 /* See if this is a One-Button-Disaster-Recovery device
3417 * by looking for "$DR-10" at offset 43 in inquiry data.
3418 */
3419 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3420 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3421 strncmp(obdr_sig, OBDR_TAPE_SIG,
3422 OBDR_SIG_LEN) == 0);
3423 }
edd16368
SC		 3424 kfree(inq_buff);
3425 return 0;
3426
3427bail_out:
3428 kfree(inq_buff);
3429 return 1;
3430}
3431
9b5c48c2
SC		 3432static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3433 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3434{
3435 unsigned long flags;
3436 int rc, entry;
3437 /*
3438 * See if this device supports aborts. If we already know
3439 * the device, we already know if it supports aborts, otherwise
3440 * we have to find out if it supports aborts by trying one.
3441 */
3442 spin_lock_irqsave(&h->devlock, flags);
3443 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3444 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3445 entry >= 0 && entry < h->ndevices) {
3446 dev->supports_aborts = h->dev[entry]->supports_aborts;
3447 spin_unlock_irqrestore(&h->devlock, flags);
3448 } else {
3449 spin_unlock_irqrestore(&h->devlock, flags);
3450 dev->supports_aborts =
3451 hpsa_device_supports_aborts(h, scsi3addr);
3452 if (dev->supports_aborts < 0)
3453 dev->supports_aborts = 0;
3454 }
3455}
3456
4f4eb9f1 3457static unsigned char *ext_target_model[] = {
edd16368
SC		 3458 "MSA2012",
3459 "MSA2024",
3460 "MSA2312",
3461 "MSA2324",
fda38518 3462 "P2000 G3 SAS",
e06c8e5c 3463 "MSA 2040 SAS",
edd16368
SC		 3464 NULL,
3465};
3466
4f4eb9f1 3467static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 3468{
3469 int i;
3470
4f4eb9f1
ST		 3471 for (i = 0; ext_target_model[i]; i++)
3472 if (strncmp(device->model, ext_target_model[i],
3473 strlen(ext_target_model[i])) == 0)
edd16368
SC		 3474 return 1;
3475 return 0;
3476}
3477
3478/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 3479 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 3480 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
3481 * Logical drive target and lun are assigned at this time, but
3482 * physical device lun and target assignment are deferred (assigned
3483 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
3484 */
3485static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3486 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3487{
1f310bde
SC		 3488 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
3489
3490 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3491 /* physical device, target and lun filled in later */
edd16368 3492 if (is_hba_lunid(lunaddrbytes))
1f310bde 3493 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 3494 else
1f310bde
SC		 3495 /* defer target, lun assignment for physical devices */
3496 hpsa_set_bus_target_lun(device, 2, -1, -1);
3497 return;
3498 }
3499 /* It's a logical device */
4f4eb9f1
ST		 3500 if (is_ext_target(h, device)) {
3501 /* external target way, put logicals on bus 1
1f310bde
SC		 3502 * and match target/lun numbers box
3503 * reports, other smart array, bus 0, target 0, match lunid
3504 */
3505 hpsa_set_bus_target_lun(device,
3506 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
3507 return;
edd16368 3508 }
1f310bde 3509 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 3510}
3511
3512/*
3513 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 3514 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 3515 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
3516 * it for some reason. *tmpdevice is the target we're adding,
3517 * this_device is a pointer into the current element of currentsd[]
3518 * that we're building up in update_scsi_devices(), below.
3519 * lunzerobits is a bitmap that tracks which targets already have a
3520 * lun 0 assigned.
3521 * Returns 1 if an enclosure was added, 0 if not.
3522 */
4f4eb9f1 3523static int add_ext_target_dev(struct ctlr_info *h,
edd16368 3524 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 3525 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 3526 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 3527{
3528 unsigned char scsi3addr[8];
3529
1f310bde 3530 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 3531 return 0; /* There is already a lun 0 on this target. */
3532
3533 if (!is_logical_dev_addr_mode(lunaddrbytes))
3534 return 0; /* It's the logical targets that may lack lun 0. */
3535
4f4eb9f1
ST		 3536 if (!is_ext_target(h, tmpdevice))
3537 return 0; /* Only external target devices have this problem. */
edd16368 3538
1f310bde 3539 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 3540 return 0;
3541
c4f8a299 3542 memset(scsi3addr, 0, 8);
1f310bde 3543 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 3544 if (is_hba_lunid(scsi3addr))
3545 return 0; /* Don't add the RAID controller here. */
3546
339b2b14
SC		 3547 if (is_scsi_rev_5(h))
3548 return 0; /* p1210m doesn't need to do this. */
3549
4f4eb9f1 3550 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 3551 dev_warn(&h->pdev->dev, "Maximum number of external "
3552 "target devices exceeded. Check your hardware "
edd16368
SC		 3553 "configuration.");
3554 return 0;
3555 }
3556
0b0e1d6c 3557 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 3558 return 0;
4f4eb9f1 3559 (*n_ext_target_devs)++;
1f310bde
SC		 3560 hpsa_set_bus_target_lun(this_device,
3561 tmpdevice->bus, tmpdevice->target, 0);
9b5c48c2 3562 hpsa_update_device_supports_aborts(h, this_device, scsi3addr);
1f310bde 3563 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 3564 return 1;
3565}
3566
54b6e9e9
ST		 3567/*
3568 * Get address of physical disk used for an ioaccel2 mode command:
3569 * 1. Extract ioaccel2 handle from the command.
3570 * 2. Find a matching ioaccel2 handle from list of physical disks.
3571 * 3. Return:
3572 * 1 and set scsi3addr to address of matching physical
3573 * 0 if no matching physical disk was found.
3574 */
3575static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3576 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3577{
41ce4c35
SC		 3578 struct io_accel2_cmd *c2 =
3579 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3580 unsigned long flags;
54b6e9e9 3581 int i;
54b6e9e9 3582
41ce4c35
SC		 3583 spin_lock_irqsave(&h->devlock, flags);
3584 for (i = 0; i < h->ndevices; i++)
3585 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3586 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3587 sizeof(h->dev[i]->scsi3addr));
3588 spin_unlock_irqrestore(&h->devlock, flags);
3589 return 1;
3590 }
3591 spin_unlock_irqrestore(&h->devlock, flags);
3592 return 0;
54b6e9e9 3593}
41ce4c35 3594
edd16368
SC		 3595/*
3596 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3597 * logdev. The number of luns in physdev and logdev are returned in
3598 * *nphysicals and *nlogicals, respectively.
3599 * Returns 0 on success, -1 otherwise.
3600 */
3601static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3602 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3603 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3604{
03383736 3605 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3606 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3607 return -1;
3608 }
03383736 3609 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3610 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3611 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3612 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3613 *nphysicals = HPSA_MAX_PHYS_LUN;
3614 }
03383736 3615 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3616 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3617 return -1;
3618 }
6df1e954 3619 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3620 /* Reject Logicals in excess of our max capability. */
3621 if (*nlogicals > HPSA_MAX_LUN) {
3622 dev_warn(&h->pdev->dev,
3623 "maximum logical LUNs (%d) exceeded. "
3624 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3625 *nlogicals - HPSA_MAX_LUN);
3626 *nlogicals = HPSA_MAX_LUN;
3627 }
3628 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3629 dev_warn(&h->pdev->dev,
3630 "maximum logical + physical LUNs (%d) exceeded. "
3631 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3632 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3633 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3634 }
3635 return 0;
3636}
3637
42a91641
DB		 3638static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3639 int i, int nphysicals, int nlogicals,
a93aa1fe 3640 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3641 struct ReportLUNdata *logdev_list)
3642{
3643 /* Helper function, figure out where the LUN ID info is coming from
3644 * given index i, lists of physical and logical devices, where in
3645 * the list the raid controller is supposed to appear (first or last)
3646 */
3647
3648 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3649 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3650
3651 if (i == raid_ctlr_position)
3652 return RAID_CTLR_LUNID;
3653
3654 if (i < logicals_start)
d5b5d964
SC		 3655 return &physdev_list->LUN[i -
3656 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3657
3658 if (i < last_device)
3659 return &logdev_list->LUN[i - nphysicals -
3660 (raid_ctlr_position == 0)][0];
3661 BUG();
3662 return NULL;
3663}
3664
03383736
DB		 3665/* get physical drive ioaccel handle and queue depth */
3666static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3667 struct hpsa_scsi_dev_t *dev,
3668 u8 *lunaddrbytes,
3669 struct bmic_identify_physical_device *id_phys)
3670{
3671 int rc;
3672 struct ext_report_lun_entry *rle =
3673 (struct ext_report_lun_entry *) lunaddrbytes;
3674
3675 dev->ioaccel_handle = rle->ioaccel_handle;
a3144e0b
JH		 3676 if (PHYS_IOACCEL(lunaddrbytes) && dev->ioaccel_handle)
3677 dev->hba_ioaccel_enabled = 1;
03383736
DB		 3678 memset(id_phys, 0, sizeof(*id_phys));
3679 rc = hpsa_bmic_id_physical_device(h, lunaddrbytes,
3680 GET_BMIC_DRIVE_NUMBER(lunaddrbytes), id_phys,
3681 sizeof(*id_phys));
3682 if (!rc)
3683 /* Reserve space for FW operations */
3684#define DRIVE_CMDS_RESERVED_FOR_FW 2
3685#define DRIVE_QUEUE_DEPTH 7
3686 dev->queue_depth =
3687 le16_to_cpu(id_phys->current_queue_depth_limit) -
3688 DRIVE_CMDS_RESERVED_FOR_FW;
3689 else
3690 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
03383736
DB		 3691}
3692
8270b862
JH		 3693static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
3694 u8 *lunaddrbytes,
3695 struct bmic_identify_physical_device *id_phys)
3696{
3697 if (PHYS_IOACCEL(lunaddrbytes)
3698 && this_device->ioaccel_handle)
3699 this_device->hba_ioaccel_enabled = 1;
3700
3701 memcpy(&this_device->active_path_index,
3702 &id_phys->active_path_number,
3703 sizeof(this_device->active_path_index));
3704 memcpy(&this_device->path_map,
3705 &id_phys->redundant_path_present_map,
3706 sizeof(this_device->path_map));
3707 memcpy(&this_device->box,
3708 &id_phys->alternate_paths_phys_box_on_port,
3709 sizeof(this_device->box));
3710 memcpy(&this_device->phys_connector,
3711 &id_phys->alternate_paths_phys_connector,
3712 sizeof(this_device->phys_connector));
3713 memcpy(&this_device->bay,
3714 &id_phys->phys_bay_in_box,
3715 sizeof(this_device->bay));
3716}
3717
8aa60681 3718static void hpsa_update_scsi_devices(struct ctlr_info *h)
edd16368
SC		 3719{
3720 /* the idea here is we could get notified
3721 * that some devices have changed, so we do a report
3722 * physical luns and report logical luns cmd, and adjust
3723 * our list of devices accordingly.
3724 *
3725 * The scsi3addr's of devices won't change so long as the
3726 * adapter is not reset. That means we can rescan and
3727 * tell which devices we already know about, vs. new
3728 * devices, vs. disappearing devices.
3729 */
a93aa1fe 3730 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3731 struct ReportLUNdata *logdev_list = NULL;
03383736 3732 struct bmic_identify_physical_device *id_phys = NULL;
01a02ffc
SC		 3733 u32 nphysicals = 0;
3734 u32 nlogicals = 0;
3735 u32 ndev_allocated = 0;
edd16368
SC		 3736 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3737 int ncurrent = 0;
4f4eb9f1 3738 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3739 int raid_ctlr_position;
aca4a520 3740 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3741
cfe5badc 3742 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 3743 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3744 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 3745 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 3746 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
edd16368 3747
03383736
DB		 3748 if (!currentsd || !physdev_list || !logdev_list ||
3749 !tmpdevice || !id_phys) {
edd16368
SC		 3750 dev_err(&h->pdev->dev, "out of memory\n");
3751 goto out;
3752 }
3753 memset(lunzerobits, 0, sizeof(lunzerobits));
3754
853633e8
DB		 3755 h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */
3756
03383736 3757 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
853633e8
DB		 3758 logdev_list, &nlogicals)) {
3759 h->drv_req_rescan = 1;
edd16368 3760 goto out;
853633e8 3761 }
edd16368 3762
aca4a520
ST		 3763 /* We might see up to the maximum number of logical and physical disks
3764 * plus external target devices, and a device for the local RAID
3765 * controller.
edd16368 3766 */
aca4a520 3767 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3768
3769 /* Allocate the per device structures */
3770 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3771 if (i >= HPSA_MAX_DEVICES) {
3772 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3773 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3774 ndevs_to_allocate - HPSA_MAX_DEVICES);
3775 break;
3776 }
3777
edd16368
SC		 3778 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3779 if (!currentsd[i]) {
3780 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3781 __FILE__, __LINE__);
853633e8 3782 h->drv_req_rescan = 1;
edd16368
SC		 3783 goto out;
3784 }
3785 ndev_allocated++;
3786 }
3787
8645291b 3788 if (is_scsi_rev_5(h))
339b2b14
SC		 3789 raid_ctlr_position = 0;
3790 else
3791 raid_ctlr_position = nphysicals + nlogicals;
3792
edd16368 3793 /* adjust our table of devices */
4f4eb9f1 3794 n_ext_target_devs = 0;
edd16368 3795 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3796 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3797
3798 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3799 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3800 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 3801
3802 /* skip masked non-disk devices */
3803 if (MASKED_DEVICE(lunaddrbytes))
3804 if (i < nphysicals + (raid_ctlr_position == 0) &&
3805 NON_DISK_PHYS_DEV(lunaddrbytes))
3806 continue;
edd16368
SC		 3807
3808 /* Get device type, vendor, model, device id */
0b0e1d6c 3809 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
853633e8
DB		 3810 &is_OBDR)) {
3811 h->drv_req_rescan = 1;
edd16368 3812 continue; /* skip it if we can't talk to it. */
853633e8 3813 }
1f310bde 3814 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 3815 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 3816 this_device = currentsd[ncurrent];
3817
3818 /*
4f4eb9f1 3819 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3820 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3821 * is nonetheless an enclosure device there. We have to
3822 * present that otherwise linux won't find anything if
3823 * there is no lun 0.
3824 */
4f4eb9f1 3825 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3826 lunaddrbytes, lunzerobits,
4f4eb9f1 3827 &n_ext_target_devs)) {
edd16368
SC		 3828 ncurrent++;
3829 this_device = currentsd[ncurrent];
3830 }
3831
3832 *this_device = *tmpdevice;
edd16368 3833
41ce4c35
SC		 3834 /* do not expose masked devices */
3835 if (MASKED_DEVICE(lunaddrbytes) &&
3836 i < nphysicals + (raid_ctlr_position == 0)) {
41ce4c35
SC		 3837 this_device->expose_state = HPSA_DO_NOT_EXPOSE;
3838 } else {
3839 this_device->expose_state =
3840 HPSA_SG_ATTACH | HPSA_ULD_ATTACH;
3841 }
3842
edd16368 3843 switch (this_device->devtype) {
0b0e1d6c 3844 case TYPE_ROM:
edd16368
SC		 3845 /* We don't *really* support actual CD-ROM devices,
3846 * just "One Button Disaster Recovery" tape drive
3847 * which temporarily pretends to be a CD-ROM drive.
3848 * So we check that the device is really an OBDR tape
3849 * device by checking for "$DR-10" in bytes 43-48 of
3850 * the inquiry data.
3851 */
0b0e1d6c
SC		 3852 if (is_OBDR)
3853 ncurrent++;
edd16368
SC		 3854 break;
3855 case TYPE_DISK:
b9092b79
KB		 3856 if (i < nphysicals + (raid_ctlr_position == 0)) {
3857 /* The disk is in HBA mode. */
3858 /* Never use RAID mapper in HBA mode. */
ecf418d1 3859 this_device->offload_enabled = 0;
b9092b79
KB		 3860 hpsa_get_ioaccel_drive_info(h, this_device,
3861 lunaddrbytes, id_phys);
3862 hpsa_get_path_info(this_device, lunaddrbytes,
3863 id_phys);
3864 }
ecf418d1 3865 ncurrent++;
edd16368
SC		 3866 break;
3867 case TYPE_TAPE:
3868 case TYPE_MEDIUM_CHANGER:
41ce4c35 3869 case TYPE_ENCLOSURE:
b9092b79 3870 ncurrent++;
41ce4c35 3871 break;
edd16368
SC		 3872 case TYPE_RAID:
3873 /* Only present the Smartarray HBA as a RAID controller.
3874 * If it's a RAID controller other than the HBA itself
3875 * (an external RAID controller, MSA500 or similar)
3876 * don't present it.
3877 */
3878 if (!is_hba_lunid(lunaddrbytes))
3879 break;
3880 ncurrent++;
3881 break;
3882 default:
3883 break;
3884 }
cfe5badc 3885 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3886 break;
3887 }
8aa60681 3888 adjust_hpsa_scsi_table(h, currentsd, ncurrent);
edd16368
SC		 3889out:
3890 kfree(tmpdevice);
3891 for (i = 0; i < ndev_allocated; i++)
3892 kfree(currentsd[i]);
3893 kfree(currentsd);
edd16368
SC		 3894 kfree(physdev_list);
3895 kfree(logdev_list);
03383736 3896 kfree(id_phys);
edd16368
SC		 3897}
3898
ec5cbf04
WS		 3899static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3900 struct scatterlist *sg)
3901{
3902 u64 addr64 = (u64) sg_dma_address(sg);
3903 unsigned int len = sg_dma_len(sg);
3904
3905 desc->Addr = cpu_to_le64(addr64);
3906 desc->Len = cpu_to_le32(len);
3907 desc->Ext = 0;
3908}
3909
c7ee65b3
WS		 3910/*
3911 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3912 * dma mapping and fills in the scatter gather entries of the
3913 * hpsa command, cp.
3914 */
33a2ffce 3915static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3916 struct CommandList *cp,
3917 struct scsi_cmnd *cmd)
3918{
edd16368 3919 struct scatterlist *sg;
b3a7ba7c 3920 int use_sg, i, sg_limit, chained, last_sg;
33a2ffce 3921 struct SGDescriptor *curr_sg;
edd16368 3922
33a2ffce 3923 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3924
3925 use_sg = scsi_dma_map(cmd);
3926 if (use_sg < 0)
3927 return use_sg;
3928
3929 if (!use_sg)
3930 goto sglist_finished;
3931
b3a7ba7c
WS		 3932 /*
3933 * If the number of entries is greater than the max for a single list,
3934 * then we have a chained list; we will set up all but one entry in the
3935 * first list (the last entry is saved for link information);
3936 * otherwise, we don't have a chained list and we'll set up at each of
3937 * the entries in the one list.
3938 */
33a2ffce 3939 curr_sg = cp->SG;
b3a7ba7c
WS		 3940 chained = use_sg > h->max_cmd_sg_entries;
3941 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
3942 last_sg = scsi_sg_count(cmd) - 1;
3943 scsi_for_each_sg(cmd, sg, sg_limit, i) {
ec5cbf04 3944 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 3945 curr_sg++;
3946 }
ec5cbf04 3947
b3a7ba7c
WS		 3948 if (chained) {
3949 /*
3950 * Continue with the chained list. Set curr_sg to the chained
3951 * list. Modify the limit to the total count less the entries
3952 * we've already set up. Resume the scan at the list entry
3953 * where the previous loop left off.
3954 */
3955 curr_sg = h->cmd_sg_list[cp->cmdindex];
3956 sg_limit = use_sg - sg_limit;
3957 for_each_sg(sg, sg, sg_limit, i) {
3958 hpsa_set_sg_descriptor(curr_sg, sg);
3959 curr_sg++;
3960 }
3961 }
3962
ec5cbf04 3963 /* Back the pointer up to the last entry and mark it as "last". */
b3a7ba7c 3964 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3965
3966 if (use_sg + chained > h->maxSG)
3967 h->maxSG = use_sg + chained;
3968
3969 if (chained) {
3970 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3971 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3972 if (hpsa_map_sg_chain_block(h, cp)) {
3973 scsi_dma_unmap(cmd);
3974 return -1;
3975 }
33a2ffce 3976 return 0;
edd16368
SC		 3977 }
3978
3979sglist_finished:
3980
01a02ffc 3981 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 3982 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 3983 return 0;
3984}
3985
283b4a9b
SC		 3986#define IO_ACCEL_INELIGIBLE (1)
3987static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3988{
3989 int is_write = 0;
3990 u32 block;
3991 u32 block_cnt;
3992
3993 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3994 switch (cdb[0]) {
3995 case WRITE_6:
3996 case WRITE_12:
3997 is_write = 1;
3998 case READ_6:
3999 case READ_12:
4000 if (*cdb_len == 6) {
4001 block = (((u32) cdb[2]) << 8) | cdb[3];
4002 block_cnt = cdb[4];
4003 } else {
4004 BUG_ON(*cdb_len != 12);
4005 block = (((u32) cdb[2]) << 24) |
4006 (((u32) cdb[3]) << 16) |
4007 (((u32) cdb[4]) << 8) |
4008 cdb[5];
4009 block_cnt =
4010 (((u32) cdb[6]) << 24) |
4011 (((u32) cdb[7]) << 16) |
4012 (((u32) cdb[8]) << 8) |
4013 cdb[9];
4014 }
4015 if (block_cnt > 0xffff)
4016 return IO_ACCEL_INELIGIBLE;
4017
4018 cdb[0] = is_write ? WRITE_10 : READ_10;
4019 cdb[1] = 0;
4020 cdb[2] = (u8) (block >> 24);
4021 cdb[3] = (u8) (block >> 16);
4022 cdb[4] = (u8) (block >> 8);
4023 cdb[5] = (u8) (block);
4024 cdb[6] = 0;
4025 cdb[7] = (u8) (block_cnt >> 8);
4026 cdb[8] = (u8) (block_cnt);
4027 cdb[9] = 0;
4028 *cdb_len = 10;
4029 break;
4030 }
4031 return 0;
4032}
4033
c349775e 4034static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 4035 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4036 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 4037{
4038 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 4039 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
4040 unsigned int len;
4041 unsigned int total_len = 0;
4042 struct scatterlist *sg;
4043 u64 addr64;
4044 int use_sg, i;
4045 struct SGDescriptor *curr_sg;
4046 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
4047
283b4a9b 4048 /* TODO: implement chaining support */
03383736
DB		 4049 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
4050 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4051 return IO_ACCEL_INELIGIBLE;
03383736 4052 }
283b4a9b 4053
e1f7de0c
MG		 4054 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
4055
03383736
DB		 4056 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4057 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4058 return IO_ACCEL_INELIGIBLE;
03383736 4059 }
283b4a9b 4060
e1f7de0c
MG		 4061 c->cmd_type = CMD_IOACCEL1;
4062
4063 /* Adjust the DMA address to point to the accelerated command buffer */
4064 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
4065 (c->cmdindex * sizeof(*cp));
4066 BUG_ON(c->busaddr & 0x0000007F);
4067
4068 use_sg = scsi_dma_map(cmd);
03383736
DB		 4069 if (use_sg < 0) {
4070 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 4071 return use_sg;
03383736 4072 }
e1f7de0c
MG		 4073
4074 if (use_sg) {
4075 curr_sg = cp->SG;
4076 scsi_for_each_sg(cmd, sg, use_sg, i) {
4077 addr64 = (u64) sg_dma_address(sg);
4078 len = sg_dma_len(sg);
4079 total_len += len;
50a0decf
SC		 4080 curr_sg->Addr = cpu_to_le64(addr64);
4081 curr_sg->Len = cpu_to_le32(len);
4082 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 4083 curr_sg++;
4084 }
50a0decf 4085 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 4086
4087 switch (cmd->sc_data_direction) {
4088 case DMA_TO_DEVICE:
4089 control |= IOACCEL1_CONTROL_DATA_OUT;
4090 break;
4091 case DMA_FROM_DEVICE:
4092 control |= IOACCEL1_CONTROL_DATA_IN;
4093 break;
4094 case DMA_NONE:
4095 control |= IOACCEL1_CONTROL_NODATAXFER;
4096 break;
4097 default:
4098 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4099 cmd->sc_data_direction);
4100 BUG();
4101 break;
4102 }
4103 } else {
4104 control |= IOACCEL1_CONTROL_NODATAXFER;
4105 }
4106
c349775e 4107 c->Header.SGList = use_sg;
e1f7de0c 4108 /* Fill out the command structure to submit */
2b08b3e9
DB		 4109 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4110 cp->transfer_len = cpu_to_le32(total_len);
4111 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4112 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4113 cp->control = cpu_to_le32(control);
283b4a9b
SC		 4114 memcpy(cp->CDB, cdb, cdb_len);
4115 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 4116 /* Tag was already set at init time. */
283b4a9b 4117 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 4118 return 0;
4119}
edd16368 4120
283b4a9b
SC		 4121/*
4122 * Queue a command directly to a device behind the controller using the
4123 * I/O accelerator path.
4124 */
4125static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4126 struct CommandList *c)
4127{
4128 struct scsi_cmnd *cmd = c->scsi_cmd;
4129 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4130
03383736
DB		 4131 c->phys_disk = dev;
4132
283b4a9b 4133 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 4134 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 4135}
4136
dd0e19f3
ST		 4137/*
4138 * Set encryption parameters for the ioaccel2 request
4139 */
4140static void set_encrypt_ioaccel2(struct ctlr_info *h,
4141 struct CommandList *c, struct io_accel2_cmd *cp)
4142{
4143 struct scsi_cmnd *cmd = c->scsi_cmd;
4144 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4145 struct raid_map_data *map = &dev->raid_map;
4146 u64 first_block;
4147
dd0e19f3 4148 /* Are we doing encryption on this device */
2b08b3e9 4149 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 4150 return;
4151 /* Set the data encryption key index. */
4152 cp->dekindex = map->dekindex;
4153
4154 /* Set the encryption enable flag, encoded into direction field. */
4155 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4156
4157 /* Set encryption tweak values based on logical block address
4158 * If block size is 512, tweak value is LBA.
4159 * For other block sizes, tweak is (LBA * block size)/ 512)
4160 */
4161 switch (cmd->cmnd[0]) {
4162 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
4163 case WRITE_6:
4164 case READ_6:
2b08b3e9 4165 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 4166 break;
4167 case WRITE_10:
4168 case READ_10:
dd0e19f3
ST		 4169 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4170 case WRITE_12:
4171 case READ_12:
2b08b3e9 4172 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 4173 break;
4174 case WRITE_16:
4175 case READ_16:
2b08b3e9 4176 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 4177 break;
4178 default:
4179 dev_err(&h->pdev->dev,
2b08b3e9
DB		 4180 "ERROR: %s: size (0x%x) not supported for encryption\n",
4181 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 4182 BUG();
4183 break;
4184 }
2b08b3e9
DB		 4185
4186 if (le32_to_cpu(map->volume_blk_size) != 512)
4187 first_block = first_block *
4188 le32_to_cpu(map->volume_blk_size)/512;
4189
4190 cp->tweak_lower = cpu_to_le32(first_block);
4191 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 4192}
4193
c349775e
ST		 4194static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4195 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4196 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 4197{
4198 struct scsi_cmnd *cmd = c->scsi_cmd;
4199 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4200 struct ioaccel2_sg_element *curr_sg;
4201 int use_sg, i;
4202 struct scatterlist *sg;
4203 u64 addr64;
4204 u32 len;
4205 u32 total_len = 0;
4206
d9a729f3 4207 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 4208
03383736
DB		 4209 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4210 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4211 return IO_ACCEL_INELIGIBLE;
03383736
DB		 4212 }
4213
c349775e
ST		 4214 c->cmd_type = CMD_IOACCEL2;
4215 /* Adjust the DMA address to point to the accelerated command buffer */
4216 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4217 (c->cmdindex * sizeof(*cp));
4218 BUG_ON(c->busaddr & 0x0000007F);
4219
4220 memset(cp, 0, sizeof(*cp));
4221 cp->IU_type = IOACCEL2_IU_TYPE;
4222
4223 use_sg = scsi_dma_map(cmd);
03383736
DB		 4224 if (use_sg < 0) {
4225 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4226 return use_sg;
03383736 4227 }
c349775e
ST		 4228
4229 if (use_sg) {
c349775e 4230 curr_sg = cp->sg;
d9a729f3
WS		 4231 if (use_sg > h->ioaccel_maxsg) {
4232 addr64 = le64_to_cpu(
4233 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4234 curr_sg->address = cpu_to_le64(addr64);
4235 curr_sg->length = 0;
4236 curr_sg->reserved[0] = 0;
4237 curr_sg->reserved[1] = 0;
4238 curr_sg->reserved[2] = 0;
4239 curr_sg->chain_indicator = 0x80;
4240
4241 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4242 }
c349775e
ST		 4243 scsi_for_each_sg(cmd, sg, use_sg, i) {
4244 addr64 = (u64) sg_dma_address(sg);
4245 len = sg_dma_len(sg);
4246 total_len += len;
4247 curr_sg->address = cpu_to_le64(addr64);
4248 curr_sg->length = cpu_to_le32(len);
4249 curr_sg->reserved[0] = 0;
4250 curr_sg->reserved[1] = 0;
4251 curr_sg->reserved[2] = 0;
4252 curr_sg->chain_indicator = 0;
4253 curr_sg++;
4254 }
4255
4256 switch (cmd->sc_data_direction) {
4257 case DMA_TO_DEVICE:
dd0e19f3
ST		 4258 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4259 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 4260 break;
4261 case DMA_FROM_DEVICE:
dd0e19f3
ST		 4262 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4263 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 4264 break;
4265 case DMA_NONE:
dd0e19f3
ST		 4266 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4267 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 4268 break;
4269 default:
4270 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4271 cmd->sc_data_direction);
4272 BUG();
4273 break;
4274 }
4275 } else {
dd0e19f3
ST		 4276 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4277 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 4278 }
dd0e19f3
ST		 4279
4280 /* Set encryption parameters, if necessary */
4281 set_encrypt_ioaccel2(h, c, cp);
4282
2b08b3e9 4283 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 4284 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 4285 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 4286
c349775e
ST		 4287 cp->data_len = cpu_to_le32(total_len);
4288 cp->err_ptr = cpu_to_le64(c->busaddr +
4289 offsetof(struct io_accel2_cmd, error_data));
50a0decf 4290 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 4291
d9a729f3
WS		 4292 /* fill in sg elements */
4293 if (use_sg > h->ioaccel_maxsg) {
4294 cp->sg_count = 1;
4295 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4296 atomic_dec(&phys_disk->ioaccel_cmds_out);
4297 scsi_dma_unmap(cmd);
4298 return -1;
4299 }
4300 } else
4301 cp->sg_count = (u8) use_sg;
4302
c349775e
ST		 4303 enqueue_cmd_and_start_io(h, c);
4304 return 0;
4305}
4306
4307/*
4308 * Queue a command to the correct I/O accelerator path.
4309 */
4310static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4311 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4312 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 4313{
03383736
DB		 4314 /* Try to honor the device's queue depth */
4315 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4316 phys_disk->queue_depth) {
4317 atomic_dec(&phys_disk->ioaccel_cmds_out);
4318 return IO_ACCEL_INELIGIBLE;
4319 }
c349775e
ST		 4320 if (h->transMethod & CFGTBL_Trans_io_accel1)
4321 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4322 cdb, cdb_len, scsi3addr,
4323 phys_disk);
c349775e
ST		 4324 else
4325 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4326 cdb, cdb_len, scsi3addr,
4327 phys_disk);
c349775e
ST		 4328}
4329
6b80b18f
ST		 4330static void raid_map_helper(struct raid_map_data *map,
4331 int offload_to_mirror, u32 *map_index, u32 *current_group)
4332{
4333 if (offload_to_mirror == 0) {
4334 /* use physical disk in the first mirrored group. */
2b08b3e9 4335 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4336 return;
4337 }
4338 do {
4339 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4340 *current_group = *map_index /
4341 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4342 if (offload_to_mirror == *current_group)
4343 continue;
2b08b3e9 4344 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4345 /* select map index from next group */
2b08b3e9 4346 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4347 (*current_group)++;
4348 } else {
4349 /* select map index from first group */
2b08b3e9 4350 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4351 *current_group = 0;
4352 }
4353 } while (offload_to_mirror != *current_group);
4354}
4355
283b4a9b
SC		 4356/*
4357 * Attempt to perform offload RAID mapping for a logical volume I/O.
4358 */
4359static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4360 struct CommandList *c)
4361{
4362 struct scsi_cmnd *cmd = c->scsi_cmd;
4363 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4364 struct raid_map_data *map = &dev->raid_map;
4365 struct raid_map_disk_data *dd = &map->data[0];
4366 int is_write = 0;
4367 u32 map_index;
4368 u64 first_block, last_block;
4369 u32 block_cnt;
4370 u32 blocks_per_row;
4371 u64 first_row, last_row;
4372 u32 first_row_offset, last_row_offset;
4373 u32 first_column, last_column;
6b80b18f
ST		 4374 u64 r0_first_row, r0_last_row;
4375 u32 r5or6_blocks_per_row;
4376 u64 r5or6_first_row, r5or6_last_row;
4377 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4378 u32 r5or6_first_column, r5or6_last_column;
4379 u32 total_disks_per_row;
4380 u32 stripesize;
4381 u32 first_group, last_group, current_group;
283b4a9b
SC		 4382 u32 map_row;
4383 u32 disk_handle;
4384 u64 disk_block;
4385 u32 disk_block_cnt;
4386 u8 cdb[16];
4387 u8 cdb_len;
2b08b3e9 4388 u16 strip_size;
283b4a9b
SC		 4389#if BITS_PER_LONG == 32
4390 u64 tmpdiv;
4391#endif
6b80b18f 4392 int offload_to_mirror;
283b4a9b 4393
283b4a9b
SC		 4394 /* check for valid opcode, get LBA and block count */
4395 switch (cmd->cmnd[0]) {
4396 case WRITE_6:
4397 is_write = 1;
4398 case READ_6:
4399 first_block =
4400 (((u64) cmd->cmnd[2]) << 8) |
4401 cmd->cmnd[3];
4402 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4403 if (block_cnt == 0)
4404 block_cnt = 256;
283b4a9b
SC		 4405 break;
4406 case WRITE_10:
4407 is_write = 1;
4408 case READ_10:
4409 first_block =
4410 (((u64) cmd->cmnd[2]) << 24) |
4411 (((u64) cmd->cmnd[3]) << 16) |
4412 (((u64) cmd->cmnd[4]) << 8) |
4413 cmd->cmnd[5];
4414 block_cnt =
4415 (((u32) cmd->cmnd[7]) << 8) |
4416 cmd->cmnd[8];
4417 break;
4418 case WRITE_12:
4419 is_write = 1;
4420 case READ_12:
4421 first_block =
4422 (((u64) cmd->cmnd[2]) << 24) |
4423 (((u64) cmd->cmnd[3]) << 16) |
4424 (((u64) cmd->cmnd[4]) << 8) |
4425 cmd->cmnd[5];
4426 block_cnt =
4427 (((u32) cmd->cmnd[6]) << 24) |
4428 (((u32) cmd->cmnd[7]) << 16) |
4429 (((u32) cmd->cmnd[8]) << 8) |
4430 cmd->cmnd[9];
4431 break;
4432 case WRITE_16:
4433 is_write = 1;
4434 case READ_16:
4435 first_block =
4436 (((u64) cmd->cmnd[2]) << 56) |
4437 (((u64) cmd->cmnd[3]) << 48) |
4438 (((u64) cmd->cmnd[4]) << 40) |
4439 (((u64) cmd->cmnd[5]) << 32) |
4440 (((u64) cmd->cmnd[6]) << 24) |
4441 (((u64) cmd->cmnd[7]) << 16) |
4442 (((u64) cmd->cmnd[8]) << 8) |
4443 cmd->cmnd[9];
4444 block_cnt =
4445 (((u32) cmd->cmnd[10]) << 24) |
4446 (((u32) cmd->cmnd[11]) << 16) |
4447 (((u32) cmd->cmnd[12]) << 8) |
4448 cmd->cmnd[13];
4449 break;
4450 default:
4451 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4452 }
283b4a9b
SC		 4453 last_block = first_block + block_cnt - 1;
4454
4455 /* check for write to non-RAID-0 */
4456 if (is_write && dev->raid_level != 0)
4457 return IO_ACCEL_INELIGIBLE;
4458
4459 /* check for invalid block or wraparound */
2b08b3e9
DB		 4460 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4461 last_block < first_block)
283b4a9b
SC		 4462 return IO_ACCEL_INELIGIBLE;
4463
4464 /* calculate stripe information for the request */
2b08b3e9
DB		 4465 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4466 le16_to_cpu(map->strip_size);
4467 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4468#if BITS_PER_LONG == 32
4469 tmpdiv = first_block;
4470 (void) do_div(tmpdiv, blocks_per_row);
4471 first_row = tmpdiv;
4472 tmpdiv = last_block;
4473 (void) do_div(tmpdiv, blocks_per_row);
4474 last_row = tmpdiv;
4475 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4476 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4477 tmpdiv = first_row_offset;
2b08b3e9 4478 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4479 first_column = tmpdiv;
4480 tmpdiv = last_row_offset;
2b08b3e9 4481 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4482 last_column = tmpdiv;
4483#else
4484 first_row = first_block / blocks_per_row;
4485 last_row = last_block / blocks_per_row;
4486 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4487 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4488 first_column = first_row_offset / strip_size;
4489 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4490#endif
4491
4492 /* if this isn't a single row/column then give to the controller */
4493 if ((first_row != last_row) || (first_column != last_column))
4494 return IO_ACCEL_INELIGIBLE;
4495
4496 /* proceeding with driver mapping */
2b08b3e9
DB		 4497 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4498 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4499 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4500 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4501 map_index = (map_row * total_disks_per_row) + first_column;
4502
4503 switch (dev->raid_level) {
4504 case HPSA_RAID_0:
4505 break; /* nothing special to do */
4506 case HPSA_RAID_1:
4507 /* Handles load balance across RAID 1 members.
4508 * (2-drive R1 and R10 with even # of drives.)
4509 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4510 */
2b08b3e9 4511 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4512 if (dev->offload_to_mirror)
2b08b3e9 4513 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4514 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4515 break;
4516 case HPSA_RAID_ADM:
4517 /* Handles N-way mirrors (R1-ADM)
4518 * and R10 with # of drives divisible by 3.)
4519 */
2b08b3e9 4520 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4521
4522 offload_to_mirror = dev->offload_to_mirror;
4523 raid_map_helper(map, offload_to_mirror,
4524 &map_index, &current_group);
4525 /* set mirror group to use next time */
4526 offload_to_mirror =
2b08b3e9
DB		 4527 (offload_to_mirror >=
4528 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4529 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4530 dev->offload_to_mirror = offload_to_mirror;
4531 /* Avoid direct use of dev->offload_to_mirror within this
4532 * function since multiple threads might simultaneously
4533 * increment it beyond the range of dev->layout_map_count -1.
4534 */
4535 break;
4536 case HPSA_RAID_5:
4537 case HPSA_RAID_6:
2b08b3e9 4538 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4539 break;
4540
4541 /* Verify first and last block are in same RAID group */
4542 r5or6_blocks_per_row =
2b08b3e9
DB		 4543 le16_to_cpu(map->strip_size) *
4544 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4545 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4546 stripesize = r5or6_blocks_per_row *
4547 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4548#if BITS_PER_LONG == 32
4549 tmpdiv = first_block;
4550 first_group = do_div(tmpdiv, stripesize);
4551 tmpdiv = first_group;
4552 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4553 first_group = tmpdiv;
4554 tmpdiv = last_block;
4555 last_group = do_div(tmpdiv, stripesize);
4556 tmpdiv = last_group;
4557 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4558 last_group = tmpdiv;
4559#else
4560 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4561 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4562#endif
000ff7c2 4563 if (first_group != last_group)
6b80b18f
ST		 4564 return IO_ACCEL_INELIGIBLE;
4565
4566 /* Verify request is in a single row of RAID 5/6 */
4567#if BITS_PER_LONG == 32
4568 tmpdiv = first_block;
4569 (void) do_div(tmpdiv, stripesize);
4570 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4571 tmpdiv = last_block;
4572 (void) do_div(tmpdiv, stripesize);
4573 r5or6_last_row = r0_last_row = tmpdiv;
4574#else
4575 first_row = r5or6_first_row = r0_first_row =
4576 first_block / stripesize;
4577 r5or6_last_row = r0_last_row = last_block / stripesize;
4578#endif
4579 if (r5or6_first_row != r5or6_last_row)
4580 return IO_ACCEL_INELIGIBLE;
4581
4582
4583 /* Verify request is in a single column */
4584#if BITS_PER_LONG == 32
4585 tmpdiv = first_block;
4586 first_row_offset = do_div(tmpdiv, stripesize);
4587 tmpdiv = first_row_offset;
4588 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4589 r5or6_first_row_offset = first_row_offset;
4590 tmpdiv = last_block;
4591 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4592 tmpdiv = r5or6_last_row_offset;
4593 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4594 tmpdiv = r5or6_first_row_offset;
4595 (void) do_div(tmpdiv, map->strip_size);
4596 first_column = r5or6_first_column = tmpdiv;
4597 tmpdiv = r5or6_last_row_offset;
4598 (void) do_div(tmpdiv, map->strip_size);
4599 r5or6_last_column = tmpdiv;
4600#else
4601 first_row_offset = r5or6_first_row_offset =
4602 (u32)((first_block % stripesize) %
4603 r5or6_blocks_per_row);
4604
4605 r5or6_last_row_offset =
4606 (u32)((last_block % stripesize) %
4607 r5or6_blocks_per_row);
4608
4609 first_column = r5or6_first_column =
2b08b3e9 4610 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4611 r5or6_last_column =
2b08b3e9 4612 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4613#endif
4614 if (r5or6_first_column != r5or6_last_column)
4615 return IO_ACCEL_INELIGIBLE;
4616
4617 /* Request is eligible */
4618 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4619 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4620
4621 map_index = (first_group *
2b08b3e9 4622 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4623 (map_row * total_disks_per_row) + first_column;
4624 break;
4625 default:
4626 return IO_ACCEL_INELIGIBLE;
283b4a9b 4627 }
6b80b18f 4628
07543e0c
SC		 4629 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4630 return IO_ACCEL_INELIGIBLE;
4631
03383736
DB		 4632 c->phys_disk = dev->phys_disk[map_index];
4633
283b4a9b 4634 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 4635 disk_block = le64_to_cpu(map->disk_starting_blk) +
4636 first_row * le16_to_cpu(map->strip_size) +
4637 (first_row_offset - first_column *
4638 le16_to_cpu(map->strip_size));
283b4a9b
SC		 4639 disk_block_cnt = block_cnt;
4640
4641 /* handle differing logical/physical block sizes */
4642 if (map->phys_blk_shift) {
4643 disk_block <<= map->phys_blk_shift;
4644 disk_block_cnt <<= map->phys_blk_shift;
4645 }
4646 BUG_ON(disk_block_cnt > 0xffff);
4647
4648 /* build the new CDB for the physical disk I/O */
4649 if (disk_block > 0xffffffff) {
4650 cdb[0] = is_write ? WRITE_16 : READ_16;
4651 cdb[1] = 0;
4652 cdb[2] = (u8) (disk_block >> 56);
4653 cdb[3] = (u8) (disk_block >> 48);
4654 cdb[4] = (u8) (disk_block >> 40);
4655 cdb[5] = (u8) (disk_block >> 32);
4656 cdb[6] = (u8) (disk_block >> 24);
4657 cdb[7] = (u8) (disk_block >> 16);
4658 cdb[8] = (u8) (disk_block >> 8);
4659 cdb[9] = (u8) (disk_block);
4660 cdb[10] = (u8) (disk_block_cnt >> 24);
4661 cdb[11] = (u8) (disk_block_cnt >> 16);
4662 cdb[12] = (u8) (disk_block_cnt >> 8);
4663 cdb[13] = (u8) (disk_block_cnt);
4664 cdb[14] = 0;
4665 cdb[15] = 0;
4666 cdb_len = 16;
4667 } else {
4668 cdb[0] = is_write ? WRITE_10 : READ_10;
4669 cdb[1] = 0;
4670 cdb[2] = (u8) (disk_block >> 24);
4671 cdb[3] = (u8) (disk_block >> 16);
4672 cdb[4] = (u8) (disk_block >> 8);
4673 cdb[5] = (u8) (disk_block);
4674 cdb[6] = 0;
4675 cdb[7] = (u8) (disk_block_cnt >> 8);
4676 cdb[8] = (u8) (disk_block_cnt);
4677 cdb[9] = 0;
4678 cdb_len = 10;
4679 }
4680 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 4681 dev->scsi3addr,
4682 dev->phys_disk[map_index]);
283b4a9b
SC		 4683}
4684
25163bd5
WS		 4685/*
4686 * Submit commands down the "normal" RAID stack path
4687 * All callers to hpsa_ciss_submit must check lockup_detected
4688 * beforehand, before (opt.) and after calling cmd_alloc
4689 */
574f05d3
SC		 4690static int hpsa_ciss_submit(struct ctlr_info *h,
4691 struct CommandList *c, struct scsi_cmnd *cmd,
4692 unsigned char scsi3addr[])
edd16368 4693{
edd16368 4694 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 4695 c->cmd_type = CMD_SCSI;
4696 c->scsi_cmd = cmd;
4697 c->Header.ReplyQueue = 0; /* unused in simple mode */
4698 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 4699 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 4700
4701 /* Fill in the request block... */
4702
4703 c->Request.Timeout = 0;
edd16368
SC		 4704 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4705 c->Request.CDBLen = cmd->cmd_len;
4706 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 4707 switch (cmd->sc_data_direction) {
4708 case DMA_TO_DEVICE:
a505b86f
SC		 4709 c->Request.type_attr_dir =
4710 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 4711 break;
4712 case DMA_FROM_DEVICE:
a505b86f
SC		 4713 c->Request.type_attr_dir =
4714 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 4715 break;
4716 case DMA_NONE:
a505b86f
SC		 4717 c->Request.type_attr_dir =
4718 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 4719 break;
4720 case DMA_BIDIRECTIONAL:
4721 /* This can happen if a buggy application does a scsi passthru
4722 * and sets both inlen and outlen to non-zero. ( see
4723 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4724 */
4725
a505b86f
SC		 4726 c->Request.type_attr_dir =
4727 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 4728 /* This is technically wrong, and hpsa controllers should
4729 * reject it with CMD_INVALID, which is the most correct
4730 * response, but non-fibre backends appear to let it
4731 * slide by, and give the same results as if this field
4732 * were set correctly. Either way is acceptable for
4733 * our purposes here.
4734 */
4735
4736 break;
4737
4738 default:
4739 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4740 cmd->sc_data_direction);
4741 BUG();
4742 break;
4743 }
4744
33a2ffce 4745 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
73153fe5 4746 hpsa_cmd_resolve_and_free(h, c);
edd16368
SC		 4747 return SCSI_MLQUEUE_HOST_BUSY;
4748 }
4749 enqueue_cmd_and_start_io(h, c);
4750 /* the cmd'll come back via intr handler in complete_scsi_command() */
4751 return 0;
4752}
4753
360c73bd
SC		 4754static void hpsa_cmd_init(struct ctlr_info *h, int index,
4755 struct CommandList *c)
4756{
4757 dma_addr_t cmd_dma_handle, err_dma_handle;
4758
4759 /* Zero out all of commandlist except the last field, refcount */
4760 memset(c, 0, offsetof(struct CommandList, refcount));
4761 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
4762 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4763 c->err_info = h->errinfo_pool + index;
4764 memset(c->err_info, 0, sizeof(*c->err_info));
4765 err_dma_handle = h->errinfo_pool_dhandle
4766 + index * sizeof(*c->err_info);
4767 c->cmdindex = index;
4768 c->busaddr = (u32) cmd_dma_handle;
4769 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4770 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
4771 c->h = h;
a58e7e53 4772 c->scsi_cmd = SCSI_CMD_IDLE;
360c73bd
SC		 4773}
4774
4775static void hpsa_preinitialize_commands(struct ctlr_info *h)
4776{
4777 int i;
4778
4779 for (i = 0; i < h->nr_cmds; i++) {
4780 struct CommandList *c = h->cmd_pool + i;
4781
4782 hpsa_cmd_init(h, i, c);
4783 atomic_set(&c->refcount, 0);
4784 }
4785}
4786
4787static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
4788 struct CommandList *c)
4789{
4790 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4791
73153fe5
WS		 4792 BUG_ON(c->cmdindex != index);
4793
360c73bd
SC		 4794 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4795 memset(c->err_info, 0, sizeof(*c->err_info));
4796 c->busaddr = (u32) cmd_dma_handle;
4797}
4798
592a0ad5
WS		 4799static int hpsa_ioaccel_submit(struct ctlr_info *h,
4800 struct CommandList *c, struct scsi_cmnd *cmd,
4801 unsigned char *scsi3addr)
4802{
4803 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4804 int rc = IO_ACCEL_INELIGIBLE;
4805
4806 cmd->host_scribble = (unsigned char *) c;
4807
4808 if (dev->offload_enabled) {
4809 hpsa_cmd_init(h, c->cmdindex, c);
4810 c->cmd_type = CMD_SCSI;
4811 c->scsi_cmd = cmd;
4812 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4813 if (rc < 0) /* scsi_dma_map failed. */
4814 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 4815 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 4816 hpsa_cmd_init(h, c->cmdindex, c);
4817 c->cmd_type = CMD_SCSI;
4818 c->scsi_cmd = cmd;
4819 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4820 if (rc < 0) /* scsi_dma_map failed. */
4821 rc = SCSI_MLQUEUE_HOST_BUSY;
4822 }
4823 return rc;
4824}
4825
080ef1cc
DB		 4826static void hpsa_command_resubmit_worker(struct work_struct *work)
4827{
4828 struct scsi_cmnd *cmd;
4829 struct hpsa_scsi_dev_t *dev;
8a0ff92c 4830 struct CommandList *c = container_of(work, struct CommandList, work);
080ef1cc
DB		 4831
4832 cmd = c->scsi_cmd;
4833 dev = cmd->device->hostdata;
4834 if (!dev) {
4835 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 4836 return hpsa_cmd_free_and_done(c->h, c, cmd);
080ef1cc 4837 }
d604f533
WS		 4838 if (c->reset_pending)
4839 return hpsa_cmd_resolve_and_free(c->h, c);
a58e7e53
WS		 4840 if (c->abort_pending)
4841 return hpsa_cmd_abort_and_free(c->h, c, cmd);
592a0ad5
WS		 4842 if (c->cmd_type == CMD_IOACCEL2) {
4843 struct ctlr_info *h = c->h;
4844 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
4845 int rc;
4846
4847 if (c2->error_data.serv_response ==
4848 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
4849 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
4850 if (rc == 0)
4851 return;
4852 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4853 /*
4854 * If we get here, it means dma mapping failed.
4855 * Try again via scsi mid layer, which will
4856 * then get SCSI_MLQUEUE_HOST_BUSY.
4857 */
4858 cmd->result = DID_IMM_RETRY << 16;
8a0ff92c 4859 return hpsa_cmd_free_and_done(h, c, cmd);
592a0ad5
WS		 4860 }
4861 /* else, fall thru and resubmit down CISS path */
4862 }
4863 }
360c73bd 4864 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 4865 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4866 /*
4867 * If we get here, it means dma mapping failed. Try
4868 * again via scsi mid layer, which will then get
4869 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 4870 *
4871 * hpsa_ciss_submit will have already freed c
4872 * if it encountered a dma mapping failure.
080ef1cc
DB		 4873 */
4874 cmd->result = DID_IMM_RETRY << 16;
4875 cmd->scsi_done(cmd);
4876 }
4877}
4878
574f05d3
SC		 4879/* Running in struct Scsi_Host->host_lock less mode */
4880static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4881{
4882 struct ctlr_info *h;
4883 struct hpsa_scsi_dev_t *dev;
4884 unsigned char scsi3addr[8];
4885 struct CommandList *c;
4886 int rc = 0;
4887
4888 /* Get the ptr to our adapter structure out of cmd->host. */
4889 h = sdev_to_hba(cmd->device);
73153fe5
WS		 4890
4891 BUG_ON(cmd->request->tag < 0);
4892
574f05d3
SC		 4893 dev = cmd->device->hostdata;
4894 if (!dev) {
4895 cmd->result = DID_NO_CONNECT << 16;
4896 cmd->scsi_done(cmd);
4897 return 0;
4898 }
574f05d3 4899
73153fe5 4900 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
bf43caf3 4901
407863cb 4902 if (unlikely(lockup_detected(h))) {
25163bd5 4903 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 4904 cmd->scsi_done(cmd);
4905 return 0;
4906 }
73153fe5 4907 c = cmd_tagged_alloc(h, cmd);
574f05d3 4908
407863cb
SC		 4909 /*
4910 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 4911 * Retries always go down the normal I/O path.
4912 */
4913 if (likely(cmd->retries == 0 &&
4914 cmd->request->cmd_type == REQ_TYPE_FS &&
4915 h->acciopath_status)) {
592a0ad5
WS		 4916 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
4917 if (rc == 0)
4918 return 0;
4919 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
73153fe5 4920 hpsa_cmd_resolve_and_free(h, c);
592a0ad5 4921 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 4922 }
4923 }
4924 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4925}
4926
8ebc9248 4927static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 4928{
4929 unsigned long flags;
4930
8ebc9248
WS		 4931 spin_lock_irqsave(&h->scan_lock, flags);
4932 h->scan_finished = 1;
4933 wake_up_all(&h->scan_wait_queue);
4934 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 4935}
4936
a08a8471
SC		 4937static void hpsa_scan_start(struct Scsi_Host *sh)
4938{
4939 struct ctlr_info *h = shost_to_hba(sh);
4940 unsigned long flags;
4941
8ebc9248
WS		 4942 /*
4943 * Don't let rescans be initiated on a controller known to be locked
4944 * up. If the controller locks up *during* a rescan, that thread is
4945 * probably hosed, but at least we can prevent new rescan threads from
4946 * piling up on a locked up controller.
4947 */
4948 if (unlikely(lockup_detected(h)))
4949 return hpsa_scan_complete(h);
5f389360 4950
a08a8471
SC		 4951 /* wait until any scan already in progress is finished. */
4952 while (1) {
4953 spin_lock_irqsave(&h->scan_lock, flags);
4954 if (h->scan_finished)
4955 break;
4956 spin_unlock_irqrestore(&h->scan_lock, flags);
4957 wait_event(h->scan_wait_queue, h->scan_finished);
4958 /* Note: We don't need to worry about a race between this
4959 * thread and driver unload because the midlayer will
4960 * have incremented the reference count, so unload won't
4961 * happen if we're in here.
4962 */
4963 }
4964 h->scan_finished = 0; /* mark scan as in progress */
4965 spin_unlock_irqrestore(&h->scan_lock, flags);
4966
8ebc9248
WS		 4967 if (unlikely(lockup_detected(h)))
4968 return hpsa_scan_complete(h);
5f389360 4969
8aa60681 4970 hpsa_update_scsi_devices(h);
a08a8471 4971
8ebc9248 4972 hpsa_scan_complete(h);
a08a8471
SC		 4973}
4974
7c0a0229
DB		 4975static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4976{
03383736
DB		 4977 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
4978
4979 if (!logical_drive)
4980 return -ENODEV;
7c0a0229
DB		 4981
4982 if (qdepth < 1)
4983 qdepth = 1;
03383736
DB		 4984 else if (qdepth > logical_drive->queue_depth)
4985 qdepth = logical_drive->queue_depth;
4986
4987 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 4988}
4989
a08a8471
SC		 4990static int hpsa_scan_finished(struct Scsi_Host *sh,
4991 unsigned long elapsed_time)
4992{
4993 struct ctlr_info *h = shost_to_hba(sh);
4994 unsigned long flags;
4995 int finished;
4996
4997 spin_lock_irqsave(&h->scan_lock, flags);
4998 finished = h->scan_finished;
4999 spin_unlock_irqrestore(&h->scan_lock, flags);
5000 return finished;
5001}
5002
2946e82b 5003static int hpsa_scsi_host_alloc(struct ctlr_info *h)
edd16368 5004{
b705690d
SC		 5005 struct Scsi_Host *sh;
5006 int error;
edd16368 5007
b705690d 5008 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2946e82b
RE		 5009 if (sh == NULL) {
5010 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
5011 return -ENOMEM;
5012 }
b705690d
SC		 5013
5014 sh->io_port = 0;
5015 sh->n_io_port = 0;
5016 sh->this_id = -1;
5017 sh->max_channel = 3;
5018 sh->max_cmd_len = MAX_COMMAND_SIZE;
5019 sh->max_lun = HPSA_MAX_LUN;
5020 sh->max_id = HPSA_MAX_LUN;
41ce4c35 5021 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 5022 sh->cmd_per_lun = sh->can_queue;
b705690d 5023 sh->sg_tablesize = h->maxsgentries;
b705690d
SC		 5024 sh->hostdata[0] = (unsigned long) h;
5025 sh->irq = h->intr[h->intr_mode];
5026 sh->unique_id = sh->irq;
73153fe5
WS		 5027 error = scsi_init_shared_tag_map(sh, sh->can_queue);
5028 if (error) {
5029 dev_err(&h->pdev->dev,
5030 "%s: scsi_init_shared_tag_map failed for controller %d\n",
5031 __func__, h->ctlr);
2946e82b
RE		 5032 scsi_host_put(sh);
5033 return error;
73153fe5 5034 }
2946e82b 5035 h->scsi_host = sh;
b705690d 5036 return 0;
2946e82b 5037}
b705690d 5038
2946e82b
RE		 5039static int hpsa_scsi_add_host(struct ctlr_info *h)
5040{
5041 int rv;
5042
5043 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
5044 if (rv) {
5045 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
5046 return rv;
5047 }
5048 scsi_scan_host(h->scsi_host);
5049 return 0;
edd16368
SC		 5050}
5051
73153fe5
WS		 5052/*
5053 * The block layer has already gone to the trouble of picking out a unique,
5054 * small-integer tag for this request. We use an offset from that value as
5055 * an index to select our command block. (The offset allows us to reserve the
5056 * low-numbered entries for our own uses.)
5057 */
5058static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
5059{
5060 int idx = scmd->request->tag;
5061
5062 if (idx < 0)
5063 return idx;
5064
5065 /* Offset to leave space for internal cmds. */
5066 return idx += HPSA_NRESERVED_CMDS;
5067}
5068
b69324ff
WS		 5069/*
5070 * Send a TEST_UNIT_READY command to the specified LUN using the specified
5071 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5072 */
5073static int hpsa_send_test_unit_ready(struct ctlr_info *h,
5074 struct CommandList *c, unsigned char lunaddr[],
5075 int reply_queue)
5076{
5077 int rc;
5078
5079 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
5080 (void) fill_cmd(c, TEST_UNIT_READY, h,
5081 NULL, 0, 0, lunaddr, TYPE_CMD);
5082 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5083 if (rc)
5084 return rc;
5085 /* no unmap needed here because no data xfer. */
5086
5087 /* Check if the unit is already ready. */
5088 if (c->err_info->CommandStatus == CMD_SUCCESS)
5089 return 0;
5090
5091 /*
5092 * The first command sent after reset will receive "unit attention" to
5093 * indicate that the LUN has been reset...this is actually what we're
5094 * looking for (but, success is good too).
5095 */
5096 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5097 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5098 (c->err_info->SenseInfo[2] == NO_SENSE ||
5099 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5100 return 0;
5101
5102 return 1;
5103}
5104
5105/*
5106 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5107 * returns zero when the unit is ready, and non-zero when giving up.
5108 */
5109static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5110 struct CommandList *c,
5111 unsigned char lunaddr[], int reply_queue)
edd16368 5112{
8919358e 5113 int rc;
edd16368
SC		 5114 int count = 0;
5115 int waittime = 1; /* seconds */
edd16368
SC		 5116
5117 /* Send test unit ready until device ready, or give up. */
b69324ff 5118 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
edd16368 5119
b69324ff
WS		 5120 /*
5121 * Wait for a bit. do this first, because if we send
edd16368
SC		 5122 * the TUR right away, the reset will just abort it.
5123 */
5124 msleep(1000 * waittime);
b69324ff
WS		 5125
5126 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5127 if (!rc)
5128 break;
edd16368
SC		 5129
5130 /* Increase wait time with each try, up to a point. */
5131 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
b69324ff 5132 waittime *= 2;
edd16368 5133
b69324ff
WS		 5134 dev_warn(&h->pdev->dev,
5135 "waiting %d secs for device to become ready.\n",
5136 waittime);
5137 }
edd16368 5138
b69324ff
WS		 5139 return rc;
5140}
edd16368 5141
b69324ff
WS		 5142static int wait_for_device_to_become_ready(struct ctlr_info *h,
5143 unsigned char lunaddr[],
5144 int reply_queue)
5145{
5146 int first_queue;
5147 int last_queue;
5148 int rq;
5149 int rc = 0;
5150 struct CommandList *c;
5151
5152 c = cmd_alloc(h);
5153
5154 /*
5155 * If no specific reply queue was requested, then send the TUR
5156 * repeatedly, requesting a reply on each reply queue; otherwise execute
5157 * the loop exactly once using only the specified queue.
5158 */
5159 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5160 first_queue = 0;
5161 last_queue = h->nreply_queues - 1;
5162 } else {
5163 first_queue = reply_queue;
5164 last_queue = reply_queue;
5165 }
5166
5167 for (rq = first_queue; rq <= last_queue; rq++) {
5168 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5169 if (rc)
edd16368 5170 break;
edd16368
SC		 5171 }
5172
5173 if (rc)
5174 dev_warn(&h->pdev->dev, "giving up on device.\n");
5175 else
5176 dev_warn(&h->pdev->dev, "device is ready.\n");
5177
45fcb86e 5178 cmd_free(h, c);
edd16368
SC		 5179 return rc;
5180}
5181
5182/* Need at least one of these error handlers to keep ../scsi/hosts.c from
5183 * complaining. Doing a host- or bus-reset can't do anything good here.
5184 */
5185static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5186{
5187 int rc;
5188 struct ctlr_info *h;
5189 struct hpsa_scsi_dev_t *dev;
2dc127bb 5190 char msg[48];
edd16368
SC		 5191
5192 /* find the controller to which the command to be aborted was sent */
5193 h = sdev_to_hba(scsicmd->device);
5194 if (h == NULL) /* paranoia */
5195 return FAILED;
e345893b
DB		 5196
5197 if (lockup_detected(h))
5198 return FAILED;
5199
edd16368
SC		 5200 dev = scsicmd->device->hostdata;
5201 if (!dev) {
d604f533 5202 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
edd16368
SC		 5203 return FAILED;
5204 }
25163bd5
WS		 5205
5206 /* if controller locked up, we can guarantee command won't complete */
5207 if (lockup_detected(h)) {
2dc127bb
DC		 5208 snprintf(msg, sizeof(msg),
5209 "cmd %d RESET FAILED, lockup detected",
5210 hpsa_get_cmd_index(scsicmd));
73153fe5 5211 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5212 return FAILED;
5213 }
5214
5215 /* this reset request might be the result of a lockup; check */
5216 if (detect_controller_lockup(h)) {
2dc127bb
DC		 5217 snprintf(msg, sizeof(msg),
5218 "cmd %d RESET FAILED, new lockup detected",
5219 hpsa_get_cmd_index(scsicmd));
73153fe5 5220 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5221 return FAILED;
5222 }
5223
d604f533
WS		 5224 /* Do not attempt on controller */
5225 if (is_hba_lunid(dev->scsi3addr))
5226 return SUCCESS;
5227
25163bd5
WS		 5228 hpsa_show_dev_msg(KERN_WARNING, h, dev, "resetting");
5229
edd16368 5230 /* send a reset to the SCSI LUN which the command was sent to */
d604f533
WS		 5231 rc = hpsa_do_reset(h, dev, dev->scsi3addr, HPSA_RESET_TYPE_LUN,
5232 DEFAULT_REPLY_QUEUE);
2dc127bb
DC		 5233 snprintf(msg, sizeof(msg), "reset %s",
5234 rc == 0 ? "completed successfully" : "failed");
d604f533
WS		 5235 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
5236 return rc == 0 ? SUCCESS : FAILED;
edd16368
SC		 5237}
5238
6cba3f19
SC		 5239static void swizzle_abort_tag(u8 *tag)
5240{
5241 u8 original_tag[8];
5242
5243 memcpy(original_tag, tag, 8);
5244 tag[0] = original_tag[3];
5245 tag[1] = original_tag[2];
5246 tag[2] = original_tag[1];
5247 tag[3] = original_tag[0];
5248 tag[4] = original_tag[7];
5249 tag[5] = original_tag[6];
5250 tag[6] = original_tag[5];
5251 tag[7] = original_tag[4];
5252}
5253
17eb87d2 5254static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 5255 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 5256{
2b08b3e9 5257 u64 tag;
17eb87d2
ST		 5258 if (c->cmd_type == CMD_IOACCEL1) {
5259 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5260 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 5261 tag = le64_to_cpu(cm1->tag);
5262 *tagupper = cpu_to_le32(tag >> 32);
5263 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 5264 return;
5265 }
5266 if (c->cmd_type == CMD_IOACCEL2) {
5267 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5268 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 5269 /* upper tag not used in ioaccel2 mode */
5270 memset(tagupper, 0, sizeof(*tagupper));
5271 *taglower = cm2->Tag;
54b6e9e9 5272 return;
17eb87d2 5273 }
2b08b3e9
DB		 5274 tag = le64_to_cpu(c->Header.tag);
5275 *tagupper = cpu_to_le32(tag >> 32);
5276 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 5277}
5278
75167d2c 5279static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 5280 struct CommandList *abort, int reply_queue)
75167d2c
SC		 5281{
5282 int rc = IO_OK;
5283 struct CommandList *c;
5284 struct ErrorInfo *ei;
2b08b3e9 5285 __le32 tagupper, taglower;
75167d2c 5286
45fcb86e 5287 c = cmd_alloc(h);
75167d2c 5288
a2dac136 5289 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 5290 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 5291 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 5292 if (h->needs_abort_tags_swizzled)
6cba3f19 5293 swizzle_abort_tag(&c->Request.CDB[4]);
25163bd5 5294 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
17eb87d2 5295 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5296 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 5297 __func__, tagupper, taglower);
75167d2c
SC		 5298 /* no unmap needed here because no data xfer. */
5299
5300 ei = c->err_info;
5301 switch (ei->CommandStatus) {
5302 case CMD_SUCCESS:
5303 break;
9437ac43
SC		 5304 case CMD_TMF_STATUS:
5305 rc = hpsa_evaluate_tmf_status(h, c);
5306 break;
75167d2c
SC		 5307 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5308 rc = -1;
5309 break;
5310 default:
5311 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 5312 __func__, tagupper, taglower);
d1e8beac 5313 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 5314 rc = -1;
5315 break;
5316 }
45fcb86e 5317 cmd_free(h, c);
dd0e19f3
ST		 5318 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5319 __func__, tagupper, taglower);
75167d2c
SC		 5320 return rc;
5321}
5322
8be986cc
SC		 5323static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5324 struct CommandList *command_to_abort, int reply_queue)
5325{
5326 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5327 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5328 struct io_accel2_cmd *c2a =
5329 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
a58e7e53 5330 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
8be986cc
SC		 5331 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5332
5333 /*
5334 * We're overlaying struct hpsa_tmf_struct on top of something which
5335 * was allocated as a struct io_accel2_cmd, so we better be sure it
5336 * actually fits, and doesn't overrun the error info space.
5337 */
5338 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5339 sizeof(struct io_accel2_cmd));
5340 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5341 offsetof(struct hpsa_tmf_struct, error_len) +
5342 sizeof(ac->error_len));
5343
5344 c->cmd_type = IOACCEL2_TMF;
a58e7e53
WS		 5345 c->scsi_cmd = SCSI_CMD_BUSY;
5346
8be986cc
SC		 5347 /* Adjust the DMA address to point to the accelerated command buffer */
5348 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5349 (c->cmdindex * sizeof(struct io_accel2_cmd));
5350 BUG_ON(c->busaddr & 0x0000007F);
5351
5352 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5353 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5354 ac->reply_queue = reply_queue;
5355 ac->tmf = IOACCEL2_TMF_ABORT;
5356 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5357 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5358 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5359 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5360 ac->error_ptr = cpu_to_le64(c->busaddr +
5361 offsetof(struct io_accel2_cmd, error_data));
5362 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5363}
5364
54b6e9e9
ST		 5365/* ioaccel2 path firmware cannot handle abort task requests.
5366 * Change abort requests to physical target reset, and send to the
5367 * address of the physical disk used for the ioaccel 2 command.
5368 * Return 0 on success (IO_OK)
5369 * -1 on failure
5370 */
5371
5372static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 5373 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 5374{
5375 int rc = IO_OK;
5376 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5377 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5378 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5379 unsigned char *psa = &phys_scsi3addr[0];
5380
5381 /* Get a pointer to the hpsa logical device. */
7fa3030c 5382 scmd = abort->scsi_cmd;
54b6e9e9
ST		 5383 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5384 if (dev == NULL) {
5385 dev_warn(&h->pdev->dev,
5386 "Cannot abort: no device pointer for command.\n");
5387 return -1; /* not abortable */
5388 }
5389
2ba8bfc8
SC		 5390 if (h->raid_offload_debug > 0)
5391 dev_info(&h->pdev->dev,
0d96ef5f 5392 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 5393 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 5394 "Reset as abort",
2ba8bfc8
SC		 5395 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5396 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5397
54b6e9e9
ST		 5398 if (!dev->offload_enabled) {
5399 dev_warn(&h->pdev->dev,
5400 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5401 return -1; /* not abortable */
5402 }
5403
5404 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5405 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5406 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5407 return -1; /* not abortable */
5408 }
5409
5410 /* send the reset */
2ba8bfc8
SC		 5411 if (h->raid_offload_debug > 0)
5412 dev_info(&h->pdev->dev,
5413 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5414 psa[0], psa[1], psa[2], psa[3],
5415 psa[4], psa[5], psa[6], psa[7]);
d604f533 5416 rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 5417 if (rc != 0) {
5418 dev_warn(&h->pdev->dev,
5419 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5420 psa[0], psa[1], psa[2], psa[3],
5421 psa[4], psa[5], psa[6], psa[7]);
5422 return rc; /* failed to reset */
5423 }
5424
5425 /* wait for device to recover */
b69324ff 5426 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
54b6e9e9
ST		 5427 dev_warn(&h->pdev->dev,
5428 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5429 psa[0], psa[1], psa[2], psa[3],
5430 psa[4], psa[5], psa[6], psa[7]);
5431 return -1; /* failed to recover */
5432 }
5433
5434 /* device recovered */
5435 dev_info(&h->pdev->dev,
5436 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5437 psa[0], psa[1], psa[2], psa[3],
5438 psa[4], psa[5], psa[6], psa[7]);
5439
5440 return rc; /* success */
5441}
5442
8be986cc
SC		 5443static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
5444 struct CommandList *abort, int reply_queue)
5445{
5446 int rc = IO_OK;
5447 struct CommandList *c;
5448 __le32 taglower, tagupper;
5449 struct hpsa_scsi_dev_t *dev;
5450 struct io_accel2_cmd *c2;
5451
5452 dev = abort->scsi_cmd->device->hostdata;
5453 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
5454 return -1;
5455
5456 c = cmd_alloc(h);
5457 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
5458 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5459 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5460 hpsa_get_tag(h, abort, &taglower, &tagupper);
5461 dev_dbg(&h->pdev->dev,
5462 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
5463 __func__, tagupper, taglower);
5464 /* no unmap needed here because no data xfer. */
5465
5466 dev_dbg(&h->pdev->dev,
5467 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
5468 __func__, tagupper, taglower, c2->error_data.serv_response);
5469 switch (c2->error_data.serv_response) {
5470 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
5471 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
5472 rc = 0;
5473 break;
5474 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
5475 case IOACCEL2_SERV_RESPONSE_FAILURE:
5476 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
5477 rc = -1;
5478 break;
5479 default:
5480 dev_warn(&h->pdev->dev,
5481 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
5482 __func__, tagupper, taglower,
5483 c2->error_data.serv_response);
5484 rc = -1;
5485 }
5486 cmd_free(h, c);
5487 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
5488 tagupper, taglower);
5489 return rc;
5490}
5491
6cba3f19 5492static int hpsa_send_abort_both_ways(struct ctlr_info *h,
25163bd5 5493 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
6cba3f19 5494{
8be986cc
SC		 5495 /*
5496 * ioccelerator mode 2 commands should be aborted via the
54b6e9e9 5497 * accelerated path, since RAID path is unaware of these commands,
8be986cc
SC		 5498 * but not all underlying firmware can handle abort TMF.
5499 * Change abort to physical device reset when abort TMF is unsupported.
54b6e9e9 5500 */
8be986cc
SC		 5501 if (abort->cmd_type == CMD_IOACCEL2) {
5502 if (HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)
5503 return hpsa_send_abort_ioaccel2(h, abort,
5504 reply_queue);
5505 else
5506 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
25163bd5 5507 abort, reply_queue);
8be986cc 5508 }
9b5c48c2 5509 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
25163bd5 5510}
54b6e9e9 5511
25163bd5
WS		 5512/* Find out which reply queue a command was meant to return on */
5513static int hpsa_extract_reply_queue(struct ctlr_info *h,
5514 struct CommandList *c)
5515{
5516 if (c->cmd_type == CMD_IOACCEL2)
5517 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5518 return c->Header.ReplyQueue;
6cba3f19
SC		 5519}
5520
9b5c48c2
SC		 5521/*
5522 * Limit concurrency of abort commands to prevent
5523 * over-subscription of commands
5524 */
5525static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5526{
5527#define ABORT_CMD_WAIT_MSECS 5000
5528 return !wait_event_timeout(h->abort_cmd_wait_queue,
5529 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5530 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5531}
5532
75167d2c
SC		 5533/* Send an abort for the specified command.
5534 * If the device and controller support it,
5535 * send a task abort request.
5536 */
5537static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5538{
5539
a58e7e53 5540 int rc;
75167d2c
SC		 5541 struct ctlr_info *h;
5542 struct hpsa_scsi_dev_t *dev;
5543 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 5544 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
5545 char msg[256]; /* For debug messaging. */
5546 int ml = 0;
2b08b3e9 5547 __le32 tagupper, taglower;
25163bd5
WS		 5548 int refcount, reply_queue;
5549
5550 if (sc == NULL)
5551 return FAILED;
75167d2c 5552
9b5c48c2
SC		 5553 if (sc->device == NULL)
5554 return FAILED;
5555
75167d2c
SC		 5556 /* Find the controller of the command to be aborted */
5557 h = sdev_to_hba(sc->device);
9b5c48c2 5558 if (h == NULL)
75167d2c
SC		 5559 return FAILED;
5560
25163bd5
WS		 5561 /* Find the device of the command to be aborted */
5562 dev = sc->device->hostdata;
5563 if (!dev) {
5564 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
5565 msg);
e345893b 5566 return FAILED;
25163bd5
WS		 5567 }
5568
5569 /* If controller locked up, we can guarantee command won't complete */
5570 if (lockup_detected(h)) {
5571 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5572 "ABORT FAILED, lockup detected");
5573 return FAILED;
5574 }
5575
5576 /* This is a good time to check if controller lockup has occurred */
5577 if (detect_controller_lockup(h)) {
5578 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5579 "ABORT FAILED, new lockup detected");
5580 return FAILED;
5581 }
e345893b 5582
75167d2c
SC		 5583 /* Check that controller supports some kind of task abort */
5584 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5585 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5586 return FAILED;
5587
5588 memset(msg, 0, sizeof(msg));
4b761557 5589 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
75167d2c 5590 h->scsi_host->host_no, sc->device->channel,
0d96ef5f 5591 sc->device->id, sc->device->lun,
4b761557 5592 "Aborting command", sc);
75167d2c 5593
75167d2c
SC		 5594 /* Get SCSI command to be aborted */
5595 abort = (struct CommandList *) sc->host_scribble;
5596 if (abort == NULL) {
281a7fd0
WS		 5597 /* This can happen if the command already completed. */
5598 return SUCCESS;
5599 }
5600 refcount = atomic_inc_return(&abort->refcount);
5601 if (refcount == 1) { /* Command is done already. */
5602 cmd_free(h, abort);
5603 return SUCCESS;
75167d2c 5604 }
9b5c48c2
SC		 5605
5606 /* Don't bother trying the abort if we know it won't work. */
5607 if (abort->cmd_type != CMD_IOACCEL2 &&
5608 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5609 cmd_free(h, abort);
5610 return FAILED;
5611 }
5612
a58e7e53
WS		 5613 /*
5614 * Check that we're aborting the right command.
5615 * It's possible the CommandList already completed and got re-used.
5616 */
5617 if (abort->scsi_cmd != sc) {
5618 cmd_free(h, abort);
5619 return SUCCESS;
5620 }
5621
5622 abort->abort_pending = true;
17eb87d2 5623 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5624 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 5625 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 5626 as = abort->scsi_cmd;
75167d2c 5627 if (as != NULL)
4b761557
RE		 5628 ml += sprintf(msg+ml,
5629 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
5630 as->cmd_len, as->cmnd[0], as->cmnd[1],
5631 as->serial_number);
5632 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
0d96ef5f 5633 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
4b761557 5634
75167d2c
SC		 5635 /*
5636 * Command is in flight, or possibly already completed
5637 * by the firmware (but not to the scsi mid layer) but we can't
5638 * distinguish which. Send the abort down.
5639 */
9b5c48c2
SC		 5640 if (wait_for_available_abort_cmd(h)) {
5641 dev_warn(&h->pdev->dev,
4b761557
RE		 5642 "%s FAILED, timeout waiting for an abort command to become available.\n",
5643 msg);
9b5c48c2
SC		 5644 cmd_free(h, abort);
5645 return FAILED;
5646 }
25163bd5 5647 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
9b5c48c2
SC		 5648 atomic_inc(&h->abort_cmds_available);
5649 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 5650 if (rc != 0) {
4b761557 5651 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
0d96ef5f 5652 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4b761557 5653 "FAILED to abort command");
281a7fd0 5654 cmd_free(h, abort);
75167d2c
SC		 5655 return FAILED;
5656 }
4b761557 5657 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
d604f533 5658 wait_event(h->event_sync_wait_queue,
a58e7e53 5659 abort->scsi_cmd != sc || lockup_detected(h));
281a7fd0 5660 cmd_free(h, abort);
a58e7e53 5661 return !lockup_detected(h) ? SUCCESS : FAILED;
75167d2c
SC		 5662}
5663
73153fe5
WS		 5664/*
5665 * For operations with an associated SCSI command, a command block is allocated
5666 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
5667 * block request tag as an index into a table of entries. cmd_tagged_free() is
5668 * the complement, although cmd_free() may be called instead.
5669 */
5670static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
5671 struct scsi_cmnd *scmd)
5672{
5673 int idx = hpsa_get_cmd_index(scmd);
5674 struct CommandList *c = h->cmd_pool + idx;
5675
5676 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
5677 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
5678 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
5679 /* The index value comes from the block layer, so if it's out of
5680 * bounds, it's probably not our bug.
5681 */
5682 BUG();
5683 }
5684
5685 atomic_inc(&c->refcount);
5686 if (unlikely(!hpsa_is_cmd_idle(c))) {
5687 /*
5688 * We expect that the SCSI layer will hand us a unique tag
5689 * value. Thus, there should never be a collision here between
5690 * two requests...because if the selected command isn't idle
5691 * then someone is going to be very disappointed.
5692 */
5693 dev_err(&h->pdev->dev,
5694 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
5695 idx);
5696 if (c->scsi_cmd != NULL)
5697 scsi_print_command(c->scsi_cmd);
5698 scsi_print_command(scmd);
5699 }
5700
5701 hpsa_cmd_partial_init(h, idx, c);
5702 return c;
5703}
5704
5705static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
5706{
5707 /*
5708 * Release our reference to the block. We don't need to do anything
5709 * else to free it, because it is accessed by index. (There's no point
5710 * in checking the result of the decrement, since we cannot guarantee
5711 * that there isn't a concurrent abort which is also accessing it.)
5712 */
5713 (void)atomic_dec(&c->refcount);
5714}
5715
edd16368
SC		 5716/*
5717 * For operations that cannot sleep, a command block is allocated at init,
5718 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
5719 * which ones are free or in use. Lock must be held when calling this.
5720 * cmd_free() is the complement.
bf43caf3
RE		 5721 * This function never gives up and returns NULL. If it hangs,
5722 * another thread must call cmd_free() to free some tags.
edd16368 5723 */
281a7fd0 5724
edd16368
SC		 5725static struct CommandList *cmd_alloc(struct ctlr_info *h)
5726{
5727 struct CommandList *c;
360c73bd 5728 int refcount, i;
73153fe5 5729 int offset = 0;
4c413128 5730
33811026
RE		 5731 /*
5732 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 5733 * multiple threads could get in here, and one thread could
5734 * be scanning through the list of bits looking for a free
5735 * one, but the free ones are always behind him, and other
5736 * threads sneak in behind him and eat them before he can
5737 * get to them, so that while there is always a free one, a
5738 * very unlucky thread might be starved anyway, never able to
5739 * beat the other threads. In reality, this happens so
5740 * infrequently as to be indistinguishable from never.
73153fe5
WS		 5741 *
5742 * Note that we start allocating commands before the SCSI host structure
5743 * is initialized. Since the search starts at bit zero, this
5744 * all works, since we have at least one command structure available;
5745 * however, it means that the structures with the low indexes have to be
5746 * reserved for driver-initiated requests, while requests from the block
5747 * layer will use the higher indexes.
4c413128 5748 */
edd16368 5749
281a7fd0 5750 for (;;) {
73153fe5
WS		 5751 i = find_next_zero_bit(h->cmd_pool_bits,
5752 HPSA_NRESERVED_CMDS,
5753 offset);
5754 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
281a7fd0
WS		 5755 offset = 0;
5756 continue;
5757 }
5758 c = h->cmd_pool + i;
5759 refcount = atomic_inc_return(&c->refcount);
5760 if (unlikely(refcount > 1)) {
5761 cmd_free(h, c); /* already in use */
73153fe5 5762 offset = (i + 1) % HPSA_NRESERVED_CMDS;
281a7fd0
WS		 5763 continue;
5764 }
5765 set_bit(i & (BITS_PER_LONG - 1),
5766 h->cmd_pool_bits + (i / BITS_PER_LONG));
5767 break; /* it's ours now. */
5768 }
360c73bd 5769 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 5770 return c;
5771}
5772
73153fe5
WS		 5773/*
5774 * This is the complementary operation to cmd_alloc(). Note, however, in some
5775 * corner cases it may also be used to free blocks allocated by
5776 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
5777 * the clear-bit is harmless.
5778 */
edd16368
SC		 5779static void cmd_free(struct ctlr_info *h, struct CommandList *c)
5780{
281a7fd0
WS		 5781 if (atomic_dec_and_test(&c->refcount)) {
5782 int i;
edd16368 5783
281a7fd0
WS		 5784 i = c - h->cmd_pool;
5785 clear_bit(i & (BITS_PER_LONG - 1),
5786 h->cmd_pool_bits + (i / BITS_PER_LONG));
5787 }
edd16368
SC		 5788}
5789
edd16368
SC		 5790#ifdef CONFIG_COMPAT
5791
42a91641
DB		 5792static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
5793 void __user *arg)
edd16368
SC		 5794{
5795 IOCTL32_Command_struct __user *arg32 =
5796 (IOCTL32_Command_struct __user *) arg;
5797 IOCTL_Command_struct arg64;
5798 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5799 int err;
5800 u32 cp;
5801
938abd84 5802 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5803 err = 0;
5804 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5805 sizeof(arg64.LUN_info));
5806 err |= copy_from_user(&arg64.Request, &arg32->Request,
5807 sizeof(arg64.Request));
5808 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5809 sizeof(arg64.error_info));
5810 err |= get_user(arg64.buf_size, &arg32->buf_size);
5811 err |= get_user(cp, &arg32->buf);
5812 arg64.buf = compat_ptr(cp);
5813 err |= copy_to_user(p, &arg64, sizeof(arg64));
5814
5815 if (err)
5816 return -EFAULT;
5817
42a91641 5818 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 5819 if (err)
5820 return err;
5821 err |= copy_in_user(&arg32->error_info, &p->error_info,
5822 sizeof(arg32->error_info));
5823 if (err)
5824 return -EFAULT;
5825 return err;
5826}
5827
5828static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 5829 int cmd, void __user *arg)
edd16368
SC		 5830{
5831 BIG_IOCTL32_Command_struct __user *arg32 =
5832 (BIG_IOCTL32_Command_struct __user *) arg;
5833 BIG_IOCTL_Command_struct arg64;
5834 BIG_IOCTL_Command_struct __user *p =
5835 compat_alloc_user_space(sizeof(arg64));
5836 int err;
5837 u32 cp;
5838
938abd84 5839 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5840 err = 0;
5841 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5842 sizeof(arg64.LUN_info));
5843 err |= copy_from_user(&arg64.Request, &arg32->Request,
5844 sizeof(arg64.Request));
5845 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5846 sizeof(arg64.error_info));
5847 err |= get_user(arg64.buf_size, &arg32->buf_size);
5848 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5849 err |= get_user(cp, &arg32->buf);
5850 arg64.buf = compat_ptr(cp);
5851 err |= copy_to_user(p, &arg64, sizeof(arg64));
5852
5853 if (err)
5854 return -EFAULT;
5855
42a91641 5856 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 5857 if (err)
5858 return err;
5859 err |= copy_in_user(&arg32->error_info, &p->error_info,
5860 sizeof(arg32->error_info));
5861 if (err)
5862 return -EFAULT;
5863 return err;
5864}
71fe75a7 5865
42a91641 5866static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 5867{
5868 switch (cmd) {
5869 case CCISS_GETPCIINFO:
5870 case CCISS_GETINTINFO:
5871 case CCISS_SETINTINFO:
5872 case CCISS_GETNODENAME:
5873 case CCISS_SETNODENAME:
5874 case CCISS_GETHEARTBEAT:
5875 case CCISS_GETBUSTYPES:
5876 case CCISS_GETFIRMVER:
5877 case CCISS_GETDRIVVER:
5878 case CCISS_REVALIDVOLS:
5879 case CCISS_DEREGDISK:
5880 case CCISS_REGNEWDISK:
5881 case CCISS_REGNEWD:
5882 case CCISS_RESCANDISK:
5883 case CCISS_GETLUNINFO:
5884 return hpsa_ioctl(dev, cmd, arg);
5885
5886 case CCISS_PASSTHRU32:
5887 return hpsa_ioctl32_passthru(dev, cmd, arg);
5888 case CCISS_BIG_PASSTHRU32:
5889 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5890
5891 default:
5892 return -ENOIOCTLCMD;
5893 }
5894}
edd16368
SC		 5895#endif
5896
5897static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5898{
5899 struct hpsa_pci_info pciinfo;
5900
5901 if (!argp)
5902 return -EINVAL;
5903 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5904 pciinfo.bus = h->pdev->bus->number;
5905 pciinfo.dev_fn = h->pdev->devfn;
5906 pciinfo.board_id = h->board_id;
5907 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5908 return -EFAULT;
5909 return 0;
5910}
5911
5912static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
5913{
5914 DriverVer_type DriverVer;
5915 unsigned char vmaj, vmin, vsubmin;
5916 int rc;
5917
5918 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
5919 &vmaj, &vmin, &vsubmin);
5920 if (rc != 3) {
5921 dev_info(&h->pdev->dev, "driver version string '%s' "
5922 "unrecognized.", HPSA_DRIVER_VERSION);
5923 vmaj = 0;
5924 vmin = 0;
5925 vsubmin = 0;
5926 }
5927 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
5928 if (!argp)
5929 return -EINVAL;
5930 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
5931 return -EFAULT;
5932 return 0;
5933}
5934
5935static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5936{
5937 IOCTL_Command_struct iocommand;
5938 struct CommandList *c;
5939 char *buff = NULL;
50a0decf 5940 u64 temp64;
c1f63c8f 5941 int rc = 0;
edd16368
SC		 5942
5943 if (!argp)
5944 return -EINVAL;
5945 if (!capable(CAP_SYS_RAWIO))
5946 return -EPERM;
5947 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
5948 return -EFAULT;
5949 if ((iocommand.buf_size < 1) &&
5950 (iocommand.Request.Type.Direction != XFER_NONE)) {
5951 return -EINVAL;
5952 }
5953 if (iocommand.buf_size > 0) {
5954 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
5955 if (buff == NULL)
2dd02d74 5956 return -ENOMEM;
9233fb10 5957 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 5958 /* Copy the data into the buffer we created */
5959 if (copy_from_user(buff, iocommand.buf,
5960 iocommand.buf_size)) {
c1f63c8f
SC		 5961 rc = -EFAULT;
5962 goto out_kfree;
b03a7771
SC		 5963 }
5964 } else {
5965 memset(buff, 0, iocommand.buf_size);
edd16368 5966 }
b03a7771 5967 }
45fcb86e 5968 c = cmd_alloc(h);
bf43caf3 5969
edd16368
SC		 5970 /* Fill in the command type */
5971 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 5972 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 5973 /* Fill in Command Header */
5974 c->Header.ReplyQueue = 0; /* unused in simple mode */
5975 if (iocommand.buf_size > 0) { /* buffer to fill */
5976 c->Header.SGList = 1;
50a0decf 5977 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5978 } else { /* no buffers to fill */
5979 c->Header.SGList = 0;
50a0decf 5980 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 5981 }
5982 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5983
5984 /* Fill in Request block */
5985 memcpy(&c->Request, &iocommand.Request,
5986 sizeof(c->Request));
5987
5988 /* Fill in the scatter gather information */
5989 if (iocommand.buf_size > 0) {
50a0decf 5990 temp64 = pci_map_single(h->pdev, buff,
edd16368 5991 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5992 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
5993 c->SG[0].Addr = cpu_to_le64(0);
5994 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 5995 rc = -ENOMEM;
5996 goto out;
5997 }
50a0decf
SC		 5998 c->SG[0].Addr = cpu_to_le64(temp64);
5999 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
6000 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 6001 }
25163bd5 6002 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
c2dd32e0
SC		 6003 if (iocommand.buf_size > 0)
6004 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 6005 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6006 if (rc) {
6007 rc = -EIO;
6008 goto out;
6009 }
edd16368
SC		 6010
6011 /* Copy the error information out */
6012 memcpy(&iocommand.error_info, c->err_info,
6013 sizeof(iocommand.error_info));
6014 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 6015 rc = -EFAULT;
6016 goto out;
edd16368 6017 }
9233fb10 6018 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 6019 iocommand.buf_size > 0) {
edd16368
SC		 6020 /* Copy the data out of the buffer we created */
6021 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 6022 rc = -EFAULT;
6023 goto out;
edd16368
SC		 6024 }
6025 }
c1f63c8f 6026out:
45fcb86e 6027 cmd_free(h, c);
c1f63c8f
SC		 6028out_kfree:
6029 kfree(buff);
6030 return rc;
edd16368
SC		 6031}
6032
6033static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6034{
6035 BIG_IOCTL_Command_struct *ioc;
6036 struct CommandList *c;
6037 unsigned char **buff = NULL;
6038 int *buff_size = NULL;
50a0decf 6039 u64 temp64;
edd16368
SC		 6040 BYTE sg_used = 0;
6041 int status = 0;
01a02ffc
SC		 6042 u32 left;
6043 u32 sz;
edd16368
SC		 6044 BYTE __user *data_ptr;
6045
6046 if (!argp)
6047 return -EINVAL;
6048 if (!capable(CAP_SYS_RAWIO))
6049 return -EPERM;
6050 ioc = (BIG_IOCTL_Command_struct *)
6051 kmalloc(sizeof(*ioc), GFP_KERNEL);
6052 if (!ioc) {
6053 status = -ENOMEM;
6054 goto cleanup1;
6055 }
6056 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
6057 status = -EFAULT;
6058 goto cleanup1;
6059 }
6060 if ((ioc->buf_size < 1) &&
6061 (ioc->Request.Type.Direction != XFER_NONE)) {
6062 status = -EINVAL;
6063 goto cleanup1;
6064 }
6065 /* Check kmalloc limits using all SGs */
6066 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
6067 status = -EINVAL;
6068 goto cleanup1;
6069 }
d66ae08b 6070 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 6071 status = -EINVAL;
6072 goto cleanup1;
6073 }
d66ae08b 6074 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 6075 if (!buff) {
6076 status = -ENOMEM;
6077 goto cleanup1;
6078 }
d66ae08b 6079 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 6080 if (!buff_size) {
6081 status = -ENOMEM;
6082 goto cleanup1;
6083 }
6084 left = ioc->buf_size;
6085 data_ptr = ioc->buf;
6086 while (left) {
6087 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6088 buff_size[sg_used] = sz;
6089 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6090 if (buff[sg_used] == NULL) {
6091 status = -ENOMEM;
6092 goto cleanup1;
6093 }
9233fb10 6094 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 6095 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 6096 status = -EFAULT;
edd16368
SC		 6097 goto cleanup1;
6098 }
6099 } else
6100 memset(buff[sg_used], 0, sz);
6101 left -= sz;
6102 data_ptr += sz;
6103 sg_used++;
6104 }
45fcb86e 6105 c = cmd_alloc(h);
bf43caf3 6106
edd16368 6107 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6108 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368 6109 c->Header.ReplyQueue = 0;
50a0decf
SC		 6110 c->Header.SGList = (u8) sg_used;
6111 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 6112 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6113 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6114 if (ioc->buf_size > 0) {
6115 int i;
6116 for (i = 0; i < sg_used; i++) {
50a0decf 6117 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 6118 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6119 if (dma_mapping_error(&h->pdev->dev,
6120 (dma_addr_t) temp64)) {
6121 c->SG[i].Addr = cpu_to_le64(0);
6122 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 6123 hpsa_pci_unmap(h->pdev, c, i,
6124 PCI_DMA_BIDIRECTIONAL);
6125 status = -ENOMEM;
e2d4a1f6 6126 goto cleanup0;
bcc48ffa 6127 }
50a0decf
SC		 6128 c->SG[i].Addr = cpu_to_le64(temp64);
6129 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6130 c->SG[i].Ext = cpu_to_le32(0);
edd16368 6131 }
50a0decf 6132 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 6133 }
25163bd5 6134 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
b03a7771
SC		 6135 if (sg_used)
6136 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 6137 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6138 if (status) {
6139 status = -EIO;
6140 goto cleanup0;
6141 }
6142
edd16368
SC		 6143 /* Copy the error information out */
6144 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6145 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 6146 status = -EFAULT;
e2d4a1f6 6147 goto cleanup0;
edd16368 6148 }
9233fb10 6149 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 6150 int i;
6151
edd16368
SC		 6152 /* Copy the data out of the buffer we created */
6153 BYTE __user *ptr = ioc->buf;
6154 for (i = 0; i < sg_used; i++) {
6155 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 6156 status = -EFAULT;
e2d4a1f6 6157 goto cleanup0;
edd16368
SC		 6158 }
6159 ptr += buff_size[i];
6160 }
6161 }
edd16368 6162 status = 0;
e2d4a1f6 6163cleanup0:
45fcb86e 6164 cmd_free(h, c);
edd16368
SC		 6165cleanup1:
6166 if (buff) {
2b08b3e9
DB		 6167 int i;
6168
edd16368
SC		 6169 for (i = 0; i < sg_used; i++)
6170 kfree(buff[i]);
6171 kfree(buff);
6172 }
6173 kfree(buff_size);
6174 kfree(ioc);
6175 return status;
6176}
6177
6178static void check_ioctl_unit_attention(struct ctlr_info *h,
6179 struct CommandList *c)
6180{
6181 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6182 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6183 (void) check_for_unit_attention(h, c);
6184}
0390f0c0 6185
edd16368
SC		 6186/*
6187 * ioctl
6188 */
42a91641 6189static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 6190{
6191 struct ctlr_info *h;
6192 void __user *argp = (void __user *)arg;
0390f0c0 6193 int rc;
edd16368
SC		 6194
6195 h = sdev_to_hba(dev);
6196
6197 switch (cmd) {
6198 case CCISS_DEREGDISK:
6199 case CCISS_REGNEWDISK:
6200 case CCISS_REGNEWD:
a08a8471 6201 hpsa_scan_start(h->scsi_host);
edd16368
SC		 6202 return 0;
6203 case CCISS_GETPCIINFO:
6204 return hpsa_getpciinfo_ioctl(h, argp);
6205 case CCISS_GETDRIVVER:
6206 return hpsa_getdrivver_ioctl(h, argp);
6207 case CCISS_PASSTHRU:
34f0c627 6208 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6209 return -EAGAIN;
6210 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 6211 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6212 return rc;
edd16368 6213 case CCISS_BIG_PASSTHRU:
34f0c627 6214 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6215 return -EAGAIN;
6216 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 6217 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6218 return rc;
edd16368
SC		 6219 default:
6220 return -ENOTTY;
6221 }
6222}
6223
bf43caf3 6224static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6f039790 6225 u8 reset_type)
64670ac8
SC		 6226{
6227 struct CommandList *c;
6228
6229 c = cmd_alloc(h);
bf43caf3 6230
a2dac136
SC		 6231 /* fill_cmd can't fail here, no data buffer to map */
6232 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 6233 RAID_CTLR_LUNID, TYPE_MSG);
6234 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6235 c->waiting = NULL;
6236 enqueue_cmd_and_start_io(h, c);
6237 /* Don't wait for completion, the reset won't complete. Don't free
6238 * the command either. This is the last command we will send before
6239 * re-initializing everything, so it doesn't matter and won't leak.
6240 */
bf43caf3 6241 return;
64670ac8
SC		 6242}
6243
a2dac136 6244static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 6245 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 6246 int cmd_type)
6247{
6248 int pci_dir = XFER_NONE;
9b5c48c2 6249 u64 tag; /* for commands to be aborted */
edd16368
SC		 6250
6251 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6252 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6253 c->Header.ReplyQueue = 0;
6254 if (buff != NULL && size > 0) {
6255 c->Header.SGList = 1;
50a0decf 6256 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6257 } else {
6258 c->Header.SGList = 0;
50a0decf 6259 c->Header.SGTotal = cpu_to_le16(0);
edd16368 6260 }
edd16368
SC		 6261 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6262
edd16368
SC		 6263 if (cmd_type == TYPE_CMD) {
6264 switch (cmd) {
6265 case HPSA_INQUIRY:
6266 /* are we trying to read a vital product page */
b7bb24eb 6267 if (page_code & VPD_PAGE) {
edd16368 6268 c->Request.CDB[1] = 0x01;
b7bb24eb 6269 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 6270 }
6271 c->Request.CDBLen = 6;
a505b86f
SC		 6272 c->Request.type_attr_dir =
6273 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6274 c->Request.Timeout = 0;
6275 c->Request.CDB[0] = HPSA_INQUIRY;
6276 c->Request.CDB[4] = size & 0xFF;
6277 break;
6278 case HPSA_REPORT_LOG:
6279 case HPSA_REPORT_PHYS:
6280 /* Talking to controller so It's a physical command
6281 mode = 00 target = 0. Nothing to write.
6282 */
6283 c->Request.CDBLen = 12;
a505b86f
SC		 6284 c->Request.type_attr_dir =
6285 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6286 c->Request.Timeout = 0;
6287 c->Request.CDB[0] = cmd;
6288 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6289 c->Request.CDB[7] = (size >> 16) & 0xFF;
6290 c->Request.CDB[8] = (size >> 8) & 0xFF;
6291 c->Request.CDB[9] = size & 0xFF;
6292 break;
edd16368
SC		 6293 case HPSA_CACHE_FLUSH:
6294 c->Request.CDBLen = 12;
a505b86f
SC		 6295 c->Request.type_attr_dir =
6296 TYPE_ATTR_DIR(cmd_type,
6297 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 6298 c->Request.Timeout = 0;
6299 c->Request.CDB[0] = BMIC_WRITE;
6300 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 6301 c->Request.CDB[7] = (size >> 8) & 0xFF;
6302 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 6303 break;
6304 case TEST_UNIT_READY:
6305 c->Request.CDBLen = 6;
a505b86f
SC		 6306 c->Request.type_attr_dir =
6307 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 6308 c->Request.Timeout = 0;
6309 break;
283b4a9b
SC		 6310 case HPSA_GET_RAID_MAP:
6311 c->Request.CDBLen = 12;
a505b86f
SC		 6312 c->Request.type_attr_dir =
6313 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 6314 c->Request.Timeout = 0;
6315 c->Request.CDB[0] = HPSA_CISS_READ;
6316 c->Request.CDB[1] = cmd;
6317 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6318 c->Request.CDB[7] = (size >> 16) & 0xFF;
6319 c->Request.CDB[8] = (size >> 8) & 0xFF;
6320 c->Request.CDB[9] = size & 0xFF;
6321 break;
316b221a
SC		 6322 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6323 c->Request.CDBLen = 10;
a505b86f
SC		 6324 c->Request.type_attr_dir =
6325 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 6326 c->Request.Timeout = 0;
6327 c->Request.CDB[0] = BMIC_READ;
6328 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6329 c->Request.CDB[7] = (size >> 16) & 0xFF;
6330 c->Request.CDB[8] = (size >> 8) & 0xFF;
6331 break;
03383736
DB		 6332 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6333 c->Request.CDBLen = 10;
6334 c->Request.type_attr_dir =
6335 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6336 c->Request.Timeout = 0;
6337 c->Request.CDB[0] = BMIC_READ;
6338 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6339 c->Request.CDB[7] = (size >> 16) & 0xFF;
6340 c->Request.CDB[8] = (size >> 8) & 0XFF;
6341 break;
edd16368
SC		 6342 default:
6343 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6344 BUG();
a2dac136 6345 return -1;
edd16368
SC		 6346 }
6347 } else if (cmd_type == TYPE_MSG) {
6348 switch (cmd) {
6349
6350 case HPSA_DEVICE_RESET_MSG:
6351 c->Request.CDBLen = 16;
a505b86f
SC		 6352 c->Request.type_attr_dir =
6353 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 6354 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 6355 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6356 c->Request.CDB[0] = cmd;
21e89afd 6357 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 6358 /* If bytes 4-7 are zero, it means reset the */
6359 /* LunID device */
6360 c->Request.CDB[4] = 0x00;
6361 c->Request.CDB[5] = 0x00;
6362 c->Request.CDB[6] = 0x00;
6363 c->Request.CDB[7] = 0x00;
75167d2c
SC		 6364 break;
6365 case HPSA_ABORT_MSG:
9b5c48c2 6366 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 6367 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 6368 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
6369 tag, c->Header.tag);
75167d2c 6370 c->Request.CDBLen = 16;
a505b86f
SC		 6371 c->Request.type_attr_dir =
6372 TYPE_ATTR_DIR(cmd_type,
6373 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 6374 c->Request.Timeout = 0; /* Don't time out */
6375 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
6376 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
6377 c->Request.CDB[2] = 0x00; /* reserved */
6378 c->Request.CDB[3] = 0x00; /* reserved */
6379 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 6380 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 6381 c->Request.CDB[12] = 0x00; /* reserved */
6382 c->Request.CDB[13] = 0x00; /* reserved */
6383 c->Request.CDB[14] = 0x00; /* reserved */
6384 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 6385 break;
edd16368
SC		 6386 default:
6387 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6388 cmd);
6389 BUG();
6390 }
6391 } else {
6392 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6393 BUG();
6394 }
6395
a505b86f 6396 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 6397 case XFER_READ:
6398 pci_dir = PCI_DMA_FROMDEVICE;
6399 break;
6400 case XFER_WRITE:
6401 pci_dir = PCI_DMA_TODEVICE;
6402 break;
6403 case XFER_NONE:
6404 pci_dir = PCI_DMA_NONE;
6405 break;
6406 default:
6407 pci_dir = PCI_DMA_BIDIRECTIONAL;
6408 }
a2dac136
SC		 6409 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
6410 return -1;
6411 return 0;
edd16368
SC		 6412}
6413
6414/*
6415 * Map (physical) PCI mem into (virtual) kernel space
6416 */
6417static void __iomem *remap_pci_mem(ulong base, ulong size)
6418{
6419 ulong page_base = ((ulong) base) & PAGE_MASK;
6420 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 6421 void __iomem *page_remapped = ioremap_nocache(page_base,
6422 page_offs + size);
edd16368
SC		 6423
6424 return page_remapped ? (page_remapped + page_offs) : NULL;
6425}
6426
254f796b 6427static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 6428{
254f796b 6429 return h->access.command_completed(h, q);
edd16368
SC		 6430}
6431
900c5440 6432static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 6433{
6434 return h->access.intr_pending(h);
6435}
6436
6437static inline long interrupt_not_for_us(struct ctlr_info *h)
6438{
10f66018
SC		 6439 return (h->access.intr_pending(h) == 0) ||
6440 (h->interrupts_enabled == 0);
edd16368
SC		 6441}
6442
01a02ffc
SC		 6443static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6444 u32 raw_tag)
edd16368
SC		 6445{
6446 if (unlikely(tag_index >= h->nr_cmds)) {
6447 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6448 return 1;
6449 }
6450 return 0;
6451}
6452
5a3d16f5 6453static inline void finish_cmd(struct CommandList *c)
edd16368 6454{
e85c5974 6455 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 6456 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6457 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 6458 complete_scsi_command(c);
8be986cc 6459 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
edd16368 6460 complete(c->waiting);
a104c99f
SC		 6461}
6462
303932fd 6463/* process completion of an indexed ("direct lookup") command */
1d94f94d 6464static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 6465 u32 raw_tag)
6466{
6467 u32 tag_index;
6468 struct CommandList *c;
6469
f2405db8 6470 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 6471 if (!bad_tag(h, tag_index, raw_tag)) {
6472 c = h->cmd_pool + tag_index;
6473 finish_cmd(c);
6474 }
303932fd
DB		 6475}
6476
64670ac8
SC		 6477/* Some controllers, like p400, will give us one interrupt
6478 * after a soft reset, even if we turned interrupts off.
6479 * Only need to check for this in the hpsa_xxx_discard_completions
6480 * functions.
6481 */
6482static int ignore_bogus_interrupt(struct ctlr_info *h)
6483{
6484 if (likely(!reset_devices))
6485 return 0;
6486
6487 if (likely(h->interrupts_enabled))
6488 return 0;
6489
6490 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
6491 "(known firmware bug.) Ignoring.\n");
6492
6493 return 1;
6494}
6495
254f796b
MG		 6496/*
6497 * Convert &h->q[x] (passed to interrupt handlers) back to h.
6498 * Relies on (h-q[x] == x) being true for x such that
6499 * 0 <= x < MAX_REPLY_QUEUES.
6500 */
6501static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 6502{
254f796b
MG		 6503 return container_of((queue - *queue), struct ctlr_info, q[0]);
6504}
6505
6506static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6507{
6508 struct ctlr_info *h = queue_to_hba(queue);
6509 u8 q = *(u8 *) queue;
64670ac8
SC		 6510 u32 raw_tag;
6511
6512 if (ignore_bogus_interrupt(h))
6513 return IRQ_NONE;
6514
6515 if (interrupt_not_for_us(h))
6516 return IRQ_NONE;
a0c12413 6517 h->last_intr_timestamp = get_jiffies_64();
64670ac8 6518 while (interrupt_pending(h)) {
254f796b 6519 raw_tag = get_next_completion(h, q);
64670ac8 6520 while (raw_tag != FIFO_EMPTY)
254f796b 6521 raw_tag = next_command(h, q);
64670ac8 6522 }
64670ac8
SC		 6523 return IRQ_HANDLED;
6524}
6525
254f796b 6526static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 6527{
254f796b 6528 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 6529 u32 raw_tag;
254f796b 6530 u8 q = *(u8 *) queue;
64670ac8
SC		 6531
6532 if (ignore_bogus_interrupt(h))
6533 return IRQ_NONE;
6534
a0c12413 6535 h->last_intr_timestamp = get_jiffies_64();
254f796b 6536 raw_tag = get_next_completion(h, q);
64670ac8 6537 while (raw_tag != FIFO_EMPTY)
254f796b 6538 raw_tag = next_command(h, q);
64670ac8
SC		 6539 return IRQ_HANDLED;
6540}
6541
254f796b 6542static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 6543{
254f796b 6544 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 6545 u32 raw_tag;
254f796b 6546 u8 q = *(u8 *) queue;
edd16368
SC		 6547
6548 if (interrupt_not_for_us(h))
6549 return IRQ_NONE;
a0c12413 6550 h->last_intr_timestamp = get_jiffies_64();
10f66018 6551 while (interrupt_pending(h)) {
254f796b 6552 raw_tag = get_next_completion(h, q);
10f66018 6553 while (raw_tag != FIFO_EMPTY) {
f2405db8 6554 process_indexed_cmd(h, raw_tag);
254f796b 6555 raw_tag = next_command(h, q);
10f66018
SC		 6556 }
6557 }
10f66018
SC		 6558 return IRQ_HANDLED;
6559}
6560
254f796b 6561static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 6562{
254f796b 6563 struct ctlr_info *h = queue_to_hba(queue);
10f66018 6564 u32 raw_tag;
254f796b 6565 u8 q = *(u8 *) queue;
10f66018 6566
a0c12413 6567 h->last_intr_timestamp = get_jiffies_64();
254f796b 6568 raw_tag = get_next_completion(h, q);
303932fd 6569 while (raw_tag != FIFO_EMPTY) {
f2405db8 6570 process_indexed_cmd(h, raw_tag);
254f796b 6571 raw_tag = next_command(h, q);
edd16368 6572 }
edd16368
SC		 6573 return IRQ_HANDLED;
6574}
6575
a9a3a273
SC		 6576/* Send a message CDB to the firmware. Careful, this only works
6577 * in simple mode, not performant mode due to the tag lookup.
6578 * We only ever use this immediately after a controller reset.
6579 */
6f039790
GKH		 6580static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
6581 unsigned char type)
edd16368
SC		 6582{
6583 struct Command {
6584 struct CommandListHeader CommandHeader;
6585 struct RequestBlock Request;
6586 struct ErrDescriptor ErrorDescriptor;
6587 };
6588 struct Command *cmd;
6589 static const size_t cmd_sz = sizeof(*cmd) +
6590 sizeof(cmd->ErrorDescriptor);
6591 dma_addr_t paddr64;
2b08b3e9
DB		 6592 __le32 paddr32;
6593 u32 tag;
edd16368
SC		 6594 void __iomem *vaddr;
6595 int i, err;
6596
6597 vaddr = pci_ioremap_bar(pdev, 0);
6598 if (vaddr == NULL)
6599 return -ENOMEM;
6600
6601 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
6602 * CCISS commands, so they must be allocated from the lower 4GiB of
6603 * memory.
6604 */
6605 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6606 if (err) {
6607 iounmap(vaddr);
1eaec8f3 6608 return err;
edd16368
SC		 6609 }
6610
6611 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
6612 if (cmd == NULL) {
6613 iounmap(vaddr);
6614 return -ENOMEM;
6615 }
6616
6617 /* This must fit, because of the 32-bit consistent DMA mask. Also,
6618 * although there's no guarantee, we assume that the address is at
6619 * least 4-byte aligned (most likely, it's page-aligned).
6620 */
2b08b3e9 6621 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 6622
6623 cmd->CommandHeader.ReplyQueue = 0;
6624 cmd->CommandHeader.SGList = 0;
50a0decf 6625 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 6626 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 6627 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
6628
6629 cmd->Request.CDBLen = 16;
a505b86f
SC		 6630 cmd->Request.type_attr_dir =
6631 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 6632 cmd->Request.Timeout = 0; /* Don't time out */
6633 cmd->Request.CDB[0] = opcode;
6634 cmd->Request.CDB[1] = type;
6635 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 6636 cmd->ErrorDescriptor.Addr =
2b08b3e9 6637 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 6638 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 6639
2b08b3e9 6640 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 6641
6642 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
6643 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 6644 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 6645 break;
6646 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
6647 }
6648
6649 iounmap(vaddr);
6650
6651 /* we leak the DMA buffer here ... no choice since the controller could
6652 * still complete the command.
6653 */
6654 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
6655 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
6656 opcode, type);
6657 return -ETIMEDOUT;
6658 }
6659
6660 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
6661
6662 if (tag & HPSA_ERROR_BIT) {
6663 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
6664 opcode, type);
6665 return -EIO;
6666 }
6667
6668 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
6669 opcode, type);
6670 return 0;
6671}
6672
edd16368
SC		 6673#define hpsa_noop(p) hpsa_message(p, 3, 0)
6674
1df8552a 6675static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 6676 void __iomem *vaddr, u32 use_doorbell)
1df8552a 6677{
1df8552a
SC		 6678
6679 if (use_doorbell) {
6680 /* For everything after the P600, the PCI power state method
6681 * of resetting the controller doesn't work, so we have this
6682 * other way using the doorbell register.
6683 */
6684 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 6685 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 6686
00701a96 6687 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 6688 * doorbell reset and before any attempt to talk to the board
6689 * at all to ensure that this actually works and doesn't fall
6690 * over in some weird corner cases.
6691 */
00701a96 6692 msleep(10000);
1df8552a
SC		 6693 } else { /* Try to do it the PCI power state way */
6694
6695 /* Quoting from the Open CISS Specification: "The Power
6696 * Management Control/Status Register (CSR) controls the power
6697 * state of the device. The normal operating state is D0,
6698 * CSR=00h. The software off state is D3, CSR=03h. To reset
6699 * the controller, place the interface device in D3 then to D0,
6700 * this causes a secondary PCI reset which will reset the
6701 * controller." */
2662cab8
DB		 6702
6703 int rc = 0;
6704
1df8552a 6705 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 6706
1df8552a 6707 /* enter the D3hot power management state */
2662cab8
DB		 6708 rc = pci_set_power_state(pdev, PCI_D3hot);
6709 if (rc)
6710 return rc;
1df8552a
SC		 6711
6712 msleep(500);
6713
6714 /* enter the D0 power management state */
2662cab8
DB		 6715 rc = pci_set_power_state(pdev, PCI_D0);
6716 if (rc)
6717 return rc;
c4853efe
MM		 6718
6719 /*
6720 * The P600 requires a small delay when changing states.
6721 * Otherwise we may think the board did not reset and we bail.
6722 * This for kdump only and is particular to the P600.
6723 */
6724 msleep(500);
1df8552a
SC		 6725 }
6726 return 0;
6727}
6728
6f039790 6729static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 6730{
6731 memset(driver_version, 0, len);
f79cfec6 6732 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 6733}
6734
6f039790 6735static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6736{
6737 char *driver_version;
6738 int i, size = sizeof(cfgtable->driver_version);
6739
6740 driver_version = kmalloc(size, GFP_KERNEL);
6741 if (!driver_version)
6742 return -ENOMEM;
6743
6744 init_driver_version(driver_version, size);
6745 for (i = 0; i < size; i++)
6746 writeb(driver_version[i], &cfgtable->driver_version[i]);
6747 kfree(driver_version);
6748 return 0;
6749}
6750
6f039790
GKH		 6751static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
6752 unsigned char *driver_ver)
580ada3c
SC		 6753{
6754 int i;
6755
6756 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
6757 driver_ver[i] = readb(&cfgtable->driver_version[i]);
6758}
6759
6f039790 6760static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6761{
6762
6763 char *driver_ver, *old_driver_ver;
6764 int rc, size = sizeof(cfgtable->driver_version);
6765
6766 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
6767 if (!old_driver_ver)
6768 return -ENOMEM;
6769 driver_ver = old_driver_ver + size;
6770
6771 /* After a reset, the 32 bytes of "driver version" in the cfgtable
6772 * should have been changed, otherwise we know the reset failed.
6773 */
6774 init_driver_version(old_driver_ver, size);
6775 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
6776 rc = !memcmp(driver_ver, old_driver_ver, size);
6777 kfree(old_driver_ver);
6778 return rc;
6779}
edd16368 6780/* This does a hard reset of the controller using PCI power management
1df8552a 6781 * states or the using the doorbell register.
edd16368 6782 */
6b6c1cd7 6783static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 6784{
1df8552a
SC		 6785 u64 cfg_offset;
6786 u32 cfg_base_addr;
6787 u64 cfg_base_addr_index;
6788 void __iomem *vaddr;
6789 unsigned long paddr;
580ada3c 6790 u32 misc_fw_support;
270d05de 6791 int rc;
1df8552a 6792 struct CfgTable __iomem *cfgtable;
cf0b08d0 6793 u32 use_doorbell;
270d05de 6794 u16 command_register;
edd16368 6795
1df8552a
SC		 6796 /* For controllers as old as the P600, this is very nearly
6797 * the same thing as
edd16368
SC		 6798 *
6799 * pci_save_state(pci_dev);
6800 * pci_set_power_state(pci_dev, PCI_D3hot);
6801 * pci_set_power_state(pci_dev, PCI_D0);
6802 * pci_restore_state(pci_dev);
6803 *
1df8552a
SC		 6804 * For controllers newer than the P600, the pci power state
6805 * method of resetting doesn't work so we have another way
6806 * using the doorbell register.
edd16368 6807 */
18867659 6808
60f923b9
RE		 6809 if (!ctlr_is_resettable(board_id)) {
6810 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 6811 return -ENODEV;
6812 }
46380786
SC		 6813
6814 /* if controller is soft- but not hard resettable... */
6815 if (!ctlr_is_hard_resettable(board_id))
6816 return -ENOTSUPP; /* try soft reset later. */
18867659 6817
270d05de
SC		 6818 /* Save the PCI command register */
6819 pci_read_config_word(pdev, 4, &command_register);
270d05de 6820 pci_save_state(pdev);
edd16368 6821
1df8552a
SC		 6822 /* find the first memory BAR, so we can find the cfg table */
6823 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6824 if (rc)
6825 return rc;
6826 vaddr = remap_pci_mem(paddr, 0x250);
6827 if (!vaddr)
6828 return -ENOMEM;
edd16368 6829
1df8552a
SC		 6830 /* find cfgtable in order to check if reset via doorbell is supported */
6831 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6832 &cfg_base_addr_index, &cfg_offset);
6833 if (rc)
6834 goto unmap_vaddr;
6835 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6836 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6837 if (!cfgtable) {
6838 rc = -ENOMEM;
6839 goto unmap_vaddr;
6840 }
580ada3c
SC		 6841 rc = write_driver_ver_to_cfgtable(cfgtable);
6842 if (rc)
03741d95 6843 goto unmap_cfgtable;
edd16368 6844
cf0b08d0
SC		 6845 /* If reset via doorbell register is supported, use that.
6846 * There are two such methods. Favor the newest method.
6847 */
1df8552a 6848 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6849 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6850 if (use_doorbell) {
6851 use_doorbell = DOORBELL_CTLR_RESET2;
6852 } else {
6853 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6854 if (use_doorbell) {
050f7147
SC		 6855 dev_warn(&pdev->dev,
6856 "Soft reset not supported. Firmware update is required.\n");
64670ac8 6857 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6858 goto unmap_cfgtable;
6859 }
6860 }
edd16368 6861
1df8552a
SC		 6862 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6863 if (rc)
6864 goto unmap_cfgtable;
edd16368 6865
270d05de 6866 pci_restore_state(pdev);
270d05de 6867 pci_write_config_word(pdev, 4, command_register);
edd16368 6868
1df8552a
SC		 6869 /* Some devices (notably the HP Smart Array 5i Controller)
6870 need a little pause here */
6871 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6872
fe5389c8
SC		 6873 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6874 if (rc) {
6875 dev_warn(&pdev->dev,
050f7147 6876 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 6877 goto unmap_cfgtable;
6878 }
fe5389c8 6879
580ada3c
SC		 6880 rc = controller_reset_failed(vaddr);
6881 if (rc < 0)
6882 goto unmap_cfgtable;
6883 if (rc) {
64670ac8
SC		 6884 dev_warn(&pdev->dev, "Unable to successfully reset "
6885 "controller. Will try soft reset.\n");
6886 rc = -ENOTSUPP;
580ada3c 6887 } else {
64670ac8 6888 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6889 }
6890
6891unmap_cfgtable:
6892 iounmap(cfgtable);
6893
6894unmap_vaddr:
6895 iounmap(vaddr);
6896 return rc;
edd16368
SC		 6897}
6898
6899/*
6900 * We cannot read the structure directly, for portability we must use
6901 * the io functions.
6902 * This is for debug only.
6903 */
42a91641 6904static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 6905{
58f8665c 6906#ifdef HPSA_DEBUG
edd16368
SC		 6907 int i;
6908 char temp_name[17];
6909
6910 dev_info(dev, "Controller Configuration information\n");
6911 dev_info(dev, "------------------------------------\n");
6912 for (i = 0; i < 4; i++)
6913 temp_name[i] = readb(&(tb->Signature[i]));
6914 temp_name[4] = '\0';
6915 dev_info(dev, " Signature = %s\n", temp_name);
6916 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6917 dev_info(dev, " Transport methods supported = 0x%x\n",
6918 readl(&(tb->TransportSupport)));
6919 dev_info(dev, " Transport methods active = 0x%x\n",
6920 readl(&(tb->TransportActive)));
6921 dev_info(dev, " Requested transport Method = 0x%x\n",
6922 readl(&(tb->HostWrite.TransportRequest)));
6923 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6924 readl(&(tb->HostWrite.CoalIntDelay)));
6925 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6926 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 6927 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 6928 readl(&(tb->CmdsOutMax)));
6929 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6930 for (i = 0; i < 16; i++)
6931 temp_name[i] = readb(&(tb->ServerName[i]));
6932 temp_name[16] = '\0';
6933 dev_info(dev, " Server Name = %s\n", temp_name);
6934 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6935 readl(&(tb->HeartBeat)));
edd16368 6936#endif /* HPSA_DEBUG */
58f8665c 6937}
edd16368
SC		 6938
6939static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6940{
6941 int i, offset, mem_type, bar_type;
6942
6943 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6944 return 0;
6945 offset = 0;
6946 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6947 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6948 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6949 offset += 4;
6950 else {
6951 mem_type = pci_resource_flags(pdev, i) &
6952 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6953 switch (mem_type) {
6954 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6955 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6956 offset += 4; /* 32 bit */
6957 break;
6958 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6959 offset += 8;
6960 break;
6961 default: /* reserved in PCI 2.2 */
6962 dev_warn(&pdev->dev,
6963 "base address is invalid\n");
6964 return -1;
6965 break;
6966 }
6967 }
6968 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6969 return i + 1;
6970 }
6971 return -1;
6972}
6973
cc64c817
RE		 6974static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
6975{
6976 if (h->msix_vector) {
6977 if (h->pdev->msix_enabled)
6978 pci_disable_msix(h->pdev);
105a3dbc 6979 h->msix_vector = 0;
cc64c817
RE		 6980 } else if (h->msi_vector) {
6981 if (h->pdev->msi_enabled)
6982 pci_disable_msi(h->pdev);
105a3dbc 6983 h->msi_vector = 0;
cc64c817
RE		 6984 }
6985}
6986
edd16368 6987/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 6988 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 6989 */
6f039790 6990static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6991{
6992#ifdef CONFIG_PCI_MSI
254f796b
MG		 6993 int err, i;
6994 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6995
6996 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6997 hpsa_msix_entries[i].vector = 0;
6998 hpsa_msix_entries[i].entry = i;
6999 }
edd16368
SC		 7000
7001 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 7002 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
7003 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 7004 goto default_int_mode;
55c06c71 7005 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 7006 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 7007 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 7008 if (h->msix_vector > num_online_cpus())
7009 h->msix_vector = num_online_cpus();
18fce3c4
AG		 7010 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
7011 1, h->msix_vector);
7012 if (err < 0) {
7013 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
7014 h->msix_vector = 0;
7015 goto single_msi_mode;
7016 } else if (err < h->msix_vector) {
55c06c71 7017 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 7018 "available\n", err);
edd16368 7019 }
18fce3c4
AG		 7020 h->msix_vector = err;
7021 for (i = 0; i < h->msix_vector; i++)
7022 h->intr[i] = hpsa_msix_entries[i].vector;
7023 return;
edd16368 7024 }
18fce3c4 7025single_msi_mode:
55c06c71 7026 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 7027 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 7028 if (!pci_enable_msi(h->pdev))
edd16368
SC		 7029 h->msi_vector = 1;
7030 else
55c06c71 7031 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 7032 }
7033default_int_mode:
7034#endif /* CONFIG_PCI_MSI */
7035 /* if we get here we're going to use the default interrupt mode */
a9a3a273 7036 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 7037}
7038
6f039790 7039static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 7040{
7041 int i;
7042 u32 subsystem_vendor_id, subsystem_device_id;
7043
7044 subsystem_vendor_id = pdev->subsystem_vendor;
7045 subsystem_device_id = pdev->subsystem_device;
7046 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
7047 subsystem_vendor_id;
7048
7049 for (i = 0; i < ARRAY_SIZE(products); i++)
7050 if (*board_id == products[i].board_id)
7051 return i;
7052
6798cc0a
SC		 7053 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
7054 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
7055 !hpsa_allow_any) {
e5c880d1
SC		 7056 dev_warn(&pdev->dev, "unrecognized board ID: "
7057 "0x%08x, ignoring.\n", *board_id);
7058 return -ENODEV;
7059 }
7060 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
7061}
7062
6f039790
GKH		 7063static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
7064 unsigned long *memory_bar)
3a7774ce
SC		 7065{
7066 int i;
7067
7068 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 7069 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 7070 /* addressing mode bits already removed */
12d2cd47
SC		 7071 *memory_bar = pci_resource_start(pdev, i);
7072 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 7073 *memory_bar);
7074 return 0;
7075 }
12d2cd47 7076 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 7077 return -ENODEV;
7078}
7079
6f039790
GKH		 7080static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7081 int wait_for_ready)
2c4c8c8b 7082{
fe5389c8 7083 int i, iterations;
2c4c8c8b 7084 u32 scratchpad;
fe5389c8
SC		 7085 if (wait_for_ready)
7086 iterations = HPSA_BOARD_READY_ITERATIONS;
7087 else
7088 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 7089
fe5389c8
SC		 7090 for (i = 0; i < iterations; i++) {
7091 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7092 if (wait_for_ready) {
7093 if (scratchpad == HPSA_FIRMWARE_READY)
7094 return 0;
7095 } else {
7096 if (scratchpad != HPSA_FIRMWARE_READY)
7097 return 0;
7098 }
2c4c8c8b
SC		 7099 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7100 }
fe5389c8 7101 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 7102 return -ENODEV;
7103}
7104
6f039790
GKH		 7105static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7106 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7107 u64 *cfg_offset)
a51fd47f
SC		 7108{
7109 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7110 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7111 *cfg_base_addr &= (u32) 0x0000ffff;
7112 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7113 if (*cfg_base_addr_index == -1) {
7114 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7115 return -ENODEV;
7116 }
7117 return 0;
7118}
7119
195f2c65
RE		 7120static void hpsa_free_cfgtables(struct ctlr_info *h)
7121{
105a3dbc 7122 if (h->transtable) {
195f2c65 7123 iounmap(h->transtable);
105a3dbc
RE		 7124 h->transtable = NULL;
7125 }
7126 if (h->cfgtable) {
195f2c65 7127 iounmap(h->cfgtable);
105a3dbc
RE		 7128 h->cfgtable = NULL;
7129 }
195f2c65
RE		 7130}
7131
7132/* Find and map CISS config table and transfer table
7133+ * several items must be unmapped (freed) later
7134+ * */
6f039790 7135static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 7136{
01a02ffc
SC		 7137 u64 cfg_offset;
7138 u32 cfg_base_addr;
7139 u64 cfg_base_addr_index;
303932fd 7140 u32 trans_offset;
a51fd47f 7141 int rc;
77c4495c 7142
a51fd47f
SC		 7143 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7144 &cfg_base_addr_index, &cfg_offset);
7145 if (rc)
7146 return rc;
77c4495c 7147 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 7148 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 7149 if (!h->cfgtable) {
7150 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 7151 return -ENOMEM;
cd3c81c4 7152 }
580ada3c
SC		 7153 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7154 if (rc)
7155 return rc;
77c4495c 7156 /* Find performant mode table. */
a51fd47f 7157 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 7158 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7159 cfg_base_addr_index)+cfg_offset+trans_offset,
7160 sizeof(*h->transtable));
195f2c65
RE		 7161 if (!h->transtable) {
7162 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7163 hpsa_free_cfgtables(h);
77c4495c 7164 return -ENOMEM;
195f2c65 7165 }
77c4495c
SC		 7166 return 0;
7167}
7168
6f039790 7169static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 7170{
41ce4c35
SC		 7171#define MIN_MAX_COMMANDS 16
7172 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7173
7174 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 7175
7176 /* Limit commands in memory limited kdump scenario. */
7177 if (reset_devices && h->max_commands > 32)
7178 h->max_commands = 32;
7179
41ce4c35
SC		 7180 if (h->max_commands < MIN_MAX_COMMANDS) {
7181 dev_warn(&h->pdev->dev,
7182 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7183 h->max_commands,
7184 MIN_MAX_COMMANDS);
7185 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 7186 }
7187}
7188
c7ee65b3
WS		 7189/* If the controller reports that the total max sg entries is greater than 512,
7190 * then we know that chained SG blocks work. (Original smart arrays did not
7191 * support chained SG blocks and would return zero for max sg entries.)
7192 */
7193static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7194{
7195 return h->maxsgentries > 512;
7196}
7197
b93d7536
SC		 7198/* Interrogate the hardware for some limits:
7199 * max commands, max SG elements without chaining, and with chaining,
7200 * SG chain block size, etc.
7201 */
6f039790 7202static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 7203{
cba3d38b 7204 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 7205 h->nr_cmds = h->max_commands;
b93d7536 7206 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 7207 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 7208 if (hpsa_supports_chained_sg_blocks(h)) {
7209 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 7210 h->max_cmd_sg_entries = 32;
1a63ea6f 7211 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 7212 h->maxsgentries--; /* save one for chain pointer */
7213 } else {
c7ee65b3
WS		 7214 /*
7215 * Original smart arrays supported at most 31 s/g entries
7216 * embedded inline in the command (trying to use more
7217 * would lock up the controller)
7218 */
7219 h->max_cmd_sg_entries = 31;
1a63ea6f 7220 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 7221 h->chainsize = 0;
b93d7536 7222 }
75167d2c
SC		 7223
7224 /* Find out what task management functions are supported and cache */
7225 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 7226 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7227 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7228 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7229 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
8be986cc
SC		 7230 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7231 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
b93d7536
SC		 7232}
7233
76c46e49
SC		 7234static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7235{
0fc9fd40 7236 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 7237 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 7238 return false;
7239 }
7240 return true;
7241}
7242
97a5e98c 7243static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 7244{
97a5e98c 7245 u32 driver_support;
f7c39101 7246
97a5e98c 7247 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 7248 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7249#ifdef CONFIG_X86
97a5e98c 7250 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 7251#endif
28e13446
SC		 7252 driver_support |= ENABLE_UNIT_ATTN;
7253 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 7254}
7255
3d0eab67
SC		 7256/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7257 * in a prefetch beyond physical memory.
7258 */
7259static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7260{
7261 u32 dma_prefetch;
7262
7263 if (h->board_id != 0x3225103C)
7264 return;
7265 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7266 dma_prefetch |= 0x8000;
7267 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7268}
7269
c706a795 7270static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 7271{
7272 int i;
7273 u32 doorbell_value;
7274 unsigned long flags;
7275 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 7276 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 7277 spin_lock_irqsave(&h->lock, flags);
7278 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7279 spin_unlock_irqrestore(&h->lock, flags);
7280 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 7281 goto done;
76438d08 7282 /* delay and try again */
007e7aa9 7283 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 7284 }
c706a795
RE		 7285 return -ENODEV;
7286done:
7287 return 0;
76438d08
SC		 7288}
7289
c706a795 7290static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 7291{
7292 int i;
6eaf46fd
SC		 7293 u32 doorbell_value;
7294 unsigned long flags;
eb6b2ae9
SC		 7295
7296 /* under certain very rare conditions, this can take awhile.
7297 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7298 * as we enter this code.)
7299 */
007e7aa9 7300 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 7301 if (h->remove_in_progress)
7302 goto done;
6eaf46fd
SC		 7303 spin_lock_irqsave(&h->lock, flags);
7304 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7305 spin_unlock_irqrestore(&h->lock, flags);
382be668 7306 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 7307 goto done;
eb6b2ae9 7308 /* delay and try again */
007e7aa9 7309 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 7310 }
c706a795
RE		 7311 return -ENODEV;
7312done:
7313 return 0;
3f4336f3
SC		 7314}
7315
c706a795 7316/* return -ENODEV or other reason on error, 0 on success */
6f039790 7317static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 7318{
7319 u32 trans_support;
7320
7321 trans_support = readl(&(h->cfgtable->TransportSupport));
7322 if (!(trans_support & SIMPLE_MODE))
7323 return -ENOTSUPP;
7324
7325 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 7326
3f4336f3
SC		 7327 /* Update the field, and then ring the doorbell */
7328 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 7329 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 7330 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7331 if (hpsa_wait_for_mode_change_ack(h))
7332 goto error;
eb6b2ae9 7333 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 7334 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7335 goto error;
960a30e7 7336 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 7337 return 0;
283b4a9b 7338error:
050f7147 7339 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 7340 return -ENODEV;
eb6b2ae9
SC		 7341}
7342
195f2c65
RE		 7343/* free items allocated or mapped by hpsa_pci_init */
7344static void hpsa_free_pci_init(struct ctlr_info *h)
7345{
7346 hpsa_free_cfgtables(h); /* pci_init 4 */
7347 iounmap(h->vaddr); /* pci_init 3 */
105a3dbc 7348 h->vaddr = NULL;
195f2c65 7349 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
943a7021
RE		 7350 /*
7351 * call pci_disable_device before pci_release_regions per
7352 * Documentation/PCI/pci.txt
7353 */
195f2c65 7354 pci_disable_device(h->pdev); /* pci_init 1 */
943a7021 7355 pci_release_regions(h->pdev); /* pci_init 2 */
195f2c65
RE		 7356}
7357
7358/* several items must be freed later */
6f039790 7359static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 7360{
eb6b2ae9 7361 int prod_index, err;
edd16368 7362
e5c880d1
SC		 7363 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
7364 if (prod_index < 0)
60f923b9 7365 return prod_index;
e5c880d1
SC		 7366 h->product_name = products[prod_index].product_name;
7367 h->access = *(products[prod_index].access);
edd16368 7368
9b5c48c2
SC		 7369 h->needs_abort_tags_swizzled =
7370 ctlr_needs_abort_tags_swizzled(h->board_id);
7371
e5a44df8
MG		 7372 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7373 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7374
55c06c71 7375 err = pci_enable_device(h->pdev);
edd16368 7376 if (err) {
195f2c65 7377 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
943a7021 7378 pci_disable_device(h->pdev);
edd16368
SC		 7379 return err;
7380 }
7381
f79cfec6 7382 err = pci_request_regions(h->pdev, HPSA);
edd16368 7383 if (err) {
55c06c71 7384 dev_err(&h->pdev->dev,
195f2c65 7385 "failed to obtain PCI resources\n");
943a7021
RE		 7386 pci_disable_device(h->pdev);
7387 return err;
edd16368 7388 }
4fa604e1
RE		 7389
7390 pci_set_master(h->pdev);
7391
6b3f4c52 7392 hpsa_interrupt_mode(h);
12d2cd47 7393 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 7394 if (err)
195f2c65 7395 goto clean2; /* intmode+region, pci */
edd16368 7396 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 7397 if (!h->vaddr) {
195f2c65 7398 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 7399 err = -ENOMEM;
195f2c65 7400 goto clean2; /* intmode+region, pci */
204892e9 7401 }
fe5389c8 7402 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 7403 if (err)
195f2c65 7404 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 7405 err = hpsa_find_cfgtables(h);
7406 if (err)
195f2c65 7407 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 7408 hpsa_find_board_params(h);
edd16368 7409
76c46e49 7410 if (!hpsa_CISS_signature_present(h)) {
edd16368 7411 err = -ENODEV;
195f2c65 7412 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 7413 }
97a5e98c 7414 hpsa_set_driver_support_bits(h);
3d0eab67 7415 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 7416 err = hpsa_enter_simple_mode(h);
7417 if (err)
195f2c65 7418 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 7419 return 0;
7420
195f2c65
RE		 7421clean4: /* cfgtables, vaddr, intmode+region, pci */
7422 hpsa_free_cfgtables(h);
7423clean3: /* vaddr, intmode+region, pci */
7424 iounmap(h->vaddr);
105a3dbc 7425 h->vaddr = NULL;
195f2c65
RE		 7426clean2: /* intmode+region, pci */
7427 hpsa_disable_interrupt_mode(h);
943a7021
RE		 7428 /*
7429 * call pci_disable_device before pci_release_regions per
7430 * Documentation/PCI/pci.txt
7431 */
195f2c65 7432 pci_disable_device(h->pdev);
943a7021 7433 pci_release_regions(h->pdev);
edd16368
SC		 7434 return err;
7435}
7436
6f039790 7437static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 7438{
7439 int rc;
7440
7441#define HBA_INQUIRY_BYTE_COUNT 64
7442 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7443 if (!h->hba_inquiry_data)
7444 return;
7445 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7446 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7447 if (rc != 0) {
7448 kfree(h->hba_inquiry_data);
7449 h->hba_inquiry_data = NULL;
7450 }
7451}
7452
6b6c1cd7 7453static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 7454{
1df8552a 7455 int rc, i;
3b747298 7456 void __iomem *vaddr;
4c2a8c40
SC		 7457
7458 if (!reset_devices)
7459 return 0;
7460
132aa220
TH		 7461 /* kdump kernel is loading, we don't know in which state is
7462 * the pci interface. The dev->enable_cnt is equal zero
7463 * so we call enable+disable, wait a while and switch it on.
7464 */
7465 rc = pci_enable_device(pdev);
7466 if (rc) {
7467 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7468 return -ENODEV;
7469 }
7470 pci_disable_device(pdev);
7471 msleep(260); /* a randomly chosen number */
7472 rc = pci_enable_device(pdev);
7473 if (rc) {
7474 dev_warn(&pdev->dev, "failed to enable device.\n");
7475 return -ENODEV;
7476 }
4fa604e1 7477
859c75ab 7478 pci_set_master(pdev);
4fa604e1 7479
3b747298
TH		 7480 vaddr = pci_ioremap_bar(pdev, 0);
7481 if (vaddr == NULL) {
7482 rc = -ENOMEM;
7483 goto out_disable;
7484 }
7485 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
7486 iounmap(vaddr);
7487
1df8552a 7488 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 7489 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 7490
1df8552a
SC		 7491 /* -ENOTSUPP here means we cannot reset the controller
7492 * but it's already (and still) up and running in
18867659
SC		 7493 * "performant mode". Or, it might be 640x, which can't reset
7494 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 7495 */
adf1b3a3 7496 if (rc)
132aa220 7497 goto out_disable;
4c2a8c40
SC		 7498
7499 /* Now try to get the controller to respond to a no-op */
1ba66c9c 7500 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 7501 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
7502 if (hpsa_noop(pdev) == 0)
7503 break;
7504 else
7505 dev_warn(&pdev->dev, "no-op failed%s\n",
7506 (i < 11 ? "; re-trying" : ""));
7507 }
132aa220
TH		 7508
7509out_disable:
7510
7511 pci_disable_device(pdev);
7512 return rc;
4c2a8c40
SC		 7513}
7514
1fb7c98a
RE		 7515static void hpsa_free_cmd_pool(struct ctlr_info *h)
7516{
7517 kfree(h->cmd_pool_bits);
105a3dbc
RE		 7518 h->cmd_pool_bits = NULL;
7519 if (h->cmd_pool) {
1fb7c98a
RE		 7520 pci_free_consistent(h->pdev,
7521 h->nr_cmds * sizeof(struct CommandList),
7522 h->cmd_pool,
7523 h->cmd_pool_dhandle);
105a3dbc
RE		 7524 h->cmd_pool = NULL;
7525 h->cmd_pool_dhandle = 0;
7526 }
7527 if (h->errinfo_pool) {
1fb7c98a
RE		 7528 pci_free_consistent(h->pdev,
7529 h->nr_cmds * sizeof(struct ErrorInfo),
7530 h->errinfo_pool,
7531 h->errinfo_pool_dhandle);
105a3dbc
RE		 7532 h->errinfo_pool = NULL;
7533 h->errinfo_pool_dhandle = 0;
7534 }
1fb7c98a
RE		 7535}
7536
d37ffbe4 7537static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 7538{
7539 h->cmd_pool_bits = kzalloc(
7540 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
7541 sizeof(unsigned long), GFP_KERNEL);
7542 h->cmd_pool = pci_alloc_consistent(h->pdev,
7543 h->nr_cmds * sizeof(*h->cmd_pool),
7544 &(h->cmd_pool_dhandle));
7545 h->errinfo_pool = pci_alloc_consistent(h->pdev,
7546 h->nr_cmds * sizeof(*h->errinfo_pool),
7547 &(h->errinfo_pool_dhandle));
7548 if ((h->cmd_pool_bits == NULL)
7549 || (h->cmd_pool == NULL)
7550 || (h->errinfo_pool == NULL)) {
7551 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 7552 goto clean_up;
2e9d1b36 7553 }
360c73bd 7554 hpsa_preinitialize_commands(h);
2e9d1b36 7555 return 0;
2c143342
RE		 7556clean_up:
7557 hpsa_free_cmd_pool(h);
7558 return -ENOMEM;
2e9d1b36
SC		 7559}
7560
41b3cf08
SC		 7561static void hpsa_irq_affinity_hints(struct ctlr_info *h)
7562{
ec429952 7563 int i, cpu;
41b3cf08
SC		 7564
7565 cpu = cpumask_first(cpu_online_mask);
7566 for (i = 0; i < h->msix_vector; i++) {
ec429952 7567 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 7568 cpu = cpumask_next(cpu, cpu_online_mask);
7569 }
7570}
7571
ec501a18
RE		 7572/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
7573static void hpsa_free_irqs(struct ctlr_info *h)
7574{
7575 int i;
7576
7577 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
7578 /* Single reply queue, only one irq to free */
7579 i = h->intr_mode;
7580 irq_set_affinity_hint(h->intr[i], NULL);
7581 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7582 h->q[i] = 0;
ec501a18
RE		 7583 return;
7584 }
7585
7586 for (i = 0; i < h->msix_vector; i++) {
7587 irq_set_affinity_hint(h->intr[i], NULL);
7588 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7589 h->q[i] = 0;
ec501a18 7590 }
a4e17fc1
RE		 7591 for (; i < MAX_REPLY_QUEUES; i++)
7592 h->q[i] = 0;
ec501a18
RE		 7593}
7594
9ee61794
RE		 7595/* returns 0 on success; cleans up and returns -Enn on error */
7596static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 7597 irqreturn_t (*msixhandler)(int, void *),
7598 irqreturn_t (*intxhandler)(int, void *))
7599{
254f796b 7600 int rc, i;
0ae01a32 7601
254f796b
MG		 7602 /*
7603 * initialize h->q[x] = x so that interrupt handlers know which
7604 * queue to process.
7605 */
7606 for (i = 0; i < MAX_REPLY_QUEUES; i++)
7607 h->q[i] = (u8) i;
7608
eee0f03a 7609 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 7610 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 7611 for (i = 0; i < h->msix_vector; i++) {
8b47004a 7612 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
254f796b 7613 rc = request_irq(h->intr[i], msixhandler,
8b47004a 7614 0, h->intrname[i],
254f796b 7615 &h->q[i]);
a4e17fc1
RE		 7616 if (rc) {
7617 int j;
7618
7619 dev_err(&h->pdev->dev,
7620 "failed to get irq %d for %s\n",
7621 h->intr[i], h->devname);
7622 for (j = 0; j < i; j++) {
7623 free_irq(h->intr[j], &h->q[j]);
7624 h->q[j] = 0;
7625 }
7626 for (; j < MAX_REPLY_QUEUES; j++)
7627 h->q[j] = 0;
7628 return rc;
7629 }
7630 }
41b3cf08 7631 hpsa_irq_affinity_hints(h);
254f796b
MG		 7632 } else {
7633 /* Use single reply pool */
eee0f03a 7634 if (h->msix_vector > 0 || h->msi_vector) {
8b47004a
RE		 7635 if (h->msix_vector)
7636 sprintf(h->intrname[h->intr_mode],
7637 "%s-msix", h->devname);
7638 else
7639 sprintf(h->intrname[h->intr_mode],
7640 "%s-msi", h->devname);
254f796b 7641 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7642 msixhandler, 0,
7643 h->intrname[h->intr_mode],
254f796b
MG		 7644 &h->q[h->intr_mode]);
7645 } else {
8b47004a
RE		 7646 sprintf(h->intrname[h->intr_mode],
7647 "%s-intx", h->devname);
254f796b 7648 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7649 intxhandler, IRQF_SHARED,
7650 h->intrname[h->intr_mode],
254f796b
MG		 7651 &h->q[h->intr_mode]);
7652 }
105a3dbc 7653 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
254f796b 7654 }
0ae01a32 7655 if (rc) {
195f2c65 7656 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 7657 h->intr[h->intr_mode], h->devname);
195f2c65 7658 hpsa_free_irqs(h);
0ae01a32
SC		 7659 return -ENODEV;
7660 }
7661 return 0;
7662}
7663
6f039790 7664static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8 7665{
39c53f55 7666 int rc;
bf43caf3 7667 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
64670ac8
SC		 7668
7669 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
39c53f55
RE		 7670 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
7671 if (rc) {
64670ac8 7672 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
39c53f55 7673 return rc;
64670ac8
SC		 7674 }
7675
7676 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
39c53f55
RE		 7677 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
7678 if (rc) {
64670ac8
SC		 7679 dev_warn(&h->pdev->dev, "Board failed to become ready "
7680 "after soft reset.\n");
39c53f55 7681 return rc;
64670ac8
SC		 7682 }
7683
7684 return 0;
7685}
7686
072b0518
SC		 7687static void hpsa_free_reply_queues(struct ctlr_info *h)
7688{
7689 int i;
7690
7691 for (i = 0; i < h->nreply_queues; i++) {
7692 if (!h->reply_queue[i].head)
7693 continue;
1fb7c98a
RE		 7694 pci_free_consistent(h->pdev,
7695 h->reply_queue_size,
7696 h->reply_queue[i].head,
7697 h->reply_queue[i].busaddr);
072b0518
SC		 7698 h->reply_queue[i].head = NULL;
7699 h->reply_queue[i].busaddr = 0;
7700 }
105a3dbc 7701 h->reply_queue_size = 0;
072b0518
SC		 7702}
7703
0097f0f4
SC		 7704static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
7705{
105a3dbc
RE		 7706 hpsa_free_performant_mode(h); /* init_one 7 */
7707 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
7708 hpsa_free_cmd_pool(h); /* init_one 5 */
7709 hpsa_free_irqs(h); /* init_one 4 */
2946e82b
RE		 7710 scsi_host_put(h->scsi_host); /* init_one 3 */
7711 h->scsi_host = NULL; /* init_one 3 */
7712 hpsa_free_pci_init(h); /* init_one 2_5 */
9ecd953a
RE		 7713 free_percpu(h->lockup_detected); /* init_one 2 */
7714 h->lockup_detected = NULL; /* init_one 2 */
7715 if (h->resubmit_wq) {
7716 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
7717 h->resubmit_wq = NULL;
7718 }
7719 if (h->rescan_ctlr_wq) {
7720 destroy_workqueue(h->rescan_ctlr_wq);
7721 h->rescan_ctlr_wq = NULL;
7722 }
105a3dbc 7723 kfree(h); /* init_one 1 */
64670ac8
SC		 7724}
7725
a0c12413 7726/* Called when controller lockup detected. */
f2405db8 7727static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 7728{
281a7fd0
WS		 7729 int i, refcount;
7730 struct CommandList *c;
25163bd5 7731 int failcount = 0;
a0c12413 7732
080ef1cc 7733 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 7734 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7735 c = h->cmd_pool + i;
281a7fd0
WS		 7736 refcount = atomic_inc_return(&c->refcount);
7737 if (refcount > 1) {
25163bd5 7738 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 7739 finish_cmd(c);
433b5f4d 7740 atomic_dec(&h->commands_outstanding);
25163bd5 7741 failcount++;
281a7fd0
WS		 7742 }
7743 cmd_free(h, c);
a0c12413 7744 }
25163bd5
WS		 7745 dev_warn(&h->pdev->dev,
7746 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 7747}
7748
094963da
SC		 7749static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
7750{
c8ed0010 7751 int cpu;
094963da 7752
c8ed0010 7753 for_each_online_cpu(cpu) {
094963da
SC		 7754 u32 *lockup_detected;
7755 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
7756 *lockup_detected = value;
094963da
SC		 7757 }
7758 wmb(); /* be sure the per-cpu variables are out to memory */
7759}
7760
a0c12413
SC		 7761static void controller_lockup_detected(struct ctlr_info *h)
7762{
7763 unsigned long flags;
094963da 7764 u32 lockup_detected;
a0c12413 7765
a0c12413
SC		 7766 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7767 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 7768 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
7769 if (!lockup_detected) {
7770 /* no heartbeat, but controller gave us a zero. */
7771 dev_warn(&h->pdev->dev,
25163bd5
WS		 7772 "lockup detected after %d but scratchpad register is zero\n",
7773 h->heartbeat_sample_interval / HZ);
094963da
SC		 7774 lockup_detected = 0xffffffff;
7775 }
7776 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 7777 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 7778 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
7779 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 7780 pci_disable_device(h->pdev);
f2405db8 7781 fail_all_outstanding_cmds(h);
a0c12413
SC		 7782}
7783
25163bd5 7784static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 7785{
7786 u64 now;
7787 u32 heartbeat;
7788 unsigned long flags;
7789
a0c12413
SC		 7790 now = get_jiffies_64();
7791 /* If we've received an interrupt recently, we're ok. */
7792 if (time_after64(h->last_intr_timestamp +
e85c5974 7793 (h->heartbeat_sample_interval), now))
25163bd5 7794 return false;
a0c12413
SC		 7795
7796 /*
7797 * If we've already checked the heartbeat recently, we're ok.
7798 * This could happen if someone sends us a signal. We
7799 * otherwise don't care about signals in this thread.
7800 */
7801 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 7802 (h->heartbeat_sample_interval), now))
25163bd5 7803 return false;
a0c12413
SC		 7804
7805 /* If heartbeat has not changed since we last looked, we're not ok. */
7806 spin_lock_irqsave(&h->lock, flags);
7807 heartbeat = readl(&h->cfgtable->HeartBeat);
7808 spin_unlock_irqrestore(&h->lock, flags);
7809 if (h->last_heartbeat == heartbeat) {
7810 controller_lockup_detected(h);
25163bd5 7811 return true;
a0c12413
SC		 7812 }
7813
7814 /* We're ok. */
7815 h->last_heartbeat = heartbeat;
7816 h->last_heartbeat_timestamp = now;
25163bd5 7817 return false;
a0c12413
SC		 7818}
7819
9846590e 7820static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 7821{
7822 int i;
7823 char *event_type;
7824
e4aa3e6a
SC		 7825 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7826 return;
7827
76438d08 7828 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 7829 if ((h->transMethod & (CFGTBL_Trans_io_accel1
7830 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 7831 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
7832 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
7833
7834 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
7835 event_type = "state change";
7836 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
7837 event_type = "configuration change";
7838 /* Stop sending new RAID offload reqs via the IO accelerator */
7839 scsi_block_requests(h->scsi_host);
7840 for (i = 0; i < h->ndevices; i++)
7841 h->dev[i]->offload_enabled = 0;
23100dd9 7842 hpsa_drain_accel_commands(h);
76438d08
SC		 7843 /* Set 'accelerator path config change' bit */
7844 dev_warn(&h->pdev->dev,
7845 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7846 h->events, event_type);
7847 writel(h->events, &(h->cfgtable->clear_event_notify));
7848 /* Set the "clear event notify field update" bit 6 */
7849 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7850 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7851 hpsa_wait_for_clear_event_notify_ack(h);
7852 scsi_unblock_requests(h->scsi_host);
7853 } else {
7854 /* Acknowledge controller notification events. */
7855 writel(h->events, &(h->cfgtable->clear_event_notify));
7856 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7857 hpsa_wait_for_clear_event_notify_ack(h);
7858#if 0
7859 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7860 hpsa_wait_for_mode_change_ack(h);
7861#endif
7862 }
9846590e 7863 return;
76438d08
SC		 7864}
7865
7866/* Check a register on the controller to see if there are configuration
7867 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 7868 * we should rescan the controller for devices.
7869 * Also check flag for driver-initiated rescan.
76438d08 7870 */
9846590e 7871static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 7872{
853633e8
DB		 7873 if (h->drv_req_rescan) {
7874 h->drv_req_rescan = 0;
7875 return 1;
7876 }
7877
76438d08 7878 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 7879 return 0;
76438d08
SC		 7880
7881 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 7882 return h->events & RESCAN_REQUIRED_EVENT_BITS;
7883}
76438d08 7884
9846590e
SC		 7885/*
7886 * Check if any of the offline devices have become ready
7887 */
7888static int hpsa_offline_devices_ready(struct ctlr_info *h)
7889{
7890 unsigned long flags;
7891 struct offline_device_entry *d;
7892 struct list_head *this, *tmp;
7893
7894 spin_lock_irqsave(&h->offline_device_lock, flags);
7895 list_for_each_safe(this, tmp, &h->offline_device_list) {
7896 d = list_entry(this, struct offline_device_entry,
7897 offline_list);
7898 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 7899 if (!hpsa_volume_offline(h, d->scsi3addr)) {
7900 spin_lock_irqsave(&h->offline_device_lock, flags);
7901 list_del(&d->offline_list);
7902 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 7903 return 1;
d1fea47c 7904 }
9846590e
SC		 7905 spin_lock_irqsave(&h->offline_device_lock, flags);
7906 }
7907 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7908 return 0;
76438d08
SC		 7909}
7910
6636e7f4 7911static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 7912{
7913 unsigned long flags;
8a98db73 7914 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 7915 struct ctlr_info, rescan_ctlr_work);
7916
7917
7918 if (h->remove_in_progress)
8a98db73 7919 return;
9846590e
SC		 7920
7921 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
7922 scsi_host_get(h->scsi_host);
9846590e
SC		 7923 hpsa_ack_ctlr_events(h);
7924 hpsa_scan_start(h->scsi_host);
7925 scsi_host_put(h->scsi_host);
7926 }
8a98db73 7927 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 7928 if (!h->remove_in_progress)
7929 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7930 h->heartbeat_sample_interval);
7931 spin_unlock_irqrestore(&h->lock, flags);
7932}
7933
7934static void hpsa_monitor_ctlr_worker(struct work_struct *work)
7935{
7936 unsigned long flags;
7937 struct ctlr_info *h = container_of(to_delayed_work(work),
7938 struct ctlr_info, monitor_ctlr_work);
7939
7940 detect_controller_lockup(h);
7941 if (lockup_detected(h))
a0c12413 7942 return;
6636e7f4
DB		 7943
7944 spin_lock_irqsave(&h->lock, flags);
7945 if (!h->remove_in_progress)
7946 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 7947 h->heartbeat_sample_interval);
7948 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 7949}
7950
6636e7f4
DB		 7951static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
7952 char *name)
7953{
7954 struct workqueue_struct *wq = NULL;
6636e7f4 7955
397ea9cb 7956 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 7957 if (!wq)
7958 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
7959
7960 return wq;
7961}
7962
6f039790 7963static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 7964{
4c2a8c40 7965 int dac, rc;
edd16368 7966 struct ctlr_info *h;
64670ac8
SC		 7967 int try_soft_reset = 0;
7968 unsigned long flags;
6b6c1cd7 7969 u32 board_id;
edd16368
SC		 7970
7971 if (number_of_controllers == 0)
7972 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 7973
6b6c1cd7
TH		 7974 rc = hpsa_lookup_board_id(pdev, &board_id);
7975 if (rc < 0) {
7976 dev_warn(&pdev->dev, "Board ID not found\n");
7977 return rc;
7978 }
7979
7980 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 7981 if (rc) {
7982 if (rc != -ENOTSUPP)
7983 return rc;
7984 /* If the reset fails in a particular way (it has no way to do
7985 * a proper hard reset, so returns -ENOTSUPP) we can try to do
7986 * a soft reset once we get the controller configured up to the
7987 * point that it can accept a command.
7988 */
7989 try_soft_reset = 1;
7990 rc = 0;
7991 }
7992
7993reinit_after_soft_reset:
edd16368 7994
303932fd
DB		 7995 /* Command structures must be aligned on a 32-byte boundary because
7996 * the 5 lower bits of the address are used by the hardware. and by
7997 * the driver. See comments in hpsa.h for more info.
7998 */
303932fd 7999 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368 8000 h = kzalloc(sizeof(*h), GFP_KERNEL);
105a3dbc
RE		 8001 if (!h) {
8002 dev_err(&pdev->dev, "Failed to allocate controller head\n");
ecd9aad4 8003 return -ENOMEM;
105a3dbc 8004 }
edd16368 8005
55c06c71 8006 h->pdev = pdev;
105a3dbc 8007
a9a3a273 8008 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 8009 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 8010 spin_lock_init(&h->lock);
9846590e 8011 spin_lock_init(&h->offline_device_lock);
6eaf46fd 8012 spin_lock_init(&h->scan_lock);
34f0c627 8013 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 8014 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da
SC		 8015
8016 /* Allocate and clear per-cpu variable lockup_detected */
8017 h->lockup_detected = alloc_percpu(u32);
2a5ac326 8018 if (!h->lockup_detected) {
105a3dbc 8019 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
2a5ac326 8020 rc = -ENOMEM;
2efa5929 8021 goto clean1; /* aer/h */
2a5ac326 8022 }
094963da
SC		 8023 set_lockup_detected_for_all_cpus(h, 0);
8024
55c06c71 8025 rc = hpsa_pci_init(h);
105a3dbc 8026 if (rc)
2946e82b
RE		 8027 goto clean2; /* lu, aer/h */
8028
8029 /* relies on h-> settings made by hpsa_pci_init, including
8030 * interrupt_mode h->intr */
8031 rc = hpsa_scsi_host_alloc(h);
8032 if (rc)
8033 goto clean2_5; /* pci, lu, aer/h */
edd16368 8034
2946e82b 8035 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
edd16368
SC		 8036 h->ctlr = number_of_controllers;
8037 number_of_controllers++;
edd16368
SC		 8038
8039 /* configure PCI DMA stuff */
ecd9aad4
SC		 8040 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
8041 if (rc == 0) {
edd16368 8042 dac = 1;
ecd9aad4
SC		 8043 } else {
8044 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8045 if (rc == 0) {
8046 dac = 0;
8047 } else {
8048 dev_err(&pdev->dev, "no suitable DMA available\n");
2946e82b 8049 goto clean3; /* shost, pci, lu, aer/h */
ecd9aad4 8050 }
edd16368
SC		 8051 }
8052
8053 /* make sure the board interrupts are off */
8054 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 8055
105a3dbc
RE		 8056 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
8057 if (rc)
2946e82b 8058 goto clean3; /* shost, pci, lu, aer/h */
d37ffbe4 8059 rc = hpsa_alloc_cmd_pool(h);
8947fd10 8060 if (rc)
2946e82b 8061 goto clean4; /* irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8062 rc = hpsa_alloc_sg_chain_blocks(h);
8063 if (rc)
2946e82b 8064 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
a08a8471 8065 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 8066 init_waitqueue_head(&h->abort_cmd_wait_queue);
d604f533
WS		 8067 init_waitqueue_head(&h->event_sync_wait_queue);
8068 mutex_init(&h->reset_mutex);
a08a8471 8069 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 8070
8071 pci_set_drvdata(pdev, h);
9a41338e 8072 h->ndevices = 0;
2946e82b 8073
9a41338e 8074 spin_lock_init(&h->devlock);
105a3dbc
RE		 8075 rc = hpsa_put_ctlr_into_performant_mode(h);
8076 if (rc)
2946e82b
RE		 8077 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8078
8079 /* hook into SCSI subsystem */
8080 rc = hpsa_scsi_add_host(h);
8081 if (rc)
8082 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
2efa5929
RE		 8083
8084 /* create the resubmit workqueue */
8085 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8086 if (!h->rescan_ctlr_wq) {
8087 rc = -ENOMEM;
8088 goto clean7;
8089 }
8090
8091 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8092 if (!h->resubmit_wq) {
8093 rc = -ENOMEM;
8094 goto clean7; /* aer/h */
8095 }
64670ac8 8096
105a3dbc
RE		 8097 /*
8098 * At this point, the controller is ready to take commands.
64670ac8
SC		 8099 * Now, if reset_devices and the hard reset didn't work, try
8100 * the soft reset and see if that works.
8101 */
8102 if (try_soft_reset) {
8103
8104 /* This is kind of gross. We may or may not get a completion
8105 * from the soft reset command, and if we do, then the value
8106 * from the fifo may or may not be valid. So, we wait 10 secs
8107 * after the reset throwing away any completions we get during
8108 * that time. Unregister the interrupt handler and register
8109 * fake ones to scoop up any residual completions.
8110 */
8111 spin_lock_irqsave(&h->lock, flags);
8112 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8113 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 8114 hpsa_free_irqs(h);
9ee61794 8115 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 8116 hpsa_intx_discard_completions);
8117 if (rc) {
9ee61794
RE		 8118 dev_warn(&h->pdev->dev,
8119 "Failed to request_irq after soft reset.\n");
d498757c 8120 /*
b2ef480c
RE		 8121 * cannot goto clean7 or free_irqs will be called
8122 * again. Instead, do its work
8123 */
8124 hpsa_free_performant_mode(h); /* clean7 */
8125 hpsa_free_sg_chain_blocks(h); /* clean6 */
8126 hpsa_free_cmd_pool(h); /* clean5 */
8127 /*
8128 * skip hpsa_free_irqs(h) clean4 since that
8129 * was just called before request_irqs failed
d498757c
RE		 8130 */
8131 goto clean3;
64670ac8
SC		 8132 }
8133
8134 rc = hpsa_kdump_soft_reset(h);
8135 if (rc)
8136 /* Neither hard nor soft reset worked, we're hosed. */
7ef7323f 8137 goto clean7;
64670ac8
SC		 8138
8139 dev_info(&h->pdev->dev, "Board READY.\n");
8140 dev_info(&h->pdev->dev,
8141 "Waiting for stale completions to drain.\n");
8142 h->access.set_intr_mask(h, HPSA_INTR_ON);
8143 msleep(10000);
8144 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8145
8146 rc = controller_reset_failed(h->cfgtable);
8147 if (rc)
8148 dev_info(&h->pdev->dev,
8149 "Soft reset appears to have failed.\n");
8150
8151 /* since the controller's reset, we have to go back and re-init
8152 * everything. Easiest to just forget what we've done and do it
8153 * all over again.
8154 */
8155 hpsa_undo_allocations_after_kdump_soft_reset(h);
8156 try_soft_reset = 0;
8157 if (rc)
b2ef480c 8158 /* don't goto clean, we already unallocated */
64670ac8
SC		 8159 return -ENODEV;
8160
8161 goto reinit_after_soft_reset;
8162 }
edd16368 8163
105a3dbc
RE		 8164 /* Enable Accelerated IO path at driver layer */
8165 h->acciopath_status = 1;
da0697bd 8166
e863d68e 8167
edd16368
SC		 8168 /* Turn the interrupts on so we can service requests */
8169 h->access.set_intr_mask(h, HPSA_INTR_ON);
8170
339b2b14 8171 hpsa_hba_inquiry(h);
8a98db73
SC		 8172
8173 /* Monitor the controller for firmware lockups */
8174 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8175 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8176 schedule_delayed_work(&h->monitor_ctlr_work,
8177 h->heartbeat_sample_interval);
6636e7f4
DB		 8178 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8179 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8180 h->heartbeat_sample_interval);
88bf6d62 8181 return 0;
edd16368 8182
2946e82b 8183clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8184 hpsa_free_performant_mode(h);
8185 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8186clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
33a2ffce 8187 hpsa_free_sg_chain_blocks(h);
2946e82b 8188clean5: /* cmd, irq, shost, pci, lu, aer/h */
2e9d1b36 8189 hpsa_free_cmd_pool(h);
2946e82b 8190clean4: /* irq, shost, pci, lu, aer/h */
ec501a18 8191 hpsa_free_irqs(h);
2946e82b
RE		 8192clean3: /* shost, pci, lu, aer/h */
8193 scsi_host_put(h->scsi_host);
8194 h->scsi_host = NULL;
8195clean2_5: /* pci, lu, aer/h */
195f2c65 8196 hpsa_free_pci_init(h);
2946e82b 8197clean2: /* lu, aer/h */
105a3dbc
RE		 8198 if (h->lockup_detected) {
8199 free_percpu(h->lockup_detected);
8200 h->lockup_detected = NULL;
8201 }
8202clean1: /* wq/aer/h */
8203 if (h->resubmit_wq) {
080ef1cc 8204 destroy_workqueue(h->resubmit_wq);
105a3dbc
RE		 8205 h->resubmit_wq = NULL;
8206 }
8207 if (h->rescan_ctlr_wq) {
6636e7f4 8208 destroy_workqueue(h->rescan_ctlr_wq);
105a3dbc
RE		 8209 h->rescan_ctlr_wq = NULL;
8210 }
edd16368 8211 kfree(h);
ecd9aad4 8212 return rc;
edd16368
SC		 8213}
8214
8215static void hpsa_flush_cache(struct ctlr_info *h)
8216{
8217 char *flush_buf;
8218 struct CommandList *c;
25163bd5 8219 int rc;
702890e3 8220
094963da 8221 if (unlikely(lockup_detected(h)))
702890e3 8222 return;
edd16368
SC		 8223 flush_buf = kzalloc(4, GFP_KERNEL);
8224 if (!flush_buf)
8225 return;
8226
45fcb86e 8227 c = cmd_alloc(h);
bf43caf3 8228
a2dac136
SC		 8229 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8230 RAID_CTLR_LUNID, TYPE_CMD)) {
8231 goto out;
8232 }
25163bd5
WS		 8233 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8234 PCI_DMA_TODEVICE, NO_TIMEOUT);
8235 if (rc)
8236 goto out;
edd16368 8237 if (c->err_info->CommandStatus != 0)
a2dac136 8238out:
edd16368
SC		 8239 dev_warn(&h->pdev->dev,
8240 "error flushing cache on controller\n");
45fcb86e 8241 cmd_free(h, c);
edd16368
SC		 8242 kfree(flush_buf);
8243}
8244
8245static void hpsa_shutdown(struct pci_dev *pdev)
8246{
8247 struct ctlr_info *h;
8248
8249 h = pci_get_drvdata(pdev);
8250 /* Turn board interrupts off and send the flush cache command
8251 * sendcmd will turn off interrupt, and send the flush...
8252 * To write all data in the battery backed cache to disks
8253 */
8254 hpsa_flush_cache(h);
8255 h->access.set_intr_mask(h, HPSA_INTR_OFF);
105a3dbc 8256 hpsa_free_irqs(h); /* init_one 4 */
cc64c817 8257 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 8258}
8259
6f039790 8260static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 8261{
8262 int i;
8263
105a3dbc 8264 for (i = 0; i < h->ndevices; i++) {
55e14e76 8265 kfree(h->dev[i]);
105a3dbc
RE		 8266 h->dev[i] = NULL;
8267 }
55e14e76
SC		 8268}
8269
6f039790 8270static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 8271{
8272 struct ctlr_info *h;
8a98db73 8273 unsigned long flags;
edd16368
SC		 8274
8275 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 8276 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 8277 return;
8278 }
8279 h = pci_get_drvdata(pdev);
8a98db73
SC		 8280
8281 /* Get rid of any controller monitoring work items */
8282 spin_lock_irqsave(&h->lock, flags);
8283 h->remove_in_progress = 1;
8a98db73 8284 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 8285 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8286 cancel_delayed_work_sync(&h->rescan_ctlr_work);
8287 destroy_workqueue(h->rescan_ctlr_wq);
8288 destroy_workqueue(h->resubmit_wq);
cc64c817 8289
2d041306
DB		 8290 /*
8291 * Call before disabling interrupts.
8292 * scsi_remove_host can trigger I/O operations especially
8293 * when multipath is enabled. There can be SYNCHRONIZE CACHE
8294 * operations which cannot complete and will hang the system.
8295 */
8296 if (h->scsi_host)
8297 scsi_remove_host(h->scsi_host); /* init_one 8 */
105a3dbc 8298 /* includes hpsa_free_irqs - init_one 4 */
195f2c65 8299 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 8300 hpsa_shutdown(pdev);
cc64c817 8301
105a3dbc
RE		 8302 hpsa_free_device_info(h); /* scan */
8303
2946e82b
RE		 8304 kfree(h->hba_inquiry_data); /* init_one 10 */
8305 h->hba_inquiry_data = NULL; /* init_one 10 */
2946e82b 8306 hpsa_free_ioaccel2_sg_chain_blocks(h);
105a3dbc
RE		 8307 hpsa_free_performant_mode(h); /* init_one 7 */
8308 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8309 hpsa_free_cmd_pool(h); /* init_one 5 */
8310
8311 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
195f2c65 8312
2946e82b
RE		 8313 scsi_host_put(h->scsi_host); /* init_one 3 */
8314 h->scsi_host = NULL; /* init_one 3 */
8315
195f2c65 8316 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
2946e82b 8317 hpsa_free_pci_init(h); /* init_one 2.5 */
195f2c65 8318
105a3dbc
RE		 8319 free_percpu(h->lockup_detected); /* init_one 2 */
8320 h->lockup_detected = NULL; /* init_one 2 */
8321 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
8322 kfree(h); /* init_one 1 */
edd16368
SC		 8323}
8324
8325static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8326 __attribute__((unused)) pm_message_t state)
8327{
8328 return -ENOSYS;
8329}
8330
8331static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8332{
8333 return -ENOSYS;
8334}
8335
8336static struct pci_driver hpsa_pci_driver = {
f79cfec6 8337 .name = HPSA,
edd16368 8338 .probe = hpsa_init_one,
6f039790 8339 .remove = hpsa_remove_one,
edd16368
SC		 8340 .id_table = hpsa_pci_device_id, /* id_table */
8341 .shutdown = hpsa_shutdown,
8342 .suspend = hpsa_suspend,
8343 .resume = hpsa_resume,
8344};
8345
303932fd
DB		 8346/* Fill in bucket_map[], given nsgs (the max number of
8347 * scatter gather elements supported) and bucket[],
8348 * which is an array of 8 integers. The bucket[] array
8349 * contains 8 different DMA transfer sizes (in 16
8350 * byte increments) which the controller uses to fetch
8351 * commands. This function fills in bucket_map[], which
8352 * maps a given number of scatter gather elements to one of
8353 * the 8 DMA transfer sizes. The point of it is to allow the
8354 * controller to only do as much DMA as needed to fetch the
8355 * command, with the DMA transfer size encoded in the lower
8356 * bits of the command address.
8357 */
8358static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 8359 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 8360{
8361 int i, j, b, size;
8362
303932fd
DB		 8363 /* Note, bucket_map must have nsgs+1 entries. */
8364 for (i = 0; i <= nsgs; i++) {
8365 /* Compute size of a command with i SG entries */
e1f7de0c 8366 size = i + min_blocks;
303932fd
DB		 8367 b = num_buckets; /* Assume the biggest bucket */
8368 /* Find the bucket that is just big enough */
e1f7de0c 8369 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 8370 if (bucket[j] >= size) {
8371 b = j;
8372 break;
8373 }
8374 }
8375 /* for a command with i SG entries, use bucket b. */
8376 bucket_map[i] = b;
8377 }
8378}
8379
105a3dbc
RE		 8380/*
8381 * return -ENODEV on err, 0 on success (or no action)
8382 * allocates numerous items that must be freed later
8383 */
c706a795 8384static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 8385{
6c311b57
SC		 8386 int i;
8387 unsigned long register_value;
e1f7de0c
MG		 8388 unsigned long transMethod = CFGTBL_Trans_Performant |
8389 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 8390 CFGTBL_Trans_enable_directed_msix |
8391 (trans_support & (CFGTBL_Trans_io_accel1 |
8392 CFGTBL_Trans_io_accel2));
e1f7de0c 8393 struct access_method access = SA5_performant_access;
def342bd
SC		 8394
8395 /* This is a bit complicated. There are 8 registers on
8396 * the controller which we write to to tell it 8 different
8397 * sizes of commands which there may be. It's a way of
8398 * reducing the DMA done to fetch each command. Encoded into
8399 * each command's tag are 3 bits which communicate to the controller
8400 * which of the eight sizes that command fits within. The size of
8401 * each command depends on how many scatter gather entries there are.
8402 * Each SG entry requires 16 bytes. The eight registers are programmed
8403 * with the number of 16-byte blocks a command of that size requires.
8404 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 8405 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 8406 * blocks. Note, this only extends to the SG entries contained
8407 * within the command block, and does not extend to chained blocks
8408 * of SG elements. bft[] contains the eight values we write to
8409 * the registers. They are not evenly distributed, but have more
8410 * sizes for small commands, and fewer sizes for larger commands.
8411 */
d66ae08b 8412 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 8413#define MIN_IOACCEL2_BFT_ENTRY 5
8414#define HPSA_IOACCEL2_HEADER_SZ 4
8415 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
8416 13, 14, 15, 16, 17, 18, 19,
8417 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
8418 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
8419 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
8420 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
8421 16 * MIN_IOACCEL2_BFT_ENTRY);
8422 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 8423 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 8424 /* 5 = 1 s/g entry or 4k
8425 * 6 = 2 s/g entry or 8k
8426 * 8 = 4 s/g entry or 16k
8427 * 10 = 6 s/g entry or 24k
8428 */
303932fd 8429
b3a52e79
SC		 8430 /* If the controller supports either ioaccel method then
8431 * we can also use the RAID stack submit path that does not
8432 * perform the superfluous readl() after each command submission.
8433 */
8434 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
8435 access = SA5_performant_access_no_read;
8436
303932fd 8437 /* Controller spec: zero out this buffer. */
072b0518
SC		 8438 for (i = 0; i < h->nreply_queues; i++)
8439 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 8440
d66ae08b
SC		 8441 bft[7] = SG_ENTRIES_IN_CMD + 4;
8442 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 8443 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 8444 for (i = 0; i < 8; i++)
8445 writel(bft[i], &h->transtable->BlockFetch[i]);
8446
8447 /* size of controller ring buffer */
8448 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 8449 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 8450 writel(0, &h->transtable->RepQCtrAddrLow32);
8451 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 8452
8453 for (i = 0; i < h->nreply_queues; i++) {
8454 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 8455 writel(h->reply_queue[i].busaddr,
254f796b
MG		 8456 &h->transtable->RepQAddr[i].lower);
8457 }
8458
b9af4937 8459 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 8460 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
8461 /*
8462 * enable outbound interrupt coalescing in accelerator mode;
8463 */
8464 if (trans_support & CFGTBL_Trans_io_accel1) {
8465 access = SA5_ioaccel_mode1_access;
8466 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8467 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 8468 } else {
8469 if (trans_support & CFGTBL_Trans_io_accel2) {
8470 access = SA5_ioaccel_mode2_access;
8471 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8472 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
8473 }
e1f7de0c 8474 }
303932fd 8475 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8476 if (hpsa_wait_for_mode_change_ack(h)) {
8477 dev_err(&h->pdev->dev,
8478 "performant mode problem - doorbell timeout\n");
8479 return -ENODEV;
8480 }
303932fd
DB		 8481 register_value = readl(&(h->cfgtable->TransportActive));
8482 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 8483 dev_err(&h->pdev->dev,
8484 "performant mode problem - transport not active\n");
c706a795 8485 return -ENODEV;
303932fd 8486 }
960a30e7 8487 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 8488 h->access = access;
8489 h->transMethod = transMethod;
8490
b9af4937
SC		 8491 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
8492 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 8493 return 0;
e1f7de0c 8494
b9af4937
SC		 8495 if (trans_support & CFGTBL_Trans_io_accel1) {
8496 /* Set up I/O accelerator mode */
8497 for (i = 0; i < h->nreply_queues; i++) {
8498 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
8499 h->reply_queue[i].current_entry =
8500 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
8501 }
8502 bft[7] = h->ioaccel_maxsg + 8;
8503 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
8504 h->ioaccel1_blockFetchTable);
e1f7de0c 8505
b9af4937 8506 /* initialize all reply queue entries to unused */
072b0518
SC		 8507 for (i = 0; i < h->nreply_queues; i++)
8508 memset(h->reply_queue[i].head,
8509 (u8) IOACCEL_MODE1_REPLY_UNUSED,
8510 h->reply_queue_size);
e1f7de0c 8511
b9af4937
SC		 8512 /* set all the constant fields in the accelerator command
8513 * frames once at init time to save CPU cycles later.
8514 */
8515 for (i = 0; i < h->nr_cmds; i++) {
8516 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
8517
8518 cp->function = IOACCEL1_FUNCTION_SCSIIO;
8519 cp->err_info = (u32) (h->errinfo_pool_dhandle +
8520 (i * sizeof(struct ErrorInfo)));
8521 cp->err_info_len = sizeof(struct ErrorInfo);
8522 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 8523 cp->host_context_flags =
8524 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 8525 cp->timeout_sec = 0;
8526 cp->ReplyQueue = 0;
50a0decf 8527 cp->tag =
f2405db8 8528 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 8529 cp->host_addr =
8530 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 8531 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 8532 }
8533 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8534 u64 cfg_offset, cfg_base_addr_index;
8535 u32 bft2_offset, cfg_base_addr;
8536 int rc;
8537
8538 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
8539 &cfg_base_addr_index, &cfg_offset);
8540 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
8541 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
8542 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
8543 4, h->ioaccel2_blockFetchTable);
8544 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
8545 BUILD_BUG_ON(offsetof(struct CfgTable,
8546 io_accel_request_size_offset) != 0xb8);
8547 h->ioaccel2_bft2_regs =
8548 remap_pci_mem(pci_resource_start(h->pdev,
8549 cfg_base_addr_index) +
8550 cfg_offset + bft2_offset,
8551 ARRAY_SIZE(bft2) *
8552 sizeof(*h->ioaccel2_bft2_regs));
8553 for (i = 0; i < ARRAY_SIZE(bft2); i++)
8554 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 8555 }
b9af4937 8556 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8557 if (hpsa_wait_for_mode_change_ack(h)) {
8558 dev_err(&h->pdev->dev,
8559 "performant mode problem - enabling ioaccel mode\n");
8560 return -ENODEV;
8561 }
8562 return 0;
e1f7de0c
MG		 8563}
8564
1fb7c98a
RE		 8565/* Free ioaccel1 mode command blocks and block fetch table */
8566static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
8567{
105a3dbc 8568 if (h->ioaccel_cmd_pool) {
1fb7c98a
RE		 8569 pci_free_consistent(h->pdev,
8570 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8571 h->ioaccel_cmd_pool,
8572 h->ioaccel_cmd_pool_dhandle);
105a3dbc
RE		 8573 h->ioaccel_cmd_pool = NULL;
8574 h->ioaccel_cmd_pool_dhandle = 0;
8575 }
1fb7c98a 8576 kfree(h->ioaccel1_blockFetchTable);
105a3dbc 8577 h->ioaccel1_blockFetchTable = NULL;
1fb7c98a
RE		 8578}
8579
d37ffbe4
RE		 8580/* Allocate ioaccel1 mode command blocks and block fetch table */
8581static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 8582{
283b4a9b
SC		 8583 h->ioaccel_maxsg =
8584 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8585 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
8586 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
8587
e1f7de0c
MG		 8588 /* Command structures must be aligned on a 128-byte boundary
8589 * because the 7 lower bits of the address are used by the
8590 * hardware.
8591 */
e1f7de0c
MG		 8592 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
8593 IOACCEL1_COMMANDLIST_ALIGNMENT);
8594 h->ioaccel_cmd_pool =
8595 pci_alloc_consistent(h->pdev,
8596 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8597 &(h->ioaccel_cmd_pool_dhandle));
8598
8599 h->ioaccel1_blockFetchTable =
283b4a9b 8600 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 8601 sizeof(u32)), GFP_KERNEL);
8602
8603 if ((h->ioaccel_cmd_pool == NULL) ||
8604 (h->ioaccel1_blockFetchTable == NULL))
8605 goto clean_up;
8606
8607 memset(h->ioaccel_cmd_pool, 0,
8608 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
8609 return 0;
8610
8611clean_up:
1fb7c98a 8612 hpsa_free_ioaccel1_cmd_and_bft(h);
2dd02d74 8613 return -ENOMEM;
6c311b57
SC		 8614}
8615
1fb7c98a
RE		 8616/* Free ioaccel2 mode command blocks and block fetch table */
8617static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
8618{
d9a729f3
WS		 8619 hpsa_free_ioaccel2_sg_chain_blocks(h);
8620
105a3dbc 8621 if (h->ioaccel2_cmd_pool) {
1fb7c98a
RE		 8622 pci_free_consistent(h->pdev,
8623 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8624 h->ioaccel2_cmd_pool,
8625 h->ioaccel2_cmd_pool_dhandle);
105a3dbc
RE		 8626 h->ioaccel2_cmd_pool = NULL;
8627 h->ioaccel2_cmd_pool_dhandle = 0;
8628 }
1fb7c98a 8629 kfree(h->ioaccel2_blockFetchTable);
105a3dbc 8630 h->ioaccel2_blockFetchTable = NULL;
1fb7c98a
RE		 8631}
8632
d37ffbe4
RE		 8633/* Allocate ioaccel2 mode command blocks and block fetch table */
8634static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 8635{
d9a729f3
WS		 8636 int rc;
8637
aca9012a
SC		 8638 /* Allocate ioaccel2 mode command blocks and block fetch table */
8639
8640 h->ioaccel_maxsg =
8641 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8642 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
8643 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
8644
aca9012a
SC		 8645 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
8646 IOACCEL2_COMMANDLIST_ALIGNMENT);
8647 h->ioaccel2_cmd_pool =
8648 pci_alloc_consistent(h->pdev,
8649 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8650 &(h->ioaccel2_cmd_pool_dhandle));
8651
8652 h->ioaccel2_blockFetchTable =
8653 kmalloc(((h->ioaccel_maxsg + 1) *
8654 sizeof(u32)), GFP_KERNEL);
8655
8656 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 8657 (h->ioaccel2_blockFetchTable == NULL)) {
8658 rc = -ENOMEM;
8659 goto clean_up;
8660 }
8661
8662 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
8663 if (rc)
aca9012a
SC		 8664 goto clean_up;
8665
8666 memset(h->ioaccel2_cmd_pool, 0,
8667 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
8668 return 0;
8669
8670clean_up:
1fb7c98a 8671 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 8672 return rc;
aca9012a
SC		 8673}
8674
105a3dbc
RE		 8675/* Free items allocated by hpsa_put_ctlr_into_performant_mode */
8676static void hpsa_free_performant_mode(struct ctlr_info *h)
8677{
8678 kfree(h->blockFetchTable);
8679 h->blockFetchTable = NULL;
8680 hpsa_free_reply_queues(h);
8681 hpsa_free_ioaccel1_cmd_and_bft(h);
8682 hpsa_free_ioaccel2_cmd_and_bft(h);
8683}
8684
8685/* return -ENODEV on error, 0 on success (or no action)
8686 * allocates numerous items that must be freed later
8687 */
8688static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 8689{
8690 u32 trans_support;
e1f7de0c
MG		 8691 unsigned long transMethod = CFGTBL_Trans_Performant |
8692 CFGTBL_Trans_use_short_tags;
105a3dbc 8693 int i, rc;
6c311b57 8694
02ec19c8 8695 if (hpsa_simple_mode)
105a3dbc 8696 return 0;
02ec19c8 8697
67c99a72 8698 trans_support = readl(&(h->cfgtable->TransportSupport));
8699 if (!(trans_support & PERFORMANT_MODE))
105a3dbc 8700 return 0;
67c99a72 8701
e1f7de0c
MG		 8702 /* Check for I/O accelerator mode support */
8703 if (trans_support & CFGTBL_Trans_io_accel1) {
8704 transMethod |= CFGTBL_Trans_io_accel1 |
8705 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8706 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
8707 if (rc)
8708 return rc;
8709 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8710 transMethod |= CFGTBL_Trans_io_accel2 |
aca9012a 8711 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8712 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
8713 if (rc)
8714 return rc;
e1f7de0c
MG		 8715 }
8716
eee0f03a 8717 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 8718 hpsa_get_max_perf_mode_cmds(h);
6c311b57 8719 /* Performant mode ring buffer and supporting data structures */
072b0518 8720 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 8721
254f796b 8722 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 8723 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
8724 h->reply_queue_size,
8725 &(h->reply_queue[i].busaddr));
105a3dbc
RE		 8726 if (!h->reply_queue[i].head) {
8727 rc = -ENOMEM;
8728 goto clean1; /* rq, ioaccel */
8729 }
254f796b
MG		 8730 h->reply_queue[i].size = h->max_commands;
8731 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
8732 h->reply_queue[i].current_entry = 0;
8733 }
8734
6c311b57 8735 /* Need a block fetch table for performant mode */
d66ae08b 8736 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 8737 sizeof(u32)), GFP_KERNEL);
105a3dbc
RE		 8738 if (!h->blockFetchTable) {
8739 rc = -ENOMEM;
8740 goto clean1; /* rq, ioaccel */
8741 }
6c311b57 8742
105a3dbc
RE		 8743 rc = hpsa_enter_performant_mode(h, trans_support);
8744 if (rc)
8745 goto clean2; /* bft, rq, ioaccel */
8746 return 0;
303932fd 8747
105a3dbc 8748clean2: /* bft, rq, ioaccel */
303932fd 8749 kfree(h->blockFetchTable);
105a3dbc
RE		 8750 h->blockFetchTable = NULL;
8751clean1: /* rq, ioaccel */
8752 hpsa_free_reply_queues(h);
8753 hpsa_free_ioaccel1_cmd_and_bft(h);
8754 hpsa_free_ioaccel2_cmd_and_bft(h);
8755 return rc;
303932fd
DB		 8756}
8757
23100dd9 8758static int is_accelerated_cmd(struct CommandList *c)
76438d08 8759{
23100dd9
SC		 8760 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
8761}
8762
8763static void hpsa_drain_accel_commands(struct ctlr_info *h)
8764{
8765 struct CommandList *c = NULL;
f2405db8 8766 int i, accel_cmds_out;
281a7fd0 8767 int refcount;
76438d08 8768
f2405db8 8769 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 8770 accel_cmds_out = 0;
f2405db8 8771 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8772 c = h->cmd_pool + i;
281a7fd0
WS		 8773 refcount = atomic_inc_return(&c->refcount);
8774 if (refcount > 1) /* Command is allocated */
8775 accel_cmds_out += is_accelerated_cmd(c);
8776 cmd_free(h, c);
f2405db8 8777 }
23100dd9 8778 if (accel_cmds_out <= 0)
281a7fd0 8779 break;
76438d08
SC		 8780 msleep(100);
8781 } while (1);
8782}
8783
edd16368
SC		 8784/*
8785 * This is it. Register the PCI driver information for the cards we control
8786 * the OS will call our registered routines when it finds one of our cards.
8787 */
8788static int __init hpsa_init(void)
8789{
31468401 8790 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 8791}
8792
8793static void __exit hpsa_cleanup(void)
8794{
8795 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 8796}
8797
e1f7de0c
MG		 8798static void __attribute__((unused)) verify_offsets(void)
8799{
dd0e19f3
ST		 8800#define VERIFY_OFFSET(member, offset) \
8801 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
8802
8803 VERIFY_OFFSET(structure_size, 0);
8804 VERIFY_OFFSET(volume_blk_size, 4);
8805 VERIFY_OFFSET(volume_blk_cnt, 8);
8806 VERIFY_OFFSET(phys_blk_shift, 16);
8807 VERIFY_OFFSET(parity_rotation_shift, 17);
8808 VERIFY_OFFSET(strip_size, 18);
8809 VERIFY_OFFSET(disk_starting_blk, 20);
8810 VERIFY_OFFSET(disk_blk_cnt, 28);
8811 VERIFY_OFFSET(data_disks_per_row, 36);
8812 VERIFY_OFFSET(metadata_disks_per_row, 38);
8813 VERIFY_OFFSET(row_cnt, 40);
8814 VERIFY_OFFSET(layout_map_count, 42);
8815 VERIFY_OFFSET(flags, 44);
8816 VERIFY_OFFSET(dekindex, 46);
8817 /* VERIFY_OFFSET(reserved, 48 */
8818 VERIFY_OFFSET(data, 64);
8819
8820#undef VERIFY_OFFSET
8821
b66cc250
MM		 8822#define VERIFY_OFFSET(member, offset) \
8823 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
8824
8825 VERIFY_OFFSET(IU_type, 0);
8826 VERIFY_OFFSET(direction, 1);
8827 VERIFY_OFFSET(reply_queue, 2);
8828 /* VERIFY_OFFSET(reserved1, 3); */
8829 VERIFY_OFFSET(scsi_nexus, 4);
8830 VERIFY_OFFSET(Tag, 8);
8831 VERIFY_OFFSET(cdb, 16);
8832 VERIFY_OFFSET(cciss_lun, 32);
8833 VERIFY_OFFSET(data_len, 40);
8834 VERIFY_OFFSET(cmd_priority_task_attr, 44);
8835 VERIFY_OFFSET(sg_count, 45);
8836 /* VERIFY_OFFSET(reserved3 */
8837 VERIFY_OFFSET(err_ptr, 48);
8838 VERIFY_OFFSET(err_len, 56);
8839 /* VERIFY_OFFSET(reserved4 */
8840 VERIFY_OFFSET(sg, 64);
8841
8842#undef VERIFY_OFFSET
8843
e1f7de0c
MG		 8844#define VERIFY_OFFSET(member, offset) \
8845 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
8846
8847 VERIFY_OFFSET(dev_handle, 0x00);
8848 VERIFY_OFFSET(reserved1, 0x02);
8849 VERIFY_OFFSET(function, 0x03);
8850 VERIFY_OFFSET(reserved2, 0x04);
8851 VERIFY_OFFSET(err_info, 0x0C);
8852 VERIFY_OFFSET(reserved3, 0x10);
8853 VERIFY_OFFSET(err_info_len, 0x12);
8854 VERIFY_OFFSET(reserved4, 0x13);
8855 VERIFY_OFFSET(sgl_offset, 0x14);
8856 VERIFY_OFFSET(reserved5, 0x15);
8857 VERIFY_OFFSET(transfer_len, 0x1C);
8858 VERIFY_OFFSET(reserved6, 0x20);
8859 VERIFY_OFFSET(io_flags, 0x24);
8860 VERIFY_OFFSET(reserved7, 0x26);
8861 VERIFY_OFFSET(LUN, 0x34);
8862 VERIFY_OFFSET(control, 0x3C);
8863 VERIFY_OFFSET(CDB, 0x40);
8864 VERIFY_OFFSET(reserved8, 0x50);
8865 VERIFY_OFFSET(host_context_flags, 0x60);
8866 VERIFY_OFFSET(timeout_sec, 0x62);
8867 VERIFY_OFFSET(ReplyQueue, 0x64);
8868 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 8869 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 8870 VERIFY_OFFSET(host_addr, 0x70);
8871 VERIFY_OFFSET(CISS_LUN, 0x78);
8872 VERIFY_OFFSET(SG, 0x78 + 8);
8873#undef VERIFY_OFFSET
8874}
8875
edd16368
SC		 8876module_init(hpsa_init);
8877module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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