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hpsa: remove bad unlikely annotation from device list updating code
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
a0c12413 50#include <linux/jiffies.h>
094963da 51#include <linux/percpu.h>
283b4a9b 52#include <asm/div64.h>
edd16368
SC		 53#include "hpsa_cmd.h"
54#include "hpsa.h"
55
56/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
9a993302 57#define HPSA_DRIVER_VERSION "3.4.4-1"
edd16368 58#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 59#define HPSA "hpsa"
edd16368
SC		 60
61/* How long to wait (in milliseconds) for board to go into simple mode */
62#define MAX_CONFIG_WAIT 30000
63#define MAX_IOCTL_CONFIG_WAIT 1000
64
65/*define how many times we will try a command because of bus resets */
66#define MAX_CMD_RETRIES 3
67
68/* Embedded module documentation macros - see modules.h */
69MODULE_AUTHOR("Hewlett-Packard Company");
70MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
71 HPSA_DRIVER_VERSION);
72MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
73MODULE_VERSION(HPSA_DRIVER_VERSION);
74MODULE_LICENSE("GPL");
75
76static int hpsa_allow_any;
77module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(hpsa_allow_any,
79 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 80static int hpsa_simple_mode;
81module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_simple_mode,
83 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 84
85/* define the PCI info for the cards we can control */
86static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
8e616a5e
SC		 128 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
129 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
130 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
131 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
132 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 133 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 134 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 135 {0,}
136};
137
138MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
139
140/* board_id = Subsystem Device ID & Vendor ID
141 * product = Marketing Name for the board
142 * access = Address of the struct of function pointers
143 */
144static struct board_type products[] = {
edd16368
SC		 145 {0x3241103C, "Smart Array P212", &SA5_access},
146 {0x3243103C, "Smart Array P410", &SA5_access},
147 {0x3245103C, "Smart Array P410i", &SA5_access},
148 {0x3247103C, "Smart Array P411", &SA5_access},
149 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 150 {0x324A103C, "Smart Array P712m", &SA5_access},
151 {0x324B103C, "Smart Array P711m", &SA5_access},
fe0c9610
MM		 152 {0x3350103C, "Smart Array P222", &SA5_access},
153 {0x3351103C, "Smart Array P420", &SA5_access},
154 {0x3352103C, "Smart Array P421", &SA5_access},
155 {0x3353103C, "Smart Array P822", &SA5_access},
156 {0x3354103C, "Smart Array P420i", &SA5_access},
157 {0x3355103C, "Smart Array P220i", &SA5_access},
158 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 159 {0x1921103C, "Smart Array P830i", &SA5_access},
160 {0x1922103C, "Smart Array P430", &SA5_access},
161 {0x1923103C, "Smart Array P431", &SA5_access},
162 {0x1924103C, "Smart Array P830", &SA5_access},
163 {0x1926103C, "Smart Array P731m", &SA5_access},
164 {0x1928103C, "Smart Array P230i", &SA5_access},
165 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 166 {0x21BD103C, "Smart Array", &SA5_access},
167 {0x21BE103C, "Smart Array", &SA5_access},
168 {0x21BF103C, "Smart Array", &SA5_access},
169 {0x21C0103C, "Smart Array", &SA5_access},
170 {0x21C1103C, "Smart Array", &SA5_access},
171 {0x21C2103C, "Smart Array", &SA5_access},
172 {0x21C3103C, "Smart Array", &SA5_access},
173 {0x21C4103C, "Smart Array", &SA5_access},
174 {0x21C5103C, "Smart Array", &SA5_access},
3b7a45e5 175 {0x21C6103C, "Smart Array", &SA5_access},
97b9f53d
MM		 176 {0x21C7103C, "Smart Array", &SA5_access},
177 {0x21C8103C, "Smart Array", &SA5_access},
178 {0x21C9103C, "Smart Array", &SA5_access},
3b7a45e5
JH		 179 {0x21CA103C, "Smart Array", &SA5_access},
180 {0x21CB103C, "Smart Array", &SA5_access},
181 {0x21CC103C, "Smart Array", &SA5_access},
182 {0x21CD103C, "Smart Array", &SA5_access},
183 {0x21CE103C, "Smart Array", &SA5_access},
8e616a5e
SC		 184 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
185 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
186 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
187 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
188 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 189 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
190};
191
192static int number_of_controllers;
193
10f66018
SC		 194static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
195static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
edd16368 196static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
0b57075d
SC		 197static void lock_and_start_io(struct ctlr_info *h);
198static void start_io(struct ctlr_info *h, unsigned long *flags);
edd16368
SC		 199
200#ifdef CONFIG_COMPAT
201static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
202#endif
203
204static void cmd_free(struct ctlr_info *h, struct CommandList *c);
205static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
206static struct CommandList *cmd_alloc(struct ctlr_info *h);
207static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
a2dac136 208static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 209 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 210 int cmd_type);
b7bb24eb 211#define VPD_PAGE (1 << 8)
edd16368 212
f281233d 213static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 214static void hpsa_scan_start(struct Scsi_Host *);
215static int hpsa_scan_finished(struct Scsi_Host *sh,
216 unsigned long elapsed_time);
667e23d4
SC		 217static int hpsa_change_queue_depth(struct scsi_device *sdev,
218 int qdepth, int reason);
edd16368
SC		 219
220static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 221static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 222static int hpsa_slave_alloc(struct scsi_device *sdev);
223static void hpsa_slave_destroy(struct scsi_device *sdev);
224
edd16368 225static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 226static int check_for_unit_attention(struct ctlr_info *h,
227 struct CommandList *c);
228static void check_ioctl_unit_attention(struct ctlr_info *h,
229 struct CommandList *c);
303932fd
DB		 230/* performant mode helper functions */
231static void calc_bucket_map(int *bucket, int num_buckets,
e1f7de0c 232 int nsgs, int min_blocks, int *bucket_map);
6f039790 233static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 234static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 235static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
236 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
237 u64 *cfg_offset);
238static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
239 unsigned long *memory_bar);
240static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
241static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
242 int wait_for_ready);
75167d2c 243static inline void finish_cmd(struct CommandList *c);
283b4a9b 244static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 245#define BOARD_NOT_READY 0
246#define BOARD_READY 1
23100dd9 247static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 248static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 249static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
250 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
251 u8 *scsi3addr);
edd16368 252
edd16368
SC		 253static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
254{
255 unsigned long *priv = shost_priv(sdev->host);
256 return (struct ctlr_info *) *priv;
257}
258
a23513e8
SC		 259static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
260{
261 unsigned long *priv = shost_priv(sh);
262 return (struct ctlr_info *) *priv;
263}
264
edd16368
SC		 265static int check_for_unit_attention(struct ctlr_info *h,
266 struct CommandList *c)
267{
268 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
269 return 0;
270
271 switch (c->err_info->SenseInfo[12]) {
272 case STATE_CHANGED:
f79cfec6 273 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 274 "detected, command retried\n", h->ctlr);
275 break;
276 case LUN_FAILED:
f79cfec6 277 dev_warn(&h->pdev->dev, HPSA "%d: LUN failure "
edd16368
SC		 278 "detected, action required\n", h->ctlr);
279 break;
280 case REPORT_LUNS_CHANGED:
f79cfec6 281 dev_warn(&h->pdev->dev, HPSA "%d: report LUN data "
31468401 282 "changed, action required\n", h->ctlr);
edd16368 283 /*
4f4eb9f1
ST		 284 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
285 * target (array) devices.
edd16368
SC		 286 */
287 break;
288 case POWER_OR_RESET:
f79cfec6 289 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 290 "or device reset detected\n", h->ctlr);
291 break;
292 case UNIT_ATTENTION_CLEARED:
f79cfec6 293 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 294 "cleared by another initiator\n", h->ctlr);
295 break;
296 default:
f79cfec6 297 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 298 "unit attention detected\n", h->ctlr);
299 break;
300 }
301 return 1;
302}
303
852af20a
MB		 304static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
305{
306 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
307 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
308 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
309 return 0;
310 dev_warn(&h->pdev->dev, HPSA "device busy");
311 return 1;
312}
313
da0697bd
ST		 314static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
315 struct device_attribute *attr,
316 const char *buf, size_t count)
317{
318 int status, len;
319 struct ctlr_info *h;
320 struct Scsi_Host *shost = class_to_shost(dev);
321 char tmpbuf[10];
322
323 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
324 return -EACCES;
325 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
326 strncpy(tmpbuf, buf, len);
327 tmpbuf[len] = '\0';
328 if (sscanf(tmpbuf, "%d", &status) != 1)
329 return -EINVAL;
330 h = shost_to_hba(shost);
331 h->acciopath_status = !!status;
332 dev_warn(&h->pdev->dev,
333 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
334 h->acciopath_status ? "enabled" : "disabled");
335 return count;
336}
337
2ba8bfc8
SC		 338static ssize_t host_store_raid_offload_debug(struct device *dev,
339 struct device_attribute *attr,
340 const char *buf, size_t count)
341{
342 int debug_level, len;
343 struct ctlr_info *h;
344 struct Scsi_Host *shost = class_to_shost(dev);
345 char tmpbuf[10];
346
347 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
348 return -EACCES;
349 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
350 strncpy(tmpbuf, buf, len);
351 tmpbuf[len] = '\0';
352 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
353 return -EINVAL;
354 if (debug_level < 0)
355 debug_level = 0;
356 h = shost_to_hba(shost);
357 h->raid_offload_debug = debug_level;
358 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
359 h->raid_offload_debug);
360 return count;
361}
362
edd16368
SC		 363static ssize_t host_store_rescan(struct device *dev,
364 struct device_attribute *attr,
365 const char *buf, size_t count)
366{
367 struct ctlr_info *h;
368 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 369 h = shost_to_hba(shost);
31468401 370 hpsa_scan_start(h->scsi_host);
edd16368
SC		 371 return count;
372}
373
d28ce020
SC		 374static ssize_t host_show_firmware_revision(struct device *dev,
375 struct device_attribute *attr, char *buf)
376{
377 struct ctlr_info *h;
378 struct Scsi_Host *shost = class_to_shost(dev);
379 unsigned char *fwrev;
380
381 h = shost_to_hba(shost);
382 if (!h->hba_inquiry_data)
383 return 0;
384 fwrev = &h->hba_inquiry_data[32];
385 return snprintf(buf, 20, "%c%c%c%c\n",
386 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
387}
388
94a13649
SC		 389static ssize_t host_show_commands_outstanding(struct device *dev,
390 struct device_attribute *attr, char *buf)
391{
392 struct Scsi_Host *shost = class_to_shost(dev);
393 struct ctlr_info *h = shost_to_hba(shost);
394
395 return snprintf(buf, 20, "%d\n", h->commands_outstanding);
396}
397
745a7a25
SC		 398static ssize_t host_show_transport_mode(struct device *dev,
399 struct device_attribute *attr, char *buf)
400{
401 struct ctlr_info *h;
402 struct Scsi_Host *shost = class_to_shost(dev);
403
404 h = shost_to_hba(shost);
405 return snprintf(buf, 20, "%s\n",
960a30e7 406 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 407 "performant" : "simple");
408}
409
da0697bd
ST		 410static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
411 struct device_attribute *attr, char *buf)
412{
413 struct ctlr_info *h;
414 struct Scsi_Host *shost = class_to_shost(dev);
415
416 h = shost_to_hba(shost);
417 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
418 (h->acciopath_status == 1) ? "enabled" : "disabled");
419}
420
46380786 421/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 422static u32 unresettable_controller[] = {
423 0x324a103C, /* Smart Array P712m */
424 0x324b103C, /* SmartArray P711m */
425 0x3223103C, /* Smart Array P800 */
426 0x3234103C, /* Smart Array P400 */
427 0x3235103C, /* Smart Array P400i */
428 0x3211103C, /* Smart Array E200i */
429 0x3212103C, /* Smart Array E200 */
430 0x3213103C, /* Smart Array E200i */
431 0x3214103C, /* Smart Array E200i */
432 0x3215103C, /* Smart Array E200i */
433 0x3237103C, /* Smart Array E500 */
434 0x323D103C, /* Smart Array P700m */
7af0abbc 435 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 436 0x409C0E11, /* Smart Array 6400 */
437 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 438 0x40700E11, /* Smart Array 5300 */
439 0x40820E11, /* Smart Array 532 */
440 0x40830E11, /* Smart Array 5312 */
441 0x409A0E11, /* Smart Array 641 */
442 0x409B0E11, /* Smart Array 642 */
443 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 444};
445
46380786
SC		 446/* List of controllers which cannot even be soft reset */
447static u32 soft_unresettable_controller[] = {
7af0abbc 448 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 449 0x40700E11, /* Smart Array 5300 */
450 0x40820E11, /* Smart Array 532 */
451 0x40830E11, /* Smart Array 5312 */
452 0x409A0E11, /* Smart Array 641 */
453 0x409B0E11, /* Smart Array 642 */
454 0x40910E11, /* Smart Array 6i */
46380786
SC		 455 /* Exclude 640x boards. These are two pci devices in one slot
456 * which share a battery backed cache module. One controls the
457 * cache, the other accesses the cache through the one that controls
458 * it. If we reset the one controlling the cache, the other will
459 * likely not be happy. Just forbid resetting this conjoined mess.
460 * The 640x isn't really supported by hpsa anyway.
461 */
462 0x409C0E11, /* Smart Array 6400 */
463 0x409D0E11, /* Smart Array 6400 EM */
464};
465
466static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 467{
468 int i;
469
470 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 471 if (unresettable_controller[i] == board_id)
472 return 0;
473 return 1;
474}
475
476static int ctlr_is_soft_resettable(u32 board_id)
477{
478 int i;
479
480 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
481 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 482 return 0;
483 return 1;
484}
485
46380786
SC		 486static int ctlr_is_resettable(u32 board_id)
487{
488 return ctlr_is_hard_resettable(board_id) ||
489 ctlr_is_soft_resettable(board_id);
490}
491
941b1cda
SC		 492static ssize_t host_show_resettable(struct device *dev,
493 struct device_attribute *attr, char *buf)
494{
495 struct ctlr_info *h;
496 struct Scsi_Host *shost = class_to_shost(dev);
497
498 h = shost_to_hba(shost);
46380786 499 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 500}
501
edd16368
SC		 502static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
503{
504 return (scsi3addr[3] & 0xC0) == 0x40;
505}
506
507static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
d82357ea 508 "1(ADM)", "UNKNOWN"
edd16368 509};
6b80b18f
ST		 510#define HPSA_RAID_0 0
511#define HPSA_RAID_4 1
512#define HPSA_RAID_1 2 /* also used for RAID 10 */
513#define HPSA_RAID_5 3 /* also used for RAID 50 */
514#define HPSA_RAID_51 4
515#define HPSA_RAID_6 5 /* also used for RAID 60 */
516#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 517#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
518
519static ssize_t raid_level_show(struct device *dev,
520 struct device_attribute *attr, char *buf)
521{
522 ssize_t l = 0;
82a72c0a 523 unsigned char rlevel;
edd16368
SC		 524 struct ctlr_info *h;
525 struct scsi_device *sdev;
526 struct hpsa_scsi_dev_t *hdev;
527 unsigned long flags;
528
529 sdev = to_scsi_device(dev);
530 h = sdev_to_hba(sdev);
531 spin_lock_irqsave(&h->lock, flags);
532 hdev = sdev->hostdata;
533 if (!hdev) {
534 spin_unlock_irqrestore(&h->lock, flags);
535 return -ENODEV;
536 }
537
538 /* Is this even a logical drive? */
539 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
540 spin_unlock_irqrestore(&h->lock, flags);
541 l = snprintf(buf, PAGE_SIZE, "N/A\n");
542 return l;
543 }
544
545 rlevel = hdev->raid_level;
546 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 547 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 548 rlevel = RAID_UNKNOWN;
549 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
550 return l;
551}
552
553static ssize_t lunid_show(struct device *dev,
554 struct device_attribute *attr, char *buf)
555{
556 struct ctlr_info *h;
557 struct scsi_device *sdev;
558 struct hpsa_scsi_dev_t *hdev;
559 unsigned long flags;
560 unsigned char lunid[8];
561
562 sdev = to_scsi_device(dev);
563 h = sdev_to_hba(sdev);
564 spin_lock_irqsave(&h->lock, flags);
565 hdev = sdev->hostdata;
566 if (!hdev) {
567 spin_unlock_irqrestore(&h->lock, flags);
568 return -ENODEV;
569 }
570 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
571 spin_unlock_irqrestore(&h->lock, flags);
572 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
573 lunid[0], lunid[1], lunid[2], lunid[3],
574 lunid[4], lunid[5], lunid[6], lunid[7]);
575}
576
577static ssize_t unique_id_show(struct device *dev,
578 struct device_attribute *attr, char *buf)
579{
580 struct ctlr_info *h;
581 struct scsi_device *sdev;
582 struct hpsa_scsi_dev_t *hdev;
583 unsigned long flags;
584 unsigned char sn[16];
585
586 sdev = to_scsi_device(dev);
587 h = sdev_to_hba(sdev);
588 spin_lock_irqsave(&h->lock, flags);
589 hdev = sdev->hostdata;
590 if (!hdev) {
591 spin_unlock_irqrestore(&h->lock, flags);
592 return -ENODEV;
593 }
594 memcpy(sn, hdev->device_id, sizeof(sn));
595 spin_unlock_irqrestore(&h->lock, flags);
596 return snprintf(buf, 16 * 2 + 2,
597 "%02X%02X%02X%02X%02X%02X%02X%02X"
598 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
599 sn[0], sn[1], sn[2], sn[3],
600 sn[4], sn[5], sn[6], sn[7],
601 sn[8], sn[9], sn[10], sn[11],
602 sn[12], sn[13], sn[14], sn[15]);
603}
604
c1988684
ST		 605static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
606 struct device_attribute *attr, char *buf)
607{
608 struct ctlr_info *h;
609 struct scsi_device *sdev;
610 struct hpsa_scsi_dev_t *hdev;
611 unsigned long flags;
612 int offload_enabled;
613
614 sdev = to_scsi_device(dev);
615 h = sdev_to_hba(sdev);
616 spin_lock_irqsave(&h->lock, flags);
617 hdev = sdev->hostdata;
618 if (!hdev) {
619 spin_unlock_irqrestore(&h->lock, flags);
620 return -ENODEV;
621 }
622 offload_enabled = hdev->offload_enabled;
623 spin_unlock_irqrestore(&h->lock, flags);
624 return snprintf(buf, 20, "%d\n", offload_enabled);
625}
626
3f5eac3a
SC		 627static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
628static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
629static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
630static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 631static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
632 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 633static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
634 host_show_hp_ssd_smart_path_status,
635 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 636static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
637 host_store_raid_offload_debug);
3f5eac3a
SC		 638static DEVICE_ATTR(firmware_revision, S_IRUGO,
639 host_show_firmware_revision, NULL);
640static DEVICE_ATTR(commands_outstanding, S_IRUGO,
641 host_show_commands_outstanding, NULL);
642static DEVICE_ATTR(transport_mode, S_IRUGO,
643 host_show_transport_mode, NULL);
941b1cda
SC		 644static DEVICE_ATTR(resettable, S_IRUGO,
645 host_show_resettable, NULL);
3f5eac3a
SC		 646
647static struct device_attribute *hpsa_sdev_attrs[] = {
648 &dev_attr_raid_level,
649 &dev_attr_lunid,
650 &dev_attr_unique_id,
c1988684 651 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 652 NULL,
653};
654
655static struct device_attribute *hpsa_shost_attrs[] = {
656 &dev_attr_rescan,
657 &dev_attr_firmware_revision,
658 &dev_attr_commands_outstanding,
659 &dev_attr_transport_mode,
941b1cda 660 &dev_attr_resettable,
da0697bd 661 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 662 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 663 NULL,
664};
665
666static struct scsi_host_template hpsa_driver_template = {
667 .module = THIS_MODULE,
f79cfec6
SC		 668 .name = HPSA,
669 .proc_name = HPSA,
3f5eac3a
SC		 670 .queuecommand = hpsa_scsi_queue_command,
671 .scan_start = hpsa_scan_start,
672 .scan_finished = hpsa_scan_finished,
673 .change_queue_depth = hpsa_change_queue_depth,
674 .this_id = -1,
675 .use_clustering = ENABLE_CLUSTERING,
75167d2c 676 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 677 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
678 .ioctl = hpsa_ioctl,
679 .slave_alloc = hpsa_slave_alloc,
680 .slave_destroy = hpsa_slave_destroy,
681#ifdef CONFIG_COMPAT
682 .compat_ioctl = hpsa_compat_ioctl,
683#endif
684 .sdev_attrs = hpsa_sdev_attrs,
685 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 686 .max_sectors = 8192,
54b2b50c 687 .no_write_same = 1,
3f5eac3a
SC		 688};
689
690
691/* Enqueuing and dequeuing functions for cmdlists. */
692static inline void addQ(struct list_head *list, struct CommandList *c)
693{
694 list_add_tail(&c->list, list);
695}
696
254f796b 697static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 698{
699 u32 a;
072b0518 700 struct reply_queue_buffer *rq = &h->reply_queue[q];
e16a33ad 701 unsigned long flags;
3f5eac3a 702
e1f7de0c
MG		 703 if (h->transMethod & CFGTBL_Trans_io_accel1)
704 return h->access.command_completed(h, q);
705
3f5eac3a 706 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 707 return h->access.command_completed(h, q);
3f5eac3a 708
254f796b
MG		 709 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
710 a = rq->head[rq->current_entry];
711 rq->current_entry++;
e16a33ad 712 spin_lock_irqsave(&h->lock, flags);
3f5eac3a 713 h->commands_outstanding--;
e16a33ad 714 spin_unlock_irqrestore(&h->lock, flags);
3f5eac3a
SC		 715 } else {
716 a = FIFO_EMPTY;
717 }
718 /* Check for wraparound */
254f796b
MG		 719 if (rq->current_entry == h->max_commands) {
720 rq->current_entry = 0;
721 rq->wraparound ^= 1;
3f5eac3a
SC		 722 }
723 return a;
724}
725
c349775e
ST		 726/*
727 * There are some special bits in the bus address of the
728 * command that we have to set for the controller to know
729 * how to process the command:
730 *
731 * Normal performant mode:
732 * bit 0: 1 means performant mode, 0 means simple mode.
733 * bits 1-3 = block fetch table entry
734 * bits 4-6 = command type (== 0)
735 *
736 * ioaccel1 mode:
737 * bit 0 = "performant mode" bit.
738 * bits 1-3 = block fetch table entry
739 * bits 4-6 = command type (== 110)
740 * (command type is needed because ioaccel1 mode
741 * commands are submitted through the same register as normal
742 * mode commands, so this is how the controller knows whether
743 * the command is normal mode or ioaccel1 mode.)
744 *
745 * ioaccel2 mode:
746 * bit 0 = "performant mode" bit.
747 * bits 1-4 = block fetch table entry (note extra bit)
748 * bits 4-6 = not needed, because ioaccel2 mode has
749 * a separate special register for submitting commands.
750 */
751
3f5eac3a
SC		 752/* set_performant_mode: Modify the tag for cciss performant
753 * set bit 0 for pull model, bits 3-1 for block fetch
754 * register number
755 */
756static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
757{
254f796b 758 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 759 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 760 if (likely(h->msix_vector > 0))
254f796b 761 c->Header.ReplyQueue =
804a5cb5 762 raw_smp_processor_id() % h->nreply_queues;
254f796b 763 }
3f5eac3a
SC		 764}
765
c349775e
ST		 766static void set_ioaccel1_performant_mode(struct ctlr_info *h,
767 struct CommandList *c)
768{
769 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
770
771 /* Tell the controller to post the reply to the queue for this
772 * processor. This seems to give the best I/O throughput.
773 */
774 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
775 /* Set the bits in the address sent down to include:
776 * - performant mode bit (bit 0)
777 * - pull count (bits 1-3)
778 * - command type (bits 4-6)
779 */
780 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
781 IOACCEL1_BUSADDR_CMDTYPE;
782}
783
784static void set_ioaccel2_performant_mode(struct ctlr_info *h,
785 struct CommandList *c)
786{
787 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
788
789 /* Tell the controller to post the reply to the queue for this
790 * processor. This seems to give the best I/O throughput.
791 */
792 cp->reply_queue = smp_processor_id() % h->nreply_queues;
793 /* Set the bits in the address sent down to include:
794 * - performant mode bit not used in ioaccel mode 2
795 * - pull count (bits 0-3)
796 * - command type isn't needed for ioaccel2
797 */
798 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
799}
800
e85c5974
SC		 801static int is_firmware_flash_cmd(u8 *cdb)
802{
803 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
804}
805
806/*
807 * During firmware flash, the heartbeat register may not update as frequently
808 * as it should. So we dial down lockup detection during firmware flash. and
809 * dial it back up when firmware flash completes.
810 */
811#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
812#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
813static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
814 struct CommandList *c)
815{
816 if (!is_firmware_flash_cmd(c->Request.CDB))
817 return;
818 atomic_inc(&h->firmware_flash_in_progress);
819 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
820}
821
822static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
823 struct CommandList *c)
824{
825 if (is_firmware_flash_cmd(c->Request.CDB) &&
826 atomic_dec_and_test(&h->firmware_flash_in_progress))
827 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
828}
829
3f5eac3a
SC		 830static void enqueue_cmd_and_start_io(struct ctlr_info *h,
831 struct CommandList *c)
832{
833 unsigned long flags;
834
c349775e
ST		 835 switch (c->cmd_type) {
836 case CMD_IOACCEL1:
837 set_ioaccel1_performant_mode(h, c);
838 break;
839 case CMD_IOACCEL2:
840 set_ioaccel2_performant_mode(h, c);
841 break;
842 default:
843 set_performant_mode(h, c);
844 }
e85c5974 845 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 846 spin_lock_irqsave(&h->lock, flags);
847 addQ(&h->reqQ, c);
848 h->Qdepth++;
0b57075d 849 start_io(h, &flags);
3f5eac3a
SC		 850 spin_unlock_irqrestore(&h->lock, flags);
851}
852
853static inline void removeQ(struct CommandList *c)
854{
855 if (WARN_ON(list_empty(&c->list)))
856 return;
857 list_del_init(&c->list);
858}
859
860static inline int is_hba_lunid(unsigned char scsi3addr[])
861{
862 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
863}
864
865static inline int is_scsi_rev_5(struct ctlr_info *h)
866{
867 if (!h->hba_inquiry_data)
868 return 0;
869 if ((h->hba_inquiry_data[2] & 0x07) == 5)
870 return 1;
871 return 0;
872}
873
edd16368
SC		 874static int hpsa_find_target_lun(struct ctlr_info *h,
875 unsigned char scsi3addr[], int bus, int *target, int *lun)
876{
877 /* finds an unused bus, target, lun for a new physical device
878 * assumes h->devlock is held
879 */
880 int i, found = 0;
cfe5badc 881 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 882
263d9401 883 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 884
885 for (i = 0; i < h->ndevices; i++) {
886 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 887 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 888 }
889
263d9401
AM		 890 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
891 if (i < HPSA_MAX_DEVICES) {
892 /* *bus = 1; */
893 *target = i;
894 *lun = 0;
895 found = 1;
edd16368
SC		 896 }
897 return !found;
898}
899
900/* Add an entry into h->dev[] array. */
901static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
902 struct hpsa_scsi_dev_t *device,
903 struct hpsa_scsi_dev_t *added[], int *nadded)
904{
905 /* assumes h->devlock is held */
906 int n = h->ndevices;
907 int i;
908 unsigned char addr1[8], addr2[8];
909 struct hpsa_scsi_dev_t *sd;
910
cfe5badc 911 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 912 dev_err(&h->pdev->dev, "too many devices, some will be "
913 "inaccessible.\n");
914 return -1;
915 }
916
917 /* physical devices do not have lun or target assigned until now. */
918 if (device->lun != -1)
919 /* Logical device, lun is already assigned. */
920 goto lun_assigned;
921
922 /* If this device a non-zero lun of a multi-lun device
923 * byte 4 of the 8-byte LUN addr will contain the logical
924 * unit no, zero otherise.
925 */
926 if (device->scsi3addr[4] == 0) {
927 /* This is not a non-zero lun of a multi-lun device */
928 if (hpsa_find_target_lun(h, device->scsi3addr,
929 device->bus, &device->target, &device->lun) != 0)
930 return -1;
931 goto lun_assigned;
932 }
933
934 /* This is a non-zero lun of a multi-lun device.
935 * Search through our list and find the device which
936 * has the same 8 byte LUN address, excepting byte 4.
937 * Assign the same bus and target for this new LUN.
938 * Use the logical unit number from the firmware.
939 */
940 memcpy(addr1, device->scsi3addr, 8);
941 addr1[4] = 0;
942 for (i = 0; i < n; i++) {
943 sd = h->dev[i];
944 memcpy(addr2, sd->scsi3addr, 8);
945 addr2[4] = 0;
946 /* differ only in byte 4? */
947 if (memcmp(addr1, addr2, 8) == 0) {
948 device->bus = sd->bus;
949 device->target = sd->target;
950 device->lun = device->scsi3addr[4];
951 break;
952 }
953 }
954 if (device->lun == -1) {
955 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
956 " suspect firmware bug or unsupported hardware "
957 "configuration.\n");
958 return -1;
959 }
960
961lun_assigned:
962
963 h->dev[n] = device;
964 h->ndevices++;
965 added[*nadded] = device;
966 (*nadded)++;
967
968 /* initially, (before registering with scsi layer) we don't
969 * know our hostno and we don't want to print anything first
970 * time anyway (the scsi layer's inquiries will show that info)
971 */
972 /* if (hostno != -1) */
973 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
974 scsi_device_type(device->devtype), hostno,
975 device->bus, device->target, device->lun);
976 return 0;
977}
978
bd9244f7
ST		 979/* Update an entry in h->dev[] array. */
980static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
981 int entry, struct hpsa_scsi_dev_t *new_entry)
982{
983 /* assumes h->devlock is held */
984 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
985
986 /* Raid level changed. */
987 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 988
989 /* Raid offload parameters changed. */
990 h->dev[entry]->offload_config = new_entry->offload_config;
991 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
9fb0de2d
SC		 992 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
993 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
994 h->dev[entry]->raid_map = new_entry->raid_map;
250fb125 995
bd9244f7
ST		 996 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
997 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
998 new_entry->target, new_entry->lun);
999}
1000
2a8ccf31
SC		 1001/* Replace an entry from h->dev[] array. */
1002static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
1003 int entry, struct hpsa_scsi_dev_t *new_entry,
1004 struct hpsa_scsi_dev_t *added[], int *nadded,
1005 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1006{
1007 /* assumes h->devlock is held */
cfe5badc 1008 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1009 removed[*nremoved] = h->dev[entry];
1010 (*nremoved)++;
01350d05
SC		 1011
1012 /*
1013 * New physical devices won't have target/lun assigned yet
1014 * so we need to preserve the values in the slot we are replacing.
1015 */
1016 if (new_entry->target == -1) {
1017 new_entry->target = h->dev[entry]->target;
1018 new_entry->lun = h->dev[entry]->lun;
1019 }
1020
2a8ccf31
SC		 1021 h->dev[entry] = new_entry;
1022 added[*nadded] = new_entry;
1023 (*nadded)++;
1024 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
1025 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
1026 new_entry->target, new_entry->lun);
1027}
1028
edd16368
SC		 1029/* Remove an entry from h->dev[] array. */
1030static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1031 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1032{
1033 /* assumes h->devlock is held */
1034 int i;
1035 struct hpsa_scsi_dev_t *sd;
1036
cfe5badc 1037 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1038
1039 sd = h->dev[entry];
1040 removed[*nremoved] = h->dev[entry];
1041 (*nremoved)++;
1042
1043 for (i = entry; i < h->ndevices-1; i++)
1044 h->dev[i] = h->dev[i+1];
1045 h->ndevices--;
1046 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
1047 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
1048 sd->lun);
1049}
1050
1051#define SCSI3ADDR_EQ(a, b) ( \
1052 (a)[7] == (b)[7] && \
1053 (a)[6] == (b)[6] && \
1054 (a)[5] == (b)[5] && \
1055 (a)[4] == (b)[4] && \
1056 (a)[3] == (b)[3] && \
1057 (a)[2] == (b)[2] && \
1058 (a)[1] == (b)[1] && \
1059 (a)[0] == (b)[0])
1060
1061static void fixup_botched_add(struct ctlr_info *h,
1062 struct hpsa_scsi_dev_t *added)
1063{
1064 /* called when scsi_add_device fails in order to re-adjust
1065 * h->dev[] to match the mid layer's view.
1066 */
1067 unsigned long flags;
1068 int i, j;
1069
1070 spin_lock_irqsave(&h->lock, flags);
1071 for (i = 0; i < h->ndevices; i++) {
1072 if (h->dev[i] == added) {
1073 for (j = i; j < h->ndevices-1; j++)
1074 h->dev[j] = h->dev[j+1];
1075 h->ndevices--;
1076 break;
1077 }
1078 }
1079 spin_unlock_irqrestore(&h->lock, flags);
1080 kfree(added);
1081}
1082
1083static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1084 struct hpsa_scsi_dev_t *dev2)
1085{
edd16368
SC		 1086 /* we compare everything except lun and target as these
1087 * are not yet assigned. Compare parts likely
1088 * to differ first
1089 */
1090 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1091 sizeof(dev1->scsi3addr)) != 0)
1092 return 0;
1093 if (memcmp(dev1->device_id, dev2->device_id,
1094 sizeof(dev1->device_id)) != 0)
1095 return 0;
1096 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1097 return 0;
1098 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1099 return 0;
edd16368
SC		 1100 if (dev1->devtype != dev2->devtype)
1101 return 0;
edd16368
SC		 1102 if (dev1->bus != dev2->bus)
1103 return 0;
1104 return 1;
1105}
1106
bd9244f7
ST		 1107static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1108 struct hpsa_scsi_dev_t *dev2)
1109{
1110 /* Device attributes that can change, but don't mean
1111 * that the device is a different device, nor that the OS
1112 * needs to be told anything about the change.
1113 */
1114 if (dev1->raid_level != dev2->raid_level)
1115 return 1;
250fb125
SC		 1116 if (dev1->offload_config != dev2->offload_config)
1117 return 1;
1118 if (dev1->offload_enabled != dev2->offload_enabled)
1119 return 1;
bd9244f7
ST		 1120 return 0;
1121}
1122
edd16368
SC		 1123/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1124 * and return needle location in *index. If scsi3addr matches, but not
1125 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1126 * location in *index.
1127 * In the case of a minor device attribute change, such as RAID level, just
1128 * return DEVICE_UPDATED, along with the updated device's location in index.
1129 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1130 */
1131static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1132 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1133 int *index)
1134{
1135 int i;
1136#define DEVICE_NOT_FOUND 0
1137#define DEVICE_CHANGED 1
1138#define DEVICE_SAME 2
bd9244f7 1139#define DEVICE_UPDATED 3
edd16368 1140 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1141 if (haystack[i] == NULL) /* previously removed. */
1142 continue;
edd16368
SC		 1143 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1144 *index = i;
bd9244f7
ST		 1145 if (device_is_the_same(needle, haystack[i])) {
1146 if (device_updated(needle, haystack[i]))
1147 return DEVICE_UPDATED;
edd16368 1148 return DEVICE_SAME;
bd9244f7 1149 } else {
9846590e
SC		 1150 /* Keep offline devices offline */
1151 if (needle->volume_offline)
1152 return DEVICE_NOT_FOUND;
edd16368 1153 return DEVICE_CHANGED;
bd9244f7 1154 }
edd16368
SC		 1155 }
1156 }
1157 *index = -1;
1158 return DEVICE_NOT_FOUND;
1159}
1160
9846590e
SC		 1161static void hpsa_monitor_offline_device(struct ctlr_info *h,
1162 unsigned char scsi3addr[])
1163{
1164 struct offline_device_entry *device;
1165 unsigned long flags;
1166
1167 /* Check to see if device is already on the list */
1168 spin_lock_irqsave(&h->offline_device_lock, flags);
1169 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1170 if (memcmp(device->scsi3addr, scsi3addr,
1171 sizeof(device->scsi3addr)) == 0) {
1172 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1173 return;
1174 }
1175 }
1176 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1177
1178 /* Device is not on the list, add it. */
1179 device = kmalloc(sizeof(*device), GFP_KERNEL);
1180 if (!device) {
1181 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1182 return;
1183 }
1184 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1185 spin_lock_irqsave(&h->offline_device_lock, flags);
1186 list_add_tail(&device->offline_list, &h->offline_device_list);
1187 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1188}
1189
1190/* Print a message explaining various offline volume states */
1191static void hpsa_show_volume_status(struct ctlr_info *h,
1192 struct hpsa_scsi_dev_t *sd)
1193{
1194 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1195 dev_info(&h->pdev->dev,
1196 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1197 h->scsi_host->host_no,
1198 sd->bus, sd->target, sd->lun);
1199 switch (sd->volume_offline) {
1200 case HPSA_LV_OK:
1201 break;
1202 case HPSA_LV_UNDERGOING_ERASE:
1203 dev_info(&h->pdev->dev,
1204 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1205 h->scsi_host->host_no,
1206 sd->bus, sd->target, sd->lun);
1207 break;
1208 case HPSA_LV_UNDERGOING_RPI:
1209 dev_info(&h->pdev->dev,
1210 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1211 h->scsi_host->host_no,
1212 sd->bus, sd->target, sd->lun);
1213 break;
1214 case HPSA_LV_PENDING_RPI:
1215 dev_info(&h->pdev->dev,
1216 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1217 h->scsi_host->host_no,
1218 sd->bus, sd->target, sd->lun);
1219 break;
1220 case HPSA_LV_ENCRYPTED_NO_KEY:
1221 dev_info(&h->pdev->dev,
1222 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1223 h->scsi_host->host_no,
1224 sd->bus, sd->target, sd->lun);
1225 break;
1226 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1227 dev_info(&h->pdev->dev,
1228 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1229 h->scsi_host->host_no,
1230 sd->bus, sd->target, sd->lun);
1231 break;
1232 case HPSA_LV_UNDERGOING_ENCRYPTION:
1233 dev_info(&h->pdev->dev,
1234 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1235 h->scsi_host->host_no,
1236 sd->bus, sd->target, sd->lun);
1237 break;
1238 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1239 dev_info(&h->pdev->dev,
1240 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1241 h->scsi_host->host_no,
1242 sd->bus, sd->target, sd->lun);
1243 break;
1244 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1245 dev_info(&h->pdev->dev,
1246 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1247 h->scsi_host->host_no,
1248 sd->bus, sd->target, sd->lun);
1249 break;
1250 case HPSA_LV_PENDING_ENCRYPTION:
1251 dev_info(&h->pdev->dev,
1252 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1253 h->scsi_host->host_no,
1254 sd->bus, sd->target, sd->lun);
1255 break;
1256 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1257 dev_info(&h->pdev->dev,
1258 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1259 h->scsi_host->host_no,
1260 sd->bus, sd->target, sd->lun);
1261 break;
1262 }
1263}
1264
4967bd3e 1265static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1266 struct hpsa_scsi_dev_t *sd[], int nsds)
1267{
1268 /* sd contains scsi3 addresses and devtypes, and inquiry
1269 * data. This function takes what's in sd to be the current
1270 * reality and updates h->dev[] to reflect that reality.
1271 */
1272 int i, entry, device_change, changes = 0;
1273 struct hpsa_scsi_dev_t *csd;
1274 unsigned long flags;
1275 struct hpsa_scsi_dev_t **added, **removed;
1276 int nadded, nremoved;
1277 struct Scsi_Host *sh = NULL;
1278
cfe5badc
ST		 1279 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1280 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1281
1282 if (!added || !removed) {
1283 dev_warn(&h->pdev->dev, "out of memory in "
1284 "adjust_hpsa_scsi_table\n");
1285 goto free_and_out;
1286 }
1287
1288 spin_lock_irqsave(&h->devlock, flags);
1289
1290 /* find any devices in h->dev[] that are not in
1291 * sd[] and remove them from h->dev[], and for any
1292 * devices which have changed, remove the old device
1293 * info and add the new device info.
bd9244f7
ST		 1294 * If minor device attributes change, just update
1295 * the existing device structure.
edd16368
SC		 1296 */
1297 i = 0;
1298 nremoved = 0;
1299 nadded = 0;
1300 while (i < h->ndevices) {
1301 csd = h->dev[i];
1302 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1303 if (device_change == DEVICE_NOT_FOUND) {
1304 changes++;
1305 hpsa_scsi_remove_entry(h, hostno, i,
1306 removed, &nremoved);
1307 continue; /* remove ^^^, hence i not incremented */
1308 } else if (device_change == DEVICE_CHANGED) {
1309 changes++;
2a8ccf31
SC		 1310 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1311 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1312 /* Set it to NULL to prevent it from being freed
1313 * at the bottom of hpsa_update_scsi_devices()
1314 */
1315 sd[entry] = NULL;
bd9244f7
ST		 1316 } else if (device_change == DEVICE_UPDATED) {
1317 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1318 }
1319 i++;
1320 }
1321
1322 /* Now, make sure every device listed in sd[] is also
1323 * listed in h->dev[], adding them if they aren't found
1324 */
1325
1326 for (i = 0; i < nsds; i++) {
1327 if (!sd[i]) /* if already added above. */
1328 continue;
9846590e
SC		 1329
1330 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1331 * as the SCSI mid-layer does not handle such devices well.
1332 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1333 * at 160Hz, and prevents the system from coming up.
1334 */
1335 if (sd[i]->volume_offline) {
1336 hpsa_show_volume_status(h, sd[i]);
1337 dev_info(&h->pdev->dev, "c%db%dt%dl%d: temporarily offline\n",
1338 h->scsi_host->host_no,
1339 sd[i]->bus, sd[i]->target, sd[i]->lun);
1340 continue;
1341 }
1342
edd16368
SC		 1343 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1344 h->ndevices, &entry);
1345 if (device_change == DEVICE_NOT_FOUND) {
1346 changes++;
1347 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1348 added, &nadded) != 0)
1349 break;
1350 sd[i] = NULL; /* prevent from being freed later. */
1351 } else if (device_change == DEVICE_CHANGED) {
1352 /* should never happen... */
1353 changes++;
1354 dev_warn(&h->pdev->dev,
1355 "device unexpectedly changed.\n");
1356 /* but if it does happen, we just ignore that device */
1357 }
1358 }
1359 spin_unlock_irqrestore(&h->devlock, flags);
1360
9846590e
SC		 1361 /* Monitor devices which are in one of several NOT READY states to be
1362 * brought online later. This must be done without holding h->devlock,
1363 * so don't touch h->dev[]
1364 */
1365 for (i = 0; i < nsds; i++) {
1366 if (!sd[i]) /* if already added above. */
1367 continue;
1368 if (sd[i]->volume_offline)
1369 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1370 }
1371
edd16368
SC		 1372 /* Don't notify scsi mid layer of any changes the first time through
1373 * (or if there are no changes) scsi_scan_host will do it later the
1374 * first time through.
1375 */
1376 if (hostno == -1 || !changes)
1377 goto free_and_out;
1378
1379 sh = h->scsi_host;
1380 /* Notify scsi mid layer of any removed devices */
1381 for (i = 0; i < nremoved; i++) {
1382 struct scsi_device *sdev =
1383 scsi_device_lookup(sh, removed[i]->bus,
1384 removed[i]->target, removed[i]->lun);
1385 if (sdev != NULL) {
1386 scsi_remove_device(sdev);
1387 scsi_device_put(sdev);
1388 } else {
1389 /* We don't expect to get here.
1390 * future cmds to this device will get selection
1391 * timeout as if the device was gone.
1392 */
1393 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1394 " for removal.", hostno, removed[i]->bus,
1395 removed[i]->target, removed[i]->lun);
1396 }
1397 kfree(removed[i]);
1398 removed[i] = NULL;
1399 }
1400
1401 /* Notify scsi mid layer of any added devices */
1402 for (i = 0; i < nadded; i++) {
1403 if (scsi_add_device(sh, added[i]->bus,
1404 added[i]->target, added[i]->lun) == 0)
1405 continue;
1406 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1407 "device not added.\n", hostno, added[i]->bus,
1408 added[i]->target, added[i]->lun);
1409 /* now we have to remove it from h->dev,
1410 * since it didn't get added to scsi mid layer
1411 */
1412 fixup_botched_add(h, added[i]);
1413 }
1414
1415free_and_out:
1416 kfree(added);
1417 kfree(removed);
edd16368
SC		 1418}
1419
1420/*
9e03aa2f 1421 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1422 * Assume's h->devlock is held.
1423 */
1424static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1425 int bus, int target, int lun)
1426{
1427 int i;
1428 struct hpsa_scsi_dev_t *sd;
1429
1430 for (i = 0; i < h->ndevices; i++) {
1431 sd = h->dev[i];
1432 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1433 return sd;
1434 }
1435 return NULL;
1436}
1437
1438/* link sdev->hostdata to our per-device structure. */
1439static int hpsa_slave_alloc(struct scsi_device *sdev)
1440{
1441 struct hpsa_scsi_dev_t *sd;
1442 unsigned long flags;
1443 struct ctlr_info *h;
1444
1445 h = sdev_to_hba(sdev);
1446 spin_lock_irqsave(&h->devlock, flags);
1447 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1448 sdev_id(sdev), sdev->lun);
1449 if (sd != NULL)
1450 sdev->hostdata = sd;
1451 spin_unlock_irqrestore(&h->devlock, flags);
1452 return 0;
1453}
1454
1455static void hpsa_slave_destroy(struct scsi_device *sdev)
1456{
bcc44255 1457 /* nothing to do. */
edd16368
SC		 1458}
1459
33a2ffce
SC		 1460static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1461{
1462 int i;
1463
1464 if (!h->cmd_sg_list)
1465 return;
1466 for (i = 0; i < h->nr_cmds; i++) {
1467 kfree(h->cmd_sg_list[i]);
1468 h->cmd_sg_list[i] = NULL;
1469 }
1470 kfree(h->cmd_sg_list);
1471 h->cmd_sg_list = NULL;
1472}
1473
1474static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1475{
1476 int i;
1477
1478 if (h->chainsize <= 0)
1479 return 0;
1480
1481 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1482 GFP_KERNEL);
1483 if (!h->cmd_sg_list)
1484 return -ENOMEM;
1485 for (i = 0; i < h->nr_cmds; i++) {
1486 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1487 h->chainsize, GFP_KERNEL);
1488 if (!h->cmd_sg_list[i])
1489 goto clean;
1490 }
1491 return 0;
1492
1493clean:
1494 hpsa_free_sg_chain_blocks(h);
1495 return -ENOMEM;
1496}
1497
e2bea6df 1498static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1499 struct CommandList *c)
1500{
1501 struct SGDescriptor *chain_sg, *chain_block;
1502 u64 temp64;
1503
1504 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1505 chain_block = h->cmd_sg_list[c->cmdindex];
1506 chain_sg->Ext = HPSA_SG_CHAIN;
1507 chain_sg->Len = sizeof(*chain_sg) *
1508 (c->Header.SGTotal - h->max_cmd_sg_entries);
1509 temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
1510 PCI_DMA_TODEVICE);
e2bea6df
SC		 1511 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1512 /* prevent subsequent unmapping */
1513 chain_sg->Addr.lower = 0;
1514 chain_sg->Addr.upper = 0;
1515 return -1;
1516 }
33a2ffce
SC		 1517 chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
1518 chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
e2bea6df 1519 return 0;
33a2ffce
SC		 1520}
1521
1522static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1523 struct CommandList *c)
1524{
1525 struct SGDescriptor *chain_sg;
1526 union u64bit temp64;
1527
1528 if (c->Header.SGTotal <= h->max_cmd_sg_entries)
1529 return;
1530
1531 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1532 temp64.val32.lower = chain_sg->Addr.lower;
1533 temp64.val32.upper = chain_sg->Addr.upper;
1534 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
1535}
1536
a09c1441
ST		 1537
1538/* Decode the various types of errors on ioaccel2 path.
1539 * Return 1 for any error that should generate a RAID path retry.
1540 * Return 0 for errors that don't require a RAID path retry.
1541 */
1542static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1543 struct CommandList *c,
1544 struct scsi_cmnd *cmd,
1545 struct io_accel2_cmd *c2)
1546{
1547 int data_len;
a09c1441 1548 int retry = 0;
c349775e
ST		 1549
1550 switch (c2->error_data.serv_response) {
1551 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1552 switch (c2->error_data.status) {
1553 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1554 break;
1555 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1556 dev_warn(&h->pdev->dev,
1557 "%s: task complete with check condition.\n",
1558 "HP SSD Smart Path");
1559 if (c2->error_data.data_present !=
1560 IOACCEL2_SENSE_DATA_PRESENT)
1561 break;
1562 /* copy the sense data */
1563 data_len = c2->error_data.sense_data_len;
1564 if (data_len > SCSI_SENSE_BUFFERSIZE)
1565 data_len = SCSI_SENSE_BUFFERSIZE;
1566 if (data_len > sizeof(c2->error_data.sense_data_buff))
1567 data_len =
1568 sizeof(c2->error_data.sense_data_buff);
1569 memcpy(cmd->sense_buffer,
1570 c2->error_data.sense_data_buff, data_len);
1571 cmd->result |= SAM_STAT_CHECK_CONDITION;
a09c1441 1572 retry = 1;
c349775e
ST		 1573 break;
1574 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1575 dev_warn(&h->pdev->dev,
1576 "%s: task complete with BUSY status.\n",
1577 "HP SSD Smart Path");
a09c1441 1578 retry = 1;
c349775e
ST		 1579 break;
1580 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1581 dev_warn(&h->pdev->dev,
1582 "%s: task complete with reservation conflict.\n",
1583 "HP SSD Smart Path");
a09c1441 1584 retry = 1;
c349775e
ST		 1585 break;
1586 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1587 /* Make scsi midlayer do unlimited retries */
1588 cmd->result = DID_IMM_RETRY << 16;
1589 break;
1590 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1591 dev_warn(&h->pdev->dev,
1592 "%s: task complete with aborted status.\n",
1593 "HP SSD Smart Path");
a09c1441 1594 retry = 1;
c349775e
ST		 1595 break;
1596 default:
1597 dev_warn(&h->pdev->dev,
1598 "%s: task complete with unrecognized status: 0x%02x\n",
1599 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1600 retry = 1;
c349775e
ST		 1601 break;
1602 }
1603 break;
1604 case IOACCEL2_SERV_RESPONSE_FAILURE:
1605 /* don't expect to get here. */
1606 dev_warn(&h->pdev->dev,
1607 "unexpected delivery or target failure, status = 0x%02x\n",
1608 c2->error_data.status);
a09c1441 1609 retry = 1;
c349775e
ST		 1610 break;
1611 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1612 break;
1613 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1614 break;
1615 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1616 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1617 retry = 1;
c349775e
ST		 1618 break;
1619 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1620 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1621 break;
1622 default:
1623 dev_warn(&h->pdev->dev,
1624 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1625 "HP SSD Smart Path",
1626 c2->error_data.serv_response);
1627 retry = 1;
c349775e
ST		 1628 break;
1629 }
a09c1441
ST		 1630
1631 return retry; /* retry on raid path? */
c349775e
ST		 1632}
1633
1634static void process_ioaccel2_completion(struct ctlr_info *h,
1635 struct CommandList *c, struct scsi_cmnd *cmd,
1636 struct hpsa_scsi_dev_t *dev)
1637{
1638 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
a09c1441 1639 int raid_retry = 0;
c349775e
ST		 1640
1641 /* check for good status */
1642 if (likely(c2->error_data.serv_response == 0 &&
1643 c2->error_data.status == 0)) {
1644 cmd_free(h, c);
1645 cmd->scsi_done(cmd);
1646 return;
1647 }
1648
1649 /* Any RAID offload error results in retry which will use
1650 * the normal I/O path so the controller can handle whatever's
1651 * wrong.
1652 */
1653 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1654 c2->error_data.serv_response ==
1655 IOACCEL2_SERV_RESPONSE_FAILURE) {
c349775e 1656 dev->offload_enabled = 0;
e863d68e 1657 h->drv_req_rescan = 1; /* schedule controller for a rescan */
c349775e
ST		 1658 cmd->result = DID_SOFT_ERROR << 16;
1659 cmd_free(h, c);
1660 cmd->scsi_done(cmd);
1661 return;
1662 }
a09c1441
ST		 1663 raid_retry = handle_ioaccel_mode2_error(h, c, cmd, c2);
1664 /* If error found, disable Smart Path, schedule a rescan,
1665 * and force a retry on the standard path.
1666 */
1667 if (raid_retry) {
1668 dev_warn(&h->pdev->dev, "%s: Retrying on standard path.\n",
1669 "HP SSD Smart Path");
1670 dev->offload_enabled = 0; /* Disable Smart Path */
1671 h->drv_req_rescan = 1; /* schedule controller rescan */
1672 cmd->result = DID_SOFT_ERROR << 16;
1673 }
c349775e
ST		 1674 cmd_free(h, c);
1675 cmd->scsi_done(cmd);
1676}
1677
1fb011fb 1678static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1679{
1680 struct scsi_cmnd *cmd;
1681 struct ctlr_info *h;
1682 struct ErrorInfo *ei;
283b4a9b 1683 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1684
1685 unsigned char sense_key;
1686 unsigned char asc; /* additional sense code */
1687 unsigned char ascq; /* additional sense code qualifier */
db111e18 1688 unsigned long sense_data_size;
edd16368
SC		 1689
1690 ei = cp->err_info;
1691 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1692 h = cp->h;
283b4a9b 1693 dev = cmd->device->hostdata;
edd16368
SC		 1694
1695 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c
MG		 1696 if ((cp->cmd_type == CMD_SCSI) &&
1697 (cp->Header.SGTotal > h->max_cmd_sg_entries))
33a2ffce 1698 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1699
1700 cmd->result = (DID_OK << 16); /* host byte */
1701 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1702
1703 if (cp->cmd_type == CMD_IOACCEL2)
1704 return process_ioaccel2_completion(h, cp, cmd, dev);
1705
5512672f 1706 cmd->result |= ei->ScsiStatus;
edd16368
SC		 1707
1708 /* copy the sense data whether we need to or not. */
db111e18
SC		 1709 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1710 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1711 else
1712 sense_data_size = sizeof(ei->SenseInfo);
1713 if (ei->SenseLen < sense_data_size)
1714 sense_data_size = ei->SenseLen;
1715
1716 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368
SC		 1717 scsi_set_resid(cmd, ei->ResidualCnt);
1718
1719 if (ei->CommandStatus == 0) {
edd16368 1720 cmd_free(h, cp);
2cc5bfaf 1721 cmd->scsi_done(cmd);
edd16368
SC		 1722 return;
1723 }
1724
e1f7de0c
MG		 1725 /* For I/O accelerator commands, copy over some fields to the normal
1726 * CISS header used below for error handling.
1727 */
1728 if (cp->cmd_type == CMD_IOACCEL1) {
1729 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
1730 cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd);
1731 cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK;
1732 cp->Header.Tag.lower = c->Tag.lower;
1733 cp->Header.Tag.upper = c->Tag.upper;
1734 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1735 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1736
1737 /* Any RAID offload error results in retry which will use
1738 * the normal I/O path so the controller can handle whatever's
1739 * wrong.
1740 */
1741 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1742 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1743 dev->offload_enabled = 0;
1744 cmd->result = DID_SOFT_ERROR << 16;
1745 cmd_free(h, cp);
1746 cmd->scsi_done(cmd);
1747 return;
1748 }
e1f7de0c
MG		 1749 }
1750
edd16368
SC		 1751 /* an error has occurred */
1752 switch (ei->CommandStatus) {
1753
1754 case CMD_TARGET_STATUS:
1755 if (ei->ScsiStatus) {
1756 /* Get sense key */
1757 sense_key = 0xf & ei->SenseInfo[2];
1758 /* Get additional sense code */
1759 asc = ei->SenseInfo[12];
1760 /* Get addition sense code qualifier */
1761 ascq = ei->SenseInfo[13];
1762 }
1763
1764 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
3ce438df 1765 if (check_for_unit_attention(h, cp))
edd16368 1766 break;
edd16368
SC		 1767 if (sense_key == ILLEGAL_REQUEST) {
1768 /*
1769 * SCSI REPORT_LUNS is commonly unsupported on
1770 * Smart Array. Suppress noisy complaint.
1771 */
1772 if (cp->Request.CDB[0] == REPORT_LUNS)
1773 break;
1774
1775 /* If ASC/ASCQ indicate Logical Unit
1776 * Not Supported condition,
1777 */
1778 if ((asc == 0x25) && (ascq == 0x0)) {
1779 dev_warn(&h->pdev->dev, "cp %p "
1780 "has check condition\n", cp);
1781 break;
1782 }
1783 }
1784
1785 if (sense_key == NOT_READY) {
1786 /* If Sense is Not Ready, Logical Unit
1787 * Not ready, Manual Intervention
1788 * required
1789 */
1790 if ((asc == 0x04) && (ascq == 0x03)) {
edd16368
SC		 1791 dev_warn(&h->pdev->dev, "cp %p "
1792 "has check condition: unit "
1793 "not ready, manual "
1794 "intervention required\n", cp);
1795 break;
1796 }
1797 }
1d3b3609
MG		 1798 if (sense_key == ABORTED_COMMAND) {
1799 /* Aborted command is retryable */
1800 dev_warn(&h->pdev->dev, "cp %p "
1801 "has check condition: aborted command: "
1802 "ASC: 0x%x, ASCQ: 0x%x\n",
1803 cp, asc, ascq);
2e311fba 1804 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1805 break;
1806 }
edd16368 1807 /* Must be some other type of check condition */
21b8e4ef 1808 dev_dbg(&h->pdev->dev, "cp %p has check condition: "
edd16368
SC		 1809 "unknown type: "
1810 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1811 "Returning result: 0x%x, "
1812 "cmd=[%02x %02x %02x %02x %02x "
807be732 1813 "%02x %02x %02x %02x %02x %02x "
edd16368
SC		 1814 "%02x %02x %02x %02x %02x]\n",
1815 cp, sense_key, asc, ascq,
1816 cmd->result,
1817 cmd->cmnd[0], cmd->cmnd[1],
1818 cmd->cmnd[2], cmd->cmnd[3],
1819 cmd->cmnd[4], cmd->cmnd[5],
1820 cmd->cmnd[6], cmd->cmnd[7],
807be732
MM		 1821 cmd->cmnd[8], cmd->cmnd[9],
1822 cmd->cmnd[10], cmd->cmnd[11],
1823 cmd->cmnd[12], cmd->cmnd[13],
1824 cmd->cmnd[14], cmd->cmnd[15]);
edd16368
SC		 1825 break;
1826 }
1827
1828
1829 /* Problem was not a check condition
1830 * Pass it up to the upper layers...
1831 */
1832 if (ei->ScsiStatus) {
1833 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1834 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1835 "Returning result: 0x%x\n",
1836 cp, ei->ScsiStatus,
1837 sense_key, asc, ascq,
1838 cmd->result);
1839 } else { /* scsi status is zero??? How??? */
1840 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1841 "Returning no connection.\n", cp),
1842
1843 /* Ordinarily, this case should never happen,
1844 * but there is a bug in some released firmware
1845 * revisions that allows it to happen if, for
1846 * example, a 4100 backplane loses power and
1847 * the tape drive is in it. We assume that
1848 * it's a fatal error of some kind because we
1849 * can't show that it wasn't. We will make it
1850 * look like selection timeout since that is
1851 * the most common reason for this to occur,
1852 * and it's severe enough.
1853 */
1854
1855 cmd->result = DID_NO_CONNECT << 16;
1856 }
1857 break;
1858
1859 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1860 break;
1861 case CMD_DATA_OVERRUN:
1862 dev_warn(&h->pdev->dev, "cp %p has"
1863 " completed with data overrun "
1864 "reported\n", cp);
1865 break;
1866 case CMD_INVALID: {
1867 /* print_bytes(cp, sizeof(*cp), 1, 0);
1868 print_cmd(cp); */
1869 /* We get CMD_INVALID if you address a non-existent device
1870 * instead of a selection timeout (no response). You will
1871 * see this if you yank out a drive, then try to access it.
1872 * This is kind of a shame because it means that any other
1873 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1874 * missing target. */
1875 cmd->result = DID_NO_CONNECT << 16;
1876 }
1877 break;
1878 case CMD_PROTOCOL_ERR:
256d0eaa 1879 cmd->result = DID_ERROR << 16;
edd16368 1880 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1881 "protocol error\n", cp);
edd16368
SC		 1882 break;
1883 case CMD_HARDWARE_ERR:
1884 cmd->result = DID_ERROR << 16;
1885 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1886 break;
1887 case CMD_CONNECTION_LOST:
1888 cmd->result = DID_ERROR << 16;
1889 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1890 break;
1891 case CMD_ABORTED:
1892 cmd->result = DID_ABORT << 16;
1893 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1894 cp, ei->ScsiStatus);
1895 break;
1896 case CMD_ABORT_FAILED:
1897 cmd->result = DID_ERROR << 16;
1898 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1899 break;
1900 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1901 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1902 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1903 "abort\n", cp);
1904 break;
1905 case CMD_TIMEOUT:
1906 cmd->result = DID_TIME_OUT << 16;
1907 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1908 break;
1d5e2ed0
SC		 1909 case CMD_UNABORTABLE:
1910 cmd->result = DID_ERROR << 16;
1911 dev_warn(&h->pdev->dev, "Command unabortable\n");
1912 break;
283b4a9b
SC		 1913 case CMD_IOACCEL_DISABLED:
1914 /* This only handles the direct pass-through case since RAID
1915 * offload is handled above. Just attempt a retry.
1916 */
1917 cmd->result = DID_SOFT_ERROR << 16;
1918 dev_warn(&h->pdev->dev,
1919 "cp %p had HP SSD Smart Path error\n", cp);
1920 break;
edd16368
SC		 1921 default:
1922 cmd->result = DID_ERROR << 16;
1923 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1924 cp, ei->CommandStatus);
1925 }
edd16368 1926 cmd_free(h, cp);
2cc5bfaf 1927 cmd->scsi_done(cmd);
edd16368
SC		 1928}
1929
edd16368
SC		 1930static void hpsa_pci_unmap(struct pci_dev *pdev,
1931 struct CommandList *c, int sg_used, int data_direction)
1932{
1933 int i;
1934 union u64bit addr64;
1935
1936 for (i = 0; i < sg_used; i++) {
1937 addr64.val32.lower = c->SG[i].Addr.lower;
1938 addr64.val32.upper = c->SG[i].Addr.upper;
1939 pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
1940 data_direction);
1941 }
1942}
1943
a2dac136 1944static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1945 struct CommandList *cp,
1946 unsigned char *buf,
1947 size_t buflen,
1948 int data_direction)
1949{
01a02ffc 1950 u64 addr64;
edd16368
SC		 1951
1952 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1953 cp->Header.SGList = 0;
1954 cp->Header.SGTotal = 0;
a2dac136 1955 return 0;
edd16368
SC		 1956 }
1957
01a02ffc 1958 addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1959 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1960 /* Prevent subsequent unmap of something never mapped */
eceaae18
SK		 1961 cp->Header.SGList = 0;
1962 cp->Header.SGTotal = 0;
a2dac136 1963 return -1;
eceaae18 1964 }
edd16368 1965 cp->SG[0].Addr.lower =
01a02ffc 1966 (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
edd16368 1967 cp->SG[0].Addr.upper =
01a02ffc 1968 (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
edd16368 1969 cp->SG[0].Len = buflen;
e1d9cbfa 1970 cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */
01a02ffc
SC		 1971 cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
1972 cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
a2dac136 1973 return 0;
edd16368
SC		 1974}
1975
1976static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1977 struct CommandList *c)
1978{
1979 DECLARE_COMPLETION_ONSTACK(wait);
1980
1981 c->waiting = &wait;
1982 enqueue_cmd_and_start_io(h, c);
1983 wait_for_completion(&wait);
1984}
1985
094963da
SC		 1986static u32 lockup_detected(struct ctlr_info *h)
1987{
1988 int cpu;
1989 u32 rc, *lockup_detected;
1990
1991 cpu = get_cpu();
1992 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
1993 rc = *lockup_detected;
1994 put_cpu();
1995 return rc;
1996}
1997
a0c12413
SC		 1998static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1999 struct CommandList *c)
2000{
a0c12413 2001 /* If controller lockup detected, fake a hardware error. */
094963da 2002 if (unlikely(lockup_detected(h)))
a0c12413 2003 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
094963da 2004 else
a0c12413 2005 hpsa_scsi_do_simple_cmd_core(h, c);
a0c12413
SC		 2006}
2007
9c2fc160 2008#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 2009static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2010 struct CommandList *c, int data_direction)
2011{
9c2fc160 2012 int backoff_time = 10, retry_count = 0;
edd16368
SC		 2013
2014 do {
7630abd0 2015 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 2016 hpsa_scsi_do_simple_cmd_core(h, c);
2017 retry_count++;
9c2fc160
SC		 2018 if (retry_count > 3) {
2019 msleep(backoff_time);
2020 if (backoff_time < 1000)
2021 backoff_time *= 2;
2022 }
852af20a 2023 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2024 check_for_busy(h, c)) &&
2025 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 2026 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
2027}
2028
d1e8beac
SC		 2029static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2030 struct CommandList *c)
edd16368 2031{
d1e8beac
SC		 2032 const u8 *cdb = c->Request.CDB;
2033 const u8 *lun = c->Header.LUN.LunAddrBytes;
2034
2035 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2036 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2037 txt, lun[0], lun[1], lun[2], lun[3],
2038 lun[4], lun[5], lun[6], lun[7],
2039 cdb[0], cdb[1], cdb[2], cdb[3],
2040 cdb[4], cdb[5], cdb[6], cdb[7],
2041 cdb[8], cdb[9], cdb[10], cdb[11],
2042 cdb[12], cdb[13], cdb[14], cdb[15]);
2043}
2044
2045static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2046 struct CommandList *cp)
2047{
2048 const struct ErrorInfo *ei = cp->err_info;
edd16368 2049 struct device *d = &cp->h->pdev->dev;
d1e8beac 2050 const u8 *sd = ei->SenseInfo;
edd16368 2051
edd16368
SC		 2052 switch (ei->CommandStatus) {
2053 case CMD_TARGET_STATUS:
d1e8beac
SC		 2054 hpsa_print_cmd(h, "SCSI status", cp);
2055 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
2056 dev_warn(d, "SCSI Status = 02, Sense key = %02x, ASC = %02x, ASCQ = %02x\n",
2057 sd[2] & 0x0f, sd[12], sd[13]);
2058 else
2059 dev_warn(d, "SCSI Status = %02x\n", ei->ScsiStatus);
edd16368
SC		 2060 if (ei->ScsiStatus == 0)
2061 dev_warn(d, "SCSI status is abnormally zero. "
2062 "(probably indicates selection timeout "
2063 "reported incorrectly due to a known "
2064 "firmware bug, circa July, 2001.)\n");
2065 break;
2066 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2067 break;
2068 case CMD_DATA_OVERRUN:
d1e8beac 2069 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2070 break;
2071 case CMD_INVALID: {
2072 /* controller unfortunately reports SCSI passthru's
2073 * to non-existent targets as invalid commands.
2074 */
d1e8beac
SC		 2075 hpsa_print_cmd(h, "invalid command", cp);
2076 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2077 }
2078 break;
2079 case CMD_PROTOCOL_ERR:
d1e8beac 2080 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2081 break;
2082 case CMD_HARDWARE_ERR:
d1e8beac 2083 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2084 break;
2085 case CMD_CONNECTION_LOST:
d1e8beac 2086 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2087 break;
2088 case CMD_ABORTED:
d1e8beac 2089 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2090 break;
2091 case CMD_ABORT_FAILED:
d1e8beac 2092 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2093 break;
2094 case CMD_UNSOLICITED_ABORT:
d1e8beac 2095 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2096 break;
2097 case CMD_TIMEOUT:
d1e8beac 2098 hpsa_print_cmd(h, "timed out", cp);
edd16368 2099 break;
1d5e2ed0 2100 case CMD_UNABORTABLE:
d1e8beac 2101 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2102 break;
edd16368 2103 default:
d1e8beac
SC		 2104 hpsa_print_cmd(h, "unknown status", cp);
2105 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2106 ei->CommandStatus);
2107 }
2108}
2109
2110static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2111 u16 page, unsigned char *buf,
edd16368
SC		 2112 unsigned char bufsize)
2113{
2114 int rc = IO_OK;
2115 struct CommandList *c;
2116 struct ErrorInfo *ei;
2117
2118 c = cmd_special_alloc(h);
2119
2120 if (c == NULL) { /* trouble... */
2121 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
ecd9aad4 2122 return -ENOMEM;
edd16368
SC		 2123 }
2124
a2dac136
SC		 2125 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2126 page, scsi3addr, TYPE_CMD)) {
2127 rc = -1;
2128 goto out;
2129 }
edd16368
SC		 2130 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2131 ei = c->err_info;
2132 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2133 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2134 rc = -1;
2135 }
a2dac136 2136out:
edd16368
SC		 2137 cmd_special_free(h, c);
2138 return rc;
2139}
2140
316b221a
SC		 2141static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2142 unsigned char *scsi3addr, unsigned char page,
2143 struct bmic_controller_parameters *buf, size_t bufsize)
2144{
2145 int rc = IO_OK;
2146 struct CommandList *c;
2147 struct ErrorInfo *ei;
2148
2149 c = cmd_special_alloc(h);
2150
2151 if (c == NULL) { /* trouble... */
2152 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2153 return -ENOMEM;
2154 }
2155
2156 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2157 page, scsi3addr, TYPE_CMD)) {
2158 rc = -1;
2159 goto out;
2160 }
2161 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2162 ei = c->err_info;
2163 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2164 hpsa_scsi_interpret_error(h, c);
2165 rc = -1;
2166 }
2167out:
2168 cmd_special_free(h, c);
2169 return rc;
2170 }
2171
bf711ac6
ST		 2172static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
2173 u8 reset_type)
edd16368
SC		 2174{
2175 int rc = IO_OK;
2176 struct CommandList *c;
2177 struct ErrorInfo *ei;
2178
2179 c = cmd_special_alloc(h);
2180
2181 if (c == NULL) { /* trouble... */
2182 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
e9ea04a6 2183 return -ENOMEM;
edd16368
SC		 2184 }
2185
a2dac136 2186 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2187 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2188 scsi3addr, TYPE_MSG);
2189 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 2190 hpsa_scsi_do_simple_cmd_core(h, c);
2191 /* no unmap needed here because no data xfer. */
2192
2193 ei = c->err_info;
2194 if (ei->CommandStatus != 0) {
d1e8beac 2195 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2196 rc = -1;
2197 }
2198 cmd_special_free(h, c);
2199 return rc;
2200}
2201
2202static void hpsa_get_raid_level(struct ctlr_info *h,
2203 unsigned char *scsi3addr, unsigned char *raid_level)
2204{
2205 int rc;
2206 unsigned char *buf;
2207
2208 *raid_level = RAID_UNKNOWN;
2209 buf = kzalloc(64, GFP_KERNEL);
2210 if (!buf)
2211 return;
b7bb24eb 2212 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2213 if (rc == 0)
2214 *raid_level = buf[8];
2215 if (*raid_level > RAID_UNKNOWN)
2216 *raid_level = RAID_UNKNOWN;
2217 kfree(buf);
2218 return;
2219}
2220
283b4a9b
SC		 2221#define HPSA_MAP_DEBUG
2222#ifdef HPSA_MAP_DEBUG
2223static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2224 struct raid_map_data *map_buff)
2225{
2226 struct raid_map_disk_data *dd = &map_buff->data[0];
2227 int map, row, col;
2228 u16 map_cnt, row_cnt, disks_per_row;
2229
2230 if (rc != 0)
2231 return;
2232
2ba8bfc8
SC		 2233 /* Show details only if debugging has been activated. */
2234 if (h->raid_offload_debug < 2)
2235 return;
2236
283b4a9b
SC		 2237 dev_info(&h->pdev->dev, "structure_size = %u\n",
2238 le32_to_cpu(map_buff->structure_size));
2239 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2240 le32_to_cpu(map_buff->volume_blk_size));
2241 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2242 le64_to_cpu(map_buff->volume_blk_cnt));
2243 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2244 map_buff->phys_blk_shift);
2245 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2246 map_buff->parity_rotation_shift);
2247 dev_info(&h->pdev->dev, "strip_size = %u\n",
2248 le16_to_cpu(map_buff->strip_size));
2249 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2250 le64_to_cpu(map_buff->disk_starting_blk));
2251 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2252 le64_to_cpu(map_buff->disk_blk_cnt));
2253 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2254 le16_to_cpu(map_buff->data_disks_per_row));
2255 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2256 le16_to_cpu(map_buff->metadata_disks_per_row));
2257 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2258 le16_to_cpu(map_buff->row_cnt));
2259 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2260 le16_to_cpu(map_buff->layout_map_count));
dd0e19f3
ST		 2261 dev_info(&h->pdev->dev, "flags = %u\n",
2262 le16_to_cpu(map_buff->flags));
2263 if (map_buff->flags & RAID_MAP_FLAG_ENCRYPT_ON)
2264 dev_info(&h->pdev->dev, "encrypytion = ON\n");
2265 else
2266 dev_info(&h->pdev->dev, "encrypytion = OFF\n");
2267 dev_info(&h->pdev->dev, "dekindex = %u\n",
2268 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2269
2270 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2271 for (map = 0; map < map_cnt; map++) {
2272 dev_info(&h->pdev->dev, "Map%u:\n", map);
2273 row_cnt = le16_to_cpu(map_buff->row_cnt);
2274 for (row = 0; row < row_cnt; row++) {
2275 dev_info(&h->pdev->dev, " Row%u:\n", row);
2276 disks_per_row =
2277 le16_to_cpu(map_buff->data_disks_per_row);
2278 for (col = 0; col < disks_per_row; col++, dd++)
2279 dev_info(&h->pdev->dev,
2280 " D%02u: h=0x%04x xor=%u,%u\n",
2281 col, dd->ioaccel_handle,
2282 dd->xor_mult[0], dd->xor_mult[1]);
2283 disks_per_row =
2284 le16_to_cpu(map_buff->metadata_disks_per_row);
2285 for (col = 0; col < disks_per_row; col++, dd++)
2286 dev_info(&h->pdev->dev,
2287 " M%02u: h=0x%04x xor=%u,%u\n",
2288 col, dd->ioaccel_handle,
2289 dd->xor_mult[0], dd->xor_mult[1]);
2290 }
2291 }
2292}
2293#else
2294static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2295 __attribute__((unused)) int rc,
2296 __attribute__((unused)) struct raid_map_data *map_buff)
2297{
2298}
2299#endif
2300
2301static int hpsa_get_raid_map(struct ctlr_info *h,
2302 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2303{
2304 int rc = 0;
2305 struct CommandList *c;
2306 struct ErrorInfo *ei;
2307
2308 c = cmd_special_alloc(h);
2309 if (c == NULL) {
2310 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2311 return -ENOMEM;
2312 }
2313 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2314 sizeof(this_device->raid_map), 0,
2315 scsi3addr, TYPE_CMD)) {
2316 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
2317 cmd_special_free(h, c);
2318 return -ENOMEM;
2319 }
2320 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2321 ei = c->err_info;
2322 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2323 hpsa_scsi_interpret_error(h, c);
283b4a9b
SC		 2324 cmd_special_free(h, c);
2325 return -1;
2326 }
2327 cmd_special_free(h, c);
2328
2329 /* @todo in the future, dynamically allocate RAID map memory */
2330 if (le32_to_cpu(this_device->raid_map.structure_size) >
2331 sizeof(this_device->raid_map)) {
2332 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2333 rc = -1;
2334 }
2335 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2336 return rc;
2337}
2338
1b70150a
SC		 2339static int hpsa_vpd_page_supported(struct ctlr_info *h,
2340 unsigned char scsi3addr[], u8 page)
2341{
2342 int rc;
2343 int i;
2344 int pages;
2345 unsigned char *buf, bufsize;
2346
2347 buf = kzalloc(256, GFP_KERNEL);
2348 if (!buf)
2349 return 0;
2350
2351 /* Get the size of the page list first */
2352 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2353 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2354 buf, HPSA_VPD_HEADER_SZ);
2355 if (rc != 0)
2356 goto exit_unsupported;
2357 pages = buf[3];
2358 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2359 bufsize = pages + HPSA_VPD_HEADER_SZ;
2360 else
2361 bufsize = 255;
2362
2363 /* Get the whole VPD page list */
2364 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2365 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2366 buf, bufsize);
2367 if (rc != 0)
2368 goto exit_unsupported;
2369
2370 pages = buf[3];
2371 for (i = 1; i <= pages; i++)
2372 if (buf[3 + i] == page)
2373 goto exit_supported;
2374exit_unsupported:
2375 kfree(buf);
2376 return 0;
2377exit_supported:
2378 kfree(buf);
2379 return 1;
2380}
2381
283b4a9b
SC		 2382static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2383 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2384{
2385 int rc;
2386 unsigned char *buf;
2387 u8 ioaccel_status;
2388
2389 this_device->offload_config = 0;
2390 this_device->offload_enabled = 0;
2391
2392 buf = kzalloc(64, GFP_KERNEL);
2393 if (!buf)
2394 return;
1b70150a
SC		 2395 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2396 goto out;
283b4a9b 2397 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2398 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2399 if (rc != 0)
2400 goto out;
2401
2402#define IOACCEL_STATUS_BYTE 4
2403#define OFFLOAD_CONFIGURED_BIT 0x01
2404#define OFFLOAD_ENABLED_BIT 0x02
2405 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2406 this_device->offload_config =
2407 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2408 if (this_device->offload_config) {
2409 this_device->offload_enabled =
2410 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2411 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2412 this_device->offload_enabled = 0;
2413 }
2414out:
2415 kfree(buf);
2416 return;
2417}
2418
edd16368
SC		 2419/* Get the device id from inquiry page 0x83 */
2420static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2421 unsigned char *device_id, int buflen)
2422{
2423 int rc;
2424 unsigned char *buf;
2425
2426 if (buflen > 16)
2427 buflen = 16;
2428 buf = kzalloc(64, GFP_KERNEL);
2429 if (!buf)
2430 return -1;
b7bb24eb 2431 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2432 if (rc == 0)
2433 memcpy(device_id, &buf[8], buflen);
2434 kfree(buf);
2435 return rc != 0;
2436}
2437
2438static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2439 struct ReportLUNdata *buf, int bufsize,
2440 int extended_response)
2441{
2442 int rc = IO_OK;
2443 struct CommandList *c;
2444 unsigned char scsi3addr[8];
2445 struct ErrorInfo *ei;
2446
2447 c = cmd_special_alloc(h);
2448 if (c == NULL) { /* trouble... */
2449 dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2450 return -1;
2451 }
e89c0ae7
SC		 2452 /* address the controller */
2453 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2454 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2455 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2456 rc = -1;
2457 goto out;
2458 }
edd16368
SC		 2459 if (extended_response)
2460 c->Request.CDB[1] = extended_response;
2461 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2462 ei = c->err_info;
2463 if (ei->CommandStatus != 0 &&
2464 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2465 hpsa_scsi_interpret_error(h, c);
edd16368 2466 rc = -1;
283b4a9b
SC		 2467 } else {
2468 if (buf->extended_response_flag != extended_response) {
2469 dev_err(&h->pdev->dev,
2470 "report luns requested format %u, got %u\n",
2471 extended_response,
2472 buf->extended_response_flag);
2473 rc = -1;
2474 }
edd16368 2475 }
a2dac136 2476out:
edd16368
SC		 2477 cmd_special_free(h, c);
2478 return rc;
2479}
2480
2481static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2482 struct ReportLUNdata *buf,
2483 int bufsize, int extended_response)
2484{
2485 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2486}
2487
2488static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2489 struct ReportLUNdata *buf, int bufsize)
2490{
2491 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2492}
2493
2494static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2495 int bus, int target, int lun)
2496{
2497 device->bus = bus;
2498 device->target = target;
2499 device->lun = lun;
2500}
2501
9846590e
SC		 2502/* Use VPD inquiry to get details of volume status */
2503static int hpsa_get_volume_status(struct ctlr_info *h,
2504 unsigned char scsi3addr[])
2505{
2506 int rc;
2507 int status;
2508 int size;
2509 unsigned char *buf;
2510
2511 buf = kzalloc(64, GFP_KERNEL);
2512 if (!buf)
2513 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2514
2515 /* Does controller have VPD for logical volume status? */
2516 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS)) {
2517 dev_warn(&h->pdev->dev, "Logical volume status VPD page is unsupported.\n");
2518 goto exit_failed;
2519 }
2520
2521 /* Get the size of the VPD return buffer */
2522 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2523 buf, HPSA_VPD_HEADER_SZ);
2524 if (rc != 0) {
2525 dev_warn(&h->pdev->dev, "Logical volume status VPD inquiry failed.\n");
2526 goto exit_failed;
2527 }
2528 size = buf[3];
2529
2530 /* Now get the whole VPD buffer */
2531 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2532 buf, size + HPSA_VPD_HEADER_SZ);
2533 if (rc != 0) {
2534 dev_warn(&h->pdev->dev, "Logical volume status VPD inquiry failed.\n");
2535 goto exit_failed;
2536 }
2537 status = buf[4]; /* status byte */
2538
2539 kfree(buf);
2540 return status;
2541exit_failed:
2542 kfree(buf);
2543 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2544}
2545
2546/* Determine offline status of a volume.
2547 * Return either:
2548 * 0 (not offline)
2549 * -1 (offline for unknown reasons)
2550 * # (integer code indicating one of several NOT READY states
2551 * describing why a volume is to be kept offline)
2552 */
2553static unsigned char hpsa_volume_offline(struct ctlr_info *h,
2554 unsigned char scsi3addr[])
2555{
2556 struct CommandList *c;
2557 unsigned char *sense, sense_key, asc, ascq;
2558 int ldstat = 0;
2559 u16 cmd_status;
2560 u8 scsi_status;
2561#define ASC_LUN_NOT_READY 0x04
2562#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
2563#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
2564
2565 c = cmd_alloc(h);
2566 if (!c)
2567 return 0;
2568 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
2569 hpsa_scsi_do_simple_cmd_core(h, c);
2570 sense = c->err_info->SenseInfo;
2571 sense_key = sense[2];
2572 asc = sense[12];
2573 ascq = sense[13];
2574 cmd_status = c->err_info->CommandStatus;
2575 scsi_status = c->err_info->ScsiStatus;
2576 cmd_free(h, c);
2577 /* Is the volume 'not ready'? */
2578 if (cmd_status != CMD_TARGET_STATUS ||
2579 scsi_status != SAM_STAT_CHECK_CONDITION ||
2580 sense_key != NOT_READY ||
2581 asc != ASC_LUN_NOT_READY) {
2582 return 0;
2583 }
2584
2585 /* Determine the reason for not ready state */
2586 ldstat = hpsa_get_volume_status(h, scsi3addr);
2587
2588 /* Keep volume offline in certain cases: */
2589 switch (ldstat) {
2590 case HPSA_LV_UNDERGOING_ERASE:
2591 case HPSA_LV_UNDERGOING_RPI:
2592 case HPSA_LV_PENDING_RPI:
2593 case HPSA_LV_ENCRYPTED_NO_KEY:
2594 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
2595 case HPSA_LV_UNDERGOING_ENCRYPTION:
2596 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
2597 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
2598 return ldstat;
2599 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
2600 /* If VPD status page isn't available,
2601 * use ASC/ASCQ to determine state
2602 */
2603 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
2604 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
2605 return ldstat;
2606 break;
2607 default:
2608 break;
2609 }
2610 return 0;
2611}
2612
edd16368 2613static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2614 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2615 unsigned char *is_OBDR_device)
edd16368 2616{
0b0e1d6c
SC		 2617
2618#define OBDR_SIG_OFFSET 43
2619#define OBDR_TAPE_SIG "$DR-10"
2620#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2621#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2622
ea6d3bc3 2623 unsigned char *inq_buff;
0b0e1d6c 2624 unsigned char *obdr_sig;
edd16368 2625
ea6d3bc3 2626 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2627 if (!inq_buff)
2628 goto bail_out;
2629
edd16368
SC		 2630 /* Do an inquiry to the device to see what it is. */
2631 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2632 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2633 /* Inquiry failed (msg printed already) */
2634 dev_err(&h->pdev->dev,
2635 "hpsa_update_device_info: inquiry failed\n");
2636 goto bail_out;
2637 }
2638
edd16368
SC		 2639 this_device->devtype = (inq_buff[0] & 0x1f);
2640 memcpy(this_device->scsi3addr, scsi3addr, 8);
2641 memcpy(this_device->vendor, &inq_buff[8],
2642 sizeof(this_device->vendor));
2643 memcpy(this_device->model, &inq_buff[16],
2644 sizeof(this_device->model));
edd16368
SC		 2645 memset(this_device->device_id, 0,
2646 sizeof(this_device->device_id));
2647 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2648 sizeof(this_device->device_id));
2649
2650 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2651 is_logical_dev_addr_mode(scsi3addr)) {
edd16368 2652 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2653 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2654 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
9846590e
SC		 2655 this_device->volume_offline =
2656 hpsa_volume_offline(h, scsi3addr);
283b4a9b 2657 } else {
edd16368 2658 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2659 this_device->offload_config = 0;
2660 this_device->offload_enabled = 0;
9846590e 2661 this_device->volume_offline = 0;
283b4a9b 2662 }
edd16368 2663
0b0e1d6c
SC		 2664 if (is_OBDR_device) {
2665 /* See if this is a One-Button-Disaster-Recovery device
2666 * by looking for "$DR-10" at offset 43 in inquiry data.
2667 */
2668 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2669 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2670 strncmp(obdr_sig, OBDR_TAPE_SIG,
2671 OBDR_SIG_LEN) == 0);
2672 }
2673
edd16368
SC		 2674 kfree(inq_buff);
2675 return 0;
2676
2677bail_out:
2678 kfree(inq_buff);
2679 return 1;
2680}
2681
4f4eb9f1 2682static unsigned char *ext_target_model[] = {
edd16368
SC		 2683 "MSA2012",
2684 "MSA2024",
2685 "MSA2312",
2686 "MSA2324",
fda38518 2687 "P2000 G3 SAS",
e06c8e5c 2688 "MSA 2040 SAS",
edd16368
SC		 2689 NULL,
2690};
2691
4f4eb9f1 2692static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2693{
2694 int i;
2695
4f4eb9f1
ST		 2696 for (i = 0; ext_target_model[i]; i++)
2697 if (strncmp(device->model, ext_target_model[i],
2698 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2699 return 1;
2700 return 0;
2701}
2702
2703/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2704 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2705 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2706 * Logical drive target and lun are assigned at this time, but
2707 * physical device lun and target assignment are deferred (assigned
2708 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2709 */
2710static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2711 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2712{
1f310bde
SC		 2713 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2714
2715 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2716 /* physical device, target and lun filled in later */
edd16368 2717 if (is_hba_lunid(lunaddrbytes))
1f310bde 2718 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2719 else
1f310bde
SC		 2720 /* defer target, lun assignment for physical devices */
2721 hpsa_set_bus_target_lun(device, 2, -1, -1);
2722 return;
2723 }
2724 /* It's a logical device */
4f4eb9f1
ST		 2725 if (is_ext_target(h, device)) {
2726 /* external target way, put logicals on bus 1
1f310bde
SC		 2727 * and match target/lun numbers box
2728 * reports, other smart array, bus 0, target 0, match lunid
2729 */
2730 hpsa_set_bus_target_lun(device,
2731 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2732 return;
edd16368 2733 }
1f310bde 2734 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2735}
2736
2737/*
2738 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2739 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2740 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2741 * it for some reason. *tmpdevice is the target we're adding,
2742 * this_device is a pointer into the current element of currentsd[]
2743 * that we're building up in update_scsi_devices(), below.
2744 * lunzerobits is a bitmap that tracks which targets already have a
2745 * lun 0 assigned.
2746 * Returns 1 if an enclosure was added, 0 if not.
2747 */
4f4eb9f1 2748static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2749 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2750 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2751 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2752{
2753 unsigned char scsi3addr[8];
2754
1f310bde 2755 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2756 return 0; /* There is already a lun 0 on this target. */
2757
2758 if (!is_logical_dev_addr_mode(lunaddrbytes))
2759 return 0; /* It's the logical targets that may lack lun 0. */
2760
4f4eb9f1
ST		 2761 if (!is_ext_target(h, tmpdevice))
2762 return 0; /* Only external target devices have this problem. */
edd16368 2763
1f310bde 2764 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2765 return 0;
2766
c4f8a299 2767 memset(scsi3addr, 0, 8);
1f310bde 2768 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2769 if (is_hba_lunid(scsi3addr))
2770 return 0; /* Don't add the RAID controller here. */
2771
339b2b14
SC		 2772 if (is_scsi_rev_5(h))
2773 return 0; /* p1210m doesn't need to do this. */
2774
4f4eb9f1 2775 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2776 dev_warn(&h->pdev->dev, "Maximum number of external "
2777 "target devices exceeded. Check your hardware "
edd16368
SC		 2778 "configuration.");
2779 return 0;
2780 }
2781
0b0e1d6c 2782 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2783 return 0;
4f4eb9f1 2784 (*n_ext_target_devs)++;
1f310bde
SC		 2785 hpsa_set_bus_target_lun(this_device,
2786 tmpdevice->bus, tmpdevice->target, 0);
2787 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2788 return 1;
2789}
2790
54b6e9e9
ST		 2791/*
2792 * Get address of physical disk used for an ioaccel2 mode command:
2793 * 1. Extract ioaccel2 handle from the command.
2794 * 2. Find a matching ioaccel2 handle from list of physical disks.
2795 * 3. Return:
2796 * 1 and set scsi3addr to address of matching physical
2797 * 0 if no matching physical disk was found.
2798 */
2799static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2800 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2801{
2802 struct ReportExtendedLUNdata *physicals = NULL;
2803 int responsesize = 24; /* size of physical extended response */
2804 int extended = 2; /* flag forces reporting 'other dev info'. */
2805 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2806 u32 nphysicals = 0; /* number of reported physical devs */
2807 int found = 0; /* found match (1) or not (0) */
2808 u32 find; /* handle we need to match */
2809 int i;
2810 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2811 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2812 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2813 u32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2814 u32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2815
2816 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2817 return 0; /* no match */
2818
2819 /* point to the ioaccel2 device handle */
2820 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2821 if (c2a == NULL)
2822 return 0; /* no match */
2823
2824 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2825 if (scmd == NULL)
2826 return 0; /* no match */
2827
2828 d = scmd->device->hostdata;
2829 if (d == NULL)
2830 return 0; /* no match */
2831
2832 it_nexus = cpu_to_le32((u32) d->ioaccel_handle);
2833 scsi_nexus = cpu_to_le32((u32) c2a->scsi_nexus);
2834 find = c2a->scsi_nexus;
2835
2ba8bfc8
SC		 2836 if (h->raid_offload_debug > 0)
2837 dev_info(&h->pdev->dev,
2838 "%s: scsi_nexus:0x%08x device id: 0x%02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x\n",
2839 __func__, scsi_nexus,
2840 d->device_id[0], d->device_id[1], d->device_id[2],
2841 d->device_id[3], d->device_id[4], d->device_id[5],
2842 d->device_id[6], d->device_id[7], d->device_id[8],
2843 d->device_id[9], d->device_id[10], d->device_id[11],
2844 d->device_id[12], d->device_id[13], d->device_id[14],
2845 d->device_id[15]);
2846
54b6e9e9
ST		 2847 /* Get the list of physical devices */
2848 physicals = kzalloc(reportsize, GFP_KERNEL);
3b51a7a3
JH		 2849 if (physicals == NULL)
2850 return 0;
54b6e9e9
ST		 2851 if (hpsa_scsi_do_report_phys_luns(h, (struct ReportLUNdata *) physicals,
2852 reportsize, extended)) {
2853 dev_err(&h->pdev->dev,
2854 "Can't lookup %s device handle: report physical LUNs failed.\n",
2855 "HP SSD Smart Path");
2856 kfree(physicals);
2857 return 0;
2858 }
2859 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2860 responsesize;
2861
54b6e9e9
ST		 2862 /* find ioaccel2 handle in list of physicals: */
2863 for (i = 0; i < nphysicals; i++) {
d5b5d964
SC		 2864 struct ext_report_lun_entry *entry = &physicals->LUN[i];
2865
54b6e9e9 2866 /* handle is in bytes 28-31 of each lun */
d5b5d964 2867 if (entry->ioaccel_handle != find)
54b6e9e9 2868 continue; /* didn't match */
54b6e9e9 2869 found = 1;
d5b5d964 2870 memcpy(scsi3addr, entry->lunid, 8);
2ba8bfc8
SC		 2871 if (h->raid_offload_debug > 0)
2872 dev_info(&h->pdev->dev,
d5b5d964 2873 "%s: Searched h=0x%08x, Found h=0x%08x, scsiaddr 0x%8phN\n",
2ba8bfc8 2874 __func__, find,
d5b5d964 2875 entry->ioaccel_handle, scsi3addr);
54b6e9e9
ST		 2876 break; /* found it */
2877 }
2878
2879 kfree(physicals);
2880 if (found)
2881 return 1;
2882 else
2883 return 0;
2884
2885}
edd16368
SC		 2886/*
2887 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2888 * logdev. The number of luns in physdev and logdev are returned in
2889 * *nphysicals and *nlogicals, respectively.
2890 * Returns 0 on success, -1 otherwise.
2891 */
2892static int hpsa_gather_lun_info(struct ctlr_info *h,
2893 int reportlunsize,
283b4a9b 2894 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2895 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2896{
283b4a9b
SC		 2897 int physical_entry_size = 8;
2898
2899 *physical_mode = 0;
2900
2901 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2902 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2903 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2904 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2905 physical_entry_size = 24;
2906 }
a93aa1fe 2907 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize,
283b4a9b 2908 *physical_mode)) {
edd16368
SC		 2909 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2910 return -1;
2911 }
283b4a9b
SC		 2912 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2913 physical_entry_size;
edd16368
SC		 2914 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2915 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2916 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2917 *nphysicals - HPSA_MAX_PHYS_LUN);
2918 *nphysicals = HPSA_MAX_PHYS_LUN;
2919 }
2920 if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
2921 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2922 return -1;
2923 }
6df1e954 2924 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2925 /* Reject Logicals in excess of our max capability. */
2926 if (*nlogicals > HPSA_MAX_LUN) {
2927 dev_warn(&h->pdev->dev,
2928 "maximum logical LUNs (%d) exceeded. "
2929 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2930 *nlogicals - HPSA_MAX_LUN);
2931 *nlogicals = HPSA_MAX_LUN;
2932 }
2933 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2934 dev_warn(&h->pdev->dev,
2935 "maximum logical + physical LUNs (%d) exceeded. "
2936 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2937 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2938 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2939 }
2940 return 0;
2941}
2942
339b2b14 2943u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
a93aa1fe
MG		 2944 int nphysicals, int nlogicals,
2945 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2946 struct ReportLUNdata *logdev_list)
2947{
2948 /* Helper function, figure out where the LUN ID info is coming from
2949 * given index i, lists of physical and logical devices, where in
2950 * the list the raid controller is supposed to appear (first or last)
2951 */
2952
2953 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2954 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2955
2956 if (i == raid_ctlr_position)
2957 return RAID_CTLR_LUNID;
2958
2959 if (i < logicals_start)
d5b5d964
SC		 2960 return &physdev_list->LUN[i -
2961 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 2962
2963 if (i < last_device)
2964 return &logdev_list->LUN[i - nphysicals -
2965 (raid_ctlr_position == 0)][0];
2966 BUG();
2967 return NULL;
2968}
2969
316b221a
SC		 2970static int hpsa_hba_mode_enabled(struct ctlr_info *h)
2971{
2972 int rc;
6e8e8088 2973 int hba_mode_enabled;
316b221a
SC		 2974 struct bmic_controller_parameters *ctlr_params;
2975 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
2976 GFP_KERNEL);
2977
2978 if (!ctlr_params)
96444fbb 2979 return -ENOMEM;
316b221a
SC		 2980 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
2981 sizeof(struct bmic_controller_parameters));
96444fbb 2982 if (rc) {
316b221a 2983 kfree(ctlr_params);
96444fbb 2984 return rc;
316b221a 2985 }
6e8e8088
JH		 2986
2987 hba_mode_enabled =
2988 ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0);
2989 kfree(ctlr_params);
2990 return hba_mode_enabled;
316b221a
SC		 2991}
2992
edd16368
SC		 2993static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2994{
2995 /* the idea here is we could get notified
2996 * that some devices have changed, so we do a report
2997 * physical luns and report logical luns cmd, and adjust
2998 * our list of devices accordingly.
2999 *
3000 * The scsi3addr's of devices won't change so long as the
3001 * adapter is not reset. That means we can rescan and
3002 * tell which devices we already know about, vs. new
3003 * devices, vs. disappearing devices.
3004 */
a93aa1fe 3005 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3006 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 3007 u32 nphysicals = 0;
3008 u32 nlogicals = 0;
283b4a9b 3009 int physical_mode = 0;
01a02ffc 3010 u32 ndev_allocated = 0;
edd16368
SC		 3011 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3012 int ncurrent = 0;
283b4a9b 3013 int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 24;
4f4eb9f1 3014 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3015 int raid_ctlr_position;
2bbf5c7f 3016 int rescan_hba_mode;
aca4a520 3017 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3018
cfe5badc 3019 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 3020 physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
3021 logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
edd16368
SC		 3022 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
3023
0b0e1d6c 3024 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 3025 dev_err(&h->pdev->dev, "out of memory\n");
3026 goto out;
3027 }
3028 memset(lunzerobits, 0, sizeof(lunzerobits));
3029
316b221a 3030 rescan_hba_mode = hpsa_hba_mode_enabled(h);
96444fbb
JH		 3031 if (rescan_hba_mode < 0)
3032 goto out;
316b221a
SC		 3033
3034 if (!h->hba_mode_enabled && rescan_hba_mode)
3035 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
3036 else if (h->hba_mode_enabled && !rescan_hba_mode)
3037 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
3038
3039 h->hba_mode_enabled = rescan_hba_mode;
3040
a93aa1fe
MG		 3041 if (hpsa_gather_lun_info(h, reportlunsize,
3042 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 3043 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 3044 goto out;
3045
aca4a520
ST		 3046 /* We might see up to the maximum number of logical and physical disks
3047 * plus external target devices, and a device for the local RAID
3048 * controller.
edd16368 3049 */
aca4a520 3050 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3051
3052 /* Allocate the per device structures */
3053 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3054 if (i >= HPSA_MAX_DEVICES) {
3055 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3056 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3057 ndevs_to_allocate - HPSA_MAX_DEVICES);
3058 break;
3059 }
3060
edd16368
SC		 3061 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3062 if (!currentsd[i]) {
3063 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3064 __FILE__, __LINE__);
3065 goto out;
3066 }
3067 ndev_allocated++;
3068 }
3069
8645291b 3070 if (is_scsi_rev_5(h))
339b2b14
SC		 3071 raid_ctlr_position = 0;
3072 else
3073 raid_ctlr_position = nphysicals + nlogicals;
3074
edd16368 3075 /* adjust our table of devices */
4f4eb9f1 3076 n_ext_target_devs = 0;
edd16368 3077 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3078 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3079
3080 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3081 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3082 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 3083 /* skip masked physical devices. */
339b2b14
SC		 3084 if (lunaddrbytes[3] & 0xC0 &&
3085 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 3086 continue;
3087
3088 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3089 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3090 &is_OBDR))
edd16368 3091 continue; /* skip it if we can't talk to it. */
1f310bde 3092 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 3093 this_device = currentsd[ncurrent];
3094
3095 /*
4f4eb9f1 3096 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3097 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3098 * is nonetheless an enclosure device there. We have to
3099 * present that otherwise linux won't find anything if
3100 * there is no lun 0.
3101 */
4f4eb9f1 3102 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3103 lunaddrbytes, lunzerobits,
4f4eb9f1 3104 &n_ext_target_devs)) {
edd16368
SC		 3105 ncurrent++;
3106 this_device = currentsd[ncurrent];
3107 }
3108
3109 *this_device = *tmpdevice;
edd16368
SC		 3110
3111 switch (this_device->devtype) {
0b0e1d6c 3112 case TYPE_ROM:
edd16368
SC		 3113 /* We don't *really* support actual CD-ROM devices,
3114 * just "One Button Disaster Recovery" tape drive
3115 * which temporarily pretends to be a CD-ROM drive.
3116 * So we check that the device is really an OBDR tape
3117 * device by checking for "$DR-10" in bytes 43-48 of
3118 * the inquiry data.
3119 */
0b0e1d6c
SC		 3120 if (is_OBDR)
3121 ncurrent++;
edd16368
SC		 3122 break;
3123 case TYPE_DISK:
316b221a
SC		 3124 if (h->hba_mode_enabled) {
3125 /* never use raid mapper in HBA mode */
3126 this_device->offload_enabled = 0;
3127 ncurrent++;
3128 break;
3129 } else if (h->acciopath_status) {
3130 if (i >= nphysicals) {
3131 ncurrent++;
3132 break;
3133 }
3134 } else {
3135 if (i < nphysicals)
3136 break;
283b4a9b 3137 ncurrent++;
edd16368 3138 break;
283b4a9b
SC		 3139 }
3140 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
3141 memcpy(&this_device->ioaccel_handle,
3142 &lunaddrbytes[20],
3143 sizeof(this_device->ioaccel_handle));
3144 ncurrent++;
3145 }
edd16368
SC		 3146 break;
3147 case TYPE_TAPE:
3148 case TYPE_MEDIUM_CHANGER:
3149 ncurrent++;
3150 break;
3151 case TYPE_RAID:
3152 /* Only present the Smartarray HBA as a RAID controller.
3153 * If it's a RAID controller other than the HBA itself
3154 * (an external RAID controller, MSA500 or similar)
3155 * don't present it.
3156 */
3157 if (!is_hba_lunid(lunaddrbytes))
3158 break;
3159 ncurrent++;
3160 break;
3161 default:
3162 break;
3163 }
cfe5badc 3164 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3165 break;
3166 }
3167 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3168out:
3169 kfree(tmpdevice);
3170 for (i = 0; i < ndev_allocated; i++)
3171 kfree(currentsd[i]);
3172 kfree(currentsd);
edd16368
SC		 3173 kfree(physdev_list);
3174 kfree(logdev_list);
edd16368
SC		 3175}
3176
3177/* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
3178 * dma mapping and fills in the scatter gather entries of the
3179 * hpsa command, cp.
3180 */
33a2ffce 3181static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3182 struct CommandList *cp,
3183 struct scsi_cmnd *cmd)
3184{
3185 unsigned int len;
3186 struct scatterlist *sg;
01a02ffc 3187 u64 addr64;
33a2ffce
SC		 3188 int use_sg, i, sg_index, chained;
3189 struct SGDescriptor *curr_sg;
edd16368 3190
33a2ffce 3191 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3192
3193 use_sg = scsi_dma_map(cmd);
3194 if (use_sg < 0)
3195 return use_sg;
3196
3197 if (!use_sg)
3198 goto sglist_finished;
3199
33a2ffce
SC		 3200 curr_sg = cp->SG;
3201 chained = 0;
3202 sg_index = 0;
edd16368 3203 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 3204 if (i == h->max_cmd_sg_entries - 1 &&
3205 use_sg > h->max_cmd_sg_entries) {
3206 chained = 1;
3207 curr_sg = h->cmd_sg_list[cp->cmdindex];
3208 sg_index = 0;
3209 }
01a02ffc 3210 addr64 = (u64) sg_dma_address(sg);
edd16368 3211 len = sg_dma_len(sg);
33a2ffce
SC		 3212 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
3213 curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
3214 curr_sg->Len = len;
e1d9cbfa 3215 curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST;
33a2ffce
SC		 3216 curr_sg++;
3217 }
3218
3219 if (use_sg + chained > h->maxSG)
3220 h->maxSG = use_sg + chained;
3221
3222 if (chained) {
3223 cp->Header.SGList = h->max_cmd_sg_entries;
3224 cp->Header.SGTotal = (u16) (use_sg + 1);
e2bea6df
SC		 3225 if (hpsa_map_sg_chain_block(h, cp)) {
3226 scsi_dma_unmap(cmd);
3227 return -1;
3228 }
33a2ffce 3229 return 0;
edd16368
SC		 3230 }
3231
3232sglist_finished:
3233
01a02ffc
SC		 3234 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
3235 cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
edd16368
SC		 3236 return 0;
3237}
3238
283b4a9b
SC		 3239#define IO_ACCEL_INELIGIBLE (1)
3240static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3241{
3242 int is_write = 0;
3243 u32 block;
3244 u32 block_cnt;
3245
3246 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3247 switch (cdb[0]) {
3248 case WRITE_6:
3249 case WRITE_12:
3250 is_write = 1;
3251 case READ_6:
3252 case READ_12:
3253 if (*cdb_len == 6) {
3254 block = (((u32) cdb[2]) << 8) | cdb[3];
3255 block_cnt = cdb[4];
3256 } else {
3257 BUG_ON(*cdb_len != 12);
3258 block = (((u32) cdb[2]) << 24) |
3259 (((u32) cdb[3]) << 16) |
3260 (((u32) cdb[4]) << 8) |
3261 cdb[5];
3262 block_cnt =
3263 (((u32) cdb[6]) << 24) |
3264 (((u32) cdb[7]) << 16) |
3265 (((u32) cdb[8]) << 8) |
3266 cdb[9];
3267 }
3268 if (block_cnt > 0xffff)
3269 return IO_ACCEL_INELIGIBLE;
3270
3271 cdb[0] = is_write ? WRITE_10 : READ_10;
3272 cdb[1] = 0;
3273 cdb[2] = (u8) (block >> 24);
3274 cdb[3] = (u8) (block >> 16);
3275 cdb[4] = (u8) (block >> 8);
3276 cdb[5] = (u8) (block);
3277 cdb[6] = 0;
3278 cdb[7] = (u8) (block_cnt >> 8);
3279 cdb[8] = (u8) (block_cnt);
3280 cdb[9] = 0;
3281 *cdb_len = 10;
3282 break;
3283 }
3284 return 0;
3285}
3286
c349775e 3287static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 3288 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3289 u8 *scsi3addr)
e1f7de0c
MG		 3290{
3291 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3292 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3293 unsigned int len;
3294 unsigned int total_len = 0;
3295 struct scatterlist *sg;
3296 u64 addr64;
3297 int use_sg, i;
3298 struct SGDescriptor *curr_sg;
3299 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3300
283b4a9b
SC		 3301 /* TODO: implement chaining support */
3302 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3303 return IO_ACCEL_INELIGIBLE;
3304
e1f7de0c
MG		 3305 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3306
283b4a9b
SC		 3307 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3308 return IO_ACCEL_INELIGIBLE;
3309
e1f7de0c
MG		 3310 c->cmd_type = CMD_IOACCEL1;
3311
3312 /* Adjust the DMA address to point to the accelerated command buffer */
3313 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3314 (c->cmdindex * sizeof(*cp));
3315 BUG_ON(c->busaddr & 0x0000007F);
3316
3317 use_sg = scsi_dma_map(cmd);
3318 if (use_sg < 0)
3319 return use_sg;
3320
3321 if (use_sg) {
3322 curr_sg = cp->SG;
3323 scsi_for_each_sg(cmd, sg, use_sg, i) {
3324 addr64 = (u64) sg_dma_address(sg);
3325 len = sg_dma_len(sg);
3326 total_len += len;
3327 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
3328 curr_sg->Addr.upper =
3329 (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
3330 curr_sg->Len = len;
3331
3332 if (i == (scsi_sg_count(cmd) - 1))
3333 curr_sg->Ext = HPSA_SG_LAST;
3334 else
3335 curr_sg->Ext = 0; /* we are not chaining */
3336 curr_sg++;
3337 }
3338
3339 switch (cmd->sc_data_direction) {
3340 case DMA_TO_DEVICE:
3341 control |= IOACCEL1_CONTROL_DATA_OUT;
3342 break;
3343 case DMA_FROM_DEVICE:
3344 control |= IOACCEL1_CONTROL_DATA_IN;
3345 break;
3346 case DMA_NONE:
3347 control |= IOACCEL1_CONTROL_NODATAXFER;
3348 break;
3349 default:
3350 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3351 cmd->sc_data_direction);
3352 BUG();
3353 break;
3354 }
3355 } else {
3356 control |= IOACCEL1_CONTROL_NODATAXFER;
3357 }
3358
c349775e 3359 c->Header.SGList = use_sg;
e1f7de0c 3360 /* Fill out the command structure to submit */
283b4a9b 3361 cp->dev_handle = ioaccel_handle & 0xFFFF;
e1f7de0c
MG		 3362 cp->transfer_len = total_len;
3363 cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ |
283b4a9b 3364 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK);
e1f7de0c 3365 cp->control = control;
283b4a9b
SC		 3366 memcpy(cp->CDB, cdb, cdb_len);
3367 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3368 /* Tag was already set at init time. */
283b4a9b 3369 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3370 return 0;
3371}
edd16368 3372
283b4a9b
SC		 3373/*
3374 * Queue a command directly to a device behind the controller using the
3375 * I/O accelerator path.
3376 */
3377static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3378 struct CommandList *c)
3379{
3380 struct scsi_cmnd *cmd = c->scsi_cmd;
3381 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3382
3383 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
3384 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
3385}
3386
dd0e19f3
ST		 3387/*
3388 * Set encryption parameters for the ioaccel2 request
3389 */
3390static void set_encrypt_ioaccel2(struct ctlr_info *h,
3391 struct CommandList *c, struct io_accel2_cmd *cp)
3392{
3393 struct scsi_cmnd *cmd = c->scsi_cmd;
3394 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3395 struct raid_map_data *map = &dev->raid_map;
3396 u64 first_block;
3397
3398 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3399
3400 /* Are we doing encryption on this device */
3401 if (!(map->flags & RAID_MAP_FLAG_ENCRYPT_ON))
3402 return;
3403 /* Set the data encryption key index. */
3404 cp->dekindex = map->dekindex;
3405
3406 /* Set the encryption enable flag, encoded into direction field. */
3407 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3408
3409 /* Set encryption tweak values based on logical block address
3410 * If block size is 512, tweak value is LBA.
3411 * For other block sizes, tweak is (LBA * block size)/ 512)
3412 */
3413 switch (cmd->cmnd[0]) {
3414 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3415 case WRITE_6:
3416 case READ_6:
3417 if (map->volume_blk_size == 512) {
3418 cp->tweak_lower =
3419 (((u32) cmd->cmnd[2]) << 8) |
3420 cmd->cmnd[3];
3421 cp->tweak_upper = 0;
3422 } else {
3423 first_block =
3424 (((u64) cmd->cmnd[2]) << 8) |
3425 cmd->cmnd[3];
3426 first_block = (first_block * map->volume_blk_size)/512;
3427 cp->tweak_lower = (u32)first_block;
3428 cp->tweak_upper = (u32)(first_block >> 32);
3429 }
3430 break;
3431 case WRITE_10:
3432 case READ_10:
3433 if (map->volume_blk_size == 512) {
3434 cp->tweak_lower =
3435 (((u32) cmd->cmnd[2]) << 24) |
3436 (((u32) cmd->cmnd[3]) << 16) |
3437 (((u32) cmd->cmnd[4]) << 8) |
3438 cmd->cmnd[5];
3439 cp->tweak_upper = 0;
3440 } else {
3441 first_block =
3442 (((u64) cmd->cmnd[2]) << 24) |
3443 (((u64) cmd->cmnd[3]) << 16) |
3444 (((u64) cmd->cmnd[4]) << 8) |
3445 cmd->cmnd[5];
3446 first_block = (first_block * map->volume_blk_size)/512;
3447 cp->tweak_lower = (u32)first_block;
3448 cp->tweak_upper = (u32)(first_block >> 32);
3449 }
3450 break;
3451 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3452 case WRITE_12:
3453 case READ_12:
3454 if (map->volume_blk_size == 512) {
3455 cp->tweak_lower =
3456 (((u32) cmd->cmnd[2]) << 24) |
3457 (((u32) cmd->cmnd[3]) << 16) |
3458 (((u32) cmd->cmnd[4]) << 8) |
3459 cmd->cmnd[5];
3460 cp->tweak_upper = 0;
3461 } else {
3462 first_block =
3463 (((u64) cmd->cmnd[2]) << 24) |
3464 (((u64) cmd->cmnd[3]) << 16) |
3465 (((u64) cmd->cmnd[4]) << 8) |
3466 cmd->cmnd[5];
3467 first_block = (first_block * map->volume_blk_size)/512;
3468 cp->tweak_lower = (u32)first_block;
3469 cp->tweak_upper = (u32)(first_block >> 32);
3470 }
3471 break;
3472 case WRITE_16:
3473 case READ_16:
3474 if (map->volume_blk_size == 512) {
3475 cp->tweak_lower =
3476 (((u32) cmd->cmnd[6]) << 24) |
3477 (((u32) cmd->cmnd[7]) << 16) |
3478 (((u32) cmd->cmnd[8]) << 8) |
3479 cmd->cmnd[9];
3480 cp->tweak_upper =
3481 (((u32) cmd->cmnd[2]) << 24) |
3482 (((u32) cmd->cmnd[3]) << 16) |
3483 (((u32) cmd->cmnd[4]) << 8) |
3484 cmd->cmnd[5];
3485 } else {
3486 first_block =
3487 (((u64) cmd->cmnd[2]) << 56) |
3488 (((u64) cmd->cmnd[3]) << 48) |
3489 (((u64) cmd->cmnd[4]) << 40) |
3490 (((u64) cmd->cmnd[5]) << 32) |
3491 (((u64) cmd->cmnd[6]) << 24) |
3492 (((u64) cmd->cmnd[7]) << 16) |
3493 (((u64) cmd->cmnd[8]) << 8) |
3494 cmd->cmnd[9];
3495 first_block = (first_block * map->volume_blk_size)/512;
3496 cp->tweak_lower = (u32)first_block;
3497 cp->tweak_upper = (u32)(first_block >> 32);
3498 }
3499 break;
3500 default:
3501 dev_err(&h->pdev->dev,
3502 "ERROR: %s: IOACCEL request CDB size not supported for encryption\n",
3503 __func__);
3504 BUG();
3505 break;
3506 }
3507}
3508
c349775e
ST		 3509static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3510 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3511 u8 *scsi3addr)
3512{
3513 struct scsi_cmnd *cmd = c->scsi_cmd;
3514 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3515 struct ioaccel2_sg_element *curr_sg;
3516 int use_sg, i;
3517 struct scatterlist *sg;
3518 u64 addr64;
3519 u32 len;
3520 u32 total_len = 0;
3521
3522 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3523 return IO_ACCEL_INELIGIBLE;
3524
3525 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3526 return IO_ACCEL_INELIGIBLE;
3527 c->cmd_type = CMD_IOACCEL2;
3528 /* Adjust the DMA address to point to the accelerated command buffer */
3529 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3530 (c->cmdindex * sizeof(*cp));
3531 BUG_ON(c->busaddr & 0x0000007F);
3532
3533 memset(cp, 0, sizeof(*cp));
3534 cp->IU_type = IOACCEL2_IU_TYPE;
3535
3536 use_sg = scsi_dma_map(cmd);
3537 if (use_sg < 0)
3538 return use_sg;
3539
3540 if (use_sg) {
3541 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
3542 curr_sg = cp->sg;
3543 scsi_for_each_sg(cmd, sg, use_sg, i) {
3544 addr64 = (u64) sg_dma_address(sg);
3545 len = sg_dma_len(sg);
3546 total_len += len;
3547 curr_sg->address = cpu_to_le64(addr64);
3548 curr_sg->length = cpu_to_le32(len);
3549 curr_sg->reserved[0] = 0;
3550 curr_sg->reserved[1] = 0;
3551 curr_sg->reserved[2] = 0;
3552 curr_sg->chain_indicator = 0;
3553 curr_sg++;
3554 }
3555
3556 switch (cmd->sc_data_direction) {
3557 case DMA_TO_DEVICE:
dd0e19f3
ST		 3558 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3559 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3560 break;
3561 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3562 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3563 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3564 break;
3565 case DMA_NONE:
dd0e19f3
ST		 3566 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3567 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3568 break;
3569 default:
3570 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3571 cmd->sc_data_direction);
3572 BUG();
3573 break;
3574 }
3575 } else {
dd0e19f3
ST		 3576 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3577 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3578 }
dd0e19f3
ST		 3579
3580 /* Set encryption parameters, if necessary */
3581 set_encrypt_ioaccel2(h, c, cp);
3582
c349775e 3583 cp->scsi_nexus = ioaccel_handle;
dd0e19f3 3584 cp->Tag = (c->cmdindex << DIRECT_LOOKUP_SHIFT) |
c349775e
ST		 3585 DIRECT_LOOKUP_BIT;
3586 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e
ST		 3587
3588 /* fill in sg elements */
3589 cp->sg_count = (u8) use_sg;
3590
3591 cp->data_len = cpu_to_le32(total_len);
3592 cp->err_ptr = cpu_to_le64(c->busaddr +
3593 offsetof(struct io_accel2_cmd, error_data));
3594 cp->err_len = cpu_to_le32((u32) sizeof(cp->error_data));
3595
3596 enqueue_cmd_and_start_io(h, c);
3597 return 0;
3598}
3599
3600/*
3601 * Queue a command to the correct I/O accelerator path.
3602 */
3603static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3604 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3605 u8 *scsi3addr)
3606{
3607 if (h->transMethod & CFGTBL_Trans_io_accel1)
3608 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
3609 cdb, cdb_len, scsi3addr);
3610 else
3611 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
3612 cdb, cdb_len, scsi3addr);
3613}
3614
6b80b18f
ST		 3615static void raid_map_helper(struct raid_map_data *map,
3616 int offload_to_mirror, u32 *map_index, u32 *current_group)
3617{
3618 if (offload_to_mirror == 0) {
3619 /* use physical disk in the first mirrored group. */
3620 *map_index %= map->data_disks_per_row;
3621 return;
3622 }
3623 do {
3624 /* determine mirror group that *map_index indicates */
3625 *current_group = *map_index / map->data_disks_per_row;
3626 if (offload_to_mirror == *current_group)
3627 continue;
3628 if (*current_group < (map->layout_map_count - 1)) {
3629 /* select map index from next group */
3630 *map_index += map->data_disks_per_row;
3631 (*current_group)++;
3632 } else {
3633 /* select map index from first group */
3634 *map_index %= map->data_disks_per_row;
3635 *current_group = 0;
3636 }
3637 } while (offload_to_mirror != *current_group);
3638}
3639
283b4a9b
SC		 3640/*
3641 * Attempt to perform offload RAID mapping for a logical volume I/O.
3642 */
3643static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3644 struct CommandList *c)
3645{
3646 struct scsi_cmnd *cmd = c->scsi_cmd;
3647 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3648 struct raid_map_data *map = &dev->raid_map;
3649 struct raid_map_disk_data *dd = &map->data[0];
3650 int is_write = 0;
3651 u32 map_index;
3652 u64 first_block, last_block;
3653 u32 block_cnt;
3654 u32 blocks_per_row;
3655 u64 first_row, last_row;
3656 u32 first_row_offset, last_row_offset;
3657 u32 first_column, last_column;
6b80b18f
ST		 3658 u64 r0_first_row, r0_last_row;
3659 u32 r5or6_blocks_per_row;
3660 u64 r5or6_first_row, r5or6_last_row;
3661 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3662 u32 r5or6_first_column, r5or6_last_column;
3663 u32 total_disks_per_row;
3664 u32 stripesize;
3665 u32 first_group, last_group, current_group;
283b4a9b
SC		 3666 u32 map_row;
3667 u32 disk_handle;
3668 u64 disk_block;
3669 u32 disk_block_cnt;
3670 u8 cdb[16];
3671 u8 cdb_len;
3672#if BITS_PER_LONG == 32
3673 u64 tmpdiv;
3674#endif
6b80b18f 3675 int offload_to_mirror;
283b4a9b
SC		 3676
3677 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3678
3679 /* check for valid opcode, get LBA and block count */
3680 switch (cmd->cmnd[0]) {
3681 case WRITE_6:
3682 is_write = 1;
3683 case READ_6:
3684 first_block =
3685 (((u64) cmd->cmnd[2]) << 8) |
3686 cmd->cmnd[3];
3687 block_cnt = cmd->cmnd[4];
3688 break;
3689 case WRITE_10:
3690 is_write = 1;
3691 case READ_10:
3692 first_block =
3693 (((u64) cmd->cmnd[2]) << 24) |
3694 (((u64) cmd->cmnd[3]) << 16) |
3695 (((u64) cmd->cmnd[4]) << 8) |
3696 cmd->cmnd[5];
3697 block_cnt =
3698 (((u32) cmd->cmnd[7]) << 8) |
3699 cmd->cmnd[8];
3700 break;
3701 case WRITE_12:
3702 is_write = 1;
3703 case READ_12:
3704 first_block =
3705 (((u64) cmd->cmnd[2]) << 24) |
3706 (((u64) cmd->cmnd[3]) << 16) |
3707 (((u64) cmd->cmnd[4]) << 8) |
3708 cmd->cmnd[5];
3709 block_cnt =
3710 (((u32) cmd->cmnd[6]) << 24) |
3711 (((u32) cmd->cmnd[7]) << 16) |
3712 (((u32) cmd->cmnd[8]) << 8) |
3713 cmd->cmnd[9];
3714 break;
3715 case WRITE_16:
3716 is_write = 1;
3717 case READ_16:
3718 first_block =
3719 (((u64) cmd->cmnd[2]) << 56) |
3720 (((u64) cmd->cmnd[3]) << 48) |
3721 (((u64) cmd->cmnd[4]) << 40) |
3722 (((u64) cmd->cmnd[5]) << 32) |
3723 (((u64) cmd->cmnd[6]) << 24) |
3724 (((u64) cmd->cmnd[7]) << 16) |
3725 (((u64) cmd->cmnd[8]) << 8) |
3726 cmd->cmnd[9];
3727 block_cnt =
3728 (((u32) cmd->cmnd[10]) << 24) |
3729 (((u32) cmd->cmnd[11]) << 16) |
3730 (((u32) cmd->cmnd[12]) << 8) |
3731 cmd->cmnd[13];
3732 break;
3733 default:
3734 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3735 }
3736 BUG_ON(block_cnt == 0);
3737 last_block = first_block + block_cnt - 1;
3738
3739 /* check for write to non-RAID-0 */
3740 if (is_write && dev->raid_level != 0)
3741 return IO_ACCEL_INELIGIBLE;
3742
3743 /* check for invalid block or wraparound */
3744 if (last_block >= map->volume_blk_cnt || last_block < first_block)
3745 return IO_ACCEL_INELIGIBLE;
3746
3747 /* calculate stripe information for the request */
3748 blocks_per_row = map->data_disks_per_row * map->strip_size;
3749#if BITS_PER_LONG == 32
3750 tmpdiv = first_block;
3751 (void) do_div(tmpdiv, blocks_per_row);
3752 first_row = tmpdiv;
3753 tmpdiv = last_block;
3754 (void) do_div(tmpdiv, blocks_per_row);
3755 last_row = tmpdiv;
3756 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3757 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3758 tmpdiv = first_row_offset;
3759 (void) do_div(tmpdiv, map->strip_size);
3760 first_column = tmpdiv;
3761 tmpdiv = last_row_offset;
3762 (void) do_div(tmpdiv, map->strip_size);
3763 last_column = tmpdiv;
3764#else
3765 first_row = first_block / blocks_per_row;
3766 last_row = last_block / blocks_per_row;
3767 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3768 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3769 first_column = first_row_offset / map->strip_size;
3770 last_column = last_row_offset / map->strip_size;
3771#endif
3772
3773 /* if this isn't a single row/column then give to the controller */
3774 if ((first_row != last_row) || (first_column != last_column))
3775 return IO_ACCEL_INELIGIBLE;
3776
3777 /* proceeding with driver mapping */
6b80b18f
ST		 3778 total_disks_per_row = map->data_disks_per_row +
3779 map->metadata_disks_per_row;
283b4a9b
SC		 3780 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3781 map->row_cnt;
6b80b18f
ST		 3782 map_index = (map_row * total_disks_per_row) + first_column;
3783
3784 switch (dev->raid_level) {
3785 case HPSA_RAID_0:
3786 break; /* nothing special to do */
3787 case HPSA_RAID_1:
3788 /* Handles load balance across RAID 1 members.
3789 * (2-drive R1 and R10 with even # of drives.)
3790 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 3791 */
6b80b18f 3792 BUG_ON(map->layout_map_count != 2);
283b4a9b
SC		 3793 if (dev->offload_to_mirror)
3794 map_index += map->data_disks_per_row;
3795 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 3796 break;
3797 case HPSA_RAID_ADM:
3798 /* Handles N-way mirrors (R1-ADM)
3799 * and R10 with # of drives divisible by 3.)
3800 */
3801 BUG_ON(map->layout_map_count != 3);
3802
3803 offload_to_mirror = dev->offload_to_mirror;
3804 raid_map_helper(map, offload_to_mirror,
3805 &map_index, &current_group);
3806 /* set mirror group to use next time */
3807 offload_to_mirror =
3808 (offload_to_mirror >= map->layout_map_count - 1)
3809 ? 0 : offload_to_mirror + 1;
3810 /* FIXME: remove after debug/dev */
3811 BUG_ON(offload_to_mirror >= map->layout_map_count);
3812 dev_warn(&h->pdev->dev,
3813 "DEBUG: Using physical disk map index %d from mirror group %d\n",
3814 map_index, offload_to_mirror);
3815 dev->offload_to_mirror = offload_to_mirror;
3816 /* Avoid direct use of dev->offload_to_mirror within this
3817 * function since multiple threads might simultaneously
3818 * increment it beyond the range of dev->layout_map_count -1.
3819 */
3820 break;
3821 case HPSA_RAID_5:
3822 case HPSA_RAID_6:
3823 if (map->layout_map_count <= 1)
3824 break;
3825
3826 /* Verify first and last block are in same RAID group */
3827 r5or6_blocks_per_row =
3828 map->strip_size * map->data_disks_per_row;
3829 BUG_ON(r5or6_blocks_per_row == 0);
3830 stripesize = r5or6_blocks_per_row * map->layout_map_count;
3831#if BITS_PER_LONG == 32
3832 tmpdiv = first_block;
3833 first_group = do_div(tmpdiv, stripesize);
3834 tmpdiv = first_group;
3835 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3836 first_group = tmpdiv;
3837 tmpdiv = last_block;
3838 last_group = do_div(tmpdiv, stripesize);
3839 tmpdiv = last_group;
3840 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3841 last_group = tmpdiv;
3842#else
3843 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
3844 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 3845#endif
000ff7c2 3846 if (first_group != last_group)
6b80b18f
ST		 3847 return IO_ACCEL_INELIGIBLE;
3848
3849 /* Verify request is in a single row of RAID 5/6 */
3850#if BITS_PER_LONG == 32
3851 tmpdiv = first_block;
3852 (void) do_div(tmpdiv, stripesize);
3853 first_row = r5or6_first_row = r0_first_row = tmpdiv;
3854 tmpdiv = last_block;
3855 (void) do_div(tmpdiv, stripesize);
3856 r5or6_last_row = r0_last_row = tmpdiv;
3857#else
3858 first_row = r5or6_first_row = r0_first_row =
3859 first_block / stripesize;
3860 r5or6_last_row = r0_last_row = last_block / stripesize;
3861#endif
3862 if (r5or6_first_row != r5or6_last_row)
3863 return IO_ACCEL_INELIGIBLE;
3864
3865
3866 /* Verify request is in a single column */
3867#if BITS_PER_LONG == 32
3868 tmpdiv = first_block;
3869 first_row_offset = do_div(tmpdiv, stripesize);
3870 tmpdiv = first_row_offset;
3871 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
3872 r5or6_first_row_offset = first_row_offset;
3873 tmpdiv = last_block;
3874 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
3875 tmpdiv = r5or6_last_row_offset;
3876 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
3877 tmpdiv = r5or6_first_row_offset;
3878 (void) do_div(tmpdiv, map->strip_size);
3879 first_column = r5or6_first_column = tmpdiv;
3880 tmpdiv = r5or6_last_row_offset;
3881 (void) do_div(tmpdiv, map->strip_size);
3882 r5or6_last_column = tmpdiv;
3883#else
3884 first_row_offset = r5or6_first_row_offset =
3885 (u32)((first_block % stripesize) %
3886 r5or6_blocks_per_row);
3887
3888 r5or6_last_row_offset =
3889 (u32)((last_block % stripesize) %
3890 r5or6_blocks_per_row);
3891
3892 first_column = r5or6_first_column =
3893 r5or6_first_row_offset / map->strip_size;
3894 r5or6_last_column =
3895 r5or6_last_row_offset / map->strip_size;
3896#endif
3897 if (r5or6_first_column != r5or6_last_column)
3898 return IO_ACCEL_INELIGIBLE;
3899
3900 /* Request is eligible */
3901 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3902 map->row_cnt;
3903
3904 map_index = (first_group *
3905 (map->row_cnt * total_disks_per_row)) +
3906 (map_row * total_disks_per_row) + first_column;
3907 break;
3908 default:
3909 return IO_ACCEL_INELIGIBLE;
283b4a9b 3910 }
6b80b18f 3911
283b4a9b
SC		 3912 disk_handle = dd[map_index].ioaccel_handle;
3913 disk_block = map->disk_starting_blk + (first_row * map->strip_size) +
3914 (first_row_offset - (first_column * map->strip_size));
3915 disk_block_cnt = block_cnt;
3916
3917 /* handle differing logical/physical block sizes */
3918 if (map->phys_blk_shift) {
3919 disk_block <<= map->phys_blk_shift;
3920 disk_block_cnt <<= map->phys_blk_shift;
3921 }
3922 BUG_ON(disk_block_cnt > 0xffff);
3923
3924 /* build the new CDB for the physical disk I/O */
3925 if (disk_block > 0xffffffff) {
3926 cdb[0] = is_write ? WRITE_16 : READ_16;
3927 cdb[1] = 0;
3928 cdb[2] = (u8) (disk_block >> 56);
3929 cdb[3] = (u8) (disk_block >> 48);
3930 cdb[4] = (u8) (disk_block >> 40);
3931 cdb[5] = (u8) (disk_block >> 32);
3932 cdb[6] = (u8) (disk_block >> 24);
3933 cdb[7] = (u8) (disk_block >> 16);
3934 cdb[8] = (u8) (disk_block >> 8);
3935 cdb[9] = (u8) (disk_block);
3936 cdb[10] = (u8) (disk_block_cnt >> 24);
3937 cdb[11] = (u8) (disk_block_cnt >> 16);
3938 cdb[12] = (u8) (disk_block_cnt >> 8);
3939 cdb[13] = (u8) (disk_block_cnt);
3940 cdb[14] = 0;
3941 cdb[15] = 0;
3942 cdb_len = 16;
3943 } else {
3944 cdb[0] = is_write ? WRITE_10 : READ_10;
3945 cdb[1] = 0;
3946 cdb[2] = (u8) (disk_block >> 24);
3947 cdb[3] = (u8) (disk_block >> 16);
3948 cdb[4] = (u8) (disk_block >> 8);
3949 cdb[5] = (u8) (disk_block);
3950 cdb[6] = 0;
3951 cdb[7] = (u8) (disk_block_cnt >> 8);
3952 cdb[8] = (u8) (disk_block_cnt);
3953 cdb[9] = 0;
3954 cdb_len = 10;
3955 }
3956 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3957 dev->scsi3addr);
3958}
3959
f281233d 3960static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
edd16368
SC		 3961 void (*done)(struct scsi_cmnd *))
3962{
3963 struct ctlr_info *h;
3964 struct hpsa_scsi_dev_t *dev;
3965 unsigned char scsi3addr[8];
3966 struct CommandList *c;
283b4a9b 3967 int rc = 0;
edd16368
SC		 3968
3969 /* Get the ptr to our adapter structure out of cmd->host. */
3970 h = sdev_to_hba(cmd->device);
3971 dev = cmd->device->hostdata;
3972 if (!dev) {
3973 cmd->result = DID_NO_CONNECT << 16;
3974 done(cmd);
3975 return 0;
3976 }
3977 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3978
094963da 3979 if (unlikely(lockup_detected(h))) {
a0c12413
SC		 3980 cmd->result = DID_ERROR << 16;
3981 done(cmd);
3982 return 0;
3983 }
e16a33ad 3984 c = cmd_alloc(h);
edd16368
SC		 3985 if (c == NULL) { /* trouble... */
3986 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
3987 return SCSI_MLQUEUE_HOST_BUSY;
3988 }
3989
3990 /* Fill in the command list header */
3991
3992 cmd->scsi_done = done; /* save this for use by completion code */
3993
3994 /* save c in case we have to abort it */
3995 cmd->host_scribble = (unsigned char *) c;
3996
3997 c->cmd_type = CMD_SCSI;
3998 c->scsi_cmd = cmd;
e1f7de0c 3999
283b4a9b
SC		 4000 /* Call alternate submit routine for I/O accelerated commands.
4001 * Retries always go down the normal I/O path.
4002 */
4003 if (likely(cmd->retries == 0 &&
da0697bd
ST		 4004 cmd->request->cmd_type == REQ_TYPE_FS &&
4005 h->acciopath_status)) {
283b4a9b
SC		 4006 if (dev->offload_enabled) {
4007 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4008 if (rc == 0)
4009 return 0; /* Sent on ioaccel path */
4010 if (rc < 0) { /* scsi_dma_map failed. */
4011 cmd_free(h, c);
4012 return SCSI_MLQUEUE_HOST_BUSY;
4013 }
4014 } else if (dev->ioaccel_handle) {
4015 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4016 if (rc == 0)
4017 return 0; /* Sent on direct map path */
4018 if (rc < 0) { /* scsi_dma_map failed. */
4019 cmd_free(h, c);
4020 return SCSI_MLQUEUE_HOST_BUSY;
4021 }
4022 }
4023 }
e1f7de0c 4024
edd16368
SC		 4025 c->Header.ReplyQueue = 0; /* unused in simple mode */
4026 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
303932fd
DB		 4027 c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
4028 c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
edd16368
SC		 4029
4030 /* Fill in the request block... */
4031
4032 c->Request.Timeout = 0;
4033 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4034 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4035 c->Request.CDBLen = cmd->cmd_len;
4036 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
4037 c->Request.Type.Type = TYPE_CMD;
4038 c->Request.Type.Attribute = ATTR_SIMPLE;
4039 switch (cmd->sc_data_direction) {
4040 case DMA_TO_DEVICE:
4041 c->Request.Type.Direction = XFER_WRITE;
4042 break;
4043 case DMA_FROM_DEVICE:
4044 c->Request.Type.Direction = XFER_READ;
4045 break;
4046 case DMA_NONE:
4047 c->Request.Type.Direction = XFER_NONE;
4048 break;
4049 case DMA_BIDIRECTIONAL:
4050 /* This can happen if a buggy application does a scsi passthru
4051 * and sets both inlen and outlen to non-zero. ( see
4052 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4053 */
4054
4055 c->Request.Type.Direction = XFER_RSVD;
4056 /* This is technically wrong, and hpsa controllers should
4057 * reject it with CMD_INVALID, which is the most correct
4058 * response, but non-fibre backends appear to let it
4059 * slide by, and give the same results as if this field
4060 * were set correctly. Either way is acceptable for
4061 * our purposes here.
4062 */
4063
4064 break;
4065
4066 default:
4067 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4068 cmd->sc_data_direction);
4069 BUG();
4070 break;
4071 }
4072
33a2ffce 4073 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 4074 cmd_free(h, c);
4075 return SCSI_MLQUEUE_HOST_BUSY;
4076 }
4077 enqueue_cmd_and_start_io(h, c);
4078 /* the cmd'll come back via intr handler in complete_scsi_command() */
4079 return 0;
4080}
4081
f281233d
JG		 4082static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
4083
5f389360
SC		 4084static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
4085{
4086 unsigned long flags;
4087
4088 /*
4089 * Don't let rescans be initiated on a controller known
4090 * to be locked up. If the controller locks up *during*
4091 * a rescan, that thread is probably hosed, but at least
4092 * we can prevent new rescan threads from piling up on a
4093 * locked up controller.
4094 */
094963da 4095 if (unlikely(lockup_detected(h))) {
5f389360
SC		 4096 spin_lock_irqsave(&h->scan_lock, flags);
4097 h->scan_finished = 1;
4098 wake_up_all(&h->scan_wait_queue);
4099 spin_unlock_irqrestore(&h->scan_lock, flags);
4100 return 1;
4101 }
5f389360
SC		 4102 return 0;
4103}
4104
a08a8471
SC		 4105static void hpsa_scan_start(struct Scsi_Host *sh)
4106{
4107 struct ctlr_info *h = shost_to_hba(sh);
4108 unsigned long flags;
4109
5f389360
SC		 4110 if (do_not_scan_if_controller_locked_up(h))
4111 return;
4112
a08a8471
SC		 4113 /* wait until any scan already in progress is finished. */
4114 while (1) {
4115 spin_lock_irqsave(&h->scan_lock, flags);
4116 if (h->scan_finished)
4117 break;
4118 spin_unlock_irqrestore(&h->scan_lock, flags);
4119 wait_event(h->scan_wait_queue, h->scan_finished);
4120 /* Note: We don't need to worry about a race between this
4121 * thread and driver unload because the midlayer will
4122 * have incremented the reference count, so unload won't
4123 * happen if we're in here.
4124 */
4125 }
4126 h->scan_finished = 0; /* mark scan as in progress */
4127 spin_unlock_irqrestore(&h->scan_lock, flags);
4128
5f389360
SC		 4129 if (do_not_scan_if_controller_locked_up(h))
4130 return;
4131
a08a8471
SC		 4132 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4133
4134 spin_lock_irqsave(&h->scan_lock, flags);
4135 h->scan_finished = 1; /* mark scan as finished. */
4136 wake_up_all(&h->scan_wait_queue);
4137 spin_unlock_irqrestore(&h->scan_lock, flags);
4138}
4139
4140static int hpsa_scan_finished(struct Scsi_Host *sh,
4141 unsigned long elapsed_time)
4142{
4143 struct ctlr_info *h = shost_to_hba(sh);
4144 unsigned long flags;
4145 int finished;
4146
4147 spin_lock_irqsave(&h->scan_lock, flags);
4148 finished = h->scan_finished;
4149 spin_unlock_irqrestore(&h->scan_lock, flags);
4150 return finished;
4151}
4152
667e23d4
SC		 4153static int hpsa_change_queue_depth(struct scsi_device *sdev,
4154 int qdepth, int reason)
4155{
4156 struct ctlr_info *h = sdev_to_hba(sdev);
4157
4158 if (reason != SCSI_QDEPTH_DEFAULT)
4159 return -ENOTSUPP;
4160
4161 if (qdepth < 1)
4162 qdepth = 1;
4163 else
4164 if (qdepth > h->nr_cmds)
4165 qdepth = h->nr_cmds;
4166 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
4167 return sdev->queue_depth;
4168}
4169
edd16368
SC		 4170static void hpsa_unregister_scsi(struct ctlr_info *h)
4171{
4172 /* we are being forcibly unloaded, and may not refuse. */
4173 scsi_remove_host(h->scsi_host);
4174 scsi_host_put(h->scsi_host);
4175 h->scsi_host = NULL;
4176}
4177
4178static int hpsa_register_scsi(struct ctlr_info *h)
4179{
b705690d
SC		 4180 struct Scsi_Host *sh;
4181 int error;
edd16368 4182
b705690d
SC		 4183 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4184 if (sh == NULL)
4185 goto fail;
4186
4187 sh->io_port = 0;
4188 sh->n_io_port = 0;
4189 sh->this_id = -1;
4190 sh->max_channel = 3;
4191 sh->max_cmd_len = MAX_COMMAND_SIZE;
4192 sh->max_lun = HPSA_MAX_LUN;
4193 sh->max_id = HPSA_MAX_LUN;
4194 sh->can_queue = h->nr_cmds;
316b221a
SC		 4195 if (h->hba_mode_enabled)
4196 sh->cmd_per_lun = 7;
4197 else
4198 sh->cmd_per_lun = h->nr_cmds;
b705690d
SC		 4199 sh->sg_tablesize = h->maxsgentries;
4200 h->scsi_host = sh;
4201 sh->hostdata[0] = (unsigned long) h;
4202 sh->irq = h->intr[h->intr_mode];
4203 sh->unique_id = sh->irq;
4204 error = scsi_add_host(sh, &h->pdev->dev);
4205 if (error)
4206 goto fail_host_put;
4207 scsi_scan_host(sh);
4208 return 0;
4209
4210 fail_host_put:
4211 dev_err(&h->pdev->dev, "%s: scsi_add_host"
4212 " failed for controller %d\n", __func__, h->ctlr);
4213 scsi_host_put(sh);
4214 return error;
4215 fail:
4216 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
4217 " failed for controller %d\n", __func__, h->ctlr);
4218 return -ENOMEM;
edd16368
SC		 4219}
4220
4221static int wait_for_device_to_become_ready(struct ctlr_info *h,
4222 unsigned char lunaddr[])
4223{
8919358e 4224 int rc;
edd16368
SC		 4225 int count = 0;
4226 int waittime = 1; /* seconds */
4227 struct CommandList *c;
4228
4229 c = cmd_special_alloc(h);
4230 if (!c) {
4231 dev_warn(&h->pdev->dev, "out of memory in "
4232 "wait_for_device_to_become_ready.\n");
4233 return IO_ERROR;
4234 }
4235
4236 /* Send test unit ready until device ready, or give up. */
4237 while (count < HPSA_TUR_RETRY_LIMIT) {
4238
4239 /* Wait for a bit. do this first, because if we send
4240 * the TUR right away, the reset will just abort it.
4241 */
4242 msleep(1000 * waittime);
4243 count++;
8919358e 4244 rc = 0; /* Device ready. */
edd16368
SC		 4245
4246 /* Increase wait time with each try, up to a point. */
4247 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
4248 waittime = waittime * 2;
4249
a2dac136
SC		 4250 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4251 (void) fill_cmd(c, TEST_UNIT_READY, h,
4252 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 4253 hpsa_scsi_do_simple_cmd_core(h, c);
4254 /* no unmap needed here because no data xfer. */
4255
4256 if (c->err_info->CommandStatus == CMD_SUCCESS)
4257 break;
4258
4259 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4260 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
4261 (c->err_info->SenseInfo[2] == NO_SENSE ||
4262 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
4263 break;
4264
4265 dev_warn(&h->pdev->dev, "waiting %d secs "
4266 "for device to become ready.\n", waittime);
4267 rc = 1; /* device not ready. */
4268 }
4269
4270 if (rc)
4271 dev_warn(&h->pdev->dev, "giving up on device.\n");
4272 else
4273 dev_warn(&h->pdev->dev, "device is ready.\n");
4274
4275 cmd_special_free(h, c);
4276 return rc;
4277}
4278
4279/* Need at least one of these error handlers to keep ../scsi/hosts.c from
4280 * complaining. Doing a host- or bus-reset can't do anything good here.
4281 */
4282static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
4283{
4284 int rc;
4285 struct ctlr_info *h;
4286 struct hpsa_scsi_dev_t *dev;
4287
4288 /* find the controller to which the command to be aborted was sent */
4289 h = sdev_to_hba(scsicmd->device);
4290 if (h == NULL) /* paranoia */
4291 return FAILED;
edd16368
SC		 4292 dev = scsicmd->device->hostdata;
4293 if (!dev) {
4294 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
4295 "device lookup failed.\n");
4296 return FAILED;
4297 }
d416b0c7
SC		 4298 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
4299 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 4300 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 4301 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 4302 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
4303 return SUCCESS;
4304
4305 dev_warn(&h->pdev->dev, "resetting device failed.\n");
4306 return FAILED;
4307}
4308
6cba3f19
SC		 4309static void swizzle_abort_tag(u8 *tag)
4310{
4311 u8 original_tag[8];
4312
4313 memcpy(original_tag, tag, 8);
4314 tag[0] = original_tag[3];
4315 tag[1] = original_tag[2];
4316 tag[2] = original_tag[1];
4317 tag[3] = original_tag[0];
4318 tag[4] = original_tag[7];
4319 tag[5] = original_tag[6];
4320 tag[6] = original_tag[5];
4321 tag[7] = original_tag[4];
4322}
4323
17eb87d2
ST		 4324static void hpsa_get_tag(struct ctlr_info *h,
4325 struct CommandList *c, u32 *taglower, u32 *tagupper)
4326{
4327 if (c->cmd_type == CMD_IOACCEL1) {
4328 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4329 &h->ioaccel_cmd_pool[c->cmdindex];
4330 *tagupper = cm1->Tag.upper;
4331 *taglower = cm1->Tag.lower;
54b6e9e9
ST		 4332 return;
4333 }
4334 if (c->cmd_type == CMD_IOACCEL2) {
4335 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4336 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4337 /* upper tag not used in ioaccel2 mode */
4338 memset(tagupper, 0, sizeof(*tagupper));
4339 *taglower = cm2->Tag;
54b6e9e9 4340 return;
17eb87d2 4341 }
54b6e9e9
ST		 4342 *tagupper = c->Header.Tag.upper;
4343 *taglower = c->Header.Tag.lower;
17eb87d2
ST		 4344}
4345
54b6e9e9 4346
75167d2c 4347static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 4348 struct CommandList *abort, int swizzle)
75167d2c
SC		 4349{
4350 int rc = IO_OK;
4351 struct CommandList *c;
4352 struct ErrorInfo *ei;
17eb87d2 4353 u32 tagupper, taglower;
75167d2c
SC		 4354
4355 c = cmd_special_alloc(h);
4356 if (c == NULL) { /* trouble... */
4357 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
4358 return -ENOMEM;
4359 }
4360
a2dac136
SC		 4361 /* fill_cmd can't fail here, no buffer to map */
4362 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
4363 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 4364 if (swizzle)
4365 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 4366 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 4367 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 4368 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 4369 __func__, tagupper, taglower);
75167d2c
SC		 4370 /* no unmap needed here because no data xfer. */
4371
4372 ei = c->err_info;
4373 switch (ei->CommandStatus) {
4374 case CMD_SUCCESS:
4375 break;
4376 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4377 rc = -1;
4378 break;
4379 default:
4380 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4381 __func__, tagupper, taglower);
d1e8beac 4382 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4383 rc = -1;
4384 break;
4385 }
4386 cmd_special_free(h, c);
dd0e19f3
ST		 4387 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4388 __func__, tagupper, taglower);
75167d2c
SC		 4389 return rc;
4390}
4391
4392/*
4393 * hpsa_find_cmd_in_queue
4394 *
4395 * Used to determine whether a command (find) is still present
4396 * in queue_head. Optionally excludes the last element of queue_head.
4397 *
4398 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
4399 * not yet been submitted, and so can be aborted by the driver without
4400 * sending an abort to the hardware.
4401 *
4402 * Returns pointer to command if found in queue, NULL otherwise.
4403 */
4404static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
4405 struct scsi_cmnd *find, struct list_head *queue_head)
4406{
4407 unsigned long flags;
4408 struct CommandList *c = NULL; /* ptr into cmpQ */
4409
4410 if (!find)
4411 return 0;
4412 spin_lock_irqsave(&h->lock, flags);
4413 list_for_each_entry(c, queue_head, list) {
4414 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
4415 continue;
4416 if (c->scsi_cmd == find) {
4417 spin_unlock_irqrestore(&h->lock, flags);
4418 return c;
4419 }
4420 }
4421 spin_unlock_irqrestore(&h->lock, flags);
4422 return NULL;
4423}
4424
6cba3f19
SC		 4425static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
4426 u8 *tag, struct list_head *queue_head)
4427{
4428 unsigned long flags;
4429 struct CommandList *c;
4430
4431 spin_lock_irqsave(&h->lock, flags);
4432 list_for_each_entry(c, queue_head, list) {
4433 if (memcmp(&c->Header.Tag, tag, 8) != 0)
4434 continue;
4435 spin_unlock_irqrestore(&h->lock, flags);
4436 return c;
4437 }
4438 spin_unlock_irqrestore(&h->lock, flags);
4439 return NULL;
4440}
4441
54b6e9e9
ST		 4442/* ioaccel2 path firmware cannot handle abort task requests.
4443 * Change abort requests to physical target reset, and send to the
4444 * address of the physical disk used for the ioaccel 2 command.
4445 * Return 0 on success (IO_OK)
4446 * -1 on failure
4447 */
4448
4449static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
4450 unsigned char *scsi3addr, struct CommandList *abort)
4451{
4452 int rc = IO_OK;
4453 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4454 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4455 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4456 unsigned char *psa = &phys_scsi3addr[0];
4457
4458 /* Get a pointer to the hpsa logical device. */
4459 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
4460 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4461 if (dev == NULL) {
4462 dev_warn(&h->pdev->dev,
4463 "Cannot abort: no device pointer for command.\n");
4464 return -1; /* not abortable */
4465 }
4466
2ba8bfc8
SC		 4467 if (h->raid_offload_debug > 0)
4468 dev_info(&h->pdev->dev,
4469 "Reset as abort: Abort requested on C%d:B%d:T%d:L%d scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4470 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
4471 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
4472 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
4473
54b6e9e9
ST		 4474 if (!dev->offload_enabled) {
4475 dev_warn(&h->pdev->dev,
4476 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4477 return -1; /* not abortable */
4478 }
4479
4480 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4481 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4482 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4483 return -1; /* not abortable */
4484 }
4485
4486 /* send the reset */
2ba8bfc8
SC		 4487 if (h->raid_offload_debug > 0)
4488 dev_info(&h->pdev->dev,
4489 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4490 psa[0], psa[1], psa[2], psa[3],
4491 psa[4], psa[5], psa[6], psa[7]);
54b6e9e9
ST		 4492 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
4493 if (rc != 0) {
4494 dev_warn(&h->pdev->dev,
4495 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4496 psa[0], psa[1], psa[2], psa[3],
4497 psa[4], psa[5], psa[6], psa[7]);
4498 return rc; /* failed to reset */
4499 }
4500
4501 /* wait for device to recover */
4502 if (wait_for_device_to_become_ready(h, psa) != 0) {
4503 dev_warn(&h->pdev->dev,
4504 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4505 psa[0], psa[1], psa[2], psa[3],
4506 psa[4], psa[5], psa[6], psa[7]);
4507 return -1; /* failed to recover */
4508 }
4509
4510 /* device recovered */
4511 dev_info(&h->pdev->dev,
4512 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4513 psa[0], psa[1], psa[2], psa[3],
4514 psa[4], psa[5], psa[6], psa[7]);
4515
4516 return rc; /* success */
4517}
4518
6cba3f19
SC		 4519/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
4520 * tell which kind we're dealing with, so we send the abort both ways. There
4521 * shouldn't be any collisions between swizzled and unswizzled tags due to the
4522 * way we construct our tags but we check anyway in case the assumptions which
4523 * make this true someday become false.
4524 */
4525static int hpsa_send_abort_both_ways(struct ctlr_info *h,
4526 unsigned char *scsi3addr, struct CommandList *abort)
4527{
4528 u8 swizzled_tag[8];
4529 struct CommandList *c;
4530 int rc = 0, rc2 = 0;
4531
54b6e9e9
ST		 4532 /* ioccelerator mode 2 commands should be aborted via the
4533 * accelerated path, since RAID path is unaware of these commands,
4534 * but underlying firmware can't handle abort TMF.
4535 * Change abort to physical device reset.
4536 */
4537 if (abort->cmd_type == CMD_IOACCEL2)
4538 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
4539
6cba3f19
SC		 4540 /* we do not expect to find the swizzled tag in our queue, but
4541 * check anyway just to be sure the assumptions which make this
4542 * the case haven't become wrong.
4543 */
4544 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
4545 swizzle_abort_tag(swizzled_tag);
4546 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
4547 if (c != NULL) {
4548 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
4549 return hpsa_send_abort(h, scsi3addr, abort, 0);
4550 }
4551 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
4552
4553 /* if the command is still in our queue, we can't conclude that it was
4554 * aborted (it might have just completed normally) but in any case
4555 * we don't need to try to abort it another way.
4556 */
4557 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
4558 if (c)
4559 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
4560 return rc && rc2;
4561}
4562
75167d2c
SC		 4563/* Send an abort for the specified command.
4564 * If the device and controller support it,
4565 * send a task abort request.
4566 */
4567static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
4568{
4569
4570 int i, rc;
4571 struct ctlr_info *h;
4572 struct hpsa_scsi_dev_t *dev;
4573 struct CommandList *abort; /* pointer to command to be aborted */
4574 struct CommandList *found;
4575 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
4576 char msg[256]; /* For debug messaging. */
4577 int ml = 0;
17eb87d2 4578 u32 tagupper, taglower;
75167d2c
SC		 4579
4580 /* Find the controller of the command to be aborted */
4581 h = sdev_to_hba(sc->device);
4582 if (WARN(h == NULL,
4583 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
4584 return FAILED;
4585
4586 /* Check that controller supports some kind of task abort */
4587 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
4588 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
4589 return FAILED;
4590
4591 memset(msg, 0, sizeof(msg));
4592 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ",
4593 h->scsi_host->host_no, sc->device->channel,
4594 sc->device->id, sc->device->lun);
4595
4596 /* Find the device of the command to be aborted */
4597 dev = sc->device->hostdata;
4598 if (!dev) {
4599 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
4600 msg);
4601 return FAILED;
4602 }
4603
4604 /* Get SCSI command to be aborted */
4605 abort = (struct CommandList *) sc->host_scribble;
4606 if (abort == NULL) {
4607 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
4608 msg);
4609 return FAILED;
4610 }
17eb87d2
ST		 4611 hpsa_get_tag(h, abort, &taglower, &tagupper);
4612 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 4613 as = (struct scsi_cmnd *) abort->scsi_cmd;
4614 if (as != NULL)
4615 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
4616 as->cmnd[0], as->serial_number);
4617 dev_dbg(&h->pdev->dev, "%s\n", msg);
4618 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
4619 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
4620
4621 /* Search reqQ to See if command is queued but not submitted,
4622 * if so, complete the command with aborted status and remove
4623 * it from the reqQ.
4624 */
4625 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
4626 if (found) {
4627 found->err_info->CommandStatus = CMD_ABORTED;
4628 finish_cmd(found);
4629 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
4630 msg);
4631 return SUCCESS;
4632 }
4633
4634 /* not in reqQ, if also not in cmpQ, must have already completed */
4635 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4636 if (!found) {
d6ebd0f7 4637 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 4638 msg);
4639 return SUCCESS;
4640 }
4641
4642 /*
4643 * Command is in flight, or possibly already completed
4644 * by the firmware (but not to the scsi mid layer) but we can't
4645 * distinguish which. Send the abort down.
4646 */
6cba3f19 4647 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 4648 if (rc != 0) {
4649 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
4650 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
4651 h->scsi_host->host_no,
4652 dev->bus, dev->target, dev->lun);
4653 return FAILED;
4654 }
4655 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
4656
4657 /* If the abort(s) above completed and actually aborted the
4658 * command, then the command to be aborted should already be
4659 * completed. If not, wait around a bit more to see if they
4660 * manage to complete normally.
4661 */
4662#define ABORT_COMPLETE_WAIT_SECS 30
4663 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
4664 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4665 if (!found)
4666 return SUCCESS;
4667 msleep(100);
4668 }
4669 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
4670 msg, ABORT_COMPLETE_WAIT_SECS);
4671 return FAILED;
4672}
4673
4674
edd16368
SC		 4675/*
4676 * For operations that cannot sleep, a command block is allocated at init,
4677 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4678 * which ones are free or in use. Lock must be held when calling this.
4679 * cmd_free() is the complement.
4680 */
4681static struct CommandList *cmd_alloc(struct ctlr_info *h)
4682{
4683 struct CommandList *c;
4684 int i;
4685 union u64bit temp64;
4686 dma_addr_t cmd_dma_handle, err_dma_handle;
e16a33ad 4687 unsigned long flags;
edd16368 4688
e16a33ad 4689 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4690 do {
4691 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
e16a33ad
MG		 4692 if (i == h->nr_cmds) {
4693 spin_unlock_irqrestore(&h->lock, flags);
edd16368 4694 return NULL;
e16a33ad 4695 }
edd16368
SC		 4696 } while (test_and_set_bit
4697 (i & (BITS_PER_LONG - 1),
4698 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
e16a33ad
MG		 4699 spin_unlock_irqrestore(&h->lock, flags);
4700
edd16368
SC		 4701 c = h->cmd_pool + i;
4702 memset(c, 0, sizeof(*c));
4703 cmd_dma_handle = h->cmd_pool_dhandle
4704 + i * sizeof(*c);
4705 c->err_info = h->errinfo_pool + i;
4706 memset(c->err_info, 0, sizeof(*c->err_info));
4707 err_dma_handle = h->errinfo_pool_dhandle
4708 + i * sizeof(*c->err_info);
edd16368
SC		 4709
4710 c->cmdindex = i;
4711
9e0fc764 4712 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4713 c->busaddr = (u32) cmd_dma_handle;
4714 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4715 c->ErrDesc.Addr.lower = temp64.val32.lower;
4716 c->ErrDesc.Addr.upper = temp64.val32.upper;
4717 c->ErrDesc.Len = sizeof(*c->err_info);
4718
4719 c->h = h;
4720 return c;
4721}
4722
4723/* For operations that can wait for kmalloc to possibly sleep,
4724 * this routine can be called. Lock need not be held to call
4725 * cmd_special_alloc. cmd_special_free() is the complement.
4726 */
4727static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
4728{
4729 struct CommandList *c;
4730 union u64bit temp64;
4731 dma_addr_t cmd_dma_handle, err_dma_handle;
4732
4733 c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
4734 if (c == NULL)
4735 return NULL;
4736 memset(c, 0, sizeof(*c));
4737
e1f7de0c 4738 c->cmd_type = CMD_SCSI;
edd16368
SC		 4739 c->cmdindex = -1;
4740
4741 c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
4742 &err_dma_handle);
4743
4744 if (c->err_info == NULL) {
4745 pci_free_consistent(h->pdev,
4746 sizeof(*c), c, cmd_dma_handle);
4747 return NULL;
4748 }
4749 memset(c->err_info, 0, sizeof(*c->err_info));
4750
9e0fc764 4751 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4752 c->busaddr = (u32) cmd_dma_handle;
4753 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4754 c->ErrDesc.Addr.lower = temp64.val32.lower;
4755 c->ErrDesc.Addr.upper = temp64.val32.upper;
4756 c->ErrDesc.Len = sizeof(*c->err_info);
4757
4758 c->h = h;
4759 return c;
4760}
4761
4762static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4763{
4764 int i;
e16a33ad 4765 unsigned long flags;
edd16368
SC		 4766
4767 i = c - h->cmd_pool;
e16a33ad 4768 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4769 clear_bit(i & (BITS_PER_LONG - 1),
4770 h->cmd_pool_bits + (i / BITS_PER_LONG));
e16a33ad 4771 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4772}
4773
4774static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
4775{
4776 union u64bit temp64;
4777
4778 temp64.val32.lower = c->ErrDesc.Addr.lower;
4779 temp64.val32.upper = c->ErrDesc.Addr.upper;
4780 pci_free_consistent(h->pdev, sizeof(*c->err_info),
4781 c->err_info, (dma_addr_t) temp64.val);
4782 pci_free_consistent(h->pdev, sizeof(*c),
d896f3f3 4783 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
edd16368
SC		 4784}
4785
4786#ifdef CONFIG_COMPAT
4787
edd16368
SC		 4788static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
4789{
4790 IOCTL32_Command_struct __user *arg32 =
4791 (IOCTL32_Command_struct __user *) arg;
4792 IOCTL_Command_struct arg64;
4793 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
4794 int err;
4795 u32 cp;
4796
938abd84 4797 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4798 err = 0;
4799 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4800 sizeof(arg64.LUN_info));
4801 err |= copy_from_user(&arg64.Request, &arg32->Request,
4802 sizeof(arg64.Request));
4803 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4804 sizeof(arg64.error_info));
4805 err |= get_user(arg64.buf_size, &arg32->buf_size);
4806 err |= get_user(cp, &arg32->buf);
4807 arg64.buf = compat_ptr(cp);
4808 err |= copy_to_user(p, &arg64, sizeof(arg64));
4809
4810 if (err)
4811 return -EFAULT;
4812
e39eeaed 4813 err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
edd16368
SC		 4814 if (err)
4815 return err;
4816 err |= copy_in_user(&arg32->error_info, &p->error_info,
4817 sizeof(arg32->error_info));
4818 if (err)
4819 return -EFAULT;
4820 return err;
4821}
4822
4823static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
4824 int cmd, void *arg)
4825{
4826 BIG_IOCTL32_Command_struct __user *arg32 =
4827 (BIG_IOCTL32_Command_struct __user *) arg;
4828 BIG_IOCTL_Command_struct arg64;
4829 BIG_IOCTL_Command_struct __user *p =
4830 compat_alloc_user_space(sizeof(arg64));
4831 int err;
4832 u32 cp;
4833
938abd84 4834 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4835 err = 0;
4836 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4837 sizeof(arg64.LUN_info));
4838 err |= copy_from_user(&arg64.Request, &arg32->Request,
4839 sizeof(arg64.Request));
4840 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4841 sizeof(arg64.error_info));
4842 err |= get_user(arg64.buf_size, &arg32->buf_size);
4843 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4844 err |= get_user(cp, &arg32->buf);
4845 arg64.buf = compat_ptr(cp);
4846 err |= copy_to_user(p, &arg64, sizeof(arg64));
4847
4848 if (err)
4849 return -EFAULT;
4850
e39eeaed 4851 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
edd16368
SC		 4852 if (err)
4853 return err;
4854 err |= copy_in_user(&arg32->error_info, &p->error_info,
4855 sizeof(arg32->error_info));
4856 if (err)
4857 return -EFAULT;
4858 return err;
4859}
71fe75a7
SC		 4860
4861static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
4862{
4863 switch (cmd) {
4864 case CCISS_GETPCIINFO:
4865 case CCISS_GETINTINFO:
4866 case CCISS_SETINTINFO:
4867 case CCISS_GETNODENAME:
4868 case CCISS_SETNODENAME:
4869 case CCISS_GETHEARTBEAT:
4870 case CCISS_GETBUSTYPES:
4871 case CCISS_GETFIRMVER:
4872 case CCISS_GETDRIVVER:
4873 case CCISS_REVALIDVOLS:
4874 case CCISS_DEREGDISK:
4875 case CCISS_REGNEWDISK:
4876 case CCISS_REGNEWD:
4877 case CCISS_RESCANDISK:
4878 case CCISS_GETLUNINFO:
4879 return hpsa_ioctl(dev, cmd, arg);
4880
4881 case CCISS_PASSTHRU32:
4882 return hpsa_ioctl32_passthru(dev, cmd, arg);
4883 case CCISS_BIG_PASSTHRU32:
4884 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4885
4886 default:
4887 return -ENOIOCTLCMD;
4888 }
4889}
edd16368
SC		 4890#endif
4891
4892static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4893{
4894 struct hpsa_pci_info pciinfo;
4895
4896 if (!argp)
4897 return -EINVAL;
4898 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4899 pciinfo.bus = h->pdev->bus->number;
4900 pciinfo.dev_fn = h->pdev->devfn;
4901 pciinfo.board_id = h->board_id;
4902 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4903 return -EFAULT;
4904 return 0;
4905}
4906
4907static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4908{
4909 DriverVer_type DriverVer;
4910 unsigned char vmaj, vmin, vsubmin;
4911 int rc;
4912
4913 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4914 &vmaj, &vmin, &vsubmin);
4915 if (rc != 3) {
4916 dev_info(&h->pdev->dev, "driver version string '%s' "
4917 "unrecognized.", HPSA_DRIVER_VERSION);
4918 vmaj = 0;
4919 vmin = 0;
4920 vsubmin = 0;
4921 }
4922 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4923 if (!argp)
4924 return -EINVAL;
4925 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4926 return -EFAULT;
4927 return 0;
4928}
4929
4930static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4931{
4932 IOCTL_Command_struct iocommand;
4933 struct CommandList *c;
4934 char *buff = NULL;
4935 union u64bit temp64;
c1f63c8f 4936 int rc = 0;
edd16368
SC		 4937
4938 if (!argp)
4939 return -EINVAL;
4940 if (!capable(CAP_SYS_RAWIO))
4941 return -EPERM;
4942 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4943 return -EFAULT;
4944 if ((iocommand.buf_size < 1) &&
4945 (iocommand.Request.Type.Direction != XFER_NONE)) {
4946 return -EINVAL;
4947 }
4948 if (iocommand.buf_size > 0) {
4949 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4950 if (buff == NULL)
4951 return -EFAULT;
9233fb10 4952 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 4953 /* Copy the data into the buffer we created */
4954 if (copy_from_user(buff, iocommand.buf,
4955 iocommand.buf_size)) {
c1f63c8f
SC		 4956 rc = -EFAULT;
4957 goto out_kfree;
b03a7771
SC		 4958 }
4959 } else {
4960 memset(buff, 0, iocommand.buf_size);
edd16368 4961 }
b03a7771 4962 }
edd16368
SC		 4963 c = cmd_special_alloc(h);
4964 if (c == NULL) {
c1f63c8f
SC		 4965 rc = -ENOMEM;
4966 goto out_kfree;
edd16368
SC		 4967 }
4968 /* Fill in the command type */
4969 c->cmd_type = CMD_IOCTL_PEND;
4970 /* Fill in Command Header */
4971 c->Header.ReplyQueue = 0; /* unused in simple mode */
4972 if (iocommand.buf_size > 0) { /* buffer to fill */
4973 c->Header.SGList = 1;
4974 c->Header.SGTotal = 1;
4975 } else { /* no buffers to fill */
4976 c->Header.SGList = 0;
4977 c->Header.SGTotal = 0;
4978 }
4979 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
4980 /* use the kernel address the cmd block for tag */
4981 c->Header.Tag.lower = c->busaddr;
4982
4983 /* Fill in Request block */
4984 memcpy(&c->Request, &iocommand.Request,
4985 sizeof(c->Request));
4986
4987 /* Fill in the scatter gather information */
4988 if (iocommand.buf_size > 0) {
4989 temp64.val = pci_map_single(h->pdev, buff,
4990 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4991 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4992 c->SG[0].Addr.lower = 0;
4993 c->SG[0].Addr.upper = 0;
4994 c->SG[0].Len = 0;
4995 rc = -ENOMEM;
4996 goto out;
4997 }
edd16368
SC		 4998 c->SG[0].Addr.lower = temp64.val32.lower;
4999 c->SG[0].Addr.upper = temp64.val32.upper;
5000 c->SG[0].Len = iocommand.buf_size;
e1d9cbfa 5001 c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/
edd16368 5002 }
a0c12413 5003 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 5004 if (iocommand.buf_size > 0)
5005 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 5006 check_ioctl_unit_attention(h, c);
5007
5008 /* Copy the error information out */
5009 memcpy(&iocommand.error_info, c->err_info,
5010 sizeof(iocommand.error_info));
5011 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 5012 rc = -EFAULT;
5013 goto out;
edd16368 5014 }
9233fb10 5015 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 5016 iocommand.buf_size > 0) {
edd16368
SC		 5017 /* Copy the data out of the buffer we created */
5018 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 5019 rc = -EFAULT;
5020 goto out;
edd16368
SC		 5021 }
5022 }
c1f63c8f 5023out:
edd16368 5024 cmd_special_free(h, c);
c1f63c8f
SC		 5025out_kfree:
5026 kfree(buff);
5027 return rc;
edd16368
SC		 5028}
5029
5030static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5031{
5032 BIG_IOCTL_Command_struct *ioc;
5033 struct CommandList *c;
5034 unsigned char **buff = NULL;
5035 int *buff_size = NULL;
5036 union u64bit temp64;
5037 BYTE sg_used = 0;
5038 int status = 0;
5039 int i;
01a02ffc
SC		 5040 u32 left;
5041 u32 sz;
edd16368
SC		 5042 BYTE __user *data_ptr;
5043
5044 if (!argp)
5045 return -EINVAL;
5046 if (!capable(CAP_SYS_RAWIO))
5047 return -EPERM;
5048 ioc = (BIG_IOCTL_Command_struct *)
5049 kmalloc(sizeof(*ioc), GFP_KERNEL);
5050 if (!ioc) {
5051 status = -ENOMEM;
5052 goto cleanup1;
5053 }
5054 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
5055 status = -EFAULT;
5056 goto cleanup1;
5057 }
5058 if ((ioc->buf_size < 1) &&
5059 (ioc->Request.Type.Direction != XFER_NONE)) {
5060 status = -EINVAL;
5061 goto cleanup1;
5062 }
5063 /* Check kmalloc limits using all SGs */
5064 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
5065 status = -EINVAL;
5066 goto cleanup1;
5067 }
d66ae08b 5068 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 5069 status = -EINVAL;
5070 goto cleanup1;
5071 }
d66ae08b 5072 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 5073 if (!buff) {
5074 status = -ENOMEM;
5075 goto cleanup1;
5076 }
d66ae08b 5077 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 5078 if (!buff_size) {
5079 status = -ENOMEM;
5080 goto cleanup1;
5081 }
5082 left = ioc->buf_size;
5083 data_ptr = ioc->buf;
5084 while (left) {
5085 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
5086 buff_size[sg_used] = sz;
5087 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
5088 if (buff[sg_used] == NULL) {
5089 status = -ENOMEM;
5090 goto cleanup1;
5091 }
9233fb10 5092 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368
SC		 5093 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
5094 status = -ENOMEM;
5095 goto cleanup1;
5096 }
5097 } else
5098 memset(buff[sg_used], 0, sz);
5099 left -= sz;
5100 data_ptr += sz;
5101 sg_used++;
5102 }
5103 c = cmd_special_alloc(h);
5104 if (c == NULL) {
5105 status = -ENOMEM;
5106 goto cleanup1;
5107 }
5108 c->cmd_type = CMD_IOCTL_PEND;
5109 c->Header.ReplyQueue = 0;
b03a7771 5110 c->Header.SGList = c->Header.SGTotal = sg_used;
edd16368
SC		 5111 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
5112 c->Header.Tag.lower = c->busaddr;
5113 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
5114 if (ioc->buf_size > 0) {
5115 int i;
5116 for (i = 0; i < sg_used; i++) {
5117 temp64.val = pci_map_single(h->pdev, buff[i],
5118 buff_size[i], PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 5119 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
5120 c->SG[i].Addr.lower = 0;
5121 c->SG[i].Addr.upper = 0;
5122 c->SG[i].Len = 0;
5123 hpsa_pci_unmap(h->pdev, c, i,
5124 PCI_DMA_BIDIRECTIONAL);
5125 status = -ENOMEM;
e2d4a1f6 5126 goto cleanup0;
bcc48ffa 5127 }
edd16368
SC		 5128 c->SG[i].Addr.lower = temp64.val32.lower;
5129 c->SG[i].Addr.upper = temp64.val32.upper;
5130 c->SG[i].Len = buff_size[i];
e1d9cbfa 5131 c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST;
edd16368
SC		 5132 }
5133 }
a0c12413 5134 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 5135 if (sg_used)
5136 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 5137 check_ioctl_unit_attention(h, c);
5138 /* Copy the error information out */
5139 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
5140 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 5141 status = -EFAULT;
e2d4a1f6 5142 goto cleanup0;
edd16368 5143 }
9233fb10 5144 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
edd16368
SC		 5145 /* Copy the data out of the buffer we created */
5146 BYTE __user *ptr = ioc->buf;
5147 for (i = 0; i < sg_used; i++) {
5148 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 5149 status = -EFAULT;
e2d4a1f6 5150 goto cleanup0;
edd16368
SC		 5151 }
5152 ptr += buff_size[i];
5153 }
5154 }
edd16368 5155 status = 0;
e2d4a1f6
SC		 5156cleanup0:
5157 cmd_special_free(h, c);
edd16368
SC		 5158cleanup1:
5159 if (buff) {
5160 for (i = 0; i < sg_used; i++)
5161 kfree(buff[i]);
5162 kfree(buff);
5163 }
5164 kfree(buff_size);
5165 kfree(ioc);
5166 return status;
5167}
5168
5169static void check_ioctl_unit_attention(struct ctlr_info *h,
5170 struct CommandList *c)
5171{
5172 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5173 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
5174 (void) check_for_unit_attention(h, c);
5175}
0390f0c0
SC		 5176
5177static int increment_passthru_count(struct ctlr_info *h)
5178{
5179 unsigned long flags;
5180
5181 spin_lock_irqsave(&h->passthru_count_lock, flags);
5182 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
5183 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5184 return -1;
5185 }
5186 h->passthru_count++;
5187 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5188 return 0;
5189}
5190
5191static void decrement_passthru_count(struct ctlr_info *h)
5192{
5193 unsigned long flags;
5194
5195 spin_lock_irqsave(&h->passthru_count_lock, flags);
5196 if (h->passthru_count <= 0) {
5197 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5198 /* not expecting to get here. */
5199 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
5200 return;
5201 }
5202 h->passthru_count--;
5203 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5204}
5205
edd16368
SC		 5206/*
5207 * ioctl
5208 */
5209static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
5210{
5211 struct ctlr_info *h;
5212 void __user *argp = (void __user *)arg;
0390f0c0 5213 int rc;
edd16368
SC		 5214
5215 h = sdev_to_hba(dev);
5216
5217 switch (cmd) {
5218 case CCISS_DEREGDISK:
5219 case CCISS_REGNEWDISK:
5220 case CCISS_REGNEWD:
a08a8471 5221 hpsa_scan_start(h->scsi_host);
edd16368
SC		 5222 return 0;
5223 case CCISS_GETPCIINFO:
5224 return hpsa_getpciinfo_ioctl(h, argp);
5225 case CCISS_GETDRIVVER:
5226 return hpsa_getdrivver_ioctl(h, argp);
5227 case CCISS_PASSTHRU:
0390f0c0
SC		 5228 if (increment_passthru_count(h))
5229 return -EAGAIN;
5230 rc = hpsa_passthru_ioctl(h, argp);
5231 decrement_passthru_count(h);
5232 return rc;
edd16368 5233 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 5234 if (increment_passthru_count(h))
5235 return -EAGAIN;
5236 rc = hpsa_big_passthru_ioctl(h, argp);
5237 decrement_passthru_count(h);
5238 return rc;
edd16368
SC		 5239 default:
5240 return -ENOTTY;
5241 }
5242}
5243
6f039790
GKH		 5244static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
5245 u8 reset_type)
64670ac8
SC		 5246{
5247 struct CommandList *c;
5248
5249 c = cmd_alloc(h);
5250 if (!c)
5251 return -ENOMEM;
a2dac136
SC		 5252 /* fill_cmd can't fail here, no data buffer to map */
5253 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 5254 RAID_CTLR_LUNID, TYPE_MSG);
5255 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
5256 c->waiting = NULL;
5257 enqueue_cmd_and_start_io(h, c);
5258 /* Don't wait for completion, the reset won't complete. Don't free
5259 * the command either. This is the last command we will send before
5260 * re-initializing everything, so it doesn't matter and won't leak.
5261 */
5262 return 0;
5263}
5264
a2dac136 5265static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 5266 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 5267 int cmd_type)
5268{
5269 int pci_dir = XFER_NONE;
75167d2c 5270 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 5271
5272 c->cmd_type = CMD_IOCTL_PEND;
5273 c->Header.ReplyQueue = 0;
5274 if (buff != NULL && size > 0) {
5275 c->Header.SGList = 1;
5276 c->Header.SGTotal = 1;
5277 } else {
5278 c->Header.SGList = 0;
5279 c->Header.SGTotal = 0;
5280 }
5281 c->Header.Tag.lower = c->busaddr;
5282 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
5283
5284 c->Request.Type.Type = cmd_type;
5285 if (cmd_type == TYPE_CMD) {
5286 switch (cmd) {
5287 case HPSA_INQUIRY:
5288 /* are we trying to read a vital product page */
b7bb24eb 5289 if (page_code & VPD_PAGE) {
edd16368 5290 c->Request.CDB[1] = 0x01;
b7bb24eb 5291 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 5292 }
5293 c->Request.CDBLen = 6;
5294 c->Request.Type.Attribute = ATTR_SIMPLE;
5295 c->Request.Type.Direction = XFER_READ;
5296 c->Request.Timeout = 0;
5297 c->Request.CDB[0] = HPSA_INQUIRY;
5298 c->Request.CDB[4] = size & 0xFF;
5299 break;
5300 case HPSA_REPORT_LOG:
5301 case HPSA_REPORT_PHYS:
5302 /* Talking to controller so It's a physical command
5303 mode = 00 target = 0. Nothing to write.
5304 */
5305 c->Request.CDBLen = 12;
5306 c->Request.Type.Attribute = ATTR_SIMPLE;
5307 c->Request.Type.Direction = XFER_READ;
5308 c->Request.Timeout = 0;
5309 c->Request.CDB[0] = cmd;
5310 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5311 c->Request.CDB[7] = (size >> 16) & 0xFF;
5312 c->Request.CDB[8] = (size >> 8) & 0xFF;
5313 c->Request.CDB[9] = size & 0xFF;
5314 break;
edd16368
SC		 5315 case HPSA_CACHE_FLUSH:
5316 c->Request.CDBLen = 12;
5317 c->Request.Type.Attribute = ATTR_SIMPLE;
5318 c->Request.Type.Direction = XFER_WRITE;
5319 c->Request.Timeout = 0;
5320 c->Request.CDB[0] = BMIC_WRITE;
5321 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 5322 c->Request.CDB[7] = (size >> 8) & 0xFF;
5323 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 5324 break;
5325 case TEST_UNIT_READY:
5326 c->Request.CDBLen = 6;
5327 c->Request.Type.Attribute = ATTR_SIMPLE;
5328 c->Request.Type.Direction = XFER_NONE;
5329 c->Request.Timeout = 0;
5330 break;
283b4a9b
SC		 5331 case HPSA_GET_RAID_MAP:
5332 c->Request.CDBLen = 12;
5333 c->Request.Type.Attribute = ATTR_SIMPLE;
5334 c->Request.Type.Direction = XFER_READ;
5335 c->Request.Timeout = 0;
5336 c->Request.CDB[0] = HPSA_CISS_READ;
5337 c->Request.CDB[1] = cmd;
5338 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5339 c->Request.CDB[7] = (size >> 16) & 0xFF;
5340 c->Request.CDB[8] = (size >> 8) & 0xFF;
5341 c->Request.CDB[9] = size & 0xFF;
5342 break;
316b221a
SC		 5343 case BMIC_SENSE_CONTROLLER_PARAMETERS:
5344 c->Request.CDBLen = 10;
5345 c->Request.Type.Attribute = ATTR_SIMPLE;
5346 c->Request.Type.Direction = XFER_READ;
5347 c->Request.Timeout = 0;
5348 c->Request.CDB[0] = BMIC_READ;
5349 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
5350 c->Request.CDB[7] = (size >> 16) & 0xFF;
5351 c->Request.CDB[8] = (size >> 8) & 0xFF;
5352 break;
edd16368
SC		 5353 default:
5354 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5355 BUG();
a2dac136 5356 return -1;
edd16368
SC		 5357 }
5358 } else if (cmd_type == TYPE_MSG) {
5359 switch (cmd) {
5360
5361 case HPSA_DEVICE_RESET_MSG:
5362 c->Request.CDBLen = 16;
5363 c->Request.Type.Type = 1; /* It is a MSG not a CMD */
5364 c->Request.Type.Attribute = ATTR_SIMPLE;
5365 c->Request.Type.Direction = XFER_NONE;
5366 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5367 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5368 c->Request.CDB[0] = cmd;
21e89afd 5369 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5370 /* If bytes 4-7 are zero, it means reset the */
5371 /* LunID device */
5372 c->Request.CDB[4] = 0x00;
5373 c->Request.CDB[5] = 0x00;
5374 c->Request.CDB[6] = 0x00;
5375 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5376 break;
5377 case HPSA_ABORT_MSG:
5378 a = buff; /* point to command to be aborted */
5379 dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n",
5380 a->Header.Tag.upper, a->Header.Tag.lower,
5381 c->Header.Tag.upper, c->Header.Tag.lower);
5382 c->Request.CDBLen = 16;
5383 c->Request.Type.Type = TYPE_MSG;
5384 c->Request.Type.Attribute = ATTR_SIMPLE;
5385 c->Request.Type.Direction = XFER_WRITE;
5386 c->Request.Timeout = 0; /* Don't time out */
5387 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5388 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5389 c->Request.CDB[2] = 0x00; /* reserved */
5390 c->Request.CDB[3] = 0x00; /* reserved */
5391 /* Tag to abort goes in CDB[4]-CDB[11] */
5392 c->Request.CDB[4] = a->Header.Tag.lower & 0xFF;
5393 c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF;
5394 c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF;
5395 c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF;
5396 c->Request.CDB[8] = a->Header.Tag.upper & 0xFF;
5397 c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF;
5398 c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF;
5399 c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF;
5400 c->Request.CDB[12] = 0x00; /* reserved */
5401 c->Request.CDB[13] = 0x00; /* reserved */
5402 c->Request.CDB[14] = 0x00; /* reserved */
5403 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5404 break;
edd16368
SC		 5405 default:
5406 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5407 cmd);
5408 BUG();
5409 }
5410 } else {
5411 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5412 BUG();
5413 }
5414
5415 switch (c->Request.Type.Direction) {
5416 case XFER_READ:
5417 pci_dir = PCI_DMA_FROMDEVICE;
5418 break;
5419 case XFER_WRITE:
5420 pci_dir = PCI_DMA_TODEVICE;
5421 break;
5422 case XFER_NONE:
5423 pci_dir = PCI_DMA_NONE;
5424 break;
5425 default:
5426 pci_dir = PCI_DMA_BIDIRECTIONAL;
5427 }
a2dac136
SC		 5428 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5429 return -1;
5430 return 0;
edd16368
SC		 5431}
5432
5433/*
5434 * Map (physical) PCI mem into (virtual) kernel space
5435 */
5436static void __iomem *remap_pci_mem(ulong base, ulong size)
5437{
5438 ulong page_base = ((ulong) base) & PAGE_MASK;
5439 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5440 void __iomem *page_remapped = ioremap_nocache(page_base,
5441 page_offs + size);
edd16368
SC		 5442
5443 return page_remapped ? (page_remapped + page_offs) : NULL;
5444}
5445
5446/* Takes cmds off the submission queue and sends them to the hardware,
5447 * then puts them on the queue of cmds waiting for completion.
0b57075d 5448 * Assumes h->lock is held
edd16368 5449 */
0b57075d 5450static void start_io(struct ctlr_info *h, unsigned long *flags)
edd16368
SC		 5451{
5452 struct CommandList *c;
5453
9e0fc764
SC		 5454 while (!list_empty(&h->reqQ)) {
5455 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 5456 /* can't do anything if fifo is full */
5457 if ((h->access.fifo_full(h))) {
396883e2 5458 h->fifo_recently_full = 1;
edd16368
SC		 5459 dev_warn(&h->pdev->dev, "fifo full\n");
5460 break;
5461 }
396883e2 5462 h->fifo_recently_full = 0;
edd16368
SC		 5463
5464 /* Get the first entry from the Request Q */
5465 removeQ(c);
5466 h->Qdepth--;
5467
edd16368
SC		 5468 /* Put job onto the completed Q */
5469 addQ(&h->cmpQ, c);
e16a33ad
MG		 5470
5471 /* Must increment commands_outstanding before unlocking
5472 * and submitting to avoid race checking for fifo full
5473 * condition.
5474 */
5475 h->commands_outstanding++;
e16a33ad
MG		 5476
5477 /* Tell the controller execute command */
0b57075d 5478 spin_unlock_irqrestore(&h->lock, *flags);
e16a33ad 5479 h->access.submit_command(h, c);
0b57075d 5480 spin_lock_irqsave(&h->lock, *flags);
edd16368 5481 }
0b57075d
SC		 5482}
5483
5484static void lock_and_start_io(struct ctlr_info *h)
5485{
5486 unsigned long flags;
5487
5488 spin_lock_irqsave(&h->lock, flags);
5489 start_io(h, &flags);
e16a33ad 5490 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 5491}
5492
254f796b 5493static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5494{
254f796b 5495 return h->access.command_completed(h, q);
edd16368
SC		 5496}
5497
900c5440 5498static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5499{
5500 return h->access.intr_pending(h);
5501}
5502
5503static inline long interrupt_not_for_us(struct ctlr_info *h)
5504{
10f66018
SC		 5505 return (h->access.intr_pending(h) == 0) ||
5506 (h->interrupts_enabled == 0);
edd16368
SC		 5507}
5508
01a02ffc
SC		 5509static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5510 u32 raw_tag)
edd16368
SC		 5511{
5512 if (unlikely(tag_index >= h->nr_cmds)) {
5513 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5514 return 1;
5515 }
5516 return 0;
5517}
5518
5a3d16f5 5519static inline void finish_cmd(struct CommandList *c)
edd16368 5520{
e16a33ad 5521 unsigned long flags;
396883e2
SC		 5522 int io_may_be_stalled = 0;
5523 struct ctlr_info *h = c->h;
e16a33ad 5524
396883e2 5525 spin_lock_irqsave(&h->lock, flags);
edd16368 5526 removeQ(c);
396883e2
SC		 5527
5528 /*
5529 * Check for possibly stalled i/o.
5530 *
5531 * If a fifo_full condition is encountered, requests will back up
5532 * in h->reqQ. This queue is only emptied out by start_io which is
5533 * only called when a new i/o request comes in. If no i/o's are
5534 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
5535 * start_io from here if we detect such a danger.
5536 *
5537 * Normally, we shouldn't hit this case, but pounding on the
5538 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
5539 * commands_outstanding is low. We want to avoid calling
5540 * start_io from in here as much as possible, and esp. don't
5541 * want to get in a cycle where we call start_io every time
5542 * through here.
5543 */
5544 if (unlikely(h->fifo_recently_full) &&
5545 h->commands_outstanding < 5)
5546 io_may_be_stalled = 1;
5547
5548 spin_unlock_irqrestore(&h->lock, flags);
5549
e85c5974 5550 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5551 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5552 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5553 complete_scsi_command(c);
edd16368
SC		 5554 else if (c->cmd_type == CMD_IOCTL_PEND)
5555 complete(c->waiting);
396883e2 5556 if (unlikely(io_may_be_stalled))
0b57075d 5557 lock_and_start_io(h);
edd16368
SC		 5558}
5559
a104c99f
SC		 5560static inline u32 hpsa_tag_contains_index(u32 tag)
5561{
a104c99f
SC		 5562 return tag & DIRECT_LOOKUP_BIT;
5563}
5564
5565static inline u32 hpsa_tag_to_index(u32 tag)
5566{
a104c99f
SC		 5567 return tag >> DIRECT_LOOKUP_SHIFT;
5568}
5569
a9a3a273
SC		 5570
5571static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5572{
a9a3a273
SC		 5573#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5574#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5575 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5576 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5577 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5578}
5579
303932fd 5580/* process completion of an indexed ("direct lookup") command */
1d94f94d 5581static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5582 u32 raw_tag)
5583{
5584 u32 tag_index;
5585 struct CommandList *c;
5586
5587 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 5588 if (!bad_tag(h, tag_index, raw_tag)) {
5589 c = h->cmd_pool + tag_index;
5590 finish_cmd(c);
5591 }
303932fd
DB		 5592}
5593
5594/* process completion of a non-indexed command */
1d94f94d 5595static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 5596 u32 raw_tag)
5597{
5598 u32 tag;
5599 struct CommandList *c = NULL;
e16a33ad 5600 unsigned long flags;
303932fd 5601
a9a3a273 5602 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 5603 spin_lock_irqsave(&h->lock, flags);
9e0fc764 5604 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 5605 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 5606 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 5607 finish_cmd(c);
1d94f94d 5608 return;
303932fd
DB		 5609 }
5610 }
e16a33ad 5611 spin_unlock_irqrestore(&h->lock, flags);
303932fd 5612 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 5613}
5614
64670ac8
SC		 5615/* Some controllers, like p400, will give us one interrupt
5616 * after a soft reset, even if we turned interrupts off.
5617 * Only need to check for this in the hpsa_xxx_discard_completions
5618 * functions.
5619 */
5620static int ignore_bogus_interrupt(struct ctlr_info *h)
5621{
5622 if (likely(!reset_devices))
5623 return 0;
5624
5625 if (likely(h->interrupts_enabled))
5626 return 0;
5627
5628 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5629 "(known firmware bug.) Ignoring.\n");
5630
5631 return 1;
5632}
5633
254f796b
MG		 5634/*
5635 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5636 * Relies on (h-q[x] == x) being true for x such that
5637 * 0 <= x < MAX_REPLY_QUEUES.
5638 */
5639static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5640{
254f796b
MG		 5641 return container_of((queue - *queue), struct ctlr_info, q[0]);
5642}
5643
5644static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5645{
5646 struct ctlr_info *h = queue_to_hba(queue);
5647 u8 q = *(u8 *) queue;
64670ac8
SC		 5648 u32 raw_tag;
5649
5650 if (ignore_bogus_interrupt(h))
5651 return IRQ_NONE;
5652
5653 if (interrupt_not_for_us(h))
5654 return IRQ_NONE;
a0c12413 5655 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5656 while (interrupt_pending(h)) {
254f796b 5657 raw_tag = get_next_completion(h, q);
64670ac8 5658 while (raw_tag != FIFO_EMPTY)
254f796b 5659 raw_tag = next_command(h, q);
64670ac8 5660 }
64670ac8
SC		 5661 return IRQ_HANDLED;
5662}
5663
254f796b 5664static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5665{
254f796b 5666 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5667 u32 raw_tag;
254f796b 5668 u8 q = *(u8 *) queue;
64670ac8
SC		 5669
5670 if (ignore_bogus_interrupt(h))
5671 return IRQ_NONE;
5672
a0c12413 5673 h->last_intr_timestamp = get_jiffies_64();
254f796b 5674 raw_tag = get_next_completion(h, q);
64670ac8 5675 while (raw_tag != FIFO_EMPTY)
254f796b 5676 raw_tag = next_command(h, q);
64670ac8
SC		 5677 return IRQ_HANDLED;
5678}
5679
254f796b 5680static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5681{
254f796b 5682 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5683 u32 raw_tag;
254f796b 5684 u8 q = *(u8 *) queue;
edd16368
SC		 5685
5686 if (interrupt_not_for_us(h))
5687 return IRQ_NONE;
a0c12413 5688 h->last_intr_timestamp = get_jiffies_64();
10f66018 5689 while (interrupt_pending(h)) {
254f796b 5690 raw_tag = get_next_completion(h, q);
10f66018 5691 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5692 if (likely(hpsa_tag_contains_index(raw_tag)))
5693 process_indexed_cmd(h, raw_tag);
10f66018 5694 else
1d94f94d 5695 process_nonindexed_cmd(h, raw_tag);
254f796b 5696 raw_tag = next_command(h, q);
10f66018
SC		 5697 }
5698 }
10f66018
SC		 5699 return IRQ_HANDLED;
5700}
5701
254f796b 5702static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5703{
254f796b 5704 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5705 u32 raw_tag;
254f796b 5706 u8 q = *(u8 *) queue;
10f66018 5707
a0c12413 5708 h->last_intr_timestamp = get_jiffies_64();
254f796b 5709 raw_tag = get_next_completion(h, q);
303932fd 5710 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5711 if (likely(hpsa_tag_contains_index(raw_tag)))
5712 process_indexed_cmd(h, raw_tag);
303932fd 5713 else
1d94f94d 5714 process_nonindexed_cmd(h, raw_tag);
254f796b 5715 raw_tag = next_command(h, q);
edd16368 5716 }
edd16368
SC		 5717 return IRQ_HANDLED;
5718}
5719
a9a3a273
SC		 5720/* Send a message CDB to the firmware. Careful, this only works
5721 * in simple mode, not performant mode due to the tag lookup.
5722 * We only ever use this immediately after a controller reset.
5723 */
6f039790
GKH		 5724static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5725 unsigned char type)
edd16368
SC		 5726{
5727 struct Command {
5728 struct CommandListHeader CommandHeader;
5729 struct RequestBlock Request;
5730 struct ErrDescriptor ErrorDescriptor;
5731 };
5732 struct Command *cmd;
5733 static const size_t cmd_sz = sizeof(*cmd) +
5734 sizeof(cmd->ErrorDescriptor);
5735 dma_addr_t paddr64;
5736 uint32_t paddr32, tag;
5737 void __iomem *vaddr;
5738 int i, err;
5739
5740 vaddr = pci_ioremap_bar(pdev, 0);
5741 if (vaddr == NULL)
5742 return -ENOMEM;
5743
5744 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5745 * CCISS commands, so they must be allocated from the lower 4GiB of
5746 * memory.
5747 */
5748 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5749 if (err) {
5750 iounmap(vaddr);
5751 return -ENOMEM;
5752 }
5753
5754 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5755 if (cmd == NULL) {
5756 iounmap(vaddr);
5757 return -ENOMEM;
5758 }
5759
5760 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5761 * although there's no guarantee, we assume that the address is at
5762 * least 4-byte aligned (most likely, it's page-aligned).
5763 */
5764 paddr32 = paddr64;
5765
5766 cmd->CommandHeader.ReplyQueue = 0;
5767 cmd->CommandHeader.SGList = 0;
5768 cmd->CommandHeader.SGTotal = 0;
5769 cmd->CommandHeader.Tag.lower = paddr32;
5770 cmd->CommandHeader.Tag.upper = 0;
5771 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5772
5773 cmd->Request.CDBLen = 16;
5774 cmd->Request.Type.Type = TYPE_MSG;
5775 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
5776 cmd->Request.Type.Direction = XFER_NONE;
5777 cmd->Request.Timeout = 0; /* Don't time out */
5778 cmd->Request.CDB[0] = opcode;
5779 cmd->Request.CDB[1] = type;
5780 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
5781 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
5782 cmd->ErrorDescriptor.Addr.upper = 0;
5783 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
5784
5785 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
5786
5787 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5788 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
a9a3a273 5789 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
edd16368
SC		 5790 break;
5791 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5792 }
5793
5794 iounmap(vaddr);
5795
5796 /* we leak the DMA buffer here ... no choice since the controller could
5797 * still complete the command.
5798 */
5799 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5800 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5801 opcode, type);
5802 return -ETIMEDOUT;
5803 }
5804
5805 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5806
5807 if (tag & HPSA_ERROR_BIT) {
5808 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5809 opcode, type);
5810 return -EIO;
5811 }
5812
5813 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5814 opcode, type);
5815 return 0;
5816}
5817
edd16368
SC		 5818#define hpsa_noop(p) hpsa_message(p, 3, 0)
5819
1df8552a 5820static int hpsa_controller_hard_reset(struct pci_dev *pdev,
cf0b08d0 5821 void * __iomem vaddr, u32 use_doorbell)
1df8552a
SC		 5822{
5823 u16 pmcsr;
5824 int pos;
5825
5826 if (use_doorbell) {
5827 /* For everything after the P600, the PCI power state method
5828 * of resetting the controller doesn't work, so we have this
5829 * other way using the doorbell register.
5830 */
5831 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5832 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 5833
00701a96 5834 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 5835 * doorbell reset and before any attempt to talk to the board
5836 * at all to ensure that this actually works and doesn't fall
5837 * over in some weird corner cases.
5838 */
00701a96 5839 msleep(10000);
1df8552a
SC		 5840 } else { /* Try to do it the PCI power state way */
5841
5842 /* Quoting from the Open CISS Specification: "The Power
5843 * Management Control/Status Register (CSR) controls the power
5844 * state of the device. The normal operating state is D0,
5845 * CSR=00h. The software off state is D3, CSR=03h. To reset
5846 * the controller, place the interface device in D3 then to D0,
5847 * this causes a secondary PCI reset which will reset the
5848 * controller." */
5849
5850 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
5851 if (pos == 0) {
5852 dev_err(&pdev->dev,
5853 "hpsa_reset_controller: "
5854 "PCI PM not supported\n");
5855 return -ENODEV;
5856 }
5857 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
5858 /* enter the D3hot power management state */
5859 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
5860 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5861 pmcsr |= PCI_D3hot;
5862 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
5863
5864 msleep(500);
5865
5866 /* enter the D0 power management state */
5867 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5868 pmcsr |= PCI_D0;
5869 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
c4853efe
MM		 5870
5871 /*
5872 * The P600 requires a small delay when changing states.
5873 * Otherwise we may think the board did not reset and we bail.
5874 * This for kdump only and is particular to the P600.
5875 */
5876 msleep(500);
1df8552a
SC		 5877 }
5878 return 0;
5879}
5880
6f039790 5881static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5882{
5883 memset(driver_version, 0, len);
f79cfec6 5884 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5885}
5886
6f039790 5887static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5888{
5889 char *driver_version;
5890 int i, size = sizeof(cfgtable->driver_version);
5891
5892 driver_version = kmalloc(size, GFP_KERNEL);
5893 if (!driver_version)
5894 return -ENOMEM;
5895
5896 init_driver_version(driver_version, size);
5897 for (i = 0; i < size; i++)
5898 writeb(driver_version[i], &cfgtable->driver_version[i]);
5899 kfree(driver_version);
5900 return 0;
5901}
5902
6f039790
GKH		 5903static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5904 unsigned char *driver_ver)
580ada3c
SC		 5905{
5906 int i;
5907
5908 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5909 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5910}
5911
6f039790 5912static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5913{
5914
5915 char *driver_ver, *old_driver_ver;
5916 int rc, size = sizeof(cfgtable->driver_version);
5917
5918 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5919 if (!old_driver_ver)
5920 return -ENOMEM;
5921 driver_ver = old_driver_ver + size;
5922
5923 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5924 * should have been changed, otherwise we know the reset failed.
5925 */
5926 init_driver_version(old_driver_ver, size);
5927 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5928 rc = !memcmp(driver_ver, old_driver_ver, size);
5929 kfree(old_driver_ver);
5930 return rc;
5931}
edd16368 5932/* This does a hard reset of the controller using PCI power management
1df8552a 5933 * states or the using the doorbell register.
edd16368 5934 */
6f039790 5935static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5936{
1df8552a
SC		 5937 u64 cfg_offset;
5938 u32 cfg_base_addr;
5939 u64 cfg_base_addr_index;
5940 void __iomem *vaddr;
5941 unsigned long paddr;
580ada3c 5942 u32 misc_fw_support;
270d05de 5943 int rc;
1df8552a 5944 struct CfgTable __iomem *cfgtable;
cf0b08d0 5945 u32 use_doorbell;
18867659 5946 u32 board_id;
270d05de 5947 u16 command_register;
edd16368 5948
1df8552a
SC		 5949 /* For controllers as old as the P600, this is very nearly
5950 * the same thing as
edd16368
SC		 5951 *
5952 * pci_save_state(pci_dev);
5953 * pci_set_power_state(pci_dev, PCI_D3hot);
5954 * pci_set_power_state(pci_dev, PCI_D0);
5955 * pci_restore_state(pci_dev);
5956 *
1df8552a
SC		 5957 * For controllers newer than the P600, the pci power state
5958 * method of resetting doesn't work so we have another way
5959 * using the doorbell register.
edd16368 5960 */
18867659 5961
25c1e56a 5962 rc = hpsa_lookup_board_id(pdev, &board_id);
46380786 5963 if (rc < 0 || !ctlr_is_resettable(board_id)) {
25c1e56a
SC		 5964 dev_warn(&pdev->dev, "Not resetting device.\n");
5965 return -ENODEV;
5966 }
46380786
SC		 5967
5968 /* if controller is soft- but not hard resettable... */
5969 if (!ctlr_is_hard_resettable(board_id))
5970 return -ENOTSUPP; /* try soft reset later. */
18867659 5971
270d05de
SC		 5972 /* Save the PCI command register */
5973 pci_read_config_word(pdev, 4, &command_register);
5974 /* Turn the board off. This is so that later pci_restore_state()
5975 * won't turn the board on before the rest of config space is ready.
5976 */
5977 pci_disable_device(pdev);
5978 pci_save_state(pdev);
edd16368 5979
1df8552a
SC		 5980 /* find the first memory BAR, so we can find the cfg table */
5981 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5982 if (rc)
5983 return rc;
5984 vaddr = remap_pci_mem(paddr, 0x250);
5985 if (!vaddr)
5986 return -ENOMEM;
edd16368 5987
1df8552a
SC		 5988 /* find cfgtable in order to check if reset via doorbell is supported */
5989 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
5990 &cfg_base_addr_index, &cfg_offset);
5991 if (rc)
5992 goto unmap_vaddr;
5993 cfgtable = remap_pci_mem(pci_resource_start(pdev,
5994 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
5995 if (!cfgtable) {
5996 rc = -ENOMEM;
5997 goto unmap_vaddr;
5998 }
580ada3c
SC		 5999 rc = write_driver_ver_to_cfgtable(cfgtable);
6000 if (rc)
6001 goto unmap_vaddr;
edd16368 6002
cf0b08d0
SC		 6003 /* If reset via doorbell register is supported, use that.
6004 * There are two such methods. Favor the newest method.
6005 */
1df8552a 6006 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6007 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6008 if (use_doorbell) {
6009 use_doorbell = DOORBELL_CTLR_RESET2;
6010 } else {
6011 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6012 if (use_doorbell) {
fba63097
MM		 6013 dev_warn(&pdev->dev, "Soft reset not supported. "
6014 "Firmware update is required.\n");
64670ac8 6015 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6016 goto unmap_cfgtable;
6017 }
6018 }
edd16368 6019
1df8552a
SC		 6020 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6021 if (rc)
6022 goto unmap_cfgtable;
edd16368 6023
270d05de
SC		 6024 pci_restore_state(pdev);
6025 rc = pci_enable_device(pdev);
6026 if (rc) {
6027 dev_warn(&pdev->dev, "failed to enable device.\n");
6028 goto unmap_cfgtable;
edd16368 6029 }
270d05de 6030 pci_write_config_word(pdev, 4, command_register);
edd16368 6031
1df8552a
SC		 6032 /* Some devices (notably the HP Smart Array 5i Controller)
6033 need a little pause here */
6034 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6035
fe5389c8
SC		 6036 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6037 if (rc) {
6038 dev_warn(&pdev->dev,
64670ac8
SC		 6039 "failed waiting for board to become ready "
6040 "after hard reset\n");
fe5389c8
SC		 6041 goto unmap_cfgtable;
6042 }
fe5389c8 6043
580ada3c
SC		 6044 rc = controller_reset_failed(vaddr);
6045 if (rc < 0)
6046 goto unmap_cfgtable;
6047 if (rc) {
64670ac8
SC		 6048 dev_warn(&pdev->dev, "Unable to successfully reset "
6049 "controller. Will try soft reset.\n");
6050 rc = -ENOTSUPP;
580ada3c 6051 } else {
64670ac8 6052 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6053 }
6054
6055unmap_cfgtable:
6056 iounmap(cfgtable);
6057
6058unmap_vaddr:
6059 iounmap(vaddr);
6060 return rc;
edd16368
SC		 6061}
6062
6063/*
6064 * We cannot read the structure directly, for portability we must use
6065 * the io functions.
6066 * This is for debug only.
6067 */
edd16368
SC		 6068static void print_cfg_table(struct device *dev, struct CfgTable *tb)
6069{
58f8665c 6070#ifdef HPSA_DEBUG
edd16368
SC		 6071 int i;
6072 char temp_name[17];
6073
6074 dev_info(dev, "Controller Configuration information\n");
6075 dev_info(dev, "------------------------------------\n");
6076 for (i = 0; i < 4; i++)
6077 temp_name[i] = readb(&(tb->Signature[i]));
6078 temp_name[4] = '\0';
6079 dev_info(dev, " Signature = %s\n", temp_name);
6080 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6081 dev_info(dev, " Transport methods supported = 0x%x\n",
6082 readl(&(tb->TransportSupport)));
6083 dev_info(dev, " Transport methods active = 0x%x\n",
6084 readl(&(tb->TransportActive)));
6085 dev_info(dev, " Requested transport Method = 0x%x\n",
6086 readl(&(tb->HostWrite.TransportRequest)));
6087 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6088 readl(&(tb->HostWrite.CoalIntDelay)));
6089 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6090 readl(&(tb->HostWrite.CoalIntCount)));
6091 dev_info(dev, " Max outstanding commands = 0x%d\n",
6092 readl(&(tb->CmdsOutMax)));
6093 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6094 for (i = 0; i < 16; i++)
6095 temp_name[i] = readb(&(tb->ServerName[i]));
6096 temp_name[16] = '\0';
6097 dev_info(dev, " Server Name = %s\n", temp_name);
6098 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6099 readl(&(tb->HeartBeat)));
edd16368 6100#endif /* HPSA_DEBUG */
58f8665c 6101}
edd16368
SC		 6102
6103static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6104{
6105 int i, offset, mem_type, bar_type;
6106
6107 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6108 return 0;
6109 offset = 0;
6110 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6111 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6112 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6113 offset += 4;
6114 else {
6115 mem_type = pci_resource_flags(pdev, i) &
6116 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6117 switch (mem_type) {
6118 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6119 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6120 offset += 4; /* 32 bit */
6121 break;
6122 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6123 offset += 8;
6124 break;
6125 default: /* reserved in PCI 2.2 */
6126 dev_warn(&pdev->dev,
6127 "base address is invalid\n");
6128 return -1;
6129 break;
6130 }
6131 }
6132 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6133 return i + 1;
6134 }
6135 return -1;
6136}
6137
6138/* If MSI/MSI-X is supported by the kernel we will try to enable it on
6139 * controllers that are capable. If not, we use IO-APIC mode.
6140 */
6141
6f039790 6142static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6143{
6144#ifdef CONFIG_PCI_MSI
254f796b
MG		 6145 int err, i;
6146 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6147
6148 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6149 hpsa_msix_entries[i].vector = 0;
6150 hpsa_msix_entries[i].entry = i;
6151 }
edd16368
SC		 6152
6153 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6154 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6155 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6156 goto default_int_mode;
55c06c71
SC		 6157 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
6158 dev_info(&h->pdev->dev, "MSIX\n");
eee0f03a 6159 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 6160 if (h->msix_vector > num_online_cpus())
6161 h->msix_vector = num_online_cpus();
254f796b 6162 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
eee0f03a 6163 h->msix_vector);
edd16368 6164 if (err > 0) {
55c06c71 6165 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 6166 "available\n", err);
eee0f03a
HR		 6167 h->msix_vector = err;
6168 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
6169 h->msix_vector);
6170 }
6171 if (!err) {
6172 for (i = 0; i < h->msix_vector; i++)
6173 h->intr[i] = hpsa_msix_entries[i].vector;
6174 return;
edd16368 6175 } else {
55c06c71 6176 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
edd16368 6177 err);
eee0f03a 6178 h->msix_vector = 0;
edd16368
SC		 6179 goto default_int_mode;
6180 }
6181 }
55c06c71
SC		 6182 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
6183 dev_info(&h->pdev->dev, "MSI\n");
6184 if (!pci_enable_msi(h->pdev))
edd16368
SC		 6185 h->msi_vector = 1;
6186 else
55c06c71 6187 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 6188 }
6189default_int_mode:
6190#endif /* CONFIG_PCI_MSI */
6191 /* if we get here we're going to use the default interrupt mode */
a9a3a273 6192 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 6193}
6194
6f039790 6195static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 6196{
6197 int i;
6198 u32 subsystem_vendor_id, subsystem_device_id;
6199
6200 subsystem_vendor_id = pdev->subsystem_vendor;
6201 subsystem_device_id = pdev->subsystem_device;
6202 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
6203 subsystem_vendor_id;
6204
6205 for (i = 0; i < ARRAY_SIZE(products); i++)
6206 if (*board_id == products[i].board_id)
6207 return i;
6208
6798cc0a
SC		 6209 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
6210 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
6211 !hpsa_allow_any) {
e5c880d1
SC		 6212 dev_warn(&pdev->dev, "unrecognized board ID: "
6213 "0x%08x, ignoring.\n", *board_id);
6214 return -ENODEV;
6215 }
6216 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
6217}
6218
6f039790
GKH		 6219static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
6220 unsigned long *memory_bar)
3a7774ce
SC		 6221{
6222 int i;
6223
6224 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 6225 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 6226 /* addressing mode bits already removed */
12d2cd47
SC		 6227 *memory_bar = pci_resource_start(pdev, i);
6228 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 6229 *memory_bar);
6230 return 0;
6231 }
12d2cd47 6232 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 6233 return -ENODEV;
6234}
6235
6f039790
GKH		 6236static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
6237 int wait_for_ready)
2c4c8c8b 6238{
fe5389c8 6239 int i, iterations;
2c4c8c8b 6240 u32 scratchpad;
fe5389c8
SC		 6241 if (wait_for_ready)
6242 iterations = HPSA_BOARD_READY_ITERATIONS;
6243 else
6244 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 6245
fe5389c8
SC		 6246 for (i = 0; i < iterations; i++) {
6247 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
6248 if (wait_for_ready) {
6249 if (scratchpad == HPSA_FIRMWARE_READY)
6250 return 0;
6251 } else {
6252 if (scratchpad != HPSA_FIRMWARE_READY)
6253 return 0;
6254 }
2c4c8c8b
SC		 6255 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
6256 }
fe5389c8 6257 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 6258 return -ENODEV;
6259}
6260
6f039790
GKH		 6261static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
6262 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
6263 u64 *cfg_offset)
a51fd47f
SC		 6264{
6265 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
6266 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
6267 *cfg_base_addr &= (u32) 0x0000ffff;
6268 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
6269 if (*cfg_base_addr_index == -1) {
6270 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
6271 return -ENODEV;
6272 }
6273 return 0;
6274}
6275
6f039790 6276static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 6277{
01a02ffc
SC		 6278 u64 cfg_offset;
6279 u32 cfg_base_addr;
6280 u64 cfg_base_addr_index;
303932fd 6281 u32 trans_offset;
a51fd47f 6282 int rc;
77c4495c 6283
a51fd47f
SC		 6284 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6285 &cfg_base_addr_index, &cfg_offset);
6286 if (rc)
6287 return rc;
77c4495c 6288 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 6289 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
77c4495c
SC		 6290 if (!h->cfgtable)
6291 return -ENOMEM;
580ada3c
SC		 6292 rc = write_driver_ver_to_cfgtable(h->cfgtable);
6293 if (rc)
6294 return rc;
77c4495c 6295 /* Find performant mode table. */
a51fd47f 6296 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 6297 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
6298 cfg_base_addr_index)+cfg_offset+trans_offset,
6299 sizeof(*h->transtable));
6300 if (!h->transtable)
6301 return -ENOMEM;
6302 return 0;
6303}
6304
6f039790 6305static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 6306{
6307 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 6308
6309 /* Limit commands in memory limited kdump scenario. */
6310 if (reset_devices && h->max_commands > 32)
6311 h->max_commands = 32;
6312
cba3d38b
SC		 6313 if (h->max_commands < 16) {
6314 dev_warn(&h->pdev->dev, "Controller reports "
6315 "max supported commands of %d, an obvious lie. "
6316 "Using 16. Ensure that firmware is up to date.\n",
6317 h->max_commands);
6318 h->max_commands = 16;
6319 }
6320}
6321
b93d7536
SC		 6322/* Interrogate the hardware for some limits:
6323 * max commands, max SG elements without chaining, and with chaining,
6324 * SG chain block size, etc.
6325 */
6f039790 6326static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 6327{
cba3d38b 6328 hpsa_get_max_perf_mode_cmds(h);
b93d7536
SC		 6329 h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
6330 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 6331 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
b93d7536
SC		 6332 /*
6333 * Limit in-command s/g elements to 32 save dma'able memory.
6334 * Howvever spec says if 0, use 31
6335 */
6336 h->max_cmd_sg_entries = 31;
6337 if (h->maxsgentries > 512) {
6338 h->max_cmd_sg_entries = 32;
6339 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
6340 h->maxsgentries--; /* save one for chain pointer */
6341 } else {
6342 h->maxsgentries = 31; /* default to traditional values */
6343 h->chainsize = 0;
6344 }
75167d2c
SC		 6345
6346 /* Find out what task management functions are supported and cache */
6347 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 6348 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
6349 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
6350 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6351 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 6352}
6353
76c46e49
SC		 6354static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
6355{
0fc9fd40 6356 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
76c46e49
SC		 6357 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
6358 return false;
6359 }
6360 return true;
6361}
6362
97a5e98c 6363static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 6364{
97a5e98c 6365 u32 driver_support;
f7c39101 6366
28e13446
SC		 6367#ifdef CONFIG_X86
6368 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
97a5e98c
SC		 6369 driver_support = readl(&(h->cfgtable->driver_support));
6370 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 6371#endif
28e13446
SC		 6372 driver_support |= ENABLE_UNIT_ATTN;
6373 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 6374}
6375
3d0eab67
SC		 6376/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
6377 * in a prefetch beyond physical memory.
6378 */
6379static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
6380{
6381 u32 dma_prefetch;
6382
6383 if (h->board_id != 0x3225103C)
6384 return;
6385 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
6386 dma_prefetch |= 0x8000;
6387 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
6388}
6389
76438d08
SC		 6390static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
6391{
6392 int i;
6393 u32 doorbell_value;
6394 unsigned long flags;
6395 /* wait until the clear_event_notify bit 6 is cleared by controller. */
6396 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6397 spin_lock_irqsave(&h->lock, flags);
6398 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6399 spin_unlock_irqrestore(&h->lock, flags);
6400 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
6401 break;
6402 /* delay and try again */
6403 msleep(20);
6404 }
6405}
6406
6f039790 6407static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 6408{
6409 int i;
6eaf46fd
SC		 6410 u32 doorbell_value;
6411 unsigned long flags;
eb6b2ae9
SC		 6412
6413 /* under certain very rare conditions, this can take awhile.
6414 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
6415 * as we enter this code.)
6416 */
6417 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 6418 spin_lock_irqsave(&h->lock, flags);
6419 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6420 spin_unlock_irqrestore(&h->lock, flags);
382be668 6421 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 6422 break;
6423 /* delay and try again */
60d3f5b0 6424 usleep_range(10000, 20000);
eb6b2ae9 6425 }
3f4336f3
SC		 6426}
6427
6f039790 6428static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6429{
6430 u32 trans_support;
6431
6432 trans_support = readl(&(h->cfgtable->TransportSupport));
6433 if (!(trans_support & SIMPLE_MODE))
6434 return -ENOTSUPP;
6435
6436 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6437
3f4336f3
SC		 6438 /* Update the field, and then ring the doorbell */
6439 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6440 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 6441 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6442 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 6443 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6444 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6445 goto error;
960a30e7 6446 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6447 return 0;
283b4a9b
SC		 6448error:
6449 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
6450 return -ENODEV;
eb6b2ae9
SC		 6451}
6452
6f039790 6453static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6454{
eb6b2ae9 6455 int prod_index, err;
edd16368 6456
e5c880d1
SC		 6457 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6458 if (prod_index < 0)
6459 return -ENODEV;
6460 h->product_name = products[prod_index].product_name;
6461 h->access = *(products[prod_index].access);
edd16368 6462
e5a44df8
MG		 6463 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6464 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6465
55c06c71 6466 err = pci_enable_device(h->pdev);
edd16368 6467 if (err) {
55c06c71 6468 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 6469 return err;
6470 }
6471
5cb460a6
SC		 6472 /* Enable bus mastering (pci_disable_device may disable this) */
6473 pci_set_master(h->pdev);
6474
f79cfec6 6475 err = pci_request_regions(h->pdev, HPSA);
edd16368 6476 if (err) {
55c06c71
SC		 6477 dev_err(&h->pdev->dev,
6478 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 6479 return err;
6480 }
6b3f4c52 6481 hpsa_interrupt_mode(h);
12d2cd47 6482 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6483 if (err)
edd16368 6484 goto err_out_free_res;
edd16368 6485 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 6486 if (!h->vaddr) {
6487 err = -ENOMEM;
6488 goto err_out_free_res;
6489 }
fe5389c8 6490 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6491 if (err)
edd16368 6492 goto err_out_free_res;
77c4495c
SC		 6493 err = hpsa_find_cfgtables(h);
6494 if (err)
edd16368 6495 goto err_out_free_res;
b93d7536 6496 hpsa_find_board_params(h);
edd16368 6497
76c46e49 6498 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 6499 err = -ENODEV;
6500 goto err_out_free_res;
6501 }
97a5e98c 6502 hpsa_set_driver_support_bits(h);
3d0eab67 6503 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6504 err = hpsa_enter_simple_mode(h);
6505 if (err)
edd16368 6506 goto err_out_free_res;
edd16368
SC		 6507 return 0;
6508
6509err_out_free_res:
204892e9
SC		 6510 if (h->transtable)
6511 iounmap(h->transtable);
6512 if (h->cfgtable)
6513 iounmap(h->cfgtable);
6514 if (h->vaddr)
6515 iounmap(h->vaddr);
f0bd0b68 6516 pci_disable_device(h->pdev);
55c06c71 6517 pci_release_regions(h->pdev);
edd16368
SC		 6518 return err;
6519}
6520
6f039790 6521static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6522{
6523 int rc;
6524
6525#define HBA_INQUIRY_BYTE_COUNT 64
6526 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6527 if (!h->hba_inquiry_data)
6528 return;
6529 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6530 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6531 if (rc != 0) {
6532 kfree(h->hba_inquiry_data);
6533 h->hba_inquiry_data = NULL;
6534 }
6535}
6536
6f039790 6537static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 6538{
1df8552a 6539 int rc, i;
4c2a8c40
SC		 6540
6541 if (!reset_devices)
6542 return 0;
6543
1df8552a
SC		 6544 /* Reset the controller with a PCI power-cycle or via doorbell */
6545 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 6546
1df8552a
SC		 6547 /* -ENOTSUPP here means we cannot reset the controller
6548 * but it's already (and still) up and running in
18867659
SC		 6549 * "performant mode". Or, it might be 640x, which can't reset
6550 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a
SC		 6551 */
6552 if (rc == -ENOTSUPP)
64670ac8 6553 return rc; /* just try to do the kdump anyhow. */
1df8552a
SC		 6554 if (rc)
6555 return -ENODEV;
4c2a8c40
SC		 6556
6557 /* Now try to get the controller to respond to a no-op */
2b870cb3 6558 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6559 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6560 if (hpsa_noop(pdev) == 0)
6561 break;
6562 else
6563 dev_warn(&pdev->dev, "no-op failed%s\n",
6564 (i < 11 ? "; re-trying" : ""));
6565 }
6566 return 0;
6567}
6568
6f039790 6569static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6570{
6571 h->cmd_pool_bits = kzalloc(
6572 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6573 sizeof(unsigned long), GFP_KERNEL);
6574 h->cmd_pool = pci_alloc_consistent(h->pdev,
6575 h->nr_cmds * sizeof(*h->cmd_pool),
6576 &(h->cmd_pool_dhandle));
6577 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6578 h->nr_cmds * sizeof(*h->errinfo_pool),
6579 &(h->errinfo_pool_dhandle));
6580 if ((h->cmd_pool_bits == NULL)
6581 || (h->cmd_pool == NULL)
6582 || (h->errinfo_pool == NULL)) {
6583 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
6584 return -ENOMEM;
6585 }
6586 return 0;
6587}
6588
6589static void hpsa_free_cmd_pool(struct ctlr_info *h)
6590{
6591 kfree(h->cmd_pool_bits);
6592 if (h->cmd_pool)
6593 pci_free_consistent(h->pdev,
6594 h->nr_cmds * sizeof(struct CommandList),
6595 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 6596 if (h->ioaccel2_cmd_pool)
6597 pci_free_consistent(h->pdev,
6598 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6599 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 6600 if (h->errinfo_pool)
6601 pci_free_consistent(h->pdev,
6602 h->nr_cmds * sizeof(struct ErrorInfo),
6603 h->errinfo_pool,
6604 h->errinfo_pool_dhandle);
e1f7de0c
MG		 6605 if (h->ioaccel_cmd_pool)
6606 pci_free_consistent(h->pdev,
6607 h->nr_cmds * sizeof(struct io_accel1_cmd),
6608 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 6609}
6610
41b3cf08
SC		 6611static void hpsa_irq_affinity_hints(struct ctlr_info *h)
6612{
6613 int i, cpu, rc;
6614
6615 cpu = cpumask_first(cpu_online_mask);
6616 for (i = 0; i < h->msix_vector; i++) {
6617 rc = irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
6618 cpu = cpumask_next(cpu, cpu_online_mask);
6619 }
6620}
6621
0ae01a32
SC		 6622static int hpsa_request_irq(struct ctlr_info *h,
6623 irqreturn_t (*msixhandler)(int, void *),
6624 irqreturn_t (*intxhandler)(int, void *))
6625{
254f796b 6626 int rc, i;
0ae01a32 6627
254f796b
MG		 6628 /*
6629 * initialize h->q[x] = x so that interrupt handlers know which
6630 * queue to process.
6631 */
6632 for (i = 0; i < MAX_REPLY_QUEUES; i++)
6633 h->q[i] = (u8) i;
6634
eee0f03a 6635 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 6636 /* If performant mode and MSI-X, use multiple reply queues */
eee0f03a 6637 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 6638 rc = request_irq(h->intr[i], msixhandler,
6639 0, h->devname,
6640 &h->q[i]);
41b3cf08 6641 hpsa_irq_affinity_hints(h);
254f796b
MG		 6642 } else {
6643 /* Use single reply pool */
eee0f03a 6644 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 6645 rc = request_irq(h->intr[h->intr_mode],
6646 msixhandler, 0, h->devname,
6647 &h->q[h->intr_mode]);
6648 } else {
6649 rc = request_irq(h->intr[h->intr_mode],
6650 intxhandler, IRQF_SHARED, h->devname,
6651 &h->q[h->intr_mode]);
6652 }
6653 }
0ae01a32
SC		 6654 if (rc) {
6655 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
6656 h->intr[h->intr_mode], h->devname);
6657 return -ENODEV;
6658 }
6659 return 0;
6660}
6661
6f039790 6662static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 6663{
6664 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6665 HPSA_RESET_TYPE_CONTROLLER)) {
6666 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6667 return -EIO;
6668 }
6669
6670 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6671 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6672 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6673 return -1;
6674 }
6675
6676 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6677 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
6678 dev_warn(&h->pdev->dev, "Board failed to become ready "
6679 "after soft reset.\n");
6680 return -1;
6681 }
6682
6683 return 0;
6684}
6685
254f796b
MG		 6686static void free_irqs(struct ctlr_info *h)
6687{
6688 int i;
6689
6690 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6691 /* Single reply queue, only one irq to free */
6692 i = h->intr_mode;
41b3cf08 6693 irq_set_affinity_hint(h->intr[i], NULL);
254f796b
MG		 6694 free_irq(h->intr[i], &h->q[i]);
6695 return;
6696 }
6697
41b3cf08
SC		 6698 for (i = 0; i < h->msix_vector; i++) {
6699 irq_set_affinity_hint(h->intr[i], NULL);
254f796b 6700 free_irq(h->intr[i], &h->q[i]);
41b3cf08 6701 }
254f796b
MG		 6702}
6703
0097f0f4 6704static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 6705{
254f796b 6706 free_irqs(h);
64670ac8 6707#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6708 if (h->msix_vector) {
6709 if (h->pdev->msix_enabled)
6710 pci_disable_msix(h->pdev);
6711 } else if (h->msi_vector) {
6712 if (h->pdev->msi_enabled)
6713 pci_disable_msi(h->pdev);
6714 }
64670ac8 6715#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6716}
6717
072b0518
SC		 6718static void hpsa_free_reply_queues(struct ctlr_info *h)
6719{
6720 int i;
6721
6722 for (i = 0; i < h->nreply_queues; i++) {
6723 if (!h->reply_queue[i].head)
6724 continue;
6725 pci_free_consistent(h->pdev, h->reply_queue_size,
6726 h->reply_queue[i].head, h->reply_queue[i].busaddr);
6727 h->reply_queue[i].head = NULL;
6728 h->reply_queue[i].busaddr = 0;
6729 }
6730}
6731
0097f0f4
SC		 6732static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6733{
6734 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6735 hpsa_free_sg_chain_blocks(h);
6736 hpsa_free_cmd_pool(h);
e1f7de0c 6737 kfree(h->ioaccel1_blockFetchTable);
64670ac8 6738 kfree(h->blockFetchTable);
072b0518 6739 hpsa_free_reply_queues(h);
64670ac8
SC		 6740 if (h->vaddr)
6741 iounmap(h->vaddr);
6742 if (h->transtable)
6743 iounmap(h->transtable);
6744 if (h->cfgtable)
6745 iounmap(h->cfgtable);
6746 pci_release_regions(h->pdev);
6747 kfree(h);
6748}
6749
a0c12413
SC		 6750/* Called when controller lockup detected. */
6751static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
6752{
6753 struct CommandList *c = NULL;
6754
6755 assert_spin_locked(&h->lock);
6756 /* Mark all outstanding commands as failed and complete them. */
6757 while (!list_empty(list)) {
6758 c = list_entry(list->next, struct CommandList, list);
6759 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 6760 finish_cmd(c);
a0c12413
SC		 6761 }
6762}
6763
094963da
SC		 6764static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
6765{
6766 int i, cpu;
6767
6768 cpu = cpumask_first(cpu_online_mask);
6769 for (i = 0; i < num_online_cpus(); i++) {
6770 u32 *lockup_detected;
6771 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
6772 *lockup_detected = value;
6773 cpu = cpumask_next(cpu, cpu_online_mask);
6774 }
6775 wmb(); /* be sure the per-cpu variables are out to memory */
6776}
6777
a0c12413
SC		 6778static void controller_lockup_detected(struct ctlr_info *h)
6779{
6780 unsigned long flags;
094963da 6781 u32 lockup_detected;
a0c12413 6782
a0c12413
SC		 6783 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6784 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 6785 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6786 if (!lockup_detected) {
6787 /* no heartbeat, but controller gave us a zero. */
6788 dev_warn(&h->pdev->dev,
6789 "lockup detected but scratchpad register is zero\n");
6790 lockup_detected = 0xffffffff;
6791 }
6792 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413
SC		 6793 spin_unlock_irqrestore(&h->lock, flags);
6794 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
094963da 6795 lockup_detected);
a0c12413
SC		 6796 pci_disable_device(h->pdev);
6797 spin_lock_irqsave(&h->lock, flags);
6798 fail_all_cmds_on_list(h, &h->cmpQ);
6799 fail_all_cmds_on_list(h, &h->reqQ);
6800 spin_unlock_irqrestore(&h->lock, flags);
6801}
6802
a0c12413
SC		 6803static void detect_controller_lockup(struct ctlr_info *h)
6804{
6805 u64 now;
6806 u32 heartbeat;
6807 unsigned long flags;
6808
a0c12413
SC		 6809 now = get_jiffies_64();
6810 /* If we've received an interrupt recently, we're ok. */
6811 if (time_after64(h->last_intr_timestamp +
e85c5974 6812 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6813 return;
6814
6815 /*
6816 * If we've already checked the heartbeat recently, we're ok.
6817 * This could happen if someone sends us a signal. We
6818 * otherwise don't care about signals in this thread.
6819 */
6820 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6821 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6822 return;
6823
6824 /* If heartbeat has not changed since we last looked, we're not ok. */
6825 spin_lock_irqsave(&h->lock, flags);
6826 heartbeat = readl(&h->cfgtable->HeartBeat);
6827 spin_unlock_irqrestore(&h->lock, flags);
6828 if (h->last_heartbeat == heartbeat) {
6829 controller_lockup_detected(h);
6830 return;
6831 }
6832
6833 /* We're ok. */
6834 h->last_heartbeat = heartbeat;
6835 h->last_heartbeat_timestamp = now;
6836}
6837
9846590e 6838static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 6839{
6840 int i;
6841 char *event_type;
6842
e863d68e
ST		 6843 /* Clear the driver-requested rescan flag */
6844 h->drv_req_rescan = 0;
6845
76438d08 6846 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6847 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6848 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6849 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6850 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6851
6852 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6853 event_type = "state change";
6854 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6855 event_type = "configuration change";
6856 /* Stop sending new RAID offload reqs via the IO accelerator */
6857 scsi_block_requests(h->scsi_host);
6858 for (i = 0; i < h->ndevices; i++)
6859 h->dev[i]->offload_enabled = 0;
23100dd9 6860 hpsa_drain_accel_commands(h);
76438d08
SC		 6861 /* Set 'accelerator path config change' bit */
6862 dev_warn(&h->pdev->dev,
6863 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
6864 h->events, event_type);
6865 writel(h->events, &(h->cfgtable->clear_event_notify));
6866 /* Set the "clear event notify field update" bit 6 */
6867 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6868 /* Wait until ctlr clears 'clear event notify field', bit 6 */
6869 hpsa_wait_for_clear_event_notify_ack(h);
6870 scsi_unblock_requests(h->scsi_host);
6871 } else {
6872 /* Acknowledge controller notification events. */
6873 writel(h->events, &(h->cfgtable->clear_event_notify));
6874 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6875 hpsa_wait_for_clear_event_notify_ack(h);
6876#if 0
6877 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6878 hpsa_wait_for_mode_change_ack(h);
6879#endif
6880 }
9846590e 6881 return;
76438d08
SC		 6882}
6883
6884/* Check a register on the controller to see if there are configuration
6885 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 6886 * we should rescan the controller for devices.
6887 * Also check flag for driver-initiated rescan.
76438d08 6888 */
9846590e 6889static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 6890{
9846590e
SC		 6891 if (h->drv_req_rescan)
6892 return 1;
6893
76438d08 6894 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 6895 return 0;
76438d08
SC		 6896
6897 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 6898 return h->events & RESCAN_REQUIRED_EVENT_BITS;
6899}
76438d08 6900
9846590e
SC		 6901/*
6902 * Check if any of the offline devices have become ready
6903 */
6904static int hpsa_offline_devices_ready(struct ctlr_info *h)
6905{
6906 unsigned long flags;
6907 struct offline_device_entry *d;
6908 struct list_head *this, *tmp;
6909
6910 spin_lock_irqsave(&h->offline_device_lock, flags);
6911 list_for_each_safe(this, tmp, &h->offline_device_list) {
6912 d = list_entry(this, struct offline_device_entry,
6913 offline_list);
6914 spin_unlock_irqrestore(&h->offline_device_lock, flags);
6915 if (!hpsa_volume_offline(h, d->scsi3addr))
6916 return 1;
6917 spin_lock_irqsave(&h->offline_device_lock, flags);
6918 }
6919 spin_unlock_irqrestore(&h->offline_device_lock, flags);
6920 return 0;
76438d08
SC		 6921}
6922
9846590e 6923
8a98db73 6924static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6925{
6926 unsigned long flags;
8a98db73
SC		 6927 struct ctlr_info *h = container_of(to_delayed_work(work),
6928 struct ctlr_info, monitor_ctlr_work);
6929 detect_controller_lockup(h);
094963da 6930 if (lockup_detected(h))
8a98db73 6931 return;
9846590e
SC		 6932
6933 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
6934 scsi_host_get(h->scsi_host);
6935 h->drv_req_rescan = 0;
6936 hpsa_ack_ctlr_events(h);
6937 hpsa_scan_start(h->scsi_host);
6938 scsi_host_put(h->scsi_host);
6939 }
6940
8a98db73
SC		 6941 spin_lock_irqsave(&h->lock, flags);
6942 if (h->remove_in_progress) {
6943 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6944 return;
6945 }
8a98db73
SC		 6946 schedule_delayed_work(&h->monitor_ctlr_work,
6947 h->heartbeat_sample_interval);
6948 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6949}
6950
6f039790 6951static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6952{
4c2a8c40 6953 int dac, rc;
edd16368 6954 struct ctlr_info *h;
64670ac8
SC		 6955 int try_soft_reset = 0;
6956 unsigned long flags;
edd16368
SC		 6957
6958 if (number_of_controllers == 0)
6959 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6960
4c2a8c40 6961 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6962 if (rc) {
6963 if (rc != -ENOTSUPP)
6964 return rc;
6965 /* If the reset fails in a particular way (it has no way to do
6966 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6967 * a soft reset once we get the controller configured up to the
6968 * point that it can accept a command.
6969 */
6970 try_soft_reset = 1;
6971 rc = 0;
6972 }
6973
6974reinit_after_soft_reset:
edd16368 6975
303932fd
DB		 6976 /* Command structures must be aligned on a 32-byte boundary because
6977 * the 5 lower bits of the address are used by the hardware. and by
6978 * the driver. See comments in hpsa.h for more info.
6979 */
303932fd 6980 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6981 h = kzalloc(sizeof(*h), GFP_KERNEL);
6982 if (!h)
ecd9aad4 6983 return -ENOMEM;
edd16368 6984
55c06c71 6985 h->pdev = pdev;
a9a3a273 6986 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 6987 INIT_LIST_HEAD(&h->cmpQ);
6988 INIT_LIST_HEAD(&h->reqQ);
9846590e 6989 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 6990 spin_lock_init(&h->lock);
9846590e 6991 spin_lock_init(&h->offline_device_lock);
6eaf46fd 6992 spin_lock_init(&h->scan_lock);
0390f0c0 6993 spin_lock_init(&h->passthru_count_lock);
094963da
SC		 6994
6995 /* Allocate and clear per-cpu variable lockup_detected */
6996 h->lockup_detected = alloc_percpu(u32);
6997 if (!h->lockup_detected)
6998 goto clean1;
6999 set_lockup_detected_for_all_cpus(h, 0);
7000
55c06c71 7001 rc = hpsa_pci_init(h);
ecd9aad4 7002 if (rc != 0)
edd16368
SC		 7003 goto clean1;
7004
f79cfec6 7005 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 7006 h->ctlr = number_of_controllers;
7007 number_of_controllers++;
edd16368
SC		 7008
7009 /* configure PCI DMA stuff */
ecd9aad4
SC		 7010 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
7011 if (rc == 0) {
edd16368 7012 dac = 1;
ecd9aad4
SC		 7013 } else {
7014 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7015 if (rc == 0) {
7016 dac = 0;
7017 } else {
7018 dev_err(&pdev->dev, "no suitable DMA available\n");
7019 goto clean1;
7020 }
edd16368
SC		 7021 }
7022
7023 /* make sure the board interrupts are off */
7024 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 7025
0ae01a32 7026 if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 7027 goto clean2;
303932fd
DB		 7028 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
7029 h->devname, pdev->device,
a9a3a273 7030 h->intr[h->intr_mode], dac ? "" : " not");
2e9d1b36 7031 if (hpsa_allocate_cmd_pool(h))
edd16368 7032 goto clean4;
33a2ffce
SC		 7033 if (hpsa_allocate_sg_chain_blocks(h))
7034 goto clean4;
a08a8471
SC		 7035 init_waitqueue_head(&h->scan_wait_queue);
7036 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 7037
7038 pci_set_drvdata(pdev, h);
9a41338e 7039 h->ndevices = 0;
316b221a 7040 h->hba_mode_enabled = 0;
9a41338e
SC		 7041 h->scsi_host = NULL;
7042 spin_lock_init(&h->devlock);
64670ac8
SC		 7043 hpsa_put_ctlr_into_performant_mode(h);
7044
7045 /* At this point, the controller is ready to take commands.
7046 * Now, if reset_devices and the hard reset didn't work, try
7047 * the soft reset and see if that works.
7048 */
7049 if (try_soft_reset) {
7050
7051 /* This is kind of gross. We may or may not get a completion
7052 * from the soft reset command, and if we do, then the value
7053 * from the fifo may or may not be valid. So, we wait 10 secs
7054 * after the reset throwing away any completions we get during
7055 * that time. Unregister the interrupt handler and register
7056 * fake ones to scoop up any residual completions.
7057 */
7058 spin_lock_irqsave(&h->lock, flags);
7059 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7060 spin_unlock_irqrestore(&h->lock, flags);
254f796b 7061 free_irqs(h);
64670ac8
SC		 7062 rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
7063 hpsa_intx_discard_completions);
7064 if (rc) {
7065 dev_warn(&h->pdev->dev, "Failed to request_irq after "
7066 "soft reset.\n");
7067 goto clean4;
7068 }
7069
7070 rc = hpsa_kdump_soft_reset(h);
7071 if (rc)
7072 /* Neither hard nor soft reset worked, we're hosed. */
7073 goto clean4;
7074
7075 dev_info(&h->pdev->dev, "Board READY.\n");
7076 dev_info(&h->pdev->dev,
7077 "Waiting for stale completions to drain.\n");
7078 h->access.set_intr_mask(h, HPSA_INTR_ON);
7079 msleep(10000);
7080 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7081
7082 rc = controller_reset_failed(h->cfgtable);
7083 if (rc)
7084 dev_info(&h->pdev->dev,
7085 "Soft reset appears to have failed.\n");
7086
7087 /* since the controller's reset, we have to go back and re-init
7088 * everything. Easiest to just forget what we've done and do it
7089 * all over again.
7090 */
7091 hpsa_undo_allocations_after_kdump_soft_reset(h);
7092 try_soft_reset = 0;
7093 if (rc)
7094 /* don't go to clean4, we already unallocated */
7095 return -ENODEV;
7096
7097 goto reinit_after_soft_reset;
7098 }
edd16368 7099
316b221a
SC		 7100 /* Enable Accelerated IO path at driver layer */
7101 h->acciopath_status = 1;
da0697bd 7102
e863d68e
ST		 7103 h->drv_req_rescan = 0;
7104
edd16368
SC		 7105 /* Turn the interrupts on so we can service requests */
7106 h->access.set_intr_mask(h, HPSA_INTR_ON);
7107
339b2b14 7108 hpsa_hba_inquiry(h);
edd16368 7109 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 7110
7111 /* Monitor the controller for firmware lockups */
7112 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
7113 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
7114 schedule_delayed_work(&h->monitor_ctlr_work,
7115 h->heartbeat_sample_interval);
88bf6d62 7116 return 0;
edd16368
SC		 7117
7118clean4:
33a2ffce 7119 hpsa_free_sg_chain_blocks(h);
2e9d1b36 7120 hpsa_free_cmd_pool(h);
254f796b 7121 free_irqs(h);
edd16368
SC		 7122clean2:
7123clean1:
094963da
SC		 7124 if (h->lockup_detected)
7125 free_percpu(h->lockup_detected);
edd16368 7126 kfree(h);
ecd9aad4 7127 return rc;
edd16368
SC		 7128}
7129
7130static void hpsa_flush_cache(struct ctlr_info *h)
7131{
7132 char *flush_buf;
7133 struct CommandList *c;
702890e3
SC		 7134
7135 /* Don't bother trying to flush the cache if locked up */
094963da 7136 if (unlikely(lockup_detected(h)))
702890e3 7137 return;
edd16368
SC		 7138 flush_buf = kzalloc(4, GFP_KERNEL);
7139 if (!flush_buf)
7140 return;
7141
7142 c = cmd_special_alloc(h);
7143 if (!c) {
7144 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
7145 goto out_of_memory;
7146 }
a2dac136
SC		 7147 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
7148 RAID_CTLR_LUNID, TYPE_CMD)) {
7149 goto out;
7150 }
edd16368
SC		 7151 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
7152 if (c->err_info->CommandStatus != 0)
a2dac136 7153out:
edd16368
SC		 7154 dev_warn(&h->pdev->dev,
7155 "error flushing cache on controller\n");
7156 cmd_special_free(h, c);
7157out_of_memory:
7158 kfree(flush_buf);
7159}
7160
7161static void hpsa_shutdown(struct pci_dev *pdev)
7162{
7163 struct ctlr_info *h;
7164
7165 h = pci_get_drvdata(pdev);
7166 /* Turn board interrupts off and send the flush cache command
7167 * sendcmd will turn off interrupt, and send the flush...
7168 * To write all data in the battery backed cache to disks
7169 */
7170 hpsa_flush_cache(h);
7171 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 7172 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 7173}
7174
6f039790 7175static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 7176{
7177 int i;
7178
7179 for (i = 0; i < h->ndevices; i++)
7180 kfree(h->dev[i]);
7181}
7182
6f039790 7183static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 7184{
7185 struct ctlr_info *h;
8a98db73 7186 unsigned long flags;
edd16368
SC		 7187
7188 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 7189 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 7190 return;
7191 }
7192 h = pci_get_drvdata(pdev);
8a98db73
SC		 7193
7194 /* Get rid of any controller monitoring work items */
7195 spin_lock_irqsave(&h->lock, flags);
7196 h->remove_in_progress = 1;
7197 cancel_delayed_work(&h->monitor_ctlr_work);
7198 spin_unlock_irqrestore(&h->lock, flags);
7199
edd16368
SC		 7200 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
7201 hpsa_shutdown(pdev);
7202 iounmap(h->vaddr);
204892e9
SC		 7203 iounmap(h->transtable);
7204 iounmap(h->cfgtable);
55e14e76 7205 hpsa_free_device_info(h);
33a2ffce 7206 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 7207 pci_free_consistent(h->pdev,
7208 h->nr_cmds * sizeof(struct CommandList),
7209 h->cmd_pool, h->cmd_pool_dhandle);
7210 pci_free_consistent(h->pdev,
7211 h->nr_cmds * sizeof(struct ErrorInfo),
7212 h->errinfo_pool, h->errinfo_pool_dhandle);
072b0518 7213 hpsa_free_reply_queues(h);
edd16368 7214 kfree(h->cmd_pool_bits);
303932fd 7215 kfree(h->blockFetchTable);
e1f7de0c 7216 kfree(h->ioaccel1_blockFetchTable);
aca9012a 7217 kfree(h->ioaccel2_blockFetchTable);
339b2b14 7218 kfree(h->hba_inquiry_data);
f0bd0b68 7219 pci_disable_device(pdev);
edd16368 7220 pci_release_regions(pdev);
094963da 7221 free_percpu(h->lockup_detected);
edd16368
SC		 7222 kfree(h);
7223}
7224
7225static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
7226 __attribute__((unused)) pm_message_t state)
7227{
7228 return -ENOSYS;
7229}
7230
7231static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
7232{
7233 return -ENOSYS;
7234}
7235
7236static struct pci_driver hpsa_pci_driver = {
f79cfec6 7237 .name = HPSA,
edd16368 7238 .probe = hpsa_init_one,
6f039790 7239 .remove = hpsa_remove_one,
edd16368
SC		 7240 .id_table = hpsa_pci_device_id, /* id_table */
7241 .shutdown = hpsa_shutdown,
7242 .suspend = hpsa_suspend,
7243 .resume = hpsa_resume,
7244};
7245
303932fd
DB		 7246/* Fill in bucket_map[], given nsgs (the max number of
7247 * scatter gather elements supported) and bucket[],
7248 * which is an array of 8 integers. The bucket[] array
7249 * contains 8 different DMA transfer sizes (in 16
7250 * byte increments) which the controller uses to fetch
7251 * commands. This function fills in bucket_map[], which
7252 * maps a given number of scatter gather elements to one of
7253 * the 8 DMA transfer sizes. The point of it is to allow the
7254 * controller to only do as much DMA as needed to fetch the
7255 * command, with the DMA transfer size encoded in the lower
7256 * bits of the command address.
7257 */
7258static void calc_bucket_map(int bucket[], int num_buckets,
e1f7de0c 7259 int nsgs, int min_blocks, int *bucket_map)
303932fd
DB		 7260{
7261 int i, j, b, size;
7262
303932fd
DB		 7263 /* Note, bucket_map must have nsgs+1 entries. */
7264 for (i = 0; i <= nsgs; i++) {
7265 /* Compute size of a command with i SG entries */
e1f7de0c 7266 size = i + min_blocks;
303932fd
DB		 7267 b = num_buckets; /* Assume the biggest bucket */
7268 /* Find the bucket that is just big enough */
e1f7de0c 7269 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 7270 if (bucket[j] >= size) {
7271 b = j;
7272 break;
7273 }
7274 }
7275 /* for a command with i SG entries, use bucket b. */
7276 bucket_map[i] = b;
7277 }
7278}
7279
e1f7de0c 7280static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 7281{
6c311b57
SC		 7282 int i;
7283 unsigned long register_value;
e1f7de0c
MG		 7284 unsigned long transMethod = CFGTBL_Trans_Performant |
7285 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 7286 CFGTBL_Trans_enable_directed_msix |
7287 (trans_support & (CFGTBL_Trans_io_accel1 |
7288 CFGTBL_Trans_io_accel2));
e1f7de0c 7289 struct access_method access = SA5_performant_access;
def342bd
SC		 7290
7291 /* This is a bit complicated. There are 8 registers on
7292 * the controller which we write to to tell it 8 different
7293 * sizes of commands which there may be. It's a way of
7294 * reducing the DMA done to fetch each command. Encoded into
7295 * each command's tag are 3 bits which communicate to the controller
7296 * which of the eight sizes that command fits within. The size of
7297 * each command depends on how many scatter gather entries there are.
7298 * Each SG entry requires 16 bytes. The eight registers are programmed
7299 * with the number of 16-byte blocks a command of that size requires.
7300 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 7301 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 7302 * blocks. Note, this only extends to the SG entries contained
7303 * within the command block, and does not extend to chained blocks
7304 * of SG elements. bft[] contains the eight values we write to
7305 * the registers. They are not evenly distributed, but have more
7306 * sizes for small commands, and fewer sizes for larger commands.
7307 */
d66ae08b 7308 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 7309#define MIN_IOACCEL2_BFT_ENTRY 5
7310#define HPSA_IOACCEL2_HEADER_SZ 4
7311 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
7312 13, 14, 15, 16, 17, 18, 19,
7313 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
7314 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
7315 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
7316 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
7317 16 * MIN_IOACCEL2_BFT_ENTRY);
7318 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 7319 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 7320 /* 5 = 1 s/g entry or 4k
7321 * 6 = 2 s/g entry or 8k
7322 * 8 = 4 s/g entry or 16k
7323 * 10 = 6 s/g entry or 24k
7324 */
303932fd 7325
b3a52e79
SC		 7326 /* If the controller supports either ioaccel method then
7327 * we can also use the RAID stack submit path that does not
7328 * perform the superfluous readl() after each command submission.
7329 */
7330 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
7331 access = SA5_performant_access_no_read;
7332
303932fd 7333 /* Controller spec: zero out this buffer. */
072b0518
SC		 7334 for (i = 0; i < h->nreply_queues; i++)
7335 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 7336
d66ae08b
SC		 7337 bft[7] = SG_ENTRIES_IN_CMD + 4;
7338 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 7339 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 7340 for (i = 0; i < 8; i++)
7341 writel(bft[i], &h->transtable->BlockFetch[i]);
7342
7343 /* size of controller ring buffer */
7344 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 7345 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 7346 writel(0, &h->transtable->RepQCtrAddrLow32);
7347 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 7348
7349 for (i = 0; i < h->nreply_queues; i++) {
7350 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 7351 writel(h->reply_queue[i].busaddr,
254f796b
MG		 7352 &h->transtable->RepQAddr[i].lower);
7353 }
7354
b9af4937 7355 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 7356 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
7357 /*
7358 * enable outbound interrupt coalescing in accelerator mode;
7359 */
7360 if (trans_support & CFGTBL_Trans_io_accel1) {
7361 access = SA5_ioaccel_mode1_access;
7362 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7363 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 7364 } else {
7365 if (trans_support & CFGTBL_Trans_io_accel2) {
7366 access = SA5_ioaccel_mode2_access;
7367 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7368 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
7369 }
e1f7de0c 7370 }
303932fd 7371 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 7372 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 7373 register_value = readl(&(h->cfgtable->TransportActive));
7374 if (!(register_value & CFGTBL_Trans_Performant)) {
7375 dev_warn(&h->pdev->dev, "unable to get board into"
7376 " performant mode\n");
7377 return;
7378 }
960a30e7 7379 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 7380 h->access = access;
7381 h->transMethod = transMethod;
7382
b9af4937
SC		 7383 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
7384 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 7385 return;
7386
b9af4937
SC		 7387 if (trans_support & CFGTBL_Trans_io_accel1) {
7388 /* Set up I/O accelerator mode */
7389 for (i = 0; i < h->nreply_queues; i++) {
7390 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
7391 h->reply_queue[i].current_entry =
7392 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
7393 }
7394 bft[7] = h->ioaccel_maxsg + 8;
7395 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
7396 h->ioaccel1_blockFetchTable);
e1f7de0c 7397
b9af4937 7398 /* initialize all reply queue entries to unused */
072b0518
SC		 7399 for (i = 0; i < h->nreply_queues; i++)
7400 memset(h->reply_queue[i].head,
7401 (u8) IOACCEL_MODE1_REPLY_UNUSED,
7402 h->reply_queue_size);
e1f7de0c 7403
b9af4937
SC		 7404 /* set all the constant fields in the accelerator command
7405 * frames once at init time to save CPU cycles later.
7406 */
7407 for (i = 0; i < h->nr_cmds; i++) {
7408 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
7409
7410 cp->function = IOACCEL1_FUNCTION_SCSIIO;
7411 cp->err_info = (u32) (h->errinfo_pool_dhandle +
7412 (i * sizeof(struct ErrorInfo)));
7413 cp->err_info_len = sizeof(struct ErrorInfo);
7414 cp->sgl_offset = IOACCEL1_SGLOFFSET;
7415 cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT;
7416 cp->timeout_sec = 0;
7417 cp->ReplyQueue = 0;
7418 cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) |
7419 DIRECT_LOOKUP_BIT;
7420 cp->Tag.upper = 0;
7421 cp->host_addr.lower =
7422 (u32) (h->ioaccel_cmd_pool_dhandle +
7423 (i * sizeof(struct io_accel1_cmd)));
7424 cp->host_addr.upper = 0;
7425 }
7426 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7427 u64 cfg_offset, cfg_base_addr_index;
7428 u32 bft2_offset, cfg_base_addr;
7429 int rc;
7430
7431 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7432 &cfg_base_addr_index, &cfg_offset);
7433 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7434 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7435 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7436 4, h->ioaccel2_blockFetchTable);
7437 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7438 BUILD_BUG_ON(offsetof(struct CfgTable,
7439 io_accel_request_size_offset) != 0xb8);
7440 h->ioaccel2_bft2_regs =
7441 remap_pci_mem(pci_resource_start(h->pdev,
7442 cfg_base_addr_index) +
7443 cfg_offset + bft2_offset,
7444 ARRAY_SIZE(bft2) *
7445 sizeof(*h->ioaccel2_bft2_regs));
7446 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7447 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7448 }
b9af4937
SC		 7449 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7450 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 7451}
7452
7453static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
7454{
283b4a9b
SC		 7455 h->ioaccel_maxsg =
7456 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7457 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7458 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7459
e1f7de0c
MG		 7460 /* Command structures must be aligned on a 128-byte boundary
7461 * because the 7 lower bits of the address are used by the
7462 * hardware.
7463 */
e1f7de0c
MG		 7464 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7465 IOACCEL1_COMMANDLIST_ALIGNMENT);
7466 h->ioaccel_cmd_pool =
7467 pci_alloc_consistent(h->pdev,
7468 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7469 &(h->ioaccel_cmd_pool_dhandle));
7470
7471 h->ioaccel1_blockFetchTable =
283b4a9b 7472 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7473 sizeof(u32)), GFP_KERNEL);
7474
7475 if ((h->ioaccel_cmd_pool == NULL) ||
7476 (h->ioaccel1_blockFetchTable == NULL))
7477 goto clean_up;
7478
7479 memset(h->ioaccel_cmd_pool, 0,
7480 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
7481 return 0;
7482
7483clean_up:
7484 if (h->ioaccel_cmd_pool)
7485 pci_free_consistent(h->pdev,
7486 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7487 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
7488 kfree(h->ioaccel1_blockFetchTable);
7489 return 1;
6c311b57
SC		 7490}
7491
aca9012a
SC		 7492static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
7493{
7494 /* Allocate ioaccel2 mode command blocks and block fetch table */
7495
7496 h->ioaccel_maxsg =
7497 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7498 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
7499 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
7500
aca9012a
SC		 7501 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
7502 IOACCEL2_COMMANDLIST_ALIGNMENT);
7503 h->ioaccel2_cmd_pool =
7504 pci_alloc_consistent(h->pdev,
7505 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7506 &(h->ioaccel2_cmd_pool_dhandle));
7507
7508 h->ioaccel2_blockFetchTable =
7509 kmalloc(((h->ioaccel_maxsg + 1) *
7510 sizeof(u32)), GFP_KERNEL);
7511
7512 if ((h->ioaccel2_cmd_pool == NULL) ||
7513 (h->ioaccel2_blockFetchTable == NULL))
7514 goto clean_up;
7515
7516 memset(h->ioaccel2_cmd_pool, 0,
7517 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
7518 return 0;
7519
7520clean_up:
7521 if (h->ioaccel2_cmd_pool)
7522 pci_free_consistent(h->pdev,
7523 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7524 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
7525 kfree(h->ioaccel2_blockFetchTable);
7526 return 1;
7527}
7528
6f039790 7529static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 7530{
7531 u32 trans_support;
e1f7de0c
MG		 7532 unsigned long transMethod = CFGTBL_Trans_Performant |
7533 CFGTBL_Trans_use_short_tags;
254f796b 7534 int i;
6c311b57 7535
02ec19c8
SC		 7536 if (hpsa_simple_mode)
7537 return;
7538
67c99a72 7539 trans_support = readl(&(h->cfgtable->TransportSupport));
7540 if (!(trans_support & PERFORMANT_MODE))
7541 return;
7542
e1f7de0c
MG		 7543 /* Check for I/O accelerator mode support */
7544 if (trans_support & CFGTBL_Trans_io_accel1) {
7545 transMethod |= CFGTBL_Trans_io_accel1 |
7546 CFGTBL_Trans_enable_directed_msix;
7547 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
7548 goto clean_up;
aca9012a
SC		 7549 } else {
7550 if (trans_support & CFGTBL_Trans_io_accel2) {
7551 transMethod |= CFGTBL_Trans_io_accel2 |
7552 CFGTBL_Trans_enable_directed_msix;
7553 if (ioaccel2_alloc_cmds_and_bft(h))
7554 goto clean_up;
7555 }
e1f7de0c
MG		 7556 }
7557
eee0f03a 7558 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 7559 hpsa_get_max_perf_mode_cmds(h);
6c311b57 7560 /* Performant mode ring buffer and supporting data structures */
072b0518 7561 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 7562
254f796b 7563 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 7564 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
7565 h->reply_queue_size,
7566 &(h->reply_queue[i].busaddr));
7567 if (!h->reply_queue[i].head)
7568 goto clean_up;
254f796b
MG		 7569 h->reply_queue[i].size = h->max_commands;
7570 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
7571 h->reply_queue[i].current_entry = 0;
7572 }
7573
6c311b57 7574 /* Need a block fetch table for performant mode */
d66ae08b 7575 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 7576 sizeof(u32)), GFP_KERNEL);
072b0518 7577 if (!h->blockFetchTable)
6c311b57
SC		 7578 goto clean_up;
7579
e1f7de0c 7580 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 7581 return;
7582
7583clean_up:
072b0518 7584 hpsa_free_reply_queues(h);
303932fd
DB		 7585 kfree(h->blockFetchTable);
7586}
7587
23100dd9 7588static int is_accelerated_cmd(struct CommandList *c)
76438d08 7589{
23100dd9
SC		 7590 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
7591}
7592
7593static void hpsa_drain_accel_commands(struct ctlr_info *h)
7594{
7595 struct CommandList *c = NULL;
76438d08 7596 unsigned long flags;
23100dd9 7597 int accel_cmds_out;
76438d08
SC		 7598
7599 do { /* wait for all outstanding commands to drain out */
23100dd9 7600 accel_cmds_out = 0;
76438d08 7601 spin_lock_irqsave(&h->lock, flags);
23100dd9
SC		 7602 list_for_each_entry(c, &h->cmpQ, list)
7603 accel_cmds_out += is_accelerated_cmd(c);
7604 list_for_each_entry(c, &h->reqQ, list)
7605 accel_cmds_out += is_accelerated_cmd(c);
76438d08 7606 spin_unlock_irqrestore(&h->lock, flags);
23100dd9 7607 if (accel_cmds_out <= 0)
76438d08
SC		 7608 break;
7609 msleep(100);
7610 } while (1);
7611}
7612
edd16368
SC		 7613/*
7614 * This is it. Register the PCI driver information for the cards we control
7615 * the OS will call our registered routines when it finds one of our cards.
7616 */
7617static int __init hpsa_init(void)
7618{
31468401 7619 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 7620}
7621
7622static void __exit hpsa_cleanup(void)
7623{
7624 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 7625}
7626
e1f7de0c
MG		 7627static void __attribute__((unused)) verify_offsets(void)
7628{
dd0e19f3
ST		 7629#define VERIFY_OFFSET(member, offset) \
7630 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
7631
7632 VERIFY_OFFSET(structure_size, 0);
7633 VERIFY_OFFSET(volume_blk_size, 4);
7634 VERIFY_OFFSET(volume_blk_cnt, 8);
7635 VERIFY_OFFSET(phys_blk_shift, 16);
7636 VERIFY_OFFSET(parity_rotation_shift, 17);
7637 VERIFY_OFFSET(strip_size, 18);
7638 VERIFY_OFFSET(disk_starting_blk, 20);
7639 VERIFY_OFFSET(disk_blk_cnt, 28);
7640 VERIFY_OFFSET(data_disks_per_row, 36);
7641 VERIFY_OFFSET(metadata_disks_per_row, 38);
7642 VERIFY_OFFSET(row_cnt, 40);
7643 VERIFY_OFFSET(layout_map_count, 42);
7644 VERIFY_OFFSET(flags, 44);
7645 VERIFY_OFFSET(dekindex, 46);
7646 /* VERIFY_OFFSET(reserved, 48 */
7647 VERIFY_OFFSET(data, 64);
7648
7649#undef VERIFY_OFFSET
7650
b66cc250
MM		 7651#define VERIFY_OFFSET(member, offset) \
7652 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
7653
7654 VERIFY_OFFSET(IU_type, 0);
7655 VERIFY_OFFSET(direction, 1);
7656 VERIFY_OFFSET(reply_queue, 2);
7657 /* VERIFY_OFFSET(reserved1, 3); */
7658 VERIFY_OFFSET(scsi_nexus, 4);
7659 VERIFY_OFFSET(Tag, 8);
7660 VERIFY_OFFSET(cdb, 16);
7661 VERIFY_OFFSET(cciss_lun, 32);
7662 VERIFY_OFFSET(data_len, 40);
7663 VERIFY_OFFSET(cmd_priority_task_attr, 44);
7664 VERIFY_OFFSET(sg_count, 45);
7665 /* VERIFY_OFFSET(reserved3 */
7666 VERIFY_OFFSET(err_ptr, 48);
7667 VERIFY_OFFSET(err_len, 56);
7668 /* VERIFY_OFFSET(reserved4 */
7669 VERIFY_OFFSET(sg, 64);
7670
7671#undef VERIFY_OFFSET
7672
e1f7de0c
MG		 7673#define VERIFY_OFFSET(member, offset) \
7674 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
7675
7676 VERIFY_OFFSET(dev_handle, 0x00);
7677 VERIFY_OFFSET(reserved1, 0x02);
7678 VERIFY_OFFSET(function, 0x03);
7679 VERIFY_OFFSET(reserved2, 0x04);
7680 VERIFY_OFFSET(err_info, 0x0C);
7681 VERIFY_OFFSET(reserved3, 0x10);
7682 VERIFY_OFFSET(err_info_len, 0x12);
7683 VERIFY_OFFSET(reserved4, 0x13);
7684 VERIFY_OFFSET(sgl_offset, 0x14);
7685 VERIFY_OFFSET(reserved5, 0x15);
7686 VERIFY_OFFSET(transfer_len, 0x1C);
7687 VERIFY_OFFSET(reserved6, 0x20);
7688 VERIFY_OFFSET(io_flags, 0x24);
7689 VERIFY_OFFSET(reserved7, 0x26);
7690 VERIFY_OFFSET(LUN, 0x34);
7691 VERIFY_OFFSET(control, 0x3C);
7692 VERIFY_OFFSET(CDB, 0x40);
7693 VERIFY_OFFSET(reserved8, 0x50);
7694 VERIFY_OFFSET(host_context_flags, 0x60);
7695 VERIFY_OFFSET(timeout_sec, 0x62);
7696 VERIFY_OFFSET(ReplyQueue, 0x64);
7697 VERIFY_OFFSET(reserved9, 0x65);
7698 VERIFY_OFFSET(Tag, 0x68);
7699 VERIFY_OFFSET(host_addr, 0x70);
7700 VERIFY_OFFSET(CISS_LUN, 0x78);
7701 VERIFY_OFFSET(SG, 0x78 + 8);
7702#undef VERIFY_OFFSET
7703}
7704
edd16368
SC		 7705module_init(hpsa_init);
7706module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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