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hpsa: clean up aborts
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
a0c12413 50#include <linux/jiffies.h>
42a91641 51#include <linux/percpu-defs.h>
094963da 52#include <linux/percpu.h>
2b08b3e9 53#include <asm/unaligned.h>
283b4a9b 54#include <asm/div64.h>
edd16368
SC		 55#include "hpsa_cmd.h"
56#include "hpsa.h"
57
58/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
9a993302 59#define HPSA_DRIVER_VERSION "3.4.4-1"
edd16368 60#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 61#define HPSA "hpsa"
edd16368 62
007e7aa9
RE		 63/* How long to wait for CISS doorbell communication */
64#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
65#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
66#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
67#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 68#define MAX_IOCTL_CONFIG_WAIT 1000
69
70/*define how many times we will try a command because of bus resets */
71#define MAX_CMD_RETRIES 3
72
73/* Embedded module documentation macros - see modules.h */
74MODULE_AUTHOR("Hewlett-Packard Company");
75MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
76 HPSA_DRIVER_VERSION);
77MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
78MODULE_VERSION(HPSA_DRIVER_VERSION);
79MODULE_LICENSE("GPL");
80
81static int hpsa_allow_any;
82module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
83MODULE_PARM_DESC(hpsa_allow_any,
84 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 85static int hpsa_simple_mode;
86module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
87MODULE_PARM_DESC(hpsa_simple_mode,
88 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 89
90/* define the PCI info for the cards we can control */
91static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
131 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
8e616a5e
SC		 132 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
133 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
134 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
135 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
136 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 137 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 138 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 139 {0,}
140};
141
142MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
143
144/* board_id = Subsystem Device ID & Vendor ID
145 * product = Marketing Name for the board
146 * access = Address of the struct of function pointers
147 */
148static struct board_type products[] = {
edd16368
SC		 149 {0x3241103C, "Smart Array P212", &SA5_access},
150 {0x3243103C, "Smart Array P410", &SA5_access},
151 {0x3245103C, "Smart Array P410i", &SA5_access},
152 {0x3247103C, "Smart Array P411", &SA5_access},
153 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 154 {0x324A103C, "Smart Array P712m", &SA5_access},
155 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 156 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 157 {0x3350103C, "Smart Array P222", &SA5_access},
158 {0x3351103C, "Smart Array P420", &SA5_access},
159 {0x3352103C, "Smart Array P421", &SA5_access},
160 {0x3353103C, "Smart Array P822", &SA5_access},
161 {0x3354103C, "Smart Array P420i", &SA5_access},
162 {0x3355103C, "Smart Array P220i", &SA5_access},
163 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 164 {0x1921103C, "Smart Array P830i", &SA5_access},
165 {0x1922103C, "Smart Array P430", &SA5_access},
166 {0x1923103C, "Smart Array P431", &SA5_access},
167 {0x1924103C, "Smart Array P830", &SA5_access},
168 {0x1926103C, "Smart Array P731m", &SA5_access},
169 {0x1928103C, "Smart Array P230i", &SA5_access},
170 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 171 {0x21BD103C, "Smart Array P244br", &SA5_access},
172 {0x21BE103C, "Smart Array P741m", &SA5_access},
173 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
174 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 175 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 176 {0x21C2103C, "Smart Array P440", &SA5_access},
177 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 178 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 179 {0x21C5103C, "Smart Array P841", &SA5_access},
180 {0x21C6103C, "Smart HBA H244br", &SA5_access},
181 {0x21C7103C, "Smart HBA H240", &SA5_access},
182 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 183 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 184 {0x21CA103C, "Smart Array P246br", &SA5_access},
185 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 186 {0x21CC103C, "Smart Array", &SA5_access},
187 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 188 {0x21CE103C, "Smart HBA", &SA5_access},
8e616a5e
SC		 189 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
190 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
191 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
192 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
193 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 194 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
195};
196
197static int number_of_controllers;
198
10f66018
SC		 199static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
200static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 201static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 202
203#ifdef CONFIG_COMPAT
42a91641
DB		 204static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
205 void __user *arg);
edd16368
SC		 206#endif
207
208static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 209static struct CommandList *cmd_alloc(struct ctlr_info *h);
a2dac136 210static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 211 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 212 int cmd_type);
2c143342 213static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 214#define VPD_PAGE (1 << 8)
edd16368 215
f281233d 216static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 217static void hpsa_scan_start(struct Scsi_Host *);
218static int hpsa_scan_finished(struct Scsi_Host *sh,
219 unsigned long elapsed_time);
7c0a0229 220static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 221
222static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 223static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 224static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 225static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 226static void hpsa_slave_destroy(struct scsi_device *sdev);
227
edd16368 228static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 229static int check_for_unit_attention(struct ctlr_info *h,
230 struct CommandList *c);
231static void check_ioctl_unit_attention(struct ctlr_info *h,
232 struct CommandList *c);
303932fd
DB		 233/* performant mode helper functions */
234static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 235 int nsgs, int min_blocks, u32 *bucket_map);
6f039790 236static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 237static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 238static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
239 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
240 u64 *cfg_offset);
241static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
242 unsigned long *memory_bar);
243static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
244static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
245 int wait_for_ready);
75167d2c 246static inline void finish_cmd(struct CommandList *c);
c706a795 247static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 248#define BOARD_NOT_READY 0
249#define BOARD_READY 1
23100dd9 250static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 251static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 252static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
253 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 254 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 255static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 256static u32 lockup_detected(struct ctlr_info *h);
257static int detect_controller_lockup(struct ctlr_info *h);
edd16368 258
edd16368
SC		 259static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
260{
261 unsigned long *priv = shost_priv(sdev->host);
262 return (struct ctlr_info *) *priv;
263}
264
a23513e8
SC		 265static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
266{
267 unsigned long *priv = shost_priv(sh);
268 return (struct ctlr_info *) *priv;
269}
270
edd16368
SC		 271static int check_for_unit_attention(struct ctlr_info *h,
272 struct CommandList *c)
273{
274 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
275 return 0;
276
277 switch (c->err_info->SenseInfo[12]) {
278 case STATE_CHANGED:
f79cfec6 279 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 280 "detected, command retried\n", h->ctlr);
281 break;
282 case LUN_FAILED:
7f73695a
SC		 283 dev_warn(&h->pdev->dev,
284 HPSA "%d: LUN failure detected\n", h->ctlr);
edd16368
SC		 285 break;
286 case REPORT_LUNS_CHANGED:
7f73695a
SC		 287 dev_warn(&h->pdev->dev,
288 HPSA "%d: report LUN data changed\n", h->ctlr);
edd16368 289 /*
4f4eb9f1
ST		 290 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
291 * target (array) devices.
edd16368
SC		 292 */
293 break;
294 case POWER_OR_RESET:
f79cfec6 295 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 296 "or device reset detected\n", h->ctlr);
297 break;
298 case UNIT_ATTENTION_CLEARED:
f79cfec6 299 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 300 "cleared by another initiator\n", h->ctlr);
301 break;
302 default:
f79cfec6 303 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 304 "unit attention detected\n", h->ctlr);
305 break;
306 }
307 return 1;
308}
309
852af20a
MB		 310static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
311{
312 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
313 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
314 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
315 return 0;
316 dev_warn(&h->pdev->dev, HPSA "device busy");
317 return 1;
318}
319
da0697bd
ST		 320static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
321 struct device_attribute *attr,
322 const char *buf, size_t count)
323{
324 int status, len;
325 struct ctlr_info *h;
326 struct Scsi_Host *shost = class_to_shost(dev);
327 char tmpbuf[10];
328
329 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
330 return -EACCES;
331 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
332 strncpy(tmpbuf, buf, len);
333 tmpbuf[len] = '\0';
334 if (sscanf(tmpbuf, "%d", &status) != 1)
335 return -EINVAL;
336 h = shost_to_hba(shost);
337 h->acciopath_status = !!status;
338 dev_warn(&h->pdev->dev,
339 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
340 h->acciopath_status ? "enabled" : "disabled");
341 return count;
342}
343
2ba8bfc8
SC		 344static ssize_t host_store_raid_offload_debug(struct device *dev,
345 struct device_attribute *attr,
346 const char *buf, size_t count)
347{
348 int debug_level, len;
349 struct ctlr_info *h;
350 struct Scsi_Host *shost = class_to_shost(dev);
351 char tmpbuf[10];
352
353 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
354 return -EACCES;
355 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
356 strncpy(tmpbuf, buf, len);
357 tmpbuf[len] = '\0';
358 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
359 return -EINVAL;
360 if (debug_level < 0)
361 debug_level = 0;
362 h = shost_to_hba(shost);
363 h->raid_offload_debug = debug_level;
364 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
365 h->raid_offload_debug);
366 return count;
367}
368
edd16368
SC		 369static ssize_t host_store_rescan(struct device *dev,
370 struct device_attribute *attr,
371 const char *buf, size_t count)
372{
373 struct ctlr_info *h;
374 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 375 h = shost_to_hba(shost);
31468401 376 hpsa_scan_start(h->scsi_host);
edd16368
SC		 377 return count;
378}
379
d28ce020
SC		 380static ssize_t host_show_firmware_revision(struct device *dev,
381 struct device_attribute *attr, char *buf)
382{
383 struct ctlr_info *h;
384 struct Scsi_Host *shost = class_to_shost(dev);
385 unsigned char *fwrev;
386
387 h = shost_to_hba(shost);
388 if (!h->hba_inquiry_data)
389 return 0;
390 fwrev = &h->hba_inquiry_data[32];
391 return snprintf(buf, 20, "%c%c%c%c\n",
392 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
393}
394
94a13649
SC		 395static ssize_t host_show_commands_outstanding(struct device *dev,
396 struct device_attribute *attr, char *buf)
397{
398 struct Scsi_Host *shost = class_to_shost(dev);
399 struct ctlr_info *h = shost_to_hba(shost);
400
0cbf768e
SC		 401 return snprintf(buf, 20, "%d\n",
402 atomic_read(&h->commands_outstanding));
94a13649
SC		 403}
404
745a7a25
SC		 405static ssize_t host_show_transport_mode(struct device *dev,
406 struct device_attribute *attr, char *buf)
407{
408 struct ctlr_info *h;
409 struct Scsi_Host *shost = class_to_shost(dev);
410
411 h = shost_to_hba(shost);
412 return snprintf(buf, 20, "%s\n",
960a30e7 413 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 414 "performant" : "simple");
415}
416
da0697bd
ST		 417static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
418 struct device_attribute *attr, char *buf)
419{
420 struct ctlr_info *h;
421 struct Scsi_Host *shost = class_to_shost(dev);
422
423 h = shost_to_hba(shost);
424 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
425 (h->acciopath_status == 1) ? "enabled" : "disabled");
426}
427
46380786 428/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 429static u32 unresettable_controller[] = {
430 0x324a103C, /* Smart Array P712m */
9b5c48c2 431 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 432 0x3223103C, /* Smart Array P800 */
433 0x3234103C, /* Smart Array P400 */
434 0x3235103C, /* Smart Array P400i */
435 0x3211103C, /* Smart Array E200i */
436 0x3212103C, /* Smart Array E200 */
437 0x3213103C, /* Smart Array E200i */
438 0x3214103C, /* Smart Array E200i */
439 0x3215103C, /* Smart Array E200i */
440 0x3237103C, /* Smart Array E500 */
441 0x323D103C, /* Smart Array P700m */
7af0abbc 442 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 443 0x409C0E11, /* Smart Array 6400 */
444 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 445 0x40700E11, /* Smart Array 5300 */
446 0x40820E11, /* Smart Array 532 */
447 0x40830E11, /* Smart Array 5312 */
448 0x409A0E11, /* Smart Array 641 */
449 0x409B0E11, /* Smart Array 642 */
450 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 451};
452
46380786
SC		 453/* List of controllers which cannot even be soft reset */
454static u32 soft_unresettable_controller[] = {
7af0abbc 455 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 456 0x40700E11, /* Smart Array 5300 */
457 0x40820E11, /* Smart Array 532 */
458 0x40830E11, /* Smart Array 5312 */
459 0x409A0E11, /* Smart Array 641 */
460 0x409B0E11, /* Smart Array 642 */
461 0x40910E11, /* Smart Array 6i */
46380786
SC		 462 /* Exclude 640x boards. These are two pci devices in one slot
463 * which share a battery backed cache module. One controls the
464 * cache, the other accesses the cache through the one that controls
465 * it. If we reset the one controlling the cache, the other will
466 * likely not be happy. Just forbid resetting this conjoined mess.
467 * The 640x isn't really supported by hpsa anyway.
468 */
469 0x409C0E11, /* Smart Array 6400 */
470 0x409D0E11, /* Smart Array 6400 EM */
471};
472
9b5c48c2
SC		 473static u32 needs_abort_tags_swizzled[] = {
474 0x323D103C, /* Smart Array P700m */
475 0x324a103C, /* Smart Array P712m */
476 0x324b103C, /* SmartArray P711m */
477};
478
479static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 480{
481 int i;
482
9b5c48c2
SC		 483 for (i = 0; i < nelems; i++)
484 if (a[i] == board_id)
485 return 1;
486 return 0;
46380786
SC		 487}
488
9b5c48c2 489static int ctlr_is_hard_resettable(u32 board_id)
46380786 490{
9b5c48c2
SC		 491 return !board_id_in_array(unresettable_controller,
492 ARRAY_SIZE(unresettable_controller), board_id);
493}
46380786 494
9b5c48c2
SC		 495static int ctlr_is_soft_resettable(u32 board_id)
496{
497 return !board_id_in_array(soft_unresettable_controller,
498 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 499}
500
46380786
SC		 501static int ctlr_is_resettable(u32 board_id)
502{
503 return ctlr_is_hard_resettable(board_id) ||
504 ctlr_is_soft_resettable(board_id);
505}
506
9b5c48c2
SC		 507static int ctlr_needs_abort_tags_swizzled(u32 board_id)
508{
509 return board_id_in_array(needs_abort_tags_swizzled,
510 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
511}
512
941b1cda
SC		 513static ssize_t host_show_resettable(struct device *dev,
514 struct device_attribute *attr, char *buf)
515{
516 struct ctlr_info *h;
517 struct Scsi_Host *shost = class_to_shost(dev);
518
519 h = shost_to_hba(shost);
46380786 520 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 521}
522
edd16368
SC		 523static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
524{
525 return (scsi3addr[3] & 0xC0) == 0x40;
526}
527
f2ef0ce7
RE		 528static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
529 "1(+0)ADM", "UNKNOWN"
edd16368 530};
6b80b18f
ST		 531#define HPSA_RAID_0 0
532#define HPSA_RAID_4 1
533#define HPSA_RAID_1 2 /* also used for RAID 10 */
534#define HPSA_RAID_5 3 /* also used for RAID 50 */
535#define HPSA_RAID_51 4
536#define HPSA_RAID_6 5 /* also used for RAID 60 */
537#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 538#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
539
540static ssize_t raid_level_show(struct device *dev,
541 struct device_attribute *attr, char *buf)
542{
543 ssize_t l = 0;
82a72c0a 544 unsigned char rlevel;
edd16368
SC		 545 struct ctlr_info *h;
546 struct scsi_device *sdev;
547 struct hpsa_scsi_dev_t *hdev;
548 unsigned long flags;
549
550 sdev = to_scsi_device(dev);
551 h = sdev_to_hba(sdev);
552 spin_lock_irqsave(&h->lock, flags);
553 hdev = sdev->hostdata;
554 if (!hdev) {
555 spin_unlock_irqrestore(&h->lock, flags);
556 return -ENODEV;
557 }
558
559 /* Is this even a logical drive? */
560 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
561 spin_unlock_irqrestore(&h->lock, flags);
562 l = snprintf(buf, PAGE_SIZE, "N/A\n");
563 return l;
564 }
565
566 rlevel = hdev->raid_level;
567 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 568 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 569 rlevel = RAID_UNKNOWN;
570 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
571 return l;
572}
573
574static ssize_t lunid_show(struct device *dev,
575 struct device_attribute *attr, char *buf)
576{
577 struct ctlr_info *h;
578 struct scsi_device *sdev;
579 struct hpsa_scsi_dev_t *hdev;
580 unsigned long flags;
581 unsigned char lunid[8];
582
583 sdev = to_scsi_device(dev);
584 h = sdev_to_hba(sdev);
585 spin_lock_irqsave(&h->lock, flags);
586 hdev = sdev->hostdata;
587 if (!hdev) {
588 spin_unlock_irqrestore(&h->lock, flags);
589 return -ENODEV;
590 }
591 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
592 spin_unlock_irqrestore(&h->lock, flags);
593 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
594 lunid[0], lunid[1], lunid[2], lunid[3],
595 lunid[4], lunid[5], lunid[6], lunid[7]);
596}
597
598static ssize_t unique_id_show(struct device *dev,
599 struct device_attribute *attr, char *buf)
600{
601 struct ctlr_info *h;
602 struct scsi_device *sdev;
603 struct hpsa_scsi_dev_t *hdev;
604 unsigned long flags;
605 unsigned char sn[16];
606
607 sdev = to_scsi_device(dev);
608 h = sdev_to_hba(sdev);
609 spin_lock_irqsave(&h->lock, flags);
610 hdev = sdev->hostdata;
611 if (!hdev) {
612 spin_unlock_irqrestore(&h->lock, flags);
613 return -ENODEV;
614 }
615 memcpy(sn, hdev->device_id, sizeof(sn));
616 spin_unlock_irqrestore(&h->lock, flags);
617 return snprintf(buf, 16 * 2 + 2,
618 "%02X%02X%02X%02X%02X%02X%02X%02X"
619 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
620 sn[0], sn[1], sn[2], sn[3],
621 sn[4], sn[5], sn[6], sn[7],
622 sn[8], sn[9], sn[10], sn[11],
623 sn[12], sn[13], sn[14], sn[15]);
624}
625
c1988684
ST		 626static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
627 struct device_attribute *attr, char *buf)
628{
629 struct ctlr_info *h;
630 struct scsi_device *sdev;
631 struct hpsa_scsi_dev_t *hdev;
632 unsigned long flags;
633 int offload_enabled;
634
635 sdev = to_scsi_device(dev);
636 h = sdev_to_hba(sdev);
637 spin_lock_irqsave(&h->lock, flags);
638 hdev = sdev->hostdata;
639 if (!hdev) {
640 spin_unlock_irqrestore(&h->lock, flags);
641 return -ENODEV;
642 }
643 offload_enabled = hdev->offload_enabled;
644 spin_unlock_irqrestore(&h->lock, flags);
645 return snprintf(buf, 20, "%d\n", offload_enabled);
646}
647
3f5eac3a
SC		 648static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
649static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
650static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
651static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 652static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
653 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 654static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
655 host_show_hp_ssd_smart_path_status,
656 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 657static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
658 host_store_raid_offload_debug);
3f5eac3a
SC		 659static DEVICE_ATTR(firmware_revision, S_IRUGO,
660 host_show_firmware_revision, NULL);
661static DEVICE_ATTR(commands_outstanding, S_IRUGO,
662 host_show_commands_outstanding, NULL);
663static DEVICE_ATTR(transport_mode, S_IRUGO,
664 host_show_transport_mode, NULL);
941b1cda
SC		 665static DEVICE_ATTR(resettable, S_IRUGO,
666 host_show_resettable, NULL);
3f5eac3a
SC		 667
668static struct device_attribute *hpsa_sdev_attrs[] = {
669 &dev_attr_raid_level,
670 &dev_attr_lunid,
671 &dev_attr_unique_id,
c1988684 672 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 673 NULL,
674};
675
676static struct device_attribute *hpsa_shost_attrs[] = {
677 &dev_attr_rescan,
678 &dev_attr_firmware_revision,
679 &dev_attr_commands_outstanding,
680 &dev_attr_transport_mode,
941b1cda 681 &dev_attr_resettable,
da0697bd 682 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 683 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 684 NULL,
685};
686
41ce4c35
SC		 687#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
688 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
689
3f5eac3a
SC		 690static struct scsi_host_template hpsa_driver_template = {
691 .module = THIS_MODULE,
f79cfec6
SC		 692 .name = HPSA,
693 .proc_name = HPSA,
3f5eac3a
SC		 694 .queuecommand = hpsa_scsi_queue_command,
695 .scan_start = hpsa_scan_start,
696 .scan_finished = hpsa_scan_finished,
7c0a0229 697 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 698 .this_id = -1,
699 .use_clustering = ENABLE_CLUSTERING,
75167d2c 700 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 701 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
702 .ioctl = hpsa_ioctl,
703 .slave_alloc = hpsa_slave_alloc,
41ce4c35 704 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 705 .slave_destroy = hpsa_slave_destroy,
706#ifdef CONFIG_COMPAT
707 .compat_ioctl = hpsa_compat_ioctl,
708#endif
709 .sdev_attrs = hpsa_sdev_attrs,
710 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 711 .max_sectors = 8192,
54b2b50c 712 .no_write_same = 1,
3f5eac3a
SC		 713};
714
254f796b 715static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 716{
717 u32 a;
072b0518 718 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 719
e1f7de0c
MG		 720 if (h->transMethod & CFGTBL_Trans_io_accel1)
721 return h->access.command_completed(h, q);
722
3f5eac3a 723 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 724 return h->access.command_completed(h, q);
3f5eac3a 725
254f796b
MG		 726 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
727 a = rq->head[rq->current_entry];
728 rq->current_entry++;
0cbf768e 729 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 730 } else {
731 a = FIFO_EMPTY;
732 }
733 /* Check for wraparound */
254f796b
MG		 734 if (rq->current_entry == h->max_commands) {
735 rq->current_entry = 0;
736 rq->wraparound ^= 1;
3f5eac3a
SC		 737 }
738 return a;
739}
740
c349775e
ST		 741/*
742 * There are some special bits in the bus address of the
743 * command that we have to set for the controller to know
744 * how to process the command:
745 *
746 * Normal performant mode:
747 * bit 0: 1 means performant mode, 0 means simple mode.
748 * bits 1-3 = block fetch table entry
749 * bits 4-6 = command type (== 0)
750 *
751 * ioaccel1 mode:
752 * bit 0 = "performant mode" bit.
753 * bits 1-3 = block fetch table entry
754 * bits 4-6 = command type (== 110)
755 * (command type is needed because ioaccel1 mode
756 * commands are submitted through the same register as normal
757 * mode commands, so this is how the controller knows whether
758 * the command is normal mode or ioaccel1 mode.)
759 *
760 * ioaccel2 mode:
761 * bit 0 = "performant mode" bit.
762 * bits 1-4 = block fetch table entry (note extra bit)
763 * bits 4-6 = not needed, because ioaccel2 mode has
764 * a separate special register for submitting commands.
765 */
766
25163bd5
WS		 767/*
768 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 769 * set bit 0 for pull model, bits 3-1 for block fetch
770 * register number
771 */
25163bd5
WS		 772#define DEFAULT_REPLY_QUEUE (-1)
773static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
774 int reply_queue)
3f5eac3a 775{
254f796b 776 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 777 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 778 if (unlikely(!h->msix_vector))
779 return;
780 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 781 c->Header.ReplyQueue =
804a5cb5 782 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 783 else
784 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 785 }
3f5eac3a
SC		 786}
787
c349775e 788static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 789 struct CommandList *c,
790 int reply_queue)
c349775e
ST		 791{
792 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
793
25163bd5
WS		 794 /*
795 * Tell the controller to post the reply to the queue for this
c349775e
ST		 796 * processor. This seems to give the best I/O throughput.
797 */
25163bd5
WS		 798 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
799 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
800 else
801 cp->ReplyQueue = reply_queue % h->nreply_queues;
802 /*
803 * Set the bits in the address sent down to include:
c349775e
ST		 804 * - performant mode bit (bit 0)
805 * - pull count (bits 1-3)
806 * - command type (bits 4-6)
807 */
808 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
809 IOACCEL1_BUSADDR_CMDTYPE;
810}
811
812static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 813 struct CommandList *c,
814 int reply_queue)
c349775e
ST		 815{
816 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
817
25163bd5
WS		 818 /*
819 * Tell the controller to post the reply to the queue for this
c349775e
ST		 820 * processor. This seems to give the best I/O throughput.
821 */
25163bd5
WS		 822 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
823 cp->reply_queue = smp_processor_id() % h->nreply_queues;
824 else
825 cp->reply_queue = reply_queue % h->nreply_queues;
826 /*
827 * Set the bits in the address sent down to include:
c349775e
ST		 828 * - performant mode bit not used in ioaccel mode 2
829 * - pull count (bits 0-3)
830 * - command type isn't needed for ioaccel2
831 */
832 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
833}
834
e85c5974
SC		 835static int is_firmware_flash_cmd(u8 *cdb)
836{
837 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
838}
839
840/*
841 * During firmware flash, the heartbeat register may not update as frequently
842 * as it should. So we dial down lockup detection during firmware flash. and
843 * dial it back up when firmware flash completes.
844 */
845#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
846#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
847static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
848 struct CommandList *c)
849{
850 if (!is_firmware_flash_cmd(c->Request.CDB))
851 return;
852 atomic_inc(&h->firmware_flash_in_progress);
853 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
854}
855
856static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
857 struct CommandList *c)
858{
859 if (is_firmware_flash_cmd(c->Request.CDB) &&
860 atomic_dec_and_test(&h->firmware_flash_in_progress))
861 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
862}
863
25163bd5
WS		 864static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
865 struct CommandList *c, int reply_queue)
3f5eac3a 866{
c05e8866
SC		 867 dial_down_lockup_detection_during_fw_flash(h, c);
868 atomic_inc(&h->commands_outstanding);
c349775e
ST		 869 switch (c->cmd_type) {
870 case CMD_IOACCEL1:
25163bd5 871 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 872 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 873 break;
874 case CMD_IOACCEL2:
25163bd5 875 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 876 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e
ST		 877 break;
878 default:
25163bd5 879 set_performant_mode(h, c, reply_queue);
c05e8866 880 h->access.submit_command(h, c);
c349775e 881 }
3f5eac3a
SC		 882}
883
25163bd5
WS		 884static void enqueue_cmd_and_start_io(struct ctlr_info *h,
885 struct CommandList *c)
886{
887 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
888}
889
3f5eac3a
SC		 890static inline int is_hba_lunid(unsigned char scsi3addr[])
891{
892 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
893}
894
895static inline int is_scsi_rev_5(struct ctlr_info *h)
896{
897 if (!h->hba_inquiry_data)
898 return 0;
899 if ((h->hba_inquiry_data[2] & 0x07) == 5)
900 return 1;
901 return 0;
902}
903
edd16368
SC		 904static int hpsa_find_target_lun(struct ctlr_info *h,
905 unsigned char scsi3addr[], int bus, int *target, int *lun)
906{
907 /* finds an unused bus, target, lun for a new physical device
908 * assumes h->devlock is held
909 */
910 int i, found = 0;
cfe5badc 911 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 912
263d9401 913 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 914
915 for (i = 0; i < h->ndevices; i++) {
916 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 917 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 918 }
919
263d9401
AM		 920 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
921 if (i < HPSA_MAX_DEVICES) {
922 /* *bus = 1; */
923 *target = i;
924 *lun = 0;
925 found = 1;
edd16368
SC		 926 }
927 return !found;
928}
929
0d96ef5f
WS		 930static inline void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
931 struct hpsa_scsi_dev_t *dev, char *description)
932{
933 dev_printk(level, &h->pdev->dev,
934 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
935 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
936 description,
937 scsi_device_type(dev->devtype),
938 dev->vendor,
939 dev->model,
940 dev->raid_level > RAID_UNKNOWN ?
941 "RAID-?" : raid_label[dev->raid_level],
942 dev->offload_config ? '+' : '-',
943 dev->offload_enabled ? '+' : '-',
944 dev->expose_state);
945}
946
edd16368
SC		 947/* Add an entry into h->dev[] array. */
948static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
949 struct hpsa_scsi_dev_t *device,
950 struct hpsa_scsi_dev_t *added[], int *nadded)
951{
952 /* assumes h->devlock is held */
953 int n = h->ndevices;
954 int i;
955 unsigned char addr1[8], addr2[8];
956 struct hpsa_scsi_dev_t *sd;
957
cfe5badc 958 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 959 dev_err(&h->pdev->dev, "too many devices, some will be "
960 "inaccessible.\n");
961 return -1;
962 }
963
964 /* physical devices do not have lun or target assigned until now. */
965 if (device->lun != -1)
966 /* Logical device, lun is already assigned. */
967 goto lun_assigned;
968
969 /* If this device a non-zero lun of a multi-lun device
970 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 971 * unit no, zero otherwise.
edd16368
SC		 972 */
973 if (device->scsi3addr[4] == 0) {
974 /* This is not a non-zero lun of a multi-lun device */
975 if (hpsa_find_target_lun(h, device->scsi3addr,
976 device->bus, &device->target, &device->lun) != 0)
977 return -1;
978 goto lun_assigned;
979 }
980
981 /* This is a non-zero lun of a multi-lun device.
982 * Search through our list and find the device which
983 * has the same 8 byte LUN address, excepting byte 4.
984 * Assign the same bus and target for this new LUN.
985 * Use the logical unit number from the firmware.
986 */
987 memcpy(addr1, device->scsi3addr, 8);
988 addr1[4] = 0;
989 for (i = 0; i < n; i++) {
990 sd = h->dev[i];
991 memcpy(addr2, sd->scsi3addr, 8);
992 addr2[4] = 0;
993 /* differ only in byte 4? */
994 if (memcmp(addr1, addr2, 8) == 0) {
995 device->bus = sd->bus;
996 device->target = sd->target;
997 device->lun = device->scsi3addr[4];
998 break;
999 }
1000 }
1001 if (device->lun == -1) {
1002 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1003 " suspect firmware bug or unsupported hardware "
1004 "configuration.\n");
1005 return -1;
1006 }
1007
1008lun_assigned:
1009
1010 h->dev[n] = device;
1011 h->ndevices++;
41ce4c35
SC		 1012 device->offload_to_be_enabled = device->offload_enabled;
1013 device->offload_enabled = 0;
edd16368
SC		 1014 added[*nadded] = device;
1015 (*nadded)++;
0d96ef5f
WS		 1016 hpsa_show_dev_msg(KERN_INFO, h, device,
1017 device->expose_state & HPSA_SCSI_ADD ? "added" : "masked");
edd16368
SC		 1018 return 0;
1019}
1020
bd9244f7
ST		 1021/* Update an entry in h->dev[] array. */
1022static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
1023 int entry, struct hpsa_scsi_dev_t *new_entry)
1024{
1025 /* assumes h->devlock is held */
1026 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1027
1028 /* Raid level changed. */
1029 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1030
03383736
DB		 1031 /* Raid offload parameters changed. Careful about the ordering. */
1032 if (new_entry->offload_config && new_entry->offload_enabled) {
1033 /*
1034 * if drive is newly offload_enabled, we want to copy the
1035 * raid map data first. If previously offload_enabled and
1036 * offload_config were set, raid map data had better be
1037 * the same as it was before. if raid map data is changed
1038 * then it had better be the case that
1039 * h->dev[entry]->offload_enabled is currently 0.
1040 */
1041 h->dev[entry]->raid_map = new_entry->raid_map;
1042 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1043 }
250fb125 1044 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1045 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1046 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1047
41ce4c35
SC		 1048 /*
1049 * We can turn off ioaccel offload now, but need to delay turning
1050 * it on until we can update h->dev[entry]->phys_disk[], but we
1051 * can't do that until all the devices are updated.
1052 */
1053 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1054 if (!new_entry->offload_enabled)
1055 h->dev[entry]->offload_enabled = 0;
1056
0d96ef5f 1057 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
bd9244f7
ST		 1058}
1059
2a8ccf31
SC		 1060/* Replace an entry from h->dev[] array. */
1061static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
1062 int entry, struct hpsa_scsi_dev_t *new_entry,
1063 struct hpsa_scsi_dev_t *added[], int *nadded,
1064 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1065{
1066 /* assumes h->devlock is held */
cfe5badc 1067 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1068 removed[*nremoved] = h->dev[entry];
1069 (*nremoved)++;
01350d05
SC		 1070
1071 /*
1072 * New physical devices won't have target/lun assigned yet
1073 * so we need to preserve the values in the slot we are replacing.
1074 */
1075 if (new_entry->target == -1) {
1076 new_entry->target = h->dev[entry]->target;
1077 new_entry->lun = h->dev[entry]->lun;
1078 }
1079
41ce4c35
SC		 1080 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1081 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1082 h->dev[entry] = new_entry;
1083 added[*nadded] = new_entry;
1084 (*nadded)++;
0d96ef5f 1085 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
2a8ccf31
SC		 1086}
1087
edd16368
SC		 1088/* Remove an entry from h->dev[] array. */
1089static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1090 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1091{
1092 /* assumes h->devlock is held */
1093 int i;
1094 struct hpsa_scsi_dev_t *sd;
1095
cfe5badc 1096 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1097
1098 sd = h->dev[entry];
1099 removed[*nremoved] = h->dev[entry];
1100 (*nremoved)++;
1101
1102 for (i = entry; i < h->ndevices-1; i++)
1103 h->dev[i] = h->dev[i+1];
1104 h->ndevices--;
0d96ef5f 1105 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1106}
1107
1108#define SCSI3ADDR_EQ(a, b) ( \
1109 (a)[7] == (b)[7] && \
1110 (a)[6] == (b)[6] && \
1111 (a)[5] == (b)[5] && \
1112 (a)[4] == (b)[4] && \
1113 (a)[3] == (b)[3] && \
1114 (a)[2] == (b)[2] && \
1115 (a)[1] == (b)[1] && \
1116 (a)[0] == (b)[0])
1117
1118static void fixup_botched_add(struct ctlr_info *h,
1119 struct hpsa_scsi_dev_t *added)
1120{
1121 /* called when scsi_add_device fails in order to re-adjust
1122 * h->dev[] to match the mid layer's view.
1123 */
1124 unsigned long flags;
1125 int i, j;
1126
1127 spin_lock_irqsave(&h->lock, flags);
1128 for (i = 0; i < h->ndevices; i++) {
1129 if (h->dev[i] == added) {
1130 for (j = i; j < h->ndevices-1; j++)
1131 h->dev[j] = h->dev[j+1];
1132 h->ndevices--;
1133 break;
1134 }
1135 }
1136 spin_unlock_irqrestore(&h->lock, flags);
1137 kfree(added);
1138}
1139
1140static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1141 struct hpsa_scsi_dev_t *dev2)
1142{
edd16368
SC		 1143 /* we compare everything except lun and target as these
1144 * are not yet assigned. Compare parts likely
1145 * to differ first
1146 */
1147 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1148 sizeof(dev1->scsi3addr)) != 0)
1149 return 0;
1150 if (memcmp(dev1->device_id, dev2->device_id,
1151 sizeof(dev1->device_id)) != 0)
1152 return 0;
1153 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1154 return 0;
1155 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1156 return 0;
edd16368
SC		 1157 if (dev1->devtype != dev2->devtype)
1158 return 0;
edd16368
SC		 1159 if (dev1->bus != dev2->bus)
1160 return 0;
1161 return 1;
1162}
1163
bd9244f7
ST		 1164static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1165 struct hpsa_scsi_dev_t *dev2)
1166{
1167 /* Device attributes that can change, but don't mean
1168 * that the device is a different device, nor that the OS
1169 * needs to be told anything about the change.
1170 */
1171 if (dev1->raid_level != dev2->raid_level)
1172 return 1;
250fb125
SC		 1173 if (dev1->offload_config != dev2->offload_config)
1174 return 1;
1175 if (dev1->offload_enabled != dev2->offload_enabled)
1176 return 1;
03383736
DB		 1177 if (dev1->queue_depth != dev2->queue_depth)
1178 return 1;
bd9244f7
ST		 1179 return 0;
1180}
1181
edd16368
SC		 1182/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1183 * and return needle location in *index. If scsi3addr matches, but not
1184 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1185 * location in *index.
1186 * In the case of a minor device attribute change, such as RAID level, just
1187 * return DEVICE_UPDATED, along with the updated device's location in index.
1188 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1189 */
1190static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1191 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1192 int *index)
1193{
1194 int i;
1195#define DEVICE_NOT_FOUND 0
1196#define DEVICE_CHANGED 1
1197#define DEVICE_SAME 2
bd9244f7 1198#define DEVICE_UPDATED 3
edd16368 1199 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1200 if (haystack[i] == NULL) /* previously removed. */
1201 continue;
edd16368
SC		 1202 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1203 *index = i;
bd9244f7
ST		 1204 if (device_is_the_same(needle, haystack[i])) {
1205 if (device_updated(needle, haystack[i]))
1206 return DEVICE_UPDATED;
edd16368 1207 return DEVICE_SAME;
bd9244f7 1208 } else {
9846590e
SC		 1209 /* Keep offline devices offline */
1210 if (needle->volume_offline)
1211 return DEVICE_NOT_FOUND;
edd16368 1212 return DEVICE_CHANGED;
bd9244f7 1213 }
edd16368
SC		 1214 }
1215 }
1216 *index = -1;
1217 return DEVICE_NOT_FOUND;
1218}
1219
9846590e
SC		 1220static void hpsa_monitor_offline_device(struct ctlr_info *h,
1221 unsigned char scsi3addr[])
1222{
1223 struct offline_device_entry *device;
1224 unsigned long flags;
1225
1226 /* Check to see if device is already on the list */
1227 spin_lock_irqsave(&h->offline_device_lock, flags);
1228 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1229 if (memcmp(device->scsi3addr, scsi3addr,
1230 sizeof(device->scsi3addr)) == 0) {
1231 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1232 return;
1233 }
1234 }
1235 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1236
1237 /* Device is not on the list, add it. */
1238 device = kmalloc(sizeof(*device), GFP_KERNEL);
1239 if (!device) {
1240 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1241 return;
1242 }
1243 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1244 spin_lock_irqsave(&h->offline_device_lock, flags);
1245 list_add_tail(&device->offline_list, &h->offline_device_list);
1246 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1247}
1248
1249/* Print a message explaining various offline volume states */
1250static void hpsa_show_volume_status(struct ctlr_info *h,
1251 struct hpsa_scsi_dev_t *sd)
1252{
1253 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1254 dev_info(&h->pdev->dev,
1255 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1256 h->scsi_host->host_no,
1257 sd->bus, sd->target, sd->lun);
1258 switch (sd->volume_offline) {
1259 case HPSA_LV_OK:
1260 break;
1261 case HPSA_LV_UNDERGOING_ERASE:
1262 dev_info(&h->pdev->dev,
1263 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1264 h->scsi_host->host_no,
1265 sd->bus, sd->target, sd->lun);
1266 break;
1267 case HPSA_LV_UNDERGOING_RPI:
1268 dev_info(&h->pdev->dev,
1269 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1270 h->scsi_host->host_no,
1271 sd->bus, sd->target, sd->lun);
1272 break;
1273 case HPSA_LV_PENDING_RPI:
1274 dev_info(&h->pdev->dev,
1275 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1276 h->scsi_host->host_no,
1277 sd->bus, sd->target, sd->lun);
1278 break;
1279 case HPSA_LV_ENCRYPTED_NO_KEY:
1280 dev_info(&h->pdev->dev,
1281 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1282 h->scsi_host->host_no,
1283 sd->bus, sd->target, sd->lun);
1284 break;
1285 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1286 dev_info(&h->pdev->dev,
1287 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1288 h->scsi_host->host_no,
1289 sd->bus, sd->target, sd->lun);
1290 break;
1291 case HPSA_LV_UNDERGOING_ENCRYPTION:
1292 dev_info(&h->pdev->dev,
1293 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1294 h->scsi_host->host_no,
1295 sd->bus, sd->target, sd->lun);
1296 break;
1297 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1298 dev_info(&h->pdev->dev,
1299 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1300 h->scsi_host->host_no,
1301 sd->bus, sd->target, sd->lun);
1302 break;
1303 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1304 dev_info(&h->pdev->dev,
1305 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1306 h->scsi_host->host_no,
1307 sd->bus, sd->target, sd->lun);
1308 break;
1309 case HPSA_LV_PENDING_ENCRYPTION:
1310 dev_info(&h->pdev->dev,
1311 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1312 h->scsi_host->host_no,
1313 sd->bus, sd->target, sd->lun);
1314 break;
1315 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1316 dev_info(&h->pdev->dev,
1317 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1318 h->scsi_host->host_no,
1319 sd->bus, sd->target, sd->lun);
1320 break;
1321 }
1322}
1323
03383736
DB		 1324/*
1325 * Figure the list of physical drive pointers for a logical drive with
1326 * raid offload configured.
1327 */
1328static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1329 struct hpsa_scsi_dev_t *dev[], int ndevices,
1330 struct hpsa_scsi_dev_t *logical_drive)
1331{
1332 struct raid_map_data *map = &logical_drive->raid_map;
1333 struct raid_map_disk_data *dd = &map->data[0];
1334 int i, j;
1335 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1336 le16_to_cpu(map->metadata_disks_per_row);
1337 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1338 le16_to_cpu(map->layout_map_count) *
1339 total_disks_per_row;
1340 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1341 total_disks_per_row;
1342 int qdepth;
1343
1344 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1345 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1346
1347 qdepth = 0;
1348 for (i = 0; i < nraid_map_entries; i++) {
1349 logical_drive->phys_disk[i] = NULL;
1350 if (!logical_drive->offload_config)
1351 continue;
1352 for (j = 0; j < ndevices; j++) {
1353 if (dev[j]->devtype != TYPE_DISK)
1354 continue;
1355 if (is_logical_dev_addr_mode(dev[j]->scsi3addr))
1356 continue;
1357 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1358 continue;
1359
1360 logical_drive->phys_disk[i] = dev[j];
1361 if (i < nphys_disk)
1362 qdepth = min(h->nr_cmds, qdepth +
1363 logical_drive->phys_disk[i]->queue_depth);
1364 break;
1365 }
1366
1367 /*
1368 * This can happen if a physical drive is removed and
1369 * the logical drive is degraded. In that case, the RAID
1370 * map data will refer to a physical disk which isn't actually
1371 * present. And in that case offload_enabled should already
1372 * be 0, but we'll turn it off here just in case
1373 */
1374 if (!logical_drive->phys_disk[i]) {
1375 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1376 logical_drive->offload_to_be_enabled = 0;
1377 logical_drive->queue_depth = 8;
03383736
DB		 1378 }
1379 }
1380 if (nraid_map_entries)
1381 /*
1382 * This is correct for reads, too high for full stripe writes,
1383 * way too high for partial stripe writes
1384 */
1385 logical_drive->queue_depth = qdepth;
1386 else
1387 logical_drive->queue_depth = h->nr_cmds;
1388}
1389
1390static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1391 struct hpsa_scsi_dev_t *dev[], int ndevices)
1392{
1393 int i;
1394
1395 for (i = 0; i < ndevices; i++) {
1396 if (dev[i]->devtype != TYPE_DISK)
1397 continue;
1398 if (!is_logical_dev_addr_mode(dev[i]->scsi3addr))
1399 continue;
41ce4c35
SC		 1400
1401 /*
1402 * If offload is currently enabled, the RAID map and
1403 * phys_disk[] assignment *better* not be changing
1404 * and since it isn't changing, we do not need to
1405 * update it.
1406 */
1407 if (dev[i]->offload_enabled)
1408 continue;
1409
03383736
DB		 1410 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1411 }
1412}
1413
4967bd3e 1414static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1415 struct hpsa_scsi_dev_t *sd[], int nsds)
1416{
1417 /* sd contains scsi3 addresses and devtypes, and inquiry
1418 * data. This function takes what's in sd to be the current
1419 * reality and updates h->dev[] to reflect that reality.
1420 */
1421 int i, entry, device_change, changes = 0;
1422 struct hpsa_scsi_dev_t *csd;
1423 unsigned long flags;
1424 struct hpsa_scsi_dev_t **added, **removed;
1425 int nadded, nremoved;
1426 struct Scsi_Host *sh = NULL;
1427
cfe5badc
ST		 1428 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1429 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1430
1431 if (!added || !removed) {
1432 dev_warn(&h->pdev->dev, "out of memory in "
1433 "adjust_hpsa_scsi_table\n");
1434 goto free_and_out;
1435 }
1436
1437 spin_lock_irqsave(&h->devlock, flags);
1438
1439 /* find any devices in h->dev[] that are not in
1440 * sd[] and remove them from h->dev[], and for any
1441 * devices which have changed, remove the old device
1442 * info and add the new device info.
bd9244f7
ST		 1443 * If minor device attributes change, just update
1444 * the existing device structure.
edd16368
SC		 1445 */
1446 i = 0;
1447 nremoved = 0;
1448 nadded = 0;
1449 while (i < h->ndevices) {
1450 csd = h->dev[i];
1451 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1452 if (device_change == DEVICE_NOT_FOUND) {
1453 changes++;
1454 hpsa_scsi_remove_entry(h, hostno, i,
1455 removed, &nremoved);
1456 continue; /* remove ^^^, hence i not incremented */
1457 } else if (device_change == DEVICE_CHANGED) {
1458 changes++;
2a8ccf31
SC		 1459 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1460 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1461 /* Set it to NULL to prevent it from being freed
1462 * at the bottom of hpsa_update_scsi_devices()
1463 */
1464 sd[entry] = NULL;
bd9244f7
ST		 1465 } else if (device_change == DEVICE_UPDATED) {
1466 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1467 }
1468 i++;
1469 }
1470
1471 /* Now, make sure every device listed in sd[] is also
1472 * listed in h->dev[], adding them if they aren't found
1473 */
1474
1475 for (i = 0; i < nsds; i++) {
1476 if (!sd[i]) /* if already added above. */
1477 continue;
9846590e
SC		 1478
1479 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1480 * as the SCSI mid-layer does not handle such devices well.
1481 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1482 * at 160Hz, and prevents the system from coming up.
1483 */
1484 if (sd[i]->volume_offline) {
1485 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1486 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1487 continue;
1488 }
1489
edd16368
SC		 1490 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1491 h->ndevices, &entry);
1492 if (device_change == DEVICE_NOT_FOUND) {
1493 changes++;
1494 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1495 added, &nadded) != 0)
1496 break;
1497 sd[i] = NULL; /* prevent from being freed later. */
1498 } else if (device_change == DEVICE_CHANGED) {
1499 /* should never happen... */
1500 changes++;
1501 dev_warn(&h->pdev->dev,
1502 "device unexpectedly changed.\n");
1503 /* but if it does happen, we just ignore that device */
1504 }
1505 }
41ce4c35
SC		 1506 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1507
1508 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1509 * any logical drives that need it enabled.
1510 */
1511 for (i = 0; i < h->ndevices; i++)
1512 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1513
edd16368
SC		 1514 spin_unlock_irqrestore(&h->devlock, flags);
1515
9846590e
SC		 1516 /* Monitor devices which are in one of several NOT READY states to be
1517 * brought online later. This must be done without holding h->devlock,
1518 * so don't touch h->dev[]
1519 */
1520 for (i = 0; i < nsds; i++) {
1521 if (!sd[i]) /* if already added above. */
1522 continue;
1523 if (sd[i]->volume_offline)
1524 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1525 }
1526
edd16368
SC		 1527 /* Don't notify scsi mid layer of any changes the first time through
1528 * (or if there are no changes) scsi_scan_host will do it later the
1529 * first time through.
1530 */
1531 if (hostno == -1 || !changes)
1532 goto free_and_out;
1533
1534 sh = h->scsi_host;
1535 /* Notify scsi mid layer of any removed devices */
1536 for (i = 0; i < nremoved; i++) {
41ce4c35
SC		 1537 if (removed[i]->expose_state & HPSA_SCSI_ADD) {
1538 struct scsi_device *sdev =
1539 scsi_device_lookup(sh, removed[i]->bus,
1540 removed[i]->target, removed[i]->lun);
1541 if (sdev != NULL) {
1542 scsi_remove_device(sdev);
1543 scsi_device_put(sdev);
1544 } else {
1545 /*
1546 * We don't expect to get here.
1547 * future cmds to this device will get selection
1548 * timeout as if the device was gone.
1549 */
0d96ef5f
WS		 1550 hpsa_show_dev_msg(KERN_WARNING, h, removed[i],
1551 "didn't find device for removal.");
41ce4c35 1552 }
edd16368
SC		 1553 }
1554 kfree(removed[i]);
1555 removed[i] = NULL;
1556 }
1557
1558 /* Notify scsi mid layer of any added devices */
1559 for (i = 0; i < nadded; i++) {
41ce4c35
SC		 1560 if (!(added[i]->expose_state & HPSA_SCSI_ADD))
1561 continue;
edd16368
SC		 1562 if (scsi_add_device(sh, added[i]->bus,
1563 added[i]->target, added[i]->lun) == 0)
1564 continue;
0d96ef5f
WS		 1565 hpsa_show_dev_msg(KERN_WARNING, h, added[i],
1566 "addition failed, device not added.");
edd16368
SC		 1567 /* now we have to remove it from h->dev,
1568 * since it didn't get added to scsi mid layer
1569 */
1570 fixup_botched_add(h, added[i]);
1571 }
1572
1573free_and_out:
1574 kfree(added);
1575 kfree(removed);
edd16368
SC		 1576}
1577
1578/*
9e03aa2f 1579 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1580 * Assume's h->devlock is held.
1581 */
1582static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1583 int bus, int target, int lun)
1584{
1585 int i;
1586 struct hpsa_scsi_dev_t *sd;
1587
1588 for (i = 0; i < h->ndevices; i++) {
1589 sd = h->dev[i];
1590 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1591 return sd;
1592 }
1593 return NULL;
1594}
1595
edd16368
SC		 1596static int hpsa_slave_alloc(struct scsi_device *sdev)
1597{
1598 struct hpsa_scsi_dev_t *sd;
1599 unsigned long flags;
1600 struct ctlr_info *h;
1601
1602 h = sdev_to_hba(sdev);
1603 spin_lock_irqsave(&h->devlock, flags);
1604 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1605 sdev_id(sdev), sdev->lun);
41ce4c35 1606 if (likely(sd)) {
03383736 1607 atomic_set(&sd->ioaccel_cmds_out, 0);
41ce4c35
SC		 1608 sdev->hostdata = (sd->expose_state & HPSA_SCSI_ADD) ? sd : NULL;
1609 } else
1610 sdev->hostdata = NULL;
edd16368
SC		 1611 spin_unlock_irqrestore(&h->devlock, flags);
1612 return 0;
1613}
1614
41ce4c35
SC		 1615/* configure scsi device based on internal per-device structure */
1616static int hpsa_slave_configure(struct scsi_device *sdev)
1617{
1618 struct hpsa_scsi_dev_t *sd;
1619 int queue_depth;
1620
1621 sd = sdev->hostdata;
1622 sdev->no_uld_attach = !sd || !(sd->expose_state & HPSA_ULD_ATTACH);
1623
1624 if (sd)
1625 queue_depth = sd->queue_depth != 0 ?
1626 sd->queue_depth : sdev->host->can_queue;
1627 else
1628 queue_depth = sdev->host->can_queue;
1629
1630 scsi_change_queue_depth(sdev, queue_depth);
1631
1632 return 0;
1633}
1634
edd16368
SC		 1635static void hpsa_slave_destroy(struct scsi_device *sdev)
1636{
bcc44255 1637 /* nothing to do. */
edd16368
SC		 1638}
1639
33a2ffce
SC		 1640static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1641{
1642 int i;
1643
1644 if (!h->cmd_sg_list)
1645 return;
1646 for (i = 0; i < h->nr_cmds; i++) {
1647 kfree(h->cmd_sg_list[i]);
1648 h->cmd_sg_list[i] = NULL;
1649 }
1650 kfree(h->cmd_sg_list);
1651 h->cmd_sg_list = NULL;
1652}
1653
1654static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1655{
1656 int i;
1657
1658 if (h->chainsize <= 0)
1659 return 0;
1660
1661 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1662 GFP_KERNEL);
3d4e6af8
RE		 1663 if (!h->cmd_sg_list) {
1664 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1665 return -ENOMEM;
3d4e6af8 1666 }
33a2ffce
SC		 1667 for (i = 0; i < h->nr_cmds; i++) {
1668 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1669 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1670 if (!h->cmd_sg_list[i]) {
1671 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1672 goto clean;
3d4e6af8 1673 }
33a2ffce
SC		 1674 }
1675 return 0;
1676
1677clean:
1678 hpsa_free_sg_chain_blocks(h);
1679 return -ENOMEM;
1680}
1681
e2bea6df 1682static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1683 struct CommandList *c)
1684{
1685 struct SGDescriptor *chain_sg, *chain_block;
1686 u64 temp64;
50a0decf 1687 u32 chain_len;
33a2ffce
SC		 1688
1689 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1690 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 1691 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1692 chain_len = sizeof(*chain_sg) *
2b08b3e9 1693 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 1694 chain_sg->Len = cpu_to_le32(chain_len);
1695 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 1696 PCI_DMA_TODEVICE);
e2bea6df
SC		 1697 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1698 /* prevent subsequent unmapping */
50a0decf 1699 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 1700 return -1;
1701 }
50a0decf 1702 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 1703 return 0;
33a2ffce
SC		 1704}
1705
1706static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1707 struct CommandList *c)
1708{
1709 struct SGDescriptor *chain_sg;
33a2ffce 1710
50a0decf 1711 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 1712 return;
1713
1714 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 1715 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
1716 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 1717}
1718
a09c1441
ST		 1719
1720/* Decode the various types of errors on ioaccel2 path.
1721 * Return 1 for any error that should generate a RAID path retry.
1722 * Return 0 for errors that don't require a RAID path retry.
1723 */
1724static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1725 struct CommandList *c,
1726 struct scsi_cmnd *cmd,
1727 struct io_accel2_cmd *c2)
1728{
1729 int data_len;
a09c1441 1730 int retry = 0;
c349775e
ST		 1731
1732 switch (c2->error_data.serv_response) {
1733 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1734 switch (c2->error_data.status) {
1735 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1736 break;
1737 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1738 dev_warn(&h->pdev->dev,
1739 "%s: task complete with check condition.\n",
1740 "HP SSD Smart Path");
ee6b1889 1741 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 1742 if (c2->error_data.data_present !=
ee6b1889
SC		 1743 IOACCEL2_SENSE_DATA_PRESENT) {
1744 memset(cmd->sense_buffer, 0,
1745 SCSI_SENSE_BUFFERSIZE);
c349775e 1746 break;
ee6b1889 1747 }
c349775e
ST		 1748 /* copy the sense data */
1749 data_len = c2->error_data.sense_data_len;
1750 if (data_len > SCSI_SENSE_BUFFERSIZE)
1751 data_len = SCSI_SENSE_BUFFERSIZE;
1752 if (data_len > sizeof(c2->error_data.sense_data_buff))
1753 data_len =
1754 sizeof(c2->error_data.sense_data_buff);
1755 memcpy(cmd->sense_buffer,
1756 c2->error_data.sense_data_buff, data_len);
a09c1441 1757 retry = 1;
c349775e
ST		 1758 break;
1759 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1760 dev_warn(&h->pdev->dev,
1761 "%s: task complete with BUSY status.\n",
1762 "HP SSD Smart Path");
a09c1441 1763 retry = 1;
c349775e
ST		 1764 break;
1765 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1766 dev_warn(&h->pdev->dev,
1767 "%s: task complete with reservation conflict.\n",
1768 "HP SSD Smart Path");
a09c1441 1769 retry = 1;
c349775e
ST		 1770 break;
1771 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1772 /* Make scsi midlayer do unlimited retries */
1773 cmd->result = DID_IMM_RETRY << 16;
1774 break;
1775 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1776 dev_warn(&h->pdev->dev,
1777 "%s: task complete with aborted status.\n",
1778 "HP SSD Smart Path");
a09c1441 1779 retry = 1;
c349775e
ST		 1780 break;
1781 default:
1782 dev_warn(&h->pdev->dev,
1783 "%s: task complete with unrecognized status: 0x%02x\n",
1784 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1785 retry = 1;
c349775e
ST		 1786 break;
1787 }
1788 break;
1789 case IOACCEL2_SERV_RESPONSE_FAILURE:
1790 /* don't expect to get here. */
1791 dev_warn(&h->pdev->dev,
1792 "unexpected delivery or target failure, status = 0x%02x\n",
1793 c2->error_data.status);
a09c1441 1794 retry = 1;
c349775e
ST		 1795 break;
1796 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1797 break;
1798 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1799 break;
1800 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1801 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1802 retry = 1;
c349775e
ST		 1803 break;
1804 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1805 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1806 break;
1807 default:
1808 dev_warn(&h->pdev->dev,
1809 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1810 "HP SSD Smart Path",
1811 c2->error_data.serv_response);
1812 retry = 1;
c349775e
ST		 1813 break;
1814 }
a09c1441
ST		 1815
1816 return retry; /* retry on raid path? */
c349775e
ST		 1817}
1818
1819static void process_ioaccel2_completion(struct ctlr_info *h,
1820 struct CommandList *c, struct scsi_cmnd *cmd,
1821 struct hpsa_scsi_dev_t *dev)
1822{
1823 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
1824
1825 /* check for good status */
1826 if (likely(c2->error_data.serv_response == 0 &&
1827 c2->error_data.status == 0)) {
1828 cmd_free(h, c);
1829 cmd->scsi_done(cmd);
1830 return;
1831 }
1832
1833 /* Any RAID offload error results in retry which will use
1834 * the normal I/O path so the controller can handle whatever's
1835 * wrong.
1836 */
1837 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1838 c2->error_data.serv_response ==
1839 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 1840 if (c2->error_data.status ==
1841 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1842 dev->offload_enabled = 0;
1843 goto retry_cmd;
a09c1441 1844 }
080ef1cc
DB		 1845
1846 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
1847 goto retry_cmd;
1848
c349775e
ST		 1849 cmd_free(h, c);
1850 cmd->scsi_done(cmd);
080ef1cc
DB		 1851 return;
1852
1853retry_cmd:
1854 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
1855 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
c349775e
ST		 1856}
1857
1fb011fb 1858static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1859{
1860 struct scsi_cmnd *cmd;
1861 struct ctlr_info *h;
1862 struct ErrorInfo *ei;
283b4a9b 1863 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1864
1865 unsigned char sense_key;
1866 unsigned char asc; /* additional sense code */
1867 unsigned char ascq; /* additional sense code qualifier */
db111e18 1868 unsigned long sense_data_size;
edd16368
SC		 1869
1870 ei = cp->err_info;
7fa3030c 1871 cmd = cp->scsi_cmd;
edd16368 1872 h = cp->h;
283b4a9b 1873 dev = cmd->device->hostdata;
edd16368
SC		 1874
1875 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 1876 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 1877 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 1878 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1879
1880 cmd->result = (DID_OK << 16); /* host byte */
1881 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 1882
03383736
DB		 1883 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
1884 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
1885
25163bd5
WS		 1886 /*
1887 * We check for lockup status here as it may be set for
1888 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
1889 * fail_all_oustanding_cmds()
1890 */
1891 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
1892 /* DID_NO_CONNECT will prevent a retry */
1893 cmd->result = DID_NO_CONNECT << 16;
1894 cmd_free(h, cp);
1895 cmd->scsi_done(cmd);
1896 return;
1897 }
1898
c349775e
ST		 1899 if (cp->cmd_type == CMD_IOACCEL2)
1900 return process_ioaccel2_completion(h, cp, cmd, dev);
1901
5512672f 1902 cmd->result |= ei->ScsiStatus;
edd16368 1903
6aa4c361
RE		 1904 scsi_set_resid(cmd, ei->ResidualCnt);
1905 if (ei->CommandStatus == 0) {
03383736
DB		 1906 if (cp->cmd_type == CMD_IOACCEL1)
1907 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
6aa4c361
RE		 1908 cmd_free(h, cp);
1909 cmd->scsi_done(cmd);
1910 return;
1911 }
1912
1913 /* copy the sense data */
db111e18
SC		 1914 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1915 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1916 else
1917 sense_data_size = sizeof(ei->SenseInfo);
1918 if (ei->SenseLen < sense_data_size)
1919 sense_data_size = ei->SenseLen;
1920
1921 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368 1922
e1f7de0c
MG		 1923 /* For I/O accelerator commands, copy over some fields to the normal
1924 * CISS header used below for error handling.
1925 */
1926 if (cp->cmd_type == CMD_IOACCEL1) {
1927 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 1928 cp->Header.SGList = scsi_sg_count(cmd);
1929 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
1930 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
1931 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 1932 cp->Header.tag = c->tag;
e1f7de0c
MG		 1933 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1934 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1935
1936 /* Any RAID offload error results in retry which will use
1937 * the normal I/O path so the controller can handle whatever's
1938 * wrong.
1939 */
1940 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1941 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1942 dev->offload_enabled = 0;
080ef1cc
DB		 1943 INIT_WORK(&cp->work, hpsa_command_resubmit_worker);
1944 queue_work_on(raw_smp_processor_id(),
1945 h->resubmit_wq, &cp->work);
283b4a9b
SC		 1946 return;
1947 }
e1f7de0c
MG		 1948 }
1949
edd16368
SC		 1950 /* an error has occurred */
1951 switch (ei->CommandStatus) {
1952
1953 case CMD_TARGET_STATUS:
1954 if (ei->ScsiStatus) {
1955 /* Get sense key */
1956 sense_key = 0xf & ei->SenseInfo[2];
1957 /* Get additional sense code */
1958 asc = ei->SenseInfo[12];
1959 /* Get addition sense code qualifier */
1960 ascq = ei->SenseInfo[13];
1961 }
edd16368 1962 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 1963 if (sense_key == ABORTED_COMMAND) {
2e311fba 1964 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1965 break;
1966 }
edd16368
SC		 1967 break;
1968 }
edd16368
SC		 1969 /* Problem was not a check condition
1970 * Pass it up to the upper layers...
1971 */
1972 if (ei->ScsiStatus) {
1973 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1974 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1975 "Returning result: 0x%x\n",
1976 cp, ei->ScsiStatus,
1977 sense_key, asc, ascq,
1978 cmd->result);
1979 } else { /* scsi status is zero??? How??? */
1980 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1981 "Returning no connection.\n", cp),
1982
1983 /* Ordinarily, this case should never happen,
1984 * but there is a bug in some released firmware
1985 * revisions that allows it to happen if, for
1986 * example, a 4100 backplane loses power and
1987 * the tape drive is in it. We assume that
1988 * it's a fatal error of some kind because we
1989 * can't show that it wasn't. We will make it
1990 * look like selection timeout since that is
1991 * the most common reason for this to occur,
1992 * and it's severe enough.
1993 */
1994
1995 cmd->result = DID_NO_CONNECT << 16;
1996 }
1997 break;
1998
1999 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2000 break;
2001 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2002 dev_warn(&h->pdev->dev,
2003 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2004 break;
2005 case CMD_INVALID: {
2006 /* print_bytes(cp, sizeof(*cp), 1, 0);
2007 print_cmd(cp); */
2008 /* We get CMD_INVALID if you address a non-existent device
2009 * instead of a selection timeout (no response). You will
2010 * see this if you yank out a drive, then try to access it.
2011 * This is kind of a shame because it means that any other
2012 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2013 * missing target. */
2014 cmd->result = DID_NO_CONNECT << 16;
2015 }
2016 break;
2017 case CMD_PROTOCOL_ERR:
256d0eaa 2018 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2019 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2020 cp->Request.CDB);
edd16368
SC		 2021 break;
2022 case CMD_HARDWARE_ERR:
2023 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2024 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2025 cp->Request.CDB);
edd16368
SC		 2026 break;
2027 case CMD_CONNECTION_LOST:
2028 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2029 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2030 cp->Request.CDB);
edd16368
SC		 2031 break;
2032 case CMD_ABORTED:
2033 cmd->result = DID_ABORT << 16;
f42e81e1
SC		 2034 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2035 cp->Request.CDB, ei->ScsiStatus);
edd16368
SC		 2036 break;
2037 case CMD_ABORT_FAILED:
2038 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2039 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2040 cp->Request.CDB);
edd16368
SC		 2041 break;
2042 case CMD_UNSOLICITED_ABORT:
f6e76055 2043 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2044 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2045 cp->Request.CDB);
edd16368
SC		 2046 break;
2047 case CMD_TIMEOUT:
2048 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2049 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2050 cp->Request.CDB);
edd16368 2051 break;
1d5e2ed0
SC		 2052 case CMD_UNABORTABLE:
2053 cmd->result = DID_ERROR << 16;
2054 dev_warn(&h->pdev->dev, "Command unabortable\n");
2055 break;
283b4a9b
SC		 2056 case CMD_IOACCEL_DISABLED:
2057 /* This only handles the direct pass-through case since RAID
2058 * offload is handled above. Just attempt a retry.
2059 */
2060 cmd->result = DID_SOFT_ERROR << 16;
2061 dev_warn(&h->pdev->dev,
2062 "cp %p had HP SSD Smart Path error\n", cp);
2063 break;
edd16368
SC		 2064 default:
2065 cmd->result = DID_ERROR << 16;
2066 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2067 cp, ei->CommandStatus);
2068 }
edd16368 2069 cmd_free(h, cp);
2cc5bfaf 2070 cmd->scsi_done(cmd);
edd16368
SC		 2071}
2072
edd16368
SC		 2073static void hpsa_pci_unmap(struct pci_dev *pdev,
2074 struct CommandList *c, int sg_used, int data_direction)
2075{
2076 int i;
edd16368 2077
50a0decf
SC		 2078 for (i = 0; i < sg_used; i++)
2079 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2080 le32_to_cpu(c->SG[i].Len),
2081 data_direction);
edd16368
SC		 2082}
2083
a2dac136 2084static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2085 struct CommandList *cp,
2086 unsigned char *buf,
2087 size_t buflen,
2088 int data_direction)
2089{
01a02ffc 2090 u64 addr64;
edd16368
SC		 2091
2092 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2093 cp->Header.SGList = 0;
50a0decf 2094 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2095 return 0;
edd16368
SC		 2096 }
2097
50a0decf 2098 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2099 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2100 /* Prevent subsequent unmap of something never mapped */
eceaae18 2101 cp->Header.SGList = 0;
50a0decf 2102 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2103 return -1;
eceaae18 2104 }
50a0decf
SC		 2105 cp->SG[0].Addr = cpu_to_le64(addr64);
2106 cp->SG[0].Len = cpu_to_le32(buflen);
2107 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2108 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2109 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2110 return 0;
edd16368
SC		 2111}
2112
25163bd5
WS		 2113#define NO_TIMEOUT ((unsigned long) -1)
2114#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2115static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2116 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2117{
2118 DECLARE_COMPLETION_ONSTACK(wait);
2119
2120 c->waiting = &wait;
25163bd5
WS		 2121 __enqueue_cmd_and_start_io(h, c, reply_queue);
2122 if (timeout_msecs == NO_TIMEOUT) {
2123 /* TODO: get rid of this no-timeout thing */
2124 wait_for_completion_io(&wait);
2125 return IO_OK;
2126 }
2127 if (!wait_for_completion_io_timeout(&wait,
2128 msecs_to_jiffies(timeout_msecs))) {
2129 dev_warn(&h->pdev->dev, "Command timed out.\n");
2130 return -ETIMEDOUT;
2131 }
2132 return IO_OK;
2133}
2134
2135static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2136 int reply_queue, unsigned long timeout_msecs)
2137{
2138 if (unlikely(lockup_detected(h))) {
2139 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2140 return IO_OK;
2141 }
2142 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2143}
2144
094963da
SC		 2145static u32 lockup_detected(struct ctlr_info *h)
2146{
2147 int cpu;
2148 u32 rc, *lockup_detected;
2149
2150 cpu = get_cpu();
2151 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2152 rc = *lockup_detected;
2153 put_cpu();
2154 return rc;
2155}
2156
9c2fc160 2157#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2158static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2159 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2160{
9c2fc160 2161 int backoff_time = 10, retry_count = 0;
25163bd5 2162 int rc;
edd16368
SC		 2163
2164 do {
7630abd0 2165 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2166 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2167 timeout_msecs);
2168 if (rc)
2169 break;
edd16368 2170 retry_count++;
9c2fc160
SC		 2171 if (retry_count > 3) {
2172 msleep(backoff_time);
2173 if (backoff_time < 1000)
2174 backoff_time *= 2;
2175 }
852af20a 2176 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2177 check_for_busy(h, c)) &&
2178 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2179 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2180 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2181 rc = -EIO;
2182 return rc;
edd16368
SC		 2183}
2184
d1e8beac
SC		 2185static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2186 struct CommandList *c)
edd16368 2187{
d1e8beac
SC		 2188 const u8 *cdb = c->Request.CDB;
2189 const u8 *lun = c->Header.LUN.LunAddrBytes;
2190
2191 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2192 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2193 txt, lun[0], lun[1], lun[2], lun[3],
2194 lun[4], lun[5], lun[6], lun[7],
2195 cdb[0], cdb[1], cdb[2], cdb[3],
2196 cdb[4], cdb[5], cdb[6], cdb[7],
2197 cdb[8], cdb[9], cdb[10], cdb[11],
2198 cdb[12], cdb[13], cdb[14], cdb[15]);
2199}
2200
2201static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2202 struct CommandList *cp)
2203{
2204 const struct ErrorInfo *ei = cp->err_info;
edd16368 2205 struct device *d = &cp->h->pdev->dev;
d1e8beac 2206 const u8 *sd = ei->SenseInfo;
edd16368 2207
edd16368
SC		 2208 switch (ei->CommandStatus) {
2209 case CMD_TARGET_STATUS:
d1e8beac
SC		 2210 hpsa_print_cmd(h, "SCSI status", cp);
2211 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
2212 dev_warn(d, "SCSI Status = 02, Sense key = %02x, ASC = %02x, ASCQ = %02x\n",
2213 sd[2] & 0x0f, sd[12], sd[13]);
2214 else
2215 dev_warn(d, "SCSI Status = %02x\n", ei->ScsiStatus);
edd16368
SC		 2216 if (ei->ScsiStatus == 0)
2217 dev_warn(d, "SCSI status is abnormally zero. "
2218 "(probably indicates selection timeout "
2219 "reported incorrectly due to a known "
2220 "firmware bug, circa July, 2001.)\n");
2221 break;
2222 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2223 break;
2224 case CMD_DATA_OVERRUN:
d1e8beac 2225 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2226 break;
2227 case CMD_INVALID: {
2228 /* controller unfortunately reports SCSI passthru's
2229 * to non-existent targets as invalid commands.
2230 */
d1e8beac
SC		 2231 hpsa_print_cmd(h, "invalid command", cp);
2232 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2233 }
2234 break;
2235 case CMD_PROTOCOL_ERR:
d1e8beac 2236 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2237 break;
2238 case CMD_HARDWARE_ERR:
d1e8beac 2239 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2240 break;
2241 case CMD_CONNECTION_LOST:
d1e8beac 2242 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2243 break;
2244 case CMD_ABORTED:
d1e8beac 2245 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2246 break;
2247 case CMD_ABORT_FAILED:
d1e8beac 2248 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2249 break;
2250 case CMD_UNSOLICITED_ABORT:
d1e8beac 2251 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2252 break;
2253 case CMD_TIMEOUT:
d1e8beac 2254 hpsa_print_cmd(h, "timed out", cp);
edd16368 2255 break;
1d5e2ed0 2256 case CMD_UNABORTABLE:
d1e8beac 2257 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2258 break;
25163bd5
WS		 2259 case CMD_CTLR_LOCKUP:
2260 hpsa_print_cmd(h, "controller lockup detected", cp);
2261 break;
edd16368 2262 default:
d1e8beac
SC		 2263 hpsa_print_cmd(h, "unknown status", cp);
2264 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2265 ei->CommandStatus);
2266 }
2267}
2268
2269static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2270 u16 page, unsigned char *buf,
edd16368
SC		 2271 unsigned char bufsize)
2272{
2273 int rc = IO_OK;
2274 struct CommandList *c;
2275 struct ErrorInfo *ei;
2276
45fcb86e 2277 c = cmd_alloc(h);
edd16368 2278
574f05d3 2279 if (c == NULL) {
45fcb86e 2280 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
ecd9aad4 2281 return -ENOMEM;
edd16368
SC		 2282 }
2283
a2dac136
SC		 2284 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2285 page, scsi3addr, TYPE_CMD)) {
2286 rc = -1;
2287 goto out;
2288 }
25163bd5
WS		 2289 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2290 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2291 if (rc)
2292 goto out;
edd16368
SC		 2293 ei = c->err_info;
2294 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2295 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2296 rc = -1;
2297 }
a2dac136 2298out:
45fcb86e 2299 cmd_free(h, c);
edd16368
SC		 2300 return rc;
2301}
2302
316b221a
SC		 2303static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2304 unsigned char *scsi3addr, unsigned char page,
2305 struct bmic_controller_parameters *buf, size_t bufsize)
2306{
2307 int rc = IO_OK;
2308 struct CommandList *c;
2309 struct ErrorInfo *ei;
2310
45fcb86e 2311 c = cmd_alloc(h);
316b221a 2312 if (c == NULL) { /* trouble... */
45fcb86e 2313 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
316b221a
SC		 2314 return -ENOMEM;
2315 }
2316
2317 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2318 page, scsi3addr, TYPE_CMD)) {
2319 rc = -1;
2320 goto out;
2321 }
25163bd5
WS		 2322 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2323 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2324 if (rc)
2325 goto out;
316b221a
SC		 2326 ei = c->err_info;
2327 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2328 hpsa_scsi_interpret_error(h, c);
2329 rc = -1;
2330 }
2331out:
45fcb86e 2332 cmd_free(h, c);
316b221a
SC		 2333 return rc;
2334 }
2335
bf711ac6 2336static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2337 u8 reset_type, int reply_queue)
edd16368
SC		 2338{
2339 int rc = IO_OK;
2340 struct CommandList *c;
2341 struct ErrorInfo *ei;
2342
45fcb86e 2343 c = cmd_alloc(h);
edd16368
SC		 2344
2345 if (c == NULL) { /* trouble... */
45fcb86e 2346 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
e9ea04a6 2347 return -ENOMEM;
edd16368
SC		 2348 }
2349
a2dac136 2350 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2351 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2352 scsi3addr, TYPE_MSG);
2353 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
25163bd5
WS		 2354 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2355 if (rc) {
2356 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2357 goto out;
2358 }
edd16368
SC		 2359 /* no unmap needed here because no data xfer. */
2360
2361 ei = c->err_info;
2362 if (ei->CommandStatus != 0) {
d1e8beac 2363 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2364 rc = -1;
2365 }
25163bd5 2366out:
45fcb86e 2367 cmd_free(h, c);
edd16368
SC		 2368 return rc;
2369}
2370
2371static void hpsa_get_raid_level(struct ctlr_info *h,
2372 unsigned char *scsi3addr, unsigned char *raid_level)
2373{
2374 int rc;
2375 unsigned char *buf;
2376
2377 *raid_level = RAID_UNKNOWN;
2378 buf = kzalloc(64, GFP_KERNEL);
2379 if (!buf)
2380 return;
b7bb24eb 2381 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2382 if (rc == 0)
2383 *raid_level = buf[8];
2384 if (*raid_level > RAID_UNKNOWN)
2385 *raid_level = RAID_UNKNOWN;
2386 kfree(buf);
2387 return;
2388}
2389
283b4a9b
SC		 2390#define HPSA_MAP_DEBUG
2391#ifdef HPSA_MAP_DEBUG
2392static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2393 struct raid_map_data *map_buff)
2394{
2395 struct raid_map_disk_data *dd = &map_buff->data[0];
2396 int map, row, col;
2397 u16 map_cnt, row_cnt, disks_per_row;
2398
2399 if (rc != 0)
2400 return;
2401
2ba8bfc8
SC		 2402 /* Show details only if debugging has been activated. */
2403 if (h->raid_offload_debug < 2)
2404 return;
2405
283b4a9b
SC		 2406 dev_info(&h->pdev->dev, "structure_size = %u\n",
2407 le32_to_cpu(map_buff->structure_size));
2408 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2409 le32_to_cpu(map_buff->volume_blk_size));
2410 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2411 le64_to_cpu(map_buff->volume_blk_cnt));
2412 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2413 map_buff->phys_blk_shift);
2414 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2415 map_buff->parity_rotation_shift);
2416 dev_info(&h->pdev->dev, "strip_size = %u\n",
2417 le16_to_cpu(map_buff->strip_size));
2418 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2419 le64_to_cpu(map_buff->disk_starting_blk));
2420 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2421 le64_to_cpu(map_buff->disk_blk_cnt));
2422 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2423 le16_to_cpu(map_buff->data_disks_per_row));
2424 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2425 le16_to_cpu(map_buff->metadata_disks_per_row));
2426 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2427 le16_to_cpu(map_buff->row_cnt));
2428 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2429 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2430 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2431 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2432 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2433 le16_to_cpu(map_buff->flags) &
2434 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2435 dev_info(&h->pdev->dev, "dekindex = %u\n",
2436 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2437 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2438 for (map = 0; map < map_cnt; map++) {
2439 dev_info(&h->pdev->dev, "Map%u:\n", map);
2440 row_cnt = le16_to_cpu(map_buff->row_cnt);
2441 for (row = 0; row < row_cnt; row++) {
2442 dev_info(&h->pdev->dev, " Row%u:\n", row);
2443 disks_per_row =
2444 le16_to_cpu(map_buff->data_disks_per_row);
2445 for (col = 0; col < disks_per_row; col++, dd++)
2446 dev_info(&h->pdev->dev,
2447 " D%02u: h=0x%04x xor=%u,%u\n",
2448 col, dd->ioaccel_handle,
2449 dd->xor_mult[0], dd->xor_mult[1]);
2450 disks_per_row =
2451 le16_to_cpu(map_buff->metadata_disks_per_row);
2452 for (col = 0; col < disks_per_row; col++, dd++)
2453 dev_info(&h->pdev->dev,
2454 " M%02u: h=0x%04x xor=%u,%u\n",
2455 col, dd->ioaccel_handle,
2456 dd->xor_mult[0], dd->xor_mult[1]);
2457 }
2458 }
2459}
2460#else
2461static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2462 __attribute__((unused)) int rc,
2463 __attribute__((unused)) struct raid_map_data *map_buff)
2464{
2465}
2466#endif
2467
2468static int hpsa_get_raid_map(struct ctlr_info *h,
2469 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2470{
2471 int rc = 0;
2472 struct CommandList *c;
2473 struct ErrorInfo *ei;
2474
45fcb86e 2475 c = cmd_alloc(h);
283b4a9b 2476 if (c == NULL) {
45fcb86e 2477 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
283b4a9b
SC		 2478 return -ENOMEM;
2479 }
2480 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2481 sizeof(this_device->raid_map), 0,
2482 scsi3addr, TYPE_CMD)) {
2483 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
25163bd5
WS		 2484 rc = -ENOMEM;
2485 goto out;
283b4a9b 2486 }
25163bd5
WS		 2487 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2488 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2489 if (rc)
2490 goto out;
283b4a9b
SC		 2491 ei = c->err_info;
2492 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2493 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 2494 rc = -1;
2495 goto out;
283b4a9b 2496 }
45fcb86e 2497 cmd_free(h, c);
283b4a9b
SC		 2498
2499 /* @todo in the future, dynamically allocate RAID map memory */
2500 if (le32_to_cpu(this_device->raid_map.structure_size) >
2501 sizeof(this_device->raid_map)) {
2502 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2503 rc = -1;
2504 }
2505 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2506 return rc;
25163bd5
WS		 2507out:
2508 cmd_free(h, c);
2509 return rc;
283b4a9b
SC		 2510}
2511
03383736
DB		 2512static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
2513 unsigned char scsi3addr[], u16 bmic_device_index,
2514 struct bmic_identify_physical_device *buf, size_t bufsize)
2515{
2516 int rc = IO_OK;
2517 struct CommandList *c;
2518 struct ErrorInfo *ei;
2519
2520 c = cmd_alloc(h);
2521 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
2522 0, RAID_CTLR_LUNID, TYPE_CMD);
2523 if (rc)
2524 goto out;
2525
2526 c->Request.CDB[2] = bmic_device_index & 0xff;
2527 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
2528
25163bd5
WS		 2529 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
2530 NO_TIMEOUT);
03383736
DB		 2531 ei = c->err_info;
2532 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2533 hpsa_scsi_interpret_error(h, c);
2534 rc = -1;
2535 }
2536out:
2537 cmd_free(h, c);
2538 return rc;
2539}
2540
1b70150a
SC		 2541static int hpsa_vpd_page_supported(struct ctlr_info *h,
2542 unsigned char scsi3addr[], u8 page)
2543{
2544 int rc;
2545 int i;
2546 int pages;
2547 unsigned char *buf, bufsize;
2548
2549 buf = kzalloc(256, GFP_KERNEL);
2550 if (!buf)
2551 return 0;
2552
2553 /* Get the size of the page list first */
2554 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2555 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2556 buf, HPSA_VPD_HEADER_SZ);
2557 if (rc != 0)
2558 goto exit_unsupported;
2559 pages = buf[3];
2560 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2561 bufsize = pages + HPSA_VPD_HEADER_SZ;
2562 else
2563 bufsize = 255;
2564
2565 /* Get the whole VPD page list */
2566 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2567 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2568 buf, bufsize);
2569 if (rc != 0)
2570 goto exit_unsupported;
2571
2572 pages = buf[3];
2573 for (i = 1; i <= pages; i++)
2574 if (buf[3 + i] == page)
2575 goto exit_supported;
2576exit_unsupported:
2577 kfree(buf);
2578 return 0;
2579exit_supported:
2580 kfree(buf);
2581 return 1;
2582}
2583
283b4a9b
SC		 2584static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2585 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2586{
2587 int rc;
2588 unsigned char *buf;
2589 u8 ioaccel_status;
2590
2591 this_device->offload_config = 0;
2592 this_device->offload_enabled = 0;
41ce4c35 2593 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 2594
2595 buf = kzalloc(64, GFP_KERNEL);
2596 if (!buf)
2597 return;
1b70150a
SC		 2598 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2599 goto out;
283b4a9b 2600 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2601 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2602 if (rc != 0)
2603 goto out;
2604
2605#define IOACCEL_STATUS_BYTE 4
2606#define OFFLOAD_CONFIGURED_BIT 0x01
2607#define OFFLOAD_ENABLED_BIT 0x02
2608 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2609 this_device->offload_config =
2610 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2611 if (this_device->offload_config) {
2612 this_device->offload_enabled =
2613 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2614 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2615 this_device->offload_enabled = 0;
2616 }
41ce4c35 2617 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 2618out:
2619 kfree(buf);
2620 return;
2621}
2622
edd16368
SC		 2623/* Get the device id from inquiry page 0x83 */
2624static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2625 unsigned char *device_id, int buflen)
2626{
2627 int rc;
2628 unsigned char *buf;
2629
2630 if (buflen > 16)
2631 buflen = 16;
2632 buf = kzalloc(64, GFP_KERNEL);
2633 if (!buf)
a84d794d 2634 return -ENOMEM;
b7bb24eb 2635 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2636 if (rc == 0)
2637 memcpy(device_id, &buf[8], buflen);
2638 kfree(buf);
2639 return rc != 0;
2640}
2641
2642static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 2643 void *buf, int bufsize,
edd16368
SC		 2644 int extended_response)
2645{
2646 int rc = IO_OK;
2647 struct CommandList *c;
2648 unsigned char scsi3addr[8];
2649 struct ErrorInfo *ei;
2650
45fcb86e 2651 c = cmd_alloc(h);
edd16368 2652 if (c == NULL) { /* trouble... */
45fcb86e 2653 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 2654 return -1;
2655 }
e89c0ae7
SC		 2656 /* address the controller */
2657 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2658 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2659 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2660 rc = -1;
2661 goto out;
2662 }
edd16368
SC		 2663 if (extended_response)
2664 c->Request.CDB[1] = extended_response;
25163bd5
WS		 2665 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2666 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2667 if (rc)
2668 goto out;
edd16368
SC		 2669 ei = c->err_info;
2670 if (ei->CommandStatus != 0 &&
2671 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2672 hpsa_scsi_interpret_error(h, c);
edd16368 2673 rc = -1;
283b4a9b 2674 } else {
03383736
DB		 2675 struct ReportLUNdata *rld = buf;
2676
2677 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 2678 dev_err(&h->pdev->dev,
2679 "report luns requested format %u, got %u\n",
2680 extended_response,
03383736 2681 rld->extended_response_flag);
283b4a9b
SC		 2682 rc = -1;
2683 }
edd16368 2684 }
a2dac136 2685out:
45fcb86e 2686 cmd_free(h, c);
edd16368
SC		 2687 return rc;
2688}
2689
2690static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 2691 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 2692{
03383736
DB		 2693 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
2694 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 2695}
2696
2697static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2698 struct ReportLUNdata *buf, int bufsize)
2699{
2700 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2701}
2702
2703static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2704 int bus, int target, int lun)
2705{
2706 device->bus = bus;
2707 device->target = target;
2708 device->lun = lun;
2709}
2710
9846590e
SC		 2711/* Use VPD inquiry to get details of volume status */
2712static int hpsa_get_volume_status(struct ctlr_info *h,
2713 unsigned char scsi3addr[])
2714{
2715 int rc;
2716 int status;
2717 int size;
2718 unsigned char *buf;
2719
2720 buf = kzalloc(64, GFP_KERNEL);
2721 if (!buf)
2722 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2723
2724 /* Does controller have VPD for logical volume status? */
24a4b078 2725 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 2726 goto exit_failed;
9846590e
SC		 2727
2728 /* Get the size of the VPD return buffer */
2729 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2730 buf, HPSA_VPD_HEADER_SZ);
24a4b078 2731 if (rc != 0)
9846590e 2732 goto exit_failed;
9846590e
SC		 2733 size = buf[3];
2734
2735 /* Now get the whole VPD buffer */
2736 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2737 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 2738 if (rc != 0)
9846590e 2739 goto exit_failed;
9846590e
SC		 2740 status = buf[4]; /* status byte */
2741
2742 kfree(buf);
2743 return status;
2744exit_failed:
2745 kfree(buf);
2746 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2747}
2748
2749/* Determine offline status of a volume.
2750 * Return either:
2751 * 0 (not offline)
67955ba3 2752 * 0xff (offline for unknown reasons)
9846590e
SC		 2753 * # (integer code indicating one of several NOT READY states
2754 * describing why a volume is to be kept offline)
2755 */
67955ba3 2756static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 2757 unsigned char scsi3addr[])
2758{
2759 struct CommandList *c;
2760 unsigned char *sense, sense_key, asc, ascq;
25163bd5 2761 int rc, ldstat = 0;
9846590e
SC		 2762 u16 cmd_status;
2763 u8 scsi_status;
2764#define ASC_LUN_NOT_READY 0x04
2765#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
2766#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
2767
2768 c = cmd_alloc(h);
2769 if (!c)
2770 return 0;
2771 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
25163bd5
WS		 2772 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
2773 if (rc) {
2774 cmd_free(h, c);
2775 return 0;
2776 }
9846590e
SC		 2777 sense = c->err_info->SenseInfo;
2778 sense_key = sense[2];
2779 asc = sense[12];
2780 ascq = sense[13];
2781 cmd_status = c->err_info->CommandStatus;
2782 scsi_status = c->err_info->ScsiStatus;
2783 cmd_free(h, c);
2784 /* Is the volume 'not ready'? */
2785 if (cmd_status != CMD_TARGET_STATUS ||
2786 scsi_status != SAM_STAT_CHECK_CONDITION ||
2787 sense_key != NOT_READY ||
2788 asc != ASC_LUN_NOT_READY) {
2789 return 0;
2790 }
2791
2792 /* Determine the reason for not ready state */
2793 ldstat = hpsa_get_volume_status(h, scsi3addr);
2794
2795 /* Keep volume offline in certain cases: */
2796 switch (ldstat) {
2797 case HPSA_LV_UNDERGOING_ERASE:
2798 case HPSA_LV_UNDERGOING_RPI:
2799 case HPSA_LV_PENDING_RPI:
2800 case HPSA_LV_ENCRYPTED_NO_KEY:
2801 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
2802 case HPSA_LV_UNDERGOING_ENCRYPTION:
2803 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
2804 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
2805 return ldstat;
2806 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
2807 /* If VPD status page isn't available,
2808 * use ASC/ASCQ to determine state
2809 */
2810 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
2811 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
2812 return ldstat;
2813 break;
2814 default:
2815 break;
2816 }
2817 return 0;
2818}
2819
9b5c48c2
SC		 2820/*
2821 * Find out if a logical device supports aborts by simply trying one.
2822 * Smart Array may claim not to support aborts on logical drives, but
2823 * if a MSA2000 * is connected, the drives on that will be presented
2824 * by the Smart Array as logical drives, and aborts may be sent to
2825 * those devices successfully. So the simplest way to find out is
2826 * to simply try an abort and see how the device responds.
2827 */
2828static int hpsa_device_supports_aborts(struct ctlr_info *h,
2829 unsigned char *scsi3addr)
2830{
2831 struct CommandList *c;
2832 struct ErrorInfo *ei;
2833 int rc = 0;
2834
2835 u64 tag = (u64) -1; /* bogus tag */
2836
2837 /* Assume that physical devices support aborts */
2838 if (!is_logical_dev_addr_mode(scsi3addr))
2839 return 1;
2840
2841 c = cmd_alloc(h);
2842 if (!c)
2843 return -ENOMEM;
2844 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
2845 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
2846 /* no unmap needed here because no data xfer. */
2847 ei = c->err_info;
2848 switch (ei->CommandStatus) {
2849 case CMD_INVALID:
2850 rc = 0;
2851 break;
2852 case CMD_UNABORTABLE:
2853 case CMD_ABORT_FAILED:
2854 rc = 1;
2855 break;
2856 default:
2857 rc = 0;
2858 break;
2859 }
2860 cmd_free(h, c);
2861 return rc;
2862}
2863
edd16368 2864static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2865 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2866 unsigned char *is_OBDR_device)
edd16368 2867{
0b0e1d6c
SC		 2868
2869#define OBDR_SIG_OFFSET 43
2870#define OBDR_TAPE_SIG "$DR-10"
2871#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2872#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2873
ea6d3bc3 2874 unsigned char *inq_buff;
0b0e1d6c 2875 unsigned char *obdr_sig;
edd16368 2876
ea6d3bc3 2877 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2878 if (!inq_buff)
2879 goto bail_out;
2880
edd16368
SC		 2881 /* Do an inquiry to the device to see what it is. */
2882 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2883 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2884 /* Inquiry failed (msg printed already) */
2885 dev_err(&h->pdev->dev,
2886 "hpsa_update_device_info: inquiry failed\n");
2887 goto bail_out;
2888 }
2889
edd16368
SC		 2890 this_device->devtype = (inq_buff[0] & 0x1f);
2891 memcpy(this_device->scsi3addr, scsi3addr, 8);
2892 memcpy(this_device->vendor, &inq_buff[8],
2893 sizeof(this_device->vendor));
2894 memcpy(this_device->model, &inq_buff[16],
2895 sizeof(this_device->model));
edd16368
SC		 2896 memset(this_device->device_id, 0,
2897 sizeof(this_device->device_id));
2898 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2899 sizeof(this_device->device_id));
2900
2901 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2902 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 2903 int volume_offline;
2904
edd16368 2905 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2906 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2907 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 2908 volume_offline = hpsa_volume_offline(h, scsi3addr);
2909 if (volume_offline < 0 || volume_offline > 0xff)
2910 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
2911 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 2912 } else {
edd16368 2913 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2914 this_device->offload_config = 0;
2915 this_device->offload_enabled = 0;
41ce4c35 2916 this_device->offload_to_be_enabled = 0;
9846590e 2917 this_device->volume_offline = 0;
03383736 2918 this_device->queue_depth = h->nr_cmds;
283b4a9b 2919 }
edd16368 2920
0b0e1d6c
SC		 2921 if (is_OBDR_device) {
2922 /* See if this is a One-Button-Disaster-Recovery device
2923 * by looking for "$DR-10" at offset 43 in inquiry data.
2924 */
2925 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2926 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2927 strncmp(obdr_sig, OBDR_TAPE_SIG,
2928 OBDR_SIG_LEN) == 0);
2929 }
edd16368
SC		 2930 kfree(inq_buff);
2931 return 0;
2932
2933bail_out:
2934 kfree(inq_buff);
2935 return 1;
2936}
2937
9b5c48c2
SC		 2938static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
2939 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
2940{
2941 unsigned long flags;
2942 int rc, entry;
2943 /*
2944 * See if this device supports aborts. If we already know
2945 * the device, we already know if it supports aborts, otherwise
2946 * we have to find out if it supports aborts by trying one.
2947 */
2948 spin_lock_irqsave(&h->devlock, flags);
2949 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
2950 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
2951 entry >= 0 && entry < h->ndevices) {
2952 dev->supports_aborts = h->dev[entry]->supports_aborts;
2953 spin_unlock_irqrestore(&h->devlock, flags);
2954 } else {
2955 spin_unlock_irqrestore(&h->devlock, flags);
2956 dev->supports_aborts =
2957 hpsa_device_supports_aborts(h, scsi3addr);
2958 if (dev->supports_aborts < 0)
2959 dev->supports_aborts = 0;
2960 }
2961}
2962
4f4eb9f1 2963static unsigned char *ext_target_model[] = {
edd16368
SC		 2964 "MSA2012",
2965 "MSA2024",
2966 "MSA2312",
2967 "MSA2324",
fda38518 2968 "P2000 G3 SAS",
e06c8e5c 2969 "MSA 2040 SAS",
edd16368
SC		 2970 NULL,
2971};
2972
4f4eb9f1 2973static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2974{
2975 int i;
2976
4f4eb9f1
ST		 2977 for (i = 0; ext_target_model[i]; i++)
2978 if (strncmp(device->model, ext_target_model[i],
2979 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2980 return 1;
2981 return 0;
2982}
2983
2984/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2985 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2986 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2987 * Logical drive target and lun are assigned at this time, but
2988 * physical device lun and target assignment are deferred (assigned
2989 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2990 */
2991static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2992 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2993{
1f310bde
SC		 2994 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2995
2996 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2997 /* physical device, target and lun filled in later */
edd16368 2998 if (is_hba_lunid(lunaddrbytes))
1f310bde 2999 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 3000 else
1f310bde
SC		 3001 /* defer target, lun assignment for physical devices */
3002 hpsa_set_bus_target_lun(device, 2, -1, -1);
3003 return;
3004 }
3005 /* It's a logical device */
4f4eb9f1
ST		 3006 if (is_ext_target(h, device)) {
3007 /* external target way, put logicals on bus 1
1f310bde
SC		 3008 * and match target/lun numbers box
3009 * reports, other smart array, bus 0, target 0, match lunid
3010 */
3011 hpsa_set_bus_target_lun(device,
3012 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
3013 return;
edd16368 3014 }
1f310bde 3015 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 3016}
3017
3018/*
3019 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 3020 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 3021 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
3022 * it for some reason. *tmpdevice is the target we're adding,
3023 * this_device is a pointer into the current element of currentsd[]
3024 * that we're building up in update_scsi_devices(), below.
3025 * lunzerobits is a bitmap that tracks which targets already have a
3026 * lun 0 assigned.
3027 * Returns 1 if an enclosure was added, 0 if not.
3028 */
4f4eb9f1 3029static int add_ext_target_dev(struct ctlr_info *h,
edd16368 3030 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 3031 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 3032 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 3033{
3034 unsigned char scsi3addr[8];
3035
1f310bde 3036 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 3037 return 0; /* There is already a lun 0 on this target. */
3038
3039 if (!is_logical_dev_addr_mode(lunaddrbytes))
3040 return 0; /* It's the logical targets that may lack lun 0. */
3041
4f4eb9f1
ST		 3042 if (!is_ext_target(h, tmpdevice))
3043 return 0; /* Only external target devices have this problem. */
edd16368 3044
1f310bde 3045 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 3046 return 0;
3047
c4f8a299 3048 memset(scsi3addr, 0, 8);
1f310bde 3049 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 3050 if (is_hba_lunid(scsi3addr))
3051 return 0; /* Don't add the RAID controller here. */
3052
339b2b14
SC		 3053 if (is_scsi_rev_5(h))
3054 return 0; /* p1210m doesn't need to do this. */
3055
4f4eb9f1 3056 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 3057 dev_warn(&h->pdev->dev, "Maximum number of external "
3058 "target devices exceeded. Check your hardware "
edd16368
SC		 3059 "configuration.");
3060 return 0;
3061 }
3062
0b0e1d6c 3063 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 3064 return 0;
4f4eb9f1 3065 (*n_ext_target_devs)++;
1f310bde
SC		 3066 hpsa_set_bus_target_lun(this_device,
3067 tmpdevice->bus, tmpdevice->target, 0);
9b5c48c2 3068 hpsa_update_device_supports_aborts(h, this_device, scsi3addr);
1f310bde 3069 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 3070 return 1;
3071}
3072
54b6e9e9
ST		 3073/*
3074 * Get address of physical disk used for an ioaccel2 mode command:
3075 * 1. Extract ioaccel2 handle from the command.
3076 * 2. Find a matching ioaccel2 handle from list of physical disks.
3077 * 3. Return:
3078 * 1 and set scsi3addr to address of matching physical
3079 * 0 if no matching physical disk was found.
3080 */
3081static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3082 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3083{
41ce4c35
SC		 3084 struct io_accel2_cmd *c2 =
3085 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3086 unsigned long flags;
54b6e9e9 3087 int i;
54b6e9e9 3088
41ce4c35
SC		 3089 spin_lock_irqsave(&h->devlock, flags);
3090 for (i = 0; i < h->ndevices; i++)
3091 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3092 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3093 sizeof(h->dev[i]->scsi3addr));
3094 spin_unlock_irqrestore(&h->devlock, flags);
3095 return 1;
3096 }
3097 spin_unlock_irqrestore(&h->devlock, flags);
3098 return 0;
54b6e9e9 3099}
41ce4c35 3100
edd16368
SC		 3101/*
3102 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3103 * logdev. The number of luns in physdev and logdev are returned in
3104 * *nphysicals and *nlogicals, respectively.
3105 * Returns 0 on success, -1 otherwise.
3106 */
3107static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3108 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3109 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3110{
03383736 3111 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3112 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3113 return -1;
3114 }
03383736 3115 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3116 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3117 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3118 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3119 *nphysicals = HPSA_MAX_PHYS_LUN;
3120 }
03383736 3121 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3122 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3123 return -1;
3124 }
6df1e954 3125 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3126 /* Reject Logicals in excess of our max capability. */
3127 if (*nlogicals > HPSA_MAX_LUN) {
3128 dev_warn(&h->pdev->dev,
3129 "maximum logical LUNs (%d) exceeded. "
3130 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3131 *nlogicals - HPSA_MAX_LUN);
3132 *nlogicals = HPSA_MAX_LUN;
3133 }
3134 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3135 dev_warn(&h->pdev->dev,
3136 "maximum logical + physical LUNs (%d) exceeded. "
3137 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3138 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3139 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3140 }
3141 return 0;
3142}
3143
42a91641
DB		 3144static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3145 int i, int nphysicals, int nlogicals,
a93aa1fe 3146 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3147 struct ReportLUNdata *logdev_list)
3148{
3149 /* Helper function, figure out where the LUN ID info is coming from
3150 * given index i, lists of physical and logical devices, where in
3151 * the list the raid controller is supposed to appear (first or last)
3152 */
3153
3154 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3155 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3156
3157 if (i == raid_ctlr_position)
3158 return RAID_CTLR_LUNID;
3159
3160 if (i < logicals_start)
d5b5d964
SC		 3161 return &physdev_list->LUN[i -
3162 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3163
3164 if (i < last_device)
3165 return &logdev_list->LUN[i - nphysicals -
3166 (raid_ctlr_position == 0)][0];
3167 BUG();
3168 return NULL;
3169}
3170
316b221a
SC		 3171static int hpsa_hba_mode_enabled(struct ctlr_info *h)
3172{
3173 int rc;
6e8e8088 3174 int hba_mode_enabled;
316b221a
SC		 3175 struct bmic_controller_parameters *ctlr_params;
3176 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
3177 GFP_KERNEL);
3178
3179 if (!ctlr_params)
96444fbb 3180 return -ENOMEM;
316b221a
SC		 3181 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
3182 sizeof(struct bmic_controller_parameters));
96444fbb 3183 if (rc) {
316b221a 3184 kfree(ctlr_params);
96444fbb 3185 return rc;
316b221a 3186 }
6e8e8088
JH		 3187
3188 hba_mode_enabled =
3189 ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0);
3190 kfree(ctlr_params);
3191 return hba_mode_enabled;
316b221a
SC		 3192}
3193
03383736
DB		 3194/* get physical drive ioaccel handle and queue depth */
3195static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3196 struct hpsa_scsi_dev_t *dev,
3197 u8 *lunaddrbytes,
3198 struct bmic_identify_physical_device *id_phys)
3199{
3200 int rc;
3201 struct ext_report_lun_entry *rle =
3202 (struct ext_report_lun_entry *) lunaddrbytes;
3203
3204 dev->ioaccel_handle = rle->ioaccel_handle;
3205 memset(id_phys, 0, sizeof(*id_phys));
3206 rc = hpsa_bmic_id_physical_device(h, lunaddrbytes,
3207 GET_BMIC_DRIVE_NUMBER(lunaddrbytes), id_phys,
3208 sizeof(*id_phys));
3209 if (!rc)
3210 /* Reserve space for FW operations */
3211#define DRIVE_CMDS_RESERVED_FOR_FW 2
3212#define DRIVE_QUEUE_DEPTH 7
3213 dev->queue_depth =
3214 le16_to_cpu(id_phys->current_queue_depth_limit) -
3215 DRIVE_CMDS_RESERVED_FOR_FW;
3216 else
3217 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
3218 atomic_set(&dev->ioaccel_cmds_out, 0);
3219}
3220
edd16368
SC		 3221static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
3222{
3223 /* the idea here is we could get notified
3224 * that some devices have changed, so we do a report
3225 * physical luns and report logical luns cmd, and adjust
3226 * our list of devices accordingly.
3227 *
3228 * The scsi3addr's of devices won't change so long as the
3229 * adapter is not reset. That means we can rescan and
3230 * tell which devices we already know about, vs. new
3231 * devices, vs. disappearing devices.
3232 */
a93aa1fe 3233 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3234 struct ReportLUNdata *logdev_list = NULL;
03383736 3235 struct bmic_identify_physical_device *id_phys = NULL;
01a02ffc
SC		 3236 u32 nphysicals = 0;
3237 u32 nlogicals = 0;
3238 u32 ndev_allocated = 0;
edd16368
SC		 3239 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3240 int ncurrent = 0;
4f4eb9f1 3241 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3242 int raid_ctlr_position;
2bbf5c7f 3243 int rescan_hba_mode;
aca4a520 3244 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3245
cfe5badc 3246 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 3247 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3248 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 3249 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 3250 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
edd16368 3251
03383736
DB		 3252 if (!currentsd || !physdev_list || !logdev_list ||
3253 !tmpdevice || !id_phys) {
edd16368
SC		 3254 dev_err(&h->pdev->dev, "out of memory\n");
3255 goto out;
3256 }
3257 memset(lunzerobits, 0, sizeof(lunzerobits));
3258
316b221a 3259 rescan_hba_mode = hpsa_hba_mode_enabled(h);
96444fbb
JH		 3260 if (rescan_hba_mode < 0)
3261 goto out;
316b221a
SC		 3262
3263 if (!h->hba_mode_enabled && rescan_hba_mode)
3264 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
3265 else if (h->hba_mode_enabled && !rescan_hba_mode)
3266 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
3267
3268 h->hba_mode_enabled = rescan_hba_mode;
3269
03383736
DB		 3270 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
3271 logdev_list, &nlogicals))
edd16368
SC		 3272 goto out;
3273
aca4a520
ST		 3274 /* We might see up to the maximum number of logical and physical disks
3275 * plus external target devices, and a device for the local RAID
3276 * controller.
edd16368 3277 */
aca4a520 3278 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3279
3280 /* Allocate the per device structures */
3281 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3282 if (i >= HPSA_MAX_DEVICES) {
3283 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3284 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3285 ndevs_to_allocate - HPSA_MAX_DEVICES);
3286 break;
3287 }
3288
edd16368
SC		 3289 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3290 if (!currentsd[i]) {
3291 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3292 __FILE__, __LINE__);
3293 goto out;
3294 }
3295 ndev_allocated++;
3296 }
3297
8645291b 3298 if (is_scsi_rev_5(h))
339b2b14
SC		 3299 raid_ctlr_position = 0;
3300 else
3301 raid_ctlr_position = nphysicals + nlogicals;
3302
edd16368 3303 /* adjust our table of devices */
4f4eb9f1 3304 n_ext_target_devs = 0;
edd16368 3305 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3306 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3307
3308 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3309 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3310 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 3311
3312 /* skip masked non-disk devices */
3313 if (MASKED_DEVICE(lunaddrbytes))
3314 if (i < nphysicals + (raid_ctlr_position == 0) &&
3315 NON_DISK_PHYS_DEV(lunaddrbytes))
3316 continue;
edd16368
SC		 3317
3318 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3319 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3320 &is_OBDR))
edd16368 3321 continue; /* skip it if we can't talk to it. */
1f310bde 3322 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 3323 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 3324 this_device = currentsd[ncurrent];
3325
3326 /*
4f4eb9f1 3327 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3328 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3329 * is nonetheless an enclosure device there. We have to
3330 * present that otherwise linux won't find anything if
3331 * there is no lun 0.
3332 */
4f4eb9f1 3333 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3334 lunaddrbytes, lunzerobits,
4f4eb9f1 3335 &n_ext_target_devs)) {
edd16368
SC		 3336 ncurrent++;
3337 this_device = currentsd[ncurrent];
3338 }
3339
3340 *this_device = *tmpdevice;
edd16368 3341
41ce4c35
SC		 3342 /* do not expose masked devices */
3343 if (MASKED_DEVICE(lunaddrbytes) &&
3344 i < nphysicals + (raid_ctlr_position == 0)) {
3345 if (h->hba_mode_enabled)
3346 dev_warn(&h->pdev->dev,
3347 "Masked physical device detected\n");
3348 this_device->expose_state = HPSA_DO_NOT_EXPOSE;
3349 } else {
3350 this_device->expose_state =
3351 HPSA_SG_ATTACH | HPSA_ULD_ATTACH;
3352 }
3353
edd16368 3354 switch (this_device->devtype) {
0b0e1d6c 3355 case TYPE_ROM:
edd16368
SC		 3356 /* We don't *really* support actual CD-ROM devices,
3357 * just "One Button Disaster Recovery" tape drive
3358 * which temporarily pretends to be a CD-ROM drive.
3359 * So we check that the device is really an OBDR tape
3360 * device by checking for "$DR-10" in bytes 43-48 of
3361 * the inquiry data.
3362 */
0b0e1d6c
SC		 3363 if (is_OBDR)
3364 ncurrent++;
edd16368
SC		 3365 break;
3366 case TYPE_DISK:
316b221a
SC		 3367 if (h->hba_mode_enabled) {
3368 /* never use raid mapper in HBA mode */
3369 this_device->offload_enabled = 0;
3370 ncurrent++;
3371 break;
3372 } else if (h->acciopath_status) {
3373 if (i >= nphysicals) {
3374 ncurrent++;
3375 break;
3376 }
3377 } else {
3378 if (i < nphysicals)
3379 break;
283b4a9b 3380 ncurrent++;
edd16368 3381 break;
283b4a9b 3382 }
03383736
DB		 3383 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
3384 h->transMethod & CFGTBL_Trans_io_accel2) {
3385 hpsa_get_ioaccel_drive_info(h, this_device,
3386 lunaddrbytes, id_phys);
3387 atomic_set(&this_device->ioaccel_cmds_out, 0);
283b4a9b
SC		 3388 ncurrent++;
3389 }
edd16368
SC		 3390 break;
3391 case TYPE_TAPE:
3392 case TYPE_MEDIUM_CHANGER:
3393 ncurrent++;
3394 break;
41ce4c35
SC		 3395 case TYPE_ENCLOSURE:
3396 if (h->hba_mode_enabled)
3397 ncurrent++;
3398 break;
edd16368
SC		 3399 case TYPE_RAID:
3400 /* Only present the Smartarray HBA as a RAID controller.
3401 * If it's a RAID controller other than the HBA itself
3402 * (an external RAID controller, MSA500 or similar)
3403 * don't present it.
3404 */
3405 if (!is_hba_lunid(lunaddrbytes))
3406 break;
3407 ncurrent++;
3408 break;
3409 default:
3410 break;
3411 }
cfe5badc 3412 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3413 break;
3414 }
3415 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3416out:
3417 kfree(tmpdevice);
3418 for (i = 0; i < ndev_allocated; i++)
3419 kfree(currentsd[i]);
3420 kfree(currentsd);
edd16368
SC		 3421 kfree(physdev_list);
3422 kfree(logdev_list);
03383736 3423 kfree(id_phys);
edd16368
SC		 3424}
3425
ec5cbf04
WS		 3426static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3427 struct scatterlist *sg)
3428{
3429 u64 addr64 = (u64) sg_dma_address(sg);
3430 unsigned int len = sg_dma_len(sg);
3431
3432 desc->Addr = cpu_to_le64(addr64);
3433 desc->Len = cpu_to_le32(len);
3434 desc->Ext = 0;
3435}
3436
c7ee65b3
WS		 3437/*
3438 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3439 * dma mapping and fills in the scatter gather entries of the
3440 * hpsa command, cp.
3441 */
33a2ffce 3442static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3443 struct CommandList *cp,
3444 struct scsi_cmnd *cmd)
3445{
edd16368 3446 struct scatterlist *sg;
33a2ffce
SC		 3447 int use_sg, i, sg_index, chained;
3448 struct SGDescriptor *curr_sg;
edd16368 3449
33a2ffce 3450 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3451
3452 use_sg = scsi_dma_map(cmd);
3453 if (use_sg < 0)
3454 return use_sg;
3455
3456 if (!use_sg)
3457 goto sglist_finished;
3458
33a2ffce
SC		 3459 curr_sg = cp->SG;
3460 chained = 0;
3461 sg_index = 0;
edd16368 3462 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 3463 if (i == h->max_cmd_sg_entries - 1 &&
3464 use_sg > h->max_cmd_sg_entries) {
3465 chained = 1;
3466 curr_sg = h->cmd_sg_list[cp->cmdindex];
3467 sg_index = 0;
3468 }
ec5cbf04 3469 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 3470 curr_sg++;
3471 }
ec5cbf04
WS		 3472
3473 /* Back the pointer up to the last entry and mark it as "last". */
50a0decf 3474 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3475
3476 if (use_sg + chained > h->maxSG)
3477 h->maxSG = use_sg + chained;
3478
3479 if (chained) {
3480 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3481 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3482 if (hpsa_map_sg_chain_block(h, cp)) {
3483 scsi_dma_unmap(cmd);
3484 return -1;
3485 }
33a2ffce 3486 return 0;
edd16368
SC		 3487 }
3488
3489sglist_finished:
3490
01a02ffc 3491 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 3492 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 3493 return 0;
3494}
3495
283b4a9b
SC		 3496#define IO_ACCEL_INELIGIBLE (1)
3497static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3498{
3499 int is_write = 0;
3500 u32 block;
3501 u32 block_cnt;
3502
3503 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3504 switch (cdb[0]) {
3505 case WRITE_6:
3506 case WRITE_12:
3507 is_write = 1;
3508 case READ_6:
3509 case READ_12:
3510 if (*cdb_len == 6) {
3511 block = (((u32) cdb[2]) << 8) | cdb[3];
3512 block_cnt = cdb[4];
3513 } else {
3514 BUG_ON(*cdb_len != 12);
3515 block = (((u32) cdb[2]) << 24) |
3516 (((u32) cdb[3]) << 16) |
3517 (((u32) cdb[4]) << 8) |
3518 cdb[5];
3519 block_cnt =
3520 (((u32) cdb[6]) << 24) |
3521 (((u32) cdb[7]) << 16) |
3522 (((u32) cdb[8]) << 8) |
3523 cdb[9];
3524 }
3525 if (block_cnt > 0xffff)
3526 return IO_ACCEL_INELIGIBLE;
3527
3528 cdb[0] = is_write ? WRITE_10 : READ_10;
3529 cdb[1] = 0;
3530 cdb[2] = (u8) (block >> 24);
3531 cdb[3] = (u8) (block >> 16);
3532 cdb[4] = (u8) (block >> 8);
3533 cdb[5] = (u8) (block);
3534 cdb[6] = 0;
3535 cdb[7] = (u8) (block_cnt >> 8);
3536 cdb[8] = (u8) (block_cnt);
3537 cdb[9] = 0;
3538 *cdb_len = 10;
3539 break;
3540 }
3541 return 0;
3542}
3543
c349775e 3544static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 3545 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3546 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 3547{
3548 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3549 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3550 unsigned int len;
3551 unsigned int total_len = 0;
3552 struct scatterlist *sg;
3553 u64 addr64;
3554 int use_sg, i;
3555 struct SGDescriptor *curr_sg;
3556 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3557
283b4a9b 3558 /* TODO: implement chaining support */
03383736
DB		 3559 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
3560 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3561 return IO_ACCEL_INELIGIBLE;
03383736 3562 }
283b4a9b 3563
e1f7de0c
MG		 3564 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3565
03383736
DB		 3566 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
3567 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3568 return IO_ACCEL_INELIGIBLE;
03383736 3569 }
283b4a9b 3570
e1f7de0c
MG		 3571 c->cmd_type = CMD_IOACCEL1;
3572
3573 /* Adjust the DMA address to point to the accelerated command buffer */
3574 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3575 (c->cmdindex * sizeof(*cp));
3576 BUG_ON(c->busaddr & 0x0000007F);
3577
3578 use_sg = scsi_dma_map(cmd);
03383736
DB		 3579 if (use_sg < 0) {
3580 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 3581 return use_sg;
03383736 3582 }
e1f7de0c
MG		 3583
3584 if (use_sg) {
3585 curr_sg = cp->SG;
3586 scsi_for_each_sg(cmd, sg, use_sg, i) {
3587 addr64 = (u64) sg_dma_address(sg);
3588 len = sg_dma_len(sg);
3589 total_len += len;
50a0decf
SC		 3590 curr_sg->Addr = cpu_to_le64(addr64);
3591 curr_sg->Len = cpu_to_le32(len);
3592 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 3593 curr_sg++;
3594 }
50a0decf 3595 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 3596
3597 switch (cmd->sc_data_direction) {
3598 case DMA_TO_DEVICE:
3599 control |= IOACCEL1_CONTROL_DATA_OUT;
3600 break;
3601 case DMA_FROM_DEVICE:
3602 control |= IOACCEL1_CONTROL_DATA_IN;
3603 break;
3604 case DMA_NONE:
3605 control |= IOACCEL1_CONTROL_NODATAXFER;
3606 break;
3607 default:
3608 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3609 cmd->sc_data_direction);
3610 BUG();
3611 break;
3612 }
3613 } else {
3614 control |= IOACCEL1_CONTROL_NODATAXFER;
3615 }
3616
c349775e 3617 c->Header.SGList = use_sg;
e1f7de0c 3618 /* Fill out the command structure to submit */
2b08b3e9
DB		 3619 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
3620 cp->transfer_len = cpu_to_le32(total_len);
3621 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
3622 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
3623 cp->control = cpu_to_le32(control);
283b4a9b
SC		 3624 memcpy(cp->CDB, cdb, cdb_len);
3625 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3626 /* Tag was already set at init time. */
283b4a9b 3627 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3628 return 0;
3629}
edd16368 3630
283b4a9b
SC		 3631/*
3632 * Queue a command directly to a device behind the controller using the
3633 * I/O accelerator path.
3634 */
3635static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3636 struct CommandList *c)
3637{
3638 struct scsi_cmnd *cmd = c->scsi_cmd;
3639 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3640
03383736
DB		 3641 c->phys_disk = dev;
3642
283b4a9b 3643 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 3644 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 3645}
3646
dd0e19f3
ST		 3647/*
3648 * Set encryption parameters for the ioaccel2 request
3649 */
3650static void set_encrypt_ioaccel2(struct ctlr_info *h,
3651 struct CommandList *c, struct io_accel2_cmd *cp)
3652{
3653 struct scsi_cmnd *cmd = c->scsi_cmd;
3654 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3655 struct raid_map_data *map = &dev->raid_map;
3656 u64 first_block;
3657
dd0e19f3 3658 /* Are we doing encryption on this device */
2b08b3e9 3659 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 3660 return;
3661 /* Set the data encryption key index. */
3662 cp->dekindex = map->dekindex;
3663
3664 /* Set the encryption enable flag, encoded into direction field. */
3665 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3666
3667 /* Set encryption tweak values based on logical block address
3668 * If block size is 512, tweak value is LBA.
3669 * For other block sizes, tweak is (LBA * block size)/ 512)
3670 */
3671 switch (cmd->cmnd[0]) {
3672 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3673 case WRITE_6:
3674 case READ_6:
2b08b3e9 3675 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 3676 break;
3677 case WRITE_10:
3678 case READ_10:
dd0e19f3
ST		 3679 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3680 case WRITE_12:
3681 case READ_12:
2b08b3e9 3682 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 3683 break;
3684 case WRITE_16:
3685 case READ_16:
2b08b3e9 3686 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 3687 break;
3688 default:
3689 dev_err(&h->pdev->dev,
2b08b3e9
DB		 3690 "ERROR: %s: size (0x%x) not supported for encryption\n",
3691 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 3692 BUG();
3693 break;
3694 }
2b08b3e9
DB		 3695
3696 if (le32_to_cpu(map->volume_blk_size) != 512)
3697 first_block = first_block *
3698 le32_to_cpu(map->volume_blk_size)/512;
3699
3700 cp->tweak_lower = cpu_to_le32(first_block);
3701 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 3702}
3703
c349775e
ST		 3704static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3705 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3706 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 3707{
3708 struct scsi_cmnd *cmd = c->scsi_cmd;
3709 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3710 struct ioaccel2_sg_element *curr_sg;
3711 int use_sg, i;
3712 struct scatterlist *sg;
3713 u64 addr64;
3714 u32 len;
3715 u32 total_len = 0;
3716
03383736
DB		 3717 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
3718 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3719 return IO_ACCEL_INELIGIBLE;
03383736 3720 }
c349775e 3721
03383736
DB		 3722 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
3723 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3724 return IO_ACCEL_INELIGIBLE;
03383736
DB		 3725 }
3726
c349775e
ST		 3727 c->cmd_type = CMD_IOACCEL2;
3728 /* Adjust the DMA address to point to the accelerated command buffer */
3729 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3730 (c->cmdindex * sizeof(*cp));
3731 BUG_ON(c->busaddr & 0x0000007F);
3732
3733 memset(cp, 0, sizeof(*cp));
3734 cp->IU_type = IOACCEL2_IU_TYPE;
3735
3736 use_sg = scsi_dma_map(cmd);
03383736
DB		 3737 if (use_sg < 0) {
3738 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3739 return use_sg;
03383736 3740 }
c349775e
ST		 3741
3742 if (use_sg) {
3743 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
3744 curr_sg = cp->sg;
3745 scsi_for_each_sg(cmd, sg, use_sg, i) {
3746 addr64 = (u64) sg_dma_address(sg);
3747 len = sg_dma_len(sg);
3748 total_len += len;
3749 curr_sg->address = cpu_to_le64(addr64);
3750 curr_sg->length = cpu_to_le32(len);
3751 curr_sg->reserved[0] = 0;
3752 curr_sg->reserved[1] = 0;
3753 curr_sg->reserved[2] = 0;
3754 curr_sg->chain_indicator = 0;
3755 curr_sg++;
3756 }
3757
3758 switch (cmd->sc_data_direction) {
3759 case DMA_TO_DEVICE:
dd0e19f3
ST		 3760 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3761 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3762 break;
3763 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3764 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3765 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3766 break;
3767 case DMA_NONE:
dd0e19f3
ST		 3768 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3769 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3770 break;
3771 default:
3772 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3773 cmd->sc_data_direction);
3774 BUG();
3775 break;
3776 }
3777 } else {
dd0e19f3
ST		 3778 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3779 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3780 }
dd0e19f3
ST		 3781
3782 /* Set encryption parameters, if necessary */
3783 set_encrypt_ioaccel2(h, c, cp);
3784
2b08b3e9 3785 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 3786 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 3787 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e
ST		 3788
3789 /* fill in sg elements */
3790 cp->sg_count = (u8) use_sg;
3791
3792 cp->data_len = cpu_to_le32(total_len);
3793 cp->err_ptr = cpu_to_le64(c->busaddr +
3794 offsetof(struct io_accel2_cmd, error_data));
50a0decf 3795 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e
ST		 3796
3797 enqueue_cmd_and_start_io(h, c);
3798 return 0;
3799}
3800
3801/*
3802 * Queue a command to the correct I/O accelerator path.
3803 */
3804static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3805 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3806 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 3807{
03383736
DB		 3808 /* Try to honor the device's queue depth */
3809 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
3810 phys_disk->queue_depth) {
3811 atomic_dec(&phys_disk->ioaccel_cmds_out);
3812 return IO_ACCEL_INELIGIBLE;
3813 }
c349775e
ST		 3814 if (h->transMethod & CFGTBL_Trans_io_accel1)
3815 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 3816 cdb, cdb_len, scsi3addr,
3817 phys_disk);
c349775e
ST		 3818 else
3819 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 3820 cdb, cdb_len, scsi3addr,
3821 phys_disk);
c349775e
ST		 3822}
3823
6b80b18f
ST		 3824static void raid_map_helper(struct raid_map_data *map,
3825 int offload_to_mirror, u32 *map_index, u32 *current_group)
3826{
3827 if (offload_to_mirror == 0) {
3828 /* use physical disk in the first mirrored group. */
2b08b3e9 3829 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3830 return;
3831 }
3832 do {
3833 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 3834 *current_group = *map_index /
3835 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3836 if (offload_to_mirror == *current_group)
3837 continue;
2b08b3e9 3838 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 3839 /* select map index from next group */
2b08b3e9 3840 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3841 (*current_group)++;
3842 } else {
3843 /* select map index from first group */
2b08b3e9 3844 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3845 *current_group = 0;
3846 }
3847 } while (offload_to_mirror != *current_group);
3848}
3849
283b4a9b
SC		 3850/*
3851 * Attempt to perform offload RAID mapping for a logical volume I/O.
3852 */
3853static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3854 struct CommandList *c)
3855{
3856 struct scsi_cmnd *cmd = c->scsi_cmd;
3857 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3858 struct raid_map_data *map = &dev->raid_map;
3859 struct raid_map_disk_data *dd = &map->data[0];
3860 int is_write = 0;
3861 u32 map_index;
3862 u64 first_block, last_block;
3863 u32 block_cnt;
3864 u32 blocks_per_row;
3865 u64 first_row, last_row;
3866 u32 first_row_offset, last_row_offset;
3867 u32 first_column, last_column;
6b80b18f
ST		 3868 u64 r0_first_row, r0_last_row;
3869 u32 r5or6_blocks_per_row;
3870 u64 r5or6_first_row, r5or6_last_row;
3871 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3872 u32 r5or6_first_column, r5or6_last_column;
3873 u32 total_disks_per_row;
3874 u32 stripesize;
3875 u32 first_group, last_group, current_group;
283b4a9b
SC		 3876 u32 map_row;
3877 u32 disk_handle;
3878 u64 disk_block;
3879 u32 disk_block_cnt;
3880 u8 cdb[16];
3881 u8 cdb_len;
2b08b3e9 3882 u16 strip_size;
283b4a9b
SC		 3883#if BITS_PER_LONG == 32
3884 u64 tmpdiv;
3885#endif
6b80b18f 3886 int offload_to_mirror;
283b4a9b 3887
283b4a9b
SC		 3888 /* check for valid opcode, get LBA and block count */
3889 switch (cmd->cmnd[0]) {
3890 case WRITE_6:
3891 is_write = 1;
3892 case READ_6:
3893 first_block =
3894 (((u64) cmd->cmnd[2]) << 8) |
3895 cmd->cmnd[3];
3896 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 3897 if (block_cnt == 0)
3898 block_cnt = 256;
283b4a9b
SC		 3899 break;
3900 case WRITE_10:
3901 is_write = 1;
3902 case READ_10:
3903 first_block =
3904 (((u64) cmd->cmnd[2]) << 24) |
3905 (((u64) cmd->cmnd[3]) << 16) |
3906 (((u64) cmd->cmnd[4]) << 8) |
3907 cmd->cmnd[5];
3908 block_cnt =
3909 (((u32) cmd->cmnd[7]) << 8) |
3910 cmd->cmnd[8];
3911 break;
3912 case WRITE_12:
3913 is_write = 1;
3914 case READ_12:
3915 first_block =
3916 (((u64) cmd->cmnd[2]) << 24) |
3917 (((u64) cmd->cmnd[3]) << 16) |
3918 (((u64) cmd->cmnd[4]) << 8) |
3919 cmd->cmnd[5];
3920 block_cnt =
3921 (((u32) cmd->cmnd[6]) << 24) |
3922 (((u32) cmd->cmnd[7]) << 16) |
3923 (((u32) cmd->cmnd[8]) << 8) |
3924 cmd->cmnd[9];
3925 break;
3926 case WRITE_16:
3927 is_write = 1;
3928 case READ_16:
3929 first_block =
3930 (((u64) cmd->cmnd[2]) << 56) |
3931 (((u64) cmd->cmnd[3]) << 48) |
3932 (((u64) cmd->cmnd[4]) << 40) |
3933 (((u64) cmd->cmnd[5]) << 32) |
3934 (((u64) cmd->cmnd[6]) << 24) |
3935 (((u64) cmd->cmnd[7]) << 16) |
3936 (((u64) cmd->cmnd[8]) << 8) |
3937 cmd->cmnd[9];
3938 block_cnt =
3939 (((u32) cmd->cmnd[10]) << 24) |
3940 (((u32) cmd->cmnd[11]) << 16) |
3941 (((u32) cmd->cmnd[12]) << 8) |
3942 cmd->cmnd[13];
3943 break;
3944 default:
3945 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3946 }
283b4a9b
SC		 3947 last_block = first_block + block_cnt - 1;
3948
3949 /* check for write to non-RAID-0 */
3950 if (is_write && dev->raid_level != 0)
3951 return IO_ACCEL_INELIGIBLE;
3952
3953 /* check for invalid block or wraparound */
2b08b3e9
DB		 3954 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
3955 last_block < first_block)
283b4a9b
SC		 3956 return IO_ACCEL_INELIGIBLE;
3957
3958 /* calculate stripe information for the request */
2b08b3e9
DB		 3959 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
3960 le16_to_cpu(map->strip_size);
3961 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 3962#if BITS_PER_LONG == 32
3963 tmpdiv = first_block;
3964 (void) do_div(tmpdiv, blocks_per_row);
3965 first_row = tmpdiv;
3966 tmpdiv = last_block;
3967 (void) do_div(tmpdiv, blocks_per_row);
3968 last_row = tmpdiv;
3969 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3970 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3971 tmpdiv = first_row_offset;
2b08b3e9 3972 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 3973 first_column = tmpdiv;
3974 tmpdiv = last_row_offset;
2b08b3e9 3975 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 3976 last_column = tmpdiv;
3977#else
3978 first_row = first_block / blocks_per_row;
3979 last_row = last_block / blocks_per_row;
3980 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3981 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 3982 first_column = first_row_offset / strip_size;
3983 last_column = last_row_offset / strip_size;
283b4a9b
SC		 3984#endif
3985
3986 /* if this isn't a single row/column then give to the controller */
3987 if ((first_row != last_row) || (first_column != last_column))
3988 return IO_ACCEL_INELIGIBLE;
3989
3990 /* proceeding with driver mapping */
2b08b3e9
DB		 3991 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
3992 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 3993 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 3994 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 3995 map_index = (map_row * total_disks_per_row) + first_column;
3996
3997 switch (dev->raid_level) {
3998 case HPSA_RAID_0:
3999 break; /* nothing special to do */
4000 case HPSA_RAID_1:
4001 /* Handles load balance across RAID 1 members.
4002 * (2-drive R1 and R10 with even # of drives.)
4003 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4004 */
2b08b3e9 4005 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4006 if (dev->offload_to_mirror)
2b08b3e9 4007 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4008 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4009 break;
4010 case HPSA_RAID_ADM:
4011 /* Handles N-way mirrors (R1-ADM)
4012 * and R10 with # of drives divisible by 3.)
4013 */
2b08b3e9 4014 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4015
4016 offload_to_mirror = dev->offload_to_mirror;
4017 raid_map_helper(map, offload_to_mirror,
4018 &map_index, &current_group);
4019 /* set mirror group to use next time */
4020 offload_to_mirror =
2b08b3e9
DB		 4021 (offload_to_mirror >=
4022 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4023 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4024 dev->offload_to_mirror = offload_to_mirror;
4025 /* Avoid direct use of dev->offload_to_mirror within this
4026 * function since multiple threads might simultaneously
4027 * increment it beyond the range of dev->layout_map_count -1.
4028 */
4029 break;
4030 case HPSA_RAID_5:
4031 case HPSA_RAID_6:
2b08b3e9 4032 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4033 break;
4034
4035 /* Verify first and last block are in same RAID group */
4036 r5or6_blocks_per_row =
2b08b3e9
DB		 4037 le16_to_cpu(map->strip_size) *
4038 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4039 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4040 stripesize = r5or6_blocks_per_row *
4041 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4042#if BITS_PER_LONG == 32
4043 tmpdiv = first_block;
4044 first_group = do_div(tmpdiv, stripesize);
4045 tmpdiv = first_group;
4046 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4047 first_group = tmpdiv;
4048 tmpdiv = last_block;
4049 last_group = do_div(tmpdiv, stripesize);
4050 tmpdiv = last_group;
4051 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4052 last_group = tmpdiv;
4053#else
4054 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4055 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4056#endif
000ff7c2 4057 if (first_group != last_group)
6b80b18f
ST		 4058 return IO_ACCEL_INELIGIBLE;
4059
4060 /* Verify request is in a single row of RAID 5/6 */
4061#if BITS_PER_LONG == 32
4062 tmpdiv = first_block;
4063 (void) do_div(tmpdiv, stripesize);
4064 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4065 tmpdiv = last_block;
4066 (void) do_div(tmpdiv, stripesize);
4067 r5or6_last_row = r0_last_row = tmpdiv;
4068#else
4069 first_row = r5or6_first_row = r0_first_row =
4070 first_block / stripesize;
4071 r5or6_last_row = r0_last_row = last_block / stripesize;
4072#endif
4073 if (r5or6_first_row != r5or6_last_row)
4074 return IO_ACCEL_INELIGIBLE;
4075
4076
4077 /* Verify request is in a single column */
4078#if BITS_PER_LONG == 32
4079 tmpdiv = first_block;
4080 first_row_offset = do_div(tmpdiv, stripesize);
4081 tmpdiv = first_row_offset;
4082 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4083 r5or6_first_row_offset = first_row_offset;
4084 tmpdiv = last_block;
4085 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4086 tmpdiv = r5or6_last_row_offset;
4087 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4088 tmpdiv = r5or6_first_row_offset;
4089 (void) do_div(tmpdiv, map->strip_size);
4090 first_column = r5or6_first_column = tmpdiv;
4091 tmpdiv = r5or6_last_row_offset;
4092 (void) do_div(tmpdiv, map->strip_size);
4093 r5or6_last_column = tmpdiv;
4094#else
4095 first_row_offset = r5or6_first_row_offset =
4096 (u32)((first_block % stripesize) %
4097 r5or6_blocks_per_row);
4098
4099 r5or6_last_row_offset =
4100 (u32)((last_block % stripesize) %
4101 r5or6_blocks_per_row);
4102
4103 first_column = r5or6_first_column =
2b08b3e9 4104 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4105 r5or6_last_column =
2b08b3e9 4106 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4107#endif
4108 if (r5or6_first_column != r5or6_last_column)
4109 return IO_ACCEL_INELIGIBLE;
4110
4111 /* Request is eligible */
4112 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4113 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4114
4115 map_index = (first_group *
2b08b3e9 4116 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4117 (map_row * total_disks_per_row) + first_column;
4118 break;
4119 default:
4120 return IO_ACCEL_INELIGIBLE;
283b4a9b 4121 }
6b80b18f 4122
07543e0c
SC		 4123 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4124 return IO_ACCEL_INELIGIBLE;
4125
03383736
DB		 4126 c->phys_disk = dev->phys_disk[map_index];
4127
283b4a9b 4128 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 4129 disk_block = le64_to_cpu(map->disk_starting_blk) +
4130 first_row * le16_to_cpu(map->strip_size) +
4131 (first_row_offset - first_column *
4132 le16_to_cpu(map->strip_size));
283b4a9b
SC		 4133 disk_block_cnt = block_cnt;
4134
4135 /* handle differing logical/physical block sizes */
4136 if (map->phys_blk_shift) {
4137 disk_block <<= map->phys_blk_shift;
4138 disk_block_cnt <<= map->phys_blk_shift;
4139 }
4140 BUG_ON(disk_block_cnt > 0xffff);
4141
4142 /* build the new CDB for the physical disk I/O */
4143 if (disk_block > 0xffffffff) {
4144 cdb[0] = is_write ? WRITE_16 : READ_16;
4145 cdb[1] = 0;
4146 cdb[2] = (u8) (disk_block >> 56);
4147 cdb[3] = (u8) (disk_block >> 48);
4148 cdb[4] = (u8) (disk_block >> 40);
4149 cdb[5] = (u8) (disk_block >> 32);
4150 cdb[6] = (u8) (disk_block >> 24);
4151 cdb[7] = (u8) (disk_block >> 16);
4152 cdb[8] = (u8) (disk_block >> 8);
4153 cdb[9] = (u8) (disk_block);
4154 cdb[10] = (u8) (disk_block_cnt >> 24);
4155 cdb[11] = (u8) (disk_block_cnt >> 16);
4156 cdb[12] = (u8) (disk_block_cnt >> 8);
4157 cdb[13] = (u8) (disk_block_cnt);
4158 cdb[14] = 0;
4159 cdb[15] = 0;
4160 cdb_len = 16;
4161 } else {
4162 cdb[0] = is_write ? WRITE_10 : READ_10;
4163 cdb[1] = 0;
4164 cdb[2] = (u8) (disk_block >> 24);
4165 cdb[3] = (u8) (disk_block >> 16);
4166 cdb[4] = (u8) (disk_block >> 8);
4167 cdb[5] = (u8) (disk_block);
4168 cdb[6] = 0;
4169 cdb[7] = (u8) (disk_block_cnt >> 8);
4170 cdb[8] = (u8) (disk_block_cnt);
4171 cdb[9] = 0;
4172 cdb_len = 10;
4173 }
4174 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 4175 dev->scsi3addr,
4176 dev->phys_disk[map_index]);
283b4a9b
SC		 4177}
4178
25163bd5
WS		 4179/*
4180 * Submit commands down the "normal" RAID stack path
4181 * All callers to hpsa_ciss_submit must check lockup_detected
4182 * beforehand, before (opt.) and after calling cmd_alloc
4183 */
574f05d3
SC		 4184static int hpsa_ciss_submit(struct ctlr_info *h,
4185 struct CommandList *c, struct scsi_cmnd *cmd,
4186 unsigned char scsi3addr[])
edd16368 4187{
edd16368 4188 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 4189 c->cmd_type = CMD_SCSI;
4190 c->scsi_cmd = cmd;
4191 c->Header.ReplyQueue = 0; /* unused in simple mode */
4192 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 4193 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 4194
4195 /* Fill in the request block... */
4196
4197 c->Request.Timeout = 0;
4198 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4199 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4200 c->Request.CDBLen = cmd->cmd_len;
4201 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 4202 switch (cmd->sc_data_direction) {
4203 case DMA_TO_DEVICE:
a505b86f
SC		 4204 c->Request.type_attr_dir =
4205 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 4206 break;
4207 case DMA_FROM_DEVICE:
a505b86f
SC		 4208 c->Request.type_attr_dir =
4209 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 4210 break;
4211 case DMA_NONE:
a505b86f
SC		 4212 c->Request.type_attr_dir =
4213 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 4214 break;
4215 case DMA_BIDIRECTIONAL:
4216 /* This can happen if a buggy application does a scsi passthru
4217 * and sets both inlen and outlen to non-zero. ( see
4218 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4219 */
4220
a505b86f
SC		 4221 c->Request.type_attr_dir =
4222 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 4223 /* This is technically wrong, and hpsa controllers should
4224 * reject it with CMD_INVALID, which is the most correct
4225 * response, but non-fibre backends appear to let it
4226 * slide by, and give the same results as if this field
4227 * were set correctly. Either way is acceptable for
4228 * our purposes here.
4229 */
4230
4231 break;
4232
4233 default:
4234 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4235 cmd->sc_data_direction);
4236 BUG();
4237 break;
4238 }
4239
33a2ffce 4240 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 4241 cmd_free(h, c);
4242 return SCSI_MLQUEUE_HOST_BUSY;
4243 }
4244 enqueue_cmd_and_start_io(h, c);
4245 /* the cmd'll come back via intr handler in complete_scsi_command() */
4246 return 0;
4247}
4248
080ef1cc
DB		 4249static void hpsa_command_resubmit_worker(struct work_struct *work)
4250{
4251 struct scsi_cmnd *cmd;
4252 struct hpsa_scsi_dev_t *dev;
4253 struct CommandList *c =
4254 container_of(work, struct CommandList, work);
4255
4256 cmd = c->scsi_cmd;
4257 dev = cmd->device->hostdata;
4258 if (!dev) {
4259 cmd->result = DID_NO_CONNECT << 16;
4260 cmd->scsi_done(cmd);
4261 return;
4262 }
4263 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4264 /*
4265 * If we get here, it means dma mapping failed. Try
4266 * again via scsi mid layer, which will then get
4267 * SCSI_MLQUEUE_HOST_BUSY.
4268 */
4269 cmd->result = DID_IMM_RETRY << 16;
4270 cmd->scsi_done(cmd);
4271 }
4272}
4273
574f05d3
SC		 4274/* Running in struct Scsi_Host->host_lock less mode */
4275static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4276{
4277 struct ctlr_info *h;
4278 struct hpsa_scsi_dev_t *dev;
4279 unsigned char scsi3addr[8];
4280 struct CommandList *c;
4281 int rc = 0;
4282
4283 /* Get the ptr to our adapter structure out of cmd->host. */
4284 h = sdev_to_hba(cmd->device);
4285 dev = cmd->device->hostdata;
4286 if (!dev) {
4287 cmd->result = DID_NO_CONNECT << 16;
4288 cmd->scsi_done(cmd);
4289 return 0;
4290 }
4291 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
4292
4293 if (unlikely(lockup_detected(h))) {
25163bd5 4294 cmd->result = DID_NO_CONNECT << 16;
574f05d3
SC		 4295 cmd->scsi_done(cmd);
4296 return 0;
4297 }
4298 c = cmd_alloc(h);
4299 if (c == NULL) { /* trouble... */
4300 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
4301 return SCSI_MLQUEUE_HOST_BUSY;
4302 }
407863cb 4303 if (unlikely(lockup_detected(h))) {
25163bd5 4304 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 4305 cmd_free(h, c);
4306 cmd->scsi_done(cmd);
4307 return 0;
4308 }
574f05d3 4309
407863cb
SC		 4310 /*
4311 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 4312 * Retries always go down the normal I/O path.
4313 */
4314 if (likely(cmd->retries == 0 &&
4315 cmd->request->cmd_type == REQ_TYPE_FS &&
4316 h->acciopath_status)) {
4317
4318 cmd->host_scribble = (unsigned char *) c;
4319 c->cmd_type = CMD_SCSI;
4320 c->scsi_cmd = cmd;
4321
4322 if (dev->offload_enabled) {
4323 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4324 if (rc == 0)
4325 return 0; /* Sent on ioaccel path */
4326 if (rc < 0) { /* scsi_dma_map failed. */
4327 cmd_free(h, c);
4328 return SCSI_MLQUEUE_HOST_BUSY;
4329 }
4330 } else if (dev->ioaccel_handle) {
4331 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4332 if (rc == 0)
4333 return 0; /* Sent on direct map path */
4334 if (rc < 0) { /* scsi_dma_map failed. */
4335 cmd_free(h, c);
4336 return SCSI_MLQUEUE_HOST_BUSY;
4337 }
4338 }
4339 }
4340 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4341}
4342
8ebc9248 4343static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 4344{
4345 unsigned long flags;
4346
8ebc9248
WS		 4347 spin_lock_irqsave(&h->scan_lock, flags);
4348 h->scan_finished = 1;
4349 wake_up_all(&h->scan_wait_queue);
4350 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 4351}
4352
a08a8471
SC		 4353static void hpsa_scan_start(struct Scsi_Host *sh)
4354{
4355 struct ctlr_info *h = shost_to_hba(sh);
4356 unsigned long flags;
4357
8ebc9248
WS		 4358 /*
4359 * Don't let rescans be initiated on a controller known to be locked
4360 * up. If the controller locks up *during* a rescan, that thread is
4361 * probably hosed, but at least we can prevent new rescan threads from
4362 * piling up on a locked up controller.
4363 */
4364 if (unlikely(lockup_detected(h)))
4365 return hpsa_scan_complete(h);
5f389360 4366
a08a8471
SC		 4367 /* wait until any scan already in progress is finished. */
4368 while (1) {
4369 spin_lock_irqsave(&h->scan_lock, flags);
4370 if (h->scan_finished)
4371 break;
4372 spin_unlock_irqrestore(&h->scan_lock, flags);
4373 wait_event(h->scan_wait_queue, h->scan_finished);
4374 /* Note: We don't need to worry about a race between this
4375 * thread and driver unload because the midlayer will
4376 * have incremented the reference count, so unload won't
4377 * happen if we're in here.
4378 */
4379 }
4380 h->scan_finished = 0; /* mark scan as in progress */
4381 spin_unlock_irqrestore(&h->scan_lock, flags);
4382
8ebc9248
WS		 4383 if (unlikely(lockup_detected(h)))
4384 return hpsa_scan_complete(h);
5f389360 4385
a08a8471
SC		 4386 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4387
8ebc9248 4388 hpsa_scan_complete(h);
a08a8471
SC		 4389}
4390
7c0a0229
DB		 4391static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4392{
03383736
DB		 4393 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
4394
4395 if (!logical_drive)
4396 return -ENODEV;
7c0a0229
DB		 4397
4398 if (qdepth < 1)
4399 qdepth = 1;
03383736
DB		 4400 else if (qdepth > logical_drive->queue_depth)
4401 qdepth = logical_drive->queue_depth;
4402
4403 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 4404}
4405
a08a8471
SC		 4406static int hpsa_scan_finished(struct Scsi_Host *sh,
4407 unsigned long elapsed_time)
4408{
4409 struct ctlr_info *h = shost_to_hba(sh);
4410 unsigned long flags;
4411 int finished;
4412
4413 spin_lock_irqsave(&h->scan_lock, flags);
4414 finished = h->scan_finished;
4415 spin_unlock_irqrestore(&h->scan_lock, flags);
4416 return finished;
4417}
4418
edd16368
SC		 4419static void hpsa_unregister_scsi(struct ctlr_info *h)
4420{
4421 /* we are being forcibly unloaded, and may not refuse. */
4422 scsi_remove_host(h->scsi_host);
4423 scsi_host_put(h->scsi_host);
4424 h->scsi_host = NULL;
4425}
4426
4427static int hpsa_register_scsi(struct ctlr_info *h)
4428{
b705690d
SC		 4429 struct Scsi_Host *sh;
4430 int error;
edd16368 4431
b705690d
SC		 4432 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4433 if (sh == NULL)
4434 goto fail;
4435
4436 sh->io_port = 0;
4437 sh->n_io_port = 0;
4438 sh->this_id = -1;
4439 sh->max_channel = 3;
4440 sh->max_cmd_len = MAX_COMMAND_SIZE;
4441 sh->max_lun = HPSA_MAX_LUN;
4442 sh->max_id = HPSA_MAX_LUN;
41ce4c35 4443 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 4444 sh->cmd_per_lun = sh->can_queue;
b705690d
SC		 4445 sh->sg_tablesize = h->maxsgentries;
4446 h->scsi_host = sh;
4447 sh->hostdata[0] = (unsigned long) h;
4448 sh->irq = h->intr[h->intr_mode];
4449 sh->unique_id = sh->irq;
4450 error = scsi_add_host(sh, &h->pdev->dev);
4451 if (error)
4452 goto fail_host_put;
4453 scsi_scan_host(sh);
4454 return 0;
4455
4456 fail_host_put:
4457 dev_err(&h->pdev->dev, "%s: scsi_add_host"
4458 " failed for controller %d\n", __func__, h->ctlr);
4459 scsi_host_put(sh);
4460 return error;
4461 fail:
4462 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
4463 " failed for controller %d\n", __func__, h->ctlr);
4464 return -ENOMEM;
edd16368
SC		 4465}
4466
4467static int wait_for_device_to_become_ready(struct ctlr_info *h,
4468 unsigned char lunaddr[])
4469{
8919358e 4470 int rc;
edd16368
SC		 4471 int count = 0;
4472 int waittime = 1; /* seconds */
4473 struct CommandList *c;
4474
45fcb86e 4475 c = cmd_alloc(h);
edd16368
SC		 4476 if (!c) {
4477 dev_warn(&h->pdev->dev, "out of memory in "
4478 "wait_for_device_to_become_ready.\n");
4479 return IO_ERROR;
4480 }
4481
4482 /* Send test unit ready until device ready, or give up. */
4483 while (count < HPSA_TUR_RETRY_LIMIT) {
4484
4485 /* Wait for a bit. do this first, because if we send
4486 * the TUR right away, the reset will just abort it.
4487 */
4488 msleep(1000 * waittime);
4489 count++;
8919358e 4490 rc = 0; /* Device ready. */
edd16368
SC		 4491
4492 /* Increase wait time with each try, up to a point. */
4493 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
4494 waittime = waittime * 2;
4495
a2dac136
SC		 4496 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4497 (void) fill_cmd(c, TEST_UNIT_READY, h,
4498 NULL, 0, 0, lunaddr, TYPE_CMD);
25163bd5
WS		 4499 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
4500 NO_TIMEOUT);
4501 if (rc)
4502 goto do_it_again;
edd16368
SC		 4503 /* no unmap needed here because no data xfer. */
4504
4505 if (c->err_info->CommandStatus == CMD_SUCCESS)
4506 break;
4507
4508 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4509 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
4510 (c->err_info->SenseInfo[2] == NO_SENSE ||
4511 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
4512 break;
25163bd5 4513do_it_again:
edd16368
SC		 4514 dev_warn(&h->pdev->dev, "waiting %d secs "
4515 "for device to become ready.\n", waittime);
4516 rc = 1; /* device not ready. */
4517 }
4518
4519 if (rc)
4520 dev_warn(&h->pdev->dev, "giving up on device.\n");
4521 else
4522 dev_warn(&h->pdev->dev, "device is ready.\n");
4523
45fcb86e 4524 cmd_free(h, c);
edd16368
SC		 4525 return rc;
4526}
4527
4528/* Need at least one of these error handlers to keep ../scsi/hosts.c from
4529 * complaining. Doing a host- or bus-reset can't do anything good here.
4530 */
4531static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
4532{
4533 int rc;
4534 struct ctlr_info *h;
4535 struct hpsa_scsi_dev_t *dev;
4536
4537 /* find the controller to which the command to be aborted was sent */
4538 h = sdev_to_hba(scsicmd->device);
4539 if (h == NULL) /* paranoia */
4540 return FAILED;
e345893b
DB		 4541
4542 if (lockup_detected(h))
4543 return FAILED;
4544
edd16368
SC		 4545 dev = scsicmd->device->hostdata;
4546 if (!dev) {
4547 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
4548 "device lookup failed.\n");
4549 return FAILED;
4550 }
25163bd5
WS		 4551
4552 /* if controller locked up, we can guarantee command won't complete */
4553 if (lockup_detected(h)) {
4554 dev_warn(&h->pdev->dev,
4555 "scsi %d:%d:%d:%d RESET FAILED, lockup detected\n",
4556 h->scsi_host->host_no, dev->bus, dev->target,
4557 dev->lun);
4558 return FAILED;
4559 }
4560
4561 /* this reset request might be the result of a lockup; check */
4562 if (detect_controller_lockup(h)) {
4563 dev_warn(&h->pdev->dev,
4564 "scsi %d:%d:%d:%d RESET FAILED, new lockup detected\n",
4565 h->scsi_host->host_no, dev->bus, dev->target,
4566 dev->lun);
4567 return FAILED;
4568 }
4569
4570 hpsa_show_dev_msg(KERN_WARNING, h, dev, "resetting");
4571
edd16368 4572 /* send a reset to the SCSI LUN which the command was sent to */
25163bd5
WS		 4573 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN,
4574 DEFAULT_REPLY_QUEUE);
edd16368
SC		 4575 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
4576 return SUCCESS;
4577
25163bd5
WS		 4578 dev_warn(&h->pdev->dev,
4579 "scsi %d:%d:%d:%d reset failed\n",
4580 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368
SC		 4581 return FAILED;
4582}
4583
6cba3f19
SC		 4584static void swizzle_abort_tag(u8 *tag)
4585{
4586 u8 original_tag[8];
4587
4588 memcpy(original_tag, tag, 8);
4589 tag[0] = original_tag[3];
4590 tag[1] = original_tag[2];
4591 tag[2] = original_tag[1];
4592 tag[3] = original_tag[0];
4593 tag[4] = original_tag[7];
4594 tag[5] = original_tag[6];
4595 tag[6] = original_tag[5];
4596 tag[7] = original_tag[4];
4597}
4598
17eb87d2 4599static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 4600 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 4601{
2b08b3e9 4602 u64 tag;
17eb87d2
ST		 4603 if (c->cmd_type == CMD_IOACCEL1) {
4604 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4605 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 4606 tag = le64_to_cpu(cm1->tag);
4607 *tagupper = cpu_to_le32(tag >> 32);
4608 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 4609 return;
4610 }
4611 if (c->cmd_type == CMD_IOACCEL2) {
4612 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4613 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4614 /* upper tag not used in ioaccel2 mode */
4615 memset(tagupper, 0, sizeof(*tagupper));
4616 *taglower = cm2->Tag;
54b6e9e9 4617 return;
17eb87d2 4618 }
2b08b3e9
DB		 4619 tag = le64_to_cpu(c->Header.tag);
4620 *tagupper = cpu_to_le32(tag >> 32);
4621 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 4622}
4623
75167d2c 4624static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 4625 struct CommandList *abort, int reply_queue)
75167d2c
SC		 4626{
4627 int rc = IO_OK;
4628 struct CommandList *c;
4629 struct ErrorInfo *ei;
2b08b3e9 4630 __le32 tagupper, taglower;
75167d2c 4631
45fcb86e 4632 c = cmd_alloc(h);
75167d2c 4633 if (c == NULL) { /* trouble... */
45fcb86e 4634 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
75167d2c
SC		 4635 return -ENOMEM;
4636 }
4637
a2dac136 4638 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 4639 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 4640 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 4641 if (h->needs_abort_tags_swizzled)
6cba3f19 4642 swizzle_abort_tag(&c->Request.CDB[4]);
25163bd5 4643 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
17eb87d2 4644 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 4645 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 4646 __func__, tagupper, taglower);
75167d2c
SC		 4647 /* no unmap needed here because no data xfer. */
4648
4649 ei = c->err_info;
4650 switch (ei->CommandStatus) {
4651 case CMD_SUCCESS:
4652 break;
4653 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4654 rc = -1;
4655 break;
4656 default:
4657 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4658 __func__, tagupper, taglower);
d1e8beac 4659 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4660 rc = -1;
4661 break;
4662 }
45fcb86e 4663 cmd_free(h, c);
dd0e19f3
ST		 4664 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4665 __func__, tagupper, taglower);
75167d2c
SC		 4666 return rc;
4667}
4668
54b6e9e9
ST		 4669/* ioaccel2 path firmware cannot handle abort task requests.
4670 * Change abort requests to physical target reset, and send to the
4671 * address of the physical disk used for the ioaccel 2 command.
4672 * Return 0 on success (IO_OK)
4673 * -1 on failure
4674 */
4675
4676static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 4677 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 4678{
4679 int rc = IO_OK;
4680 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4681 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4682 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4683 unsigned char *psa = &phys_scsi3addr[0];
4684
4685 /* Get a pointer to the hpsa logical device. */
7fa3030c 4686 scmd = abort->scsi_cmd;
54b6e9e9
ST		 4687 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4688 if (dev == NULL) {
4689 dev_warn(&h->pdev->dev,
4690 "Cannot abort: no device pointer for command.\n");
4691 return -1; /* not abortable */
4692 }
4693
2ba8bfc8
SC		 4694 if (h->raid_offload_debug > 0)
4695 dev_info(&h->pdev->dev,
0d96ef5f 4696 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 4697 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 4698 "Reset as abort",
2ba8bfc8
SC		 4699 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
4700 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
4701
54b6e9e9
ST		 4702 if (!dev->offload_enabled) {
4703 dev_warn(&h->pdev->dev,
4704 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4705 return -1; /* not abortable */
4706 }
4707
4708 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4709 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4710 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4711 return -1; /* not abortable */
4712 }
4713
4714 /* send the reset */
2ba8bfc8
SC		 4715 if (h->raid_offload_debug > 0)
4716 dev_info(&h->pdev->dev,
4717 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4718 psa[0], psa[1], psa[2], psa[3],
4719 psa[4], psa[5], psa[6], psa[7]);
25163bd5 4720 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 4721 if (rc != 0) {
4722 dev_warn(&h->pdev->dev,
4723 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4724 psa[0], psa[1], psa[2], psa[3],
4725 psa[4], psa[5], psa[6], psa[7]);
4726 return rc; /* failed to reset */
4727 }
4728
4729 /* wait for device to recover */
4730 if (wait_for_device_to_become_ready(h, psa) != 0) {
4731 dev_warn(&h->pdev->dev,
4732 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4733 psa[0], psa[1], psa[2], psa[3],
4734 psa[4], psa[5], psa[6], psa[7]);
4735 return -1; /* failed to recover */
4736 }
4737
4738 /* device recovered */
4739 dev_info(&h->pdev->dev,
4740 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4741 psa[0], psa[1], psa[2], psa[3],
4742 psa[4], psa[5], psa[6], psa[7]);
4743
4744 return rc; /* success */
4745}
4746
6cba3f19 4747static int hpsa_send_abort_both_ways(struct ctlr_info *h,
25163bd5 4748 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
6cba3f19 4749{
54b6e9e9
ST		 4750 /* ioccelerator mode 2 commands should be aborted via the
4751 * accelerated path, since RAID path is unaware of these commands,
4752 * but underlying firmware can't handle abort TMF.
4753 * Change abort to physical device reset.
4754 */
4755 if (abort->cmd_type == CMD_IOACCEL2)
25163bd5
WS		 4756 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
4757 abort, reply_queue);
9b5c48c2 4758 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
25163bd5 4759}
54b6e9e9 4760
25163bd5
WS		 4761/* Find out which reply queue a command was meant to return on */
4762static int hpsa_extract_reply_queue(struct ctlr_info *h,
4763 struct CommandList *c)
4764{
4765 if (c->cmd_type == CMD_IOACCEL2)
4766 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
4767 return c->Header.ReplyQueue;
6cba3f19
SC		 4768}
4769
9b5c48c2
SC		 4770/*
4771 * Limit concurrency of abort commands to prevent
4772 * over-subscription of commands
4773 */
4774static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
4775{
4776#define ABORT_CMD_WAIT_MSECS 5000
4777 return !wait_event_timeout(h->abort_cmd_wait_queue,
4778 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
4779 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
4780}
4781
75167d2c
SC		 4782/* Send an abort for the specified command.
4783 * If the device and controller support it,
4784 * send a task abort request.
4785 */
4786static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
4787{
4788
4789 int i, rc;
4790 struct ctlr_info *h;
4791 struct hpsa_scsi_dev_t *dev;
4792 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 4793 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
4794 char msg[256]; /* For debug messaging. */
4795 int ml = 0;
2b08b3e9 4796 __le32 tagupper, taglower;
25163bd5
WS		 4797 int refcount, reply_queue;
4798
4799 if (sc == NULL)
4800 return FAILED;
75167d2c 4801
9b5c48c2
SC		 4802 if (sc->device == NULL)
4803 return FAILED;
4804
75167d2c
SC		 4805 /* Find the controller of the command to be aborted */
4806 h = sdev_to_hba(sc->device);
9b5c48c2 4807 if (h == NULL)
75167d2c
SC		 4808 return FAILED;
4809
25163bd5
WS		 4810 /* Find the device of the command to be aborted */
4811 dev = sc->device->hostdata;
4812 if (!dev) {
4813 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
4814 msg);
e345893b 4815 return FAILED;
25163bd5
WS		 4816 }
4817
4818 /* If controller locked up, we can guarantee command won't complete */
4819 if (lockup_detected(h)) {
4820 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4821 "ABORT FAILED, lockup detected");
4822 return FAILED;
4823 }
4824
4825 /* This is a good time to check if controller lockup has occurred */
4826 if (detect_controller_lockup(h)) {
4827 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4828 "ABORT FAILED, new lockup detected");
4829 return FAILED;
4830 }
e345893b 4831
75167d2c
SC		 4832 /* Check that controller supports some kind of task abort */
4833 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
4834 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
4835 return FAILED;
4836
4837 memset(msg, 0, sizeof(msg));
0d96ef5f 4838 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s",
75167d2c 4839 h->scsi_host->host_no, sc->device->channel,
0d96ef5f
WS		 4840 sc->device->id, sc->device->lun,
4841 "Aborting command");
75167d2c 4842
75167d2c
SC		 4843 /* Get SCSI command to be aborted */
4844 abort = (struct CommandList *) sc->host_scribble;
4845 if (abort == NULL) {
281a7fd0
WS		 4846 /* This can happen if the command already completed. */
4847 return SUCCESS;
4848 }
4849 refcount = atomic_inc_return(&abort->refcount);
4850 if (refcount == 1) { /* Command is done already. */
4851 cmd_free(h, abort);
4852 return SUCCESS;
75167d2c 4853 }
9b5c48c2
SC		 4854
4855 /* Don't bother trying the abort if we know it won't work. */
4856 if (abort->cmd_type != CMD_IOACCEL2 &&
4857 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
4858 cmd_free(h, abort);
4859 return FAILED;
4860 }
4861
17eb87d2 4862 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 4863 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 4864 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 4865 as = abort->scsi_cmd;
75167d2c
SC		 4866 if (as != NULL)
4867 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
4868 as->cmnd[0], as->serial_number);
4869 dev_dbg(&h->pdev->dev, "%s\n", msg);
0d96ef5f 4870 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
75167d2c
SC		 4871 /*
4872 * Command is in flight, or possibly already completed
4873 * by the firmware (but not to the scsi mid layer) but we can't
4874 * distinguish which. Send the abort down.
4875 */
9b5c48c2
SC		 4876 if (wait_for_available_abort_cmd(h)) {
4877 dev_warn(&h->pdev->dev,
4878 "Timed out waiting for an abort command to become available.\n");
4879 cmd_free(h, abort);
4880 return FAILED;
4881 }
25163bd5 4882 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
9b5c48c2
SC		 4883 atomic_inc(&h->abort_cmds_available);
4884 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 4885 if (rc != 0) {
0d96ef5f
WS		 4886 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4887 "FAILED to abort command");
281a7fd0 4888 cmd_free(h, abort);
75167d2c
SC		 4889 return FAILED;
4890 }
4891 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
4892
4893 /* If the abort(s) above completed and actually aborted the
4894 * command, then the command to be aborted should already be
4895 * completed. If not, wait around a bit more to see if they
4896 * manage to complete normally.
4897 */
4898#define ABORT_COMPLETE_WAIT_SECS 30
4899 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
281a7fd0
WS		 4900 refcount = atomic_read(&abort->refcount);
4901 if (refcount < 2) {
4902 cmd_free(h, abort);
75167d2c 4903 return SUCCESS;
281a7fd0
WS		 4904 } else {
4905 msleep(100);
4906 }
75167d2c
SC		 4907 }
4908 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
4909 msg, ABORT_COMPLETE_WAIT_SECS);
281a7fd0 4910 cmd_free(h, abort);
75167d2c
SC		 4911 return FAILED;
4912}
4913
edd16368
SC		 4914/*
4915 * For operations that cannot sleep, a command block is allocated at init,
4916 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4917 * which ones are free or in use. Lock must be held when calling this.
4918 * cmd_free() is the complement.
4919 */
281a7fd0 4920
edd16368
SC		 4921static struct CommandList *cmd_alloc(struct ctlr_info *h)
4922{
4923 struct CommandList *c;
4924 int i;
4925 union u64bit temp64;
4926 dma_addr_t cmd_dma_handle, err_dma_handle;
281a7fd0 4927 int refcount;
33811026 4928 unsigned long offset;
4c413128 4929
33811026
RE		 4930 /*
4931 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 4932 * multiple threads could get in here, and one thread could
4933 * be scanning through the list of bits looking for a free
4934 * one, but the free ones are always behind him, and other
4935 * threads sneak in behind him and eat them before he can
4936 * get to them, so that while there is always a free one, a
4937 * very unlucky thread might be starved anyway, never able to
4938 * beat the other threads. In reality, this happens so
4939 * infrequently as to be indistinguishable from never.
4940 */
edd16368 4941
33811026 4942 offset = h->last_allocation; /* benignly racy */
281a7fd0
WS		 4943 for (;;) {
4944 i = find_next_zero_bit(h->cmd_pool_bits, h->nr_cmds, offset);
4945 if (unlikely(i == h->nr_cmds)) {
4946 offset = 0;
4947 continue;
4948 }
4949 c = h->cmd_pool + i;
4950 refcount = atomic_inc_return(&c->refcount);
4951 if (unlikely(refcount > 1)) {
4952 cmd_free(h, c); /* already in use */
4953 offset = (i + 1) % h->nr_cmds;
4954 continue;
4955 }
4956 set_bit(i & (BITS_PER_LONG - 1),
4957 h->cmd_pool_bits + (i / BITS_PER_LONG));
4958 break; /* it's ours now. */
4959 }
33811026 4960 h->last_allocation = i; /* benignly racy */
281a7fd0
WS		 4961
4962 /* Zero out all of commandlist except the last field, refcount */
4963 memset(c, 0, offsetof(struct CommandList, refcount));
4964 c->Header.tag = cpu_to_le64((u64) (i << DIRECT_LOOKUP_SHIFT));
f2405db8 4965 cmd_dma_handle = h->cmd_pool_dhandle + i * sizeof(*c);
edd16368
SC		 4966 c->err_info = h->errinfo_pool + i;
4967 memset(c->err_info, 0, sizeof(*c->err_info));
4968 err_dma_handle = h->errinfo_pool_dhandle
4969 + i * sizeof(*c->err_info);
edd16368
SC		 4970
4971 c->cmdindex = i;
4972
01a02ffc
SC		 4973 c->busaddr = (u32) cmd_dma_handle;
4974 temp64.val = (u64) err_dma_handle;
281a7fd0
WS		 4975 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4976 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
edd16368
SC		 4977
4978 c->h = h;
4979 return c;
4980}
4981
edd16368
SC		 4982static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4983{
281a7fd0
WS		 4984 if (atomic_dec_and_test(&c->refcount)) {
4985 int i;
edd16368 4986
281a7fd0
WS		 4987 i = c - h->cmd_pool;
4988 clear_bit(i & (BITS_PER_LONG - 1),
4989 h->cmd_pool_bits + (i / BITS_PER_LONG));
4990 }
edd16368
SC		 4991}
4992
edd16368
SC		 4993#ifdef CONFIG_COMPAT
4994
42a91641
DB		 4995static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
4996 void __user *arg)
edd16368
SC		 4997{
4998 IOCTL32_Command_struct __user *arg32 =
4999 (IOCTL32_Command_struct __user *) arg;
5000 IOCTL_Command_struct arg64;
5001 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5002 int err;
5003 u32 cp;
5004
938abd84 5005 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5006 err = 0;
5007 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5008 sizeof(arg64.LUN_info));
5009 err |= copy_from_user(&arg64.Request, &arg32->Request,
5010 sizeof(arg64.Request));
5011 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5012 sizeof(arg64.error_info));
5013 err |= get_user(arg64.buf_size, &arg32->buf_size);
5014 err |= get_user(cp, &arg32->buf);
5015 arg64.buf = compat_ptr(cp);
5016 err |= copy_to_user(p, &arg64, sizeof(arg64));
5017
5018 if (err)
5019 return -EFAULT;
5020
42a91641 5021 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 5022 if (err)
5023 return err;
5024 err |= copy_in_user(&arg32->error_info, &p->error_info,
5025 sizeof(arg32->error_info));
5026 if (err)
5027 return -EFAULT;
5028 return err;
5029}
5030
5031static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 5032 int cmd, void __user *arg)
edd16368
SC		 5033{
5034 BIG_IOCTL32_Command_struct __user *arg32 =
5035 (BIG_IOCTL32_Command_struct __user *) arg;
5036 BIG_IOCTL_Command_struct arg64;
5037 BIG_IOCTL_Command_struct __user *p =
5038 compat_alloc_user_space(sizeof(arg64));
5039 int err;
5040 u32 cp;
5041
938abd84 5042 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5043 err = 0;
5044 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5045 sizeof(arg64.LUN_info));
5046 err |= copy_from_user(&arg64.Request, &arg32->Request,
5047 sizeof(arg64.Request));
5048 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5049 sizeof(arg64.error_info));
5050 err |= get_user(arg64.buf_size, &arg32->buf_size);
5051 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5052 err |= get_user(cp, &arg32->buf);
5053 arg64.buf = compat_ptr(cp);
5054 err |= copy_to_user(p, &arg64, sizeof(arg64));
5055
5056 if (err)
5057 return -EFAULT;
5058
42a91641 5059 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 5060 if (err)
5061 return err;
5062 err |= copy_in_user(&arg32->error_info, &p->error_info,
5063 sizeof(arg32->error_info));
5064 if (err)
5065 return -EFAULT;
5066 return err;
5067}
71fe75a7 5068
42a91641 5069static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 5070{
5071 switch (cmd) {
5072 case CCISS_GETPCIINFO:
5073 case CCISS_GETINTINFO:
5074 case CCISS_SETINTINFO:
5075 case CCISS_GETNODENAME:
5076 case CCISS_SETNODENAME:
5077 case CCISS_GETHEARTBEAT:
5078 case CCISS_GETBUSTYPES:
5079 case CCISS_GETFIRMVER:
5080 case CCISS_GETDRIVVER:
5081 case CCISS_REVALIDVOLS:
5082 case CCISS_DEREGDISK:
5083 case CCISS_REGNEWDISK:
5084 case CCISS_REGNEWD:
5085 case CCISS_RESCANDISK:
5086 case CCISS_GETLUNINFO:
5087 return hpsa_ioctl(dev, cmd, arg);
5088
5089 case CCISS_PASSTHRU32:
5090 return hpsa_ioctl32_passthru(dev, cmd, arg);
5091 case CCISS_BIG_PASSTHRU32:
5092 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5093
5094 default:
5095 return -ENOIOCTLCMD;
5096 }
5097}
edd16368
SC		 5098#endif
5099
5100static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5101{
5102 struct hpsa_pci_info pciinfo;
5103
5104 if (!argp)
5105 return -EINVAL;
5106 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5107 pciinfo.bus = h->pdev->bus->number;
5108 pciinfo.dev_fn = h->pdev->devfn;
5109 pciinfo.board_id = h->board_id;
5110 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5111 return -EFAULT;
5112 return 0;
5113}
5114
5115static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
5116{
5117 DriverVer_type DriverVer;
5118 unsigned char vmaj, vmin, vsubmin;
5119 int rc;
5120
5121 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
5122 &vmaj, &vmin, &vsubmin);
5123 if (rc != 3) {
5124 dev_info(&h->pdev->dev, "driver version string '%s' "
5125 "unrecognized.", HPSA_DRIVER_VERSION);
5126 vmaj = 0;
5127 vmin = 0;
5128 vsubmin = 0;
5129 }
5130 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
5131 if (!argp)
5132 return -EINVAL;
5133 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
5134 return -EFAULT;
5135 return 0;
5136}
5137
5138static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5139{
5140 IOCTL_Command_struct iocommand;
5141 struct CommandList *c;
5142 char *buff = NULL;
50a0decf 5143 u64 temp64;
c1f63c8f 5144 int rc = 0;
edd16368
SC		 5145
5146 if (!argp)
5147 return -EINVAL;
5148 if (!capable(CAP_SYS_RAWIO))
5149 return -EPERM;
5150 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
5151 return -EFAULT;
5152 if ((iocommand.buf_size < 1) &&
5153 (iocommand.Request.Type.Direction != XFER_NONE)) {
5154 return -EINVAL;
5155 }
5156 if (iocommand.buf_size > 0) {
5157 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
5158 if (buff == NULL)
5159 return -EFAULT;
9233fb10 5160 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 5161 /* Copy the data into the buffer we created */
5162 if (copy_from_user(buff, iocommand.buf,
5163 iocommand.buf_size)) {
c1f63c8f
SC		 5164 rc = -EFAULT;
5165 goto out_kfree;
b03a7771
SC		 5166 }
5167 } else {
5168 memset(buff, 0, iocommand.buf_size);
edd16368 5169 }
b03a7771 5170 }
45fcb86e 5171 c = cmd_alloc(h);
edd16368 5172 if (c == NULL) {
c1f63c8f
SC		 5173 rc = -ENOMEM;
5174 goto out_kfree;
edd16368
SC		 5175 }
5176 /* Fill in the command type */
5177 c->cmd_type = CMD_IOCTL_PEND;
5178 /* Fill in Command Header */
5179 c->Header.ReplyQueue = 0; /* unused in simple mode */
5180 if (iocommand.buf_size > 0) { /* buffer to fill */
5181 c->Header.SGList = 1;
50a0decf 5182 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5183 } else { /* no buffers to fill */
5184 c->Header.SGList = 0;
50a0decf 5185 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 5186 }
5187 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5188
5189 /* Fill in Request block */
5190 memcpy(&c->Request, &iocommand.Request,
5191 sizeof(c->Request));
5192
5193 /* Fill in the scatter gather information */
5194 if (iocommand.buf_size > 0) {
50a0decf 5195 temp64 = pci_map_single(h->pdev, buff,
edd16368 5196 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5197 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
5198 c->SG[0].Addr = cpu_to_le64(0);
5199 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 5200 rc = -ENOMEM;
5201 goto out;
5202 }
50a0decf
SC		 5203 c->SG[0].Addr = cpu_to_le64(temp64);
5204 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
5205 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 5206 }
25163bd5 5207 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
c2dd32e0
SC		 5208 if (iocommand.buf_size > 0)
5209 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 5210 check_ioctl_unit_attention(h, c);
25163bd5
WS		 5211 if (rc) {
5212 rc = -EIO;
5213 goto out;
5214 }
edd16368
SC		 5215
5216 /* Copy the error information out */
5217 memcpy(&iocommand.error_info, c->err_info,
5218 sizeof(iocommand.error_info));
5219 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 5220 rc = -EFAULT;
5221 goto out;
edd16368 5222 }
9233fb10 5223 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 5224 iocommand.buf_size > 0) {
edd16368
SC		 5225 /* Copy the data out of the buffer we created */
5226 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 5227 rc = -EFAULT;
5228 goto out;
edd16368
SC		 5229 }
5230 }
c1f63c8f 5231out:
45fcb86e 5232 cmd_free(h, c);
c1f63c8f
SC		 5233out_kfree:
5234 kfree(buff);
5235 return rc;
edd16368
SC		 5236}
5237
5238static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5239{
5240 BIG_IOCTL_Command_struct *ioc;
5241 struct CommandList *c;
5242 unsigned char **buff = NULL;
5243 int *buff_size = NULL;
50a0decf 5244 u64 temp64;
edd16368
SC		 5245 BYTE sg_used = 0;
5246 int status = 0;
01a02ffc
SC		 5247 u32 left;
5248 u32 sz;
edd16368
SC		 5249 BYTE __user *data_ptr;
5250
5251 if (!argp)
5252 return -EINVAL;
5253 if (!capable(CAP_SYS_RAWIO))
5254 return -EPERM;
5255 ioc = (BIG_IOCTL_Command_struct *)
5256 kmalloc(sizeof(*ioc), GFP_KERNEL);
5257 if (!ioc) {
5258 status = -ENOMEM;
5259 goto cleanup1;
5260 }
5261 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
5262 status = -EFAULT;
5263 goto cleanup1;
5264 }
5265 if ((ioc->buf_size < 1) &&
5266 (ioc->Request.Type.Direction != XFER_NONE)) {
5267 status = -EINVAL;
5268 goto cleanup1;
5269 }
5270 /* Check kmalloc limits using all SGs */
5271 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
5272 status = -EINVAL;
5273 goto cleanup1;
5274 }
d66ae08b 5275 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 5276 status = -EINVAL;
5277 goto cleanup1;
5278 }
d66ae08b 5279 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 5280 if (!buff) {
5281 status = -ENOMEM;
5282 goto cleanup1;
5283 }
d66ae08b 5284 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 5285 if (!buff_size) {
5286 status = -ENOMEM;
5287 goto cleanup1;
5288 }
5289 left = ioc->buf_size;
5290 data_ptr = ioc->buf;
5291 while (left) {
5292 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
5293 buff_size[sg_used] = sz;
5294 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
5295 if (buff[sg_used] == NULL) {
5296 status = -ENOMEM;
5297 goto cleanup1;
5298 }
9233fb10 5299 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 5300 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 5301 status = -EFAULT;
edd16368
SC		 5302 goto cleanup1;
5303 }
5304 } else
5305 memset(buff[sg_used], 0, sz);
5306 left -= sz;
5307 data_ptr += sz;
5308 sg_used++;
5309 }
45fcb86e 5310 c = cmd_alloc(h);
edd16368
SC		 5311 if (c == NULL) {
5312 status = -ENOMEM;
5313 goto cleanup1;
5314 }
5315 c->cmd_type = CMD_IOCTL_PEND;
5316 c->Header.ReplyQueue = 0;
50a0decf
SC		 5317 c->Header.SGList = (u8) sg_used;
5318 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 5319 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5320 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
5321 if (ioc->buf_size > 0) {
5322 int i;
5323 for (i = 0; i < sg_used; i++) {
50a0decf 5324 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 5325 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5326 if (dma_mapping_error(&h->pdev->dev,
5327 (dma_addr_t) temp64)) {
5328 c->SG[i].Addr = cpu_to_le64(0);
5329 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 5330 hpsa_pci_unmap(h->pdev, c, i,
5331 PCI_DMA_BIDIRECTIONAL);
5332 status = -ENOMEM;
e2d4a1f6 5333 goto cleanup0;
bcc48ffa 5334 }
50a0decf
SC		 5335 c->SG[i].Addr = cpu_to_le64(temp64);
5336 c->SG[i].Len = cpu_to_le32(buff_size[i]);
5337 c->SG[i].Ext = cpu_to_le32(0);
edd16368 5338 }
50a0decf 5339 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 5340 }
25163bd5 5341 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
b03a7771
SC		 5342 if (sg_used)
5343 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 5344 check_ioctl_unit_attention(h, c);
25163bd5
WS		 5345 if (status) {
5346 status = -EIO;
5347 goto cleanup0;
5348 }
5349
edd16368
SC		 5350 /* Copy the error information out */
5351 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
5352 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 5353 status = -EFAULT;
e2d4a1f6 5354 goto cleanup0;
edd16368 5355 }
9233fb10 5356 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 5357 int i;
5358
edd16368
SC		 5359 /* Copy the data out of the buffer we created */
5360 BYTE __user *ptr = ioc->buf;
5361 for (i = 0; i < sg_used; i++) {
5362 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 5363 status = -EFAULT;
e2d4a1f6 5364 goto cleanup0;
edd16368
SC		 5365 }
5366 ptr += buff_size[i];
5367 }
5368 }
edd16368 5369 status = 0;
e2d4a1f6 5370cleanup0:
45fcb86e 5371 cmd_free(h, c);
edd16368
SC		 5372cleanup1:
5373 if (buff) {
2b08b3e9
DB		 5374 int i;
5375
edd16368
SC		 5376 for (i = 0; i < sg_used; i++)
5377 kfree(buff[i]);
5378 kfree(buff);
5379 }
5380 kfree(buff_size);
5381 kfree(ioc);
5382 return status;
5383}
5384
5385static void check_ioctl_unit_attention(struct ctlr_info *h,
5386 struct CommandList *c)
5387{
5388 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5389 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
5390 (void) check_for_unit_attention(h, c);
5391}
0390f0c0 5392
edd16368
SC		 5393/*
5394 * ioctl
5395 */
42a91641 5396static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 5397{
5398 struct ctlr_info *h;
5399 void __user *argp = (void __user *)arg;
0390f0c0 5400 int rc;
edd16368
SC		 5401
5402 h = sdev_to_hba(dev);
5403
5404 switch (cmd) {
5405 case CCISS_DEREGDISK:
5406 case CCISS_REGNEWDISK:
5407 case CCISS_REGNEWD:
a08a8471 5408 hpsa_scan_start(h->scsi_host);
edd16368
SC		 5409 return 0;
5410 case CCISS_GETPCIINFO:
5411 return hpsa_getpciinfo_ioctl(h, argp);
5412 case CCISS_GETDRIVVER:
5413 return hpsa_getdrivver_ioctl(h, argp);
5414 case CCISS_PASSTHRU:
34f0c627 5415 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 5416 return -EAGAIN;
5417 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 5418 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 5419 return rc;
edd16368 5420 case CCISS_BIG_PASSTHRU:
34f0c627 5421 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 5422 return -EAGAIN;
5423 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 5424 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 5425 return rc;
edd16368
SC		 5426 default:
5427 return -ENOTTY;
5428 }
5429}
5430
6f039790
GKH		 5431static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
5432 u8 reset_type)
64670ac8
SC		 5433{
5434 struct CommandList *c;
5435
5436 c = cmd_alloc(h);
5437 if (!c)
5438 return -ENOMEM;
a2dac136
SC		 5439 /* fill_cmd can't fail here, no data buffer to map */
5440 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 5441 RAID_CTLR_LUNID, TYPE_MSG);
5442 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
5443 c->waiting = NULL;
5444 enqueue_cmd_and_start_io(h, c);
5445 /* Don't wait for completion, the reset won't complete. Don't free
5446 * the command either. This is the last command we will send before
5447 * re-initializing everything, so it doesn't matter and won't leak.
5448 */
5449 return 0;
5450}
5451
a2dac136 5452static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 5453 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 5454 int cmd_type)
5455{
5456 int pci_dir = XFER_NONE;
9b5c48c2 5457 u64 tag; /* for commands to be aborted */
edd16368
SC		 5458
5459 c->cmd_type = CMD_IOCTL_PEND;
5460 c->Header.ReplyQueue = 0;
5461 if (buff != NULL && size > 0) {
5462 c->Header.SGList = 1;
50a0decf 5463 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5464 } else {
5465 c->Header.SGList = 0;
50a0decf 5466 c->Header.SGTotal = cpu_to_le16(0);
edd16368 5467 }
edd16368
SC		 5468 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
5469
edd16368
SC		 5470 if (cmd_type == TYPE_CMD) {
5471 switch (cmd) {
5472 case HPSA_INQUIRY:
5473 /* are we trying to read a vital product page */
b7bb24eb 5474 if (page_code & VPD_PAGE) {
edd16368 5475 c->Request.CDB[1] = 0x01;
b7bb24eb 5476 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 5477 }
5478 c->Request.CDBLen = 6;
a505b86f
SC		 5479 c->Request.type_attr_dir =
5480 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5481 c->Request.Timeout = 0;
5482 c->Request.CDB[0] = HPSA_INQUIRY;
5483 c->Request.CDB[4] = size & 0xFF;
5484 break;
5485 case HPSA_REPORT_LOG:
5486 case HPSA_REPORT_PHYS:
5487 /* Talking to controller so It's a physical command
5488 mode = 00 target = 0. Nothing to write.
5489 */
5490 c->Request.CDBLen = 12;
a505b86f
SC		 5491 c->Request.type_attr_dir =
5492 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5493 c->Request.Timeout = 0;
5494 c->Request.CDB[0] = cmd;
5495 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5496 c->Request.CDB[7] = (size >> 16) & 0xFF;
5497 c->Request.CDB[8] = (size >> 8) & 0xFF;
5498 c->Request.CDB[9] = size & 0xFF;
5499 break;
edd16368
SC		 5500 case HPSA_CACHE_FLUSH:
5501 c->Request.CDBLen = 12;
a505b86f
SC		 5502 c->Request.type_attr_dir =
5503 TYPE_ATTR_DIR(cmd_type,
5504 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5505 c->Request.Timeout = 0;
5506 c->Request.CDB[0] = BMIC_WRITE;
5507 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 5508 c->Request.CDB[7] = (size >> 8) & 0xFF;
5509 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 5510 break;
5511 case TEST_UNIT_READY:
5512 c->Request.CDBLen = 6;
a505b86f
SC		 5513 c->Request.type_attr_dir =
5514 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5515 c->Request.Timeout = 0;
5516 break;
283b4a9b
SC		 5517 case HPSA_GET_RAID_MAP:
5518 c->Request.CDBLen = 12;
a505b86f
SC		 5519 c->Request.type_attr_dir =
5520 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 5521 c->Request.Timeout = 0;
5522 c->Request.CDB[0] = HPSA_CISS_READ;
5523 c->Request.CDB[1] = cmd;
5524 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5525 c->Request.CDB[7] = (size >> 16) & 0xFF;
5526 c->Request.CDB[8] = (size >> 8) & 0xFF;
5527 c->Request.CDB[9] = size & 0xFF;
5528 break;
316b221a
SC		 5529 case BMIC_SENSE_CONTROLLER_PARAMETERS:
5530 c->Request.CDBLen = 10;
a505b86f
SC		 5531 c->Request.type_attr_dir =
5532 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 5533 c->Request.Timeout = 0;
5534 c->Request.CDB[0] = BMIC_READ;
5535 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
5536 c->Request.CDB[7] = (size >> 16) & 0xFF;
5537 c->Request.CDB[8] = (size >> 8) & 0xFF;
5538 break;
03383736
DB		 5539 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
5540 c->Request.CDBLen = 10;
5541 c->Request.type_attr_dir =
5542 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
5543 c->Request.Timeout = 0;
5544 c->Request.CDB[0] = BMIC_READ;
5545 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
5546 c->Request.CDB[7] = (size >> 16) & 0xFF;
5547 c->Request.CDB[8] = (size >> 8) & 0XFF;
5548 break;
edd16368
SC		 5549 default:
5550 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5551 BUG();
a2dac136 5552 return -1;
edd16368
SC		 5553 }
5554 } else if (cmd_type == TYPE_MSG) {
5555 switch (cmd) {
5556
5557 case HPSA_DEVICE_RESET_MSG:
5558 c->Request.CDBLen = 16;
a505b86f
SC		 5559 c->Request.type_attr_dir =
5560 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 5561 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5562 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5563 c->Request.CDB[0] = cmd;
21e89afd 5564 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5565 /* If bytes 4-7 are zero, it means reset the */
5566 /* LunID device */
5567 c->Request.CDB[4] = 0x00;
5568 c->Request.CDB[5] = 0x00;
5569 c->Request.CDB[6] = 0x00;
5570 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5571 break;
5572 case HPSA_ABORT_MSG:
9b5c48c2 5573 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 5574 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 5575 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
5576 tag, c->Header.tag);
75167d2c 5577 c->Request.CDBLen = 16;
a505b86f
SC		 5578 c->Request.type_attr_dir =
5579 TYPE_ATTR_DIR(cmd_type,
5580 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 5581 c->Request.Timeout = 0; /* Don't time out */
5582 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5583 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5584 c->Request.CDB[2] = 0x00; /* reserved */
5585 c->Request.CDB[3] = 0x00; /* reserved */
5586 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 5587 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 5588 c->Request.CDB[12] = 0x00; /* reserved */
5589 c->Request.CDB[13] = 0x00; /* reserved */
5590 c->Request.CDB[14] = 0x00; /* reserved */
5591 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5592 break;
edd16368
SC		 5593 default:
5594 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5595 cmd);
5596 BUG();
5597 }
5598 } else {
5599 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5600 BUG();
5601 }
5602
a505b86f 5603 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 5604 case XFER_READ:
5605 pci_dir = PCI_DMA_FROMDEVICE;
5606 break;
5607 case XFER_WRITE:
5608 pci_dir = PCI_DMA_TODEVICE;
5609 break;
5610 case XFER_NONE:
5611 pci_dir = PCI_DMA_NONE;
5612 break;
5613 default:
5614 pci_dir = PCI_DMA_BIDIRECTIONAL;
5615 }
a2dac136
SC		 5616 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5617 return -1;
5618 return 0;
edd16368
SC		 5619}
5620
5621/*
5622 * Map (physical) PCI mem into (virtual) kernel space
5623 */
5624static void __iomem *remap_pci_mem(ulong base, ulong size)
5625{
5626 ulong page_base = ((ulong) base) & PAGE_MASK;
5627 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5628 void __iomem *page_remapped = ioremap_nocache(page_base,
5629 page_offs + size);
edd16368
SC		 5630
5631 return page_remapped ? (page_remapped + page_offs) : NULL;
5632}
5633
254f796b 5634static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5635{
254f796b 5636 return h->access.command_completed(h, q);
edd16368
SC		 5637}
5638
900c5440 5639static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5640{
5641 return h->access.intr_pending(h);
5642}
5643
5644static inline long interrupt_not_for_us(struct ctlr_info *h)
5645{
10f66018
SC		 5646 return (h->access.intr_pending(h) == 0) ||
5647 (h->interrupts_enabled == 0);
edd16368
SC		 5648}
5649
01a02ffc
SC		 5650static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5651 u32 raw_tag)
edd16368
SC		 5652{
5653 if (unlikely(tag_index >= h->nr_cmds)) {
5654 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5655 return 1;
5656 }
5657 return 0;
5658}
5659
5a3d16f5 5660static inline void finish_cmd(struct CommandList *c)
edd16368 5661{
e85c5974 5662 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5663 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5664 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5665 complete_scsi_command(c);
edd16368
SC		 5666 else if (c->cmd_type == CMD_IOCTL_PEND)
5667 complete(c->waiting);
a104c99f
SC		 5668}
5669
a9a3a273
SC		 5670
5671static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5672{
a9a3a273
SC		 5673#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5674#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5675 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5676 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5677 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5678}
5679
303932fd 5680/* process completion of an indexed ("direct lookup") command */
1d94f94d 5681static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5682 u32 raw_tag)
5683{
5684 u32 tag_index;
5685 struct CommandList *c;
5686
f2405db8 5687 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 5688 if (!bad_tag(h, tag_index, raw_tag)) {
5689 c = h->cmd_pool + tag_index;
5690 finish_cmd(c);
5691 }
303932fd
DB		 5692}
5693
64670ac8
SC		 5694/* Some controllers, like p400, will give us one interrupt
5695 * after a soft reset, even if we turned interrupts off.
5696 * Only need to check for this in the hpsa_xxx_discard_completions
5697 * functions.
5698 */
5699static int ignore_bogus_interrupt(struct ctlr_info *h)
5700{
5701 if (likely(!reset_devices))
5702 return 0;
5703
5704 if (likely(h->interrupts_enabled))
5705 return 0;
5706
5707 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5708 "(known firmware bug.) Ignoring.\n");
5709
5710 return 1;
5711}
5712
254f796b
MG		 5713/*
5714 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5715 * Relies on (h-q[x] == x) being true for x such that
5716 * 0 <= x < MAX_REPLY_QUEUES.
5717 */
5718static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5719{
254f796b
MG		 5720 return container_of((queue - *queue), struct ctlr_info, q[0]);
5721}
5722
5723static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5724{
5725 struct ctlr_info *h = queue_to_hba(queue);
5726 u8 q = *(u8 *) queue;
64670ac8
SC		 5727 u32 raw_tag;
5728
5729 if (ignore_bogus_interrupt(h))
5730 return IRQ_NONE;
5731
5732 if (interrupt_not_for_us(h))
5733 return IRQ_NONE;
a0c12413 5734 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5735 while (interrupt_pending(h)) {
254f796b 5736 raw_tag = get_next_completion(h, q);
64670ac8 5737 while (raw_tag != FIFO_EMPTY)
254f796b 5738 raw_tag = next_command(h, q);
64670ac8 5739 }
64670ac8
SC		 5740 return IRQ_HANDLED;
5741}
5742
254f796b 5743static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5744{
254f796b 5745 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5746 u32 raw_tag;
254f796b 5747 u8 q = *(u8 *) queue;
64670ac8
SC		 5748
5749 if (ignore_bogus_interrupt(h))
5750 return IRQ_NONE;
5751
a0c12413 5752 h->last_intr_timestamp = get_jiffies_64();
254f796b 5753 raw_tag = get_next_completion(h, q);
64670ac8 5754 while (raw_tag != FIFO_EMPTY)
254f796b 5755 raw_tag = next_command(h, q);
64670ac8
SC		 5756 return IRQ_HANDLED;
5757}
5758
254f796b 5759static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5760{
254f796b 5761 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5762 u32 raw_tag;
254f796b 5763 u8 q = *(u8 *) queue;
edd16368
SC		 5764
5765 if (interrupt_not_for_us(h))
5766 return IRQ_NONE;
a0c12413 5767 h->last_intr_timestamp = get_jiffies_64();
10f66018 5768 while (interrupt_pending(h)) {
254f796b 5769 raw_tag = get_next_completion(h, q);
10f66018 5770 while (raw_tag != FIFO_EMPTY) {
f2405db8 5771 process_indexed_cmd(h, raw_tag);
254f796b 5772 raw_tag = next_command(h, q);
10f66018
SC		 5773 }
5774 }
10f66018
SC		 5775 return IRQ_HANDLED;
5776}
5777
254f796b 5778static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5779{
254f796b 5780 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5781 u32 raw_tag;
254f796b 5782 u8 q = *(u8 *) queue;
10f66018 5783
a0c12413 5784 h->last_intr_timestamp = get_jiffies_64();
254f796b 5785 raw_tag = get_next_completion(h, q);
303932fd 5786 while (raw_tag != FIFO_EMPTY) {
f2405db8 5787 process_indexed_cmd(h, raw_tag);
254f796b 5788 raw_tag = next_command(h, q);
edd16368 5789 }
edd16368
SC		 5790 return IRQ_HANDLED;
5791}
5792
a9a3a273
SC		 5793/* Send a message CDB to the firmware. Careful, this only works
5794 * in simple mode, not performant mode due to the tag lookup.
5795 * We only ever use this immediately after a controller reset.
5796 */
6f039790
GKH		 5797static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5798 unsigned char type)
edd16368
SC		 5799{
5800 struct Command {
5801 struct CommandListHeader CommandHeader;
5802 struct RequestBlock Request;
5803 struct ErrDescriptor ErrorDescriptor;
5804 };
5805 struct Command *cmd;
5806 static const size_t cmd_sz = sizeof(*cmd) +
5807 sizeof(cmd->ErrorDescriptor);
5808 dma_addr_t paddr64;
2b08b3e9
DB		 5809 __le32 paddr32;
5810 u32 tag;
edd16368
SC		 5811 void __iomem *vaddr;
5812 int i, err;
5813
5814 vaddr = pci_ioremap_bar(pdev, 0);
5815 if (vaddr == NULL)
5816 return -ENOMEM;
5817
5818 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5819 * CCISS commands, so they must be allocated from the lower 4GiB of
5820 * memory.
5821 */
5822 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5823 if (err) {
5824 iounmap(vaddr);
1eaec8f3 5825 return err;
edd16368
SC		 5826 }
5827
5828 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5829 if (cmd == NULL) {
5830 iounmap(vaddr);
5831 return -ENOMEM;
5832 }
5833
5834 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5835 * although there's no guarantee, we assume that the address is at
5836 * least 4-byte aligned (most likely, it's page-aligned).
5837 */
2b08b3e9 5838 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 5839
5840 cmd->CommandHeader.ReplyQueue = 0;
5841 cmd->CommandHeader.SGList = 0;
50a0decf 5842 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 5843 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 5844 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5845
5846 cmd->Request.CDBLen = 16;
a505b86f
SC		 5847 cmd->Request.type_attr_dir =
5848 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 5849 cmd->Request.Timeout = 0; /* Don't time out */
5850 cmd->Request.CDB[0] = opcode;
5851 cmd->Request.CDB[1] = type;
5852 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 5853 cmd->ErrorDescriptor.Addr =
2b08b3e9 5854 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 5855 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 5856
2b08b3e9 5857 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 5858
5859 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5860 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 5861 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 5862 break;
5863 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5864 }
5865
5866 iounmap(vaddr);
5867
5868 /* we leak the DMA buffer here ... no choice since the controller could
5869 * still complete the command.
5870 */
5871 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5872 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5873 opcode, type);
5874 return -ETIMEDOUT;
5875 }
5876
5877 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5878
5879 if (tag & HPSA_ERROR_BIT) {
5880 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5881 opcode, type);
5882 return -EIO;
5883 }
5884
5885 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5886 opcode, type);
5887 return 0;
5888}
5889
edd16368
SC		 5890#define hpsa_noop(p) hpsa_message(p, 3, 0)
5891
1df8552a 5892static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 5893 void __iomem *vaddr, u32 use_doorbell)
1df8552a 5894{
1df8552a
SC		 5895
5896 if (use_doorbell) {
5897 /* For everything after the P600, the PCI power state method
5898 * of resetting the controller doesn't work, so we have this
5899 * other way using the doorbell register.
5900 */
5901 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5902 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 5903
00701a96 5904 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 5905 * doorbell reset and before any attempt to talk to the board
5906 * at all to ensure that this actually works and doesn't fall
5907 * over in some weird corner cases.
5908 */
00701a96 5909 msleep(10000);
1df8552a
SC		 5910 } else { /* Try to do it the PCI power state way */
5911
5912 /* Quoting from the Open CISS Specification: "The Power
5913 * Management Control/Status Register (CSR) controls the power
5914 * state of the device. The normal operating state is D0,
5915 * CSR=00h. The software off state is D3, CSR=03h. To reset
5916 * the controller, place the interface device in D3 then to D0,
5917 * this causes a secondary PCI reset which will reset the
5918 * controller." */
2662cab8
DB		 5919
5920 int rc = 0;
5921
1df8552a 5922 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 5923
1df8552a 5924 /* enter the D3hot power management state */
2662cab8
DB		 5925 rc = pci_set_power_state(pdev, PCI_D3hot);
5926 if (rc)
5927 return rc;
1df8552a
SC		 5928
5929 msleep(500);
5930
5931 /* enter the D0 power management state */
2662cab8
DB		 5932 rc = pci_set_power_state(pdev, PCI_D0);
5933 if (rc)
5934 return rc;
c4853efe
MM		 5935
5936 /*
5937 * The P600 requires a small delay when changing states.
5938 * Otherwise we may think the board did not reset and we bail.
5939 * This for kdump only and is particular to the P600.
5940 */
5941 msleep(500);
1df8552a
SC		 5942 }
5943 return 0;
5944}
5945
6f039790 5946static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5947{
5948 memset(driver_version, 0, len);
f79cfec6 5949 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5950}
5951
6f039790 5952static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5953{
5954 char *driver_version;
5955 int i, size = sizeof(cfgtable->driver_version);
5956
5957 driver_version = kmalloc(size, GFP_KERNEL);
5958 if (!driver_version)
5959 return -ENOMEM;
5960
5961 init_driver_version(driver_version, size);
5962 for (i = 0; i < size; i++)
5963 writeb(driver_version[i], &cfgtable->driver_version[i]);
5964 kfree(driver_version);
5965 return 0;
5966}
5967
6f039790
GKH		 5968static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5969 unsigned char *driver_ver)
580ada3c
SC		 5970{
5971 int i;
5972
5973 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5974 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5975}
5976
6f039790 5977static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5978{
5979
5980 char *driver_ver, *old_driver_ver;
5981 int rc, size = sizeof(cfgtable->driver_version);
5982
5983 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5984 if (!old_driver_ver)
5985 return -ENOMEM;
5986 driver_ver = old_driver_ver + size;
5987
5988 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5989 * should have been changed, otherwise we know the reset failed.
5990 */
5991 init_driver_version(old_driver_ver, size);
5992 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5993 rc = !memcmp(driver_ver, old_driver_ver, size);
5994 kfree(old_driver_ver);
5995 return rc;
5996}
edd16368 5997/* This does a hard reset of the controller using PCI power management
1df8552a 5998 * states or the using the doorbell register.
edd16368 5999 */
6b6c1cd7 6000static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 6001{
1df8552a
SC		 6002 u64 cfg_offset;
6003 u32 cfg_base_addr;
6004 u64 cfg_base_addr_index;
6005 void __iomem *vaddr;
6006 unsigned long paddr;
580ada3c 6007 u32 misc_fw_support;
270d05de 6008 int rc;
1df8552a 6009 struct CfgTable __iomem *cfgtable;
cf0b08d0 6010 u32 use_doorbell;
270d05de 6011 u16 command_register;
edd16368 6012
1df8552a
SC		 6013 /* For controllers as old as the P600, this is very nearly
6014 * the same thing as
edd16368
SC		 6015 *
6016 * pci_save_state(pci_dev);
6017 * pci_set_power_state(pci_dev, PCI_D3hot);
6018 * pci_set_power_state(pci_dev, PCI_D0);
6019 * pci_restore_state(pci_dev);
6020 *
1df8552a
SC		 6021 * For controllers newer than the P600, the pci power state
6022 * method of resetting doesn't work so we have another way
6023 * using the doorbell register.
edd16368 6024 */
18867659 6025
60f923b9
RE		 6026 if (!ctlr_is_resettable(board_id)) {
6027 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 6028 return -ENODEV;
6029 }
46380786
SC		 6030
6031 /* if controller is soft- but not hard resettable... */
6032 if (!ctlr_is_hard_resettable(board_id))
6033 return -ENOTSUPP; /* try soft reset later. */
18867659 6034
270d05de
SC		 6035 /* Save the PCI command register */
6036 pci_read_config_word(pdev, 4, &command_register);
270d05de 6037 pci_save_state(pdev);
edd16368 6038
1df8552a
SC		 6039 /* find the first memory BAR, so we can find the cfg table */
6040 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6041 if (rc)
6042 return rc;
6043 vaddr = remap_pci_mem(paddr, 0x250);
6044 if (!vaddr)
6045 return -ENOMEM;
edd16368 6046
1df8552a
SC		 6047 /* find cfgtable in order to check if reset via doorbell is supported */
6048 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6049 &cfg_base_addr_index, &cfg_offset);
6050 if (rc)
6051 goto unmap_vaddr;
6052 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6053 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6054 if (!cfgtable) {
6055 rc = -ENOMEM;
6056 goto unmap_vaddr;
6057 }
580ada3c
SC		 6058 rc = write_driver_ver_to_cfgtable(cfgtable);
6059 if (rc)
03741d95 6060 goto unmap_cfgtable;
edd16368 6061
cf0b08d0
SC		 6062 /* If reset via doorbell register is supported, use that.
6063 * There are two such methods. Favor the newest method.
6064 */
1df8552a 6065 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6066 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6067 if (use_doorbell) {
6068 use_doorbell = DOORBELL_CTLR_RESET2;
6069 } else {
6070 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6071 if (use_doorbell) {
050f7147
SC		 6072 dev_warn(&pdev->dev,
6073 "Soft reset not supported. Firmware update is required.\n");
64670ac8 6074 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6075 goto unmap_cfgtable;
6076 }
6077 }
edd16368 6078
1df8552a
SC		 6079 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6080 if (rc)
6081 goto unmap_cfgtable;
edd16368 6082
270d05de 6083 pci_restore_state(pdev);
270d05de 6084 pci_write_config_word(pdev, 4, command_register);
edd16368 6085
1df8552a
SC		 6086 /* Some devices (notably the HP Smart Array 5i Controller)
6087 need a little pause here */
6088 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6089
fe5389c8
SC		 6090 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6091 if (rc) {
6092 dev_warn(&pdev->dev,
050f7147 6093 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 6094 goto unmap_cfgtable;
6095 }
fe5389c8 6096
580ada3c
SC		 6097 rc = controller_reset_failed(vaddr);
6098 if (rc < 0)
6099 goto unmap_cfgtable;
6100 if (rc) {
64670ac8
SC		 6101 dev_warn(&pdev->dev, "Unable to successfully reset "
6102 "controller. Will try soft reset.\n");
6103 rc = -ENOTSUPP;
580ada3c 6104 } else {
64670ac8 6105 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6106 }
6107
6108unmap_cfgtable:
6109 iounmap(cfgtable);
6110
6111unmap_vaddr:
6112 iounmap(vaddr);
6113 return rc;
edd16368
SC		 6114}
6115
6116/*
6117 * We cannot read the structure directly, for portability we must use
6118 * the io functions.
6119 * This is for debug only.
6120 */
42a91641 6121static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 6122{
58f8665c 6123#ifdef HPSA_DEBUG
edd16368
SC		 6124 int i;
6125 char temp_name[17];
6126
6127 dev_info(dev, "Controller Configuration information\n");
6128 dev_info(dev, "------------------------------------\n");
6129 for (i = 0; i < 4; i++)
6130 temp_name[i] = readb(&(tb->Signature[i]));
6131 temp_name[4] = '\0';
6132 dev_info(dev, " Signature = %s\n", temp_name);
6133 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6134 dev_info(dev, " Transport methods supported = 0x%x\n",
6135 readl(&(tb->TransportSupport)));
6136 dev_info(dev, " Transport methods active = 0x%x\n",
6137 readl(&(tb->TransportActive)));
6138 dev_info(dev, " Requested transport Method = 0x%x\n",
6139 readl(&(tb->HostWrite.TransportRequest)));
6140 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6141 readl(&(tb->HostWrite.CoalIntDelay)));
6142 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6143 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 6144 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 6145 readl(&(tb->CmdsOutMax)));
6146 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6147 for (i = 0; i < 16; i++)
6148 temp_name[i] = readb(&(tb->ServerName[i]));
6149 temp_name[16] = '\0';
6150 dev_info(dev, " Server Name = %s\n", temp_name);
6151 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6152 readl(&(tb->HeartBeat)));
edd16368 6153#endif /* HPSA_DEBUG */
58f8665c 6154}
edd16368
SC		 6155
6156static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6157{
6158 int i, offset, mem_type, bar_type;
6159
6160 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6161 return 0;
6162 offset = 0;
6163 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6164 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6165 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6166 offset += 4;
6167 else {
6168 mem_type = pci_resource_flags(pdev, i) &
6169 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6170 switch (mem_type) {
6171 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6172 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6173 offset += 4; /* 32 bit */
6174 break;
6175 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6176 offset += 8;
6177 break;
6178 default: /* reserved in PCI 2.2 */
6179 dev_warn(&pdev->dev,
6180 "base address is invalid\n");
6181 return -1;
6182 break;
6183 }
6184 }
6185 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6186 return i + 1;
6187 }
6188 return -1;
6189}
6190
6191/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 6192 * controllers that are capable. If not, we use legacy INTx mode.
edd16368
SC		 6193 */
6194
6f039790 6195static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6196{
6197#ifdef CONFIG_PCI_MSI
254f796b
MG		 6198 int err, i;
6199 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6200
6201 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6202 hpsa_msix_entries[i].vector = 0;
6203 hpsa_msix_entries[i].entry = i;
6204 }
edd16368
SC		 6205
6206 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6207 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6208 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6209 goto default_int_mode;
55c06c71 6210 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 6211 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 6212 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 6213 if (h->msix_vector > num_online_cpus())
6214 h->msix_vector = num_online_cpus();
18fce3c4
AG		 6215 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
6216 1, h->msix_vector);
6217 if (err < 0) {
6218 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
6219 h->msix_vector = 0;
6220 goto single_msi_mode;
6221 } else if (err < h->msix_vector) {
55c06c71 6222 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 6223 "available\n", err);
edd16368 6224 }
18fce3c4
AG		 6225 h->msix_vector = err;
6226 for (i = 0; i < h->msix_vector; i++)
6227 h->intr[i] = hpsa_msix_entries[i].vector;
6228 return;
edd16368 6229 }
18fce3c4 6230single_msi_mode:
55c06c71 6231 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 6232 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 6233 if (!pci_enable_msi(h->pdev))
edd16368
SC		 6234 h->msi_vector = 1;
6235 else
55c06c71 6236 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 6237 }
6238default_int_mode:
6239#endif /* CONFIG_PCI_MSI */
6240 /* if we get here we're going to use the default interrupt mode */
a9a3a273 6241 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 6242}
6243
6f039790 6244static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 6245{
6246 int i;
6247 u32 subsystem_vendor_id, subsystem_device_id;
6248
6249 subsystem_vendor_id = pdev->subsystem_vendor;
6250 subsystem_device_id = pdev->subsystem_device;
6251 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
6252 subsystem_vendor_id;
6253
6254 for (i = 0; i < ARRAY_SIZE(products); i++)
6255 if (*board_id == products[i].board_id)
6256 return i;
6257
6798cc0a
SC		 6258 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
6259 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
6260 !hpsa_allow_any) {
e5c880d1
SC		 6261 dev_warn(&pdev->dev, "unrecognized board ID: "
6262 "0x%08x, ignoring.\n", *board_id);
6263 return -ENODEV;
6264 }
6265 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
6266}
6267
6f039790
GKH		 6268static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
6269 unsigned long *memory_bar)
3a7774ce
SC		 6270{
6271 int i;
6272
6273 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 6274 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 6275 /* addressing mode bits already removed */
12d2cd47
SC		 6276 *memory_bar = pci_resource_start(pdev, i);
6277 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 6278 *memory_bar);
6279 return 0;
6280 }
12d2cd47 6281 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 6282 return -ENODEV;
6283}
6284
6f039790
GKH		 6285static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
6286 int wait_for_ready)
2c4c8c8b 6287{
fe5389c8 6288 int i, iterations;
2c4c8c8b 6289 u32 scratchpad;
fe5389c8
SC		 6290 if (wait_for_ready)
6291 iterations = HPSA_BOARD_READY_ITERATIONS;
6292 else
6293 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 6294
fe5389c8
SC		 6295 for (i = 0; i < iterations; i++) {
6296 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
6297 if (wait_for_ready) {
6298 if (scratchpad == HPSA_FIRMWARE_READY)
6299 return 0;
6300 } else {
6301 if (scratchpad != HPSA_FIRMWARE_READY)
6302 return 0;
6303 }
2c4c8c8b
SC		 6304 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
6305 }
fe5389c8 6306 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 6307 return -ENODEV;
6308}
6309
6f039790
GKH		 6310static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
6311 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
6312 u64 *cfg_offset)
a51fd47f
SC		 6313{
6314 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
6315 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
6316 *cfg_base_addr &= (u32) 0x0000ffff;
6317 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
6318 if (*cfg_base_addr_index == -1) {
6319 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
6320 return -ENODEV;
6321 }
6322 return 0;
6323}
6324
6f039790 6325static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 6326{
01a02ffc
SC		 6327 u64 cfg_offset;
6328 u32 cfg_base_addr;
6329 u64 cfg_base_addr_index;
303932fd 6330 u32 trans_offset;
a51fd47f 6331 int rc;
77c4495c 6332
a51fd47f
SC		 6333 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6334 &cfg_base_addr_index, &cfg_offset);
6335 if (rc)
6336 return rc;
77c4495c 6337 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 6338 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 6339 if (!h->cfgtable) {
6340 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 6341 return -ENOMEM;
cd3c81c4 6342 }
580ada3c
SC		 6343 rc = write_driver_ver_to_cfgtable(h->cfgtable);
6344 if (rc)
6345 return rc;
77c4495c 6346 /* Find performant mode table. */
a51fd47f 6347 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 6348 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
6349 cfg_base_addr_index)+cfg_offset+trans_offset,
6350 sizeof(*h->transtable));
6351 if (!h->transtable)
6352 return -ENOMEM;
6353 return 0;
6354}
6355
6f039790 6356static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 6357{
41ce4c35
SC		 6358#define MIN_MAX_COMMANDS 16
6359 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
6360
6361 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 6362
6363 /* Limit commands in memory limited kdump scenario. */
6364 if (reset_devices && h->max_commands > 32)
6365 h->max_commands = 32;
6366
41ce4c35
SC		 6367 if (h->max_commands < MIN_MAX_COMMANDS) {
6368 dev_warn(&h->pdev->dev,
6369 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
6370 h->max_commands,
6371 MIN_MAX_COMMANDS);
6372 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 6373 }
6374}
6375
c7ee65b3
WS		 6376/* If the controller reports that the total max sg entries is greater than 512,
6377 * then we know that chained SG blocks work. (Original smart arrays did not
6378 * support chained SG blocks and would return zero for max sg entries.)
6379 */
6380static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
6381{
6382 return h->maxsgentries > 512;
6383}
6384
b93d7536
SC		 6385/* Interrogate the hardware for some limits:
6386 * max commands, max SG elements without chaining, and with chaining,
6387 * SG chain block size, etc.
6388 */
6f039790 6389static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 6390{
cba3d38b 6391 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 6392 h->nr_cmds = h->max_commands;
b93d7536 6393 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 6394 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 6395 if (hpsa_supports_chained_sg_blocks(h)) {
6396 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 6397 h->max_cmd_sg_entries = 32;
1a63ea6f 6398 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 6399 h->maxsgentries--; /* save one for chain pointer */
6400 } else {
c7ee65b3
WS		 6401 /*
6402 * Original smart arrays supported at most 31 s/g entries
6403 * embedded inline in the command (trying to use more
6404 * would lock up the controller)
6405 */
6406 h->max_cmd_sg_entries = 31;
1a63ea6f 6407 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 6408 h->chainsize = 0;
b93d7536 6409 }
75167d2c
SC		 6410
6411 /* Find out what task management functions are supported and cache */
6412 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 6413 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
6414 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
6415 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6416 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 6417}
6418
76c46e49
SC		 6419static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
6420{
0fc9fd40 6421 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 6422 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 6423 return false;
6424 }
6425 return true;
6426}
6427
97a5e98c 6428static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 6429{
97a5e98c 6430 u32 driver_support;
f7c39101 6431
97a5e98c 6432 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 6433 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
6434#ifdef CONFIG_X86
97a5e98c 6435 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 6436#endif
28e13446
SC		 6437 driver_support |= ENABLE_UNIT_ATTN;
6438 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 6439}
6440
3d0eab67
SC		 6441/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
6442 * in a prefetch beyond physical memory.
6443 */
6444static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
6445{
6446 u32 dma_prefetch;
6447
6448 if (h->board_id != 0x3225103C)
6449 return;
6450 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
6451 dma_prefetch |= 0x8000;
6452 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
6453}
6454
c706a795 6455static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 6456{
6457 int i;
6458 u32 doorbell_value;
6459 unsigned long flags;
6460 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 6461 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 6462 spin_lock_irqsave(&h->lock, flags);
6463 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6464 spin_unlock_irqrestore(&h->lock, flags);
6465 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 6466 goto done;
76438d08 6467 /* delay and try again */
007e7aa9 6468 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 6469 }
c706a795
RE		 6470 return -ENODEV;
6471done:
6472 return 0;
76438d08
SC		 6473}
6474
c706a795 6475static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 6476{
6477 int i;
6eaf46fd
SC		 6478 u32 doorbell_value;
6479 unsigned long flags;
eb6b2ae9
SC		 6480
6481 /* under certain very rare conditions, this can take awhile.
6482 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
6483 * as we enter this code.)
6484 */
007e7aa9 6485 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 6486 if (h->remove_in_progress)
6487 goto done;
6eaf46fd
SC		 6488 spin_lock_irqsave(&h->lock, flags);
6489 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6490 spin_unlock_irqrestore(&h->lock, flags);
382be668 6491 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 6492 goto done;
eb6b2ae9 6493 /* delay and try again */
007e7aa9 6494 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 6495 }
c706a795
RE		 6496 return -ENODEV;
6497done:
6498 return 0;
3f4336f3
SC		 6499}
6500
c706a795 6501/* return -ENODEV or other reason on error, 0 on success */
6f039790 6502static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6503{
6504 u32 trans_support;
6505
6506 trans_support = readl(&(h->cfgtable->TransportSupport));
6507 if (!(trans_support & SIMPLE_MODE))
6508 return -ENOTSUPP;
6509
6510 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6511
3f4336f3
SC		 6512 /* Update the field, and then ring the doorbell */
6513 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6514 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 6515 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 6516 if (hpsa_wait_for_mode_change_ack(h))
6517 goto error;
eb6b2ae9 6518 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6519 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6520 goto error;
960a30e7 6521 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6522 return 0;
283b4a9b 6523error:
050f7147 6524 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 6525 return -ENODEV;
eb6b2ae9
SC		 6526}
6527
6f039790 6528static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6529{
eb6b2ae9 6530 int prod_index, err;
edd16368 6531
e5c880d1
SC		 6532 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6533 if (prod_index < 0)
60f923b9 6534 return prod_index;
e5c880d1
SC		 6535 h->product_name = products[prod_index].product_name;
6536 h->access = *(products[prod_index].access);
edd16368 6537
9b5c48c2
SC		 6538 h->needs_abort_tags_swizzled =
6539 ctlr_needs_abort_tags_swizzled(h->board_id);
6540
e5a44df8
MG		 6541 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6542 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6543
55c06c71 6544 err = pci_enable_device(h->pdev);
edd16368 6545 if (err) {
55c06c71 6546 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 6547 return err;
6548 }
6549
f79cfec6 6550 err = pci_request_regions(h->pdev, HPSA);
edd16368 6551 if (err) {
55c06c71
SC		 6552 dev_err(&h->pdev->dev,
6553 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 6554 return err;
6555 }
4fa604e1
RE		 6556
6557 pci_set_master(h->pdev);
6558
6b3f4c52 6559 hpsa_interrupt_mode(h);
12d2cd47 6560 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6561 if (err)
edd16368 6562 goto err_out_free_res;
edd16368 6563 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 6564 if (!h->vaddr) {
6565 err = -ENOMEM;
6566 goto err_out_free_res;
6567 }
fe5389c8 6568 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6569 if (err)
edd16368 6570 goto err_out_free_res;
77c4495c
SC		 6571 err = hpsa_find_cfgtables(h);
6572 if (err)
edd16368 6573 goto err_out_free_res;
b93d7536 6574 hpsa_find_board_params(h);
edd16368 6575
76c46e49 6576 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 6577 err = -ENODEV;
6578 goto err_out_free_res;
6579 }
97a5e98c 6580 hpsa_set_driver_support_bits(h);
3d0eab67 6581 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6582 err = hpsa_enter_simple_mode(h);
6583 if (err)
edd16368 6584 goto err_out_free_res;
edd16368
SC		 6585 return 0;
6586
6587err_out_free_res:
204892e9
SC		 6588 if (h->transtable)
6589 iounmap(h->transtable);
6590 if (h->cfgtable)
6591 iounmap(h->cfgtable);
6592 if (h->vaddr)
6593 iounmap(h->vaddr);
f0bd0b68 6594 pci_disable_device(h->pdev);
55c06c71 6595 pci_release_regions(h->pdev);
edd16368
SC		 6596 return err;
6597}
6598
6f039790 6599static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6600{
6601 int rc;
6602
6603#define HBA_INQUIRY_BYTE_COUNT 64
6604 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6605 if (!h->hba_inquiry_data)
6606 return;
6607 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6608 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6609 if (rc != 0) {
6610 kfree(h->hba_inquiry_data);
6611 h->hba_inquiry_data = NULL;
6612 }
6613}
6614
6b6c1cd7 6615static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 6616{
1df8552a 6617 int rc, i;
3b747298 6618 void __iomem *vaddr;
4c2a8c40
SC		 6619
6620 if (!reset_devices)
6621 return 0;
6622
132aa220
TH		 6623 /* kdump kernel is loading, we don't know in which state is
6624 * the pci interface. The dev->enable_cnt is equal zero
6625 * so we call enable+disable, wait a while and switch it on.
6626 */
6627 rc = pci_enable_device(pdev);
6628 if (rc) {
6629 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
6630 return -ENODEV;
6631 }
6632 pci_disable_device(pdev);
6633 msleep(260); /* a randomly chosen number */
6634 rc = pci_enable_device(pdev);
6635 if (rc) {
6636 dev_warn(&pdev->dev, "failed to enable device.\n");
6637 return -ENODEV;
6638 }
4fa604e1 6639
859c75ab 6640 pci_set_master(pdev);
4fa604e1 6641
3b747298
TH		 6642 vaddr = pci_ioremap_bar(pdev, 0);
6643 if (vaddr == NULL) {
6644 rc = -ENOMEM;
6645 goto out_disable;
6646 }
6647 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
6648 iounmap(vaddr);
6649
1df8552a 6650 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 6651 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 6652
1df8552a
SC		 6653 /* -ENOTSUPP here means we cannot reset the controller
6654 * but it's already (and still) up and running in
18867659
SC		 6655 * "performant mode". Or, it might be 640x, which can't reset
6656 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 6657 */
adf1b3a3 6658 if (rc)
132aa220 6659 goto out_disable;
4c2a8c40
SC		 6660
6661 /* Now try to get the controller to respond to a no-op */
1ba66c9c 6662 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6663 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6664 if (hpsa_noop(pdev) == 0)
6665 break;
6666 else
6667 dev_warn(&pdev->dev, "no-op failed%s\n",
6668 (i < 11 ? "; re-trying" : ""));
6669 }
132aa220
TH		 6670
6671out_disable:
6672
6673 pci_disable_device(pdev);
6674 return rc;
4c2a8c40
SC		 6675}
6676
6f039790 6677static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6678{
6679 h->cmd_pool_bits = kzalloc(
6680 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6681 sizeof(unsigned long), GFP_KERNEL);
6682 h->cmd_pool = pci_alloc_consistent(h->pdev,
6683 h->nr_cmds * sizeof(*h->cmd_pool),
6684 &(h->cmd_pool_dhandle));
6685 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6686 h->nr_cmds * sizeof(*h->errinfo_pool),
6687 &(h->errinfo_pool_dhandle));
6688 if ((h->cmd_pool_bits == NULL)
6689 || (h->cmd_pool == NULL)
6690 || (h->errinfo_pool == NULL)) {
6691 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 6692 goto clean_up;
2e9d1b36
SC		 6693 }
6694 return 0;
2c143342
RE		 6695clean_up:
6696 hpsa_free_cmd_pool(h);
6697 return -ENOMEM;
2e9d1b36
SC		 6698}
6699
6700static void hpsa_free_cmd_pool(struct ctlr_info *h)
6701{
6702 kfree(h->cmd_pool_bits);
6703 if (h->cmd_pool)
6704 pci_free_consistent(h->pdev,
6705 h->nr_cmds * sizeof(struct CommandList),
6706 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 6707 if (h->ioaccel2_cmd_pool)
6708 pci_free_consistent(h->pdev,
6709 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6710 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 6711 if (h->errinfo_pool)
6712 pci_free_consistent(h->pdev,
6713 h->nr_cmds * sizeof(struct ErrorInfo),
6714 h->errinfo_pool,
6715 h->errinfo_pool_dhandle);
e1f7de0c
MG		 6716 if (h->ioaccel_cmd_pool)
6717 pci_free_consistent(h->pdev,
6718 h->nr_cmds * sizeof(struct io_accel1_cmd),
6719 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 6720}
6721
41b3cf08
SC		 6722static void hpsa_irq_affinity_hints(struct ctlr_info *h)
6723{
ec429952 6724 int i, cpu;
41b3cf08
SC		 6725
6726 cpu = cpumask_first(cpu_online_mask);
6727 for (i = 0; i < h->msix_vector; i++) {
ec429952 6728 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 6729 cpu = cpumask_next(cpu, cpu_online_mask);
6730 }
6731}
6732
ec501a18
RE		 6733/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
6734static void hpsa_free_irqs(struct ctlr_info *h)
6735{
6736 int i;
6737
6738 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6739 /* Single reply queue, only one irq to free */
6740 i = h->intr_mode;
6741 irq_set_affinity_hint(h->intr[i], NULL);
6742 free_irq(h->intr[i], &h->q[i]);
6743 return;
6744 }
6745
6746 for (i = 0; i < h->msix_vector; i++) {
6747 irq_set_affinity_hint(h->intr[i], NULL);
6748 free_irq(h->intr[i], &h->q[i]);
6749 }
a4e17fc1
RE		 6750 for (; i < MAX_REPLY_QUEUES; i++)
6751 h->q[i] = 0;
ec501a18
RE		 6752}
6753
9ee61794
RE		 6754/* returns 0 on success; cleans up and returns -Enn on error */
6755static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 6756 irqreturn_t (*msixhandler)(int, void *),
6757 irqreturn_t (*intxhandler)(int, void *))
6758{
254f796b 6759 int rc, i;
0ae01a32 6760
254f796b
MG		 6761 /*
6762 * initialize h->q[x] = x so that interrupt handlers know which
6763 * queue to process.
6764 */
6765 for (i = 0; i < MAX_REPLY_QUEUES; i++)
6766 h->q[i] = (u8) i;
6767
eee0f03a 6768 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 6769 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 6770 for (i = 0; i < h->msix_vector; i++) {
254f796b
MG		 6771 rc = request_irq(h->intr[i], msixhandler,
6772 0, h->devname,
6773 &h->q[i]);
a4e17fc1
RE		 6774 if (rc) {
6775 int j;
6776
6777 dev_err(&h->pdev->dev,
6778 "failed to get irq %d for %s\n",
6779 h->intr[i], h->devname);
6780 for (j = 0; j < i; j++) {
6781 free_irq(h->intr[j], &h->q[j]);
6782 h->q[j] = 0;
6783 }
6784 for (; j < MAX_REPLY_QUEUES; j++)
6785 h->q[j] = 0;
6786 return rc;
6787 }
6788 }
41b3cf08 6789 hpsa_irq_affinity_hints(h);
254f796b
MG		 6790 } else {
6791 /* Use single reply pool */
eee0f03a 6792 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 6793 rc = request_irq(h->intr[h->intr_mode],
6794 msixhandler, 0, h->devname,
6795 &h->q[h->intr_mode]);
6796 } else {
6797 rc = request_irq(h->intr[h->intr_mode],
6798 intxhandler, IRQF_SHARED, h->devname,
6799 &h->q[h->intr_mode]);
6800 }
6801 }
0ae01a32
SC		 6802 if (rc) {
6803 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
6804 h->intr[h->intr_mode], h->devname);
6805 return -ENODEV;
6806 }
6807 return 0;
6808}
6809
6f039790 6810static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 6811{
6812 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6813 HPSA_RESET_TYPE_CONTROLLER)) {
6814 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6815 return -EIO;
6816 }
6817
6818 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6819 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6820 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6821 return -1;
6822 }
6823
6824 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6825 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
6826 dev_warn(&h->pdev->dev, "Board failed to become ready "
6827 "after soft reset.\n");
6828 return -1;
6829 }
6830
6831 return 0;
6832}
6833
0097f0f4 6834static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 6835{
ec501a18 6836 hpsa_free_irqs(h);
64670ac8 6837#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6838 if (h->msix_vector) {
6839 if (h->pdev->msix_enabled)
6840 pci_disable_msix(h->pdev);
6841 } else if (h->msi_vector) {
6842 if (h->pdev->msi_enabled)
6843 pci_disable_msi(h->pdev);
6844 }
64670ac8 6845#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6846}
6847
072b0518
SC		 6848static void hpsa_free_reply_queues(struct ctlr_info *h)
6849{
6850 int i;
6851
6852 for (i = 0; i < h->nreply_queues; i++) {
6853 if (!h->reply_queue[i].head)
6854 continue;
6855 pci_free_consistent(h->pdev, h->reply_queue_size,
6856 h->reply_queue[i].head, h->reply_queue[i].busaddr);
6857 h->reply_queue[i].head = NULL;
6858 h->reply_queue[i].busaddr = 0;
6859 }
6860}
6861
0097f0f4
SC		 6862static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6863{
6864 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6865 hpsa_free_sg_chain_blocks(h);
6866 hpsa_free_cmd_pool(h);
e1f7de0c 6867 kfree(h->ioaccel1_blockFetchTable);
64670ac8 6868 kfree(h->blockFetchTable);
072b0518 6869 hpsa_free_reply_queues(h);
64670ac8
SC		 6870 if (h->vaddr)
6871 iounmap(h->vaddr);
6872 if (h->transtable)
6873 iounmap(h->transtable);
6874 if (h->cfgtable)
6875 iounmap(h->cfgtable);
132aa220 6876 pci_disable_device(h->pdev);
64670ac8
SC		 6877 pci_release_regions(h->pdev);
6878 kfree(h);
6879}
6880
a0c12413 6881/* Called when controller lockup detected. */
f2405db8 6882static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 6883{
281a7fd0
WS		 6884 int i, refcount;
6885 struct CommandList *c;
25163bd5 6886 int failcount = 0;
a0c12413 6887
080ef1cc 6888 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 6889 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 6890 c = h->cmd_pool + i;
281a7fd0
WS		 6891 refcount = atomic_inc_return(&c->refcount);
6892 if (refcount > 1) {
25163bd5 6893 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 6894 finish_cmd(c);
25163bd5 6895 failcount++;
281a7fd0
WS		 6896 }
6897 cmd_free(h, c);
a0c12413 6898 }
25163bd5
WS		 6899 dev_warn(&h->pdev->dev,
6900 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 6901}
6902
094963da
SC		 6903static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
6904{
c8ed0010 6905 int cpu;
094963da 6906
c8ed0010 6907 for_each_online_cpu(cpu) {
094963da
SC		 6908 u32 *lockup_detected;
6909 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
6910 *lockup_detected = value;
094963da
SC		 6911 }
6912 wmb(); /* be sure the per-cpu variables are out to memory */
6913}
6914
a0c12413
SC		 6915static void controller_lockup_detected(struct ctlr_info *h)
6916{
6917 unsigned long flags;
094963da 6918 u32 lockup_detected;
a0c12413 6919
a0c12413
SC		 6920 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6921 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 6922 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6923 if (!lockup_detected) {
6924 /* no heartbeat, but controller gave us a zero. */
6925 dev_warn(&h->pdev->dev,
25163bd5
WS		 6926 "lockup detected after %d but scratchpad register is zero\n",
6927 h->heartbeat_sample_interval / HZ);
094963da
SC		 6928 lockup_detected = 0xffffffff;
6929 }
6930 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 6931 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 6932 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
6933 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 6934 pci_disable_device(h->pdev);
f2405db8 6935 fail_all_outstanding_cmds(h);
a0c12413
SC		 6936}
6937
25163bd5 6938static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 6939{
6940 u64 now;
6941 u32 heartbeat;
6942 unsigned long flags;
6943
a0c12413
SC		 6944 now = get_jiffies_64();
6945 /* If we've received an interrupt recently, we're ok. */
6946 if (time_after64(h->last_intr_timestamp +
e85c5974 6947 (h->heartbeat_sample_interval), now))
25163bd5 6948 return false;
a0c12413
SC		 6949
6950 /*
6951 * If we've already checked the heartbeat recently, we're ok.
6952 * This could happen if someone sends us a signal. We
6953 * otherwise don't care about signals in this thread.
6954 */
6955 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6956 (h->heartbeat_sample_interval), now))
25163bd5 6957 return false;
a0c12413
SC		 6958
6959 /* If heartbeat has not changed since we last looked, we're not ok. */
6960 spin_lock_irqsave(&h->lock, flags);
6961 heartbeat = readl(&h->cfgtable->HeartBeat);
6962 spin_unlock_irqrestore(&h->lock, flags);
6963 if (h->last_heartbeat == heartbeat) {
6964 controller_lockup_detected(h);
25163bd5 6965 return true;
a0c12413
SC		 6966 }
6967
6968 /* We're ok. */
6969 h->last_heartbeat = heartbeat;
6970 h->last_heartbeat_timestamp = now;
25163bd5 6971 return false;
a0c12413
SC		 6972}
6973
9846590e 6974static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 6975{
6976 int i;
6977 char *event_type;
6978
e4aa3e6a
SC		 6979 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
6980 return;
6981
76438d08 6982 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6983 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6984 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6985 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6986 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6987
6988 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6989 event_type = "state change";
6990 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6991 event_type = "configuration change";
6992 /* Stop sending new RAID offload reqs via the IO accelerator */
6993 scsi_block_requests(h->scsi_host);
6994 for (i = 0; i < h->ndevices; i++)
6995 h->dev[i]->offload_enabled = 0;
23100dd9 6996 hpsa_drain_accel_commands(h);
76438d08
SC		 6997 /* Set 'accelerator path config change' bit */
6998 dev_warn(&h->pdev->dev,
6999 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7000 h->events, event_type);
7001 writel(h->events, &(h->cfgtable->clear_event_notify));
7002 /* Set the "clear event notify field update" bit 6 */
7003 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7004 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7005 hpsa_wait_for_clear_event_notify_ack(h);
7006 scsi_unblock_requests(h->scsi_host);
7007 } else {
7008 /* Acknowledge controller notification events. */
7009 writel(h->events, &(h->cfgtable->clear_event_notify));
7010 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7011 hpsa_wait_for_clear_event_notify_ack(h);
7012#if 0
7013 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7014 hpsa_wait_for_mode_change_ack(h);
7015#endif
7016 }
9846590e 7017 return;
76438d08
SC		 7018}
7019
7020/* Check a register on the controller to see if there are configuration
7021 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 7022 * we should rescan the controller for devices.
7023 * Also check flag for driver-initiated rescan.
76438d08 7024 */
9846590e 7025static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08
SC		 7026{
7027 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 7028 return 0;
76438d08
SC		 7029
7030 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 7031 return h->events & RESCAN_REQUIRED_EVENT_BITS;
7032}
76438d08 7033
9846590e
SC		 7034/*
7035 * Check if any of the offline devices have become ready
7036 */
7037static int hpsa_offline_devices_ready(struct ctlr_info *h)
7038{
7039 unsigned long flags;
7040 struct offline_device_entry *d;
7041 struct list_head *this, *tmp;
7042
7043 spin_lock_irqsave(&h->offline_device_lock, flags);
7044 list_for_each_safe(this, tmp, &h->offline_device_list) {
7045 d = list_entry(this, struct offline_device_entry,
7046 offline_list);
7047 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 7048 if (!hpsa_volume_offline(h, d->scsi3addr)) {
7049 spin_lock_irqsave(&h->offline_device_lock, flags);
7050 list_del(&d->offline_list);
7051 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 7052 return 1;
d1fea47c 7053 }
9846590e
SC		 7054 spin_lock_irqsave(&h->offline_device_lock, flags);
7055 }
7056 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7057 return 0;
76438d08
SC		 7058}
7059
6636e7f4 7060static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 7061{
7062 unsigned long flags;
8a98db73 7063 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 7064 struct ctlr_info, rescan_ctlr_work);
7065
7066
7067 if (h->remove_in_progress)
8a98db73 7068 return;
9846590e
SC		 7069
7070 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
7071 scsi_host_get(h->scsi_host);
9846590e
SC		 7072 hpsa_ack_ctlr_events(h);
7073 hpsa_scan_start(h->scsi_host);
7074 scsi_host_put(h->scsi_host);
7075 }
8a98db73 7076 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 7077 if (!h->remove_in_progress)
7078 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7079 h->heartbeat_sample_interval);
7080 spin_unlock_irqrestore(&h->lock, flags);
7081}
7082
7083static void hpsa_monitor_ctlr_worker(struct work_struct *work)
7084{
7085 unsigned long flags;
7086 struct ctlr_info *h = container_of(to_delayed_work(work),
7087 struct ctlr_info, monitor_ctlr_work);
7088
7089 detect_controller_lockup(h);
7090 if (lockup_detected(h))
a0c12413 7091 return;
6636e7f4
DB		 7092
7093 spin_lock_irqsave(&h->lock, flags);
7094 if (!h->remove_in_progress)
7095 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 7096 h->heartbeat_sample_interval);
7097 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 7098}
7099
6636e7f4
DB		 7100static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
7101 char *name)
7102{
7103 struct workqueue_struct *wq = NULL;
6636e7f4 7104
397ea9cb 7105 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 7106 if (!wq)
7107 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
7108
7109 return wq;
7110}
7111
6f039790 7112static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 7113{
4c2a8c40 7114 int dac, rc;
edd16368 7115 struct ctlr_info *h;
64670ac8
SC		 7116 int try_soft_reset = 0;
7117 unsigned long flags;
6b6c1cd7 7118 u32 board_id;
edd16368
SC		 7119
7120 if (number_of_controllers == 0)
7121 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 7122
6b6c1cd7
TH		 7123 rc = hpsa_lookup_board_id(pdev, &board_id);
7124 if (rc < 0) {
7125 dev_warn(&pdev->dev, "Board ID not found\n");
7126 return rc;
7127 }
7128
7129 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 7130 if (rc) {
7131 if (rc != -ENOTSUPP)
7132 return rc;
7133 /* If the reset fails in a particular way (it has no way to do
7134 * a proper hard reset, so returns -ENOTSUPP) we can try to do
7135 * a soft reset once we get the controller configured up to the
7136 * point that it can accept a command.
7137 */
7138 try_soft_reset = 1;
7139 rc = 0;
7140 }
7141
7142reinit_after_soft_reset:
edd16368 7143
303932fd
DB		 7144 /* Command structures must be aligned on a 32-byte boundary because
7145 * the 5 lower bits of the address are used by the hardware. and by
7146 * the driver. See comments in hpsa.h for more info.
7147 */
303932fd 7148 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 7149 h = kzalloc(sizeof(*h), GFP_KERNEL);
7150 if (!h)
ecd9aad4 7151 return -ENOMEM;
edd16368 7152
55c06c71 7153 h->pdev = pdev;
a9a3a273 7154 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 7155 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 7156 spin_lock_init(&h->lock);
9846590e 7157 spin_lock_init(&h->offline_device_lock);
6eaf46fd 7158 spin_lock_init(&h->scan_lock);
34f0c627 7159 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 7160 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da 7161
6636e7f4
DB		 7162 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
7163 if (!h->rescan_ctlr_wq) {
7164 rc = -ENOMEM;
7165 goto clean1;
7166 }
7167
7168 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
080ef1cc 7169 if (!h->resubmit_wq) {
080ef1cc
DB		 7170 rc = -ENOMEM;
7171 goto clean1;
7172 }
6636e7f4 7173
094963da
SC		 7174 /* Allocate and clear per-cpu variable lockup_detected */
7175 h->lockup_detected = alloc_percpu(u32);
2a5ac326
SC		 7176 if (!h->lockup_detected) {
7177 rc = -ENOMEM;
094963da 7178 goto clean1;
2a5ac326 7179 }
094963da
SC		 7180 set_lockup_detected_for_all_cpus(h, 0);
7181
55c06c71 7182 rc = hpsa_pci_init(h);
ecd9aad4 7183 if (rc != 0)
edd16368
SC		 7184 goto clean1;
7185
f79cfec6 7186 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 7187 h->ctlr = number_of_controllers;
7188 number_of_controllers++;
edd16368
SC		 7189
7190 /* configure PCI DMA stuff */
ecd9aad4
SC		 7191 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
7192 if (rc == 0) {
edd16368 7193 dac = 1;
ecd9aad4
SC		 7194 } else {
7195 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7196 if (rc == 0) {
7197 dac = 0;
7198 } else {
7199 dev_err(&pdev->dev, "no suitable DMA available\n");
7200 goto clean1;
7201 }
edd16368
SC		 7202 }
7203
7204 /* make sure the board interrupts are off */
7205 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 7206
9ee61794 7207 if (hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 7208 goto clean2;
303932fd
DB		 7209 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
7210 h->devname, pdev->device,
a9a3a273 7211 h->intr[h->intr_mode], dac ? "" : " not");
8947fd10
RE		 7212 rc = hpsa_allocate_cmd_pool(h);
7213 if (rc)
7214 goto clean2_and_free_irqs;
33a2ffce
SC		 7215 if (hpsa_allocate_sg_chain_blocks(h))
7216 goto clean4;
a08a8471 7217 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 7218 init_waitqueue_head(&h->abort_cmd_wait_queue);
a08a8471 7219 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 7220
7221 pci_set_drvdata(pdev, h);
9a41338e 7222 h->ndevices = 0;
316b221a 7223 h->hba_mode_enabled = 0;
9a41338e
SC		 7224 h->scsi_host = NULL;
7225 spin_lock_init(&h->devlock);
64670ac8
SC		 7226 hpsa_put_ctlr_into_performant_mode(h);
7227
7228 /* At this point, the controller is ready to take commands.
7229 * Now, if reset_devices and the hard reset didn't work, try
7230 * the soft reset and see if that works.
7231 */
7232 if (try_soft_reset) {
7233
7234 /* This is kind of gross. We may or may not get a completion
7235 * from the soft reset command, and if we do, then the value
7236 * from the fifo may or may not be valid. So, we wait 10 secs
7237 * after the reset throwing away any completions we get during
7238 * that time. Unregister the interrupt handler and register
7239 * fake ones to scoop up any residual completions.
7240 */
7241 spin_lock_irqsave(&h->lock, flags);
7242 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7243 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 7244 hpsa_free_irqs(h);
9ee61794 7245 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 7246 hpsa_intx_discard_completions);
7247 if (rc) {
9ee61794
RE		 7248 dev_warn(&h->pdev->dev,
7249 "Failed to request_irq after soft reset.\n");
64670ac8
SC		 7250 goto clean4;
7251 }
7252
7253 rc = hpsa_kdump_soft_reset(h);
7254 if (rc)
7255 /* Neither hard nor soft reset worked, we're hosed. */
7256 goto clean4;
7257
7258 dev_info(&h->pdev->dev, "Board READY.\n");
7259 dev_info(&h->pdev->dev,
7260 "Waiting for stale completions to drain.\n");
7261 h->access.set_intr_mask(h, HPSA_INTR_ON);
7262 msleep(10000);
7263 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7264
7265 rc = controller_reset_failed(h->cfgtable);
7266 if (rc)
7267 dev_info(&h->pdev->dev,
7268 "Soft reset appears to have failed.\n");
7269
7270 /* since the controller's reset, we have to go back and re-init
7271 * everything. Easiest to just forget what we've done and do it
7272 * all over again.
7273 */
7274 hpsa_undo_allocations_after_kdump_soft_reset(h);
7275 try_soft_reset = 0;
7276 if (rc)
7277 /* don't go to clean4, we already unallocated */
7278 return -ENODEV;
7279
7280 goto reinit_after_soft_reset;
7281 }
edd16368 7282
316b221a
SC		 7283 /* Enable Accelerated IO path at driver layer */
7284 h->acciopath_status = 1;
da0697bd 7285
e863d68e 7286
edd16368
SC		 7287 /* Turn the interrupts on so we can service requests */
7288 h->access.set_intr_mask(h, HPSA_INTR_ON);
7289
339b2b14 7290 hpsa_hba_inquiry(h);
edd16368 7291 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 7292
7293 /* Monitor the controller for firmware lockups */
7294 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
7295 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
7296 schedule_delayed_work(&h->monitor_ctlr_work,
7297 h->heartbeat_sample_interval);
6636e7f4
DB		 7298 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
7299 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7300 h->heartbeat_sample_interval);
88bf6d62 7301 return 0;
edd16368
SC		 7302
7303clean4:
33a2ffce 7304 hpsa_free_sg_chain_blocks(h);
2e9d1b36 7305 hpsa_free_cmd_pool(h);
8947fd10 7306clean2_and_free_irqs:
ec501a18 7307 hpsa_free_irqs(h);
edd16368
SC		 7308clean2:
7309clean1:
080ef1cc
DB		 7310 if (h->resubmit_wq)
7311 destroy_workqueue(h->resubmit_wq);
6636e7f4
DB		 7312 if (h->rescan_ctlr_wq)
7313 destroy_workqueue(h->rescan_ctlr_wq);
094963da
SC		 7314 if (h->lockup_detected)
7315 free_percpu(h->lockup_detected);
edd16368 7316 kfree(h);
ecd9aad4 7317 return rc;
edd16368
SC		 7318}
7319
7320static void hpsa_flush_cache(struct ctlr_info *h)
7321{
7322 char *flush_buf;
7323 struct CommandList *c;
25163bd5 7324 int rc;
702890e3
SC		 7325
7326 /* Don't bother trying to flush the cache if locked up */
25163bd5 7327 /* FIXME not necessary if do_simple_cmd does the check */
094963da 7328 if (unlikely(lockup_detected(h)))
702890e3 7329 return;
edd16368
SC		 7330 flush_buf = kzalloc(4, GFP_KERNEL);
7331 if (!flush_buf)
7332 return;
7333
45fcb86e 7334 c = cmd_alloc(h);
edd16368 7335 if (!c) {
45fcb86e 7336 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 7337 goto out_of_memory;
7338 }
a2dac136
SC		 7339 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
7340 RAID_CTLR_LUNID, TYPE_CMD)) {
7341 goto out;
7342 }
25163bd5
WS		 7343 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
7344 PCI_DMA_TODEVICE, NO_TIMEOUT);
7345 if (rc)
7346 goto out;
edd16368 7347 if (c->err_info->CommandStatus != 0)
a2dac136 7348out:
edd16368
SC		 7349 dev_warn(&h->pdev->dev,
7350 "error flushing cache on controller\n");
45fcb86e 7351 cmd_free(h, c);
edd16368
SC		 7352out_of_memory:
7353 kfree(flush_buf);
7354}
7355
7356static void hpsa_shutdown(struct pci_dev *pdev)
7357{
7358 struct ctlr_info *h;
7359
7360 h = pci_get_drvdata(pdev);
7361 /* Turn board interrupts off and send the flush cache command
7362 * sendcmd will turn off interrupt, and send the flush...
7363 * To write all data in the battery backed cache to disks
7364 */
7365 hpsa_flush_cache(h);
7366 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 7367 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 7368}
7369
6f039790 7370static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 7371{
7372 int i;
7373
7374 for (i = 0; i < h->ndevices; i++)
7375 kfree(h->dev[i]);
7376}
7377
6f039790 7378static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 7379{
7380 struct ctlr_info *h;
8a98db73 7381 unsigned long flags;
edd16368
SC		 7382
7383 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 7384 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 7385 return;
7386 }
7387 h = pci_get_drvdata(pdev);
8a98db73
SC		 7388
7389 /* Get rid of any controller monitoring work items */
7390 spin_lock_irqsave(&h->lock, flags);
7391 h->remove_in_progress = 1;
8a98db73 7392 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 7393 cancel_delayed_work_sync(&h->monitor_ctlr_work);
7394 cancel_delayed_work_sync(&h->rescan_ctlr_work);
7395 destroy_workqueue(h->rescan_ctlr_wq);
7396 destroy_workqueue(h->resubmit_wq);
edd16368
SC		 7397 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
7398 hpsa_shutdown(pdev);
7399 iounmap(h->vaddr);
204892e9
SC		 7400 iounmap(h->transtable);
7401 iounmap(h->cfgtable);
55e14e76 7402 hpsa_free_device_info(h);
33a2ffce 7403 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 7404 pci_free_consistent(h->pdev,
7405 h->nr_cmds * sizeof(struct CommandList),
7406 h->cmd_pool, h->cmd_pool_dhandle);
7407 pci_free_consistent(h->pdev,
7408 h->nr_cmds * sizeof(struct ErrorInfo),
7409 h->errinfo_pool, h->errinfo_pool_dhandle);
072b0518 7410 hpsa_free_reply_queues(h);
edd16368 7411 kfree(h->cmd_pool_bits);
303932fd 7412 kfree(h->blockFetchTable);
e1f7de0c 7413 kfree(h->ioaccel1_blockFetchTable);
aca9012a 7414 kfree(h->ioaccel2_blockFetchTable);
339b2b14 7415 kfree(h->hba_inquiry_data);
f0bd0b68 7416 pci_disable_device(pdev);
edd16368 7417 pci_release_regions(pdev);
094963da 7418 free_percpu(h->lockup_detected);
edd16368
SC		 7419 kfree(h);
7420}
7421
7422static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
7423 __attribute__((unused)) pm_message_t state)
7424{
7425 return -ENOSYS;
7426}
7427
7428static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
7429{
7430 return -ENOSYS;
7431}
7432
7433static struct pci_driver hpsa_pci_driver = {
f79cfec6 7434 .name = HPSA,
edd16368 7435 .probe = hpsa_init_one,
6f039790 7436 .remove = hpsa_remove_one,
edd16368
SC		 7437 .id_table = hpsa_pci_device_id, /* id_table */
7438 .shutdown = hpsa_shutdown,
7439 .suspend = hpsa_suspend,
7440 .resume = hpsa_resume,
7441};
7442
303932fd
DB		 7443/* Fill in bucket_map[], given nsgs (the max number of
7444 * scatter gather elements supported) and bucket[],
7445 * which is an array of 8 integers. The bucket[] array
7446 * contains 8 different DMA transfer sizes (in 16
7447 * byte increments) which the controller uses to fetch
7448 * commands. This function fills in bucket_map[], which
7449 * maps a given number of scatter gather elements to one of
7450 * the 8 DMA transfer sizes. The point of it is to allow the
7451 * controller to only do as much DMA as needed to fetch the
7452 * command, with the DMA transfer size encoded in the lower
7453 * bits of the command address.
7454 */
7455static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 7456 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 7457{
7458 int i, j, b, size;
7459
303932fd
DB		 7460 /* Note, bucket_map must have nsgs+1 entries. */
7461 for (i = 0; i <= nsgs; i++) {
7462 /* Compute size of a command with i SG entries */
e1f7de0c 7463 size = i + min_blocks;
303932fd
DB		 7464 b = num_buckets; /* Assume the biggest bucket */
7465 /* Find the bucket that is just big enough */
e1f7de0c 7466 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 7467 if (bucket[j] >= size) {
7468 b = j;
7469 break;
7470 }
7471 }
7472 /* for a command with i SG entries, use bucket b. */
7473 bucket_map[i] = b;
7474 }
7475}
7476
c706a795
RE		 7477/* return -ENODEV or other reason on error, 0 on success */
7478static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 7479{
6c311b57
SC		 7480 int i;
7481 unsigned long register_value;
e1f7de0c
MG		 7482 unsigned long transMethod = CFGTBL_Trans_Performant |
7483 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 7484 CFGTBL_Trans_enable_directed_msix |
7485 (trans_support & (CFGTBL_Trans_io_accel1 |
7486 CFGTBL_Trans_io_accel2));
e1f7de0c 7487 struct access_method access = SA5_performant_access;
def342bd
SC		 7488
7489 /* This is a bit complicated. There are 8 registers on
7490 * the controller which we write to to tell it 8 different
7491 * sizes of commands which there may be. It's a way of
7492 * reducing the DMA done to fetch each command. Encoded into
7493 * each command's tag are 3 bits which communicate to the controller
7494 * which of the eight sizes that command fits within. The size of
7495 * each command depends on how many scatter gather entries there are.
7496 * Each SG entry requires 16 bytes. The eight registers are programmed
7497 * with the number of 16-byte blocks a command of that size requires.
7498 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 7499 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 7500 * blocks. Note, this only extends to the SG entries contained
7501 * within the command block, and does not extend to chained blocks
7502 * of SG elements. bft[] contains the eight values we write to
7503 * the registers. They are not evenly distributed, but have more
7504 * sizes for small commands, and fewer sizes for larger commands.
7505 */
d66ae08b 7506 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 7507#define MIN_IOACCEL2_BFT_ENTRY 5
7508#define HPSA_IOACCEL2_HEADER_SZ 4
7509 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
7510 13, 14, 15, 16, 17, 18, 19,
7511 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
7512 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
7513 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
7514 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
7515 16 * MIN_IOACCEL2_BFT_ENTRY);
7516 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 7517 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 7518 /* 5 = 1 s/g entry or 4k
7519 * 6 = 2 s/g entry or 8k
7520 * 8 = 4 s/g entry or 16k
7521 * 10 = 6 s/g entry or 24k
7522 */
303932fd 7523
b3a52e79
SC		 7524 /* If the controller supports either ioaccel method then
7525 * we can also use the RAID stack submit path that does not
7526 * perform the superfluous readl() after each command submission.
7527 */
7528 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
7529 access = SA5_performant_access_no_read;
7530
303932fd 7531 /* Controller spec: zero out this buffer. */
072b0518
SC		 7532 for (i = 0; i < h->nreply_queues; i++)
7533 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 7534
d66ae08b
SC		 7535 bft[7] = SG_ENTRIES_IN_CMD + 4;
7536 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 7537 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 7538 for (i = 0; i < 8; i++)
7539 writel(bft[i], &h->transtable->BlockFetch[i]);
7540
7541 /* size of controller ring buffer */
7542 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 7543 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 7544 writel(0, &h->transtable->RepQCtrAddrLow32);
7545 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 7546
7547 for (i = 0; i < h->nreply_queues; i++) {
7548 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 7549 writel(h->reply_queue[i].busaddr,
254f796b
MG		 7550 &h->transtable->RepQAddr[i].lower);
7551 }
7552
b9af4937 7553 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 7554 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
7555 /*
7556 * enable outbound interrupt coalescing in accelerator mode;
7557 */
7558 if (trans_support & CFGTBL_Trans_io_accel1) {
7559 access = SA5_ioaccel_mode1_access;
7560 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7561 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 7562 } else {
7563 if (trans_support & CFGTBL_Trans_io_accel2) {
7564 access = SA5_ioaccel_mode2_access;
7565 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7566 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
7567 }
e1f7de0c 7568 }
303932fd 7569 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7570 if (hpsa_wait_for_mode_change_ack(h)) {
7571 dev_err(&h->pdev->dev,
7572 "performant mode problem - doorbell timeout\n");
7573 return -ENODEV;
7574 }
303932fd
DB		 7575 register_value = readl(&(h->cfgtable->TransportActive));
7576 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 7577 dev_err(&h->pdev->dev,
7578 "performant mode problem - transport not active\n");
c706a795 7579 return -ENODEV;
303932fd 7580 }
960a30e7 7581 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 7582 h->access = access;
7583 h->transMethod = transMethod;
7584
b9af4937
SC		 7585 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
7586 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 7587 return 0;
e1f7de0c 7588
b9af4937
SC		 7589 if (trans_support & CFGTBL_Trans_io_accel1) {
7590 /* Set up I/O accelerator mode */
7591 for (i = 0; i < h->nreply_queues; i++) {
7592 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
7593 h->reply_queue[i].current_entry =
7594 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
7595 }
7596 bft[7] = h->ioaccel_maxsg + 8;
7597 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
7598 h->ioaccel1_blockFetchTable);
e1f7de0c 7599
b9af4937 7600 /* initialize all reply queue entries to unused */
072b0518
SC		 7601 for (i = 0; i < h->nreply_queues; i++)
7602 memset(h->reply_queue[i].head,
7603 (u8) IOACCEL_MODE1_REPLY_UNUSED,
7604 h->reply_queue_size);
e1f7de0c 7605
b9af4937
SC		 7606 /* set all the constant fields in the accelerator command
7607 * frames once at init time to save CPU cycles later.
7608 */
7609 for (i = 0; i < h->nr_cmds; i++) {
7610 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
7611
7612 cp->function = IOACCEL1_FUNCTION_SCSIIO;
7613 cp->err_info = (u32) (h->errinfo_pool_dhandle +
7614 (i * sizeof(struct ErrorInfo)));
7615 cp->err_info_len = sizeof(struct ErrorInfo);
7616 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 7617 cp->host_context_flags =
7618 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 7619 cp->timeout_sec = 0;
7620 cp->ReplyQueue = 0;
50a0decf 7621 cp->tag =
f2405db8 7622 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 7623 cp->host_addr =
7624 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 7625 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 7626 }
7627 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7628 u64 cfg_offset, cfg_base_addr_index;
7629 u32 bft2_offset, cfg_base_addr;
7630 int rc;
7631
7632 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7633 &cfg_base_addr_index, &cfg_offset);
7634 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7635 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7636 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7637 4, h->ioaccel2_blockFetchTable);
7638 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7639 BUILD_BUG_ON(offsetof(struct CfgTable,
7640 io_accel_request_size_offset) != 0xb8);
7641 h->ioaccel2_bft2_regs =
7642 remap_pci_mem(pci_resource_start(h->pdev,
7643 cfg_base_addr_index) +
7644 cfg_offset + bft2_offset,
7645 ARRAY_SIZE(bft2) *
7646 sizeof(*h->ioaccel2_bft2_regs));
7647 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7648 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7649 }
b9af4937 7650 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7651 if (hpsa_wait_for_mode_change_ack(h)) {
7652 dev_err(&h->pdev->dev,
7653 "performant mode problem - enabling ioaccel mode\n");
7654 return -ENODEV;
7655 }
7656 return 0;
e1f7de0c
MG		 7657}
7658
7659static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
7660{
283b4a9b
SC		 7661 h->ioaccel_maxsg =
7662 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7663 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7664 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7665
e1f7de0c
MG		 7666 /* Command structures must be aligned on a 128-byte boundary
7667 * because the 7 lower bits of the address are used by the
7668 * hardware.
7669 */
e1f7de0c
MG		 7670 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7671 IOACCEL1_COMMANDLIST_ALIGNMENT);
7672 h->ioaccel_cmd_pool =
7673 pci_alloc_consistent(h->pdev,
7674 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7675 &(h->ioaccel_cmd_pool_dhandle));
7676
7677 h->ioaccel1_blockFetchTable =
283b4a9b 7678 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7679 sizeof(u32)), GFP_KERNEL);
7680
7681 if ((h->ioaccel_cmd_pool == NULL) ||
7682 (h->ioaccel1_blockFetchTable == NULL))
7683 goto clean_up;
7684
7685 memset(h->ioaccel_cmd_pool, 0,
7686 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
7687 return 0;
7688
7689clean_up:
7690 if (h->ioaccel_cmd_pool)
7691 pci_free_consistent(h->pdev,
7692 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7693 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
7694 kfree(h->ioaccel1_blockFetchTable);
7695 return 1;
6c311b57
SC		 7696}
7697
aca9012a
SC		 7698static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
7699{
7700 /* Allocate ioaccel2 mode command blocks and block fetch table */
7701
7702 h->ioaccel_maxsg =
7703 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7704 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
7705 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
7706
aca9012a
SC		 7707 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
7708 IOACCEL2_COMMANDLIST_ALIGNMENT);
7709 h->ioaccel2_cmd_pool =
7710 pci_alloc_consistent(h->pdev,
7711 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7712 &(h->ioaccel2_cmd_pool_dhandle));
7713
7714 h->ioaccel2_blockFetchTable =
7715 kmalloc(((h->ioaccel_maxsg + 1) *
7716 sizeof(u32)), GFP_KERNEL);
7717
7718 if ((h->ioaccel2_cmd_pool == NULL) ||
7719 (h->ioaccel2_blockFetchTable == NULL))
7720 goto clean_up;
7721
7722 memset(h->ioaccel2_cmd_pool, 0,
7723 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
7724 return 0;
7725
7726clean_up:
7727 if (h->ioaccel2_cmd_pool)
7728 pci_free_consistent(h->pdev,
7729 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7730 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
7731 kfree(h->ioaccel2_blockFetchTable);
7732 return 1;
7733}
7734
6f039790 7735static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 7736{
7737 u32 trans_support;
e1f7de0c
MG		 7738 unsigned long transMethod = CFGTBL_Trans_Performant |
7739 CFGTBL_Trans_use_short_tags;
254f796b 7740 int i;
6c311b57 7741
02ec19c8
SC		 7742 if (hpsa_simple_mode)
7743 return;
7744
67c99a72 7745 trans_support = readl(&(h->cfgtable->TransportSupport));
7746 if (!(trans_support & PERFORMANT_MODE))
7747 return;
7748
e1f7de0c
MG		 7749 /* Check for I/O accelerator mode support */
7750 if (trans_support & CFGTBL_Trans_io_accel1) {
7751 transMethod |= CFGTBL_Trans_io_accel1 |
7752 CFGTBL_Trans_enable_directed_msix;
7753 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
7754 goto clean_up;
aca9012a
SC		 7755 } else {
7756 if (trans_support & CFGTBL_Trans_io_accel2) {
7757 transMethod |= CFGTBL_Trans_io_accel2 |
7758 CFGTBL_Trans_enable_directed_msix;
7759 if (ioaccel2_alloc_cmds_and_bft(h))
7760 goto clean_up;
7761 }
e1f7de0c
MG		 7762 }
7763
eee0f03a 7764 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 7765 hpsa_get_max_perf_mode_cmds(h);
6c311b57 7766 /* Performant mode ring buffer and supporting data structures */
072b0518 7767 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 7768
254f796b 7769 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 7770 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
7771 h->reply_queue_size,
7772 &(h->reply_queue[i].busaddr));
7773 if (!h->reply_queue[i].head)
7774 goto clean_up;
254f796b
MG		 7775 h->reply_queue[i].size = h->max_commands;
7776 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
7777 h->reply_queue[i].current_entry = 0;
7778 }
7779
6c311b57 7780 /* Need a block fetch table for performant mode */
d66ae08b 7781 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 7782 sizeof(u32)), GFP_KERNEL);
072b0518 7783 if (!h->blockFetchTable)
6c311b57
SC		 7784 goto clean_up;
7785
e1f7de0c 7786 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 7787 return;
7788
7789clean_up:
072b0518 7790 hpsa_free_reply_queues(h);
303932fd
DB		 7791 kfree(h->blockFetchTable);
7792}
7793
23100dd9 7794static int is_accelerated_cmd(struct CommandList *c)
76438d08 7795{
23100dd9
SC		 7796 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
7797}
7798
7799static void hpsa_drain_accel_commands(struct ctlr_info *h)
7800{
7801 struct CommandList *c = NULL;
f2405db8 7802 int i, accel_cmds_out;
281a7fd0 7803 int refcount;
76438d08 7804
f2405db8 7805 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 7806 accel_cmds_out = 0;
f2405db8 7807 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7808 c = h->cmd_pool + i;
281a7fd0
WS		 7809 refcount = atomic_inc_return(&c->refcount);
7810 if (refcount > 1) /* Command is allocated */
7811 accel_cmds_out += is_accelerated_cmd(c);
7812 cmd_free(h, c);
f2405db8 7813 }
23100dd9 7814 if (accel_cmds_out <= 0)
281a7fd0 7815 break;
76438d08
SC		 7816 msleep(100);
7817 } while (1);
7818}
7819
edd16368
SC		 7820/*
7821 * This is it. Register the PCI driver information for the cards we control
7822 * the OS will call our registered routines when it finds one of our cards.
7823 */
7824static int __init hpsa_init(void)
7825{
31468401 7826 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 7827}
7828
7829static void __exit hpsa_cleanup(void)
7830{
7831 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 7832}
7833
e1f7de0c
MG		 7834static void __attribute__((unused)) verify_offsets(void)
7835{
dd0e19f3
ST		 7836#define VERIFY_OFFSET(member, offset) \
7837 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
7838
7839 VERIFY_OFFSET(structure_size, 0);
7840 VERIFY_OFFSET(volume_blk_size, 4);
7841 VERIFY_OFFSET(volume_blk_cnt, 8);
7842 VERIFY_OFFSET(phys_blk_shift, 16);
7843 VERIFY_OFFSET(parity_rotation_shift, 17);
7844 VERIFY_OFFSET(strip_size, 18);
7845 VERIFY_OFFSET(disk_starting_blk, 20);
7846 VERIFY_OFFSET(disk_blk_cnt, 28);
7847 VERIFY_OFFSET(data_disks_per_row, 36);
7848 VERIFY_OFFSET(metadata_disks_per_row, 38);
7849 VERIFY_OFFSET(row_cnt, 40);
7850 VERIFY_OFFSET(layout_map_count, 42);
7851 VERIFY_OFFSET(flags, 44);
7852 VERIFY_OFFSET(dekindex, 46);
7853 /* VERIFY_OFFSET(reserved, 48 */
7854 VERIFY_OFFSET(data, 64);
7855
7856#undef VERIFY_OFFSET
7857
b66cc250
MM		 7858#define VERIFY_OFFSET(member, offset) \
7859 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
7860
7861 VERIFY_OFFSET(IU_type, 0);
7862 VERIFY_OFFSET(direction, 1);
7863 VERIFY_OFFSET(reply_queue, 2);
7864 /* VERIFY_OFFSET(reserved1, 3); */
7865 VERIFY_OFFSET(scsi_nexus, 4);
7866 VERIFY_OFFSET(Tag, 8);
7867 VERIFY_OFFSET(cdb, 16);
7868 VERIFY_OFFSET(cciss_lun, 32);
7869 VERIFY_OFFSET(data_len, 40);
7870 VERIFY_OFFSET(cmd_priority_task_attr, 44);
7871 VERIFY_OFFSET(sg_count, 45);
7872 /* VERIFY_OFFSET(reserved3 */
7873 VERIFY_OFFSET(err_ptr, 48);
7874 VERIFY_OFFSET(err_len, 56);
7875 /* VERIFY_OFFSET(reserved4 */
7876 VERIFY_OFFSET(sg, 64);
7877
7878#undef VERIFY_OFFSET
7879
e1f7de0c
MG		 7880#define VERIFY_OFFSET(member, offset) \
7881 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
7882
7883 VERIFY_OFFSET(dev_handle, 0x00);
7884 VERIFY_OFFSET(reserved1, 0x02);
7885 VERIFY_OFFSET(function, 0x03);
7886 VERIFY_OFFSET(reserved2, 0x04);
7887 VERIFY_OFFSET(err_info, 0x0C);
7888 VERIFY_OFFSET(reserved3, 0x10);
7889 VERIFY_OFFSET(err_info_len, 0x12);
7890 VERIFY_OFFSET(reserved4, 0x13);
7891 VERIFY_OFFSET(sgl_offset, 0x14);
7892 VERIFY_OFFSET(reserved5, 0x15);
7893 VERIFY_OFFSET(transfer_len, 0x1C);
7894 VERIFY_OFFSET(reserved6, 0x20);
7895 VERIFY_OFFSET(io_flags, 0x24);
7896 VERIFY_OFFSET(reserved7, 0x26);
7897 VERIFY_OFFSET(LUN, 0x34);
7898 VERIFY_OFFSET(control, 0x3C);
7899 VERIFY_OFFSET(CDB, 0x40);
7900 VERIFY_OFFSET(reserved8, 0x50);
7901 VERIFY_OFFSET(host_context_flags, 0x60);
7902 VERIFY_OFFSET(timeout_sec, 0x62);
7903 VERIFY_OFFSET(ReplyQueue, 0x64);
7904 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 7905 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 7906 VERIFY_OFFSET(host_addr, 0x70);
7907 VERIFY_OFFSET(CISS_LUN, 0x78);
7908 VERIFY_OFFSET(SG, 0x78 + 8);
7909#undef VERIFY_OFFSET
7910}
7911
edd16368
SC		 7912module_init(hpsa_init);
7913module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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