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Change how controllers in mixed mode are handled.
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
1358f6dc
DB		 3 * Copyright 2014-2015 PMC-Sierra, Inc.
4 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
edd16368
SC		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
1358f6dc 15 * Questions/Comments/Bugfixes to storagedev@pmcs.com
edd16368
SC		 16 *
17 */
18
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/types.h>
22#include <linux/pci.h>
e5a44df8 23#include <linux/pci-aspm.h>
edd16368
SC		 24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/fs.h>
28#include <linux/timer.h>
edd16368
SC		 29#include <linux/init.h>
30#include <linux/spinlock.h>
edd16368
SC		 31#include <linux/compat.h>
32#include <linux/blktrace_api.h>
33#include <linux/uaccess.h>
34#include <linux/io.h>
35#include <linux/dma-mapping.h>
36#include <linux/completion.h>
37#include <linux/moduleparam.h>
38#include <scsi/scsi.h>
39#include <scsi/scsi_cmnd.h>
40#include <scsi/scsi_device.h>
41#include <scsi/scsi_host.h>
667e23d4 42#include <scsi/scsi_tcq.h>
9437ac43 43#include <scsi/scsi_eh.h>
73153fe5 44#include <scsi/scsi_dbg.h>
edd16368
SC		 45#include <linux/cciss_ioctl.h>
46#include <linux/string.h>
47#include <linux/bitmap.h>
60063497 48#include <linux/atomic.h>
a0c12413 49#include <linux/jiffies.h>
42a91641 50#include <linux/percpu-defs.h>
094963da 51#include <linux/percpu.h>
2b08b3e9 52#include <asm/unaligned.h>
283b4a9b 53#include <asm/div64.h>
edd16368
SC		 54#include "hpsa_cmd.h"
55#include "hpsa.h"
56
57/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
f532a3f9 58#define HPSA_DRIVER_VERSION "3.4.10-0"
edd16368 59#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 60#define HPSA "hpsa"
edd16368 61
007e7aa9
RE		 62/* How long to wait for CISS doorbell communication */
63#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
64#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
65#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
66#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 67#define MAX_IOCTL_CONFIG_WAIT 1000
68
69/*define how many times we will try a command because of bus resets */
70#define MAX_CMD_RETRIES 3
71
72/* Embedded module documentation macros - see modules.h */
73MODULE_AUTHOR("Hewlett-Packard Company");
74MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
75 HPSA_DRIVER_VERSION);
76MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
77MODULE_VERSION(HPSA_DRIVER_VERSION);
78MODULE_LICENSE("GPL");
79
80static int hpsa_allow_any;
81module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_allow_any,
83 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 84static int hpsa_simple_mode;
85module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
86MODULE_PARM_DESC(hpsa_simple_mode,
87 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 88
89/* define the PCI info for the cards we can control */
90static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
fdfa4b6d 131 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
cbb47dcb
DB		 132 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
133 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
134 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
135 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
8e616a5e
SC		 137 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
138 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
139 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
140 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
141 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 142 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 143 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 144 {0,}
145};
146
147MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
148
149/* board_id = Subsystem Device ID & Vendor ID
150 * product = Marketing Name for the board
151 * access = Address of the struct of function pointers
152 */
153static struct board_type products[] = {
edd16368
SC		 154 {0x3241103C, "Smart Array P212", &SA5_access},
155 {0x3243103C, "Smart Array P410", &SA5_access},
156 {0x3245103C, "Smart Array P410i", &SA5_access},
157 {0x3247103C, "Smart Array P411", &SA5_access},
158 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 159 {0x324A103C, "Smart Array P712m", &SA5_access},
160 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 161 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 162 {0x3350103C, "Smart Array P222", &SA5_access},
163 {0x3351103C, "Smart Array P420", &SA5_access},
164 {0x3352103C, "Smart Array P421", &SA5_access},
165 {0x3353103C, "Smart Array P822", &SA5_access},
166 {0x3354103C, "Smart Array P420i", &SA5_access},
167 {0x3355103C, "Smart Array P220i", &SA5_access},
168 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 169 {0x1921103C, "Smart Array P830i", &SA5_access},
170 {0x1922103C, "Smart Array P430", &SA5_access},
171 {0x1923103C, "Smart Array P431", &SA5_access},
172 {0x1924103C, "Smart Array P830", &SA5_access},
173 {0x1926103C, "Smart Array P731m", &SA5_access},
174 {0x1928103C, "Smart Array P230i", &SA5_access},
175 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 176 {0x21BD103C, "Smart Array P244br", &SA5_access},
177 {0x21BE103C, "Smart Array P741m", &SA5_access},
178 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
179 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 180 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 181 {0x21C2103C, "Smart Array P440", &SA5_access},
182 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 183 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 184 {0x21C5103C, "Smart Array P841", &SA5_access},
185 {0x21C6103C, "Smart HBA H244br", &SA5_access},
186 {0x21C7103C, "Smart HBA H240", &SA5_access},
187 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 188 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 189 {0x21CA103C, "Smart Array P246br", &SA5_access},
190 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 191 {0x21CC103C, "Smart Array", &SA5_access},
192 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 193 {0x21CE103C, "Smart HBA", &SA5_access},
fdfa4b6d 194 {0x05809005, "SmartHBA-SA", &SA5_access},
cbb47dcb
DB		 195 {0x05819005, "SmartHBA-SA 8i", &SA5_access},
196 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
197 {0x05839005, "SmartHBA-SA 8e", &SA5_access},
198 {0x05849005, "SmartHBA-SA 16i", &SA5_access},
199 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
8e616a5e
SC		 200 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
201 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
202 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
203 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
204 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 205 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
206};
207
a58e7e53
WS		 208#define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
209static const struct scsi_cmnd hpsa_cmd_busy;
210#define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
211static const struct scsi_cmnd hpsa_cmd_idle;
edd16368
SC		 212static int number_of_controllers;
213
10f66018
SC		 214static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
215static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 216static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 217
218#ifdef CONFIG_COMPAT
42a91641
DB		 219static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
220 void __user *arg);
edd16368
SC		 221#endif
222
223static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 224static struct CommandList *cmd_alloc(struct ctlr_info *h);
73153fe5
WS		 225static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
226static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
227 struct scsi_cmnd *scmd);
a2dac136 228static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 229 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 230 int cmd_type);
2c143342 231static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 232#define VPD_PAGE (1 << 8)
edd16368 233
f281233d 234static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 235static void hpsa_scan_start(struct Scsi_Host *);
236static int hpsa_scan_finished(struct Scsi_Host *sh,
237 unsigned long elapsed_time);
7c0a0229 238static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 239
240static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 241static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 242static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 243static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 244static void hpsa_slave_destroy(struct scsi_device *sdev);
245
edd16368 246static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 247static int check_for_unit_attention(struct ctlr_info *h,
248 struct CommandList *c);
249static void check_ioctl_unit_attention(struct ctlr_info *h,
250 struct CommandList *c);
303932fd
DB		 251/* performant mode helper functions */
252static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 253 int nsgs, int min_blocks, u32 *bucket_map);
105a3dbc
RE		 254static void hpsa_free_performant_mode(struct ctlr_info *h);
255static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 256static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 257static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
258 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
259 u64 *cfg_offset);
260static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
261 unsigned long *memory_bar);
262static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
263static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
264 int wait_for_ready);
75167d2c 265static inline void finish_cmd(struct CommandList *c);
c706a795 266static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 267#define BOARD_NOT_READY 0
268#define BOARD_READY 1
23100dd9 269static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 270static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 271static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
272 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 273 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 274static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 275static u32 lockup_detected(struct ctlr_info *h);
276static int detect_controller_lockup(struct ctlr_info *h);
8270b862 277static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device);
edd16368 278
edd16368
SC		 279static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
280{
281 unsigned long *priv = shost_priv(sdev->host);
282 return (struct ctlr_info *) *priv;
283}
284
a23513e8
SC		 285static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
286{
287 unsigned long *priv = shost_priv(sh);
288 return (struct ctlr_info *) *priv;
289}
290
a58e7e53
WS		 291static inline bool hpsa_is_cmd_idle(struct CommandList *c)
292{
293 return c->scsi_cmd == SCSI_CMD_IDLE;
294}
295
d604f533
WS		 296static inline bool hpsa_is_pending_event(struct CommandList *c)
297{
298 return c->abort_pending || c->reset_pending;
299}
300
9437ac43
SC		 301/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
302static void decode_sense_data(const u8 *sense_data, int sense_data_len,
303 u8 *sense_key, u8 *asc, u8 *ascq)
304{
305 struct scsi_sense_hdr sshdr;
306 bool rc;
307
308 *sense_key = -1;
309 *asc = -1;
310 *ascq = -1;
311
312 if (sense_data_len < 1)
313 return;
314
315 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
316 if (rc) {
317 *sense_key = sshdr.sense_key;
318 *asc = sshdr.asc;
319 *ascq = sshdr.ascq;
320 }
321}
322
edd16368
SC		 323static int check_for_unit_attention(struct ctlr_info *h,
324 struct CommandList *c)
325{
9437ac43
SC		 326 u8 sense_key, asc, ascq;
327 int sense_len;
328
329 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
330 sense_len = sizeof(c->err_info->SenseInfo);
331 else
332 sense_len = c->err_info->SenseLen;
333
334 decode_sense_data(c->err_info->SenseInfo, sense_len,
335 &sense_key, &asc, &ascq);
81c27557 336 if (sense_key != UNIT_ATTENTION || asc == 0xff)
edd16368
SC		 337 return 0;
338
9437ac43 339 switch (asc) {
edd16368 340 case STATE_CHANGED:
9437ac43 341 dev_warn(&h->pdev->dev,
2946e82b
RE		 342 "%s: a state change detected, command retried\n",
343 h->devname);
edd16368
SC		 344 break;
345 case LUN_FAILED:
7f73695a 346 dev_warn(&h->pdev->dev,
2946e82b 347 "%s: LUN failure detected\n", h->devname);
edd16368
SC		 348 break;
349 case REPORT_LUNS_CHANGED:
7f73695a 350 dev_warn(&h->pdev->dev,
2946e82b 351 "%s: report LUN data changed\n", h->devname);
edd16368 352 /*
4f4eb9f1
ST		 353 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
354 * target (array) devices.
edd16368
SC		 355 */
356 break;
357 case POWER_OR_RESET:
2946e82b
RE		 358 dev_warn(&h->pdev->dev,
359 "%s: a power on or device reset detected\n",
360 h->devname);
edd16368
SC		 361 break;
362 case UNIT_ATTENTION_CLEARED:
2946e82b
RE		 363 dev_warn(&h->pdev->dev,
364 "%s: unit attention cleared by another initiator\n",
365 h->devname);
edd16368
SC		 366 break;
367 default:
2946e82b
RE		 368 dev_warn(&h->pdev->dev,
369 "%s: unknown unit attention detected\n",
370 h->devname);
edd16368
SC		 371 break;
372 }
373 return 1;
374}
375
852af20a
MB		 376static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
377{
378 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
379 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
380 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
381 return 0;
382 dev_warn(&h->pdev->dev, HPSA "device busy");
383 return 1;
384}
385
e985c58f
SC		 386static u32 lockup_detected(struct ctlr_info *h);
387static ssize_t host_show_lockup_detected(struct device *dev,
388 struct device_attribute *attr, char *buf)
389{
390 int ld;
391 struct ctlr_info *h;
392 struct Scsi_Host *shost = class_to_shost(dev);
393
394 h = shost_to_hba(shost);
395 ld = lockup_detected(h);
396
397 return sprintf(buf, "ld=%d\n", ld);
398}
399
da0697bd
ST		 400static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
401 struct device_attribute *attr,
402 const char *buf, size_t count)
403{
404 int status, len;
405 struct ctlr_info *h;
406 struct Scsi_Host *shost = class_to_shost(dev);
407 char tmpbuf[10];
408
409 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
410 return -EACCES;
411 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
412 strncpy(tmpbuf, buf, len);
413 tmpbuf[len] = '\0';
414 if (sscanf(tmpbuf, "%d", &status) != 1)
415 return -EINVAL;
416 h = shost_to_hba(shost);
417 h->acciopath_status = !!status;
418 dev_warn(&h->pdev->dev,
419 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
420 h->acciopath_status ? "enabled" : "disabled");
421 return count;
422}
423
2ba8bfc8
SC		 424static ssize_t host_store_raid_offload_debug(struct device *dev,
425 struct device_attribute *attr,
426 const char *buf, size_t count)
427{
428 int debug_level, len;
429 struct ctlr_info *h;
430 struct Scsi_Host *shost = class_to_shost(dev);
431 char tmpbuf[10];
432
433 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
434 return -EACCES;
435 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
436 strncpy(tmpbuf, buf, len);
437 tmpbuf[len] = '\0';
438 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
439 return -EINVAL;
440 if (debug_level < 0)
441 debug_level = 0;
442 h = shost_to_hba(shost);
443 h->raid_offload_debug = debug_level;
444 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
445 h->raid_offload_debug);
446 return count;
447}
448
edd16368
SC		 449static ssize_t host_store_rescan(struct device *dev,
450 struct device_attribute *attr,
451 const char *buf, size_t count)
452{
453 struct ctlr_info *h;
454 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 455 h = shost_to_hba(shost);
31468401 456 hpsa_scan_start(h->scsi_host);
edd16368
SC		 457 return count;
458}
459
d28ce020
SC		 460static ssize_t host_show_firmware_revision(struct device *dev,
461 struct device_attribute *attr, char *buf)
462{
463 struct ctlr_info *h;
464 struct Scsi_Host *shost = class_to_shost(dev);
465 unsigned char *fwrev;
466
467 h = shost_to_hba(shost);
468 if (!h->hba_inquiry_data)
469 return 0;
470 fwrev = &h->hba_inquiry_data[32];
471 return snprintf(buf, 20, "%c%c%c%c\n",
472 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
473}
474
94a13649
SC		 475static ssize_t host_show_commands_outstanding(struct device *dev,
476 struct device_attribute *attr, char *buf)
477{
478 struct Scsi_Host *shost = class_to_shost(dev);
479 struct ctlr_info *h = shost_to_hba(shost);
480
0cbf768e
SC		 481 return snprintf(buf, 20, "%d\n",
482 atomic_read(&h->commands_outstanding));
94a13649
SC		 483}
484
745a7a25
SC		 485static ssize_t host_show_transport_mode(struct device *dev,
486 struct device_attribute *attr, char *buf)
487{
488 struct ctlr_info *h;
489 struct Scsi_Host *shost = class_to_shost(dev);
490
491 h = shost_to_hba(shost);
492 return snprintf(buf, 20, "%s\n",
960a30e7 493 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 494 "performant" : "simple");
495}
496
da0697bd
ST		 497static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
498 struct device_attribute *attr, char *buf)
499{
500 struct ctlr_info *h;
501 struct Scsi_Host *shost = class_to_shost(dev);
502
503 h = shost_to_hba(shost);
504 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
505 (h->acciopath_status == 1) ? "enabled" : "disabled");
506}
507
46380786 508/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 509static u32 unresettable_controller[] = {
510 0x324a103C, /* Smart Array P712m */
9b5c48c2 511 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 512 0x3223103C, /* Smart Array P800 */
513 0x3234103C, /* Smart Array P400 */
514 0x3235103C, /* Smart Array P400i */
515 0x3211103C, /* Smart Array E200i */
516 0x3212103C, /* Smart Array E200 */
517 0x3213103C, /* Smart Array E200i */
518 0x3214103C, /* Smart Array E200i */
519 0x3215103C, /* Smart Array E200i */
520 0x3237103C, /* Smart Array E500 */
521 0x323D103C, /* Smart Array P700m */
7af0abbc 522 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 523 0x409C0E11, /* Smart Array 6400 */
524 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 525 0x40700E11, /* Smart Array 5300 */
526 0x40820E11, /* Smart Array 532 */
527 0x40830E11, /* Smart Array 5312 */
528 0x409A0E11, /* Smart Array 641 */
529 0x409B0E11, /* Smart Array 642 */
530 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 531};
532
46380786
SC		 533/* List of controllers which cannot even be soft reset */
534static u32 soft_unresettable_controller[] = {
7af0abbc 535 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 536 0x40700E11, /* Smart Array 5300 */
537 0x40820E11, /* Smart Array 532 */
538 0x40830E11, /* Smart Array 5312 */
539 0x409A0E11, /* Smart Array 641 */
540 0x409B0E11, /* Smart Array 642 */
541 0x40910E11, /* Smart Array 6i */
46380786
SC		 542 /* Exclude 640x boards. These are two pci devices in one slot
543 * which share a battery backed cache module. One controls the
544 * cache, the other accesses the cache through the one that controls
545 * it. If we reset the one controlling the cache, the other will
546 * likely not be happy. Just forbid resetting this conjoined mess.
547 * The 640x isn't really supported by hpsa anyway.
548 */
549 0x409C0E11, /* Smart Array 6400 */
550 0x409D0E11, /* Smart Array 6400 EM */
551};
552
9b5c48c2
SC		 553static u32 needs_abort_tags_swizzled[] = {
554 0x323D103C, /* Smart Array P700m */
555 0x324a103C, /* Smart Array P712m */
556 0x324b103C, /* SmartArray P711m */
557};
558
559static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 560{
561 int i;
562
9b5c48c2
SC		 563 for (i = 0; i < nelems; i++)
564 if (a[i] == board_id)
565 return 1;
566 return 0;
46380786
SC		 567}
568
9b5c48c2 569static int ctlr_is_hard_resettable(u32 board_id)
46380786 570{
9b5c48c2
SC		 571 return !board_id_in_array(unresettable_controller,
572 ARRAY_SIZE(unresettable_controller), board_id);
573}
46380786 574
9b5c48c2
SC		 575static int ctlr_is_soft_resettable(u32 board_id)
576{
577 return !board_id_in_array(soft_unresettable_controller,
578 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 579}
580
46380786
SC		 581static int ctlr_is_resettable(u32 board_id)
582{
583 return ctlr_is_hard_resettable(board_id) ||
584 ctlr_is_soft_resettable(board_id);
585}
586
9b5c48c2
SC		 587static int ctlr_needs_abort_tags_swizzled(u32 board_id)
588{
589 return board_id_in_array(needs_abort_tags_swizzled,
590 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
591}
592
941b1cda
SC		 593static ssize_t host_show_resettable(struct device *dev,
594 struct device_attribute *attr, char *buf)
595{
596 struct ctlr_info *h;
597 struct Scsi_Host *shost = class_to_shost(dev);
598
599 h = shost_to_hba(shost);
46380786 600 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 601}
602
edd16368
SC		 603static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
604{
605 return (scsi3addr[3] & 0xC0) == 0x40;
606}
607
f2ef0ce7
RE		 608static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
609 "1(+0)ADM", "UNKNOWN"
edd16368 610};
6b80b18f
ST		 611#define HPSA_RAID_0 0
612#define HPSA_RAID_4 1
613#define HPSA_RAID_1 2 /* also used for RAID 10 */
614#define HPSA_RAID_5 3 /* also used for RAID 50 */
615#define HPSA_RAID_51 4
616#define HPSA_RAID_6 5 /* also used for RAID 60 */
617#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 618#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
619
620static ssize_t raid_level_show(struct device *dev,
621 struct device_attribute *attr, char *buf)
622{
623 ssize_t l = 0;
82a72c0a 624 unsigned char rlevel;
edd16368
SC		 625 struct ctlr_info *h;
626 struct scsi_device *sdev;
627 struct hpsa_scsi_dev_t *hdev;
628 unsigned long flags;
629
630 sdev = to_scsi_device(dev);
631 h = sdev_to_hba(sdev);
632 spin_lock_irqsave(&h->lock, flags);
633 hdev = sdev->hostdata;
634 if (!hdev) {
635 spin_unlock_irqrestore(&h->lock, flags);
636 return -ENODEV;
637 }
638
639 /* Is this even a logical drive? */
640 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
641 spin_unlock_irqrestore(&h->lock, flags);
642 l = snprintf(buf, PAGE_SIZE, "N/A\n");
643 return l;
644 }
645
646 rlevel = hdev->raid_level;
647 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 648 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 649 rlevel = RAID_UNKNOWN;
650 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
651 return l;
652}
653
654static ssize_t lunid_show(struct device *dev,
655 struct device_attribute *attr, char *buf)
656{
657 struct ctlr_info *h;
658 struct scsi_device *sdev;
659 struct hpsa_scsi_dev_t *hdev;
660 unsigned long flags;
661 unsigned char lunid[8];
662
663 sdev = to_scsi_device(dev);
664 h = sdev_to_hba(sdev);
665 spin_lock_irqsave(&h->lock, flags);
666 hdev = sdev->hostdata;
667 if (!hdev) {
668 spin_unlock_irqrestore(&h->lock, flags);
669 return -ENODEV;
670 }
671 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
672 spin_unlock_irqrestore(&h->lock, flags);
673 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
674 lunid[0], lunid[1], lunid[2], lunid[3],
675 lunid[4], lunid[5], lunid[6], lunid[7]);
676}
677
678static ssize_t unique_id_show(struct device *dev,
679 struct device_attribute *attr, char *buf)
680{
681 struct ctlr_info *h;
682 struct scsi_device *sdev;
683 struct hpsa_scsi_dev_t *hdev;
684 unsigned long flags;
685 unsigned char sn[16];
686
687 sdev = to_scsi_device(dev);
688 h = sdev_to_hba(sdev);
689 spin_lock_irqsave(&h->lock, flags);
690 hdev = sdev->hostdata;
691 if (!hdev) {
692 spin_unlock_irqrestore(&h->lock, flags);
693 return -ENODEV;
694 }
695 memcpy(sn, hdev->device_id, sizeof(sn));
696 spin_unlock_irqrestore(&h->lock, flags);
697 return snprintf(buf, 16 * 2 + 2,
698 "%02X%02X%02X%02X%02X%02X%02X%02X"
699 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
700 sn[0], sn[1], sn[2], sn[3],
701 sn[4], sn[5], sn[6], sn[7],
702 sn[8], sn[9], sn[10], sn[11],
703 sn[12], sn[13], sn[14], sn[15]);
704}
705
c1988684
ST		 706static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
707 struct device_attribute *attr, char *buf)
708{
709 struct ctlr_info *h;
710 struct scsi_device *sdev;
711 struct hpsa_scsi_dev_t *hdev;
712 unsigned long flags;
713 int offload_enabled;
714
715 sdev = to_scsi_device(dev);
716 h = sdev_to_hba(sdev);
717 spin_lock_irqsave(&h->lock, flags);
718 hdev = sdev->hostdata;
719 if (!hdev) {
720 spin_unlock_irqrestore(&h->lock, flags);
721 return -ENODEV;
722 }
723 offload_enabled = hdev->offload_enabled;
724 spin_unlock_irqrestore(&h->lock, flags);
725 return snprintf(buf, 20, "%d\n", offload_enabled);
726}
727
8270b862
JH		 728#define MAX_PATHS 8
729#define PATH_STRING_LEN 50
730
731static ssize_t path_info_show(struct device *dev,
732 struct device_attribute *attr, char *buf)
733{
734 struct ctlr_info *h;
735 struct scsi_device *sdev;
736 struct hpsa_scsi_dev_t *hdev;
737 unsigned long flags;
738 int i;
739 int output_len = 0;
740 u8 box;
741 u8 bay;
742 u8 path_map_index = 0;
743 char *active;
744 unsigned char phys_connector[2];
745 unsigned char path[MAX_PATHS][PATH_STRING_LEN];
746
747 memset(path, 0, MAX_PATHS * PATH_STRING_LEN);
748 sdev = to_scsi_device(dev);
749 h = sdev_to_hba(sdev);
750 spin_lock_irqsave(&h->devlock, flags);
751 hdev = sdev->hostdata;
752 if (!hdev) {
753 spin_unlock_irqrestore(&h->devlock, flags);
754 return -ENODEV;
755 }
756
757 bay = hdev->bay;
758 for (i = 0; i < MAX_PATHS; i++) {
759 path_map_index = 1<<i;
760 if (i == hdev->active_path_index)
761 active = "Active";
762 else if (hdev->path_map & path_map_index)
763 active = "Inactive";
764 else
765 continue;
766
767 output_len = snprintf(path[i],
768 PATH_STRING_LEN, "[%d:%d:%d:%d] %20.20s ",
769 h->scsi_host->host_no,
770 hdev->bus, hdev->target, hdev->lun,
771 scsi_device_type(hdev->devtype));
772
773 if (is_ext_target(h, hdev) ||
774 (hdev->devtype == TYPE_RAID) ||
775 is_logical_dev_addr_mode(hdev->scsi3addr)) {
776 output_len += snprintf(path[i] + output_len,
777 PATH_STRING_LEN, "%s\n",
778 active);
779 continue;
780 }
781
782 box = hdev->box[i];
783 memcpy(&phys_connector, &hdev->phys_connector[i],
784 sizeof(phys_connector));
785 if (phys_connector[0] < '0')
786 phys_connector[0] = '0';
787 if (phys_connector[1] < '0')
788 phys_connector[1] = '0';
789 if (hdev->phys_connector[i] > 0)
790 output_len += snprintf(path[i] + output_len,
791 PATH_STRING_LEN,
792 "PORT: %.2s ",
793 phys_connector);
b9092b79
KB		 794 if (hdev->devtype == TYPE_DISK &&
795 hdev->expose_state != HPSA_DO_NOT_EXPOSE) {
8270b862
JH		 796 if (box == 0 || box == 0xFF) {
797 output_len += snprintf(path[i] + output_len,
798 PATH_STRING_LEN,
799 "BAY: %hhu %s\n",
800 bay, active);
801 } else {
802 output_len += snprintf(path[i] + output_len,
803 PATH_STRING_LEN,
804 "BOX: %hhu BAY: %hhu %s\n",
805 box, bay, active);
806 }
807 } else if (box != 0 && box != 0xFF) {
808 output_len += snprintf(path[i] + output_len,
809 PATH_STRING_LEN, "BOX: %hhu %s\n",
810 box, active);
811 } else
812 output_len += snprintf(path[i] + output_len,
813 PATH_STRING_LEN, "%s\n", active);
814 }
815
816 spin_unlock_irqrestore(&h->devlock, flags);
817 return snprintf(buf, output_len+1, "%s%s%s%s%s%s%s%s",
818 path[0], path[1], path[2], path[3],
819 path[4], path[5], path[6], path[7]);
820}
821
3f5eac3a
SC		 822static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
823static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
824static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
825static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 826static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
827 host_show_hp_ssd_smart_path_enabled, NULL);
8270b862 828static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
da0697bd
ST		 829static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
830 host_show_hp_ssd_smart_path_status,
831 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 832static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
833 host_store_raid_offload_debug);
3f5eac3a
SC		 834static DEVICE_ATTR(firmware_revision, S_IRUGO,
835 host_show_firmware_revision, NULL);
836static DEVICE_ATTR(commands_outstanding, S_IRUGO,
837 host_show_commands_outstanding, NULL);
838static DEVICE_ATTR(transport_mode, S_IRUGO,
839 host_show_transport_mode, NULL);
941b1cda
SC		 840static DEVICE_ATTR(resettable, S_IRUGO,
841 host_show_resettable, NULL);
e985c58f
SC		 842static DEVICE_ATTR(lockup_detected, S_IRUGO,
843 host_show_lockup_detected, NULL);
3f5eac3a
SC		 844
845static struct device_attribute *hpsa_sdev_attrs[] = {
846 &dev_attr_raid_level,
847 &dev_attr_lunid,
848 &dev_attr_unique_id,
c1988684 849 &dev_attr_hp_ssd_smart_path_enabled,
8270b862 850 &dev_attr_path_info,
e985c58f 851 &dev_attr_lockup_detected,
3f5eac3a
SC		 852 NULL,
853};
854
855static struct device_attribute *hpsa_shost_attrs[] = {
856 &dev_attr_rescan,
857 &dev_attr_firmware_revision,
858 &dev_attr_commands_outstanding,
859 &dev_attr_transport_mode,
941b1cda 860 &dev_attr_resettable,
da0697bd 861 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 862 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 863 NULL,
864};
865
41ce4c35
SC		 866#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
867 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
868
3f5eac3a
SC		 869static struct scsi_host_template hpsa_driver_template = {
870 .module = THIS_MODULE,
f79cfec6
SC		 871 .name = HPSA,
872 .proc_name = HPSA,
3f5eac3a
SC		 873 .queuecommand = hpsa_scsi_queue_command,
874 .scan_start = hpsa_scan_start,
875 .scan_finished = hpsa_scan_finished,
7c0a0229 876 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 877 .this_id = -1,
878 .use_clustering = ENABLE_CLUSTERING,
75167d2c 879 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 880 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
881 .ioctl = hpsa_ioctl,
882 .slave_alloc = hpsa_slave_alloc,
41ce4c35 883 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 884 .slave_destroy = hpsa_slave_destroy,
885#ifdef CONFIG_COMPAT
886 .compat_ioctl = hpsa_compat_ioctl,
887#endif
888 .sdev_attrs = hpsa_sdev_attrs,
889 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 890 .max_sectors = 8192,
54b2b50c 891 .no_write_same = 1,
3f5eac3a
SC		 892};
893
254f796b 894static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 895{
896 u32 a;
072b0518 897 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 898
e1f7de0c
MG		 899 if (h->transMethod & CFGTBL_Trans_io_accel1)
900 return h->access.command_completed(h, q);
901
3f5eac3a 902 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 903 return h->access.command_completed(h, q);
3f5eac3a 904
254f796b
MG		 905 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
906 a = rq->head[rq->current_entry];
907 rq->current_entry++;
0cbf768e 908 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 909 } else {
910 a = FIFO_EMPTY;
911 }
912 /* Check for wraparound */
254f796b
MG		 913 if (rq->current_entry == h->max_commands) {
914 rq->current_entry = 0;
915 rq->wraparound ^= 1;
3f5eac3a
SC		 916 }
917 return a;
918}
919
c349775e
ST		 920/*
921 * There are some special bits in the bus address of the
922 * command that we have to set for the controller to know
923 * how to process the command:
924 *
925 * Normal performant mode:
926 * bit 0: 1 means performant mode, 0 means simple mode.
927 * bits 1-3 = block fetch table entry
928 * bits 4-6 = command type (== 0)
929 *
930 * ioaccel1 mode:
931 * bit 0 = "performant mode" bit.
932 * bits 1-3 = block fetch table entry
933 * bits 4-6 = command type (== 110)
934 * (command type is needed because ioaccel1 mode
935 * commands are submitted through the same register as normal
936 * mode commands, so this is how the controller knows whether
937 * the command is normal mode or ioaccel1 mode.)
938 *
939 * ioaccel2 mode:
940 * bit 0 = "performant mode" bit.
941 * bits 1-4 = block fetch table entry (note extra bit)
942 * bits 4-6 = not needed, because ioaccel2 mode has
943 * a separate special register for submitting commands.
944 */
945
25163bd5
WS		 946/*
947 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 948 * set bit 0 for pull model, bits 3-1 for block fetch
949 * register number
950 */
25163bd5
WS		 951#define DEFAULT_REPLY_QUEUE (-1)
952static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
953 int reply_queue)
3f5eac3a 954{
254f796b 955 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 956 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 957 if (unlikely(!h->msix_vector))
958 return;
959 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 960 c->Header.ReplyQueue =
804a5cb5 961 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 962 else
963 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 964 }
3f5eac3a
SC		 965}
966
c349775e 967static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 968 struct CommandList *c,
969 int reply_queue)
c349775e
ST		 970{
971 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
972
25163bd5
WS		 973 /*
974 * Tell the controller to post the reply to the queue for this
c349775e
ST		 975 * processor. This seems to give the best I/O throughput.
976 */
25163bd5
WS		 977 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
978 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
979 else
980 cp->ReplyQueue = reply_queue % h->nreply_queues;
981 /*
982 * Set the bits in the address sent down to include:
c349775e
ST		 983 * - performant mode bit (bit 0)
984 * - pull count (bits 1-3)
985 * - command type (bits 4-6)
986 */
987 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
988 IOACCEL1_BUSADDR_CMDTYPE;
989}
990
8be986cc
SC		 991static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
992 struct CommandList *c,
993 int reply_queue)
994{
995 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
996 &h->ioaccel2_cmd_pool[c->cmdindex];
997
998 /* Tell the controller to post the reply to the queue for this
999 * processor. This seems to give the best I/O throughput.
1000 */
1001 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1002 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1003 else
1004 cp->reply_queue = reply_queue % h->nreply_queues;
1005 /* Set the bits in the address sent down to include:
1006 * - performant mode bit not used in ioaccel mode 2
1007 * - pull count (bits 0-3)
1008 * - command type isn't needed for ioaccel2
1009 */
1010 c->busaddr |= h->ioaccel2_blockFetchTable[0];
1011}
1012
c349775e 1013static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1014 struct CommandList *c,
1015 int reply_queue)
c349775e
ST		 1016{
1017 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
1018
25163bd5
WS		 1019 /*
1020 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1021 * processor. This seems to give the best I/O throughput.
1022 */
25163bd5
WS		 1023 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1024 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1025 else
1026 cp->reply_queue = reply_queue % h->nreply_queues;
1027 /*
1028 * Set the bits in the address sent down to include:
c349775e
ST		 1029 * - performant mode bit not used in ioaccel mode 2
1030 * - pull count (bits 0-3)
1031 * - command type isn't needed for ioaccel2
1032 */
1033 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
1034}
1035
e85c5974
SC		 1036static int is_firmware_flash_cmd(u8 *cdb)
1037{
1038 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
1039}
1040
1041/*
1042 * During firmware flash, the heartbeat register may not update as frequently
1043 * as it should. So we dial down lockup detection during firmware flash. and
1044 * dial it back up when firmware flash completes.
1045 */
1046#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
1047#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
1048static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
1049 struct CommandList *c)
1050{
1051 if (!is_firmware_flash_cmd(c->Request.CDB))
1052 return;
1053 atomic_inc(&h->firmware_flash_in_progress);
1054 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
1055}
1056
1057static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
1058 struct CommandList *c)
1059{
1060 if (is_firmware_flash_cmd(c->Request.CDB) &&
1061 atomic_dec_and_test(&h->firmware_flash_in_progress))
1062 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
1063}
1064
25163bd5
WS		 1065static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
1066 struct CommandList *c, int reply_queue)
3f5eac3a 1067{
c05e8866
SC		 1068 dial_down_lockup_detection_during_fw_flash(h, c);
1069 atomic_inc(&h->commands_outstanding);
c349775e
ST		 1070 switch (c->cmd_type) {
1071 case CMD_IOACCEL1:
25163bd5 1072 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 1073 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 1074 break;
1075 case CMD_IOACCEL2:
25163bd5 1076 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 1077 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e 1078 break;
8be986cc
SC		 1079 case IOACCEL2_TMF:
1080 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
1081 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1082 break;
c349775e 1083 default:
25163bd5 1084 set_performant_mode(h, c, reply_queue);
c05e8866 1085 h->access.submit_command(h, c);
c349775e 1086 }
3f5eac3a
SC		 1087}
1088
a58e7e53 1089static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
25163bd5 1090{
d604f533 1091 if (unlikely(hpsa_is_pending_event(c)))
a58e7e53
WS		 1092 return finish_cmd(c);
1093
25163bd5
WS		 1094 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
1095}
1096
3f5eac3a
SC		 1097static inline int is_hba_lunid(unsigned char scsi3addr[])
1098{
1099 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
1100}
1101
1102static inline int is_scsi_rev_5(struct ctlr_info *h)
1103{
1104 if (!h->hba_inquiry_data)
1105 return 0;
1106 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1107 return 1;
1108 return 0;
1109}
1110
edd16368
SC		 1111static int hpsa_find_target_lun(struct ctlr_info *h,
1112 unsigned char scsi3addr[], int bus, int *target, int *lun)
1113{
1114 /* finds an unused bus, target, lun for a new physical device
1115 * assumes h->devlock is held
1116 */
1117 int i, found = 0;
cfe5badc 1118 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 1119
263d9401 1120 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 1121
1122 for (i = 0; i < h->ndevices; i++) {
1123 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 1124 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 1125 }
1126
263d9401
AM		 1127 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1128 if (i < HPSA_MAX_DEVICES) {
1129 /* *bus = 1; */
1130 *target = i;
1131 *lun = 0;
1132 found = 1;
edd16368
SC		 1133 }
1134 return !found;
1135}
1136
0d96ef5f
WS		 1137static inline void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
1138 struct hpsa_scsi_dev_t *dev, char *description)
1139{
1140 dev_printk(level, &h->pdev->dev,
1141 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
1142 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1143 description,
1144 scsi_device_type(dev->devtype),
1145 dev->vendor,
1146 dev->model,
1147 dev->raid_level > RAID_UNKNOWN ?
1148 "RAID-?" : raid_label[dev->raid_level],
1149 dev->offload_config ? '+' : '-',
1150 dev->offload_enabled ? '+' : '-',
1151 dev->expose_state);
1152}
1153
edd16368
SC		 1154/* Add an entry into h->dev[] array. */
1155static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
1156 struct hpsa_scsi_dev_t *device,
1157 struct hpsa_scsi_dev_t *added[], int *nadded)
1158{
1159 /* assumes h->devlock is held */
1160 int n = h->ndevices;
1161 int i;
1162 unsigned char addr1[8], addr2[8];
1163 struct hpsa_scsi_dev_t *sd;
1164
cfe5badc 1165 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1166 dev_err(&h->pdev->dev, "too many devices, some will be "
1167 "inaccessible.\n");
1168 return -1;
1169 }
1170
1171 /* physical devices do not have lun or target assigned until now. */
1172 if (device->lun != -1)
1173 /* Logical device, lun is already assigned. */
1174 goto lun_assigned;
1175
1176 /* If this device a non-zero lun of a multi-lun device
1177 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1178 * unit no, zero otherwise.
edd16368
SC		 1179 */
1180 if (device->scsi3addr[4] == 0) {
1181 /* This is not a non-zero lun of a multi-lun device */
1182 if (hpsa_find_target_lun(h, device->scsi3addr,
1183 device->bus, &device->target, &device->lun) != 0)
1184 return -1;
1185 goto lun_assigned;
1186 }
1187
1188 /* This is a non-zero lun of a multi-lun device.
1189 * Search through our list and find the device which
1190 * has the same 8 byte LUN address, excepting byte 4.
1191 * Assign the same bus and target for this new LUN.
1192 * Use the logical unit number from the firmware.
1193 */
1194 memcpy(addr1, device->scsi3addr, 8);
1195 addr1[4] = 0;
1196 for (i = 0; i < n; i++) {
1197 sd = h->dev[i];
1198 memcpy(addr2, sd->scsi3addr, 8);
1199 addr2[4] = 0;
1200 /* differ only in byte 4? */
1201 if (memcmp(addr1, addr2, 8) == 0) {
1202 device->bus = sd->bus;
1203 device->target = sd->target;
1204 device->lun = device->scsi3addr[4];
1205 break;
1206 }
1207 }
1208 if (device->lun == -1) {
1209 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1210 " suspect firmware bug or unsupported hardware "
1211 "configuration.\n");
1212 return -1;
1213 }
1214
1215lun_assigned:
1216
1217 h->dev[n] = device;
1218 h->ndevices++;
1219 added[*nadded] = device;
1220 (*nadded)++;
0d96ef5f
WS		 1221 hpsa_show_dev_msg(KERN_INFO, h, device,
1222 device->expose_state & HPSA_SCSI_ADD ? "added" : "masked");
a473d86c
RE		 1223 device->offload_to_be_enabled = device->offload_enabled;
1224 device->offload_enabled = 0;
edd16368
SC		 1225 return 0;
1226}
1227
bd9244f7
ST		 1228/* Update an entry in h->dev[] array. */
1229static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
1230 int entry, struct hpsa_scsi_dev_t *new_entry)
1231{
a473d86c 1232 int offload_enabled;
bd9244f7
ST		 1233 /* assumes h->devlock is held */
1234 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1235
1236 /* Raid level changed. */
1237 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1238
03383736
DB		 1239 /* Raid offload parameters changed. Careful about the ordering. */
1240 if (new_entry->offload_config && new_entry->offload_enabled) {
1241 /*
1242 * if drive is newly offload_enabled, we want to copy the
1243 * raid map data first. If previously offload_enabled and
1244 * offload_config were set, raid map data had better be
1245 * the same as it was before. if raid map data is changed
1246 * then it had better be the case that
1247 * h->dev[entry]->offload_enabled is currently 0.
1248 */
1249 h->dev[entry]->raid_map = new_entry->raid_map;
1250 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1251 }
a3144e0b
JH		 1252 if (new_entry->hba_ioaccel_enabled) {
1253 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1254 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1255 }
1256 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1257 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1258 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1259 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1260
41ce4c35
SC		 1261 /*
1262 * We can turn off ioaccel offload now, but need to delay turning
1263 * it on until we can update h->dev[entry]->phys_disk[], but we
1264 * can't do that until all the devices are updated.
1265 */
1266 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1267 if (!new_entry->offload_enabled)
1268 h->dev[entry]->offload_enabled = 0;
1269
a473d86c
RE		 1270 offload_enabled = h->dev[entry]->offload_enabled;
1271 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1272 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1273 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1274}
1275
2a8ccf31
SC		 1276/* Replace an entry from h->dev[] array. */
1277static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
1278 int entry, struct hpsa_scsi_dev_t *new_entry,
1279 struct hpsa_scsi_dev_t *added[], int *nadded,
1280 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1281{
1282 /* assumes h->devlock is held */
cfe5badc 1283 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1284 removed[*nremoved] = h->dev[entry];
1285 (*nremoved)++;
01350d05
SC		 1286
1287 /*
1288 * New physical devices won't have target/lun assigned yet
1289 * so we need to preserve the values in the slot we are replacing.
1290 */
1291 if (new_entry->target == -1) {
1292 new_entry->target = h->dev[entry]->target;
1293 new_entry->lun = h->dev[entry]->lun;
1294 }
1295
2a8ccf31
SC		 1296 h->dev[entry] = new_entry;
1297 added[*nadded] = new_entry;
1298 (*nadded)++;
0d96ef5f 1299 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1300 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1301 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1302}
1303
edd16368
SC		 1304/* Remove an entry from h->dev[] array. */
1305static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1306 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1307{
1308 /* assumes h->devlock is held */
1309 int i;
1310 struct hpsa_scsi_dev_t *sd;
1311
cfe5badc 1312 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1313
1314 sd = h->dev[entry];
1315 removed[*nremoved] = h->dev[entry];
1316 (*nremoved)++;
1317
1318 for (i = entry; i < h->ndevices-1; i++)
1319 h->dev[i] = h->dev[i+1];
1320 h->ndevices--;
0d96ef5f 1321 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1322}
1323
1324#define SCSI3ADDR_EQ(a, b) ( \
1325 (a)[7] == (b)[7] && \
1326 (a)[6] == (b)[6] && \
1327 (a)[5] == (b)[5] && \
1328 (a)[4] == (b)[4] && \
1329 (a)[3] == (b)[3] && \
1330 (a)[2] == (b)[2] && \
1331 (a)[1] == (b)[1] && \
1332 (a)[0] == (b)[0])
1333
1334static void fixup_botched_add(struct ctlr_info *h,
1335 struct hpsa_scsi_dev_t *added)
1336{
1337 /* called when scsi_add_device fails in order to re-adjust
1338 * h->dev[] to match the mid layer's view.
1339 */
1340 unsigned long flags;
1341 int i, j;
1342
1343 spin_lock_irqsave(&h->lock, flags);
1344 for (i = 0; i < h->ndevices; i++) {
1345 if (h->dev[i] == added) {
1346 for (j = i; j < h->ndevices-1; j++)
1347 h->dev[j] = h->dev[j+1];
1348 h->ndevices--;
1349 break;
1350 }
1351 }
1352 spin_unlock_irqrestore(&h->lock, flags);
1353 kfree(added);
1354}
1355
1356static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1357 struct hpsa_scsi_dev_t *dev2)
1358{
edd16368
SC		 1359 /* we compare everything except lun and target as these
1360 * are not yet assigned. Compare parts likely
1361 * to differ first
1362 */
1363 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1364 sizeof(dev1->scsi3addr)) != 0)
1365 return 0;
1366 if (memcmp(dev1->device_id, dev2->device_id,
1367 sizeof(dev1->device_id)) != 0)
1368 return 0;
1369 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1370 return 0;
1371 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1372 return 0;
edd16368
SC		 1373 if (dev1->devtype != dev2->devtype)
1374 return 0;
edd16368
SC		 1375 if (dev1->bus != dev2->bus)
1376 return 0;
1377 return 1;
1378}
1379
bd9244f7
ST		 1380static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1381 struct hpsa_scsi_dev_t *dev2)
1382{
1383 /* Device attributes that can change, but don't mean
1384 * that the device is a different device, nor that the OS
1385 * needs to be told anything about the change.
1386 */
1387 if (dev1->raid_level != dev2->raid_level)
1388 return 1;
250fb125
SC		 1389 if (dev1->offload_config != dev2->offload_config)
1390 return 1;
1391 if (dev1->offload_enabled != dev2->offload_enabled)
1392 return 1;
93849508
DB		 1393 if (!is_logical_dev_addr_mode(dev1->scsi3addr))
1394 if (dev1->queue_depth != dev2->queue_depth)
1395 return 1;
bd9244f7
ST		 1396 return 0;
1397}
1398
edd16368
SC		 1399/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1400 * and return needle location in *index. If scsi3addr matches, but not
1401 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1402 * location in *index.
1403 * In the case of a minor device attribute change, such as RAID level, just
1404 * return DEVICE_UPDATED, along with the updated device's location in index.
1405 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1406 */
1407static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1408 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1409 int *index)
1410{
1411 int i;
1412#define DEVICE_NOT_FOUND 0
1413#define DEVICE_CHANGED 1
1414#define DEVICE_SAME 2
bd9244f7 1415#define DEVICE_UPDATED 3
edd16368 1416 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1417 if (haystack[i] == NULL) /* previously removed. */
1418 continue;
edd16368
SC		 1419 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1420 *index = i;
bd9244f7
ST		 1421 if (device_is_the_same(needle, haystack[i])) {
1422 if (device_updated(needle, haystack[i]))
1423 return DEVICE_UPDATED;
edd16368 1424 return DEVICE_SAME;
bd9244f7 1425 } else {
9846590e
SC		 1426 /* Keep offline devices offline */
1427 if (needle->volume_offline)
1428 return DEVICE_NOT_FOUND;
edd16368 1429 return DEVICE_CHANGED;
bd9244f7 1430 }
edd16368
SC		 1431 }
1432 }
1433 *index = -1;
1434 return DEVICE_NOT_FOUND;
1435}
1436
9846590e
SC		 1437static void hpsa_monitor_offline_device(struct ctlr_info *h,
1438 unsigned char scsi3addr[])
1439{
1440 struct offline_device_entry *device;
1441 unsigned long flags;
1442
1443 /* Check to see if device is already on the list */
1444 spin_lock_irqsave(&h->offline_device_lock, flags);
1445 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1446 if (memcmp(device->scsi3addr, scsi3addr,
1447 sizeof(device->scsi3addr)) == 0) {
1448 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1449 return;
1450 }
1451 }
1452 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1453
1454 /* Device is not on the list, add it. */
1455 device = kmalloc(sizeof(*device), GFP_KERNEL);
1456 if (!device) {
1457 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1458 return;
1459 }
1460 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1461 spin_lock_irqsave(&h->offline_device_lock, flags);
1462 list_add_tail(&device->offline_list, &h->offline_device_list);
1463 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1464}
1465
1466/* Print a message explaining various offline volume states */
1467static void hpsa_show_volume_status(struct ctlr_info *h,
1468 struct hpsa_scsi_dev_t *sd)
1469{
1470 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1471 dev_info(&h->pdev->dev,
1472 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1473 h->scsi_host->host_no,
1474 sd->bus, sd->target, sd->lun);
1475 switch (sd->volume_offline) {
1476 case HPSA_LV_OK:
1477 break;
1478 case HPSA_LV_UNDERGOING_ERASE:
1479 dev_info(&h->pdev->dev,
1480 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1481 h->scsi_host->host_no,
1482 sd->bus, sd->target, sd->lun);
1483 break;
1484 case HPSA_LV_UNDERGOING_RPI:
1485 dev_info(&h->pdev->dev,
1486 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1487 h->scsi_host->host_no,
1488 sd->bus, sd->target, sd->lun);
1489 break;
1490 case HPSA_LV_PENDING_RPI:
1491 dev_info(&h->pdev->dev,
1492 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1493 h->scsi_host->host_no,
1494 sd->bus, sd->target, sd->lun);
1495 break;
1496 case HPSA_LV_ENCRYPTED_NO_KEY:
1497 dev_info(&h->pdev->dev,
1498 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1499 h->scsi_host->host_no,
1500 sd->bus, sd->target, sd->lun);
1501 break;
1502 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1503 dev_info(&h->pdev->dev,
1504 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1505 h->scsi_host->host_no,
1506 sd->bus, sd->target, sd->lun);
1507 break;
1508 case HPSA_LV_UNDERGOING_ENCRYPTION:
1509 dev_info(&h->pdev->dev,
1510 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1511 h->scsi_host->host_no,
1512 sd->bus, sd->target, sd->lun);
1513 break;
1514 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1515 dev_info(&h->pdev->dev,
1516 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1517 h->scsi_host->host_no,
1518 sd->bus, sd->target, sd->lun);
1519 break;
1520 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1521 dev_info(&h->pdev->dev,
1522 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1523 h->scsi_host->host_no,
1524 sd->bus, sd->target, sd->lun);
1525 break;
1526 case HPSA_LV_PENDING_ENCRYPTION:
1527 dev_info(&h->pdev->dev,
1528 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1529 h->scsi_host->host_no,
1530 sd->bus, sd->target, sd->lun);
1531 break;
1532 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1533 dev_info(&h->pdev->dev,
1534 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1535 h->scsi_host->host_no,
1536 sd->bus, sd->target, sd->lun);
1537 break;
1538 }
1539}
1540
03383736
DB		 1541/*
1542 * Figure the list of physical drive pointers for a logical drive with
1543 * raid offload configured.
1544 */
1545static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1546 struct hpsa_scsi_dev_t *dev[], int ndevices,
1547 struct hpsa_scsi_dev_t *logical_drive)
1548{
1549 struct raid_map_data *map = &logical_drive->raid_map;
1550 struct raid_map_disk_data *dd = &map->data[0];
1551 int i, j;
1552 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1553 le16_to_cpu(map->metadata_disks_per_row);
1554 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1555 le16_to_cpu(map->layout_map_count) *
1556 total_disks_per_row;
1557 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1558 total_disks_per_row;
1559 int qdepth;
1560
1561 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1562 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1563
d604f533
WS		 1564 logical_drive->nphysical_disks = nraid_map_entries;
1565
03383736
DB		 1566 qdepth = 0;
1567 for (i = 0; i < nraid_map_entries; i++) {
1568 logical_drive->phys_disk[i] = NULL;
1569 if (!logical_drive->offload_config)
1570 continue;
1571 for (j = 0; j < ndevices; j++) {
1572 if (dev[j]->devtype != TYPE_DISK)
1573 continue;
1574 if (is_logical_dev_addr_mode(dev[j]->scsi3addr))
1575 continue;
1576 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1577 continue;
1578
1579 logical_drive->phys_disk[i] = dev[j];
1580 if (i < nphys_disk)
1581 qdepth = min(h->nr_cmds, qdepth +
1582 logical_drive->phys_disk[i]->queue_depth);
1583 break;
1584 }
1585
1586 /*
1587 * This can happen if a physical drive is removed and
1588 * the logical drive is degraded. In that case, the RAID
1589 * map data will refer to a physical disk which isn't actually
1590 * present. And in that case offload_enabled should already
1591 * be 0, but we'll turn it off here just in case
1592 */
1593 if (!logical_drive->phys_disk[i]) {
1594 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1595 logical_drive->offload_to_be_enabled = 0;
1596 logical_drive->queue_depth = 8;
03383736
DB		 1597 }
1598 }
1599 if (nraid_map_entries)
1600 /*
1601 * This is correct for reads, too high for full stripe writes,
1602 * way too high for partial stripe writes
1603 */
1604 logical_drive->queue_depth = qdepth;
1605 else
1606 logical_drive->queue_depth = h->nr_cmds;
1607}
1608
1609static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1610 struct hpsa_scsi_dev_t *dev[], int ndevices)
1611{
1612 int i;
1613
1614 for (i = 0; i < ndevices; i++) {
1615 if (dev[i]->devtype != TYPE_DISK)
1616 continue;
1617 if (!is_logical_dev_addr_mode(dev[i]->scsi3addr))
1618 continue;
41ce4c35
SC		 1619
1620 /*
1621 * If offload is currently enabled, the RAID map and
1622 * phys_disk[] assignment *better* not be changing
1623 * and since it isn't changing, we do not need to
1624 * update it.
1625 */
1626 if (dev[i]->offload_enabled)
1627 continue;
1628
03383736
DB		 1629 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1630 }
1631}
1632
4967bd3e 1633static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1634 struct hpsa_scsi_dev_t *sd[], int nsds)
1635{
1636 /* sd contains scsi3 addresses and devtypes, and inquiry
1637 * data. This function takes what's in sd to be the current
1638 * reality and updates h->dev[] to reflect that reality.
1639 */
1640 int i, entry, device_change, changes = 0;
1641 struct hpsa_scsi_dev_t *csd;
1642 unsigned long flags;
1643 struct hpsa_scsi_dev_t **added, **removed;
1644 int nadded, nremoved;
1645 struct Scsi_Host *sh = NULL;
1646
cfe5badc
ST		 1647 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1648 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1649
1650 if (!added || !removed) {
1651 dev_warn(&h->pdev->dev, "out of memory in "
1652 "adjust_hpsa_scsi_table\n");
1653 goto free_and_out;
1654 }
1655
1656 spin_lock_irqsave(&h->devlock, flags);
1657
1658 /* find any devices in h->dev[] that are not in
1659 * sd[] and remove them from h->dev[], and for any
1660 * devices which have changed, remove the old device
1661 * info and add the new device info.
bd9244f7
ST		 1662 * If minor device attributes change, just update
1663 * the existing device structure.
edd16368
SC		 1664 */
1665 i = 0;
1666 nremoved = 0;
1667 nadded = 0;
1668 while (i < h->ndevices) {
1669 csd = h->dev[i];
1670 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1671 if (device_change == DEVICE_NOT_FOUND) {
1672 changes++;
1673 hpsa_scsi_remove_entry(h, hostno, i,
1674 removed, &nremoved);
1675 continue; /* remove ^^^, hence i not incremented */
1676 } else if (device_change == DEVICE_CHANGED) {
1677 changes++;
2a8ccf31
SC		 1678 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1679 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1680 /* Set it to NULL to prevent it from being freed
1681 * at the bottom of hpsa_update_scsi_devices()
1682 */
1683 sd[entry] = NULL;
bd9244f7
ST		 1684 } else if (device_change == DEVICE_UPDATED) {
1685 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1686 }
1687 i++;
1688 }
1689
1690 /* Now, make sure every device listed in sd[] is also
1691 * listed in h->dev[], adding them if they aren't found
1692 */
1693
1694 for (i = 0; i < nsds; i++) {
1695 if (!sd[i]) /* if already added above. */
1696 continue;
9846590e
SC		 1697
1698 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1699 * as the SCSI mid-layer does not handle such devices well.
1700 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1701 * at 160Hz, and prevents the system from coming up.
1702 */
1703 if (sd[i]->volume_offline) {
1704 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1705 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1706 continue;
1707 }
1708
edd16368
SC		 1709 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1710 h->ndevices, &entry);
1711 if (device_change == DEVICE_NOT_FOUND) {
1712 changes++;
1713 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1714 added, &nadded) != 0)
1715 break;
1716 sd[i] = NULL; /* prevent from being freed later. */
1717 } else if (device_change == DEVICE_CHANGED) {
1718 /* should never happen... */
1719 changes++;
1720 dev_warn(&h->pdev->dev,
1721 "device unexpectedly changed.\n");
1722 /* but if it does happen, we just ignore that device */
1723 }
1724 }
41ce4c35
SC		 1725 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1726
1727 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1728 * any logical drives that need it enabled.
1729 */
1730 for (i = 0; i < h->ndevices; i++)
1731 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1732
edd16368
SC		 1733 spin_unlock_irqrestore(&h->devlock, flags);
1734
9846590e
SC		 1735 /* Monitor devices which are in one of several NOT READY states to be
1736 * brought online later. This must be done without holding h->devlock,
1737 * so don't touch h->dev[]
1738 */
1739 for (i = 0; i < nsds; i++) {
1740 if (!sd[i]) /* if already added above. */
1741 continue;
1742 if (sd[i]->volume_offline)
1743 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1744 }
1745
edd16368
SC		 1746 /* Don't notify scsi mid layer of any changes the first time through
1747 * (or if there are no changes) scsi_scan_host will do it later the
1748 * first time through.
1749 */
1750 if (hostno == -1 || !changes)
1751 goto free_and_out;
1752
1753 sh = h->scsi_host;
1754 /* Notify scsi mid layer of any removed devices */
1755 for (i = 0; i < nremoved; i++) {
41ce4c35
SC		 1756 if (removed[i]->expose_state & HPSA_SCSI_ADD) {
1757 struct scsi_device *sdev =
1758 scsi_device_lookup(sh, removed[i]->bus,
1759 removed[i]->target, removed[i]->lun);
1760 if (sdev != NULL) {
1761 scsi_remove_device(sdev);
1762 scsi_device_put(sdev);
1763 } else {
1764 /*
1765 * We don't expect to get here.
1766 * future cmds to this device will get selection
1767 * timeout as if the device was gone.
1768 */
0d96ef5f
WS		 1769 hpsa_show_dev_msg(KERN_WARNING, h, removed[i],
1770 "didn't find device for removal.");
41ce4c35 1771 }
edd16368
SC		 1772 }
1773 kfree(removed[i]);
1774 removed[i] = NULL;
1775 }
1776
1777 /* Notify scsi mid layer of any added devices */
1778 for (i = 0; i < nadded; i++) {
41ce4c35
SC		 1779 if (!(added[i]->expose_state & HPSA_SCSI_ADD))
1780 continue;
edd16368
SC		 1781 if (scsi_add_device(sh, added[i]->bus,
1782 added[i]->target, added[i]->lun) == 0)
1783 continue;
0d96ef5f
WS		 1784 hpsa_show_dev_msg(KERN_WARNING, h, added[i],
1785 "addition failed, device not added.");
edd16368
SC		 1786 /* now we have to remove it from h->dev,
1787 * since it didn't get added to scsi mid layer
1788 */
1789 fixup_botched_add(h, added[i]);
105a3dbc 1790 added[i] = NULL;
edd16368
SC		 1791 }
1792
1793free_and_out:
1794 kfree(added);
1795 kfree(removed);
edd16368
SC		 1796}
1797
1798/*
9e03aa2f 1799 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1800 * Assume's h->devlock is held.
1801 */
1802static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1803 int bus, int target, int lun)
1804{
1805 int i;
1806 struct hpsa_scsi_dev_t *sd;
1807
1808 for (i = 0; i < h->ndevices; i++) {
1809 sd = h->dev[i];
1810 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1811 return sd;
1812 }
1813 return NULL;
1814}
1815
edd16368
SC		 1816static int hpsa_slave_alloc(struct scsi_device *sdev)
1817{
1818 struct hpsa_scsi_dev_t *sd;
1819 unsigned long flags;
1820 struct ctlr_info *h;
1821
1822 h = sdev_to_hba(sdev);
1823 spin_lock_irqsave(&h->devlock, flags);
1824 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1825 sdev_id(sdev), sdev->lun);
41ce4c35 1826 if (likely(sd)) {
03383736 1827 atomic_set(&sd->ioaccel_cmds_out, 0);
41ce4c35
SC		 1828 sdev->hostdata = (sd->expose_state & HPSA_SCSI_ADD) ? sd : NULL;
1829 } else
1830 sdev->hostdata = NULL;
edd16368
SC		 1831 spin_unlock_irqrestore(&h->devlock, flags);
1832 return 0;
1833}
1834
41ce4c35
SC		 1835/* configure scsi device based on internal per-device structure */
1836static int hpsa_slave_configure(struct scsi_device *sdev)
1837{
1838 struct hpsa_scsi_dev_t *sd;
1839 int queue_depth;
1840
1841 sd = sdev->hostdata;
1842 sdev->no_uld_attach = !sd || !(sd->expose_state & HPSA_ULD_ATTACH);
1843
1844 if (sd)
1845 queue_depth = sd->queue_depth != 0 ?
1846 sd->queue_depth : sdev->host->can_queue;
1847 else
1848 queue_depth = sdev->host->can_queue;
1849
1850 scsi_change_queue_depth(sdev, queue_depth);
1851
1852 return 0;
1853}
1854
edd16368
SC		 1855static void hpsa_slave_destroy(struct scsi_device *sdev)
1856{
bcc44255 1857 /* nothing to do. */
edd16368
SC		 1858}
1859
d9a729f3
WS		 1860static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1861{
1862 int i;
1863
1864 if (!h->ioaccel2_cmd_sg_list)
1865 return;
1866 for (i = 0; i < h->nr_cmds; i++) {
1867 kfree(h->ioaccel2_cmd_sg_list[i]);
1868 h->ioaccel2_cmd_sg_list[i] = NULL;
1869 }
1870 kfree(h->ioaccel2_cmd_sg_list);
1871 h->ioaccel2_cmd_sg_list = NULL;
1872}
1873
1874static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1875{
1876 int i;
1877
1878 if (h->chainsize <= 0)
1879 return 0;
1880
1881 h->ioaccel2_cmd_sg_list =
1882 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
1883 GFP_KERNEL);
1884 if (!h->ioaccel2_cmd_sg_list)
1885 return -ENOMEM;
1886 for (i = 0; i < h->nr_cmds; i++) {
1887 h->ioaccel2_cmd_sg_list[i] =
1888 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
1889 h->maxsgentries, GFP_KERNEL);
1890 if (!h->ioaccel2_cmd_sg_list[i])
1891 goto clean;
1892 }
1893 return 0;
1894
1895clean:
1896 hpsa_free_ioaccel2_sg_chain_blocks(h);
1897 return -ENOMEM;
1898}
1899
33a2ffce
SC		 1900static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1901{
1902 int i;
1903
1904 if (!h->cmd_sg_list)
1905 return;
1906 for (i = 0; i < h->nr_cmds; i++) {
1907 kfree(h->cmd_sg_list[i]);
1908 h->cmd_sg_list[i] = NULL;
1909 }
1910 kfree(h->cmd_sg_list);
1911 h->cmd_sg_list = NULL;
1912}
1913
105a3dbc 1914static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
33a2ffce
SC		 1915{
1916 int i;
1917
1918 if (h->chainsize <= 0)
1919 return 0;
1920
1921 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1922 GFP_KERNEL);
3d4e6af8
RE		 1923 if (!h->cmd_sg_list) {
1924 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1925 return -ENOMEM;
3d4e6af8 1926 }
33a2ffce
SC		 1927 for (i = 0; i < h->nr_cmds; i++) {
1928 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1929 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1930 if (!h->cmd_sg_list[i]) {
1931 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1932 goto clean;
3d4e6af8 1933 }
33a2ffce
SC		 1934 }
1935 return 0;
1936
1937clean:
1938 hpsa_free_sg_chain_blocks(h);
1939 return -ENOMEM;
1940}
1941
d9a729f3
WS		 1942static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
1943 struct io_accel2_cmd *cp, struct CommandList *c)
1944{
1945 struct ioaccel2_sg_element *chain_block;
1946 u64 temp64;
1947 u32 chain_size;
1948
1949 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
1950 chain_size = le32_to_cpu(cp->data_len);
1951 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
1952 PCI_DMA_TODEVICE);
1953 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1954 /* prevent subsequent unmapping */
1955 cp->sg->address = 0;
1956 return -1;
1957 }
1958 cp->sg->address = cpu_to_le64(temp64);
1959 return 0;
1960}
1961
1962static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
1963 struct io_accel2_cmd *cp)
1964{
1965 struct ioaccel2_sg_element *chain_sg;
1966 u64 temp64;
1967 u32 chain_size;
1968
1969 chain_sg = cp->sg;
1970 temp64 = le64_to_cpu(chain_sg->address);
1971 chain_size = le32_to_cpu(cp->data_len);
1972 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
1973}
1974
e2bea6df 1975static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1976 struct CommandList *c)
1977{
1978 struct SGDescriptor *chain_sg, *chain_block;
1979 u64 temp64;
50a0decf 1980 u32 chain_len;
33a2ffce
SC		 1981
1982 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1983 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 1984 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1985 chain_len = sizeof(*chain_sg) *
2b08b3e9 1986 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 1987 chain_sg->Len = cpu_to_le32(chain_len);
1988 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 1989 PCI_DMA_TODEVICE);
e2bea6df
SC		 1990 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1991 /* prevent subsequent unmapping */
50a0decf 1992 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 1993 return -1;
1994 }
50a0decf 1995 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 1996 return 0;
33a2ffce
SC		 1997}
1998
1999static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
2000 struct CommandList *c)
2001{
2002 struct SGDescriptor *chain_sg;
33a2ffce 2003
50a0decf 2004 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 2005 return;
2006
2007 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 2008 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
2009 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 2010}
2011
a09c1441
ST		 2012
2013/* Decode the various types of errors on ioaccel2 path.
2014 * Return 1 for any error that should generate a RAID path retry.
2015 * Return 0 for errors that don't require a RAID path retry.
2016 */
2017static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 2018 struct CommandList *c,
2019 struct scsi_cmnd *cmd,
2020 struct io_accel2_cmd *c2)
2021{
2022 int data_len;
a09c1441 2023 int retry = 0;
c40820d5 2024 u32 ioaccel2_resid = 0;
c349775e
ST		 2025
2026 switch (c2->error_data.serv_response) {
2027 case IOACCEL2_SERV_RESPONSE_COMPLETE:
2028 switch (c2->error_data.status) {
2029 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
2030 break;
2031 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
ee6b1889 2032 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 2033 if (c2->error_data.data_present !=
ee6b1889
SC		 2034 IOACCEL2_SENSE_DATA_PRESENT) {
2035 memset(cmd->sense_buffer, 0,
2036 SCSI_SENSE_BUFFERSIZE);
c349775e 2037 break;
ee6b1889 2038 }
c349775e
ST		 2039 /* copy the sense data */
2040 data_len = c2->error_data.sense_data_len;
2041 if (data_len > SCSI_SENSE_BUFFERSIZE)
2042 data_len = SCSI_SENSE_BUFFERSIZE;
2043 if (data_len > sizeof(c2->error_data.sense_data_buff))
2044 data_len =
2045 sizeof(c2->error_data.sense_data_buff);
2046 memcpy(cmd->sense_buffer,
2047 c2->error_data.sense_data_buff, data_len);
a09c1441 2048 retry = 1;
c349775e
ST		 2049 break;
2050 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
a09c1441 2051 retry = 1;
c349775e
ST		 2052 break;
2053 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
a09c1441 2054 retry = 1;
c349775e
ST		 2055 break;
2056 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 2057 retry = 1;
c349775e
ST		 2058 break;
2059 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
a09c1441 2060 retry = 1;
c349775e
ST		 2061 break;
2062 default:
a09c1441 2063 retry = 1;
c349775e
ST		 2064 break;
2065 }
2066 break;
2067 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 2068 switch (c2->error_data.status) {
2069 case IOACCEL2_STATUS_SR_IO_ERROR:
2070 case IOACCEL2_STATUS_SR_IO_ABORTED:
2071 case IOACCEL2_STATUS_SR_OVERRUN:
2072 retry = 1;
2073 break;
2074 case IOACCEL2_STATUS_SR_UNDERRUN:
2075 cmd->result = (DID_OK << 16); /* host byte */
2076 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2077 ioaccel2_resid = get_unaligned_le32(
2078 &c2->error_data.resid_cnt[0]);
2079 scsi_set_resid(cmd, ioaccel2_resid);
2080 break;
2081 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
2082 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
2083 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
2084 /* We will get an event from ctlr to trigger rescan */
2085 retry = 1;
2086 break;
2087 default:
2088 retry = 1;
c40820d5 2089 }
c349775e
ST		 2090 break;
2091 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
2092 break;
2093 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
2094 break;
2095 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
a09c1441 2096 retry = 1;
c349775e
ST		 2097 break;
2098 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
c349775e
ST		 2099 break;
2100 default:
a09c1441 2101 retry = 1;
c349775e
ST		 2102 break;
2103 }
a09c1441
ST		 2104
2105 return retry; /* retry on raid path? */
c349775e
ST		 2106}
2107
a58e7e53
WS		 2108static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2109 struct CommandList *c)
2110{
d604f533
WS		 2111 bool do_wake = false;
2112
a58e7e53
WS		 2113 /*
2114 * Prevent the following race in the abort handler:
2115 *
2116 * 1. LLD is requested to abort a SCSI command
2117 * 2. The SCSI command completes
2118 * 3. The struct CommandList associated with step 2 is made available
2119 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2120 * 5. Abort handler follows scsi_cmnd->host_scribble and
2121 * finds struct CommandList and tries to aborts it
2122 * Now we have aborted the wrong command.
2123 *
d604f533
WS		 2124 * Reset c->scsi_cmd here so that the abort or reset handler will know
2125 * this command has completed. Then, check to see if the handler is
a58e7e53
WS		 2126 * waiting for this command, and, if so, wake it.
2127 */
2128 c->scsi_cmd = SCSI_CMD_IDLE;
d604f533 2129 mb(); /* Declare command idle before checking for pending events. */
a58e7e53 2130 if (c->abort_pending) {
d604f533 2131 do_wake = true;
a58e7e53 2132 c->abort_pending = false;
a58e7e53 2133 }
d604f533
WS		 2134 if (c->reset_pending) {
2135 unsigned long flags;
2136 struct hpsa_scsi_dev_t *dev;
2137
2138 /*
2139 * There appears to be a reset pending; lock the lock and
2140 * reconfirm. If so, then decrement the count of outstanding
2141 * commands and wake the reset command if this is the last one.
2142 */
2143 spin_lock_irqsave(&h->lock, flags);
2144 dev = c->reset_pending; /* Re-fetch under the lock. */
2145 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2146 do_wake = true;
2147 c->reset_pending = NULL;
2148 spin_unlock_irqrestore(&h->lock, flags);
2149 }
2150
2151 if (do_wake)
2152 wake_up_all(&h->event_sync_wait_queue);
a58e7e53
WS		 2153}
2154
73153fe5
WS		 2155static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2156 struct CommandList *c)
2157{
2158 hpsa_cmd_resolve_events(h, c);
2159 cmd_tagged_free(h, c);
2160}
2161
8a0ff92c
WS		 2162static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2163 struct CommandList *c, struct scsi_cmnd *cmd)
2164{
73153fe5 2165 hpsa_cmd_resolve_and_free(h, c);
8a0ff92c
WS		 2166 cmd->scsi_done(cmd);
2167}
2168
2169static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2170{
2171 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2172 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2173}
2174
a58e7e53
WS		 2175static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2176{
2177 cmd->result = DID_ABORT << 16;
2178}
2179
2180static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2181 struct scsi_cmnd *cmd)
2182{
2183 hpsa_set_scsi_cmd_aborted(cmd);
2184 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2185 c->Request.CDB, c->err_info->ScsiStatus);
73153fe5 2186 hpsa_cmd_resolve_and_free(h, c);
a58e7e53
WS		 2187}
2188
c349775e
ST		 2189static void process_ioaccel2_completion(struct ctlr_info *h,
2190 struct CommandList *c, struct scsi_cmnd *cmd,
2191 struct hpsa_scsi_dev_t *dev)
2192{
2193 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2194
2195 /* check for good status */
2196 if (likely(c2->error_data.serv_response == 0 &&
8a0ff92c
WS		 2197 c2->error_data.status == 0))
2198 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e 2199
8a0ff92c
WS		 2200 /*
2201 * Any RAID offload error results in retry which will use
c349775e
ST		 2202 * the normal I/O path so the controller can handle whatever's
2203 * wrong.
2204 */
2205 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
2206 c2->error_data.serv_response ==
2207 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 2208 if (c2->error_data.status ==
2209 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
2210 dev->offload_enabled = 0;
8a0ff92c
WS		 2211
2212 return hpsa_retry_cmd(h, c);
a09c1441 2213 }
080ef1cc
DB		 2214
2215 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
8a0ff92c 2216 return hpsa_retry_cmd(h, c);
080ef1cc 2217
8a0ff92c 2218 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e
ST		 2219}
2220
9437ac43
SC		 2221/* Returns 0 on success, < 0 otherwise. */
2222static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2223 struct CommandList *cp)
2224{
2225 u8 tmf_status = cp->err_info->ScsiStatus;
2226
2227 switch (tmf_status) {
2228 case CISS_TMF_COMPLETE:
2229 /*
2230 * CISS_TMF_COMPLETE never happens, instead,
2231 * ei->CommandStatus == 0 for this case.
2232 */
2233 case CISS_TMF_SUCCESS:
2234 return 0;
2235 case CISS_TMF_INVALID_FRAME:
2236 case CISS_TMF_NOT_SUPPORTED:
2237 case CISS_TMF_FAILED:
2238 case CISS_TMF_WRONG_LUN:
2239 case CISS_TMF_OVERLAPPED_TAG:
2240 break;
2241 default:
2242 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2243 tmf_status);
2244 break;
2245 }
2246 return -tmf_status;
2247}
2248
1fb011fb 2249static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2250{
2251 struct scsi_cmnd *cmd;
2252 struct ctlr_info *h;
2253 struct ErrorInfo *ei;
283b4a9b 2254 struct hpsa_scsi_dev_t *dev;
d9a729f3 2255 struct io_accel2_cmd *c2;
edd16368 2256
9437ac43
SC		 2257 u8 sense_key;
2258 u8 asc; /* additional sense code */
2259 u8 ascq; /* additional sense code qualifier */
db111e18 2260 unsigned long sense_data_size;
edd16368
SC		 2261
2262 ei = cp->err_info;
7fa3030c 2263 cmd = cp->scsi_cmd;
edd16368 2264 h = cp->h;
283b4a9b 2265 dev = cmd->device->hostdata;
d9a729f3 2266 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2267
2268 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2269 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2270 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2271 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2272
d9a729f3
WS		 2273 if ((cp->cmd_type == CMD_IOACCEL2) &&
2274 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2275 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2276
edd16368
SC		 2277 cmd->result = (DID_OK << 16); /* host byte */
2278 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2279
03383736
DB		 2280 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2281 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2282
25163bd5
WS		 2283 /*
2284 * We check for lockup status here as it may be set for
2285 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2286 * fail_all_oustanding_cmds()
2287 */
2288 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2289 /* DID_NO_CONNECT will prevent a retry */
2290 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 2291 return hpsa_cmd_free_and_done(h, cp, cmd);
25163bd5
WS		 2292 }
2293
d604f533
WS		 2294 if ((unlikely(hpsa_is_pending_event(cp)))) {
2295 if (cp->reset_pending)
2296 return hpsa_cmd_resolve_and_free(h, cp);
2297 if (cp->abort_pending)
2298 return hpsa_cmd_abort_and_free(h, cp, cmd);
2299 }
2300
c349775e
ST		 2301 if (cp->cmd_type == CMD_IOACCEL2)
2302 return process_ioaccel2_completion(h, cp, cmd, dev);
2303
6aa4c361 2304 scsi_set_resid(cmd, ei->ResidualCnt);
8a0ff92c
WS		 2305 if (ei->CommandStatus == 0)
2306 return hpsa_cmd_free_and_done(h, cp, cmd);
6aa4c361 2307
e1f7de0c
MG		 2308 /* For I/O accelerator commands, copy over some fields to the normal
2309 * CISS header used below for error handling.
2310 */
2311 if (cp->cmd_type == CMD_IOACCEL1) {
2312 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2313 cp->Header.SGList = scsi_sg_count(cmd);
2314 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2315 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2316 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2317 cp->Header.tag = c->tag;
e1f7de0c
MG		 2318 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2319 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2320
2321 /* Any RAID offload error results in retry which will use
2322 * the normal I/O path so the controller can handle whatever's
2323 * wrong.
2324 */
2325 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
2326 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2327 dev->offload_enabled = 0;
d604f533 2328 return hpsa_retry_cmd(h, cp);
283b4a9b 2329 }
e1f7de0c
MG		 2330 }
2331
edd16368
SC		 2332 /* an error has occurred */
2333 switch (ei->CommandStatus) {
2334
2335 case CMD_TARGET_STATUS:
9437ac43
SC		 2336 cmd->result |= ei->ScsiStatus;
2337 /* copy the sense data */
2338 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2339 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2340 else
2341 sense_data_size = sizeof(ei->SenseInfo);
2342 if (ei->SenseLen < sense_data_size)
2343 sense_data_size = ei->SenseLen;
2344 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2345 if (ei->ScsiStatus)
2346 decode_sense_data(ei->SenseInfo, sense_data_size,
2347 &sense_key, &asc, &ascq);
edd16368 2348 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2349 if (sense_key == ABORTED_COMMAND) {
2e311fba 2350 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2351 break;
2352 }
edd16368
SC		 2353 break;
2354 }
edd16368
SC		 2355 /* Problem was not a check condition
2356 * Pass it up to the upper layers...
2357 */
2358 if (ei->ScsiStatus) {
2359 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2360 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2361 "Returning result: 0x%x\n",
2362 cp, ei->ScsiStatus,
2363 sense_key, asc, ascq,
2364 cmd->result);
2365 } else { /* scsi status is zero??? How??? */
2366 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2367 "Returning no connection.\n", cp),
2368
2369 /* Ordinarily, this case should never happen,
2370 * but there is a bug in some released firmware
2371 * revisions that allows it to happen if, for
2372 * example, a 4100 backplane loses power and
2373 * the tape drive is in it. We assume that
2374 * it's a fatal error of some kind because we
2375 * can't show that it wasn't. We will make it
2376 * look like selection timeout since that is
2377 * the most common reason for this to occur,
2378 * and it's severe enough.
2379 */
2380
2381 cmd->result = DID_NO_CONNECT << 16;
2382 }
2383 break;
2384
2385 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2386 break;
2387 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2388 dev_warn(&h->pdev->dev,
2389 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2390 break;
2391 case CMD_INVALID: {
2392 /* print_bytes(cp, sizeof(*cp), 1, 0);
2393 print_cmd(cp); */
2394 /* We get CMD_INVALID if you address a non-existent device
2395 * instead of a selection timeout (no response). You will
2396 * see this if you yank out a drive, then try to access it.
2397 * This is kind of a shame because it means that any other
2398 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2399 * missing target. */
2400 cmd->result = DID_NO_CONNECT << 16;
2401 }
2402 break;
2403 case CMD_PROTOCOL_ERR:
256d0eaa 2404 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2405 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2406 cp->Request.CDB);
edd16368
SC		 2407 break;
2408 case CMD_HARDWARE_ERR:
2409 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2410 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2411 cp->Request.CDB);
edd16368
SC		 2412 break;
2413 case CMD_CONNECTION_LOST:
2414 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2415 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2416 cp->Request.CDB);
edd16368
SC		 2417 break;
2418 case CMD_ABORTED:
a58e7e53
WS		 2419 /* Return now to avoid calling scsi_done(). */
2420 return hpsa_cmd_abort_and_free(h, cp, cmd);
edd16368
SC		 2421 case CMD_ABORT_FAILED:
2422 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2423 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2424 cp->Request.CDB);
edd16368
SC		 2425 break;
2426 case CMD_UNSOLICITED_ABORT:
f6e76055 2427 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2428 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2429 cp->Request.CDB);
edd16368
SC		 2430 break;
2431 case CMD_TIMEOUT:
2432 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2433 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2434 cp->Request.CDB);
edd16368 2435 break;
1d5e2ed0
SC		 2436 case CMD_UNABORTABLE:
2437 cmd->result = DID_ERROR << 16;
2438 dev_warn(&h->pdev->dev, "Command unabortable\n");
2439 break;
9437ac43
SC		 2440 case CMD_TMF_STATUS:
2441 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2442 cmd->result = DID_ERROR << 16;
2443 break;
283b4a9b
SC		 2444 case CMD_IOACCEL_DISABLED:
2445 /* This only handles the direct pass-through case since RAID
2446 * offload is handled above. Just attempt a retry.
2447 */
2448 cmd->result = DID_SOFT_ERROR << 16;
2449 dev_warn(&h->pdev->dev,
2450 "cp %p had HP SSD Smart Path error\n", cp);
2451 break;
edd16368
SC		 2452 default:
2453 cmd->result = DID_ERROR << 16;
2454 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2455 cp, ei->CommandStatus);
2456 }
8a0ff92c
WS		 2457
2458 return hpsa_cmd_free_and_done(h, cp, cmd);
edd16368
SC		 2459}
2460
edd16368
SC		 2461static void hpsa_pci_unmap(struct pci_dev *pdev,
2462 struct CommandList *c, int sg_used, int data_direction)
2463{
2464 int i;
edd16368 2465
50a0decf
SC		 2466 for (i = 0; i < sg_used; i++)
2467 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2468 le32_to_cpu(c->SG[i].Len),
2469 data_direction);
edd16368
SC		 2470}
2471
a2dac136 2472static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2473 struct CommandList *cp,
2474 unsigned char *buf,
2475 size_t buflen,
2476 int data_direction)
2477{
01a02ffc 2478 u64 addr64;
edd16368
SC		 2479
2480 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2481 cp->Header.SGList = 0;
50a0decf 2482 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2483 return 0;
edd16368
SC		 2484 }
2485
50a0decf 2486 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2487 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2488 /* Prevent subsequent unmap of something never mapped */
eceaae18 2489 cp->Header.SGList = 0;
50a0decf 2490 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2491 return -1;
eceaae18 2492 }
50a0decf
SC		 2493 cp->SG[0].Addr = cpu_to_le64(addr64);
2494 cp->SG[0].Len = cpu_to_le32(buflen);
2495 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2496 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2497 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2498 return 0;
edd16368
SC		 2499}
2500
25163bd5
WS		 2501#define NO_TIMEOUT ((unsigned long) -1)
2502#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2503static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2504 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2505{
2506 DECLARE_COMPLETION_ONSTACK(wait);
2507
2508 c->waiting = &wait;
25163bd5
WS		 2509 __enqueue_cmd_and_start_io(h, c, reply_queue);
2510 if (timeout_msecs == NO_TIMEOUT) {
2511 /* TODO: get rid of this no-timeout thing */
2512 wait_for_completion_io(&wait);
2513 return IO_OK;
2514 }
2515 if (!wait_for_completion_io_timeout(&wait,
2516 msecs_to_jiffies(timeout_msecs))) {
2517 dev_warn(&h->pdev->dev, "Command timed out.\n");
2518 return -ETIMEDOUT;
2519 }
2520 return IO_OK;
2521}
2522
2523static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2524 int reply_queue, unsigned long timeout_msecs)
2525{
2526 if (unlikely(lockup_detected(h))) {
2527 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2528 return IO_OK;
2529 }
2530 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2531}
2532
094963da
SC		 2533static u32 lockup_detected(struct ctlr_info *h)
2534{
2535 int cpu;
2536 u32 rc, *lockup_detected;
2537
2538 cpu = get_cpu();
2539 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2540 rc = *lockup_detected;
2541 put_cpu();
2542 return rc;
2543}
2544
9c2fc160 2545#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2546static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2547 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2548{
9c2fc160 2549 int backoff_time = 10, retry_count = 0;
25163bd5 2550 int rc;
edd16368
SC		 2551
2552 do {
7630abd0 2553 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2554 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2555 timeout_msecs);
2556 if (rc)
2557 break;
edd16368 2558 retry_count++;
9c2fc160
SC		 2559 if (retry_count > 3) {
2560 msleep(backoff_time);
2561 if (backoff_time < 1000)
2562 backoff_time *= 2;
2563 }
852af20a 2564 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2565 check_for_busy(h, c)) &&
2566 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2567 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2568 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2569 rc = -EIO;
2570 return rc;
edd16368
SC		 2571}
2572
d1e8beac
SC		 2573static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2574 struct CommandList *c)
edd16368 2575{
d1e8beac
SC		 2576 const u8 *cdb = c->Request.CDB;
2577 const u8 *lun = c->Header.LUN.LunAddrBytes;
2578
2579 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2580 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2581 txt, lun[0], lun[1], lun[2], lun[3],
2582 lun[4], lun[5], lun[6], lun[7],
2583 cdb[0], cdb[1], cdb[2], cdb[3],
2584 cdb[4], cdb[5], cdb[6], cdb[7],
2585 cdb[8], cdb[9], cdb[10], cdb[11],
2586 cdb[12], cdb[13], cdb[14], cdb[15]);
2587}
2588
2589static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2590 struct CommandList *cp)
2591{
2592 const struct ErrorInfo *ei = cp->err_info;
edd16368 2593 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2594 u8 sense_key, asc, ascq;
2595 int sense_len;
edd16368 2596
edd16368
SC		 2597 switch (ei->CommandStatus) {
2598 case CMD_TARGET_STATUS:
9437ac43
SC		 2599 if (ei->SenseLen > sizeof(ei->SenseInfo))
2600 sense_len = sizeof(ei->SenseInfo);
2601 else
2602 sense_len = ei->SenseLen;
2603 decode_sense_data(ei->SenseInfo, sense_len,
2604 &sense_key, &asc, &ascq);
d1e8beac
SC		 2605 hpsa_print_cmd(h, "SCSI status", cp);
2606 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2607 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2608 sense_key, asc, ascq);
d1e8beac 2609 else
9437ac43 2610 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2611 if (ei->ScsiStatus == 0)
2612 dev_warn(d, "SCSI status is abnormally zero. "
2613 "(probably indicates selection timeout "
2614 "reported incorrectly due to a known "
2615 "firmware bug, circa July, 2001.)\n");
2616 break;
2617 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2618 break;
2619 case CMD_DATA_OVERRUN:
d1e8beac 2620 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2621 break;
2622 case CMD_INVALID: {
2623 /* controller unfortunately reports SCSI passthru's
2624 * to non-existent targets as invalid commands.
2625 */
d1e8beac
SC		 2626 hpsa_print_cmd(h, "invalid command", cp);
2627 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2628 }
2629 break;
2630 case CMD_PROTOCOL_ERR:
d1e8beac 2631 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2632 break;
2633 case CMD_HARDWARE_ERR:
d1e8beac 2634 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2635 break;
2636 case CMD_CONNECTION_LOST:
d1e8beac 2637 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2638 break;
2639 case CMD_ABORTED:
d1e8beac 2640 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2641 break;
2642 case CMD_ABORT_FAILED:
d1e8beac 2643 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2644 break;
2645 case CMD_UNSOLICITED_ABORT:
d1e8beac 2646 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2647 break;
2648 case CMD_TIMEOUT:
d1e8beac 2649 hpsa_print_cmd(h, "timed out", cp);
edd16368 2650 break;
1d5e2ed0 2651 case CMD_UNABORTABLE:
d1e8beac 2652 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2653 break;
25163bd5
WS		 2654 case CMD_CTLR_LOCKUP:
2655 hpsa_print_cmd(h, "controller lockup detected", cp);
2656 break;
edd16368 2657 default:
d1e8beac
SC		 2658 hpsa_print_cmd(h, "unknown status", cp);
2659 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2660 ei->CommandStatus);
2661 }
2662}
2663
2664static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2665 u16 page, unsigned char *buf,
edd16368
SC		 2666 unsigned char bufsize)
2667{
2668 int rc = IO_OK;
2669 struct CommandList *c;
2670 struct ErrorInfo *ei;
2671
45fcb86e 2672 c = cmd_alloc(h);
edd16368 2673
a2dac136
SC		 2674 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2675 page, scsi3addr, TYPE_CMD)) {
2676 rc = -1;
2677 goto out;
2678 }
25163bd5
WS		 2679 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2680 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2681 if (rc)
2682 goto out;
edd16368
SC		 2683 ei = c->err_info;
2684 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2685 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2686 rc = -1;
2687 }
a2dac136 2688out:
45fcb86e 2689 cmd_free(h, c);
edd16368
SC		 2690 return rc;
2691}
2692
bf711ac6 2693static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2694 u8 reset_type, int reply_queue)
edd16368
SC		 2695{
2696 int rc = IO_OK;
2697 struct CommandList *c;
2698 struct ErrorInfo *ei;
2699
45fcb86e 2700 c = cmd_alloc(h);
edd16368 2701
edd16368 2702
a2dac136 2703 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2704 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2705 scsi3addr, TYPE_MSG);
2706 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
25163bd5
WS		 2707 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2708 if (rc) {
2709 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2710 goto out;
2711 }
edd16368
SC		 2712 /* no unmap needed here because no data xfer. */
2713
2714 ei = c->err_info;
2715 if (ei->CommandStatus != 0) {
d1e8beac 2716 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2717 rc = -1;
2718 }
25163bd5 2719out:
45fcb86e 2720 cmd_free(h, c);
edd16368
SC		 2721 return rc;
2722}
2723
d604f533
WS		 2724static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2725 struct hpsa_scsi_dev_t *dev,
2726 unsigned char *scsi3addr)
2727{
2728 int i;
2729 bool match = false;
2730 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2731 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2732
2733 if (hpsa_is_cmd_idle(c))
2734 return false;
2735
2736 switch (c->cmd_type) {
2737 case CMD_SCSI:
2738 case CMD_IOCTL_PEND:
2739 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2740 sizeof(c->Header.LUN.LunAddrBytes));
2741 break;
2742
2743 case CMD_IOACCEL1:
2744 case CMD_IOACCEL2:
2745 if (c->phys_disk == dev) {
2746 /* HBA mode match */
2747 match = true;
2748 } else {
2749 /* Possible RAID mode -- check each phys dev. */
2750 /* FIXME: Do we need to take out a lock here? If
2751 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2752 * instead. */
2753 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2754 /* FIXME: an alternate test might be
2755 *
2756 * match = dev->phys_disk[i]->ioaccel_handle
2757 * == c2->scsi_nexus; */
2758 match = dev->phys_disk[i] == c->phys_disk;
2759 }
2760 }
2761 break;
2762
2763 case IOACCEL2_TMF:
2764 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2765 match = dev->phys_disk[i]->ioaccel_handle ==
2766 le32_to_cpu(ac->it_nexus);
2767 }
2768 break;
2769
2770 case 0: /* The command is in the middle of being initialized. */
2771 match = false;
2772 break;
2773
2774 default:
2775 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
2776 c->cmd_type);
2777 BUG();
2778 }
2779
2780 return match;
2781}
2782
2783static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
2784 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
2785{
2786 int i;
2787 int rc = 0;
2788
2789 /* We can really only handle one reset at a time */
2790 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
2791 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
2792 return -EINTR;
2793 }
2794
2795 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
2796
2797 for (i = 0; i < h->nr_cmds; i++) {
2798 struct CommandList *c = h->cmd_pool + i;
2799 int refcount = atomic_inc_return(&c->refcount);
2800
2801 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
2802 unsigned long flags;
2803
2804 /*
2805 * Mark the target command as having a reset pending,
2806 * then lock a lock so that the command cannot complete
2807 * while we're considering it. If the command is not
2808 * idle then count it; otherwise revoke the event.
2809 */
2810 c->reset_pending = dev;
2811 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
2812 if (!hpsa_is_cmd_idle(c))
2813 atomic_inc(&dev->reset_cmds_out);
2814 else
2815 c->reset_pending = NULL;
2816 spin_unlock_irqrestore(&h->lock, flags);
2817 }
2818
2819 cmd_free(h, c);
2820 }
2821
2822 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
2823 if (!rc)
2824 wait_event(h->event_sync_wait_queue,
2825 atomic_read(&dev->reset_cmds_out) == 0 ||
2826 lockup_detected(h));
2827
2828 if (unlikely(lockup_detected(h))) {
77678d3a
DB		 2829 dev_warn(&h->pdev->dev,
2830 "Controller lockup detected during reset wait\n");
2831 rc = -ENODEV;
2832 }
d604f533
WS		 2833
2834 if (unlikely(rc))
2835 atomic_set(&dev->reset_cmds_out, 0);
2836
2837 mutex_unlock(&h->reset_mutex);
2838 return rc;
2839}
2840
edd16368
SC		 2841static void hpsa_get_raid_level(struct ctlr_info *h,
2842 unsigned char *scsi3addr, unsigned char *raid_level)
2843{
2844 int rc;
2845 unsigned char *buf;
2846
2847 *raid_level = RAID_UNKNOWN;
2848 buf = kzalloc(64, GFP_KERNEL);
2849 if (!buf)
2850 return;
b7bb24eb 2851 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2852 if (rc == 0)
2853 *raid_level = buf[8];
2854 if (*raid_level > RAID_UNKNOWN)
2855 *raid_level = RAID_UNKNOWN;
2856 kfree(buf);
2857 return;
2858}
2859
283b4a9b
SC		 2860#define HPSA_MAP_DEBUG
2861#ifdef HPSA_MAP_DEBUG
2862static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2863 struct raid_map_data *map_buff)
2864{
2865 struct raid_map_disk_data *dd = &map_buff->data[0];
2866 int map, row, col;
2867 u16 map_cnt, row_cnt, disks_per_row;
2868
2869 if (rc != 0)
2870 return;
2871
2ba8bfc8
SC		 2872 /* Show details only if debugging has been activated. */
2873 if (h->raid_offload_debug < 2)
2874 return;
2875
283b4a9b
SC		 2876 dev_info(&h->pdev->dev, "structure_size = %u\n",
2877 le32_to_cpu(map_buff->structure_size));
2878 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2879 le32_to_cpu(map_buff->volume_blk_size));
2880 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2881 le64_to_cpu(map_buff->volume_blk_cnt));
2882 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2883 map_buff->phys_blk_shift);
2884 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2885 map_buff->parity_rotation_shift);
2886 dev_info(&h->pdev->dev, "strip_size = %u\n",
2887 le16_to_cpu(map_buff->strip_size));
2888 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2889 le64_to_cpu(map_buff->disk_starting_blk));
2890 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2891 le64_to_cpu(map_buff->disk_blk_cnt));
2892 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2893 le16_to_cpu(map_buff->data_disks_per_row));
2894 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2895 le16_to_cpu(map_buff->metadata_disks_per_row));
2896 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2897 le16_to_cpu(map_buff->row_cnt));
2898 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2899 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2900 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2901 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2902 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2903 le16_to_cpu(map_buff->flags) &
2904 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2905 dev_info(&h->pdev->dev, "dekindex = %u\n",
2906 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2907 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2908 for (map = 0; map < map_cnt; map++) {
2909 dev_info(&h->pdev->dev, "Map%u:\n", map);
2910 row_cnt = le16_to_cpu(map_buff->row_cnt);
2911 for (row = 0; row < row_cnt; row++) {
2912 dev_info(&h->pdev->dev, " Row%u:\n", row);
2913 disks_per_row =
2914 le16_to_cpu(map_buff->data_disks_per_row);
2915 for (col = 0; col < disks_per_row; col++, dd++)
2916 dev_info(&h->pdev->dev,
2917 " D%02u: h=0x%04x xor=%u,%u\n",
2918 col, dd->ioaccel_handle,
2919 dd->xor_mult[0], dd->xor_mult[1]);
2920 disks_per_row =
2921 le16_to_cpu(map_buff->metadata_disks_per_row);
2922 for (col = 0; col < disks_per_row; col++, dd++)
2923 dev_info(&h->pdev->dev,
2924 " M%02u: h=0x%04x xor=%u,%u\n",
2925 col, dd->ioaccel_handle,
2926 dd->xor_mult[0], dd->xor_mult[1]);
2927 }
2928 }
2929}
2930#else
2931static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2932 __attribute__((unused)) int rc,
2933 __attribute__((unused)) struct raid_map_data *map_buff)
2934{
2935}
2936#endif
2937
2938static int hpsa_get_raid_map(struct ctlr_info *h,
2939 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2940{
2941 int rc = 0;
2942 struct CommandList *c;
2943 struct ErrorInfo *ei;
2944
45fcb86e 2945 c = cmd_alloc(h);
bf43caf3 2946
283b4a9b
SC		 2947 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2948 sizeof(this_device->raid_map), 0,
2949 scsi3addr, TYPE_CMD)) {
2dd02d74
RE		 2950 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
2951 cmd_free(h, c);
2952 return -1;
283b4a9b 2953 }
25163bd5
WS		 2954 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2955 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2956 if (rc)
2957 goto out;
283b4a9b
SC		 2958 ei = c->err_info;
2959 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2960 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 2961 rc = -1;
2962 goto out;
283b4a9b 2963 }
45fcb86e 2964 cmd_free(h, c);
283b4a9b
SC		 2965
2966 /* @todo in the future, dynamically allocate RAID map memory */
2967 if (le32_to_cpu(this_device->raid_map.structure_size) >
2968 sizeof(this_device->raid_map)) {
2969 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2970 rc = -1;
2971 }
2972 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2973 return rc;
25163bd5
WS		 2974out:
2975 cmd_free(h, c);
2976 return rc;
283b4a9b
SC		 2977}
2978
03383736
DB		 2979static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
2980 unsigned char scsi3addr[], u16 bmic_device_index,
2981 struct bmic_identify_physical_device *buf, size_t bufsize)
2982{
2983 int rc = IO_OK;
2984 struct CommandList *c;
2985 struct ErrorInfo *ei;
2986
2987 c = cmd_alloc(h);
2988 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
2989 0, RAID_CTLR_LUNID, TYPE_CMD);
2990 if (rc)
2991 goto out;
2992
2993 c->Request.CDB[2] = bmic_device_index & 0xff;
2994 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
2995
25163bd5
WS		 2996 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
2997 NO_TIMEOUT);
03383736
DB		 2998 ei = c->err_info;
2999 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3000 hpsa_scsi_interpret_error(h, c);
3001 rc = -1;
3002 }
3003out:
3004 cmd_free(h, c);
3005 return rc;
3006}
3007
1b70150a
SC		 3008static int hpsa_vpd_page_supported(struct ctlr_info *h,
3009 unsigned char scsi3addr[], u8 page)
3010{
3011 int rc;
3012 int i;
3013 int pages;
3014 unsigned char *buf, bufsize;
3015
3016 buf = kzalloc(256, GFP_KERNEL);
3017 if (!buf)
3018 return 0;
3019
3020 /* Get the size of the page list first */
3021 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3022 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3023 buf, HPSA_VPD_HEADER_SZ);
3024 if (rc != 0)
3025 goto exit_unsupported;
3026 pages = buf[3];
3027 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3028 bufsize = pages + HPSA_VPD_HEADER_SZ;
3029 else
3030 bufsize = 255;
3031
3032 /* Get the whole VPD page list */
3033 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3034 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3035 buf, bufsize);
3036 if (rc != 0)
3037 goto exit_unsupported;
3038
3039 pages = buf[3];
3040 for (i = 1; i <= pages; i++)
3041 if (buf[3 + i] == page)
3042 goto exit_supported;
3043exit_unsupported:
3044 kfree(buf);
3045 return 0;
3046exit_supported:
3047 kfree(buf);
3048 return 1;
3049}
3050
283b4a9b
SC		 3051static void hpsa_get_ioaccel_status(struct ctlr_info *h,
3052 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3053{
3054 int rc;
3055 unsigned char *buf;
3056 u8 ioaccel_status;
3057
3058 this_device->offload_config = 0;
3059 this_device->offload_enabled = 0;
41ce4c35 3060 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 3061
3062 buf = kzalloc(64, GFP_KERNEL);
3063 if (!buf)
3064 return;
1b70150a
SC		 3065 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
3066 goto out;
283b4a9b 3067 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 3068 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 3069 if (rc != 0)
3070 goto out;
3071
3072#define IOACCEL_STATUS_BYTE 4
3073#define OFFLOAD_CONFIGURED_BIT 0x01
3074#define OFFLOAD_ENABLED_BIT 0x02
3075 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
3076 this_device->offload_config =
3077 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3078 if (this_device->offload_config) {
3079 this_device->offload_enabled =
3080 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3081 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3082 this_device->offload_enabled = 0;
3083 }
41ce4c35 3084 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 3085out:
3086 kfree(buf);
3087 return;
3088}
3089
edd16368
SC		 3090/* Get the device id from inquiry page 0x83 */
3091static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
3092 unsigned char *device_id, int buflen)
3093{
3094 int rc;
3095 unsigned char *buf;
3096
3097 if (buflen > 16)
3098 buflen = 16;
3099 buf = kzalloc(64, GFP_KERNEL);
3100 if (!buf)
a84d794d 3101 return -ENOMEM;
b7bb24eb 3102 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 3103 if (rc == 0)
3104 memcpy(device_id, &buf[8], buflen);
3105 kfree(buf);
3106 return rc != 0;
3107}
3108
3109static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 3110 void *buf, int bufsize,
edd16368
SC		 3111 int extended_response)
3112{
3113 int rc = IO_OK;
3114 struct CommandList *c;
3115 unsigned char scsi3addr[8];
3116 struct ErrorInfo *ei;
3117
45fcb86e 3118 c = cmd_alloc(h);
bf43caf3 3119
e89c0ae7
SC		 3120 /* address the controller */
3121 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 3122 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3123 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3124 rc = -1;
3125 goto out;
3126 }
edd16368
SC		 3127 if (extended_response)
3128 c->Request.CDB[1] = extended_response;
25163bd5
WS		 3129 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3130 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3131 if (rc)
3132 goto out;
edd16368
SC		 3133 ei = c->err_info;
3134 if (ei->CommandStatus != 0 &&
3135 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3136 hpsa_scsi_interpret_error(h, c);
edd16368 3137 rc = -1;
283b4a9b 3138 } else {
03383736
DB		 3139 struct ReportLUNdata *rld = buf;
3140
3141 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 3142 dev_err(&h->pdev->dev,
3143 "report luns requested format %u, got %u\n",
3144 extended_response,
03383736 3145 rld->extended_response_flag);
283b4a9b
SC		 3146 rc = -1;
3147 }
edd16368 3148 }
a2dac136 3149out:
45fcb86e 3150 cmd_free(h, c);
edd16368
SC		 3151 return rc;
3152}
3153
3154static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 3155 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 3156{
03383736
DB		 3157 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3158 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 3159}
3160
3161static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3162 struct ReportLUNdata *buf, int bufsize)
3163{
3164 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3165}
3166
3167static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3168 int bus, int target, int lun)
3169{
3170 device->bus = bus;
3171 device->target = target;
3172 device->lun = lun;
3173}
3174
9846590e
SC		 3175/* Use VPD inquiry to get details of volume status */
3176static int hpsa_get_volume_status(struct ctlr_info *h,
3177 unsigned char scsi3addr[])
3178{
3179 int rc;
3180 int status;
3181 int size;
3182 unsigned char *buf;
3183
3184 buf = kzalloc(64, GFP_KERNEL);
3185 if (!buf)
3186 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3187
3188 /* Does controller have VPD for logical volume status? */
24a4b078 3189 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 3190 goto exit_failed;
9846590e
SC		 3191
3192 /* Get the size of the VPD return buffer */
3193 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3194 buf, HPSA_VPD_HEADER_SZ);
24a4b078 3195 if (rc != 0)
9846590e 3196 goto exit_failed;
9846590e
SC		 3197 size = buf[3];
3198
3199 /* Now get the whole VPD buffer */
3200 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3201 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 3202 if (rc != 0)
9846590e 3203 goto exit_failed;
9846590e
SC		 3204 status = buf[4]; /* status byte */
3205
3206 kfree(buf);
3207 return status;
3208exit_failed:
3209 kfree(buf);
3210 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3211}
3212
3213/* Determine offline status of a volume.
3214 * Return either:
3215 * 0 (not offline)
67955ba3 3216 * 0xff (offline for unknown reasons)
9846590e
SC		 3217 * # (integer code indicating one of several NOT READY states
3218 * describing why a volume is to be kept offline)
3219 */
67955ba3 3220static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 3221 unsigned char scsi3addr[])
3222{
3223 struct CommandList *c;
9437ac43
SC		 3224 unsigned char *sense;
3225 u8 sense_key, asc, ascq;
3226 int sense_len;
25163bd5 3227 int rc, ldstat = 0;
9846590e
SC		 3228 u16 cmd_status;
3229 u8 scsi_status;
3230#define ASC_LUN_NOT_READY 0x04
3231#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3232#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3233
3234 c = cmd_alloc(h);
bf43caf3 3235
9846590e 3236 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
25163bd5
WS		 3237 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3238 if (rc) {
3239 cmd_free(h, c);
3240 return 0;
3241 }
9846590e 3242 sense = c->err_info->SenseInfo;
9437ac43
SC		 3243 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3244 sense_len = sizeof(c->err_info->SenseInfo);
3245 else
3246 sense_len = c->err_info->SenseLen;
3247 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 3248 cmd_status = c->err_info->CommandStatus;
3249 scsi_status = c->err_info->ScsiStatus;
3250 cmd_free(h, c);
3251 /* Is the volume 'not ready'? */
3252 if (cmd_status != CMD_TARGET_STATUS ||
3253 scsi_status != SAM_STAT_CHECK_CONDITION ||
3254 sense_key != NOT_READY ||
3255 asc != ASC_LUN_NOT_READY) {
3256 return 0;
3257 }
3258
3259 /* Determine the reason for not ready state */
3260 ldstat = hpsa_get_volume_status(h, scsi3addr);
3261
3262 /* Keep volume offline in certain cases: */
3263 switch (ldstat) {
3264 case HPSA_LV_UNDERGOING_ERASE:
3265 case HPSA_LV_UNDERGOING_RPI:
3266 case HPSA_LV_PENDING_RPI:
3267 case HPSA_LV_ENCRYPTED_NO_KEY:
3268 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3269 case HPSA_LV_UNDERGOING_ENCRYPTION:
3270 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3271 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3272 return ldstat;
3273 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3274 /* If VPD status page isn't available,
3275 * use ASC/ASCQ to determine state
3276 */
3277 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3278 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3279 return ldstat;
3280 break;
3281 default:
3282 break;
3283 }
3284 return 0;
3285}
3286
9b5c48c2
SC		 3287/*
3288 * Find out if a logical device supports aborts by simply trying one.
3289 * Smart Array may claim not to support aborts on logical drives, but
3290 * if a MSA2000 * is connected, the drives on that will be presented
3291 * by the Smart Array as logical drives, and aborts may be sent to
3292 * those devices successfully. So the simplest way to find out is
3293 * to simply try an abort and see how the device responds.
3294 */
3295static int hpsa_device_supports_aborts(struct ctlr_info *h,
3296 unsigned char *scsi3addr)
3297{
3298 struct CommandList *c;
3299 struct ErrorInfo *ei;
3300 int rc = 0;
3301
3302 u64 tag = (u64) -1; /* bogus tag */
3303
3304 /* Assume that physical devices support aborts */
3305 if (!is_logical_dev_addr_mode(scsi3addr))
3306 return 1;
3307
3308 c = cmd_alloc(h);
bf43caf3 3309
9b5c48c2
SC		 3310 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
3311 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3312 /* no unmap needed here because no data xfer. */
3313 ei = c->err_info;
3314 switch (ei->CommandStatus) {
3315 case CMD_INVALID:
3316 rc = 0;
3317 break;
3318 case CMD_UNABORTABLE:
3319 case CMD_ABORT_FAILED:
3320 rc = 1;
3321 break;
9437ac43
SC		 3322 case CMD_TMF_STATUS:
3323 rc = hpsa_evaluate_tmf_status(h, c);
3324 break;
9b5c48c2
SC		 3325 default:
3326 rc = 0;
3327 break;
3328 }
3329 cmd_free(h, c);
3330 return rc;
3331}
3332
edd16368 3333static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3334 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3335 unsigned char *is_OBDR_device)
edd16368 3336{
0b0e1d6c
SC		 3337
3338#define OBDR_SIG_OFFSET 43
3339#define OBDR_TAPE_SIG "$DR-10"
3340#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3341#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3342
ea6d3bc3 3343 unsigned char *inq_buff;
0b0e1d6c 3344 unsigned char *obdr_sig;
edd16368 3345
ea6d3bc3 3346 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 3347 if (!inq_buff)
3348 goto bail_out;
3349
edd16368
SC		 3350 /* Do an inquiry to the device to see what it is. */
3351 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3352 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3353 /* Inquiry failed (msg printed already) */
3354 dev_err(&h->pdev->dev,
3355 "hpsa_update_device_info: inquiry failed\n");
3356 goto bail_out;
3357 }
3358
edd16368
SC		 3359 this_device->devtype = (inq_buff[0] & 0x1f);
3360 memcpy(this_device->scsi3addr, scsi3addr, 8);
3361 memcpy(this_device->vendor, &inq_buff[8],
3362 sizeof(this_device->vendor));
3363 memcpy(this_device->model, &inq_buff[16],
3364 sizeof(this_device->model));
edd16368
SC		 3365 memset(this_device->device_id, 0,
3366 sizeof(this_device->device_id));
3367 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
3368 sizeof(this_device->device_id));
3369
3370 if (this_device->devtype == TYPE_DISK &&
283b4a9b 3371 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3372 int volume_offline;
3373
edd16368 3374 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3375 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3376 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3377 volume_offline = hpsa_volume_offline(h, scsi3addr);
3378 if (volume_offline < 0 || volume_offline > 0xff)
3379 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3380 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3381 } else {
edd16368 3382 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3383 this_device->offload_config = 0;
3384 this_device->offload_enabled = 0;
41ce4c35 3385 this_device->offload_to_be_enabled = 0;
a3144e0b 3386 this_device->hba_ioaccel_enabled = 0;
9846590e 3387 this_device->volume_offline = 0;
03383736 3388 this_device->queue_depth = h->nr_cmds;
283b4a9b 3389 }
edd16368 3390
0b0e1d6c
SC		 3391 if (is_OBDR_device) {
3392 /* See if this is a One-Button-Disaster-Recovery device
3393 * by looking for "$DR-10" at offset 43 in inquiry data.
3394 */
3395 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3396 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3397 strncmp(obdr_sig, OBDR_TAPE_SIG,
3398 OBDR_SIG_LEN) == 0);
3399 }
edd16368
SC		 3400 kfree(inq_buff);
3401 return 0;
3402
3403bail_out:
3404 kfree(inq_buff);
3405 return 1;
3406}
3407
9b5c48c2
SC		 3408static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3409 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3410{
3411 unsigned long flags;
3412 int rc, entry;
3413 /*
3414 * See if this device supports aborts. If we already know
3415 * the device, we already know if it supports aborts, otherwise
3416 * we have to find out if it supports aborts by trying one.
3417 */
3418 spin_lock_irqsave(&h->devlock, flags);
3419 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3420 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3421 entry >= 0 && entry < h->ndevices) {
3422 dev->supports_aborts = h->dev[entry]->supports_aborts;
3423 spin_unlock_irqrestore(&h->devlock, flags);
3424 } else {
3425 spin_unlock_irqrestore(&h->devlock, flags);
3426 dev->supports_aborts =
3427 hpsa_device_supports_aborts(h, scsi3addr);
3428 if (dev->supports_aborts < 0)
3429 dev->supports_aborts = 0;
3430 }
3431}
3432
4f4eb9f1 3433static unsigned char *ext_target_model[] = {
edd16368
SC		 3434 "MSA2012",
3435 "MSA2024",
3436 "MSA2312",
3437 "MSA2324",
fda38518 3438 "P2000 G3 SAS",
e06c8e5c 3439 "MSA 2040 SAS",
edd16368
SC		 3440 NULL,
3441};
3442
4f4eb9f1 3443static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 3444{
3445 int i;
3446
4f4eb9f1
ST		 3447 for (i = 0; ext_target_model[i]; i++)
3448 if (strncmp(device->model, ext_target_model[i],
3449 strlen(ext_target_model[i])) == 0)
edd16368
SC		 3450 return 1;
3451 return 0;
3452}
3453
3454/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 3455 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 3456 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
3457 * Logical drive target and lun are assigned at this time, but
3458 * physical device lun and target assignment are deferred (assigned
3459 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
3460 */
3461static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3462 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3463{
1f310bde
SC		 3464 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
3465
3466 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3467 /* physical device, target and lun filled in later */
edd16368 3468 if (is_hba_lunid(lunaddrbytes))
1f310bde 3469 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 3470 else
1f310bde
SC		 3471 /* defer target, lun assignment for physical devices */
3472 hpsa_set_bus_target_lun(device, 2, -1, -1);
3473 return;
3474 }
3475 /* It's a logical device */
4f4eb9f1
ST		 3476 if (is_ext_target(h, device)) {
3477 /* external target way, put logicals on bus 1
1f310bde
SC		 3478 * and match target/lun numbers box
3479 * reports, other smart array, bus 0, target 0, match lunid
3480 */
3481 hpsa_set_bus_target_lun(device,
3482 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
3483 return;
edd16368 3484 }
1f310bde 3485 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 3486}
3487
3488/*
3489 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 3490 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 3491 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
3492 * it for some reason. *tmpdevice is the target we're adding,
3493 * this_device is a pointer into the current element of currentsd[]
3494 * that we're building up in update_scsi_devices(), below.
3495 * lunzerobits is a bitmap that tracks which targets already have a
3496 * lun 0 assigned.
3497 * Returns 1 if an enclosure was added, 0 if not.
3498 */
4f4eb9f1 3499static int add_ext_target_dev(struct ctlr_info *h,
edd16368 3500 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 3501 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 3502 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 3503{
3504 unsigned char scsi3addr[8];
3505
1f310bde 3506 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 3507 return 0; /* There is already a lun 0 on this target. */
3508
3509 if (!is_logical_dev_addr_mode(lunaddrbytes))
3510 return 0; /* It's the logical targets that may lack lun 0. */
3511
4f4eb9f1
ST		 3512 if (!is_ext_target(h, tmpdevice))
3513 return 0; /* Only external target devices have this problem. */
edd16368 3514
1f310bde 3515 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 3516 return 0;
3517
c4f8a299 3518 memset(scsi3addr, 0, 8);
1f310bde 3519 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 3520 if (is_hba_lunid(scsi3addr))
3521 return 0; /* Don't add the RAID controller here. */
3522
339b2b14
SC		 3523 if (is_scsi_rev_5(h))
3524 return 0; /* p1210m doesn't need to do this. */
3525
4f4eb9f1 3526 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 3527 dev_warn(&h->pdev->dev, "Maximum number of external "
3528 "target devices exceeded. Check your hardware "
edd16368
SC		 3529 "configuration.");
3530 return 0;
3531 }
3532
0b0e1d6c 3533 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 3534 return 0;
4f4eb9f1 3535 (*n_ext_target_devs)++;
1f310bde
SC		 3536 hpsa_set_bus_target_lun(this_device,
3537 tmpdevice->bus, tmpdevice->target, 0);
9b5c48c2 3538 hpsa_update_device_supports_aborts(h, this_device, scsi3addr);
1f310bde 3539 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 3540 return 1;
3541}
3542
54b6e9e9
ST		 3543/*
3544 * Get address of physical disk used for an ioaccel2 mode command:
3545 * 1. Extract ioaccel2 handle from the command.
3546 * 2. Find a matching ioaccel2 handle from list of physical disks.
3547 * 3. Return:
3548 * 1 and set scsi3addr to address of matching physical
3549 * 0 if no matching physical disk was found.
3550 */
3551static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3552 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3553{
41ce4c35
SC		 3554 struct io_accel2_cmd *c2 =
3555 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3556 unsigned long flags;
54b6e9e9 3557 int i;
54b6e9e9 3558
41ce4c35
SC		 3559 spin_lock_irqsave(&h->devlock, flags);
3560 for (i = 0; i < h->ndevices; i++)
3561 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3562 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3563 sizeof(h->dev[i]->scsi3addr));
3564 spin_unlock_irqrestore(&h->devlock, flags);
3565 return 1;
3566 }
3567 spin_unlock_irqrestore(&h->devlock, flags);
3568 return 0;
54b6e9e9 3569}
41ce4c35 3570
edd16368
SC		 3571/*
3572 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3573 * logdev. The number of luns in physdev and logdev are returned in
3574 * *nphysicals and *nlogicals, respectively.
3575 * Returns 0 on success, -1 otherwise.
3576 */
3577static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3578 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3579 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3580{
03383736 3581 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3582 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3583 return -1;
3584 }
03383736 3585 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3586 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3587 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3588 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3589 *nphysicals = HPSA_MAX_PHYS_LUN;
3590 }
03383736 3591 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3592 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3593 return -1;
3594 }
6df1e954 3595 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3596 /* Reject Logicals in excess of our max capability. */
3597 if (*nlogicals > HPSA_MAX_LUN) {
3598 dev_warn(&h->pdev->dev,
3599 "maximum logical LUNs (%d) exceeded. "
3600 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3601 *nlogicals - HPSA_MAX_LUN);
3602 *nlogicals = HPSA_MAX_LUN;
3603 }
3604 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3605 dev_warn(&h->pdev->dev,
3606 "maximum logical + physical LUNs (%d) exceeded. "
3607 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3608 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3609 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3610 }
3611 return 0;
3612}
3613
42a91641
DB		 3614static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3615 int i, int nphysicals, int nlogicals,
a93aa1fe 3616 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3617 struct ReportLUNdata *logdev_list)
3618{
3619 /* Helper function, figure out where the LUN ID info is coming from
3620 * given index i, lists of physical and logical devices, where in
3621 * the list the raid controller is supposed to appear (first or last)
3622 */
3623
3624 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3625 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3626
3627 if (i == raid_ctlr_position)
3628 return RAID_CTLR_LUNID;
3629
3630 if (i < logicals_start)
d5b5d964
SC		 3631 return &physdev_list->LUN[i -
3632 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3633
3634 if (i < last_device)
3635 return &logdev_list->LUN[i - nphysicals -
3636 (raid_ctlr_position == 0)][0];
3637 BUG();
3638 return NULL;
3639}
3640
03383736
DB		 3641/* get physical drive ioaccel handle and queue depth */
3642static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3643 struct hpsa_scsi_dev_t *dev,
3644 u8 *lunaddrbytes,
3645 struct bmic_identify_physical_device *id_phys)
3646{
3647 int rc;
3648 struct ext_report_lun_entry *rle =
3649 (struct ext_report_lun_entry *) lunaddrbytes;
3650
3651 dev->ioaccel_handle = rle->ioaccel_handle;
a3144e0b
JH		 3652 if (PHYS_IOACCEL(lunaddrbytes) && dev->ioaccel_handle)
3653 dev->hba_ioaccel_enabled = 1;
03383736
DB		 3654 memset(id_phys, 0, sizeof(*id_phys));
3655 rc = hpsa_bmic_id_physical_device(h, lunaddrbytes,
3656 GET_BMIC_DRIVE_NUMBER(lunaddrbytes), id_phys,
3657 sizeof(*id_phys));
3658 if (!rc)
3659 /* Reserve space for FW operations */
3660#define DRIVE_CMDS_RESERVED_FOR_FW 2
3661#define DRIVE_QUEUE_DEPTH 7
3662 dev->queue_depth =
3663 le16_to_cpu(id_phys->current_queue_depth_limit) -
3664 DRIVE_CMDS_RESERVED_FOR_FW;
3665 else
3666 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
3667 atomic_set(&dev->ioaccel_cmds_out, 0);
d604f533 3668 atomic_set(&dev->reset_cmds_out, 0);
03383736
DB		 3669}
3670
8270b862
JH		 3671static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
3672 u8 *lunaddrbytes,
3673 struct bmic_identify_physical_device *id_phys)
3674{
3675 if (PHYS_IOACCEL(lunaddrbytes)
3676 && this_device->ioaccel_handle)
3677 this_device->hba_ioaccel_enabled = 1;
3678
3679 memcpy(&this_device->active_path_index,
3680 &id_phys->active_path_number,
3681 sizeof(this_device->active_path_index));
3682 memcpy(&this_device->path_map,
3683 &id_phys->redundant_path_present_map,
3684 sizeof(this_device->path_map));
3685 memcpy(&this_device->box,
3686 &id_phys->alternate_paths_phys_box_on_port,
3687 sizeof(this_device->box));
3688 memcpy(&this_device->phys_connector,
3689 &id_phys->alternate_paths_phys_connector,
3690 sizeof(this_device->phys_connector));
3691 memcpy(&this_device->bay,
3692 &id_phys->phys_bay_in_box,
3693 sizeof(this_device->bay));
3694}
3695
edd16368
SC		 3696static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
3697{
3698 /* the idea here is we could get notified
3699 * that some devices have changed, so we do a report
3700 * physical luns and report logical luns cmd, and adjust
3701 * our list of devices accordingly.
3702 *
3703 * The scsi3addr's of devices won't change so long as the
3704 * adapter is not reset. That means we can rescan and
3705 * tell which devices we already know about, vs. new
3706 * devices, vs. disappearing devices.
3707 */
a93aa1fe 3708 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3709 struct ReportLUNdata *logdev_list = NULL;
03383736 3710 struct bmic_identify_physical_device *id_phys = NULL;
01a02ffc
SC		 3711 u32 nphysicals = 0;
3712 u32 nlogicals = 0;
3713 u32 ndev_allocated = 0;
edd16368
SC		 3714 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3715 int ncurrent = 0;
4f4eb9f1 3716 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3717 int raid_ctlr_position;
aca4a520 3718 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3719
cfe5badc 3720 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 3721 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3722 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 3723 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 3724 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
edd16368 3725
03383736
DB		 3726 if (!currentsd || !physdev_list || !logdev_list ||
3727 !tmpdevice || !id_phys) {
edd16368
SC		 3728 dev_err(&h->pdev->dev, "out of memory\n");
3729 goto out;
3730 }
3731 memset(lunzerobits, 0, sizeof(lunzerobits));
3732
03383736
DB		 3733 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
3734 logdev_list, &nlogicals))
edd16368
SC		 3735 goto out;
3736
aca4a520
ST		 3737 /* We might see up to the maximum number of logical and physical disks
3738 * plus external target devices, and a device for the local RAID
3739 * controller.
edd16368 3740 */
aca4a520 3741 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3742
3743 /* Allocate the per device structures */
3744 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3745 if (i >= HPSA_MAX_DEVICES) {
3746 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3747 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3748 ndevs_to_allocate - HPSA_MAX_DEVICES);
3749 break;
3750 }
3751
edd16368
SC		 3752 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3753 if (!currentsd[i]) {
3754 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3755 __FILE__, __LINE__);
3756 goto out;
3757 }
3758 ndev_allocated++;
3759 }
3760
8645291b 3761 if (is_scsi_rev_5(h))
339b2b14
SC		 3762 raid_ctlr_position = 0;
3763 else
3764 raid_ctlr_position = nphysicals + nlogicals;
3765
edd16368 3766 /* adjust our table of devices */
4f4eb9f1 3767 n_ext_target_devs = 0;
edd16368 3768 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3769 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3770
3771 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3772 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3773 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 3774
3775 /* skip masked non-disk devices */
3776 if (MASKED_DEVICE(lunaddrbytes))
3777 if (i < nphysicals + (raid_ctlr_position == 0) &&
3778 NON_DISK_PHYS_DEV(lunaddrbytes))
3779 continue;
edd16368
SC		 3780
3781 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3782 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3783 &is_OBDR))
edd16368 3784 continue; /* skip it if we can't talk to it. */
1f310bde 3785 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 3786 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 3787 this_device = currentsd[ncurrent];
3788
3789 /*
4f4eb9f1 3790 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3791 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3792 * is nonetheless an enclosure device there. We have to
3793 * present that otherwise linux won't find anything if
3794 * there is no lun 0.
3795 */
4f4eb9f1 3796 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3797 lunaddrbytes, lunzerobits,
4f4eb9f1 3798 &n_ext_target_devs)) {
edd16368
SC		 3799 ncurrent++;
3800 this_device = currentsd[ncurrent];
3801 }
3802
3803 *this_device = *tmpdevice;
edd16368 3804
41ce4c35
SC		 3805 /* do not expose masked devices */
3806 if (MASKED_DEVICE(lunaddrbytes) &&
3807 i < nphysicals + (raid_ctlr_position == 0)) {
41ce4c35
SC		 3808 this_device->expose_state = HPSA_DO_NOT_EXPOSE;
3809 } else {
3810 this_device->expose_state =
3811 HPSA_SG_ATTACH | HPSA_ULD_ATTACH;
3812 }
3813
edd16368 3814 switch (this_device->devtype) {
0b0e1d6c 3815 case TYPE_ROM:
edd16368
SC		 3816 /* We don't *really* support actual CD-ROM devices,
3817 * just "One Button Disaster Recovery" tape drive
3818 * which temporarily pretends to be a CD-ROM drive.
3819 * So we check that the device is really an OBDR tape
3820 * device by checking for "$DR-10" in bytes 43-48 of
3821 * the inquiry data.
3822 */
0b0e1d6c
SC		 3823 if (is_OBDR)
3824 ncurrent++;
edd16368
SC		 3825 break;
3826 case TYPE_DISK:
b9092b79
KB		 3827 if (i < nphysicals + (raid_ctlr_position == 0)) {
3828 /* The disk is in HBA mode. */
3829 /* Never use RAID mapper in HBA mode. */
ecf418d1 3830 this_device->offload_enabled = 0;
b9092b79
KB		 3831 hpsa_get_ioaccel_drive_info(h, this_device,
3832 lunaddrbytes, id_phys);
3833 hpsa_get_path_info(this_device, lunaddrbytes,
3834 id_phys);
3835 }
ecf418d1 3836 ncurrent++;
edd16368
SC		 3837 break;
3838 case TYPE_TAPE:
3839 case TYPE_MEDIUM_CHANGER:
41ce4c35 3840 case TYPE_ENCLOSURE:
b9092b79 3841 ncurrent++;
41ce4c35 3842 break;
edd16368
SC		 3843 case TYPE_RAID:
3844 /* Only present the Smartarray HBA as a RAID controller.
3845 * If it's a RAID controller other than the HBA itself
3846 * (an external RAID controller, MSA500 or similar)
3847 * don't present it.
3848 */
3849 if (!is_hba_lunid(lunaddrbytes))
3850 break;
3851 ncurrent++;
3852 break;
3853 default:
3854 break;
3855 }
cfe5badc 3856 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3857 break;
3858 }
3859 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3860out:
3861 kfree(tmpdevice);
3862 for (i = 0; i < ndev_allocated; i++)
3863 kfree(currentsd[i]);
3864 kfree(currentsd);
edd16368
SC		 3865 kfree(physdev_list);
3866 kfree(logdev_list);
03383736 3867 kfree(id_phys);
edd16368
SC		 3868}
3869
ec5cbf04
WS		 3870static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3871 struct scatterlist *sg)
3872{
3873 u64 addr64 = (u64) sg_dma_address(sg);
3874 unsigned int len = sg_dma_len(sg);
3875
3876 desc->Addr = cpu_to_le64(addr64);
3877 desc->Len = cpu_to_le32(len);
3878 desc->Ext = 0;
3879}
3880
c7ee65b3
WS		 3881/*
3882 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3883 * dma mapping and fills in the scatter gather entries of the
3884 * hpsa command, cp.
3885 */
33a2ffce 3886static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3887 struct CommandList *cp,
3888 struct scsi_cmnd *cmd)
3889{
edd16368 3890 struct scatterlist *sg;
b3a7ba7c 3891 int use_sg, i, sg_limit, chained, last_sg;
33a2ffce 3892 struct SGDescriptor *curr_sg;
edd16368 3893
33a2ffce 3894 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3895
3896 use_sg = scsi_dma_map(cmd);
3897 if (use_sg < 0)
3898 return use_sg;
3899
3900 if (!use_sg)
3901 goto sglist_finished;
3902
b3a7ba7c
WS		 3903 /*
3904 * If the number of entries is greater than the max for a single list,
3905 * then we have a chained list; we will set up all but one entry in the
3906 * first list (the last entry is saved for link information);
3907 * otherwise, we don't have a chained list and we'll set up at each of
3908 * the entries in the one list.
3909 */
33a2ffce 3910 curr_sg = cp->SG;
b3a7ba7c
WS		 3911 chained = use_sg > h->max_cmd_sg_entries;
3912 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
3913 last_sg = scsi_sg_count(cmd) - 1;
3914 scsi_for_each_sg(cmd, sg, sg_limit, i) {
ec5cbf04 3915 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 3916 curr_sg++;
3917 }
ec5cbf04 3918
b3a7ba7c
WS		 3919 if (chained) {
3920 /*
3921 * Continue with the chained list. Set curr_sg to the chained
3922 * list. Modify the limit to the total count less the entries
3923 * we've already set up. Resume the scan at the list entry
3924 * where the previous loop left off.
3925 */
3926 curr_sg = h->cmd_sg_list[cp->cmdindex];
3927 sg_limit = use_sg - sg_limit;
3928 for_each_sg(sg, sg, sg_limit, i) {
3929 hpsa_set_sg_descriptor(curr_sg, sg);
3930 curr_sg++;
3931 }
3932 }
3933
ec5cbf04 3934 /* Back the pointer up to the last entry and mark it as "last". */
b3a7ba7c 3935 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3936
3937 if (use_sg + chained > h->maxSG)
3938 h->maxSG = use_sg + chained;
3939
3940 if (chained) {
3941 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3942 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3943 if (hpsa_map_sg_chain_block(h, cp)) {
3944 scsi_dma_unmap(cmd);
3945 return -1;
3946 }
33a2ffce 3947 return 0;
edd16368
SC		 3948 }
3949
3950sglist_finished:
3951
01a02ffc 3952 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 3953 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 3954 return 0;
3955}
3956
283b4a9b
SC		 3957#define IO_ACCEL_INELIGIBLE (1)
3958static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3959{
3960 int is_write = 0;
3961 u32 block;
3962 u32 block_cnt;
3963
3964 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3965 switch (cdb[0]) {
3966 case WRITE_6:
3967 case WRITE_12:
3968 is_write = 1;
3969 case READ_6:
3970 case READ_12:
3971 if (*cdb_len == 6) {
3972 block = (((u32) cdb[2]) << 8) | cdb[3];
3973 block_cnt = cdb[4];
3974 } else {
3975 BUG_ON(*cdb_len != 12);
3976 block = (((u32) cdb[2]) << 24) |
3977 (((u32) cdb[3]) << 16) |
3978 (((u32) cdb[4]) << 8) |
3979 cdb[5];
3980 block_cnt =
3981 (((u32) cdb[6]) << 24) |
3982 (((u32) cdb[7]) << 16) |
3983 (((u32) cdb[8]) << 8) |
3984 cdb[9];
3985 }
3986 if (block_cnt > 0xffff)
3987 return IO_ACCEL_INELIGIBLE;
3988
3989 cdb[0] = is_write ? WRITE_10 : READ_10;
3990 cdb[1] = 0;
3991 cdb[2] = (u8) (block >> 24);
3992 cdb[3] = (u8) (block >> 16);
3993 cdb[4] = (u8) (block >> 8);
3994 cdb[5] = (u8) (block);
3995 cdb[6] = 0;
3996 cdb[7] = (u8) (block_cnt >> 8);
3997 cdb[8] = (u8) (block_cnt);
3998 cdb[9] = 0;
3999 *cdb_len = 10;
4000 break;
4001 }
4002 return 0;
4003}
4004
c349775e 4005static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 4006 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4007 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 4008{
4009 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 4010 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
4011 unsigned int len;
4012 unsigned int total_len = 0;
4013 struct scatterlist *sg;
4014 u64 addr64;
4015 int use_sg, i;
4016 struct SGDescriptor *curr_sg;
4017 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
4018
283b4a9b 4019 /* TODO: implement chaining support */
03383736
DB		 4020 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
4021 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4022 return IO_ACCEL_INELIGIBLE;
03383736 4023 }
283b4a9b 4024
e1f7de0c
MG		 4025 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
4026
03383736
DB		 4027 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4028 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4029 return IO_ACCEL_INELIGIBLE;
03383736 4030 }
283b4a9b 4031
e1f7de0c
MG		 4032 c->cmd_type = CMD_IOACCEL1;
4033
4034 /* Adjust the DMA address to point to the accelerated command buffer */
4035 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
4036 (c->cmdindex * sizeof(*cp));
4037 BUG_ON(c->busaddr & 0x0000007F);
4038
4039 use_sg = scsi_dma_map(cmd);
03383736
DB		 4040 if (use_sg < 0) {
4041 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 4042 return use_sg;
03383736 4043 }
e1f7de0c
MG		 4044
4045 if (use_sg) {
4046 curr_sg = cp->SG;
4047 scsi_for_each_sg(cmd, sg, use_sg, i) {
4048 addr64 = (u64) sg_dma_address(sg);
4049 len = sg_dma_len(sg);
4050 total_len += len;
50a0decf
SC		 4051 curr_sg->Addr = cpu_to_le64(addr64);
4052 curr_sg->Len = cpu_to_le32(len);
4053 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 4054 curr_sg++;
4055 }
50a0decf 4056 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 4057
4058 switch (cmd->sc_data_direction) {
4059 case DMA_TO_DEVICE:
4060 control |= IOACCEL1_CONTROL_DATA_OUT;
4061 break;
4062 case DMA_FROM_DEVICE:
4063 control |= IOACCEL1_CONTROL_DATA_IN;
4064 break;
4065 case DMA_NONE:
4066 control |= IOACCEL1_CONTROL_NODATAXFER;
4067 break;
4068 default:
4069 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4070 cmd->sc_data_direction);
4071 BUG();
4072 break;
4073 }
4074 } else {
4075 control |= IOACCEL1_CONTROL_NODATAXFER;
4076 }
4077
c349775e 4078 c->Header.SGList = use_sg;
e1f7de0c 4079 /* Fill out the command structure to submit */
2b08b3e9
DB		 4080 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4081 cp->transfer_len = cpu_to_le32(total_len);
4082 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4083 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4084 cp->control = cpu_to_le32(control);
283b4a9b
SC		 4085 memcpy(cp->CDB, cdb, cdb_len);
4086 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 4087 /* Tag was already set at init time. */
283b4a9b 4088 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 4089 return 0;
4090}
edd16368 4091
283b4a9b
SC		 4092/*
4093 * Queue a command directly to a device behind the controller using the
4094 * I/O accelerator path.
4095 */
4096static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4097 struct CommandList *c)
4098{
4099 struct scsi_cmnd *cmd = c->scsi_cmd;
4100 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4101
03383736
DB		 4102 c->phys_disk = dev;
4103
283b4a9b 4104 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 4105 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 4106}
4107
dd0e19f3
ST		 4108/*
4109 * Set encryption parameters for the ioaccel2 request
4110 */
4111static void set_encrypt_ioaccel2(struct ctlr_info *h,
4112 struct CommandList *c, struct io_accel2_cmd *cp)
4113{
4114 struct scsi_cmnd *cmd = c->scsi_cmd;
4115 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4116 struct raid_map_data *map = &dev->raid_map;
4117 u64 first_block;
4118
dd0e19f3 4119 /* Are we doing encryption on this device */
2b08b3e9 4120 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 4121 return;
4122 /* Set the data encryption key index. */
4123 cp->dekindex = map->dekindex;
4124
4125 /* Set the encryption enable flag, encoded into direction field. */
4126 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4127
4128 /* Set encryption tweak values based on logical block address
4129 * If block size is 512, tweak value is LBA.
4130 * For other block sizes, tweak is (LBA * block size)/ 512)
4131 */
4132 switch (cmd->cmnd[0]) {
4133 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
4134 case WRITE_6:
4135 case READ_6:
2b08b3e9 4136 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 4137 break;
4138 case WRITE_10:
4139 case READ_10:
dd0e19f3
ST		 4140 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4141 case WRITE_12:
4142 case READ_12:
2b08b3e9 4143 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 4144 break;
4145 case WRITE_16:
4146 case READ_16:
2b08b3e9 4147 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 4148 break;
4149 default:
4150 dev_err(&h->pdev->dev,
2b08b3e9
DB		 4151 "ERROR: %s: size (0x%x) not supported for encryption\n",
4152 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 4153 BUG();
4154 break;
4155 }
2b08b3e9
DB		 4156
4157 if (le32_to_cpu(map->volume_blk_size) != 512)
4158 first_block = first_block *
4159 le32_to_cpu(map->volume_blk_size)/512;
4160
4161 cp->tweak_lower = cpu_to_le32(first_block);
4162 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 4163}
4164
c349775e
ST		 4165static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4166 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4167 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 4168{
4169 struct scsi_cmnd *cmd = c->scsi_cmd;
4170 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4171 struct ioaccel2_sg_element *curr_sg;
4172 int use_sg, i;
4173 struct scatterlist *sg;
4174 u64 addr64;
4175 u32 len;
4176 u32 total_len = 0;
4177
d9a729f3 4178 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 4179
03383736
DB		 4180 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4181 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4182 return IO_ACCEL_INELIGIBLE;
03383736
DB		 4183 }
4184
c349775e
ST		 4185 c->cmd_type = CMD_IOACCEL2;
4186 /* Adjust the DMA address to point to the accelerated command buffer */
4187 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4188 (c->cmdindex * sizeof(*cp));
4189 BUG_ON(c->busaddr & 0x0000007F);
4190
4191 memset(cp, 0, sizeof(*cp));
4192 cp->IU_type = IOACCEL2_IU_TYPE;
4193
4194 use_sg = scsi_dma_map(cmd);
03383736
DB		 4195 if (use_sg < 0) {
4196 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4197 return use_sg;
03383736 4198 }
c349775e
ST		 4199
4200 if (use_sg) {
c349775e 4201 curr_sg = cp->sg;
d9a729f3
WS		 4202 if (use_sg > h->ioaccel_maxsg) {
4203 addr64 = le64_to_cpu(
4204 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4205 curr_sg->address = cpu_to_le64(addr64);
4206 curr_sg->length = 0;
4207 curr_sg->reserved[0] = 0;
4208 curr_sg->reserved[1] = 0;
4209 curr_sg->reserved[2] = 0;
4210 curr_sg->chain_indicator = 0x80;
4211
4212 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4213 }
c349775e
ST		 4214 scsi_for_each_sg(cmd, sg, use_sg, i) {
4215 addr64 = (u64) sg_dma_address(sg);
4216 len = sg_dma_len(sg);
4217 total_len += len;
4218 curr_sg->address = cpu_to_le64(addr64);
4219 curr_sg->length = cpu_to_le32(len);
4220 curr_sg->reserved[0] = 0;
4221 curr_sg->reserved[1] = 0;
4222 curr_sg->reserved[2] = 0;
4223 curr_sg->chain_indicator = 0;
4224 curr_sg++;
4225 }
4226
4227 switch (cmd->sc_data_direction) {
4228 case DMA_TO_DEVICE:
dd0e19f3
ST		 4229 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4230 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 4231 break;
4232 case DMA_FROM_DEVICE:
dd0e19f3
ST		 4233 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4234 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 4235 break;
4236 case DMA_NONE:
dd0e19f3
ST		 4237 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4238 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 4239 break;
4240 default:
4241 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4242 cmd->sc_data_direction);
4243 BUG();
4244 break;
4245 }
4246 } else {
dd0e19f3
ST		 4247 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4248 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 4249 }
dd0e19f3
ST		 4250
4251 /* Set encryption parameters, if necessary */
4252 set_encrypt_ioaccel2(h, c, cp);
4253
2b08b3e9 4254 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 4255 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 4256 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 4257
c349775e
ST		 4258 cp->data_len = cpu_to_le32(total_len);
4259 cp->err_ptr = cpu_to_le64(c->busaddr +
4260 offsetof(struct io_accel2_cmd, error_data));
50a0decf 4261 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 4262
d9a729f3
WS		 4263 /* fill in sg elements */
4264 if (use_sg > h->ioaccel_maxsg) {
4265 cp->sg_count = 1;
4266 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4267 atomic_dec(&phys_disk->ioaccel_cmds_out);
4268 scsi_dma_unmap(cmd);
4269 return -1;
4270 }
4271 } else
4272 cp->sg_count = (u8) use_sg;
4273
c349775e
ST		 4274 enqueue_cmd_and_start_io(h, c);
4275 return 0;
4276}
4277
4278/*
4279 * Queue a command to the correct I/O accelerator path.
4280 */
4281static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4282 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4283 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 4284{
03383736
DB		 4285 /* Try to honor the device's queue depth */
4286 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4287 phys_disk->queue_depth) {
4288 atomic_dec(&phys_disk->ioaccel_cmds_out);
4289 return IO_ACCEL_INELIGIBLE;
4290 }
c349775e
ST		 4291 if (h->transMethod & CFGTBL_Trans_io_accel1)
4292 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4293 cdb, cdb_len, scsi3addr,
4294 phys_disk);
c349775e
ST		 4295 else
4296 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4297 cdb, cdb_len, scsi3addr,
4298 phys_disk);
c349775e
ST		 4299}
4300
6b80b18f
ST		 4301static void raid_map_helper(struct raid_map_data *map,
4302 int offload_to_mirror, u32 *map_index, u32 *current_group)
4303{
4304 if (offload_to_mirror == 0) {
4305 /* use physical disk in the first mirrored group. */
2b08b3e9 4306 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4307 return;
4308 }
4309 do {
4310 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4311 *current_group = *map_index /
4312 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4313 if (offload_to_mirror == *current_group)
4314 continue;
2b08b3e9 4315 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4316 /* select map index from next group */
2b08b3e9 4317 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4318 (*current_group)++;
4319 } else {
4320 /* select map index from first group */
2b08b3e9 4321 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4322 *current_group = 0;
4323 }
4324 } while (offload_to_mirror != *current_group);
4325}
4326
283b4a9b
SC		 4327/*
4328 * Attempt to perform offload RAID mapping for a logical volume I/O.
4329 */
4330static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4331 struct CommandList *c)
4332{
4333 struct scsi_cmnd *cmd = c->scsi_cmd;
4334 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4335 struct raid_map_data *map = &dev->raid_map;
4336 struct raid_map_disk_data *dd = &map->data[0];
4337 int is_write = 0;
4338 u32 map_index;
4339 u64 first_block, last_block;
4340 u32 block_cnt;
4341 u32 blocks_per_row;
4342 u64 first_row, last_row;
4343 u32 first_row_offset, last_row_offset;
4344 u32 first_column, last_column;
6b80b18f
ST		 4345 u64 r0_first_row, r0_last_row;
4346 u32 r5or6_blocks_per_row;
4347 u64 r5or6_first_row, r5or6_last_row;
4348 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4349 u32 r5or6_first_column, r5or6_last_column;
4350 u32 total_disks_per_row;
4351 u32 stripesize;
4352 u32 first_group, last_group, current_group;
283b4a9b
SC		 4353 u32 map_row;
4354 u32 disk_handle;
4355 u64 disk_block;
4356 u32 disk_block_cnt;
4357 u8 cdb[16];
4358 u8 cdb_len;
2b08b3e9 4359 u16 strip_size;
283b4a9b
SC		 4360#if BITS_PER_LONG == 32
4361 u64 tmpdiv;
4362#endif
6b80b18f 4363 int offload_to_mirror;
283b4a9b 4364
283b4a9b
SC		 4365 /* check for valid opcode, get LBA and block count */
4366 switch (cmd->cmnd[0]) {
4367 case WRITE_6:
4368 is_write = 1;
4369 case READ_6:
4370 first_block =
4371 (((u64) cmd->cmnd[2]) << 8) |
4372 cmd->cmnd[3];
4373 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4374 if (block_cnt == 0)
4375 block_cnt = 256;
283b4a9b
SC		 4376 break;
4377 case WRITE_10:
4378 is_write = 1;
4379 case READ_10:
4380 first_block =
4381 (((u64) cmd->cmnd[2]) << 24) |
4382 (((u64) cmd->cmnd[3]) << 16) |
4383 (((u64) cmd->cmnd[4]) << 8) |
4384 cmd->cmnd[5];
4385 block_cnt =
4386 (((u32) cmd->cmnd[7]) << 8) |
4387 cmd->cmnd[8];
4388 break;
4389 case WRITE_12:
4390 is_write = 1;
4391 case READ_12:
4392 first_block =
4393 (((u64) cmd->cmnd[2]) << 24) |
4394 (((u64) cmd->cmnd[3]) << 16) |
4395 (((u64) cmd->cmnd[4]) << 8) |
4396 cmd->cmnd[5];
4397 block_cnt =
4398 (((u32) cmd->cmnd[6]) << 24) |
4399 (((u32) cmd->cmnd[7]) << 16) |
4400 (((u32) cmd->cmnd[8]) << 8) |
4401 cmd->cmnd[9];
4402 break;
4403 case WRITE_16:
4404 is_write = 1;
4405 case READ_16:
4406 first_block =
4407 (((u64) cmd->cmnd[2]) << 56) |
4408 (((u64) cmd->cmnd[3]) << 48) |
4409 (((u64) cmd->cmnd[4]) << 40) |
4410 (((u64) cmd->cmnd[5]) << 32) |
4411 (((u64) cmd->cmnd[6]) << 24) |
4412 (((u64) cmd->cmnd[7]) << 16) |
4413 (((u64) cmd->cmnd[8]) << 8) |
4414 cmd->cmnd[9];
4415 block_cnt =
4416 (((u32) cmd->cmnd[10]) << 24) |
4417 (((u32) cmd->cmnd[11]) << 16) |
4418 (((u32) cmd->cmnd[12]) << 8) |
4419 cmd->cmnd[13];
4420 break;
4421 default:
4422 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4423 }
283b4a9b
SC		 4424 last_block = first_block + block_cnt - 1;
4425
4426 /* check for write to non-RAID-0 */
4427 if (is_write && dev->raid_level != 0)
4428 return IO_ACCEL_INELIGIBLE;
4429
4430 /* check for invalid block or wraparound */
2b08b3e9
DB		 4431 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4432 last_block < first_block)
283b4a9b
SC		 4433 return IO_ACCEL_INELIGIBLE;
4434
4435 /* calculate stripe information for the request */
2b08b3e9
DB		 4436 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4437 le16_to_cpu(map->strip_size);
4438 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4439#if BITS_PER_LONG == 32
4440 tmpdiv = first_block;
4441 (void) do_div(tmpdiv, blocks_per_row);
4442 first_row = tmpdiv;
4443 tmpdiv = last_block;
4444 (void) do_div(tmpdiv, blocks_per_row);
4445 last_row = tmpdiv;
4446 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4447 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4448 tmpdiv = first_row_offset;
2b08b3e9 4449 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4450 first_column = tmpdiv;
4451 tmpdiv = last_row_offset;
2b08b3e9 4452 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4453 last_column = tmpdiv;
4454#else
4455 first_row = first_block / blocks_per_row;
4456 last_row = last_block / blocks_per_row;
4457 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4458 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4459 first_column = first_row_offset / strip_size;
4460 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4461#endif
4462
4463 /* if this isn't a single row/column then give to the controller */
4464 if ((first_row != last_row) || (first_column != last_column))
4465 return IO_ACCEL_INELIGIBLE;
4466
4467 /* proceeding with driver mapping */
2b08b3e9
DB		 4468 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4469 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4470 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4471 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4472 map_index = (map_row * total_disks_per_row) + first_column;
4473
4474 switch (dev->raid_level) {
4475 case HPSA_RAID_0:
4476 break; /* nothing special to do */
4477 case HPSA_RAID_1:
4478 /* Handles load balance across RAID 1 members.
4479 * (2-drive R1 and R10 with even # of drives.)
4480 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4481 */
2b08b3e9 4482 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4483 if (dev->offload_to_mirror)
2b08b3e9 4484 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4485 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4486 break;
4487 case HPSA_RAID_ADM:
4488 /* Handles N-way mirrors (R1-ADM)
4489 * and R10 with # of drives divisible by 3.)
4490 */
2b08b3e9 4491 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4492
4493 offload_to_mirror = dev->offload_to_mirror;
4494 raid_map_helper(map, offload_to_mirror,
4495 &map_index, &current_group);
4496 /* set mirror group to use next time */
4497 offload_to_mirror =
2b08b3e9
DB		 4498 (offload_to_mirror >=
4499 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4500 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4501 dev->offload_to_mirror = offload_to_mirror;
4502 /* Avoid direct use of dev->offload_to_mirror within this
4503 * function since multiple threads might simultaneously
4504 * increment it beyond the range of dev->layout_map_count -1.
4505 */
4506 break;
4507 case HPSA_RAID_5:
4508 case HPSA_RAID_6:
2b08b3e9 4509 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4510 break;
4511
4512 /* Verify first and last block are in same RAID group */
4513 r5or6_blocks_per_row =
2b08b3e9
DB		 4514 le16_to_cpu(map->strip_size) *
4515 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4516 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4517 stripesize = r5or6_blocks_per_row *
4518 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4519#if BITS_PER_LONG == 32
4520 tmpdiv = first_block;
4521 first_group = do_div(tmpdiv, stripesize);
4522 tmpdiv = first_group;
4523 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4524 first_group = tmpdiv;
4525 tmpdiv = last_block;
4526 last_group = do_div(tmpdiv, stripesize);
4527 tmpdiv = last_group;
4528 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4529 last_group = tmpdiv;
4530#else
4531 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4532 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4533#endif
000ff7c2 4534 if (first_group != last_group)
6b80b18f
ST		 4535 return IO_ACCEL_INELIGIBLE;
4536
4537 /* Verify request is in a single row of RAID 5/6 */
4538#if BITS_PER_LONG == 32
4539 tmpdiv = first_block;
4540 (void) do_div(tmpdiv, stripesize);
4541 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4542 tmpdiv = last_block;
4543 (void) do_div(tmpdiv, stripesize);
4544 r5or6_last_row = r0_last_row = tmpdiv;
4545#else
4546 first_row = r5or6_first_row = r0_first_row =
4547 first_block / stripesize;
4548 r5or6_last_row = r0_last_row = last_block / stripesize;
4549#endif
4550 if (r5or6_first_row != r5or6_last_row)
4551 return IO_ACCEL_INELIGIBLE;
4552
4553
4554 /* Verify request is in a single column */
4555#if BITS_PER_LONG == 32
4556 tmpdiv = first_block;
4557 first_row_offset = do_div(tmpdiv, stripesize);
4558 tmpdiv = first_row_offset;
4559 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4560 r5or6_first_row_offset = first_row_offset;
4561 tmpdiv = last_block;
4562 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4563 tmpdiv = r5or6_last_row_offset;
4564 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4565 tmpdiv = r5or6_first_row_offset;
4566 (void) do_div(tmpdiv, map->strip_size);
4567 first_column = r5or6_first_column = tmpdiv;
4568 tmpdiv = r5or6_last_row_offset;
4569 (void) do_div(tmpdiv, map->strip_size);
4570 r5or6_last_column = tmpdiv;
4571#else
4572 first_row_offset = r5or6_first_row_offset =
4573 (u32)((first_block % stripesize) %
4574 r5or6_blocks_per_row);
4575
4576 r5or6_last_row_offset =
4577 (u32)((last_block % stripesize) %
4578 r5or6_blocks_per_row);
4579
4580 first_column = r5or6_first_column =
2b08b3e9 4581 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4582 r5or6_last_column =
2b08b3e9 4583 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4584#endif
4585 if (r5or6_first_column != r5or6_last_column)
4586 return IO_ACCEL_INELIGIBLE;
4587
4588 /* Request is eligible */
4589 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4590 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4591
4592 map_index = (first_group *
2b08b3e9 4593 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4594 (map_row * total_disks_per_row) + first_column;
4595 break;
4596 default:
4597 return IO_ACCEL_INELIGIBLE;
283b4a9b 4598 }
6b80b18f 4599
07543e0c
SC		 4600 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4601 return IO_ACCEL_INELIGIBLE;
4602
03383736
DB		 4603 c->phys_disk = dev->phys_disk[map_index];
4604
283b4a9b 4605 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 4606 disk_block = le64_to_cpu(map->disk_starting_blk) +
4607 first_row * le16_to_cpu(map->strip_size) +
4608 (first_row_offset - first_column *
4609 le16_to_cpu(map->strip_size));
283b4a9b
SC		 4610 disk_block_cnt = block_cnt;
4611
4612 /* handle differing logical/physical block sizes */
4613 if (map->phys_blk_shift) {
4614 disk_block <<= map->phys_blk_shift;
4615 disk_block_cnt <<= map->phys_blk_shift;
4616 }
4617 BUG_ON(disk_block_cnt > 0xffff);
4618
4619 /* build the new CDB for the physical disk I/O */
4620 if (disk_block > 0xffffffff) {
4621 cdb[0] = is_write ? WRITE_16 : READ_16;
4622 cdb[1] = 0;
4623 cdb[2] = (u8) (disk_block >> 56);
4624 cdb[3] = (u8) (disk_block >> 48);
4625 cdb[4] = (u8) (disk_block >> 40);
4626 cdb[5] = (u8) (disk_block >> 32);
4627 cdb[6] = (u8) (disk_block >> 24);
4628 cdb[7] = (u8) (disk_block >> 16);
4629 cdb[8] = (u8) (disk_block >> 8);
4630 cdb[9] = (u8) (disk_block);
4631 cdb[10] = (u8) (disk_block_cnt >> 24);
4632 cdb[11] = (u8) (disk_block_cnt >> 16);
4633 cdb[12] = (u8) (disk_block_cnt >> 8);
4634 cdb[13] = (u8) (disk_block_cnt);
4635 cdb[14] = 0;
4636 cdb[15] = 0;
4637 cdb_len = 16;
4638 } else {
4639 cdb[0] = is_write ? WRITE_10 : READ_10;
4640 cdb[1] = 0;
4641 cdb[2] = (u8) (disk_block >> 24);
4642 cdb[3] = (u8) (disk_block >> 16);
4643 cdb[4] = (u8) (disk_block >> 8);
4644 cdb[5] = (u8) (disk_block);
4645 cdb[6] = 0;
4646 cdb[7] = (u8) (disk_block_cnt >> 8);
4647 cdb[8] = (u8) (disk_block_cnt);
4648 cdb[9] = 0;
4649 cdb_len = 10;
4650 }
4651 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 4652 dev->scsi3addr,
4653 dev->phys_disk[map_index]);
283b4a9b
SC		 4654}
4655
25163bd5
WS		 4656/*
4657 * Submit commands down the "normal" RAID stack path
4658 * All callers to hpsa_ciss_submit must check lockup_detected
4659 * beforehand, before (opt.) and after calling cmd_alloc
4660 */
574f05d3
SC		 4661static int hpsa_ciss_submit(struct ctlr_info *h,
4662 struct CommandList *c, struct scsi_cmnd *cmd,
4663 unsigned char scsi3addr[])
edd16368 4664{
edd16368 4665 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 4666 c->cmd_type = CMD_SCSI;
4667 c->scsi_cmd = cmd;
4668 c->Header.ReplyQueue = 0; /* unused in simple mode */
4669 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 4670 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 4671
4672 /* Fill in the request block... */
4673
4674 c->Request.Timeout = 0;
edd16368
SC		 4675 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4676 c->Request.CDBLen = cmd->cmd_len;
4677 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 4678 switch (cmd->sc_data_direction) {
4679 case DMA_TO_DEVICE:
a505b86f
SC		 4680 c->Request.type_attr_dir =
4681 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 4682 break;
4683 case DMA_FROM_DEVICE:
a505b86f
SC		 4684 c->Request.type_attr_dir =
4685 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 4686 break;
4687 case DMA_NONE:
a505b86f
SC		 4688 c->Request.type_attr_dir =
4689 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 4690 break;
4691 case DMA_BIDIRECTIONAL:
4692 /* This can happen if a buggy application does a scsi passthru
4693 * and sets both inlen and outlen to non-zero. ( see
4694 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4695 */
4696
a505b86f
SC		 4697 c->Request.type_attr_dir =
4698 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 4699 /* This is technically wrong, and hpsa controllers should
4700 * reject it with CMD_INVALID, which is the most correct
4701 * response, but non-fibre backends appear to let it
4702 * slide by, and give the same results as if this field
4703 * were set correctly. Either way is acceptable for
4704 * our purposes here.
4705 */
4706
4707 break;
4708
4709 default:
4710 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4711 cmd->sc_data_direction);
4712 BUG();
4713 break;
4714 }
4715
33a2ffce 4716 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
73153fe5 4717 hpsa_cmd_resolve_and_free(h, c);
edd16368
SC		 4718 return SCSI_MLQUEUE_HOST_BUSY;
4719 }
4720 enqueue_cmd_and_start_io(h, c);
4721 /* the cmd'll come back via intr handler in complete_scsi_command() */
4722 return 0;
4723}
4724
360c73bd
SC		 4725static void hpsa_cmd_init(struct ctlr_info *h, int index,
4726 struct CommandList *c)
4727{
4728 dma_addr_t cmd_dma_handle, err_dma_handle;
4729
4730 /* Zero out all of commandlist except the last field, refcount */
4731 memset(c, 0, offsetof(struct CommandList, refcount));
4732 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
4733 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4734 c->err_info = h->errinfo_pool + index;
4735 memset(c->err_info, 0, sizeof(*c->err_info));
4736 err_dma_handle = h->errinfo_pool_dhandle
4737 + index * sizeof(*c->err_info);
4738 c->cmdindex = index;
4739 c->busaddr = (u32) cmd_dma_handle;
4740 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4741 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
4742 c->h = h;
a58e7e53 4743 c->scsi_cmd = SCSI_CMD_IDLE;
360c73bd
SC		 4744}
4745
4746static void hpsa_preinitialize_commands(struct ctlr_info *h)
4747{
4748 int i;
4749
4750 for (i = 0; i < h->nr_cmds; i++) {
4751 struct CommandList *c = h->cmd_pool + i;
4752
4753 hpsa_cmd_init(h, i, c);
4754 atomic_set(&c->refcount, 0);
4755 }
4756}
4757
4758static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
4759 struct CommandList *c)
4760{
4761 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4762
73153fe5
WS		 4763 BUG_ON(c->cmdindex != index);
4764
360c73bd
SC		 4765 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4766 memset(c->err_info, 0, sizeof(*c->err_info));
4767 c->busaddr = (u32) cmd_dma_handle;
4768}
4769
592a0ad5
WS		 4770static int hpsa_ioaccel_submit(struct ctlr_info *h,
4771 struct CommandList *c, struct scsi_cmnd *cmd,
4772 unsigned char *scsi3addr)
4773{
4774 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4775 int rc = IO_ACCEL_INELIGIBLE;
4776
4777 cmd->host_scribble = (unsigned char *) c;
4778
4779 if (dev->offload_enabled) {
4780 hpsa_cmd_init(h, c->cmdindex, c);
4781 c->cmd_type = CMD_SCSI;
4782 c->scsi_cmd = cmd;
4783 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4784 if (rc < 0) /* scsi_dma_map failed. */
4785 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 4786 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 4787 hpsa_cmd_init(h, c->cmdindex, c);
4788 c->cmd_type = CMD_SCSI;
4789 c->scsi_cmd = cmd;
4790 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4791 if (rc < 0) /* scsi_dma_map failed. */
4792 rc = SCSI_MLQUEUE_HOST_BUSY;
4793 }
4794 return rc;
4795}
4796
080ef1cc
DB		 4797static void hpsa_command_resubmit_worker(struct work_struct *work)
4798{
4799 struct scsi_cmnd *cmd;
4800 struct hpsa_scsi_dev_t *dev;
8a0ff92c 4801 struct CommandList *c = container_of(work, struct CommandList, work);
080ef1cc
DB		 4802
4803 cmd = c->scsi_cmd;
4804 dev = cmd->device->hostdata;
4805 if (!dev) {
4806 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 4807 return hpsa_cmd_free_and_done(c->h, c, cmd);
080ef1cc 4808 }
d604f533
WS		 4809 if (c->reset_pending)
4810 return hpsa_cmd_resolve_and_free(c->h, c);
a58e7e53
WS		 4811 if (c->abort_pending)
4812 return hpsa_cmd_abort_and_free(c->h, c, cmd);
592a0ad5
WS		 4813 if (c->cmd_type == CMD_IOACCEL2) {
4814 struct ctlr_info *h = c->h;
4815 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
4816 int rc;
4817
4818 if (c2->error_data.serv_response ==
4819 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
4820 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
4821 if (rc == 0)
4822 return;
4823 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4824 /*
4825 * If we get here, it means dma mapping failed.
4826 * Try again via scsi mid layer, which will
4827 * then get SCSI_MLQUEUE_HOST_BUSY.
4828 */
4829 cmd->result = DID_IMM_RETRY << 16;
8a0ff92c 4830 return hpsa_cmd_free_and_done(h, c, cmd);
592a0ad5
WS		 4831 }
4832 /* else, fall thru and resubmit down CISS path */
4833 }
4834 }
360c73bd 4835 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 4836 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4837 /*
4838 * If we get here, it means dma mapping failed. Try
4839 * again via scsi mid layer, which will then get
4840 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 4841 *
4842 * hpsa_ciss_submit will have already freed c
4843 * if it encountered a dma mapping failure.
080ef1cc
DB		 4844 */
4845 cmd->result = DID_IMM_RETRY << 16;
4846 cmd->scsi_done(cmd);
4847 }
4848}
4849
574f05d3
SC		 4850/* Running in struct Scsi_Host->host_lock less mode */
4851static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4852{
4853 struct ctlr_info *h;
4854 struct hpsa_scsi_dev_t *dev;
4855 unsigned char scsi3addr[8];
4856 struct CommandList *c;
4857 int rc = 0;
4858
4859 /* Get the ptr to our adapter structure out of cmd->host. */
4860 h = sdev_to_hba(cmd->device);
73153fe5
WS		 4861
4862 BUG_ON(cmd->request->tag < 0);
4863
574f05d3
SC		 4864 dev = cmd->device->hostdata;
4865 if (!dev) {
4866 cmd->result = DID_NO_CONNECT << 16;
4867 cmd->scsi_done(cmd);
4868 return 0;
4869 }
574f05d3 4870
73153fe5 4871 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
bf43caf3 4872
407863cb 4873 if (unlikely(lockup_detected(h))) {
25163bd5 4874 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 4875 cmd->scsi_done(cmd);
4876 return 0;
4877 }
73153fe5 4878 c = cmd_tagged_alloc(h, cmd);
574f05d3 4879
407863cb
SC		 4880 /*
4881 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 4882 * Retries always go down the normal I/O path.
4883 */
4884 if (likely(cmd->retries == 0 &&
4885 cmd->request->cmd_type == REQ_TYPE_FS &&
4886 h->acciopath_status)) {
592a0ad5
WS		 4887 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
4888 if (rc == 0)
4889 return 0;
4890 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
73153fe5 4891 hpsa_cmd_resolve_and_free(h, c);
592a0ad5 4892 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 4893 }
4894 }
4895 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4896}
4897
8ebc9248 4898static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 4899{
4900 unsigned long flags;
4901
8ebc9248
WS		 4902 spin_lock_irqsave(&h->scan_lock, flags);
4903 h->scan_finished = 1;
4904 wake_up_all(&h->scan_wait_queue);
4905 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 4906}
4907
a08a8471
SC		 4908static void hpsa_scan_start(struct Scsi_Host *sh)
4909{
4910 struct ctlr_info *h = shost_to_hba(sh);
4911 unsigned long flags;
4912
8ebc9248
WS		 4913 /*
4914 * Don't let rescans be initiated on a controller known to be locked
4915 * up. If the controller locks up *during* a rescan, that thread is
4916 * probably hosed, but at least we can prevent new rescan threads from
4917 * piling up on a locked up controller.
4918 */
4919 if (unlikely(lockup_detected(h)))
4920 return hpsa_scan_complete(h);
5f389360 4921
a08a8471
SC		 4922 /* wait until any scan already in progress is finished. */
4923 while (1) {
4924 spin_lock_irqsave(&h->scan_lock, flags);
4925 if (h->scan_finished)
4926 break;
4927 spin_unlock_irqrestore(&h->scan_lock, flags);
4928 wait_event(h->scan_wait_queue, h->scan_finished);
4929 /* Note: We don't need to worry about a race between this
4930 * thread and driver unload because the midlayer will
4931 * have incremented the reference count, so unload won't
4932 * happen if we're in here.
4933 */
4934 }
4935 h->scan_finished = 0; /* mark scan as in progress */
4936 spin_unlock_irqrestore(&h->scan_lock, flags);
4937
8ebc9248
WS		 4938 if (unlikely(lockup_detected(h)))
4939 return hpsa_scan_complete(h);
5f389360 4940
a08a8471
SC		 4941 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4942
8ebc9248 4943 hpsa_scan_complete(h);
a08a8471
SC		 4944}
4945
7c0a0229
DB		 4946static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4947{
03383736
DB		 4948 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
4949
4950 if (!logical_drive)
4951 return -ENODEV;
7c0a0229
DB		 4952
4953 if (qdepth < 1)
4954 qdepth = 1;
03383736
DB		 4955 else if (qdepth > logical_drive->queue_depth)
4956 qdepth = logical_drive->queue_depth;
4957
4958 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 4959}
4960
a08a8471
SC		 4961static int hpsa_scan_finished(struct Scsi_Host *sh,
4962 unsigned long elapsed_time)
4963{
4964 struct ctlr_info *h = shost_to_hba(sh);
4965 unsigned long flags;
4966 int finished;
4967
4968 spin_lock_irqsave(&h->scan_lock, flags);
4969 finished = h->scan_finished;
4970 spin_unlock_irqrestore(&h->scan_lock, flags);
4971 return finished;
4972}
4973
2946e82b 4974static int hpsa_scsi_host_alloc(struct ctlr_info *h)
edd16368 4975{
b705690d
SC		 4976 struct Scsi_Host *sh;
4977 int error;
edd16368 4978
b705690d 4979 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2946e82b
RE		 4980 if (sh == NULL) {
4981 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
4982 return -ENOMEM;
4983 }
b705690d
SC		 4984
4985 sh->io_port = 0;
4986 sh->n_io_port = 0;
4987 sh->this_id = -1;
4988 sh->max_channel = 3;
4989 sh->max_cmd_len = MAX_COMMAND_SIZE;
4990 sh->max_lun = HPSA_MAX_LUN;
4991 sh->max_id = HPSA_MAX_LUN;
41ce4c35 4992 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 4993 sh->cmd_per_lun = sh->can_queue;
b705690d 4994 sh->sg_tablesize = h->maxsgentries;
b705690d
SC		 4995 sh->hostdata[0] = (unsigned long) h;
4996 sh->irq = h->intr[h->intr_mode];
4997 sh->unique_id = sh->irq;
73153fe5
WS		 4998 error = scsi_init_shared_tag_map(sh, sh->can_queue);
4999 if (error) {
5000 dev_err(&h->pdev->dev,
5001 "%s: scsi_init_shared_tag_map failed for controller %d\n",
5002 __func__, h->ctlr);
2946e82b
RE		 5003 scsi_host_put(sh);
5004 return error;
73153fe5 5005 }
2946e82b 5006 h->scsi_host = sh;
b705690d 5007 return 0;
2946e82b 5008}
b705690d 5009
2946e82b
RE		 5010static int hpsa_scsi_add_host(struct ctlr_info *h)
5011{
5012 int rv;
5013
5014 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
5015 if (rv) {
5016 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
5017 return rv;
5018 }
5019 scsi_scan_host(h->scsi_host);
5020 return 0;
edd16368
SC		 5021}
5022
73153fe5
WS		 5023/*
5024 * The block layer has already gone to the trouble of picking out a unique,
5025 * small-integer tag for this request. We use an offset from that value as
5026 * an index to select our command block. (The offset allows us to reserve the
5027 * low-numbered entries for our own uses.)
5028 */
5029static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
5030{
5031 int idx = scmd->request->tag;
5032
5033 if (idx < 0)
5034 return idx;
5035
5036 /* Offset to leave space for internal cmds. */
5037 return idx += HPSA_NRESERVED_CMDS;
5038}
5039
b69324ff
WS		 5040/*
5041 * Send a TEST_UNIT_READY command to the specified LUN using the specified
5042 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5043 */
5044static int hpsa_send_test_unit_ready(struct ctlr_info *h,
5045 struct CommandList *c, unsigned char lunaddr[],
5046 int reply_queue)
5047{
5048 int rc;
5049
5050 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
5051 (void) fill_cmd(c, TEST_UNIT_READY, h,
5052 NULL, 0, 0, lunaddr, TYPE_CMD);
5053 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5054 if (rc)
5055 return rc;
5056 /* no unmap needed here because no data xfer. */
5057
5058 /* Check if the unit is already ready. */
5059 if (c->err_info->CommandStatus == CMD_SUCCESS)
5060 return 0;
5061
5062 /*
5063 * The first command sent after reset will receive "unit attention" to
5064 * indicate that the LUN has been reset...this is actually what we're
5065 * looking for (but, success is good too).
5066 */
5067 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5068 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5069 (c->err_info->SenseInfo[2] == NO_SENSE ||
5070 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5071 return 0;
5072
5073 return 1;
5074}
5075
5076/*
5077 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5078 * returns zero when the unit is ready, and non-zero when giving up.
5079 */
5080static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5081 struct CommandList *c,
5082 unsigned char lunaddr[], int reply_queue)
edd16368 5083{
8919358e 5084 int rc;
edd16368
SC		 5085 int count = 0;
5086 int waittime = 1; /* seconds */
edd16368
SC		 5087
5088 /* Send test unit ready until device ready, or give up. */
b69324ff 5089 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
edd16368 5090
b69324ff
WS		 5091 /*
5092 * Wait for a bit. do this first, because if we send
edd16368
SC		 5093 * the TUR right away, the reset will just abort it.
5094 */
5095 msleep(1000 * waittime);
b69324ff
WS		 5096
5097 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5098 if (!rc)
5099 break;
edd16368
SC		 5100
5101 /* Increase wait time with each try, up to a point. */
5102 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
b69324ff 5103 waittime *= 2;
edd16368 5104
b69324ff
WS		 5105 dev_warn(&h->pdev->dev,
5106 "waiting %d secs for device to become ready.\n",
5107 waittime);
5108 }
edd16368 5109
b69324ff
WS		 5110 return rc;
5111}
edd16368 5112
b69324ff
WS		 5113static int wait_for_device_to_become_ready(struct ctlr_info *h,
5114 unsigned char lunaddr[],
5115 int reply_queue)
5116{
5117 int first_queue;
5118 int last_queue;
5119 int rq;
5120 int rc = 0;
5121 struct CommandList *c;
5122
5123 c = cmd_alloc(h);
5124
5125 /*
5126 * If no specific reply queue was requested, then send the TUR
5127 * repeatedly, requesting a reply on each reply queue; otherwise execute
5128 * the loop exactly once using only the specified queue.
5129 */
5130 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5131 first_queue = 0;
5132 last_queue = h->nreply_queues - 1;
5133 } else {
5134 first_queue = reply_queue;
5135 last_queue = reply_queue;
5136 }
5137
5138 for (rq = first_queue; rq <= last_queue; rq++) {
5139 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5140 if (rc)
edd16368 5141 break;
edd16368
SC		 5142 }
5143
5144 if (rc)
5145 dev_warn(&h->pdev->dev, "giving up on device.\n");
5146 else
5147 dev_warn(&h->pdev->dev, "device is ready.\n");
5148
45fcb86e 5149 cmd_free(h, c);
edd16368
SC		 5150 return rc;
5151}
5152
5153/* Need at least one of these error handlers to keep ../scsi/hosts.c from
5154 * complaining. Doing a host- or bus-reset can't do anything good here.
5155 */
5156static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5157{
5158 int rc;
5159 struct ctlr_info *h;
5160 struct hpsa_scsi_dev_t *dev;
2dc127bb 5161 char msg[48];
edd16368
SC		 5162
5163 /* find the controller to which the command to be aborted was sent */
5164 h = sdev_to_hba(scsicmd->device);
5165 if (h == NULL) /* paranoia */
5166 return FAILED;
e345893b
DB		 5167
5168 if (lockup_detected(h))
5169 return FAILED;
5170
edd16368
SC		 5171 dev = scsicmd->device->hostdata;
5172 if (!dev) {
d604f533 5173 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
edd16368
SC		 5174 return FAILED;
5175 }
25163bd5
WS		 5176
5177 /* if controller locked up, we can guarantee command won't complete */
5178 if (lockup_detected(h)) {
2dc127bb
DC		 5179 snprintf(msg, sizeof(msg),
5180 "cmd %d RESET FAILED, lockup detected",
5181 hpsa_get_cmd_index(scsicmd));
73153fe5 5182 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5183 return FAILED;
5184 }
5185
5186 /* this reset request might be the result of a lockup; check */
5187 if (detect_controller_lockup(h)) {
2dc127bb
DC		 5188 snprintf(msg, sizeof(msg),
5189 "cmd %d RESET FAILED, new lockup detected",
5190 hpsa_get_cmd_index(scsicmd));
73153fe5 5191 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5192 return FAILED;
5193 }
5194
d604f533
WS		 5195 /* Do not attempt on controller */
5196 if (is_hba_lunid(dev->scsi3addr))
5197 return SUCCESS;
5198
25163bd5
WS		 5199 hpsa_show_dev_msg(KERN_WARNING, h, dev, "resetting");
5200
edd16368 5201 /* send a reset to the SCSI LUN which the command was sent to */
d604f533
WS		 5202 rc = hpsa_do_reset(h, dev, dev->scsi3addr, HPSA_RESET_TYPE_LUN,
5203 DEFAULT_REPLY_QUEUE);
2dc127bb
DC		 5204 snprintf(msg, sizeof(msg), "reset %s",
5205 rc == 0 ? "completed successfully" : "failed");
d604f533
WS		 5206 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
5207 return rc == 0 ? SUCCESS : FAILED;
edd16368
SC		 5208}
5209
6cba3f19
SC		 5210static void swizzle_abort_tag(u8 *tag)
5211{
5212 u8 original_tag[8];
5213
5214 memcpy(original_tag, tag, 8);
5215 tag[0] = original_tag[3];
5216 tag[1] = original_tag[2];
5217 tag[2] = original_tag[1];
5218 tag[3] = original_tag[0];
5219 tag[4] = original_tag[7];
5220 tag[5] = original_tag[6];
5221 tag[6] = original_tag[5];
5222 tag[7] = original_tag[4];
5223}
5224
17eb87d2 5225static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 5226 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 5227{
2b08b3e9 5228 u64 tag;
17eb87d2
ST		 5229 if (c->cmd_type == CMD_IOACCEL1) {
5230 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5231 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 5232 tag = le64_to_cpu(cm1->tag);
5233 *tagupper = cpu_to_le32(tag >> 32);
5234 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 5235 return;
5236 }
5237 if (c->cmd_type == CMD_IOACCEL2) {
5238 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5239 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 5240 /* upper tag not used in ioaccel2 mode */
5241 memset(tagupper, 0, sizeof(*tagupper));
5242 *taglower = cm2->Tag;
54b6e9e9 5243 return;
17eb87d2 5244 }
2b08b3e9
DB		 5245 tag = le64_to_cpu(c->Header.tag);
5246 *tagupper = cpu_to_le32(tag >> 32);
5247 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 5248}
5249
75167d2c 5250static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 5251 struct CommandList *abort, int reply_queue)
75167d2c
SC		 5252{
5253 int rc = IO_OK;
5254 struct CommandList *c;
5255 struct ErrorInfo *ei;
2b08b3e9 5256 __le32 tagupper, taglower;
75167d2c 5257
45fcb86e 5258 c = cmd_alloc(h);
75167d2c 5259
a2dac136 5260 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 5261 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 5262 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 5263 if (h->needs_abort_tags_swizzled)
6cba3f19 5264 swizzle_abort_tag(&c->Request.CDB[4]);
25163bd5 5265 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
17eb87d2 5266 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5267 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 5268 __func__, tagupper, taglower);
75167d2c
SC		 5269 /* no unmap needed here because no data xfer. */
5270
5271 ei = c->err_info;
5272 switch (ei->CommandStatus) {
5273 case CMD_SUCCESS:
5274 break;
9437ac43
SC		 5275 case CMD_TMF_STATUS:
5276 rc = hpsa_evaluate_tmf_status(h, c);
5277 break;
75167d2c
SC		 5278 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5279 rc = -1;
5280 break;
5281 default:
5282 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 5283 __func__, tagupper, taglower);
d1e8beac 5284 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 5285 rc = -1;
5286 break;
5287 }
45fcb86e 5288 cmd_free(h, c);
dd0e19f3
ST		 5289 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5290 __func__, tagupper, taglower);
75167d2c
SC		 5291 return rc;
5292}
5293
8be986cc
SC		 5294static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5295 struct CommandList *command_to_abort, int reply_queue)
5296{
5297 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5298 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5299 struct io_accel2_cmd *c2a =
5300 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
a58e7e53 5301 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
8be986cc
SC		 5302 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5303
5304 /*
5305 * We're overlaying struct hpsa_tmf_struct on top of something which
5306 * was allocated as a struct io_accel2_cmd, so we better be sure it
5307 * actually fits, and doesn't overrun the error info space.
5308 */
5309 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5310 sizeof(struct io_accel2_cmd));
5311 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5312 offsetof(struct hpsa_tmf_struct, error_len) +
5313 sizeof(ac->error_len));
5314
5315 c->cmd_type = IOACCEL2_TMF;
a58e7e53
WS		 5316 c->scsi_cmd = SCSI_CMD_BUSY;
5317
8be986cc
SC		 5318 /* Adjust the DMA address to point to the accelerated command buffer */
5319 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5320 (c->cmdindex * sizeof(struct io_accel2_cmd));
5321 BUG_ON(c->busaddr & 0x0000007F);
5322
5323 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5324 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5325 ac->reply_queue = reply_queue;
5326 ac->tmf = IOACCEL2_TMF_ABORT;
5327 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5328 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5329 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5330 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5331 ac->error_ptr = cpu_to_le64(c->busaddr +
5332 offsetof(struct io_accel2_cmd, error_data));
5333 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5334}
5335
54b6e9e9
ST		 5336/* ioaccel2 path firmware cannot handle abort task requests.
5337 * Change abort requests to physical target reset, and send to the
5338 * address of the physical disk used for the ioaccel 2 command.
5339 * Return 0 on success (IO_OK)
5340 * -1 on failure
5341 */
5342
5343static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 5344 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 5345{
5346 int rc = IO_OK;
5347 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5348 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5349 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5350 unsigned char *psa = &phys_scsi3addr[0];
5351
5352 /* Get a pointer to the hpsa logical device. */
7fa3030c 5353 scmd = abort->scsi_cmd;
54b6e9e9
ST		 5354 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5355 if (dev == NULL) {
5356 dev_warn(&h->pdev->dev,
5357 "Cannot abort: no device pointer for command.\n");
5358 return -1; /* not abortable */
5359 }
5360
2ba8bfc8
SC		 5361 if (h->raid_offload_debug > 0)
5362 dev_info(&h->pdev->dev,
0d96ef5f 5363 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 5364 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 5365 "Reset as abort",
2ba8bfc8
SC		 5366 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5367 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5368
54b6e9e9
ST		 5369 if (!dev->offload_enabled) {
5370 dev_warn(&h->pdev->dev,
5371 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5372 return -1; /* not abortable */
5373 }
5374
5375 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5376 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5377 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5378 return -1; /* not abortable */
5379 }
5380
5381 /* send the reset */
2ba8bfc8
SC		 5382 if (h->raid_offload_debug > 0)
5383 dev_info(&h->pdev->dev,
5384 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5385 psa[0], psa[1], psa[2], psa[3],
5386 psa[4], psa[5], psa[6], psa[7]);
d604f533 5387 rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 5388 if (rc != 0) {
5389 dev_warn(&h->pdev->dev,
5390 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5391 psa[0], psa[1], psa[2], psa[3],
5392 psa[4], psa[5], psa[6], psa[7]);
5393 return rc; /* failed to reset */
5394 }
5395
5396 /* wait for device to recover */
b69324ff 5397 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
54b6e9e9
ST		 5398 dev_warn(&h->pdev->dev,
5399 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5400 psa[0], psa[1], psa[2], psa[3],
5401 psa[4], psa[5], psa[6], psa[7]);
5402 return -1; /* failed to recover */
5403 }
5404
5405 /* device recovered */
5406 dev_info(&h->pdev->dev,
5407 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5408 psa[0], psa[1], psa[2], psa[3],
5409 psa[4], psa[5], psa[6], psa[7]);
5410
5411 return rc; /* success */
5412}
5413
8be986cc
SC		 5414static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
5415 struct CommandList *abort, int reply_queue)
5416{
5417 int rc = IO_OK;
5418 struct CommandList *c;
5419 __le32 taglower, tagupper;
5420 struct hpsa_scsi_dev_t *dev;
5421 struct io_accel2_cmd *c2;
5422
5423 dev = abort->scsi_cmd->device->hostdata;
5424 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
5425 return -1;
5426
5427 c = cmd_alloc(h);
5428 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
5429 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5430 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5431 hpsa_get_tag(h, abort, &taglower, &tagupper);
5432 dev_dbg(&h->pdev->dev,
5433 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
5434 __func__, tagupper, taglower);
5435 /* no unmap needed here because no data xfer. */
5436
5437 dev_dbg(&h->pdev->dev,
5438 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
5439 __func__, tagupper, taglower, c2->error_data.serv_response);
5440 switch (c2->error_data.serv_response) {
5441 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
5442 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
5443 rc = 0;
5444 break;
5445 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
5446 case IOACCEL2_SERV_RESPONSE_FAILURE:
5447 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
5448 rc = -1;
5449 break;
5450 default:
5451 dev_warn(&h->pdev->dev,
5452 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
5453 __func__, tagupper, taglower,
5454 c2->error_data.serv_response);
5455 rc = -1;
5456 }
5457 cmd_free(h, c);
5458 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
5459 tagupper, taglower);
5460 return rc;
5461}
5462
6cba3f19 5463static int hpsa_send_abort_both_ways(struct ctlr_info *h,
25163bd5 5464 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
6cba3f19 5465{
8be986cc
SC		 5466 /*
5467 * ioccelerator mode 2 commands should be aborted via the
54b6e9e9 5468 * accelerated path, since RAID path is unaware of these commands,
8be986cc
SC		 5469 * but not all underlying firmware can handle abort TMF.
5470 * Change abort to physical device reset when abort TMF is unsupported.
54b6e9e9 5471 */
8be986cc
SC		 5472 if (abort->cmd_type == CMD_IOACCEL2) {
5473 if (HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)
5474 return hpsa_send_abort_ioaccel2(h, abort,
5475 reply_queue);
5476 else
5477 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
25163bd5 5478 abort, reply_queue);
8be986cc 5479 }
9b5c48c2 5480 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
25163bd5 5481}
54b6e9e9 5482
25163bd5
WS		 5483/* Find out which reply queue a command was meant to return on */
5484static int hpsa_extract_reply_queue(struct ctlr_info *h,
5485 struct CommandList *c)
5486{
5487 if (c->cmd_type == CMD_IOACCEL2)
5488 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5489 return c->Header.ReplyQueue;
6cba3f19
SC		 5490}
5491
9b5c48c2
SC		 5492/*
5493 * Limit concurrency of abort commands to prevent
5494 * over-subscription of commands
5495 */
5496static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5497{
5498#define ABORT_CMD_WAIT_MSECS 5000
5499 return !wait_event_timeout(h->abort_cmd_wait_queue,
5500 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5501 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5502}
5503
75167d2c
SC		 5504/* Send an abort for the specified command.
5505 * If the device and controller support it,
5506 * send a task abort request.
5507 */
5508static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5509{
5510
a58e7e53 5511 int rc;
75167d2c
SC		 5512 struct ctlr_info *h;
5513 struct hpsa_scsi_dev_t *dev;
5514 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 5515 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
5516 char msg[256]; /* For debug messaging. */
5517 int ml = 0;
2b08b3e9 5518 __le32 tagupper, taglower;
25163bd5
WS		 5519 int refcount, reply_queue;
5520
5521 if (sc == NULL)
5522 return FAILED;
75167d2c 5523
9b5c48c2
SC		 5524 if (sc->device == NULL)
5525 return FAILED;
5526
75167d2c
SC		 5527 /* Find the controller of the command to be aborted */
5528 h = sdev_to_hba(sc->device);
9b5c48c2 5529 if (h == NULL)
75167d2c
SC		 5530 return FAILED;
5531
25163bd5
WS		 5532 /* Find the device of the command to be aborted */
5533 dev = sc->device->hostdata;
5534 if (!dev) {
5535 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
5536 msg);
e345893b 5537 return FAILED;
25163bd5
WS		 5538 }
5539
5540 /* If controller locked up, we can guarantee command won't complete */
5541 if (lockup_detected(h)) {
5542 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5543 "ABORT FAILED, lockup detected");
5544 return FAILED;
5545 }
5546
5547 /* This is a good time to check if controller lockup has occurred */
5548 if (detect_controller_lockup(h)) {
5549 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5550 "ABORT FAILED, new lockup detected");
5551 return FAILED;
5552 }
e345893b 5553
75167d2c
SC		 5554 /* Check that controller supports some kind of task abort */
5555 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5556 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5557 return FAILED;
5558
5559 memset(msg, 0, sizeof(msg));
4b761557 5560 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
75167d2c 5561 h->scsi_host->host_no, sc->device->channel,
0d96ef5f 5562 sc->device->id, sc->device->lun,
4b761557 5563 "Aborting command", sc);
75167d2c 5564
75167d2c
SC		 5565 /* Get SCSI command to be aborted */
5566 abort = (struct CommandList *) sc->host_scribble;
5567 if (abort == NULL) {
281a7fd0
WS		 5568 /* This can happen if the command already completed. */
5569 return SUCCESS;
5570 }
5571 refcount = atomic_inc_return(&abort->refcount);
5572 if (refcount == 1) { /* Command is done already. */
5573 cmd_free(h, abort);
5574 return SUCCESS;
75167d2c 5575 }
9b5c48c2
SC		 5576
5577 /* Don't bother trying the abort if we know it won't work. */
5578 if (abort->cmd_type != CMD_IOACCEL2 &&
5579 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5580 cmd_free(h, abort);
5581 return FAILED;
5582 }
5583
a58e7e53
WS		 5584 /*
5585 * Check that we're aborting the right command.
5586 * It's possible the CommandList already completed and got re-used.
5587 */
5588 if (abort->scsi_cmd != sc) {
5589 cmd_free(h, abort);
5590 return SUCCESS;
5591 }
5592
5593 abort->abort_pending = true;
17eb87d2 5594 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5595 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 5596 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 5597 as = abort->scsi_cmd;
75167d2c 5598 if (as != NULL)
4b761557
RE		 5599 ml += sprintf(msg+ml,
5600 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
5601 as->cmd_len, as->cmnd[0], as->cmnd[1],
5602 as->serial_number);
5603 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
0d96ef5f 5604 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
4b761557 5605
75167d2c
SC		 5606 /*
5607 * Command is in flight, or possibly already completed
5608 * by the firmware (but not to the scsi mid layer) but we can't
5609 * distinguish which. Send the abort down.
5610 */
9b5c48c2
SC		 5611 if (wait_for_available_abort_cmd(h)) {
5612 dev_warn(&h->pdev->dev,
4b761557
RE		 5613 "%s FAILED, timeout waiting for an abort command to become available.\n",
5614 msg);
9b5c48c2
SC		 5615 cmd_free(h, abort);
5616 return FAILED;
5617 }
25163bd5 5618 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
9b5c48c2
SC		 5619 atomic_inc(&h->abort_cmds_available);
5620 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 5621 if (rc != 0) {
4b761557 5622 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
0d96ef5f 5623 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4b761557 5624 "FAILED to abort command");
281a7fd0 5625 cmd_free(h, abort);
75167d2c
SC		 5626 return FAILED;
5627 }
4b761557 5628 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
d604f533 5629 wait_event(h->event_sync_wait_queue,
a58e7e53 5630 abort->scsi_cmd != sc || lockup_detected(h));
281a7fd0 5631 cmd_free(h, abort);
a58e7e53 5632 return !lockup_detected(h) ? SUCCESS : FAILED;
75167d2c
SC		 5633}
5634
73153fe5
WS		 5635/*
5636 * For operations with an associated SCSI command, a command block is allocated
5637 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
5638 * block request tag as an index into a table of entries. cmd_tagged_free() is
5639 * the complement, although cmd_free() may be called instead.
5640 */
5641static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
5642 struct scsi_cmnd *scmd)
5643{
5644 int idx = hpsa_get_cmd_index(scmd);
5645 struct CommandList *c = h->cmd_pool + idx;
5646
5647 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
5648 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
5649 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
5650 /* The index value comes from the block layer, so if it's out of
5651 * bounds, it's probably not our bug.
5652 */
5653 BUG();
5654 }
5655
5656 atomic_inc(&c->refcount);
5657 if (unlikely(!hpsa_is_cmd_idle(c))) {
5658 /*
5659 * We expect that the SCSI layer will hand us a unique tag
5660 * value. Thus, there should never be a collision here between
5661 * two requests...because if the selected command isn't idle
5662 * then someone is going to be very disappointed.
5663 */
5664 dev_err(&h->pdev->dev,
5665 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
5666 idx);
5667 if (c->scsi_cmd != NULL)
5668 scsi_print_command(c->scsi_cmd);
5669 scsi_print_command(scmd);
5670 }
5671
5672 hpsa_cmd_partial_init(h, idx, c);
5673 return c;
5674}
5675
5676static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
5677{
5678 /*
5679 * Release our reference to the block. We don't need to do anything
5680 * else to free it, because it is accessed by index. (There's no point
5681 * in checking the result of the decrement, since we cannot guarantee
5682 * that there isn't a concurrent abort which is also accessing it.)
5683 */
5684 (void)atomic_dec(&c->refcount);
5685}
5686
edd16368
SC		 5687/*
5688 * For operations that cannot sleep, a command block is allocated at init,
5689 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
5690 * which ones are free or in use. Lock must be held when calling this.
5691 * cmd_free() is the complement.
bf43caf3
RE		 5692 * This function never gives up and returns NULL. If it hangs,
5693 * another thread must call cmd_free() to free some tags.
edd16368 5694 */
281a7fd0 5695
edd16368
SC		 5696static struct CommandList *cmd_alloc(struct ctlr_info *h)
5697{
5698 struct CommandList *c;
360c73bd 5699 int refcount, i;
73153fe5 5700 int offset = 0;
4c413128 5701
33811026
RE		 5702 /*
5703 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 5704 * multiple threads could get in here, and one thread could
5705 * be scanning through the list of bits looking for a free
5706 * one, but the free ones are always behind him, and other
5707 * threads sneak in behind him and eat them before he can
5708 * get to them, so that while there is always a free one, a
5709 * very unlucky thread might be starved anyway, never able to
5710 * beat the other threads. In reality, this happens so
5711 * infrequently as to be indistinguishable from never.
73153fe5
WS		 5712 *
5713 * Note that we start allocating commands before the SCSI host structure
5714 * is initialized. Since the search starts at bit zero, this
5715 * all works, since we have at least one command structure available;
5716 * however, it means that the structures with the low indexes have to be
5717 * reserved for driver-initiated requests, while requests from the block
5718 * layer will use the higher indexes.
4c413128 5719 */
edd16368 5720
281a7fd0 5721 for (;;) {
73153fe5
WS		 5722 i = find_next_zero_bit(h->cmd_pool_bits,
5723 HPSA_NRESERVED_CMDS,
5724 offset);
5725 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
281a7fd0
WS		 5726 offset = 0;
5727 continue;
5728 }
5729 c = h->cmd_pool + i;
5730 refcount = atomic_inc_return(&c->refcount);
5731 if (unlikely(refcount > 1)) {
5732 cmd_free(h, c); /* already in use */
73153fe5 5733 offset = (i + 1) % HPSA_NRESERVED_CMDS;
281a7fd0
WS		 5734 continue;
5735 }
5736 set_bit(i & (BITS_PER_LONG - 1),
5737 h->cmd_pool_bits + (i / BITS_PER_LONG));
5738 break; /* it's ours now. */
5739 }
360c73bd 5740 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 5741 return c;
5742}
5743
73153fe5
WS		 5744/*
5745 * This is the complementary operation to cmd_alloc(). Note, however, in some
5746 * corner cases it may also be used to free blocks allocated by
5747 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
5748 * the clear-bit is harmless.
5749 */
edd16368
SC		 5750static void cmd_free(struct ctlr_info *h, struct CommandList *c)
5751{
281a7fd0
WS		 5752 if (atomic_dec_and_test(&c->refcount)) {
5753 int i;
edd16368 5754
281a7fd0
WS		 5755 i = c - h->cmd_pool;
5756 clear_bit(i & (BITS_PER_LONG - 1),
5757 h->cmd_pool_bits + (i / BITS_PER_LONG));
5758 }
edd16368
SC		 5759}
5760
edd16368
SC		 5761#ifdef CONFIG_COMPAT
5762
42a91641
DB		 5763static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
5764 void __user *arg)
edd16368
SC		 5765{
5766 IOCTL32_Command_struct __user *arg32 =
5767 (IOCTL32_Command_struct __user *) arg;
5768 IOCTL_Command_struct arg64;
5769 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5770 int err;
5771 u32 cp;
5772
938abd84 5773 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5774 err = 0;
5775 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5776 sizeof(arg64.LUN_info));
5777 err |= copy_from_user(&arg64.Request, &arg32->Request,
5778 sizeof(arg64.Request));
5779 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5780 sizeof(arg64.error_info));
5781 err |= get_user(arg64.buf_size, &arg32->buf_size);
5782 err |= get_user(cp, &arg32->buf);
5783 arg64.buf = compat_ptr(cp);
5784 err |= copy_to_user(p, &arg64, sizeof(arg64));
5785
5786 if (err)
5787 return -EFAULT;
5788
42a91641 5789 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 5790 if (err)
5791 return err;
5792 err |= copy_in_user(&arg32->error_info, &p->error_info,
5793 sizeof(arg32->error_info));
5794 if (err)
5795 return -EFAULT;
5796 return err;
5797}
5798
5799static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 5800 int cmd, void __user *arg)
edd16368
SC		 5801{
5802 BIG_IOCTL32_Command_struct __user *arg32 =
5803 (BIG_IOCTL32_Command_struct __user *) arg;
5804 BIG_IOCTL_Command_struct arg64;
5805 BIG_IOCTL_Command_struct __user *p =
5806 compat_alloc_user_space(sizeof(arg64));
5807 int err;
5808 u32 cp;
5809
938abd84 5810 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5811 err = 0;
5812 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5813 sizeof(arg64.LUN_info));
5814 err |= copy_from_user(&arg64.Request, &arg32->Request,
5815 sizeof(arg64.Request));
5816 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5817 sizeof(arg64.error_info));
5818 err |= get_user(arg64.buf_size, &arg32->buf_size);
5819 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5820 err |= get_user(cp, &arg32->buf);
5821 arg64.buf = compat_ptr(cp);
5822 err |= copy_to_user(p, &arg64, sizeof(arg64));
5823
5824 if (err)
5825 return -EFAULT;
5826
42a91641 5827 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 5828 if (err)
5829 return err;
5830 err |= copy_in_user(&arg32->error_info, &p->error_info,
5831 sizeof(arg32->error_info));
5832 if (err)
5833 return -EFAULT;
5834 return err;
5835}
71fe75a7 5836
42a91641 5837static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 5838{
5839 switch (cmd) {
5840 case CCISS_GETPCIINFO:
5841 case CCISS_GETINTINFO:
5842 case CCISS_SETINTINFO:
5843 case CCISS_GETNODENAME:
5844 case CCISS_SETNODENAME:
5845 case CCISS_GETHEARTBEAT:
5846 case CCISS_GETBUSTYPES:
5847 case CCISS_GETFIRMVER:
5848 case CCISS_GETDRIVVER:
5849 case CCISS_REVALIDVOLS:
5850 case CCISS_DEREGDISK:
5851 case CCISS_REGNEWDISK:
5852 case CCISS_REGNEWD:
5853 case CCISS_RESCANDISK:
5854 case CCISS_GETLUNINFO:
5855 return hpsa_ioctl(dev, cmd, arg);
5856
5857 case CCISS_PASSTHRU32:
5858 return hpsa_ioctl32_passthru(dev, cmd, arg);
5859 case CCISS_BIG_PASSTHRU32:
5860 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5861
5862 default:
5863 return -ENOIOCTLCMD;
5864 }
5865}
edd16368
SC		 5866#endif
5867
5868static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5869{
5870 struct hpsa_pci_info pciinfo;
5871
5872 if (!argp)
5873 return -EINVAL;
5874 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5875 pciinfo.bus = h->pdev->bus->number;
5876 pciinfo.dev_fn = h->pdev->devfn;
5877 pciinfo.board_id = h->board_id;
5878 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5879 return -EFAULT;
5880 return 0;
5881}
5882
5883static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
5884{
5885 DriverVer_type DriverVer;
5886 unsigned char vmaj, vmin, vsubmin;
5887 int rc;
5888
5889 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
5890 &vmaj, &vmin, &vsubmin);
5891 if (rc != 3) {
5892 dev_info(&h->pdev->dev, "driver version string '%s' "
5893 "unrecognized.", HPSA_DRIVER_VERSION);
5894 vmaj = 0;
5895 vmin = 0;
5896 vsubmin = 0;
5897 }
5898 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
5899 if (!argp)
5900 return -EINVAL;
5901 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
5902 return -EFAULT;
5903 return 0;
5904}
5905
5906static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5907{
5908 IOCTL_Command_struct iocommand;
5909 struct CommandList *c;
5910 char *buff = NULL;
50a0decf 5911 u64 temp64;
c1f63c8f 5912 int rc = 0;
edd16368
SC		 5913
5914 if (!argp)
5915 return -EINVAL;
5916 if (!capable(CAP_SYS_RAWIO))
5917 return -EPERM;
5918 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
5919 return -EFAULT;
5920 if ((iocommand.buf_size < 1) &&
5921 (iocommand.Request.Type.Direction != XFER_NONE)) {
5922 return -EINVAL;
5923 }
5924 if (iocommand.buf_size > 0) {
5925 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
5926 if (buff == NULL)
2dd02d74 5927 return -ENOMEM;
9233fb10 5928 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 5929 /* Copy the data into the buffer we created */
5930 if (copy_from_user(buff, iocommand.buf,
5931 iocommand.buf_size)) {
c1f63c8f
SC		 5932 rc = -EFAULT;
5933 goto out_kfree;
b03a7771
SC		 5934 }
5935 } else {
5936 memset(buff, 0, iocommand.buf_size);
edd16368 5937 }
b03a7771 5938 }
45fcb86e 5939 c = cmd_alloc(h);
bf43caf3 5940
edd16368
SC		 5941 /* Fill in the command type */
5942 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 5943 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 5944 /* Fill in Command Header */
5945 c->Header.ReplyQueue = 0; /* unused in simple mode */
5946 if (iocommand.buf_size > 0) { /* buffer to fill */
5947 c->Header.SGList = 1;
50a0decf 5948 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5949 } else { /* no buffers to fill */
5950 c->Header.SGList = 0;
50a0decf 5951 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 5952 }
5953 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5954
5955 /* Fill in Request block */
5956 memcpy(&c->Request, &iocommand.Request,
5957 sizeof(c->Request));
5958
5959 /* Fill in the scatter gather information */
5960 if (iocommand.buf_size > 0) {
50a0decf 5961 temp64 = pci_map_single(h->pdev, buff,
edd16368 5962 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5963 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
5964 c->SG[0].Addr = cpu_to_le64(0);
5965 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 5966 rc = -ENOMEM;
5967 goto out;
5968 }
50a0decf
SC		 5969 c->SG[0].Addr = cpu_to_le64(temp64);
5970 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
5971 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 5972 }
25163bd5 5973 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
c2dd32e0
SC		 5974 if (iocommand.buf_size > 0)
5975 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 5976 check_ioctl_unit_attention(h, c);
25163bd5
WS		 5977 if (rc) {
5978 rc = -EIO;
5979 goto out;
5980 }
edd16368
SC		 5981
5982 /* Copy the error information out */
5983 memcpy(&iocommand.error_info, c->err_info,
5984 sizeof(iocommand.error_info));
5985 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 5986 rc = -EFAULT;
5987 goto out;
edd16368 5988 }
9233fb10 5989 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 5990 iocommand.buf_size > 0) {
edd16368
SC		 5991 /* Copy the data out of the buffer we created */
5992 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 5993 rc = -EFAULT;
5994 goto out;
edd16368
SC		 5995 }
5996 }
c1f63c8f 5997out:
45fcb86e 5998 cmd_free(h, c);
c1f63c8f
SC		 5999out_kfree:
6000 kfree(buff);
6001 return rc;
edd16368
SC		 6002}
6003
6004static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6005{
6006 BIG_IOCTL_Command_struct *ioc;
6007 struct CommandList *c;
6008 unsigned char **buff = NULL;
6009 int *buff_size = NULL;
50a0decf 6010 u64 temp64;
edd16368
SC		 6011 BYTE sg_used = 0;
6012 int status = 0;
01a02ffc
SC		 6013 u32 left;
6014 u32 sz;
edd16368
SC		 6015 BYTE __user *data_ptr;
6016
6017 if (!argp)
6018 return -EINVAL;
6019 if (!capable(CAP_SYS_RAWIO))
6020 return -EPERM;
6021 ioc = (BIG_IOCTL_Command_struct *)
6022 kmalloc(sizeof(*ioc), GFP_KERNEL);
6023 if (!ioc) {
6024 status = -ENOMEM;
6025 goto cleanup1;
6026 }
6027 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
6028 status = -EFAULT;
6029 goto cleanup1;
6030 }
6031 if ((ioc->buf_size < 1) &&
6032 (ioc->Request.Type.Direction != XFER_NONE)) {
6033 status = -EINVAL;
6034 goto cleanup1;
6035 }
6036 /* Check kmalloc limits using all SGs */
6037 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
6038 status = -EINVAL;
6039 goto cleanup1;
6040 }
d66ae08b 6041 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 6042 status = -EINVAL;
6043 goto cleanup1;
6044 }
d66ae08b 6045 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 6046 if (!buff) {
6047 status = -ENOMEM;
6048 goto cleanup1;
6049 }
d66ae08b 6050 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 6051 if (!buff_size) {
6052 status = -ENOMEM;
6053 goto cleanup1;
6054 }
6055 left = ioc->buf_size;
6056 data_ptr = ioc->buf;
6057 while (left) {
6058 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6059 buff_size[sg_used] = sz;
6060 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6061 if (buff[sg_used] == NULL) {
6062 status = -ENOMEM;
6063 goto cleanup1;
6064 }
9233fb10 6065 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 6066 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 6067 status = -EFAULT;
edd16368
SC		 6068 goto cleanup1;
6069 }
6070 } else
6071 memset(buff[sg_used], 0, sz);
6072 left -= sz;
6073 data_ptr += sz;
6074 sg_used++;
6075 }
45fcb86e 6076 c = cmd_alloc(h);
bf43caf3 6077
edd16368 6078 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6079 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368 6080 c->Header.ReplyQueue = 0;
50a0decf
SC		 6081 c->Header.SGList = (u8) sg_used;
6082 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 6083 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6084 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6085 if (ioc->buf_size > 0) {
6086 int i;
6087 for (i = 0; i < sg_used; i++) {
50a0decf 6088 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 6089 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6090 if (dma_mapping_error(&h->pdev->dev,
6091 (dma_addr_t) temp64)) {
6092 c->SG[i].Addr = cpu_to_le64(0);
6093 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 6094 hpsa_pci_unmap(h->pdev, c, i,
6095 PCI_DMA_BIDIRECTIONAL);
6096 status = -ENOMEM;
e2d4a1f6 6097 goto cleanup0;
bcc48ffa 6098 }
50a0decf
SC		 6099 c->SG[i].Addr = cpu_to_le64(temp64);
6100 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6101 c->SG[i].Ext = cpu_to_le32(0);
edd16368 6102 }
50a0decf 6103 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 6104 }
25163bd5 6105 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
b03a7771
SC		 6106 if (sg_used)
6107 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 6108 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6109 if (status) {
6110 status = -EIO;
6111 goto cleanup0;
6112 }
6113
edd16368
SC		 6114 /* Copy the error information out */
6115 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6116 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 6117 status = -EFAULT;
e2d4a1f6 6118 goto cleanup0;
edd16368 6119 }
9233fb10 6120 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 6121 int i;
6122
edd16368
SC		 6123 /* Copy the data out of the buffer we created */
6124 BYTE __user *ptr = ioc->buf;
6125 for (i = 0; i < sg_used; i++) {
6126 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 6127 status = -EFAULT;
e2d4a1f6 6128 goto cleanup0;
edd16368
SC		 6129 }
6130 ptr += buff_size[i];
6131 }
6132 }
edd16368 6133 status = 0;
e2d4a1f6 6134cleanup0:
45fcb86e 6135 cmd_free(h, c);
edd16368
SC		 6136cleanup1:
6137 if (buff) {
2b08b3e9
DB		 6138 int i;
6139
edd16368
SC		 6140 for (i = 0; i < sg_used; i++)
6141 kfree(buff[i]);
6142 kfree(buff);
6143 }
6144 kfree(buff_size);
6145 kfree(ioc);
6146 return status;
6147}
6148
6149static void check_ioctl_unit_attention(struct ctlr_info *h,
6150 struct CommandList *c)
6151{
6152 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6153 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6154 (void) check_for_unit_attention(h, c);
6155}
0390f0c0 6156
edd16368
SC		 6157/*
6158 * ioctl
6159 */
42a91641 6160static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 6161{
6162 struct ctlr_info *h;
6163 void __user *argp = (void __user *)arg;
0390f0c0 6164 int rc;
edd16368
SC		 6165
6166 h = sdev_to_hba(dev);
6167
6168 switch (cmd) {
6169 case CCISS_DEREGDISK:
6170 case CCISS_REGNEWDISK:
6171 case CCISS_REGNEWD:
a08a8471 6172 hpsa_scan_start(h->scsi_host);
edd16368
SC		 6173 return 0;
6174 case CCISS_GETPCIINFO:
6175 return hpsa_getpciinfo_ioctl(h, argp);
6176 case CCISS_GETDRIVVER:
6177 return hpsa_getdrivver_ioctl(h, argp);
6178 case CCISS_PASSTHRU:
34f0c627 6179 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6180 return -EAGAIN;
6181 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 6182 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6183 return rc;
edd16368 6184 case CCISS_BIG_PASSTHRU:
34f0c627 6185 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6186 return -EAGAIN;
6187 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 6188 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6189 return rc;
edd16368
SC		 6190 default:
6191 return -ENOTTY;
6192 }
6193}
6194
bf43caf3 6195static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6f039790 6196 u8 reset_type)
64670ac8
SC		 6197{
6198 struct CommandList *c;
6199
6200 c = cmd_alloc(h);
bf43caf3 6201
a2dac136
SC		 6202 /* fill_cmd can't fail here, no data buffer to map */
6203 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 6204 RAID_CTLR_LUNID, TYPE_MSG);
6205 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6206 c->waiting = NULL;
6207 enqueue_cmd_and_start_io(h, c);
6208 /* Don't wait for completion, the reset won't complete. Don't free
6209 * the command either. This is the last command we will send before
6210 * re-initializing everything, so it doesn't matter and won't leak.
6211 */
bf43caf3 6212 return;
64670ac8
SC		 6213}
6214
a2dac136 6215static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 6216 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 6217 int cmd_type)
6218{
6219 int pci_dir = XFER_NONE;
9b5c48c2 6220 u64 tag; /* for commands to be aborted */
edd16368
SC		 6221
6222 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6223 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6224 c->Header.ReplyQueue = 0;
6225 if (buff != NULL && size > 0) {
6226 c->Header.SGList = 1;
50a0decf 6227 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6228 } else {
6229 c->Header.SGList = 0;
50a0decf 6230 c->Header.SGTotal = cpu_to_le16(0);
edd16368 6231 }
edd16368
SC		 6232 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6233
edd16368
SC		 6234 if (cmd_type == TYPE_CMD) {
6235 switch (cmd) {
6236 case HPSA_INQUIRY:
6237 /* are we trying to read a vital product page */
b7bb24eb 6238 if (page_code & VPD_PAGE) {
edd16368 6239 c->Request.CDB[1] = 0x01;
b7bb24eb 6240 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 6241 }
6242 c->Request.CDBLen = 6;
a505b86f
SC		 6243 c->Request.type_attr_dir =
6244 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6245 c->Request.Timeout = 0;
6246 c->Request.CDB[0] = HPSA_INQUIRY;
6247 c->Request.CDB[4] = size & 0xFF;
6248 break;
6249 case HPSA_REPORT_LOG:
6250 case HPSA_REPORT_PHYS:
6251 /* Talking to controller so It's a physical command
6252 mode = 00 target = 0. Nothing to write.
6253 */
6254 c->Request.CDBLen = 12;
a505b86f
SC		 6255 c->Request.type_attr_dir =
6256 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6257 c->Request.Timeout = 0;
6258 c->Request.CDB[0] = cmd;
6259 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6260 c->Request.CDB[7] = (size >> 16) & 0xFF;
6261 c->Request.CDB[8] = (size >> 8) & 0xFF;
6262 c->Request.CDB[9] = size & 0xFF;
6263 break;
edd16368
SC		 6264 case HPSA_CACHE_FLUSH:
6265 c->Request.CDBLen = 12;
a505b86f
SC		 6266 c->Request.type_attr_dir =
6267 TYPE_ATTR_DIR(cmd_type,
6268 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 6269 c->Request.Timeout = 0;
6270 c->Request.CDB[0] = BMIC_WRITE;
6271 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 6272 c->Request.CDB[7] = (size >> 8) & 0xFF;
6273 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 6274 break;
6275 case TEST_UNIT_READY:
6276 c->Request.CDBLen = 6;
a505b86f
SC		 6277 c->Request.type_attr_dir =
6278 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 6279 c->Request.Timeout = 0;
6280 break;
283b4a9b
SC		 6281 case HPSA_GET_RAID_MAP:
6282 c->Request.CDBLen = 12;
a505b86f
SC		 6283 c->Request.type_attr_dir =
6284 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 6285 c->Request.Timeout = 0;
6286 c->Request.CDB[0] = HPSA_CISS_READ;
6287 c->Request.CDB[1] = cmd;
6288 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6289 c->Request.CDB[7] = (size >> 16) & 0xFF;
6290 c->Request.CDB[8] = (size >> 8) & 0xFF;
6291 c->Request.CDB[9] = size & 0xFF;
6292 break;
316b221a
SC		 6293 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6294 c->Request.CDBLen = 10;
a505b86f
SC		 6295 c->Request.type_attr_dir =
6296 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 6297 c->Request.Timeout = 0;
6298 c->Request.CDB[0] = BMIC_READ;
6299 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6300 c->Request.CDB[7] = (size >> 16) & 0xFF;
6301 c->Request.CDB[8] = (size >> 8) & 0xFF;
6302 break;
03383736
DB		 6303 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6304 c->Request.CDBLen = 10;
6305 c->Request.type_attr_dir =
6306 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6307 c->Request.Timeout = 0;
6308 c->Request.CDB[0] = BMIC_READ;
6309 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6310 c->Request.CDB[7] = (size >> 16) & 0xFF;
6311 c->Request.CDB[8] = (size >> 8) & 0XFF;
6312 break;
edd16368
SC		 6313 default:
6314 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6315 BUG();
a2dac136 6316 return -1;
edd16368
SC		 6317 }
6318 } else if (cmd_type == TYPE_MSG) {
6319 switch (cmd) {
6320
6321 case HPSA_DEVICE_RESET_MSG:
6322 c->Request.CDBLen = 16;
a505b86f
SC		 6323 c->Request.type_attr_dir =
6324 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 6325 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 6326 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6327 c->Request.CDB[0] = cmd;
21e89afd 6328 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 6329 /* If bytes 4-7 are zero, it means reset the */
6330 /* LunID device */
6331 c->Request.CDB[4] = 0x00;
6332 c->Request.CDB[5] = 0x00;
6333 c->Request.CDB[6] = 0x00;
6334 c->Request.CDB[7] = 0x00;
75167d2c
SC		 6335 break;
6336 case HPSA_ABORT_MSG:
9b5c48c2 6337 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 6338 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 6339 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
6340 tag, c->Header.tag);
75167d2c 6341 c->Request.CDBLen = 16;
a505b86f
SC		 6342 c->Request.type_attr_dir =
6343 TYPE_ATTR_DIR(cmd_type,
6344 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 6345 c->Request.Timeout = 0; /* Don't time out */
6346 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
6347 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
6348 c->Request.CDB[2] = 0x00; /* reserved */
6349 c->Request.CDB[3] = 0x00; /* reserved */
6350 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 6351 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 6352 c->Request.CDB[12] = 0x00; /* reserved */
6353 c->Request.CDB[13] = 0x00; /* reserved */
6354 c->Request.CDB[14] = 0x00; /* reserved */
6355 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 6356 break;
edd16368
SC		 6357 default:
6358 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6359 cmd);
6360 BUG();
6361 }
6362 } else {
6363 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6364 BUG();
6365 }
6366
a505b86f 6367 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 6368 case XFER_READ:
6369 pci_dir = PCI_DMA_FROMDEVICE;
6370 break;
6371 case XFER_WRITE:
6372 pci_dir = PCI_DMA_TODEVICE;
6373 break;
6374 case XFER_NONE:
6375 pci_dir = PCI_DMA_NONE;
6376 break;
6377 default:
6378 pci_dir = PCI_DMA_BIDIRECTIONAL;
6379 }
a2dac136
SC		 6380 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
6381 return -1;
6382 return 0;
edd16368
SC		 6383}
6384
6385/*
6386 * Map (physical) PCI mem into (virtual) kernel space
6387 */
6388static void __iomem *remap_pci_mem(ulong base, ulong size)
6389{
6390 ulong page_base = ((ulong) base) & PAGE_MASK;
6391 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 6392 void __iomem *page_remapped = ioremap_nocache(page_base,
6393 page_offs + size);
edd16368
SC		 6394
6395 return page_remapped ? (page_remapped + page_offs) : NULL;
6396}
6397
254f796b 6398static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 6399{
254f796b 6400 return h->access.command_completed(h, q);
edd16368
SC		 6401}
6402
900c5440 6403static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 6404{
6405 return h->access.intr_pending(h);
6406}
6407
6408static inline long interrupt_not_for_us(struct ctlr_info *h)
6409{
10f66018
SC		 6410 return (h->access.intr_pending(h) == 0) ||
6411 (h->interrupts_enabled == 0);
edd16368
SC		 6412}
6413
01a02ffc
SC		 6414static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6415 u32 raw_tag)
edd16368
SC		 6416{
6417 if (unlikely(tag_index >= h->nr_cmds)) {
6418 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6419 return 1;
6420 }
6421 return 0;
6422}
6423
5a3d16f5 6424static inline void finish_cmd(struct CommandList *c)
edd16368 6425{
e85c5974 6426 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 6427 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6428 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 6429 complete_scsi_command(c);
8be986cc 6430 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
edd16368 6431 complete(c->waiting);
a104c99f
SC		 6432}
6433
a9a3a273
SC		 6434
6435static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 6436{
a9a3a273
SC		 6437#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
6438#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 6439 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 6440 return tag & ~HPSA_SIMPLE_ERROR_BITS;
6441 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 6442}
6443
303932fd 6444/* process completion of an indexed ("direct lookup") command */
1d94f94d 6445static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 6446 u32 raw_tag)
6447{
6448 u32 tag_index;
6449 struct CommandList *c;
6450
f2405db8 6451 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 6452 if (!bad_tag(h, tag_index, raw_tag)) {
6453 c = h->cmd_pool + tag_index;
6454 finish_cmd(c);
6455 }
303932fd
DB		 6456}
6457
64670ac8
SC		 6458/* Some controllers, like p400, will give us one interrupt
6459 * after a soft reset, even if we turned interrupts off.
6460 * Only need to check for this in the hpsa_xxx_discard_completions
6461 * functions.
6462 */
6463static int ignore_bogus_interrupt(struct ctlr_info *h)
6464{
6465 if (likely(!reset_devices))
6466 return 0;
6467
6468 if (likely(h->interrupts_enabled))
6469 return 0;
6470
6471 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
6472 "(known firmware bug.) Ignoring.\n");
6473
6474 return 1;
6475}
6476
254f796b
MG		 6477/*
6478 * Convert &h->q[x] (passed to interrupt handlers) back to h.
6479 * Relies on (h-q[x] == x) being true for x such that
6480 * 0 <= x < MAX_REPLY_QUEUES.
6481 */
6482static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 6483{
254f796b
MG		 6484 return container_of((queue - *queue), struct ctlr_info, q[0]);
6485}
6486
6487static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6488{
6489 struct ctlr_info *h = queue_to_hba(queue);
6490 u8 q = *(u8 *) queue;
64670ac8
SC		 6491 u32 raw_tag;
6492
6493 if (ignore_bogus_interrupt(h))
6494 return IRQ_NONE;
6495
6496 if (interrupt_not_for_us(h))
6497 return IRQ_NONE;
a0c12413 6498 h->last_intr_timestamp = get_jiffies_64();
64670ac8 6499 while (interrupt_pending(h)) {
254f796b 6500 raw_tag = get_next_completion(h, q);
64670ac8 6501 while (raw_tag != FIFO_EMPTY)
254f796b 6502 raw_tag = next_command(h, q);
64670ac8 6503 }
64670ac8
SC		 6504 return IRQ_HANDLED;
6505}
6506
254f796b 6507static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 6508{
254f796b 6509 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 6510 u32 raw_tag;
254f796b 6511 u8 q = *(u8 *) queue;
64670ac8
SC		 6512
6513 if (ignore_bogus_interrupt(h))
6514 return IRQ_NONE;
6515
a0c12413 6516 h->last_intr_timestamp = get_jiffies_64();
254f796b 6517 raw_tag = get_next_completion(h, q);
64670ac8 6518 while (raw_tag != FIFO_EMPTY)
254f796b 6519 raw_tag = next_command(h, q);
64670ac8
SC		 6520 return IRQ_HANDLED;
6521}
6522
254f796b 6523static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 6524{
254f796b 6525 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 6526 u32 raw_tag;
254f796b 6527 u8 q = *(u8 *) queue;
edd16368
SC		 6528
6529 if (interrupt_not_for_us(h))
6530 return IRQ_NONE;
a0c12413 6531 h->last_intr_timestamp = get_jiffies_64();
10f66018 6532 while (interrupt_pending(h)) {
254f796b 6533 raw_tag = get_next_completion(h, q);
10f66018 6534 while (raw_tag != FIFO_EMPTY) {
f2405db8 6535 process_indexed_cmd(h, raw_tag);
254f796b 6536 raw_tag = next_command(h, q);
10f66018
SC		 6537 }
6538 }
10f66018
SC		 6539 return IRQ_HANDLED;
6540}
6541
254f796b 6542static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 6543{
254f796b 6544 struct ctlr_info *h = queue_to_hba(queue);
10f66018 6545 u32 raw_tag;
254f796b 6546 u8 q = *(u8 *) queue;
10f66018 6547
a0c12413 6548 h->last_intr_timestamp = get_jiffies_64();
254f796b 6549 raw_tag = get_next_completion(h, q);
303932fd 6550 while (raw_tag != FIFO_EMPTY) {
f2405db8 6551 process_indexed_cmd(h, raw_tag);
254f796b 6552 raw_tag = next_command(h, q);
edd16368 6553 }
edd16368
SC		 6554 return IRQ_HANDLED;
6555}
6556
a9a3a273
SC		 6557/* Send a message CDB to the firmware. Careful, this only works
6558 * in simple mode, not performant mode due to the tag lookup.
6559 * We only ever use this immediately after a controller reset.
6560 */
6f039790
GKH		 6561static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
6562 unsigned char type)
edd16368
SC		 6563{
6564 struct Command {
6565 struct CommandListHeader CommandHeader;
6566 struct RequestBlock Request;
6567 struct ErrDescriptor ErrorDescriptor;
6568 };
6569 struct Command *cmd;
6570 static const size_t cmd_sz = sizeof(*cmd) +
6571 sizeof(cmd->ErrorDescriptor);
6572 dma_addr_t paddr64;
2b08b3e9
DB		 6573 __le32 paddr32;
6574 u32 tag;
edd16368
SC		 6575 void __iomem *vaddr;
6576 int i, err;
6577
6578 vaddr = pci_ioremap_bar(pdev, 0);
6579 if (vaddr == NULL)
6580 return -ENOMEM;
6581
6582 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
6583 * CCISS commands, so they must be allocated from the lower 4GiB of
6584 * memory.
6585 */
6586 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6587 if (err) {
6588 iounmap(vaddr);
1eaec8f3 6589 return err;
edd16368
SC		 6590 }
6591
6592 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
6593 if (cmd == NULL) {
6594 iounmap(vaddr);
6595 return -ENOMEM;
6596 }
6597
6598 /* This must fit, because of the 32-bit consistent DMA mask. Also,
6599 * although there's no guarantee, we assume that the address is at
6600 * least 4-byte aligned (most likely, it's page-aligned).
6601 */
2b08b3e9 6602 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 6603
6604 cmd->CommandHeader.ReplyQueue = 0;
6605 cmd->CommandHeader.SGList = 0;
50a0decf 6606 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 6607 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 6608 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
6609
6610 cmd->Request.CDBLen = 16;
a505b86f
SC		 6611 cmd->Request.type_attr_dir =
6612 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 6613 cmd->Request.Timeout = 0; /* Don't time out */
6614 cmd->Request.CDB[0] = opcode;
6615 cmd->Request.CDB[1] = type;
6616 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 6617 cmd->ErrorDescriptor.Addr =
2b08b3e9 6618 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 6619 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 6620
2b08b3e9 6621 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 6622
6623 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
6624 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 6625 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 6626 break;
6627 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
6628 }
6629
6630 iounmap(vaddr);
6631
6632 /* we leak the DMA buffer here ... no choice since the controller could
6633 * still complete the command.
6634 */
6635 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
6636 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
6637 opcode, type);
6638 return -ETIMEDOUT;
6639 }
6640
6641 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
6642
6643 if (tag & HPSA_ERROR_BIT) {
6644 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
6645 opcode, type);
6646 return -EIO;
6647 }
6648
6649 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
6650 opcode, type);
6651 return 0;
6652}
6653
edd16368
SC		 6654#define hpsa_noop(p) hpsa_message(p, 3, 0)
6655
1df8552a 6656static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 6657 void __iomem *vaddr, u32 use_doorbell)
1df8552a 6658{
1df8552a
SC		 6659
6660 if (use_doorbell) {
6661 /* For everything after the P600, the PCI power state method
6662 * of resetting the controller doesn't work, so we have this
6663 * other way using the doorbell register.
6664 */
6665 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 6666 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 6667
00701a96 6668 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 6669 * doorbell reset and before any attempt to talk to the board
6670 * at all to ensure that this actually works and doesn't fall
6671 * over in some weird corner cases.
6672 */
00701a96 6673 msleep(10000);
1df8552a
SC		 6674 } else { /* Try to do it the PCI power state way */
6675
6676 /* Quoting from the Open CISS Specification: "The Power
6677 * Management Control/Status Register (CSR) controls the power
6678 * state of the device. The normal operating state is D0,
6679 * CSR=00h. The software off state is D3, CSR=03h. To reset
6680 * the controller, place the interface device in D3 then to D0,
6681 * this causes a secondary PCI reset which will reset the
6682 * controller." */
2662cab8
DB		 6683
6684 int rc = 0;
6685
1df8552a 6686 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 6687
1df8552a 6688 /* enter the D3hot power management state */
2662cab8
DB		 6689 rc = pci_set_power_state(pdev, PCI_D3hot);
6690 if (rc)
6691 return rc;
1df8552a
SC		 6692
6693 msleep(500);
6694
6695 /* enter the D0 power management state */
2662cab8
DB		 6696 rc = pci_set_power_state(pdev, PCI_D0);
6697 if (rc)
6698 return rc;
c4853efe
MM		 6699
6700 /*
6701 * The P600 requires a small delay when changing states.
6702 * Otherwise we may think the board did not reset and we bail.
6703 * This for kdump only and is particular to the P600.
6704 */
6705 msleep(500);
1df8552a
SC		 6706 }
6707 return 0;
6708}
6709
6f039790 6710static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 6711{
6712 memset(driver_version, 0, len);
f79cfec6 6713 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 6714}
6715
6f039790 6716static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6717{
6718 char *driver_version;
6719 int i, size = sizeof(cfgtable->driver_version);
6720
6721 driver_version = kmalloc(size, GFP_KERNEL);
6722 if (!driver_version)
6723 return -ENOMEM;
6724
6725 init_driver_version(driver_version, size);
6726 for (i = 0; i < size; i++)
6727 writeb(driver_version[i], &cfgtable->driver_version[i]);
6728 kfree(driver_version);
6729 return 0;
6730}
6731
6f039790
GKH		 6732static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
6733 unsigned char *driver_ver)
580ada3c
SC		 6734{
6735 int i;
6736
6737 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
6738 driver_ver[i] = readb(&cfgtable->driver_version[i]);
6739}
6740
6f039790 6741static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6742{
6743
6744 char *driver_ver, *old_driver_ver;
6745 int rc, size = sizeof(cfgtable->driver_version);
6746
6747 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
6748 if (!old_driver_ver)
6749 return -ENOMEM;
6750 driver_ver = old_driver_ver + size;
6751
6752 /* After a reset, the 32 bytes of "driver version" in the cfgtable
6753 * should have been changed, otherwise we know the reset failed.
6754 */
6755 init_driver_version(old_driver_ver, size);
6756 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
6757 rc = !memcmp(driver_ver, old_driver_ver, size);
6758 kfree(old_driver_ver);
6759 return rc;
6760}
edd16368 6761/* This does a hard reset of the controller using PCI power management
1df8552a 6762 * states or the using the doorbell register.
edd16368 6763 */
6b6c1cd7 6764static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 6765{
1df8552a
SC		 6766 u64 cfg_offset;
6767 u32 cfg_base_addr;
6768 u64 cfg_base_addr_index;
6769 void __iomem *vaddr;
6770 unsigned long paddr;
580ada3c 6771 u32 misc_fw_support;
270d05de 6772 int rc;
1df8552a 6773 struct CfgTable __iomem *cfgtable;
cf0b08d0 6774 u32 use_doorbell;
270d05de 6775 u16 command_register;
edd16368 6776
1df8552a
SC		 6777 /* For controllers as old as the P600, this is very nearly
6778 * the same thing as
edd16368
SC		 6779 *
6780 * pci_save_state(pci_dev);
6781 * pci_set_power_state(pci_dev, PCI_D3hot);
6782 * pci_set_power_state(pci_dev, PCI_D0);
6783 * pci_restore_state(pci_dev);
6784 *
1df8552a
SC		 6785 * For controllers newer than the P600, the pci power state
6786 * method of resetting doesn't work so we have another way
6787 * using the doorbell register.
edd16368 6788 */
18867659 6789
60f923b9
RE		 6790 if (!ctlr_is_resettable(board_id)) {
6791 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 6792 return -ENODEV;
6793 }
46380786
SC		 6794
6795 /* if controller is soft- but not hard resettable... */
6796 if (!ctlr_is_hard_resettable(board_id))
6797 return -ENOTSUPP; /* try soft reset later. */
18867659 6798
270d05de
SC		 6799 /* Save the PCI command register */
6800 pci_read_config_word(pdev, 4, &command_register);
270d05de 6801 pci_save_state(pdev);
edd16368 6802
1df8552a
SC		 6803 /* find the first memory BAR, so we can find the cfg table */
6804 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6805 if (rc)
6806 return rc;
6807 vaddr = remap_pci_mem(paddr, 0x250);
6808 if (!vaddr)
6809 return -ENOMEM;
edd16368 6810
1df8552a
SC		 6811 /* find cfgtable in order to check if reset via doorbell is supported */
6812 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6813 &cfg_base_addr_index, &cfg_offset);
6814 if (rc)
6815 goto unmap_vaddr;
6816 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6817 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6818 if (!cfgtable) {
6819 rc = -ENOMEM;
6820 goto unmap_vaddr;
6821 }
580ada3c
SC		 6822 rc = write_driver_ver_to_cfgtable(cfgtable);
6823 if (rc)
03741d95 6824 goto unmap_cfgtable;
edd16368 6825
cf0b08d0
SC		 6826 /* If reset via doorbell register is supported, use that.
6827 * There are two such methods. Favor the newest method.
6828 */
1df8552a 6829 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6830 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6831 if (use_doorbell) {
6832 use_doorbell = DOORBELL_CTLR_RESET2;
6833 } else {
6834 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6835 if (use_doorbell) {
050f7147
SC		 6836 dev_warn(&pdev->dev,
6837 "Soft reset not supported. Firmware update is required.\n");
64670ac8 6838 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6839 goto unmap_cfgtable;
6840 }
6841 }
edd16368 6842
1df8552a
SC		 6843 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6844 if (rc)
6845 goto unmap_cfgtable;
edd16368 6846
270d05de 6847 pci_restore_state(pdev);
270d05de 6848 pci_write_config_word(pdev, 4, command_register);
edd16368 6849
1df8552a
SC		 6850 /* Some devices (notably the HP Smart Array 5i Controller)
6851 need a little pause here */
6852 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6853
fe5389c8
SC		 6854 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6855 if (rc) {
6856 dev_warn(&pdev->dev,
050f7147 6857 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 6858 goto unmap_cfgtable;
6859 }
fe5389c8 6860
580ada3c
SC		 6861 rc = controller_reset_failed(vaddr);
6862 if (rc < 0)
6863 goto unmap_cfgtable;
6864 if (rc) {
64670ac8
SC		 6865 dev_warn(&pdev->dev, "Unable to successfully reset "
6866 "controller. Will try soft reset.\n");
6867 rc = -ENOTSUPP;
580ada3c 6868 } else {
64670ac8 6869 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6870 }
6871
6872unmap_cfgtable:
6873 iounmap(cfgtable);
6874
6875unmap_vaddr:
6876 iounmap(vaddr);
6877 return rc;
edd16368
SC		 6878}
6879
6880/*
6881 * We cannot read the structure directly, for portability we must use
6882 * the io functions.
6883 * This is for debug only.
6884 */
42a91641 6885static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 6886{
58f8665c 6887#ifdef HPSA_DEBUG
edd16368
SC		 6888 int i;
6889 char temp_name[17];
6890
6891 dev_info(dev, "Controller Configuration information\n");
6892 dev_info(dev, "------------------------------------\n");
6893 for (i = 0; i < 4; i++)
6894 temp_name[i] = readb(&(tb->Signature[i]));
6895 temp_name[4] = '\0';
6896 dev_info(dev, " Signature = %s\n", temp_name);
6897 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6898 dev_info(dev, " Transport methods supported = 0x%x\n",
6899 readl(&(tb->TransportSupport)));
6900 dev_info(dev, " Transport methods active = 0x%x\n",
6901 readl(&(tb->TransportActive)));
6902 dev_info(dev, " Requested transport Method = 0x%x\n",
6903 readl(&(tb->HostWrite.TransportRequest)));
6904 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6905 readl(&(tb->HostWrite.CoalIntDelay)));
6906 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6907 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 6908 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 6909 readl(&(tb->CmdsOutMax)));
6910 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6911 for (i = 0; i < 16; i++)
6912 temp_name[i] = readb(&(tb->ServerName[i]));
6913 temp_name[16] = '\0';
6914 dev_info(dev, " Server Name = %s\n", temp_name);
6915 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6916 readl(&(tb->HeartBeat)));
edd16368 6917#endif /* HPSA_DEBUG */
58f8665c 6918}
edd16368
SC		 6919
6920static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6921{
6922 int i, offset, mem_type, bar_type;
6923
6924 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6925 return 0;
6926 offset = 0;
6927 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6928 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6929 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6930 offset += 4;
6931 else {
6932 mem_type = pci_resource_flags(pdev, i) &
6933 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6934 switch (mem_type) {
6935 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6936 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6937 offset += 4; /* 32 bit */
6938 break;
6939 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6940 offset += 8;
6941 break;
6942 default: /* reserved in PCI 2.2 */
6943 dev_warn(&pdev->dev,
6944 "base address is invalid\n");
6945 return -1;
6946 break;
6947 }
6948 }
6949 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6950 return i + 1;
6951 }
6952 return -1;
6953}
6954
cc64c817
RE		 6955static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
6956{
6957 if (h->msix_vector) {
6958 if (h->pdev->msix_enabled)
6959 pci_disable_msix(h->pdev);
105a3dbc 6960 h->msix_vector = 0;
cc64c817
RE		 6961 } else if (h->msi_vector) {
6962 if (h->pdev->msi_enabled)
6963 pci_disable_msi(h->pdev);
105a3dbc 6964 h->msi_vector = 0;
cc64c817
RE		 6965 }
6966}
6967
edd16368 6968/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 6969 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 6970 */
6f039790 6971static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6972{
6973#ifdef CONFIG_PCI_MSI
254f796b
MG		 6974 int err, i;
6975 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6976
6977 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6978 hpsa_msix_entries[i].vector = 0;
6979 hpsa_msix_entries[i].entry = i;
6980 }
edd16368
SC		 6981
6982 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6983 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6984 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6985 goto default_int_mode;
55c06c71 6986 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 6987 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 6988 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 6989 if (h->msix_vector > num_online_cpus())
6990 h->msix_vector = num_online_cpus();
18fce3c4
AG		 6991 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
6992 1, h->msix_vector);
6993 if (err < 0) {
6994 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
6995 h->msix_vector = 0;
6996 goto single_msi_mode;
6997 } else if (err < h->msix_vector) {
55c06c71 6998 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 6999 "available\n", err);
edd16368 7000 }
18fce3c4
AG		 7001 h->msix_vector = err;
7002 for (i = 0; i < h->msix_vector; i++)
7003 h->intr[i] = hpsa_msix_entries[i].vector;
7004 return;
edd16368 7005 }
18fce3c4 7006single_msi_mode:
55c06c71 7007 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 7008 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 7009 if (!pci_enable_msi(h->pdev))
edd16368
SC		 7010 h->msi_vector = 1;
7011 else
55c06c71 7012 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 7013 }
7014default_int_mode:
7015#endif /* CONFIG_PCI_MSI */
7016 /* if we get here we're going to use the default interrupt mode */
a9a3a273 7017 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 7018}
7019
6f039790 7020static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 7021{
7022 int i;
7023 u32 subsystem_vendor_id, subsystem_device_id;
7024
7025 subsystem_vendor_id = pdev->subsystem_vendor;
7026 subsystem_device_id = pdev->subsystem_device;
7027 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
7028 subsystem_vendor_id;
7029
7030 for (i = 0; i < ARRAY_SIZE(products); i++)
7031 if (*board_id == products[i].board_id)
7032 return i;
7033
6798cc0a
SC		 7034 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
7035 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
7036 !hpsa_allow_any) {
e5c880d1
SC		 7037 dev_warn(&pdev->dev, "unrecognized board ID: "
7038 "0x%08x, ignoring.\n", *board_id);
7039 return -ENODEV;
7040 }
7041 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
7042}
7043
6f039790
GKH		 7044static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
7045 unsigned long *memory_bar)
3a7774ce
SC		 7046{
7047 int i;
7048
7049 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 7050 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 7051 /* addressing mode bits already removed */
12d2cd47
SC		 7052 *memory_bar = pci_resource_start(pdev, i);
7053 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 7054 *memory_bar);
7055 return 0;
7056 }
12d2cd47 7057 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 7058 return -ENODEV;
7059}
7060
6f039790
GKH		 7061static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7062 int wait_for_ready)
2c4c8c8b 7063{
fe5389c8 7064 int i, iterations;
2c4c8c8b 7065 u32 scratchpad;
fe5389c8
SC		 7066 if (wait_for_ready)
7067 iterations = HPSA_BOARD_READY_ITERATIONS;
7068 else
7069 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 7070
fe5389c8
SC		 7071 for (i = 0; i < iterations; i++) {
7072 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7073 if (wait_for_ready) {
7074 if (scratchpad == HPSA_FIRMWARE_READY)
7075 return 0;
7076 } else {
7077 if (scratchpad != HPSA_FIRMWARE_READY)
7078 return 0;
7079 }
2c4c8c8b
SC		 7080 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7081 }
fe5389c8 7082 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 7083 return -ENODEV;
7084}
7085
6f039790
GKH		 7086static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7087 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7088 u64 *cfg_offset)
a51fd47f
SC		 7089{
7090 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7091 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7092 *cfg_base_addr &= (u32) 0x0000ffff;
7093 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7094 if (*cfg_base_addr_index == -1) {
7095 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7096 return -ENODEV;
7097 }
7098 return 0;
7099}
7100
195f2c65
RE		 7101static void hpsa_free_cfgtables(struct ctlr_info *h)
7102{
105a3dbc 7103 if (h->transtable) {
195f2c65 7104 iounmap(h->transtable);
105a3dbc
RE		 7105 h->transtable = NULL;
7106 }
7107 if (h->cfgtable) {
195f2c65 7108 iounmap(h->cfgtable);
105a3dbc
RE		 7109 h->cfgtable = NULL;
7110 }
195f2c65
RE		 7111}
7112
7113/* Find and map CISS config table and transfer table
7114+ * several items must be unmapped (freed) later
7115+ * */
6f039790 7116static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 7117{
01a02ffc
SC		 7118 u64 cfg_offset;
7119 u32 cfg_base_addr;
7120 u64 cfg_base_addr_index;
303932fd 7121 u32 trans_offset;
a51fd47f 7122 int rc;
77c4495c 7123
a51fd47f
SC		 7124 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7125 &cfg_base_addr_index, &cfg_offset);
7126 if (rc)
7127 return rc;
77c4495c 7128 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 7129 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 7130 if (!h->cfgtable) {
7131 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 7132 return -ENOMEM;
cd3c81c4 7133 }
580ada3c
SC		 7134 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7135 if (rc)
7136 return rc;
77c4495c 7137 /* Find performant mode table. */
a51fd47f 7138 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 7139 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7140 cfg_base_addr_index)+cfg_offset+trans_offset,
7141 sizeof(*h->transtable));
195f2c65
RE		 7142 if (!h->transtable) {
7143 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7144 hpsa_free_cfgtables(h);
77c4495c 7145 return -ENOMEM;
195f2c65 7146 }
77c4495c
SC		 7147 return 0;
7148}
7149
6f039790 7150static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 7151{
41ce4c35
SC		 7152#define MIN_MAX_COMMANDS 16
7153 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7154
7155 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 7156
7157 /* Limit commands in memory limited kdump scenario. */
7158 if (reset_devices && h->max_commands > 32)
7159 h->max_commands = 32;
7160
41ce4c35
SC		 7161 if (h->max_commands < MIN_MAX_COMMANDS) {
7162 dev_warn(&h->pdev->dev,
7163 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7164 h->max_commands,
7165 MIN_MAX_COMMANDS);
7166 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 7167 }
7168}
7169
c7ee65b3
WS		 7170/* If the controller reports that the total max sg entries is greater than 512,
7171 * then we know that chained SG blocks work. (Original smart arrays did not
7172 * support chained SG blocks and would return zero for max sg entries.)
7173 */
7174static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7175{
7176 return h->maxsgentries > 512;
7177}
7178
b93d7536
SC		 7179/* Interrogate the hardware for some limits:
7180 * max commands, max SG elements without chaining, and with chaining,
7181 * SG chain block size, etc.
7182 */
6f039790 7183static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 7184{
cba3d38b 7185 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 7186 h->nr_cmds = h->max_commands;
b93d7536 7187 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 7188 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 7189 if (hpsa_supports_chained_sg_blocks(h)) {
7190 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 7191 h->max_cmd_sg_entries = 32;
1a63ea6f 7192 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 7193 h->maxsgentries--; /* save one for chain pointer */
7194 } else {
c7ee65b3
WS		 7195 /*
7196 * Original smart arrays supported at most 31 s/g entries
7197 * embedded inline in the command (trying to use more
7198 * would lock up the controller)
7199 */
7200 h->max_cmd_sg_entries = 31;
1a63ea6f 7201 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 7202 h->chainsize = 0;
b93d7536 7203 }
75167d2c
SC		 7204
7205 /* Find out what task management functions are supported and cache */
7206 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 7207 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7208 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7209 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7210 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
8be986cc
SC		 7211 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7212 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
b93d7536
SC		 7213}
7214
76c46e49
SC		 7215static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7216{
0fc9fd40 7217 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 7218 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 7219 return false;
7220 }
7221 return true;
7222}
7223
97a5e98c 7224static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 7225{
97a5e98c 7226 u32 driver_support;
f7c39101 7227
97a5e98c 7228 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 7229 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7230#ifdef CONFIG_X86
97a5e98c 7231 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 7232#endif
28e13446
SC		 7233 driver_support |= ENABLE_UNIT_ATTN;
7234 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 7235}
7236
3d0eab67
SC		 7237/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7238 * in a prefetch beyond physical memory.
7239 */
7240static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7241{
7242 u32 dma_prefetch;
7243
7244 if (h->board_id != 0x3225103C)
7245 return;
7246 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7247 dma_prefetch |= 0x8000;
7248 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7249}
7250
c706a795 7251static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 7252{
7253 int i;
7254 u32 doorbell_value;
7255 unsigned long flags;
7256 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 7257 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 7258 spin_lock_irqsave(&h->lock, flags);
7259 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7260 spin_unlock_irqrestore(&h->lock, flags);
7261 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 7262 goto done;
76438d08 7263 /* delay and try again */
007e7aa9 7264 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 7265 }
c706a795
RE		 7266 return -ENODEV;
7267done:
7268 return 0;
76438d08
SC		 7269}
7270
c706a795 7271static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 7272{
7273 int i;
6eaf46fd
SC		 7274 u32 doorbell_value;
7275 unsigned long flags;
eb6b2ae9
SC		 7276
7277 /* under certain very rare conditions, this can take awhile.
7278 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7279 * as we enter this code.)
7280 */
007e7aa9 7281 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 7282 if (h->remove_in_progress)
7283 goto done;
6eaf46fd
SC		 7284 spin_lock_irqsave(&h->lock, flags);
7285 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7286 spin_unlock_irqrestore(&h->lock, flags);
382be668 7287 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 7288 goto done;
eb6b2ae9 7289 /* delay and try again */
007e7aa9 7290 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 7291 }
c706a795
RE		 7292 return -ENODEV;
7293done:
7294 return 0;
3f4336f3
SC		 7295}
7296
c706a795 7297/* return -ENODEV or other reason on error, 0 on success */
6f039790 7298static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 7299{
7300 u32 trans_support;
7301
7302 trans_support = readl(&(h->cfgtable->TransportSupport));
7303 if (!(trans_support & SIMPLE_MODE))
7304 return -ENOTSUPP;
7305
7306 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 7307
3f4336f3
SC		 7308 /* Update the field, and then ring the doorbell */
7309 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 7310 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 7311 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7312 if (hpsa_wait_for_mode_change_ack(h))
7313 goto error;
eb6b2ae9 7314 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 7315 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7316 goto error;
960a30e7 7317 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 7318 return 0;
283b4a9b 7319error:
050f7147 7320 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 7321 return -ENODEV;
eb6b2ae9
SC		 7322}
7323
195f2c65
RE		 7324/* free items allocated or mapped by hpsa_pci_init */
7325static void hpsa_free_pci_init(struct ctlr_info *h)
7326{
7327 hpsa_free_cfgtables(h); /* pci_init 4 */
7328 iounmap(h->vaddr); /* pci_init 3 */
105a3dbc 7329 h->vaddr = NULL;
195f2c65 7330 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
943a7021
RE		 7331 /*
7332 * call pci_disable_device before pci_release_regions per
7333 * Documentation/PCI/pci.txt
7334 */
195f2c65 7335 pci_disable_device(h->pdev); /* pci_init 1 */
943a7021 7336 pci_release_regions(h->pdev); /* pci_init 2 */
195f2c65
RE		 7337}
7338
7339/* several items must be freed later */
6f039790 7340static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 7341{
eb6b2ae9 7342 int prod_index, err;
edd16368 7343
e5c880d1
SC		 7344 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
7345 if (prod_index < 0)
60f923b9 7346 return prod_index;
e5c880d1
SC		 7347 h->product_name = products[prod_index].product_name;
7348 h->access = *(products[prod_index].access);
edd16368 7349
9b5c48c2
SC		 7350 h->needs_abort_tags_swizzled =
7351 ctlr_needs_abort_tags_swizzled(h->board_id);
7352
e5a44df8
MG		 7353 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7354 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7355
55c06c71 7356 err = pci_enable_device(h->pdev);
edd16368 7357 if (err) {
195f2c65 7358 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
943a7021 7359 pci_disable_device(h->pdev);
edd16368
SC		 7360 return err;
7361 }
7362
f79cfec6 7363 err = pci_request_regions(h->pdev, HPSA);
edd16368 7364 if (err) {
55c06c71 7365 dev_err(&h->pdev->dev,
195f2c65 7366 "failed to obtain PCI resources\n");
943a7021
RE		 7367 pci_disable_device(h->pdev);
7368 return err;
edd16368 7369 }
4fa604e1
RE		 7370
7371 pci_set_master(h->pdev);
7372
6b3f4c52 7373 hpsa_interrupt_mode(h);
12d2cd47 7374 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 7375 if (err)
195f2c65 7376 goto clean2; /* intmode+region, pci */
edd16368 7377 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 7378 if (!h->vaddr) {
195f2c65 7379 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 7380 err = -ENOMEM;
195f2c65 7381 goto clean2; /* intmode+region, pci */
204892e9 7382 }
fe5389c8 7383 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 7384 if (err)
195f2c65 7385 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 7386 err = hpsa_find_cfgtables(h);
7387 if (err)
195f2c65 7388 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 7389 hpsa_find_board_params(h);
edd16368 7390
76c46e49 7391 if (!hpsa_CISS_signature_present(h)) {
edd16368 7392 err = -ENODEV;
195f2c65 7393 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 7394 }
97a5e98c 7395 hpsa_set_driver_support_bits(h);
3d0eab67 7396 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 7397 err = hpsa_enter_simple_mode(h);
7398 if (err)
195f2c65 7399 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 7400 return 0;
7401
195f2c65
RE		 7402clean4: /* cfgtables, vaddr, intmode+region, pci */
7403 hpsa_free_cfgtables(h);
7404clean3: /* vaddr, intmode+region, pci */
7405 iounmap(h->vaddr);
105a3dbc 7406 h->vaddr = NULL;
195f2c65
RE		 7407clean2: /* intmode+region, pci */
7408 hpsa_disable_interrupt_mode(h);
943a7021
RE		 7409 /*
7410 * call pci_disable_device before pci_release_regions per
7411 * Documentation/PCI/pci.txt
7412 */
195f2c65 7413 pci_disable_device(h->pdev);
943a7021 7414 pci_release_regions(h->pdev);
edd16368
SC		 7415 return err;
7416}
7417
6f039790 7418static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 7419{
7420 int rc;
7421
7422#define HBA_INQUIRY_BYTE_COUNT 64
7423 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7424 if (!h->hba_inquiry_data)
7425 return;
7426 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7427 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7428 if (rc != 0) {
7429 kfree(h->hba_inquiry_data);
7430 h->hba_inquiry_data = NULL;
7431 }
7432}
7433
6b6c1cd7 7434static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 7435{
1df8552a 7436 int rc, i;
3b747298 7437 void __iomem *vaddr;
4c2a8c40
SC		 7438
7439 if (!reset_devices)
7440 return 0;
7441
132aa220
TH		 7442 /* kdump kernel is loading, we don't know in which state is
7443 * the pci interface. The dev->enable_cnt is equal zero
7444 * so we call enable+disable, wait a while and switch it on.
7445 */
7446 rc = pci_enable_device(pdev);
7447 if (rc) {
7448 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7449 return -ENODEV;
7450 }
7451 pci_disable_device(pdev);
7452 msleep(260); /* a randomly chosen number */
7453 rc = pci_enable_device(pdev);
7454 if (rc) {
7455 dev_warn(&pdev->dev, "failed to enable device.\n");
7456 return -ENODEV;
7457 }
4fa604e1 7458
859c75ab 7459 pci_set_master(pdev);
4fa604e1 7460
3b747298
TH		 7461 vaddr = pci_ioremap_bar(pdev, 0);
7462 if (vaddr == NULL) {
7463 rc = -ENOMEM;
7464 goto out_disable;
7465 }
7466 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
7467 iounmap(vaddr);
7468
1df8552a 7469 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 7470 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 7471
1df8552a
SC		 7472 /* -ENOTSUPP here means we cannot reset the controller
7473 * but it's already (and still) up and running in
18867659
SC		 7474 * "performant mode". Or, it might be 640x, which can't reset
7475 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 7476 */
adf1b3a3 7477 if (rc)
132aa220 7478 goto out_disable;
4c2a8c40
SC		 7479
7480 /* Now try to get the controller to respond to a no-op */
1ba66c9c 7481 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 7482 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
7483 if (hpsa_noop(pdev) == 0)
7484 break;
7485 else
7486 dev_warn(&pdev->dev, "no-op failed%s\n",
7487 (i < 11 ? "; re-trying" : ""));
7488 }
132aa220
TH		 7489
7490out_disable:
7491
7492 pci_disable_device(pdev);
7493 return rc;
4c2a8c40
SC		 7494}
7495
1fb7c98a
RE		 7496static void hpsa_free_cmd_pool(struct ctlr_info *h)
7497{
7498 kfree(h->cmd_pool_bits);
105a3dbc
RE		 7499 h->cmd_pool_bits = NULL;
7500 if (h->cmd_pool) {
1fb7c98a
RE		 7501 pci_free_consistent(h->pdev,
7502 h->nr_cmds * sizeof(struct CommandList),
7503 h->cmd_pool,
7504 h->cmd_pool_dhandle);
105a3dbc
RE		 7505 h->cmd_pool = NULL;
7506 h->cmd_pool_dhandle = 0;
7507 }
7508 if (h->errinfo_pool) {
1fb7c98a
RE		 7509 pci_free_consistent(h->pdev,
7510 h->nr_cmds * sizeof(struct ErrorInfo),
7511 h->errinfo_pool,
7512 h->errinfo_pool_dhandle);
105a3dbc
RE		 7513 h->errinfo_pool = NULL;
7514 h->errinfo_pool_dhandle = 0;
7515 }
1fb7c98a
RE		 7516}
7517
d37ffbe4 7518static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 7519{
7520 h->cmd_pool_bits = kzalloc(
7521 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
7522 sizeof(unsigned long), GFP_KERNEL);
7523 h->cmd_pool = pci_alloc_consistent(h->pdev,
7524 h->nr_cmds * sizeof(*h->cmd_pool),
7525 &(h->cmd_pool_dhandle));
7526 h->errinfo_pool = pci_alloc_consistent(h->pdev,
7527 h->nr_cmds * sizeof(*h->errinfo_pool),
7528 &(h->errinfo_pool_dhandle));
7529 if ((h->cmd_pool_bits == NULL)
7530 || (h->cmd_pool == NULL)
7531 || (h->errinfo_pool == NULL)) {
7532 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 7533 goto clean_up;
2e9d1b36 7534 }
360c73bd 7535 hpsa_preinitialize_commands(h);
2e9d1b36 7536 return 0;
2c143342
RE		 7537clean_up:
7538 hpsa_free_cmd_pool(h);
7539 return -ENOMEM;
2e9d1b36
SC		 7540}
7541
41b3cf08
SC		 7542static void hpsa_irq_affinity_hints(struct ctlr_info *h)
7543{
ec429952 7544 int i, cpu;
41b3cf08
SC		 7545
7546 cpu = cpumask_first(cpu_online_mask);
7547 for (i = 0; i < h->msix_vector; i++) {
ec429952 7548 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 7549 cpu = cpumask_next(cpu, cpu_online_mask);
7550 }
7551}
7552
ec501a18
RE		 7553/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
7554static void hpsa_free_irqs(struct ctlr_info *h)
7555{
7556 int i;
7557
7558 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
7559 /* Single reply queue, only one irq to free */
7560 i = h->intr_mode;
7561 irq_set_affinity_hint(h->intr[i], NULL);
7562 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7563 h->q[i] = 0;
ec501a18
RE		 7564 return;
7565 }
7566
7567 for (i = 0; i < h->msix_vector; i++) {
7568 irq_set_affinity_hint(h->intr[i], NULL);
7569 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7570 h->q[i] = 0;
ec501a18 7571 }
a4e17fc1
RE		 7572 for (; i < MAX_REPLY_QUEUES; i++)
7573 h->q[i] = 0;
ec501a18
RE		 7574}
7575
9ee61794
RE		 7576/* returns 0 on success; cleans up and returns -Enn on error */
7577static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 7578 irqreturn_t (*msixhandler)(int, void *),
7579 irqreturn_t (*intxhandler)(int, void *))
7580{
254f796b 7581 int rc, i;
0ae01a32 7582
254f796b
MG		 7583 /*
7584 * initialize h->q[x] = x so that interrupt handlers know which
7585 * queue to process.
7586 */
7587 for (i = 0; i < MAX_REPLY_QUEUES; i++)
7588 h->q[i] = (u8) i;
7589
eee0f03a 7590 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 7591 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 7592 for (i = 0; i < h->msix_vector; i++) {
8b47004a 7593 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
254f796b 7594 rc = request_irq(h->intr[i], msixhandler,
8b47004a 7595 0, h->intrname[i],
254f796b 7596 &h->q[i]);
a4e17fc1
RE		 7597 if (rc) {
7598 int j;
7599
7600 dev_err(&h->pdev->dev,
7601 "failed to get irq %d for %s\n",
7602 h->intr[i], h->devname);
7603 for (j = 0; j < i; j++) {
7604 free_irq(h->intr[j], &h->q[j]);
7605 h->q[j] = 0;
7606 }
7607 for (; j < MAX_REPLY_QUEUES; j++)
7608 h->q[j] = 0;
7609 return rc;
7610 }
7611 }
41b3cf08 7612 hpsa_irq_affinity_hints(h);
254f796b
MG		 7613 } else {
7614 /* Use single reply pool */
eee0f03a 7615 if (h->msix_vector > 0 || h->msi_vector) {
8b47004a
RE		 7616 if (h->msix_vector)
7617 sprintf(h->intrname[h->intr_mode],
7618 "%s-msix", h->devname);
7619 else
7620 sprintf(h->intrname[h->intr_mode],
7621 "%s-msi", h->devname);
254f796b 7622 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7623 msixhandler, 0,
7624 h->intrname[h->intr_mode],
254f796b
MG		 7625 &h->q[h->intr_mode]);
7626 } else {
8b47004a
RE		 7627 sprintf(h->intrname[h->intr_mode],
7628 "%s-intx", h->devname);
254f796b 7629 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7630 intxhandler, IRQF_SHARED,
7631 h->intrname[h->intr_mode],
254f796b
MG		 7632 &h->q[h->intr_mode]);
7633 }
105a3dbc 7634 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
254f796b 7635 }
0ae01a32 7636 if (rc) {
195f2c65 7637 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 7638 h->intr[h->intr_mode], h->devname);
195f2c65 7639 hpsa_free_irqs(h);
0ae01a32
SC		 7640 return -ENODEV;
7641 }
7642 return 0;
7643}
7644
6f039790 7645static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8 7646{
39c53f55 7647 int rc;
bf43caf3 7648 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
64670ac8
SC		 7649
7650 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
39c53f55
RE		 7651 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
7652 if (rc) {
64670ac8 7653 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
39c53f55 7654 return rc;
64670ac8
SC		 7655 }
7656
7657 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
39c53f55
RE		 7658 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
7659 if (rc) {
64670ac8
SC		 7660 dev_warn(&h->pdev->dev, "Board failed to become ready "
7661 "after soft reset.\n");
39c53f55 7662 return rc;
64670ac8
SC		 7663 }
7664
7665 return 0;
7666}
7667
072b0518
SC		 7668static void hpsa_free_reply_queues(struct ctlr_info *h)
7669{
7670 int i;
7671
7672 for (i = 0; i < h->nreply_queues; i++) {
7673 if (!h->reply_queue[i].head)
7674 continue;
1fb7c98a
RE		 7675 pci_free_consistent(h->pdev,
7676 h->reply_queue_size,
7677 h->reply_queue[i].head,
7678 h->reply_queue[i].busaddr);
072b0518
SC		 7679 h->reply_queue[i].head = NULL;
7680 h->reply_queue[i].busaddr = 0;
7681 }
105a3dbc 7682 h->reply_queue_size = 0;
072b0518
SC		 7683}
7684
0097f0f4
SC		 7685static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
7686{
105a3dbc
RE		 7687 hpsa_free_performant_mode(h); /* init_one 7 */
7688 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
7689 hpsa_free_cmd_pool(h); /* init_one 5 */
7690 hpsa_free_irqs(h); /* init_one 4 */
2946e82b
RE		 7691 scsi_host_put(h->scsi_host); /* init_one 3 */
7692 h->scsi_host = NULL; /* init_one 3 */
7693 hpsa_free_pci_init(h); /* init_one 2_5 */
9ecd953a
RE		 7694 free_percpu(h->lockup_detected); /* init_one 2 */
7695 h->lockup_detected = NULL; /* init_one 2 */
7696 if (h->resubmit_wq) {
7697 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
7698 h->resubmit_wq = NULL;
7699 }
7700 if (h->rescan_ctlr_wq) {
7701 destroy_workqueue(h->rescan_ctlr_wq);
7702 h->rescan_ctlr_wq = NULL;
7703 }
105a3dbc 7704 kfree(h); /* init_one 1 */
64670ac8
SC		 7705}
7706
a0c12413 7707/* Called when controller lockup detected. */
f2405db8 7708static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 7709{
281a7fd0
WS		 7710 int i, refcount;
7711 struct CommandList *c;
25163bd5 7712 int failcount = 0;
a0c12413 7713
080ef1cc 7714 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 7715 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7716 c = h->cmd_pool + i;
281a7fd0
WS		 7717 refcount = atomic_inc_return(&c->refcount);
7718 if (refcount > 1) {
25163bd5 7719 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 7720 finish_cmd(c);
433b5f4d 7721 atomic_dec(&h->commands_outstanding);
25163bd5 7722 failcount++;
281a7fd0
WS		 7723 }
7724 cmd_free(h, c);
a0c12413 7725 }
25163bd5
WS		 7726 dev_warn(&h->pdev->dev,
7727 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 7728}
7729
094963da
SC		 7730static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
7731{
c8ed0010 7732 int cpu;
094963da 7733
c8ed0010 7734 for_each_online_cpu(cpu) {
094963da
SC		 7735 u32 *lockup_detected;
7736 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
7737 *lockup_detected = value;
094963da
SC		 7738 }
7739 wmb(); /* be sure the per-cpu variables are out to memory */
7740}
7741
a0c12413
SC		 7742static void controller_lockup_detected(struct ctlr_info *h)
7743{
7744 unsigned long flags;
094963da 7745 u32 lockup_detected;
a0c12413 7746
a0c12413
SC		 7747 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7748 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 7749 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
7750 if (!lockup_detected) {
7751 /* no heartbeat, but controller gave us a zero. */
7752 dev_warn(&h->pdev->dev,
25163bd5
WS		 7753 "lockup detected after %d but scratchpad register is zero\n",
7754 h->heartbeat_sample_interval / HZ);
094963da
SC		 7755 lockup_detected = 0xffffffff;
7756 }
7757 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 7758 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 7759 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
7760 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 7761 pci_disable_device(h->pdev);
f2405db8 7762 fail_all_outstanding_cmds(h);
a0c12413
SC		 7763}
7764
25163bd5 7765static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 7766{
7767 u64 now;
7768 u32 heartbeat;
7769 unsigned long flags;
7770
a0c12413
SC		 7771 now = get_jiffies_64();
7772 /* If we've received an interrupt recently, we're ok. */
7773 if (time_after64(h->last_intr_timestamp +
e85c5974 7774 (h->heartbeat_sample_interval), now))
25163bd5 7775 return false;
a0c12413
SC		 7776
7777 /*
7778 * If we've already checked the heartbeat recently, we're ok.
7779 * This could happen if someone sends us a signal. We
7780 * otherwise don't care about signals in this thread.
7781 */
7782 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 7783 (h->heartbeat_sample_interval), now))
25163bd5 7784 return false;
a0c12413
SC		 7785
7786 /* If heartbeat has not changed since we last looked, we're not ok. */
7787 spin_lock_irqsave(&h->lock, flags);
7788 heartbeat = readl(&h->cfgtable->HeartBeat);
7789 spin_unlock_irqrestore(&h->lock, flags);
7790 if (h->last_heartbeat == heartbeat) {
7791 controller_lockup_detected(h);
25163bd5 7792 return true;
a0c12413
SC		 7793 }
7794
7795 /* We're ok. */
7796 h->last_heartbeat = heartbeat;
7797 h->last_heartbeat_timestamp = now;
25163bd5 7798 return false;
a0c12413
SC		 7799}
7800
9846590e 7801static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 7802{
7803 int i;
7804 char *event_type;
7805
e4aa3e6a
SC		 7806 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7807 return;
7808
76438d08 7809 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 7810 if ((h->transMethod & (CFGTBL_Trans_io_accel1
7811 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 7812 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
7813 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
7814
7815 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
7816 event_type = "state change";
7817 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
7818 event_type = "configuration change";
7819 /* Stop sending new RAID offload reqs via the IO accelerator */
7820 scsi_block_requests(h->scsi_host);
7821 for (i = 0; i < h->ndevices; i++)
7822 h->dev[i]->offload_enabled = 0;
23100dd9 7823 hpsa_drain_accel_commands(h);
76438d08
SC		 7824 /* Set 'accelerator path config change' bit */
7825 dev_warn(&h->pdev->dev,
7826 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7827 h->events, event_type);
7828 writel(h->events, &(h->cfgtable->clear_event_notify));
7829 /* Set the "clear event notify field update" bit 6 */
7830 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7831 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7832 hpsa_wait_for_clear_event_notify_ack(h);
7833 scsi_unblock_requests(h->scsi_host);
7834 } else {
7835 /* Acknowledge controller notification events. */
7836 writel(h->events, &(h->cfgtable->clear_event_notify));
7837 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7838 hpsa_wait_for_clear_event_notify_ack(h);
7839#if 0
7840 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7841 hpsa_wait_for_mode_change_ack(h);
7842#endif
7843 }
9846590e 7844 return;
76438d08
SC		 7845}
7846
7847/* Check a register on the controller to see if there are configuration
7848 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 7849 * we should rescan the controller for devices.
7850 * Also check flag for driver-initiated rescan.
76438d08 7851 */
9846590e 7852static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08
SC		 7853{
7854 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 7855 return 0;
76438d08
SC		 7856
7857 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 7858 return h->events & RESCAN_REQUIRED_EVENT_BITS;
7859}
76438d08 7860
9846590e
SC		 7861/*
7862 * Check if any of the offline devices have become ready
7863 */
7864static int hpsa_offline_devices_ready(struct ctlr_info *h)
7865{
7866 unsigned long flags;
7867 struct offline_device_entry *d;
7868 struct list_head *this, *tmp;
7869
7870 spin_lock_irqsave(&h->offline_device_lock, flags);
7871 list_for_each_safe(this, tmp, &h->offline_device_list) {
7872 d = list_entry(this, struct offline_device_entry,
7873 offline_list);
7874 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 7875 if (!hpsa_volume_offline(h, d->scsi3addr)) {
7876 spin_lock_irqsave(&h->offline_device_lock, flags);
7877 list_del(&d->offline_list);
7878 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 7879 return 1;
d1fea47c 7880 }
9846590e
SC		 7881 spin_lock_irqsave(&h->offline_device_lock, flags);
7882 }
7883 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7884 return 0;
76438d08
SC		 7885}
7886
6636e7f4 7887static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 7888{
7889 unsigned long flags;
8a98db73 7890 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 7891 struct ctlr_info, rescan_ctlr_work);
7892
7893
7894 if (h->remove_in_progress)
8a98db73 7895 return;
9846590e
SC		 7896
7897 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
7898 scsi_host_get(h->scsi_host);
9846590e
SC		 7899 hpsa_ack_ctlr_events(h);
7900 hpsa_scan_start(h->scsi_host);
7901 scsi_host_put(h->scsi_host);
7902 }
8a98db73 7903 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 7904 if (!h->remove_in_progress)
7905 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7906 h->heartbeat_sample_interval);
7907 spin_unlock_irqrestore(&h->lock, flags);
7908}
7909
7910static void hpsa_monitor_ctlr_worker(struct work_struct *work)
7911{
7912 unsigned long flags;
7913 struct ctlr_info *h = container_of(to_delayed_work(work),
7914 struct ctlr_info, monitor_ctlr_work);
7915
7916 detect_controller_lockup(h);
7917 if (lockup_detected(h))
a0c12413 7918 return;
6636e7f4
DB		 7919
7920 spin_lock_irqsave(&h->lock, flags);
7921 if (!h->remove_in_progress)
7922 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 7923 h->heartbeat_sample_interval);
7924 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 7925}
7926
6636e7f4
DB		 7927static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
7928 char *name)
7929{
7930 struct workqueue_struct *wq = NULL;
6636e7f4 7931
397ea9cb 7932 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 7933 if (!wq)
7934 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
7935
7936 return wq;
7937}
7938
6f039790 7939static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 7940{
4c2a8c40 7941 int dac, rc;
edd16368 7942 struct ctlr_info *h;
64670ac8
SC		 7943 int try_soft_reset = 0;
7944 unsigned long flags;
6b6c1cd7 7945 u32 board_id;
edd16368
SC		 7946
7947 if (number_of_controllers == 0)
7948 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 7949
6b6c1cd7
TH		 7950 rc = hpsa_lookup_board_id(pdev, &board_id);
7951 if (rc < 0) {
7952 dev_warn(&pdev->dev, "Board ID not found\n");
7953 return rc;
7954 }
7955
7956 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 7957 if (rc) {
7958 if (rc != -ENOTSUPP)
7959 return rc;
7960 /* If the reset fails in a particular way (it has no way to do
7961 * a proper hard reset, so returns -ENOTSUPP) we can try to do
7962 * a soft reset once we get the controller configured up to the
7963 * point that it can accept a command.
7964 */
7965 try_soft_reset = 1;
7966 rc = 0;
7967 }
7968
7969reinit_after_soft_reset:
edd16368 7970
303932fd
DB		 7971 /* Command structures must be aligned on a 32-byte boundary because
7972 * the 5 lower bits of the address are used by the hardware. and by
7973 * the driver. See comments in hpsa.h for more info.
7974 */
303932fd 7975 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368 7976 h = kzalloc(sizeof(*h), GFP_KERNEL);
105a3dbc
RE		 7977 if (!h) {
7978 dev_err(&pdev->dev, "Failed to allocate controller head\n");
ecd9aad4 7979 return -ENOMEM;
105a3dbc 7980 }
edd16368 7981
55c06c71 7982 h->pdev = pdev;
105a3dbc 7983
a9a3a273 7984 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 7985 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 7986 spin_lock_init(&h->lock);
9846590e 7987 spin_lock_init(&h->offline_device_lock);
6eaf46fd 7988 spin_lock_init(&h->scan_lock);
34f0c627 7989 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 7990 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da
SC		 7991
7992 /* Allocate and clear per-cpu variable lockup_detected */
7993 h->lockup_detected = alloc_percpu(u32);
2a5ac326 7994 if (!h->lockup_detected) {
105a3dbc 7995 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
2a5ac326 7996 rc = -ENOMEM;
2efa5929 7997 goto clean1; /* aer/h */
2a5ac326 7998 }
094963da
SC		 7999 set_lockup_detected_for_all_cpus(h, 0);
8000
55c06c71 8001 rc = hpsa_pci_init(h);
105a3dbc 8002 if (rc)
2946e82b
RE		 8003 goto clean2; /* lu, aer/h */
8004
8005 /* relies on h-> settings made by hpsa_pci_init, including
8006 * interrupt_mode h->intr */
8007 rc = hpsa_scsi_host_alloc(h);
8008 if (rc)
8009 goto clean2_5; /* pci, lu, aer/h */
edd16368 8010
2946e82b 8011 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
edd16368
SC		 8012 h->ctlr = number_of_controllers;
8013 number_of_controllers++;
edd16368
SC		 8014
8015 /* configure PCI DMA stuff */
ecd9aad4
SC		 8016 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
8017 if (rc == 0) {
edd16368 8018 dac = 1;
ecd9aad4
SC		 8019 } else {
8020 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8021 if (rc == 0) {
8022 dac = 0;
8023 } else {
8024 dev_err(&pdev->dev, "no suitable DMA available\n");
2946e82b 8025 goto clean3; /* shost, pci, lu, aer/h */
ecd9aad4 8026 }
edd16368
SC		 8027 }
8028
8029 /* make sure the board interrupts are off */
8030 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 8031
105a3dbc
RE		 8032 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
8033 if (rc)
2946e82b 8034 goto clean3; /* shost, pci, lu, aer/h */
d37ffbe4 8035 rc = hpsa_alloc_cmd_pool(h);
8947fd10 8036 if (rc)
2946e82b 8037 goto clean4; /* irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8038 rc = hpsa_alloc_sg_chain_blocks(h);
8039 if (rc)
2946e82b 8040 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
a08a8471 8041 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 8042 init_waitqueue_head(&h->abort_cmd_wait_queue);
d604f533
WS		 8043 init_waitqueue_head(&h->event_sync_wait_queue);
8044 mutex_init(&h->reset_mutex);
a08a8471 8045 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 8046
8047 pci_set_drvdata(pdev, h);
9a41338e 8048 h->ndevices = 0;
2946e82b 8049
9a41338e 8050 spin_lock_init(&h->devlock);
105a3dbc
RE		 8051 rc = hpsa_put_ctlr_into_performant_mode(h);
8052 if (rc)
2946e82b
RE		 8053 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8054
8055 /* hook into SCSI subsystem */
8056 rc = hpsa_scsi_add_host(h);
8057 if (rc)
8058 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
2efa5929
RE		 8059
8060 /* create the resubmit workqueue */
8061 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8062 if (!h->rescan_ctlr_wq) {
8063 rc = -ENOMEM;
8064 goto clean7;
8065 }
8066
8067 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8068 if (!h->resubmit_wq) {
8069 rc = -ENOMEM;
8070 goto clean7; /* aer/h */
8071 }
64670ac8 8072
105a3dbc
RE		 8073 /*
8074 * At this point, the controller is ready to take commands.
64670ac8
SC		 8075 * Now, if reset_devices and the hard reset didn't work, try
8076 * the soft reset and see if that works.
8077 */
8078 if (try_soft_reset) {
8079
8080 /* This is kind of gross. We may or may not get a completion
8081 * from the soft reset command, and if we do, then the value
8082 * from the fifo may or may not be valid. So, we wait 10 secs
8083 * after the reset throwing away any completions we get during
8084 * that time. Unregister the interrupt handler and register
8085 * fake ones to scoop up any residual completions.
8086 */
8087 spin_lock_irqsave(&h->lock, flags);
8088 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8089 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 8090 hpsa_free_irqs(h);
9ee61794 8091 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 8092 hpsa_intx_discard_completions);
8093 if (rc) {
9ee61794
RE		 8094 dev_warn(&h->pdev->dev,
8095 "Failed to request_irq after soft reset.\n");
d498757c 8096 /*
b2ef480c
RE		 8097 * cannot goto clean7 or free_irqs will be called
8098 * again. Instead, do its work
8099 */
8100 hpsa_free_performant_mode(h); /* clean7 */
8101 hpsa_free_sg_chain_blocks(h); /* clean6 */
8102 hpsa_free_cmd_pool(h); /* clean5 */
8103 /*
8104 * skip hpsa_free_irqs(h) clean4 since that
8105 * was just called before request_irqs failed
d498757c
RE		 8106 */
8107 goto clean3;
64670ac8
SC		 8108 }
8109
8110 rc = hpsa_kdump_soft_reset(h);
8111 if (rc)
8112 /* Neither hard nor soft reset worked, we're hosed. */
7ef7323f 8113 goto clean7;
64670ac8
SC		 8114
8115 dev_info(&h->pdev->dev, "Board READY.\n");
8116 dev_info(&h->pdev->dev,
8117 "Waiting for stale completions to drain.\n");
8118 h->access.set_intr_mask(h, HPSA_INTR_ON);
8119 msleep(10000);
8120 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8121
8122 rc = controller_reset_failed(h->cfgtable);
8123 if (rc)
8124 dev_info(&h->pdev->dev,
8125 "Soft reset appears to have failed.\n");
8126
8127 /* since the controller's reset, we have to go back and re-init
8128 * everything. Easiest to just forget what we've done and do it
8129 * all over again.
8130 */
8131 hpsa_undo_allocations_after_kdump_soft_reset(h);
8132 try_soft_reset = 0;
8133 if (rc)
b2ef480c 8134 /* don't goto clean, we already unallocated */
64670ac8
SC		 8135 return -ENODEV;
8136
8137 goto reinit_after_soft_reset;
8138 }
edd16368 8139
105a3dbc
RE		 8140 /* Enable Accelerated IO path at driver layer */
8141 h->acciopath_status = 1;
da0697bd 8142
e863d68e 8143
edd16368
SC		 8144 /* Turn the interrupts on so we can service requests */
8145 h->access.set_intr_mask(h, HPSA_INTR_ON);
8146
339b2b14 8147 hpsa_hba_inquiry(h);
8a98db73
SC		 8148
8149 /* Monitor the controller for firmware lockups */
8150 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8151 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8152 schedule_delayed_work(&h->monitor_ctlr_work,
8153 h->heartbeat_sample_interval);
6636e7f4
DB		 8154 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8155 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8156 h->heartbeat_sample_interval);
88bf6d62 8157 return 0;
edd16368 8158
2946e82b 8159clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8160 hpsa_free_performant_mode(h);
8161 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8162clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
33a2ffce 8163 hpsa_free_sg_chain_blocks(h);
2946e82b 8164clean5: /* cmd, irq, shost, pci, lu, aer/h */
2e9d1b36 8165 hpsa_free_cmd_pool(h);
2946e82b 8166clean4: /* irq, shost, pci, lu, aer/h */
ec501a18 8167 hpsa_free_irqs(h);
2946e82b
RE		 8168clean3: /* shost, pci, lu, aer/h */
8169 scsi_host_put(h->scsi_host);
8170 h->scsi_host = NULL;
8171clean2_5: /* pci, lu, aer/h */
195f2c65 8172 hpsa_free_pci_init(h);
2946e82b 8173clean2: /* lu, aer/h */
105a3dbc
RE		 8174 if (h->lockup_detected) {
8175 free_percpu(h->lockup_detected);
8176 h->lockup_detected = NULL;
8177 }
8178clean1: /* wq/aer/h */
8179 if (h->resubmit_wq) {
080ef1cc 8180 destroy_workqueue(h->resubmit_wq);
105a3dbc
RE		 8181 h->resubmit_wq = NULL;
8182 }
8183 if (h->rescan_ctlr_wq) {
6636e7f4 8184 destroy_workqueue(h->rescan_ctlr_wq);
105a3dbc
RE		 8185 h->rescan_ctlr_wq = NULL;
8186 }
edd16368 8187 kfree(h);
ecd9aad4 8188 return rc;
edd16368
SC		 8189}
8190
8191static void hpsa_flush_cache(struct ctlr_info *h)
8192{
8193 char *flush_buf;
8194 struct CommandList *c;
25163bd5 8195 int rc;
702890e3 8196
094963da 8197 if (unlikely(lockup_detected(h)))
702890e3 8198 return;
edd16368
SC		 8199 flush_buf = kzalloc(4, GFP_KERNEL);
8200 if (!flush_buf)
8201 return;
8202
45fcb86e 8203 c = cmd_alloc(h);
bf43caf3 8204
a2dac136
SC		 8205 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8206 RAID_CTLR_LUNID, TYPE_CMD)) {
8207 goto out;
8208 }
25163bd5
WS		 8209 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8210 PCI_DMA_TODEVICE, NO_TIMEOUT);
8211 if (rc)
8212 goto out;
edd16368 8213 if (c->err_info->CommandStatus != 0)
a2dac136 8214out:
edd16368
SC		 8215 dev_warn(&h->pdev->dev,
8216 "error flushing cache on controller\n");
45fcb86e 8217 cmd_free(h, c);
edd16368
SC		 8218 kfree(flush_buf);
8219}
8220
8221static void hpsa_shutdown(struct pci_dev *pdev)
8222{
8223 struct ctlr_info *h;
8224
8225 h = pci_get_drvdata(pdev);
8226 /* Turn board interrupts off and send the flush cache command
8227 * sendcmd will turn off interrupt, and send the flush...
8228 * To write all data in the battery backed cache to disks
8229 */
8230 hpsa_flush_cache(h);
8231 h->access.set_intr_mask(h, HPSA_INTR_OFF);
105a3dbc 8232 hpsa_free_irqs(h); /* init_one 4 */
cc64c817 8233 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 8234}
8235
6f039790 8236static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 8237{
8238 int i;
8239
105a3dbc 8240 for (i = 0; i < h->ndevices; i++) {
55e14e76 8241 kfree(h->dev[i]);
105a3dbc
RE		 8242 h->dev[i] = NULL;
8243 }
55e14e76
SC		 8244}
8245
6f039790 8246static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 8247{
8248 struct ctlr_info *h;
8a98db73 8249 unsigned long flags;
edd16368
SC		 8250
8251 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 8252 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 8253 return;
8254 }
8255 h = pci_get_drvdata(pdev);
8a98db73
SC		 8256
8257 /* Get rid of any controller monitoring work items */
8258 spin_lock_irqsave(&h->lock, flags);
8259 h->remove_in_progress = 1;
8a98db73 8260 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 8261 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8262 cancel_delayed_work_sync(&h->rescan_ctlr_work);
8263 destroy_workqueue(h->rescan_ctlr_wq);
8264 destroy_workqueue(h->resubmit_wq);
cc64c817 8265
105a3dbc 8266 /* includes hpsa_free_irqs - init_one 4 */
195f2c65 8267 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 8268 hpsa_shutdown(pdev);
cc64c817 8269
105a3dbc
RE		 8270 hpsa_free_device_info(h); /* scan */
8271
2946e82b
RE		 8272 kfree(h->hba_inquiry_data); /* init_one 10 */
8273 h->hba_inquiry_data = NULL; /* init_one 10 */
8274 if (h->scsi_host)
8275 scsi_remove_host(h->scsi_host); /* init_one 8 */
8276 hpsa_free_ioaccel2_sg_chain_blocks(h);
105a3dbc
RE		 8277 hpsa_free_performant_mode(h); /* init_one 7 */
8278 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8279 hpsa_free_cmd_pool(h); /* init_one 5 */
8280
8281 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
195f2c65 8282
2946e82b
RE		 8283 scsi_host_put(h->scsi_host); /* init_one 3 */
8284 h->scsi_host = NULL; /* init_one 3 */
8285
195f2c65 8286 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
2946e82b 8287 hpsa_free_pci_init(h); /* init_one 2.5 */
195f2c65 8288
105a3dbc
RE		 8289 free_percpu(h->lockup_detected); /* init_one 2 */
8290 h->lockup_detected = NULL; /* init_one 2 */
8291 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
8292 kfree(h); /* init_one 1 */
edd16368
SC		 8293}
8294
8295static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8296 __attribute__((unused)) pm_message_t state)
8297{
8298 return -ENOSYS;
8299}
8300
8301static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8302{
8303 return -ENOSYS;
8304}
8305
8306static struct pci_driver hpsa_pci_driver = {
f79cfec6 8307 .name = HPSA,
edd16368 8308 .probe = hpsa_init_one,
6f039790 8309 .remove = hpsa_remove_one,
edd16368
SC		 8310 .id_table = hpsa_pci_device_id, /* id_table */
8311 .shutdown = hpsa_shutdown,
8312 .suspend = hpsa_suspend,
8313 .resume = hpsa_resume,
8314};
8315
303932fd
DB		 8316/* Fill in bucket_map[], given nsgs (the max number of
8317 * scatter gather elements supported) and bucket[],
8318 * which is an array of 8 integers. The bucket[] array
8319 * contains 8 different DMA transfer sizes (in 16
8320 * byte increments) which the controller uses to fetch
8321 * commands. This function fills in bucket_map[], which
8322 * maps a given number of scatter gather elements to one of
8323 * the 8 DMA transfer sizes. The point of it is to allow the
8324 * controller to only do as much DMA as needed to fetch the
8325 * command, with the DMA transfer size encoded in the lower
8326 * bits of the command address.
8327 */
8328static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 8329 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 8330{
8331 int i, j, b, size;
8332
303932fd
DB		 8333 /* Note, bucket_map must have nsgs+1 entries. */
8334 for (i = 0; i <= nsgs; i++) {
8335 /* Compute size of a command with i SG entries */
e1f7de0c 8336 size = i + min_blocks;
303932fd
DB		 8337 b = num_buckets; /* Assume the biggest bucket */
8338 /* Find the bucket that is just big enough */
e1f7de0c 8339 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 8340 if (bucket[j] >= size) {
8341 b = j;
8342 break;
8343 }
8344 }
8345 /* for a command with i SG entries, use bucket b. */
8346 bucket_map[i] = b;
8347 }
8348}
8349
105a3dbc
RE		 8350/*
8351 * return -ENODEV on err, 0 on success (or no action)
8352 * allocates numerous items that must be freed later
8353 */
c706a795 8354static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 8355{
6c311b57
SC		 8356 int i;
8357 unsigned long register_value;
e1f7de0c
MG		 8358 unsigned long transMethod = CFGTBL_Trans_Performant |
8359 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 8360 CFGTBL_Trans_enable_directed_msix |
8361 (trans_support & (CFGTBL_Trans_io_accel1 |
8362 CFGTBL_Trans_io_accel2));
e1f7de0c 8363 struct access_method access = SA5_performant_access;
def342bd
SC		 8364
8365 /* This is a bit complicated. There are 8 registers on
8366 * the controller which we write to to tell it 8 different
8367 * sizes of commands which there may be. It's a way of
8368 * reducing the DMA done to fetch each command. Encoded into
8369 * each command's tag are 3 bits which communicate to the controller
8370 * which of the eight sizes that command fits within. The size of
8371 * each command depends on how many scatter gather entries there are.
8372 * Each SG entry requires 16 bytes. The eight registers are programmed
8373 * with the number of 16-byte blocks a command of that size requires.
8374 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 8375 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 8376 * blocks. Note, this only extends to the SG entries contained
8377 * within the command block, and does not extend to chained blocks
8378 * of SG elements. bft[] contains the eight values we write to
8379 * the registers. They are not evenly distributed, but have more
8380 * sizes for small commands, and fewer sizes for larger commands.
8381 */
d66ae08b 8382 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 8383#define MIN_IOACCEL2_BFT_ENTRY 5
8384#define HPSA_IOACCEL2_HEADER_SZ 4
8385 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
8386 13, 14, 15, 16, 17, 18, 19,
8387 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
8388 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
8389 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
8390 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
8391 16 * MIN_IOACCEL2_BFT_ENTRY);
8392 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 8393 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 8394 /* 5 = 1 s/g entry or 4k
8395 * 6 = 2 s/g entry or 8k
8396 * 8 = 4 s/g entry or 16k
8397 * 10 = 6 s/g entry or 24k
8398 */
303932fd 8399
b3a52e79
SC		 8400 /* If the controller supports either ioaccel method then
8401 * we can also use the RAID stack submit path that does not
8402 * perform the superfluous readl() after each command submission.
8403 */
8404 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
8405 access = SA5_performant_access_no_read;
8406
303932fd 8407 /* Controller spec: zero out this buffer. */
072b0518
SC		 8408 for (i = 0; i < h->nreply_queues; i++)
8409 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 8410
d66ae08b
SC		 8411 bft[7] = SG_ENTRIES_IN_CMD + 4;
8412 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 8413 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 8414 for (i = 0; i < 8; i++)
8415 writel(bft[i], &h->transtable->BlockFetch[i]);
8416
8417 /* size of controller ring buffer */
8418 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 8419 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 8420 writel(0, &h->transtable->RepQCtrAddrLow32);
8421 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 8422
8423 for (i = 0; i < h->nreply_queues; i++) {
8424 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 8425 writel(h->reply_queue[i].busaddr,
254f796b
MG		 8426 &h->transtable->RepQAddr[i].lower);
8427 }
8428
b9af4937 8429 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 8430 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
8431 /*
8432 * enable outbound interrupt coalescing in accelerator mode;
8433 */
8434 if (trans_support & CFGTBL_Trans_io_accel1) {
8435 access = SA5_ioaccel_mode1_access;
8436 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8437 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 8438 } else {
8439 if (trans_support & CFGTBL_Trans_io_accel2) {
8440 access = SA5_ioaccel_mode2_access;
8441 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8442 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
8443 }
e1f7de0c 8444 }
303932fd 8445 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8446 if (hpsa_wait_for_mode_change_ack(h)) {
8447 dev_err(&h->pdev->dev,
8448 "performant mode problem - doorbell timeout\n");
8449 return -ENODEV;
8450 }
303932fd
DB		 8451 register_value = readl(&(h->cfgtable->TransportActive));
8452 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 8453 dev_err(&h->pdev->dev,
8454 "performant mode problem - transport not active\n");
c706a795 8455 return -ENODEV;
303932fd 8456 }
960a30e7 8457 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 8458 h->access = access;
8459 h->transMethod = transMethod;
8460
b9af4937
SC		 8461 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
8462 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 8463 return 0;
e1f7de0c 8464
b9af4937
SC		 8465 if (trans_support & CFGTBL_Trans_io_accel1) {
8466 /* Set up I/O accelerator mode */
8467 for (i = 0; i < h->nreply_queues; i++) {
8468 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
8469 h->reply_queue[i].current_entry =
8470 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
8471 }
8472 bft[7] = h->ioaccel_maxsg + 8;
8473 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
8474 h->ioaccel1_blockFetchTable);
e1f7de0c 8475
b9af4937 8476 /* initialize all reply queue entries to unused */
072b0518
SC		 8477 for (i = 0; i < h->nreply_queues; i++)
8478 memset(h->reply_queue[i].head,
8479 (u8) IOACCEL_MODE1_REPLY_UNUSED,
8480 h->reply_queue_size);
e1f7de0c 8481
b9af4937
SC		 8482 /* set all the constant fields in the accelerator command
8483 * frames once at init time to save CPU cycles later.
8484 */
8485 for (i = 0; i < h->nr_cmds; i++) {
8486 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
8487
8488 cp->function = IOACCEL1_FUNCTION_SCSIIO;
8489 cp->err_info = (u32) (h->errinfo_pool_dhandle +
8490 (i * sizeof(struct ErrorInfo)));
8491 cp->err_info_len = sizeof(struct ErrorInfo);
8492 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 8493 cp->host_context_flags =
8494 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 8495 cp->timeout_sec = 0;
8496 cp->ReplyQueue = 0;
50a0decf 8497 cp->tag =
f2405db8 8498 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 8499 cp->host_addr =
8500 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 8501 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 8502 }
8503 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8504 u64 cfg_offset, cfg_base_addr_index;
8505 u32 bft2_offset, cfg_base_addr;
8506 int rc;
8507
8508 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
8509 &cfg_base_addr_index, &cfg_offset);
8510 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
8511 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
8512 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
8513 4, h->ioaccel2_blockFetchTable);
8514 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
8515 BUILD_BUG_ON(offsetof(struct CfgTable,
8516 io_accel_request_size_offset) != 0xb8);
8517 h->ioaccel2_bft2_regs =
8518 remap_pci_mem(pci_resource_start(h->pdev,
8519 cfg_base_addr_index) +
8520 cfg_offset + bft2_offset,
8521 ARRAY_SIZE(bft2) *
8522 sizeof(*h->ioaccel2_bft2_regs));
8523 for (i = 0; i < ARRAY_SIZE(bft2); i++)
8524 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 8525 }
b9af4937 8526 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8527 if (hpsa_wait_for_mode_change_ack(h)) {
8528 dev_err(&h->pdev->dev,
8529 "performant mode problem - enabling ioaccel mode\n");
8530 return -ENODEV;
8531 }
8532 return 0;
e1f7de0c
MG		 8533}
8534
1fb7c98a
RE		 8535/* Free ioaccel1 mode command blocks and block fetch table */
8536static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
8537{
105a3dbc 8538 if (h->ioaccel_cmd_pool) {
1fb7c98a
RE		 8539 pci_free_consistent(h->pdev,
8540 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8541 h->ioaccel_cmd_pool,
8542 h->ioaccel_cmd_pool_dhandle);
105a3dbc
RE		 8543 h->ioaccel_cmd_pool = NULL;
8544 h->ioaccel_cmd_pool_dhandle = 0;
8545 }
1fb7c98a 8546 kfree(h->ioaccel1_blockFetchTable);
105a3dbc 8547 h->ioaccel1_blockFetchTable = NULL;
1fb7c98a
RE		 8548}
8549
d37ffbe4
RE		 8550/* Allocate ioaccel1 mode command blocks and block fetch table */
8551static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 8552{
283b4a9b
SC		 8553 h->ioaccel_maxsg =
8554 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8555 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
8556 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
8557
e1f7de0c
MG		 8558 /* Command structures must be aligned on a 128-byte boundary
8559 * because the 7 lower bits of the address are used by the
8560 * hardware.
8561 */
e1f7de0c
MG		 8562 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
8563 IOACCEL1_COMMANDLIST_ALIGNMENT);
8564 h->ioaccel_cmd_pool =
8565 pci_alloc_consistent(h->pdev,
8566 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8567 &(h->ioaccel_cmd_pool_dhandle));
8568
8569 h->ioaccel1_blockFetchTable =
283b4a9b 8570 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 8571 sizeof(u32)), GFP_KERNEL);
8572
8573 if ((h->ioaccel_cmd_pool == NULL) ||
8574 (h->ioaccel1_blockFetchTable == NULL))
8575 goto clean_up;
8576
8577 memset(h->ioaccel_cmd_pool, 0,
8578 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
8579 return 0;
8580
8581clean_up:
1fb7c98a 8582 hpsa_free_ioaccel1_cmd_and_bft(h);
2dd02d74 8583 return -ENOMEM;
6c311b57
SC		 8584}
8585
1fb7c98a
RE		 8586/* Free ioaccel2 mode command blocks and block fetch table */
8587static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
8588{
d9a729f3
WS		 8589 hpsa_free_ioaccel2_sg_chain_blocks(h);
8590
105a3dbc 8591 if (h->ioaccel2_cmd_pool) {
1fb7c98a
RE		 8592 pci_free_consistent(h->pdev,
8593 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8594 h->ioaccel2_cmd_pool,
8595 h->ioaccel2_cmd_pool_dhandle);
105a3dbc
RE		 8596 h->ioaccel2_cmd_pool = NULL;
8597 h->ioaccel2_cmd_pool_dhandle = 0;
8598 }
1fb7c98a 8599 kfree(h->ioaccel2_blockFetchTable);
105a3dbc 8600 h->ioaccel2_blockFetchTable = NULL;
1fb7c98a
RE		 8601}
8602
d37ffbe4
RE		 8603/* Allocate ioaccel2 mode command blocks and block fetch table */
8604static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 8605{
d9a729f3
WS		 8606 int rc;
8607
aca9012a
SC		 8608 /* Allocate ioaccel2 mode command blocks and block fetch table */
8609
8610 h->ioaccel_maxsg =
8611 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8612 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
8613 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
8614
aca9012a
SC		 8615 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
8616 IOACCEL2_COMMANDLIST_ALIGNMENT);
8617 h->ioaccel2_cmd_pool =
8618 pci_alloc_consistent(h->pdev,
8619 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8620 &(h->ioaccel2_cmd_pool_dhandle));
8621
8622 h->ioaccel2_blockFetchTable =
8623 kmalloc(((h->ioaccel_maxsg + 1) *
8624 sizeof(u32)), GFP_KERNEL);
8625
8626 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 8627 (h->ioaccel2_blockFetchTable == NULL)) {
8628 rc = -ENOMEM;
8629 goto clean_up;
8630 }
8631
8632 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
8633 if (rc)
aca9012a
SC		 8634 goto clean_up;
8635
8636 memset(h->ioaccel2_cmd_pool, 0,
8637 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
8638 return 0;
8639
8640clean_up:
1fb7c98a 8641 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 8642 return rc;
aca9012a
SC		 8643}
8644
105a3dbc
RE		 8645/* Free items allocated by hpsa_put_ctlr_into_performant_mode */
8646static void hpsa_free_performant_mode(struct ctlr_info *h)
8647{
8648 kfree(h->blockFetchTable);
8649 h->blockFetchTable = NULL;
8650 hpsa_free_reply_queues(h);
8651 hpsa_free_ioaccel1_cmd_and_bft(h);
8652 hpsa_free_ioaccel2_cmd_and_bft(h);
8653}
8654
8655/* return -ENODEV on error, 0 on success (or no action)
8656 * allocates numerous items that must be freed later
8657 */
8658static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 8659{
8660 u32 trans_support;
e1f7de0c
MG		 8661 unsigned long transMethod = CFGTBL_Trans_Performant |
8662 CFGTBL_Trans_use_short_tags;
105a3dbc 8663 int i, rc;
6c311b57 8664
02ec19c8 8665 if (hpsa_simple_mode)
105a3dbc 8666 return 0;
02ec19c8 8667
67c99a72 8668 trans_support = readl(&(h->cfgtable->TransportSupport));
8669 if (!(trans_support & PERFORMANT_MODE))
105a3dbc 8670 return 0;
67c99a72 8671
e1f7de0c
MG		 8672 /* Check for I/O accelerator mode support */
8673 if (trans_support & CFGTBL_Trans_io_accel1) {
8674 transMethod |= CFGTBL_Trans_io_accel1 |
8675 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8676 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
8677 if (rc)
8678 return rc;
8679 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8680 transMethod |= CFGTBL_Trans_io_accel2 |
aca9012a 8681 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8682 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
8683 if (rc)
8684 return rc;
e1f7de0c
MG		 8685 }
8686
eee0f03a 8687 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 8688 hpsa_get_max_perf_mode_cmds(h);
6c311b57 8689 /* Performant mode ring buffer and supporting data structures */
072b0518 8690 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 8691
254f796b 8692 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 8693 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
8694 h->reply_queue_size,
8695 &(h->reply_queue[i].busaddr));
105a3dbc
RE		 8696 if (!h->reply_queue[i].head) {
8697 rc = -ENOMEM;
8698 goto clean1; /* rq, ioaccel */
8699 }
254f796b
MG		 8700 h->reply_queue[i].size = h->max_commands;
8701 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
8702 h->reply_queue[i].current_entry = 0;
8703 }
8704
6c311b57 8705 /* Need a block fetch table for performant mode */
d66ae08b 8706 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 8707 sizeof(u32)), GFP_KERNEL);
105a3dbc
RE		 8708 if (!h->blockFetchTable) {
8709 rc = -ENOMEM;
8710 goto clean1; /* rq, ioaccel */
8711 }
6c311b57 8712
105a3dbc
RE		 8713 rc = hpsa_enter_performant_mode(h, trans_support);
8714 if (rc)
8715 goto clean2; /* bft, rq, ioaccel */
8716 return 0;
303932fd 8717
105a3dbc 8718clean2: /* bft, rq, ioaccel */
303932fd 8719 kfree(h->blockFetchTable);
105a3dbc
RE		 8720 h->blockFetchTable = NULL;
8721clean1: /* rq, ioaccel */
8722 hpsa_free_reply_queues(h);
8723 hpsa_free_ioaccel1_cmd_and_bft(h);
8724 hpsa_free_ioaccel2_cmd_and_bft(h);
8725 return rc;
303932fd
DB		 8726}
8727
23100dd9 8728static int is_accelerated_cmd(struct CommandList *c)
76438d08 8729{
23100dd9
SC		 8730 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
8731}
8732
8733static void hpsa_drain_accel_commands(struct ctlr_info *h)
8734{
8735 struct CommandList *c = NULL;
f2405db8 8736 int i, accel_cmds_out;
281a7fd0 8737 int refcount;
76438d08 8738
f2405db8 8739 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 8740 accel_cmds_out = 0;
f2405db8 8741 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8742 c = h->cmd_pool + i;
281a7fd0
WS		 8743 refcount = atomic_inc_return(&c->refcount);
8744 if (refcount > 1) /* Command is allocated */
8745 accel_cmds_out += is_accelerated_cmd(c);
8746 cmd_free(h, c);
f2405db8 8747 }
23100dd9 8748 if (accel_cmds_out <= 0)
281a7fd0 8749 break;
76438d08
SC		 8750 msleep(100);
8751 } while (1);
8752}
8753
edd16368
SC		 8754/*
8755 * This is it. Register the PCI driver information for the cards we control
8756 * the OS will call our registered routines when it finds one of our cards.
8757 */
8758static int __init hpsa_init(void)
8759{
31468401 8760 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 8761}
8762
8763static void __exit hpsa_cleanup(void)
8764{
8765 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 8766}
8767
e1f7de0c
MG		 8768static void __attribute__((unused)) verify_offsets(void)
8769{
dd0e19f3
ST		 8770#define VERIFY_OFFSET(member, offset) \
8771 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
8772
8773 VERIFY_OFFSET(structure_size, 0);
8774 VERIFY_OFFSET(volume_blk_size, 4);
8775 VERIFY_OFFSET(volume_blk_cnt, 8);
8776 VERIFY_OFFSET(phys_blk_shift, 16);
8777 VERIFY_OFFSET(parity_rotation_shift, 17);
8778 VERIFY_OFFSET(strip_size, 18);
8779 VERIFY_OFFSET(disk_starting_blk, 20);
8780 VERIFY_OFFSET(disk_blk_cnt, 28);
8781 VERIFY_OFFSET(data_disks_per_row, 36);
8782 VERIFY_OFFSET(metadata_disks_per_row, 38);
8783 VERIFY_OFFSET(row_cnt, 40);
8784 VERIFY_OFFSET(layout_map_count, 42);
8785 VERIFY_OFFSET(flags, 44);
8786 VERIFY_OFFSET(dekindex, 46);
8787 /* VERIFY_OFFSET(reserved, 48 */
8788 VERIFY_OFFSET(data, 64);
8789
8790#undef VERIFY_OFFSET
8791
b66cc250
MM		 8792#define VERIFY_OFFSET(member, offset) \
8793 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
8794
8795 VERIFY_OFFSET(IU_type, 0);
8796 VERIFY_OFFSET(direction, 1);
8797 VERIFY_OFFSET(reply_queue, 2);
8798 /* VERIFY_OFFSET(reserved1, 3); */
8799 VERIFY_OFFSET(scsi_nexus, 4);
8800 VERIFY_OFFSET(Tag, 8);
8801 VERIFY_OFFSET(cdb, 16);
8802 VERIFY_OFFSET(cciss_lun, 32);
8803 VERIFY_OFFSET(data_len, 40);
8804 VERIFY_OFFSET(cmd_priority_task_attr, 44);
8805 VERIFY_OFFSET(sg_count, 45);
8806 /* VERIFY_OFFSET(reserved3 */
8807 VERIFY_OFFSET(err_ptr, 48);
8808 VERIFY_OFFSET(err_len, 56);
8809 /* VERIFY_OFFSET(reserved4 */
8810 VERIFY_OFFSET(sg, 64);
8811
8812#undef VERIFY_OFFSET
8813
e1f7de0c
MG		 8814#define VERIFY_OFFSET(member, offset) \
8815 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
8816
8817 VERIFY_OFFSET(dev_handle, 0x00);
8818 VERIFY_OFFSET(reserved1, 0x02);
8819 VERIFY_OFFSET(function, 0x03);
8820 VERIFY_OFFSET(reserved2, 0x04);
8821 VERIFY_OFFSET(err_info, 0x0C);
8822 VERIFY_OFFSET(reserved3, 0x10);
8823 VERIFY_OFFSET(err_info_len, 0x12);
8824 VERIFY_OFFSET(reserved4, 0x13);
8825 VERIFY_OFFSET(sgl_offset, 0x14);
8826 VERIFY_OFFSET(reserved5, 0x15);
8827 VERIFY_OFFSET(transfer_len, 0x1C);
8828 VERIFY_OFFSET(reserved6, 0x20);
8829 VERIFY_OFFSET(io_flags, 0x24);
8830 VERIFY_OFFSET(reserved7, 0x26);
8831 VERIFY_OFFSET(LUN, 0x34);
8832 VERIFY_OFFSET(control, 0x3C);
8833 VERIFY_OFFSET(CDB, 0x40);
8834 VERIFY_OFFSET(reserved8, 0x50);
8835 VERIFY_OFFSET(host_context_flags, 0x60);
8836 VERIFY_OFFSET(timeout_sec, 0x62);
8837 VERIFY_OFFSET(ReplyQueue, 0x64);
8838 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 8839 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 8840 VERIFY_OFFSET(host_addr, 0x70);
8841 VERIFY_OFFSET(CISS_LUN, 0x78);
8842 VERIFY_OFFSET(SG, 0x78 + 8);
8843#undef VERIFY_OFFSET
8844}
8845
edd16368
SC		 8846module_init(hpsa_init);
8847module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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