Commit | Line | Data |
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edd16368 SC |
1 | /* |
2 | * Disk Array driver for HP Smart Array SAS controllers | |
3 | * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; version 2 of the License. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
12 | * NON INFRINGEMENT. See the GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | * | |
18 | * Questions/Comments/Bugfixes to iss_storagedev@hp.com | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/pci.h> | |
e5a44df8 | 26 | #include <linux/pci-aspm.h> |
edd16368 SC |
27 | #include <linux/kernel.h> |
28 | #include <linux/slab.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/fs.h> | |
31 | #include <linux/timer.h> | |
edd16368 SC |
32 | #include <linux/init.h> |
33 | #include <linux/spinlock.h> | |
edd16368 SC |
34 | #include <linux/compat.h> |
35 | #include <linux/blktrace_api.h> | |
36 | #include <linux/uaccess.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/completion.h> | |
40 | #include <linux/moduleparam.h> | |
41 | #include <scsi/scsi.h> | |
42 | #include <scsi/scsi_cmnd.h> | |
43 | #include <scsi/scsi_device.h> | |
44 | #include <scsi/scsi_host.h> | |
667e23d4 | 45 | #include <scsi/scsi_tcq.h> |
edd16368 SC |
46 | #include <linux/cciss_ioctl.h> |
47 | #include <linux/string.h> | |
48 | #include <linux/bitmap.h> | |
60063497 | 49 | #include <linux/atomic.h> |
edd16368 | 50 | #include <linux/kthread.h> |
a0c12413 | 51 | #include <linux/jiffies.h> |
283b4a9b | 52 | #include <asm/div64.h> |
edd16368 SC |
53 | #include "hpsa_cmd.h" |
54 | #include "hpsa.h" | |
55 | ||
56 | /* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */ | |
e481cce8 | 57 | #define HPSA_DRIVER_VERSION "3.4.0-1" |
edd16368 | 58 | #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")" |
f79cfec6 | 59 | #define HPSA "hpsa" |
edd16368 SC |
60 | |
61 | /* How long to wait (in milliseconds) for board to go into simple mode */ | |
62 | #define MAX_CONFIG_WAIT 30000 | |
63 | #define MAX_IOCTL_CONFIG_WAIT 1000 | |
64 | ||
65 | /*define how many times we will try a command because of bus resets */ | |
66 | #define MAX_CMD_RETRIES 3 | |
67 | ||
68 | /* Embedded module documentation macros - see modules.h */ | |
69 | MODULE_AUTHOR("Hewlett-Packard Company"); | |
70 | MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \ | |
71 | HPSA_DRIVER_VERSION); | |
72 | MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers"); | |
73 | MODULE_VERSION(HPSA_DRIVER_VERSION); | |
74 | MODULE_LICENSE("GPL"); | |
75 | ||
76 | static int hpsa_allow_any; | |
77 | module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR); | |
78 | MODULE_PARM_DESC(hpsa_allow_any, | |
79 | "Allow hpsa driver to access unknown HP Smart Array hardware"); | |
02ec19c8 SC |
80 | static int hpsa_simple_mode; |
81 | module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR); | |
82 | MODULE_PARM_DESC(hpsa_simple_mode, | |
83 | "Use 'simple mode' rather than 'performant mode'"); | |
edd16368 SC |
84 | |
85 | /* define the PCI info for the cards we can control */ | |
86 | static const struct pci_device_id hpsa_pci_device_id[] = { | |
edd16368 SC |
87 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241}, |
88 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243}, | |
89 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245}, | |
90 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247}, | |
91 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249}, | |
163dbcd8 MM |
92 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A}, |
93 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B}, | |
f8b01eb9 | 94 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233}, |
9143a961 | 95 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350}, |
96 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351}, | |
97 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352}, | |
98 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353}, | |
99 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354}, | |
100 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355}, | |
101 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356}, | |
fe0c9610 MM |
102 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921}, |
103 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922}, | |
104 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923}, | |
105 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924}, | |
106 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925}, | |
107 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926}, | |
108 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928}, | |
97b9f53d MM |
109 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929}, |
110 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD}, | |
111 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE}, | |
112 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF}, | |
113 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0}, | |
114 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1}, | |
115 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2}, | |
116 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3}, | |
117 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4}, | |
118 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5}, | |
119 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7}, | |
120 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8}, | |
121 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9}, | |
7c03b870 | 122 | {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
6798cc0a | 123 | PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0}, |
edd16368 SC |
124 | {0,} |
125 | }; | |
126 | ||
127 | MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id); | |
128 | ||
129 | /* board_id = Subsystem Device ID & Vendor ID | |
130 | * product = Marketing Name for the board | |
131 | * access = Address of the struct of function pointers | |
132 | */ | |
133 | static struct board_type products[] = { | |
edd16368 SC |
134 | {0x3241103C, "Smart Array P212", &SA5_access}, |
135 | {0x3243103C, "Smart Array P410", &SA5_access}, | |
136 | {0x3245103C, "Smart Array P410i", &SA5_access}, | |
137 | {0x3247103C, "Smart Array P411", &SA5_access}, | |
138 | {0x3249103C, "Smart Array P812", &SA5_access}, | |
163dbcd8 MM |
139 | {0x324A103C, "Smart Array P712m", &SA5_access}, |
140 | {0x324B103C, "Smart Array P711m", &SA5_access}, | |
fe0c9610 MM |
141 | {0x3350103C, "Smart Array P222", &SA5_access}, |
142 | {0x3351103C, "Smart Array P420", &SA5_access}, | |
143 | {0x3352103C, "Smart Array P421", &SA5_access}, | |
144 | {0x3353103C, "Smart Array P822", &SA5_access}, | |
145 | {0x3354103C, "Smart Array P420i", &SA5_access}, | |
146 | {0x3355103C, "Smart Array P220i", &SA5_access}, | |
147 | {0x3356103C, "Smart Array P721m", &SA5_access}, | |
1fd6c8e3 MM |
148 | {0x1921103C, "Smart Array P830i", &SA5_access}, |
149 | {0x1922103C, "Smart Array P430", &SA5_access}, | |
150 | {0x1923103C, "Smart Array P431", &SA5_access}, | |
151 | {0x1924103C, "Smart Array P830", &SA5_access}, | |
152 | {0x1926103C, "Smart Array P731m", &SA5_access}, | |
153 | {0x1928103C, "Smart Array P230i", &SA5_access}, | |
154 | {0x1929103C, "Smart Array P530", &SA5_access}, | |
97b9f53d MM |
155 | {0x21BD103C, "Smart Array", &SA5_access}, |
156 | {0x21BE103C, "Smart Array", &SA5_access}, | |
157 | {0x21BF103C, "Smart Array", &SA5_access}, | |
158 | {0x21C0103C, "Smart Array", &SA5_access}, | |
159 | {0x21C1103C, "Smart Array", &SA5_access}, | |
160 | {0x21C2103C, "Smart Array", &SA5_access}, | |
161 | {0x21C3103C, "Smart Array", &SA5_access}, | |
162 | {0x21C4103C, "Smart Array", &SA5_access}, | |
163 | {0x21C5103C, "Smart Array", &SA5_access}, | |
164 | {0x21C7103C, "Smart Array", &SA5_access}, | |
165 | {0x21C8103C, "Smart Array", &SA5_access}, | |
166 | {0x21C9103C, "Smart Array", &SA5_access}, | |
edd16368 SC |
167 | {0xFFFF103C, "Unknown Smart Array", &SA5_access}, |
168 | }; | |
169 | ||
170 | static int number_of_controllers; | |
171 | ||
10f66018 SC |
172 | static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id); |
173 | static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id); | |
edd16368 SC |
174 | static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg); |
175 | static void start_io(struct ctlr_info *h); | |
176 | ||
177 | #ifdef CONFIG_COMPAT | |
178 | static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg); | |
179 | #endif | |
180 | ||
181 | static void cmd_free(struct ctlr_info *h, struct CommandList *c); | |
182 | static void cmd_special_free(struct ctlr_info *h, struct CommandList *c); | |
183 | static struct CommandList *cmd_alloc(struct ctlr_info *h); | |
184 | static struct CommandList *cmd_special_alloc(struct ctlr_info *h); | |
a2dac136 | 185 | static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, |
01a02ffc | 186 | void *buff, size_t size, u8 page_code, unsigned char *scsi3addr, |
edd16368 SC |
187 | int cmd_type); |
188 | ||
f281233d | 189 | static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd); |
a08a8471 SC |
190 | static void hpsa_scan_start(struct Scsi_Host *); |
191 | static int hpsa_scan_finished(struct Scsi_Host *sh, | |
192 | unsigned long elapsed_time); | |
667e23d4 SC |
193 | static int hpsa_change_queue_depth(struct scsi_device *sdev, |
194 | int qdepth, int reason); | |
edd16368 SC |
195 | |
196 | static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd); | |
75167d2c | 197 | static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd); |
edd16368 SC |
198 | static int hpsa_slave_alloc(struct scsi_device *sdev); |
199 | static void hpsa_slave_destroy(struct scsi_device *sdev); | |
200 | ||
edd16368 | 201 | static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno); |
edd16368 SC |
202 | static int check_for_unit_attention(struct ctlr_info *h, |
203 | struct CommandList *c); | |
204 | static void check_ioctl_unit_attention(struct ctlr_info *h, | |
205 | struct CommandList *c); | |
303932fd DB |
206 | /* performant mode helper functions */ |
207 | static void calc_bucket_map(int *bucket, int num_buckets, | |
e1f7de0c | 208 | int nsgs, int min_blocks, int *bucket_map); |
6f039790 | 209 | static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h); |
254f796b | 210 | static inline u32 next_command(struct ctlr_info *h, u8 q); |
6f039790 GKH |
211 | static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, |
212 | u32 *cfg_base_addr, u64 *cfg_base_addr_index, | |
213 | u64 *cfg_offset); | |
214 | static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, | |
215 | unsigned long *memory_bar); | |
216 | static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id); | |
217 | static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, | |
218 | int wait_for_ready); | |
75167d2c | 219 | static inline void finish_cmd(struct CommandList *c); |
283b4a9b | 220 | static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h); |
fe5389c8 SC |
221 | #define BOARD_NOT_READY 0 |
222 | #define BOARD_READY 1 | |
76438d08 SC |
223 | static void hpsa_drain_commands(struct ctlr_info *h); |
224 | static void hpsa_flush_cache(struct ctlr_info *h); | |
c349775e ST |
225 | static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, |
226 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, | |
227 | u8 *scsi3addr); | |
edd16368 | 228 | |
edd16368 SC |
229 | static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev) |
230 | { | |
231 | unsigned long *priv = shost_priv(sdev->host); | |
232 | return (struct ctlr_info *) *priv; | |
233 | } | |
234 | ||
a23513e8 SC |
235 | static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh) |
236 | { | |
237 | unsigned long *priv = shost_priv(sh); | |
238 | return (struct ctlr_info *) *priv; | |
239 | } | |
240 | ||
edd16368 SC |
241 | static int check_for_unit_attention(struct ctlr_info *h, |
242 | struct CommandList *c) | |
243 | { | |
244 | if (c->err_info->SenseInfo[2] != UNIT_ATTENTION) | |
245 | return 0; | |
246 | ||
247 | switch (c->err_info->SenseInfo[12]) { | |
248 | case STATE_CHANGED: | |
f79cfec6 | 249 | dev_warn(&h->pdev->dev, HPSA "%d: a state change " |
edd16368 SC |
250 | "detected, command retried\n", h->ctlr); |
251 | break; | |
252 | case LUN_FAILED: | |
f79cfec6 | 253 | dev_warn(&h->pdev->dev, HPSA "%d: LUN failure " |
edd16368 SC |
254 | "detected, action required\n", h->ctlr); |
255 | break; | |
256 | case REPORT_LUNS_CHANGED: | |
f79cfec6 | 257 | dev_warn(&h->pdev->dev, HPSA "%d: report LUN data " |
31468401 | 258 | "changed, action required\n", h->ctlr); |
edd16368 | 259 | /* |
4f4eb9f1 ST |
260 | * Note: this REPORT_LUNS_CHANGED condition only occurs on the external |
261 | * target (array) devices. | |
edd16368 SC |
262 | */ |
263 | break; | |
264 | case POWER_OR_RESET: | |
f79cfec6 | 265 | dev_warn(&h->pdev->dev, HPSA "%d: a power on " |
edd16368 SC |
266 | "or device reset detected\n", h->ctlr); |
267 | break; | |
268 | case UNIT_ATTENTION_CLEARED: | |
f79cfec6 | 269 | dev_warn(&h->pdev->dev, HPSA "%d: unit attention " |
edd16368 SC |
270 | "cleared by another initiator\n", h->ctlr); |
271 | break; | |
272 | default: | |
f79cfec6 | 273 | dev_warn(&h->pdev->dev, HPSA "%d: unknown " |
edd16368 SC |
274 | "unit attention detected\n", h->ctlr); |
275 | break; | |
276 | } | |
277 | return 1; | |
278 | } | |
279 | ||
852af20a MB |
280 | static int check_for_busy(struct ctlr_info *h, struct CommandList *c) |
281 | { | |
282 | if (c->err_info->CommandStatus != CMD_TARGET_STATUS || | |
283 | (c->err_info->ScsiStatus != SAM_STAT_BUSY && | |
284 | c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL)) | |
285 | return 0; | |
286 | dev_warn(&h->pdev->dev, HPSA "device busy"); | |
287 | return 1; | |
288 | } | |
289 | ||
edd16368 SC |
290 | static ssize_t host_store_rescan(struct device *dev, |
291 | struct device_attribute *attr, | |
292 | const char *buf, size_t count) | |
293 | { | |
294 | struct ctlr_info *h; | |
295 | struct Scsi_Host *shost = class_to_shost(dev); | |
a23513e8 | 296 | h = shost_to_hba(shost); |
31468401 | 297 | hpsa_scan_start(h->scsi_host); |
edd16368 SC |
298 | return count; |
299 | } | |
300 | ||
d28ce020 SC |
301 | static ssize_t host_show_firmware_revision(struct device *dev, |
302 | struct device_attribute *attr, char *buf) | |
303 | { | |
304 | struct ctlr_info *h; | |
305 | struct Scsi_Host *shost = class_to_shost(dev); | |
306 | unsigned char *fwrev; | |
307 | ||
308 | h = shost_to_hba(shost); | |
309 | if (!h->hba_inquiry_data) | |
310 | return 0; | |
311 | fwrev = &h->hba_inquiry_data[32]; | |
312 | return snprintf(buf, 20, "%c%c%c%c\n", | |
313 | fwrev[0], fwrev[1], fwrev[2], fwrev[3]); | |
314 | } | |
315 | ||
94a13649 SC |
316 | static ssize_t host_show_commands_outstanding(struct device *dev, |
317 | struct device_attribute *attr, char *buf) | |
318 | { | |
319 | struct Scsi_Host *shost = class_to_shost(dev); | |
320 | struct ctlr_info *h = shost_to_hba(shost); | |
321 | ||
322 | return snprintf(buf, 20, "%d\n", h->commands_outstanding); | |
323 | } | |
324 | ||
745a7a25 SC |
325 | static ssize_t host_show_transport_mode(struct device *dev, |
326 | struct device_attribute *attr, char *buf) | |
327 | { | |
328 | struct ctlr_info *h; | |
329 | struct Scsi_Host *shost = class_to_shost(dev); | |
330 | ||
331 | h = shost_to_hba(shost); | |
332 | return snprintf(buf, 20, "%s\n", | |
960a30e7 | 333 | h->transMethod & CFGTBL_Trans_Performant ? |
745a7a25 SC |
334 | "performant" : "simple"); |
335 | } | |
336 | ||
46380786 | 337 | /* List of controllers which cannot be hard reset on kexec with reset_devices */ |
941b1cda SC |
338 | static u32 unresettable_controller[] = { |
339 | 0x324a103C, /* Smart Array P712m */ | |
340 | 0x324b103C, /* SmartArray P711m */ | |
341 | 0x3223103C, /* Smart Array P800 */ | |
342 | 0x3234103C, /* Smart Array P400 */ | |
343 | 0x3235103C, /* Smart Array P400i */ | |
344 | 0x3211103C, /* Smart Array E200i */ | |
345 | 0x3212103C, /* Smart Array E200 */ | |
346 | 0x3213103C, /* Smart Array E200i */ | |
347 | 0x3214103C, /* Smart Array E200i */ | |
348 | 0x3215103C, /* Smart Array E200i */ | |
349 | 0x3237103C, /* Smart Array E500 */ | |
350 | 0x323D103C, /* Smart Array P700m */ | |
7af0abbc | 351 | 0x40800E11, /* Smart Array 5i */ |
941b1cda SC |
352 | 0x409C0E11, /* Smart Array 6400 */ |
353 | 0x409D0E11, /* Smart Array 6400 EM */ | |
5a4f934e TH |
354 | 0x40700E11, /* Smart Array 5300 */ |
355 | 0x40820E11, /* Smart Array 532 */ | |
356 | 0x40830E11, /* Smart Array 5312 */ | |
357 | 0x409A0E11, /* Smart Array 641 */ | |
358 | 0x409B0E11, /* Smart Array 642 */ | |
359 | 0x40910E11, /* Smart Array 6i */ | |
941b1cda SC |
360 | }; |
361 | ||
46380786 SC |
362 | /* List of controllers which cannot even be soft reset */ |
363 | static u32 soft_unresettable_controller[] = { | |
7af0abbc | 364 | 0x40800E11, /* Smart Array 5i */ |
5a4f934e TH |
365 | 0x40700E11, /* Smart Array 5300 */ |
366 | 0x40820E11, /* Smart Array 532 */ | |
367 | 0x40830E11, /* Smart Array 5312 */ | |
368 | 0x409A0E11, /* Smart Array 641 */ | |
369 | 0x409B0E11, /* Smart Array 642 */ | |
370 | 0x40910E11, /* Smart Array 6i */ | |
46380786 SC |
371 | /* Exclude 640x boards. These are two pci devices in one slot |
372 | * which share a battery backed cache module. One controls the | |
373 | * cache, the other accesses the cache through the one that controls | |
374 | * it. If we reset the one controlling the cache, the other will | |
375 | * likely not be happy. Just forbid resetting this conjoined mess. | |
376 | * The 640x isn't really supported by hpsa anyway. | |
377 | */ | |
378 | 0x409C0E11, /* Smart Array 6400 */ | |
379 | 0x409D0E11, /* Smart Array 6400 EM */ | |
380 | }; | |
381 | ||
382 | static int ctlr_is_hard_resettable(u32 board_id) | |
941b1cda SC |
383 | { |
384 | int i; | |
385 | ||
386 | for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++) | |
46380786 SC |
387 | if (unresettable_controller[i] == board_id) |
388 | return 0; | |
389 | return 1; | |
390 | } | |
391 | ||
392 | static int ctlr_is_soft_resettable(u32 board_id) | |
393 | { | |
394 | int i; | |
395 | ||
396 | for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++) | |
397 | if (soft_unresettable_controller[i] == board_id) | |
941b1cda SC |
398 | return 0; |
399 | return 1; | |
400 | } | |
401 | ||
46380786 SC |
402 | static int ctlr_is_resettable(u32 board_id) |
403 | { | |
404 | return ctlr_is_hard_resettable(board_id) || | |
405 | ctlr_is_soft_resettable(board_id); | |
406 | } | |
407 | ||
941b1cda SC |
408 | static ssize_t host_show_resettable(struct device *dev, |
409 | struct device_attribute *attr, char *buf) | |
410 | { | |
411 | struct ctlr_info *h; | |
412 | struct Scsi_Host *shost = class_to_shost(dev); | |
413 | ||
414 | h = shost_to_hba(shost); | |
46380786 | 415 | return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id)); |
941b1cda SC |
416 | } |
417 | ||
edd16368 SC |
418 | static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[]) |
419 | { | |
420 | return (scsi3addr[3] & 0xC0) == 0x40; | |
421 | } | |
422 | ||
423 | static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG", | |
d82357ea | 424 | "1(ADM)", "UNKNOWN" |
edd16368 SC |
425 | }; |
426 | #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1) | |
427 | ||
428 | static ssize_t raid_level_show(struct device *dev, | |
429 | struct device_attribute *attr, char *buf) | |
430 | { | |
431 | ssize_t l = 0; | |
82a72c0a | 432 | unsigned char rlevel; |
edd16368 SC |
433 | struct ctlr_info *h; |
434 | struct scsi_device *sdev; | |
435 | struct hpsa_scsi_dev_t *hdev; | |
436 | unsigned long flags; | |
437 | ||
438 | sdev = to_scsi_device(dev); | |
439 | h = sdev_to_hba(sdev); | |
440 | spin_lock_irqsave(&h->lock, flags); | |
441 | hdev = sdev->hostdata; | |
442 | if (!hdev) { | |
443 | spin_unlock_irqrestore(&h->lock, flags); | |
444 | return -ENODEV; | |
445 | } | |
446 | ||
447 | /* Is this even a logical drive? */ | |
448 | if (!is_logical_dev_addr_mode(hdev->scsi3addr)) { | |
449 | spin_unlock_irqrestore(&h->lock, flags); | |
450 | l = snprintf(buf, PAGE_SIZE, "N/A\n"); | |
451 | return l; | |
452 | } | |
453 | ||
454 | rlevel = hdev->raid_level; | |
455 | spin_unlock_irqrestore(&h->lock, flags); | |
82a72c0a | 456 | if (rlevel > RAID_UNKNOWN) |
edd16368 SC |
457 | rlevel = RAID_UNKNOWN; |
458 | l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]); | |
459 | return l; | |
460 | } | |
461 | ||
462 | static ssize_t lunid_show(struct device *dev, | |
463 | struct device_attribute *attr, char *buf) | |
464 | { | |
465 | struct ctlr_info *h; | |
466 | struct scsi_device *sdev; | |
467 | struct hpsa_scsi_dev_t *hdev; | |
468 | unsigned long flags; | |
469 | unsigned char lunid[8]; | |
470 | ||
471 | sdev = to_scsi_device(dev); | |
472 | h = sdev_to_hba(sdev); | |
473 | spin_lock_irqsave(&h->lock, flags); | |
474 | hdev = sdev->hostdata; | |
475 | if (!hdev) { | |
476 | spin_unlock_irqrestore(&h->lock, flags); | |
477 | return -ENODEV; | |
478 | } | |
479 | memcpy(lunid, hdev->scsi3addr, sizeof(lunid)); | |
480 | spin_unlock_irqrestore(&h->lock, flags); | |
481 | return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
482 | lunid[0], lunid[1], lunid[2], lunid[3], | |
483 | lunid[4], lunid[5], lunid[6], lunid[7]); | |
484 | } | |
485 | ||
486 | static ssize_t unique_id_show(struct device *dev, | |
487 | struct device_attribute *attr, char *buf) | |
488 | { | |
489 | struct ctlr_info *h; | |
490 | struct scsi_device *sdev; | |
491 | struct hpsa_scsi_dev_t *hdev; | |
492 | unsigned long flags; | |
493 | unsigned char sn[16]; | |
494 | ||
495 | sdev = to_scsi_device(dev); | |
496 | h = sdev_to_hba(sdev); | |
497 | spin_lock_irqsave(&h->lock, flags); | |
498 | hdev = sdev->hostdata; | |
499 | if (!hdev) { | |
500 | spin_unlock_irqrestore(&h->lock, flags); | |
501 | return -ENODEV; | |
502 | } | |
503 | memcpy(sn, hdev->device_id, sizeof(sn)); | |
504 | spin_unlock_irqrestore(&h->lock, flags); | |
505 | return snprintf(buf, 16 * 2 + 2, | |
506 | "%02X%02X%02X%02X%02X%02X%02X%02X" | |
507 | "%02X%02X%02X%02X%02X%02X%02X%02X\n", | |
508 | sn[0], sn[1], sn[2], sn[3], | |
509 | sn[4], sn[5], sn[6], sn[7], | |
510 | sn[8], sn[9], sn[10], sn[11], | |
511 | sn[12], sn[13], sn[14], sn[15]); | |
512 | } | |
513 | ||
c1988684 ST |
514 | static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev, |
515 | struct device_attribute *attr, char *buf) | |
516 | { | |
517 | struct ctlr_info *h; | |
518 | struct scsi_device *sdev; | |
519 | struct hpsa_scsi_dev_t *hdev; | |
520 | unsigned long flags; | |
521 | int offload_enabled; | |
522 | ||
523 | sdev = to_scsi_device(dev); | |
524 | h = sdev_to_hba(sdev); | |
525 | spin_lock_irqsave(&h->lock, flags); | |
526 | hdev = sdev->hostdata; | |
527 | if (!hdev) { | |
528 | spin_unlock_irqrestore(&h->lock, flags); | |
529 | return -ENODEV; | |
530 | } | |
531 | offload_enabled = hdev->offload_enabled; | |
532 | spin_unlock_irqrestore(&h->lock, flags); | |
533 | return snprintf(buf, 20, "%d\n", offload_enabled); | |
534 | } | |
535 | ||
3f5eac3a SC |
536 | static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL); |
537 | static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL); | |
538 | static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL); | |
539 | static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan); | |
c1988684 ST |
540 | static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO, |
541 | host_show_hp_ssd_smart_path_enabled, NULL); | |
3f5eac3a SC |
542 | static DEVICE_ATTR(firmware_revision, S_IRUGO, |
543 | host_show_firmware_revision, NULL); | |
544 | static DEVICE_ATTR(commands_outstanding, S_IRUGO, | |
545 | host_show_commands_outstanding, NULL); | |
546 | static DEVICE_ATTR(transport_mode, S_IRUGO, | |
547 | host_show_transport_mode, NULL); | |
941b1cda SC |
548 | static DEVICE_ATTR(resettable, S_IRUGO, |
549 | host_show_resettable, NULL); | |
3f5eac3a SC |
550 | |
551 | static struct device_attribute *hpsa_sdev_attrs[] = { | |
552 | &dev_attr_raid_level, | |
553 | &dev_attr_lunid, | |
554 | &dev_attr_unique_id, | |
c1988684 | 555 | &dev_attr_hp_ssd_smart_path_enabled, |
3f5eac3a SC |
556 | NULL, |
557 | }; | |
558 | ||
559 | static struct device_attribute *hpsa_shost_attrs[] = { | |
560 | &dev_attr_rescan, | |
561 | &dev_attr_firmware_revision, | |
562 | &dev_attr_commands_outstanding, | |
563 | &dev_attr_transport_mode, | |
941b1cda | 564 | &dev_attr_resettable, |
3f5eac3a SC |
565 | NULL, |
566 | }; | |
567 | ||
568 | static struct scsi_host_template hpsa_driver_template = { | |
569 | .module = THIS_MODULE, | |
f79cfec6 SC |
570 | .name = HPSA, |
571 | .proc_name = HPSA, | |
3f5eac3a SC |
572 | .queuecommand = hpsa_scsi_queue_command, |
573 | .scan_start = hpsa_scan_start, | |
574 | .scan_finished = hpsa_scan_finished, | |
575 | .change_queue_depth = hpsa_change_queue_depth, | |
576 | .this_id = -1, | |
577 | .use_clustering = ENABLE_CLUSTERING, | |
75167d2c | 578 | .eh_abort_handler = hpsa_eh_abort_handler, |
3f5eac3a SC |
579 | .eh_device_reset_handler = hpsa_eh_device_reset_handler, |
580 | .ioctl = hpsa_ioctl, | |
581 | .slave_alloc = hpsa_slave_alloc, | |
582 | .slave_destroy = hpsa_slave_destroy, | |
583 | #ifdef CONFIG_COMPAT | |
584 | .compat_ioctl = hpsa_compat_ioctl, | |
585 | #endif | |
586 | .sdev_attrs = hpsa_sdev_attrs, | |
587 | .shost_attrs = hpsa_shost_attrs, | |
c0d6a4d1 | 588 | .max_sectors = 8192, |
54b2b50c | 589 | .no_write_same = 1, |
3f5eac3a SC |
590 | }; |
591 | ||
592 | ||
593 | /* Enqueuing and dequeuing functions for cmdlists. */ | |
594 | static inline void addQ(struct list_head *list, struct CommandList *c) | |
595 | { | |
596 | list_add_tail(&c->list, list); | |
597 | } | |
598 | ||
254f796b | 599 | static inline u32 next_command(struct ctlr_info *h, u8 q) |
3f5eac3a SC |
600 | { |
601 | u32 a; | |
254f796b | 602 | struct reply_pool *rq = &h->reply_queue[q]; |
e16a33ad | 603 | unsigned long flags; |
3f5eac3a | 604 | |
e1f7de0c MG |
605 | if (h->transMethod & CFGTBL_Trans_io_accel1) |
606 | return h->access.command_completed(h, q); | |
607 | ||
3f5eac3a | 608 | if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant))) |
254f796b | 609 | return h->access.command_completed(h, q); |
3f5eac3a | 610 | |
254f796b MG |
611 | if ((rq->head[rq->current_entry] & 1) == rq->wraparound) { |
612 | a = rq->head[rq->current_entry]; | |
613 | rq->current_entry++; | |
e16a33ad | 614 | spin_lock_irqsave(&h->lock, flags); |
3f5eac3a | 615 | h->commands_outstanding--; |
e16a33ad | 616 | spin_unlock_irqrestore(&h->lock, flags); |
3f5eac3a SC |
617 | } else { |
618 | a = FIFO_EMPTY; | |
619 | } | |
620 | /* Check for wraparound */ | |
254f796b MG |
621 | if (rq->current_entry == h->max_commands) { |
622 | rq->current_entry = 0; | |
623 | rq->wraparound ^= 1; | |
3f5eac3a SC |
624 | } |
625 | return a; | |
626 | } | |
627 | ||
c349775e ST |
628 | /* |
629 | * There are some special bits in the bus address of the | |
630 | * command that we have to set for the controller to know | |
631 | * how to process the command: | |
632 | * | |
633 | * Normal performant mode: | |
634 | * bit 0: 1 means performant mode, 0 means simple mode. | |
635 | * bits 1-3 = block fetch table entry | |
636 | * bits 4-6 = command type (== 0) | |
637 | * | |
638 | * ioaccel1 mode: | |
639 | * bit 0 = "performant mode" bit. | |
640 | * bits 1-3 = block fetch table entry | |
641 | * bits 4-6 = command type (== 110) | |
642 | * (command type is needed because ioaccel1 mode | |
643 | * commands are submitted through the same register as normal | |
644 | * mode commands, so this is how the controller knows whether | |
645 | * the command is normal mode or ioaccel1 mode.) | |
646 | * | |
647 | * ioaccel2 mode: | |
648 | * bit 0 = "performant mode" bit. | |
649 | * bits 1-4 = block fetch table entry (note extra bit) | |
650 | * bits 4-6 = not needed, because ioaccel2 mode has | |
651 | * a separate special register for submitting commands. | |
652 | */ | |
653 | ||
3f5eac3a SC |
654 | /* set_performant_mode: Modify the tag for cciss performant |
655 | * set bit 0 for pull model, bits 3-1 for block fetch | |
656 | * register number | |
657 | */ | |
658 | static void set_performant_mode(struct ctlr_info *h, struct CommandList *c) | |
659 | { | |
254f796b | 660 | if (likely(h->transMethod & CFGTBL_Trans_Performant)) { |
3f5eac3a | 661 | c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1); |
eee0f03a | 662 | if (likely(h->msix_vector > 0)) |
254f796b | 663 | c->Header.ReplyQueue = |
804a5cb5 | 664 | raw_smp_processor_id() % h->nreply_queues; |
254f796b | 665 | } |
3f5eac3a SC |
666 | } |
667 | ||
c349775e ST |
668 | static void set_ioaccel1_performant_mode(struct ctlr_info *h, |
669 | struct CommandList *c) | |
670 | { | |
671 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; | |
672 | ||
673 | /* Tell the controller to post the reply to the queue for this | |
674 | * processor. This seems to give the best I/O throughput. | |
675 | */ | |
676 | cp->ReplyQueue = smp_processor_id() % h->nreply_queues; | |
677 | /* Set the bits in the address sent down to include: | |
678 | * - performant mode bit (bit 0) | |
679 | * - pull count (bits 1-3) | |
680 | * - command type (bits 4-6) | |
681 | */ | |
682 | c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) | | |
683 | IOACCEL1_BUSADDR_CMDTYPE; | |
684 | } | |
685 | ||
686 | static void set_ioaccel2_performant_mode(struct ctlr_info *h, | |
687 | struct CommandList *c) | |
688 | { | |
689 | struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
690 | ||
691 | /* Tell the controller to post the reply to the queue for this | |
692 | * processor. This seems to give the best I/O throughput. | |
693 | */ | |
694 | cp->reply_queue = smp_processor_id() % h->nreply_queues; | |
695 | /* Set the bits in the address sent down to include: | |
696 | * - performant mode bit not used in ioaccel mode 2 | |
697 | * - pull count (bits 0-3) | |
698 | * - command type isn't needed for ioaccel2 | |
699 | */ | |
700 | c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]); | |
701 | } | |
702 | ||
e85c5974 SC |
703 | static int is_firmware_flash_cmd(u8 *cdb) |
704 | { | |
705 | return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE; | |
706 | } | |
707 | ||
708 | /* | |
709 | * During firmware flash, the heartbeat register may not update as frequently | |
710 | * as it should. So we dial down lockup detection during firmware flash. and | |
711 | * dial it back up when firmware flash completes. | |
712 | */ | |
713 | #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ) | |
714 | #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ) | |
715 | static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h, | |
716 | struct CommandList *c) | |
717 | { | |
718 | if (!is_firmware_flash_cmd(c->Request.CDB)) | |
719 | return; | |
720 | atomic_inc(&h->firmware_flash_in_progress); | |
721 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH; | |
722 | } | |
723 | ||
724 | static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h, | |
725 | struct CommandList *c) | |
726 | { | |
727 | if (is_firmware_flash_cmd(c->Request.CDB) && | |
728 | atomic_dec_and_test(&h->firmware_flash_in_progress)) | |
729 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; | |
730 | } | |
731 | ||
3f5eac3a SC |
732 | static void enqueue_cmd_and_start_io(struct ctlr_info *h, |
733 | struct CommandList *c) | |
734 | { | |
735 | unsigned long flags; | |
736 | ||
c349775e ST |
737 | switch (c->cmd_type) { |
738 | case CMD_IOACCEL1: | |
739 | set_ioaccel1_performant_mode(h, c); | |
740 | break; | |
741 | case CMD_IOACCEL2: | |
742 | set_ioaccel2_performant_mode(h, c); | |
743 | break; | |
744 | default: | |
745 | set_performant_mode(h, c); | |
746 | } | |
e85c5974 | 747 | dial_down_lockup_detection_during_fw_flash(h, c); |
3f5eac3a SC |
748 | spin_lock_irqsave(&h->lock, flags); |
749 | addQ(&h->reqQ, c); | |
750 | h->Qdepth++; | |
3f5eac3a | 751 | spin_unlock_irqrestore(&h->lock, flags); |
e16a33ad | 752 | start_io(h); |
3f5eac3a SC |
753 | } |
754 | ||
755 | static inline void removeQ(struct CommandList *c) | |
756 | { | |
757 | if (WARN_ON(list_empty(&c->list))) | |
758 | return; | |
759 | list_del_init(&c->list); | |
760 | } | |
761 | ||
762 | static inline int is_hba_lunid(unsigned char scsi3addr[]) | |
763 | { | |
764 | return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0; | |
765 | } | |
766 | ||
767 | static inline int is_scsi_rev_5(struct ctlr_info *h) | |
768 | { | |
769 | if (!h->hba_inquiry_data) | |
770 | return 0; | |
771 | if ((h->hba_inquiry_data[2] & 0x07) == 5) | |
772 | return 1; | |
773 | return 0; | |
774 | } | |
775 | ||
edd16368 SC |
776 | static int hpsa_find_target_lun(struct ctlr_info *h, |
777 | unsigned char scsi3addr[], int bus, int *target, int *lun) | |
778 | { | |
779 | /* finds an unused bus, target, lun for a new physical device | |
780 | * assumes h->devlock is held | |
781 | */ | |
782 | int i, found = 0; | |
cfe5badc | 783 | DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES); |
edd16368 | 784 | |
263d9401 | 785 | bitmap_zero(lun_taken, HPSA_MAX_DEVICES); |
edd16368 SC |
786 | |
787 | for (i = 0; i < h->ndevices; i++) { | |
788 | if (h->dev[i]->bus == bus && h->dev[i]->target != -1) | |
263d9401 | 789 | __set_bit(h->dev[i]->target, lun_taken); |
edd16368 SC |
790 | } |
791 | ||
263d9401 AM |
792 | i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES); |
793 | if (i < HPSA_MAX_DEVICES) { | |
794 | /* *bus = 1; */ | |
795 | *target = i; | |
796 | *lun = 0; | |
797 | found = 1; | |
edd16368 SC |
798 | } |
799 | return !found; | |
800 | } | |
801 | ||
802 | /* Add an entry into h->dev[] array. */ | |
803 | static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno, | |
804 | struct hpsa_scsi_dev_t *device, | |
805 | struct hpsa_scsi_dev_t *added[], int *nadded) | |
806 | { | |
807 | /* assumes h->devlock is held */ | |
808 | int n = h->ndevices; | |
809 | int i; | |
810 | unsigned char addr1[8], addr2[8]; | |
811 | struct hpsa_scsi_dev_t *sd; | |
812 | ||
cfe5badc | 813 | if (n >= HPSA_MAX_DEVICES) { |
edd16368 SC |
814 | dev_err(&h->pdev->dev, "too many devices, some will be " |
815 | "inaccessible.\n"); | |
816 | return -1; | |
817 | } | |
818 | ||
819 | /* physical devices do not have lun or target assigned until now. */ | |
820 | if (device->lun != -1) | |
821 | /* Logical device, lun is already assigned. */ | |
822 | goto lun_assigned; | |
823 | ||
824 | /* If this device a non-zero lun of a multi-lun device | |
825 | * byte 4 of the 8-byte LUN addr will contain the logical | |
826 | * unit no, zero otherise. | |
827 | */ | |
828 | if (device->scsi3addr[4] == 0) { | |
829 | /* This is not a non-zero lun of a multi-lun device */ | |
830 | if (hpsa_find_target_lun(h, device->scsi3addr, | |
831 | device->bus, &device->target, &device->lun) != 0) | |
832 | return -1; | |
833 | goto lun_assigned; | |
834 | } | |
835 | ||
836 | /* This is a non-zero lun of a multi-lun device. | |
837 | * Search through our list and find the device which | |
838 | * has the same 8 byte LUN address, excepting byte 4. | |
839 | * Assign the same bus and target for this new LUN. | |
840 | * Use the logical unit number from the firmware. | |
841 | */ | |
842 | memcpy(addr1, device->scsi3addr, 8); | |
843 | addr1[4] = 0; | |
844 | for (i = 0; i < n; i++) { | |
845 | sd = h->dev[i]; | |
846 | memcpy(addr2, sd->scsi3addr, 8); | |
847 | addr2[4] = 0; | |
848 | /* differ only in byte 4? */ | |
849 | if (memcmp(addr1, addr2, 8) == 0) { | |
850 | device->bus = sd->bus; | |
851 | device->target = sd->target; | |
852 | device->lun = device->scsi3addr[4]; | |
853 | break; | |
854 | } | |
855 | } | |
856 | if (device->lun == -1) { | |
857 | dev_warn(&h->pdev->dev, "physical device with no LUN=0," | |
858 | " suspect firmware bug or unsupported hardware " | |
859 | "configuration.\n"); | |
860 | return -1; | |
861 | } | |
862 | ||
863 | lun_assigned: | |
864 | ||
865 | h->dev[n] = device; | |
866 | h->ndevices++; | |
867 | added[*nadded] = device; | |
868 | (*nadded)++; | |
869 | ||
870 | /* initially, (before registering with scsi layer) we don't | |
871 | * know our hostno and we don't want to print anything first | |
872 | * time anyway (the scsi layer's inquiries will show that info) | |
873 | */ | |
874 | /* if (hostno != -1) */ | |
875 | dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n", | |
876 | scsi_device_type(device->devtype), hostno, | |
877 | device->bus, device->target, device->lun); | |
878 | return 0; | |
879 | } | |
880 | ||
bd9244f7 ST |
881 | /* Update an entry in h->dev[] array. */ |
882 | static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno, | |
883 | int entry, struct hpsa_scsi_dev_t *new_entry) | |
884 | { | |
885 | /* assumes h->devlock is held */ | |
886 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); | |
887 | ||
888 | /* Raid level changed. */ | |
889 | h->dev[entry]->raid_level = new_entry->raid_level; | |
250fb125 SC |
890 | |
891 | /* Raid offload parameters changed. */ | |
892 | h->dev[entry]->offload_config = new_entry->offload_config; | |
893 | h->dev[entry]->offload_enabled = new_entry->offload_enabled; | |
894 | ||
bd9244f7 ST |
895 | dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n", |
896 | scsi_device_type(new_entry->devtype), hostno, new_entry->bus, | |
897 | new_entry->target, new_entry->lun); | |
898 | } | |
899 | ||
2a8ccf31 SC |
900 | /* Replace an entry from h->dev[] array. */ |
901 | static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno, | |
902 | int entry, struct hpsa_scsi_dev_t *new_entry, | |
903 | struct hpsa_scsi_dev_t *added[], int *nadded, | |
904 | struct hpsa_scsi_dev_t *removed[], int *nremoved) | |
905 | { | |
906 | /* assumes h->devlock is held */ | |
cfe5badc | 907 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); |
2a8ccf31 SC |
908 | removed[*nremoved] = h->dev[entry]; |
909 | (*nremoved)++; | |
01350d05 SC |
910 | |
911 | /* | |
912 | * New physical devices won't have target/lun assigned yet | |
913 | * so we need to preserve the values in the slot we are replacing. | |
914 | */ | |
915 | if (new_entry->target == -1) { | |
916 | new_entry->target = h->dev[entry]->target; | |
917 | new_entry->lun = h->dev[entry]->lun; | |
918 | } | |
919 | ||
2a8ccf31 SC |
920 | h->dev[entry] = new_entry; |
921 | added[*nadded] = new_entry; | |
922 | (*nadded)++; | |
923 | dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n", | |
924 | scsi_device_type(new_entry->devtype), hostno, new_entry->bus, | |
925 | new_entry->target, new_entry->lun); | |
926 | } | |
927 | ||
edd16368 SC |
928 | /* Remove an entry from h->dev[] array. */ |
929 | static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry, | |
930 | struct hpsa_scsi_dev_t *removed[], int *nremoved) | |
931 | { | |
932 | /* assumes h->devlock is held */ | |
933 | int i; | |
934 | struct hpsa_scsi_dev_t *sd; | |
935 | ||
cfe5badc | 936 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); |
edd16368 SC |
937 | |
938 | sd = h->dev[entry]; | |
939 | removed[*nremoved] = h->dev[entry]; | |
940 | (*nremoved)++; | |
941 | ||
942 | for (i = entry; i < h->ndevices-1; i++) | |
943 | h->dev[i] = h->dev[i+1]; | |
944 | h->ndevices--; | |
945 | dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n", | |
946 | scsi_device_type(sd->devtype), hostno, sd->bus, sd->target, | |
947 | sd->lun); | |
948 | } | |
949 | ||
950 | #define SCSI3ADDR_EQ(a, b) ( \ | |
951 | (a)[7] == (b)[7] && \ | |
952 | (a)[6] == (b)[6] && \ | |
953 | (a)[5] == (b)[5] && \ | |
954 | (a)[4] == (b)[4] && \ | |
955 | (a)[3] == (b)[3] && \ | |
956 | (a)[2] == (b)[2] && \ | |
957 | (a)[1] == (b)[1] && \ | |
958 | (a)[0] == (b)[0]) | |
959 | ||
960 | static void fixup_botched_add(struct ctlr_info *h, | |
961 | struct hpsa_scsi_dev_t *added) | |
962 | { | |
963 | /* called when scsi_add_device fails in order to re-adjust | |
964 | * h->dev[] to match the mid layer's view. | |
965 | */ | |
966 | unsigned long flags; | |
967 | int i, j; | |
968 | ||
969 | spin_lock_irqsave(&h->lock, flags); | |
970 | for (i = 0; i < h->ndevices; i++) { | |
971 | if (h->dev[i] == added) { | |
972 | for (j = i; j < h->ndevices-1; j++) | |
973 | h->dev[j] = h->dev[j+1]; | |
974 | h->ndevices--; | |
975 | break; | |
976 | } | |
977 | } | |
978 | spin_unlock_irqrestore(&h->lock, flags); | |
979 | kfree(added); | |
980 | } | |
981 | ||
982 | static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1, | |
983 | struct hpsa_scsi_dev_t *dev2) | |
984 | { | |
edd16368 SC |
985 | /* we compare everything except lun and target as these |
986 | * are not yet assigned. Compare parts likely | |
987 | * to differ first | |
988 | */ | |
989 | if (memcmp(dev1->scsi3addr, dev2->scsi3addr, | |
990 | sizeof(dev1->scsi3addr)) != 0) | |
991 | return 0; | |
992 | if (memcmp(dev1->device_id, dev2->device_id, | |
993 | sizeof(dev1->device_id)) != 0) | |
994 | return 0; | |
995 | if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0) | |
996 | return 0; | |
997 | if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0) | |
998 | return 0; | |
edd16368 SC |
999 | if (dev1->devtype != dev2->devtype) |
1000 | return 0; | |
edd16368 SC |
1001 | if (dev1->bus != dev2->bus) |
1002 | return 0; | |
1003 | return 1; | |
1004 | } | |
1005 | ||
bd9244f7 ST |
1006 | static inline int device_updated(struct hpsa_scsi_dev_t *dev1, |
1007 | struct hpsa_scsi_dev_t *dev2) | |
1008 | { | |
1009 | /* Device attributes that can change, but don't mean | |
1010 | * that the device is a different device, nor that the OS | |
1011 | * needs to be told anything about the change. | |
1012 | */ | |
1013 | if (dev1->raid_level != dev2->raid_level) | |
1014 | return 1; | |
250fb125 SC |
1015 | if (dev1->offload_config != dev2->offload_config) |
1016 | return 1; | |
1017 | if (dev1->offload_enabled != dev2->offload_enabled) | |
1018 | return 1; | |
bd9244f7 ST |
1019 | return 0; |
1020 | } | |
1021 | ||
edd16368 SC |
1022 | /* Find needle in haystack. If exact match found, return DEVICE_SAME, |
1023 | * and return needle location in *index. If scsi3addr matches, but not | |
1024 | * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle | |
bd9244f7 ST |
1025 | * location in *index. |
1026 | * In the case of a minor device attribute change, such as RAID level, just | |
1027 | * return DEVICE_UPDATED, along with the updated device's location in index. | |
1028 | * If needle not found, return DEVICE_NOT_FOUND. | |
edd16368 SC |
1029 | */ |
1030 | static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle, | |
1031 | struct hpsa_scsi_dev_t *haystack[], int haystack_size, | |
1032 | int *index) | |
1033 | { | |
1034 | int i; | |
1035 | #define DEVICE_NOT_FOUND 0 | |
1036 | #define DEVICE_CHANGED 1 | |
1037 | #define DEVICE_SAME 2 | |
bd9244f7 | 1038 | #define DEVICE_UPDATED 3 |
edd16368 | 1039 | for (i = 0; i < haystack_size; i++) { |
23231048 SC |
1040 | if (haystack[i] == NULL) /* previously removed. */ |
1041 | continue; | |
edd16368 SC |
1042 | if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) { |
1043 | *index = i; | |
bd9244f7 ST |
1044 | if (device_is_the_same(needle, haystack[i])) { |
1045 | if (device_updated(needle, haystack[i])) | |
1046 | return DEVICE_UPDATED; | |
edd16368 | 1047 | return DEVICE_SAME; |
bd9244f7 | 1048 | } else { |
edd16368 | 1049 | return DEVICE_CHANGED; |
bd9244f7 | 1050 | } |
edd16368 SC |
1051 | } |
1052 | } | |
1053 | *index = -1; | |
1054 | return DEVICE_NOT_FOUND; | |
1055 | } | |
1056 | ||
4967bd3e | 1057 | static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno, |
edd16368 SC |
1058 | struct hpsa_scsi_dev_t *sd[], int nsds) |
1059 | { | |
1060 | /* sd contains scsi3 addresses and devtypes, and inquiry | |
1061 | * data. This function takes what's in sd to be the current | |
1062 | * reality and updates h->dev[] to reflect that reality. | |
1063 | */ | |
1064 | int i, entry, device_change, changes = 0; | |
1065 | struct hpsa_scsi_dev_t *csd; | |
1066 | unsigned long flags; | |
1067 | struct hpsa_scsi_dev_t **added, **removed; | |
1068 | int nadded, nremoved; | |
1069 | struct Scsi_Host *sh = NULL; | |
1070 | ||
cfe5badc ST |
1071 | added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL); |
1072 | removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL); | |
edd16368 SC |
1073 | |
1074 | if (!added || !removed) { | |
1075 | dev_warn(&h->pdev->dev, "out of memory in " | |
1076 | "adjust_hpsa_scsi_table\n"); | |
1077 | goto free_and_out; | |
1078 | } | |
1079 | ||
1080 | spin_lock_irqsave(&h->devlock, flags); | |
1081 | ||
1082 | /* find any devices in h->dev[] that are not in | |
1083 | * sd[] and remove them from h->dev[], and for any | |
1084 | * devices which have changed, remove the old device | |
1085 | * info and add the new device info. | |
bd9244f7 ST |
1086 | * If minor device attributes change, just update |
1087 | * the existing device structure. | |
edd16368 SC |
1088 | */ |
1089 | i = 0; | |
1090 | nremoved = 0; | |
1091 | nadded = 0; | |
1092 | while (i < h->ndevices) { | |
1093 | csd = h->dev[i]; | |
1094 | device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry); | |
1095 | if (device_change == DEVICE_NOT_FOUND) { | |
1096 | changes++; | |
1097 | hpsa_scsi_remove_entry(h, hostno, i, | |
1098 | removed, &nremoved); | |
1099 | continue; /* remove ^^^, hence i not incremented */ | |
1100 | } else if (device_change == DEVICE_CHANGED) { | |
1101 | changes++; | |
2a8ccf31 SC |
1102 | hpsa_scsi_replace_entry(h, hostno, i, sd[entry], |
1103 | added, &nadded, removed, &nremoved); | |
c7f172dc SC |
1104 | /* Set it to NULL to prevent it from being freed |
1105 | * at the bottom of hpsa_update_scsi_devices() | |
1106 | */ | |
1107 | sd[entry] = NULL; | |
bd9244f7 ST |
1108 | } else if (device_change == DEVICE_UPDATED) { |
1109 | hpsa_scsi_update_entry(h, hostno, i, sd[entry]); | |
edd16368 SC |
1110 | } |
1111 | i++; | |
1112 | } | |
1113 | ||
1114 | /* Now, make sure every device listed in sd[] is also | |
1115 | * listed in h->dev[], adding them if they aren't found | |
1116 | */ | |
1117 | ||
1118 | for (i = 0; i < nsds; i++) { | |
1119 | if (!sd[i]) /* if already added above. */ | |
1120 | continue; | |
1121 | device_change = hpsa_scsi_find_entry(sd[i], h->dev, | |
1122 | h->ndevices, &entry); | |
1123 | if (device_change == DEVICE_NOT_FOUND) { | |
1124 | changes++; | |
1125 | if (hpsa_scsi_add_entry(h, hostno, sd[i], | |
1126 | added, &nadded) != 0) | |
1127 | break; | |
1128 | sd[i] = NULL; /* prevent from being freed later. */ | |
1129 | } else if (device_change == DEVICE_CHANGED) { | |
1130 | /* should never happen... */ | |
1131 | changes++; | |
1132 | dev_warn(&h->pdev->dev, | |
1133 | "device unexpectedly changed.\n"); | |
1134 | /* but if it does happen, we just ignore that device */ | |
1135 | } | |
1136 | } | |
1137 | spin_unlock_irqrestore(&h->devlock, flags); | |
1138 | ||
1139 | /* Don't notify scsi mid layer of any changes the first time through | |
1140 | * (or if there are no changes) scsi_scan_host will do it later the | |
1141 | * first time through. | |
1142 | */ | |
1143 | if (hostno == -1 || !changes) | |
1144 | goto free_and_out; | |
1145 | ||
1146 | sh = h->scsi_host; | |
1147 | /* Notify scsi mid layer of any removed devices */ | |
1148 | for (i = 0; i < nremoved; i++) { | |
1149 | struct scsi_device *sdev = | |
1150 | scsi_device_lookup(sh, removed[i]->bus, | |
1151 | removed[i]->target, removed[i]->lun); | |
1152 | if (sdev != NULL) { | |
1153 | scsi_remove_device(sdev); | |
1154 | scsi_device_put(sdev); | |
1155 | } else { | |
1156 | /* We don't expect to get here. | |
1157 | * future cmds to this device will get selection | |
1158 | * timeout as if the device was gone. | |
1159 | */ | |
1160 | dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d " | |
1161 | " for removal.", hostno, removed[i]->bus, | |
1162 | removed[i]->target, removed[i]->lun); | |
1163 | } | |
1164 | kfree(removed[i]); | |
1165 | removed[i] = NULL; | |
1166 | } | |
1167 | ||
1168 | /* Notify scsi mid layer of any added devices */ | |
1169 | for (i = 0; i < nadded; i++) { | |
1170 | if (scsi_add_device(sh, added[i]->bus, | |
1171 | added[i]->target, added[i]->lun) == 0) | |
1172 | continue; | |
1173 | dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, " | |
1174 | "device not added.\n", hostno, added[i]->bus, | |
1175 | added[i]->target, added[i]->lun); | |
1176 | /* now we have to remove it from h->dev, | |
1177 | * since it didn't get added to scsi mid layer | |
1178 | */ | |
1179 | fixup_botched_add(h, added[i]); | |
1180 | } | |
1181 | ||
1182 | free_and_out: | |
1183 | kfree(added); | |
1184 | kfree(removed); | |
edd16368 SC |
1185 | } |
1186 | ||
1187 | /* | |
9e03aa2f | 1188 | * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t * |
edd16368 SC |
1189 | * Assume's h->devlock is held. |
1190 | */ | |
1191 | static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h, | |
1192 | int bus, int target, int lun) | |
1193 | { | |
1194 | int i; | |
1195 | struct hpsa_scsi_dev_t *sd; | |
1196 | ||
1197 | for (i = 0; i < h->ndevices; i++) { | |
1198 | sd = h->dev[i]; | |
1199 | if (sd->bus == bus && sd->target == target && sd->lun == lun) | |
1200 | return sd; | |
1201 | } | |
1202 | return NULL; | |
1203 | } | |
1204 | ||
1205 | /* link sdev->hostdata to our per-device structure. */ | |
1206 | static int hpsa_slave_alloc(struct scsi_device *sdev) | |
1207 | { | |
1208 | struct hpsa_scsi_dev_t *sd; | |
1209 | unsigned long flags; | |
1210 | struct ctlr_info *h; | |
1211 | ||
1212 | h = sdev_to_hba(sdev); | |
1213 | spin_lock_irqsave(&h->devlock, flags); | |
1214 | sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev), | |
1215 | sdev_id(sdev), sdev->lun); | |
1216 | if (sd != NULL) | |
1217 | sdev->hostdata = sd; | |
1218 | spin_unlock_irqrestore(&h->devlock, flags); | |
1219 | return 0; | |
1220 | } | |
1221 | ||
1222 | static void hpsa_slave_destroy(struct scsi_device *sdev) | |
1223 | { | |
bcc44255 | 1224 | /* nothing to do. */ |
edd16368 SC |
1225 | } |
1226 | ||
33a2ffce SC |
1227 | static void hpsa_free_sg_chain_blocks(struct ctlr_info *h) |
1228 | { | |
1229 | int i; | |
1230 | ||
1231 | if (!h->cmd_sg_list) | |
1232 | return; | |
1233 | for (i = 0; i < h->nr_cmds; i++) { | |
1234 | kfree(h->cmd_sg_list[i]); | |
1235 | h->cmd_sg_list[i] = NULL; | |
1236 | } | |
1237 | kfree(h->cmd_sg_list); | |
1238 | h->cmd_sg_list = NULL; | |
1239 | } | |
1240 | ||
1241 | static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h) | |
1242 | { | |
1243 | int i; | |
1244 | ||
1245 | if (h->chainsize <= 0) | |
1246 | return 0; | |
1247 | ||
1248 | h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds, | |
1249 | GFP_KERNEL); | |
1250 | if (!h->cmd_sg_list) | |
1251 | return -ENOMEM; | |
1252 | for (i = 0; i < h->nr_cmds; i++) { | |
1253 | h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) * | |
1254 | h->chainsize, GFP_KERNEL); | |
1255 | if (!h->cmd_sg_list[i]) | |
1256 | goto clean; | |
1257 | } | |
1258 | return 0; | |
1259 | ||
1260 | clean: | |
1261 | hpsa_free_sg_chain_blocks(h); | |
1262 | return -ENOMEM; | |
1263 | } | |
1264 | ||
e2bea6df | 1265 | static int hpsa_map_sg_chain_block(struct ctlr_info *h, |
33a2ffce SC |
1266 | struct CommandList *c) |
1267 | { | |
1268 | struct SGDescriptor *chain_sg, *chain_block; | |
1269 | u64 temp64; | |
1270 | ||
1271 | chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; | |
1272 | chain_block = h->cmd_sg_list[c->cmdindex]; | |
1273 | chain_sg->Ext = HPSA_SG_CHAIN; | |
1274 | chain_sg->Len = sizeof(*chain_sg) * | |
1275 | (c->Header.SGTotal - h->max_cmd_sg_entries); | |
1276 | temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len, | |
1277 | PCI_DMA_TODEVICE); | |
e2bea6df SC |
1278 | if (dma_mapping_error(&h->pdev->dev, temp64)) { |
1279 | /* prevent subsequent unmapping */ | |
1280 | chain_sg->Addr.lower = 0; | |
1281 | chain_sg->Addr.upper = 0; | |
1282 | return -1; | |
1283 | } | |
33a2ffce SC |
1284 | chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL); |
1285 | chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL); | |
e2bea6df | 1286 | return 0; |
33a2ffce SC |
1287 | } |
1288 | ||
1289 | static void hpsa_unmap_sg_chain_block(struct ctlr_info *h, | |
1290 | struct CommandList *c) | |
1291 | { | |
1292 | struct SGDescriptor *chain_sg; | |
1293 | union u64bit temp64; | |
1294 | ||
1295 | if (c->Header.SGTotal <= h->max_cmd_sg_entries) | |
1296 | return; | |
1297 | ||
1298 | chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; | |
1299 | temp64.val32.lower = chain_sg->Addr.lower; | |
1300 | temp64.val32.upper = chain_sg->Addr.upper; | |
1301 | pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE); | |
1302 | } | |
1303 | ||
c349775e ST |
1304 | static void handle_ioaccel_mode2_error(struct ctlr_info *h, |
1305 | struct CommandList *c, | |
1306 | struct scsi_cmnd *cmd, | |
1307 | struct io_accel2_cmd *c2) | |
1308 | { | |
1309 | int data_len; | |
1310 | ||
1311 | switch (c2->error_data.serv_response) { | |
1312 | case IOACCEL2_SERV_RESPONSE_COMPLETE: | |
1313 | switch (c2->error_data.status) { | |
1314 | case IOACCEL2_STATUS_SR_TASK_COMP_GOOD: | |
1315 | break; | |
1316 | case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND: | |
1317 | dev_warn(&h->pdev->dev, | |
1318 | "%s: task complete with check condition.\n", | |
1319 | "HP SSD Smart Path"); | |
1320 | if (c2->error_data.data_present != | |
1321 | IOACCEL2_SENSE_DATA_PRESENT) | |
1322 | break; | |
1323 | /* copy the sense data */ | |
1324 | data_len = c2->error_data.sense_data_len; | |
1325 | if (data_len > SCSI_SENSE_BUFFERSIZE) | |
1326 | data_len = SCSI_SENSE_BUFFERSIZE; | |
1327 | if (data_len > sizeof(c2->error_data.sense_data_buff)) | |
1328 | data_len = | |
1329 | sizeof(c2->error_data.sense_data_buff); | |
1330 | memcpy(cmd->sense_buffer, | |
1331 | c2->error_data.sense_data_buff, data_len); | |
1332 | cmd->result |= SAM_STAT_CHECK_CONDITION; | |
1333 | break; | |
1334 | case IOACCEL2_STATUS_SR_TASK_COMP_BUSY: | |
1335 | dev_warn(&h->pdev->dev, | |
1336 | "%s: task complete with BUSY status.\n", | |
1337 | "HP SSD Smart Path"); | |
1338 | break; | |
1339 | case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON: | |
1340 | dev_warn(&h->pdev->dev, | |
1341 | "%s: task complete with reservation conflict.\n", | |
1342 | "HP SSD Smart Path"); | |
1343 | break; | |
1344 | case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL: | |
1345 | /* Make scsi midlayer do unlimited retries */ | |
1346 | cmd->result = DID_IMM_RETRY << 16; | |
1347 | break; | |
1348 | case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED: | |
1349 | dev_warn(&h->pdev->dev, | |
1350 | "%s: task complete with aborted status.\n", | |
1351 | "HP SSD Smart Path"); | |
1352 | break; | |
1353 | default: | |
1354 | dev_warn(&h->pdev->dev, | |
1355 | "%s: task complete with unrecognized status: 0x%02x\n", | |
1356 | "HP SSD Smart Path", c2->error_data.status); | |
1357 | break; | |
1358 | } | |
1359 | break; | |
1360 | case IOACCEL2_SERV_RESPONSE_FAILURE: | |
1361 | /* don't expect to get here. */ | |
1362 | dev_warn(&h->pdev->dev, | |
1363 | "unexpected delivery or target failure, status = 0x%02x\n", | |
1364 | c2->error_data.status); | |
1365 | break; | |
1366 | case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE: | |
1367 | break; | |
1368 | case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS: | |
1369 | break; | |
1370 | case IOACCEL2_SERV_RESPONSE_TMF_REJECTED: | |
1371 | dev_warn(&h->pdev->dev, "task management function rejected.\n"); | |
1372 | break; | |
1373 | case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN: | |
1374 | dev_warn(&h->pdev->dev, "task management function invalid LUN\n"); | |
1375 | break; | |
1376 | default: | |
1377 | dev_warn(&h->pdev->dev, | |
1378 | "%s: Unrecognized server response: 0x%02x\n", | |
1379 | "HP SSD Smart Path", c2->error_data.serv_response); | |
1380 | break; | |
1381 | } | |
1382 | } | |
1383 | ||
1384 | static void process_ioaccel2_completion(struct ctlr_info *h, | |
1385 | struct CommandList *c, struct scsi_cmnd *cmd, | |
1386 | struct hpsa_scsi_dev_t *dev) | |
1387 | { | |
1388 | struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
1389 | ||
1390 | /* check for good status */ | |
1391 | if (likely(c2->error_data.serv_response == 0 && | |
1392 | c2->error_data.status == 0)) { | |
1393 | cmd_free(h, c); | |
1394 | cmd->scsi_done(cmd); | |
1395 | return; | |
1396 | } | |
1397 | ||
1398 | /* Any RAID offload error results in retry which will use | |
1399 | * the normal I/O path so the controller can handle whatever's | |
1400 | * wrong. | |
1401 | */ | |
1402 | if (is_logical_dev_addr_mode(dev->scsi3addr) && | |
1403 | c2->error_data.serv_response == | |
1404 | IOACCEL2_SERV_RESPONSE_FAILURE) { | |
1405 | if (c2->error_data.status != | |
1406 | IOACCEL2_STATUS_SR_IOACCEL_DISABLED) | |
1407 | dev_warn(&h->pdev->dev, | |
1408 | "%s: Error 0x%02x, Retrying on standard path.\n", | |
1409 | "HP SSD Smart Path", c2->error_data.status); | |
1410 | dev->offload_enabled = 0; | |
1411 | cmd->result = DID_SOFT_ERROR << 16; | |
1412 | cmd_free(h, c); | |
1413 | cmd->scsi_done(cmd); | |
1414 | return; | |
1415 | } | |
1416 | handle_ioaccel_mode2_error(h, c, cmd, c2); | |
1417 | cmd_free(h, c); | |
1418 | cmd->scsi_done(cmd); | |
1419 | } | |
1420 | ||
1fb011fb | 1421 | static void complete_scsi_command(struct CommandList *cp) |
edd16368 SC |
1422 | { |
1423 | struct scsi_cmnd *cmd; | |
1424 | struct ctlr_info *h; | |
1425 | struct ErrorInfo *ei; | |
283b4a9b | 1426 | struct hpsa_scsi_dev_t *dev; |
edd16368 SC |
1427 | |
1428 | unsigned char sense_key; | |
1429 | unsigned char asc; /* additional sense code */ | |
1430 | unsigned char ascq; /* additional sense code qualifier */ | |
db111e18 | 1431 | unsigned long sense_data_size; |
edd16368 SC |
1432 | |
1433 | ei = cp->err_info; | |
1434 | cmd = (struct scsi_cmnd *) cp->scsi_cmd; | |
1435 | h = cp->h; | |
283b4a9b | 1436 | dev = cmd->device->hostdata; |
edd16368 SC |
1437 | |
1438 | scsi_dma_unmap(cmd); /* undo the DMA mappings */ | |
e1f7de0c MG |
1439 | if ((cp->cmd_type == CMD_SCSI) && |
1440 | (cp->Header.SGTotal > h->max_cmd_sg_entries)) | |
33a2ffce | 1441 | hpsa_unmap_sg_chain_block(h, cp); |
edd16368 SC |
1442 | |
1443 | cmd->result = (DID_OK << 16); /* host byte */ | |
1444 | cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ | |
c349775e ST |
1445 | |
1446 | if (cp->cmd_type == CMD_IOACCEL2) | |
1447 | return process_ioaccel2_completion(h, cp, cmd, dev); | |
1448 | ||
5512672f | 1449 | cmd->result |= ei->ScsiStatus; |
edd16368 SC |
1450 | |
1451 | /* copy the sense data whether we need to or not. */ | |
db111e18 SC |
1452 | if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo)) |
1453 | sense_data_size = SCSI_SENSE_BUFFERSIZE; | |
1454 | else | |
1455 | sense_data_size = sizeof(ei->SenseInfo); | |
1456 | if (ei->SenseLen < sense_data_size) | |
1457 | sense_data_size = ei->SenseLen; | |
1458 | ||
1459 | memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size); | |
edd16368 SC |
1460 | scsi_set_resid(cmd, ei->ResidualCnt); |
1461 | ||
1462 | if (ei->CommandStatus == 0) { | |
edd16368 | 1463 | cmd_free(h, cp); |
2cc5bfaf | 1464 | cmd->scsi_done(cmd); |
edd16368 SC |
1465 | return; |
1466 | } | |
1467 | ||
e1f7de0c MG |
1468 | /* For I/O accelerator commands, copy over some fields to the normal |
1469 | * CISS header used below for error handling. | |
1470 | */ | |
1471 | if (cp->cmd_type == CMD_IOACCEL1) { | |
1472 | struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex]; | |
1473 | cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd); | |
1474 | cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK; | |
1475 | cp->Header.Tag.lower = c->Tag.lower; | |
1476 | cp->Header.Tag.upper = c->Tag.upper; | |
1477 | memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8); | |
1478 | memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen); | |
283b4a9b SC |
1479 | |
1480 | /* Any RAID offload error results in retry which will use | |
1481 | * the normal I/O path so the controller can handle whatever's | |
1482 | * wrong. | |
1483 | */ | |
1484 | if (is_logical_dev_addr_mode(dev->scsi3addr)) { | |
1485 | if (ei->CommandStatus == CMD_IOACCEL_DISABLED) | |
1486 | dev->offload_enabled = 0; | |
1487 | cmd->result = DID_SOFT_ERROR << 16; | |
1488 | cmd_free(h, cp); | |
1489 | cmd->scsi_done(cmd); | |
1490 | return; | |
1491 | } | |
e1f7de0c MG |
1492 | } |
1493 | ||
edd16368 SC |
1494 | /* an error has occurred */ |
1495 | switch (ei->CommandStatus) { | |
1496 | ||
1497 | case CMD_TARGET_STATUS: | |
1498 | if (ei->ScsiStatus) { | |
1499 | /* Get sense key */ | |
1500 | sense_key = 0xf & ei->SenseInfo[2]; | |
1501 | /* Get additional sense code */ | |
1502 | asc = ei->SenseInfo[12]; | |
1503 | /* Get addition sense code qualifier */ | |
1504 | ascq = ei->SenseInfo[13]; | |
1505 | } | |
1506 | ||
1507 | if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) { | |
3ce438df | 1508 | if (check_for_unit_attention(h, cp)) |
edd16368 | 1509 | break; |
edd16368 SC |
1510 | if (sense_key == ILLEGAL_REQUEST) { |
1511 | /* | |
1512 | * SCSI REPORT_LUNS is commonly unsupported on | |
1513 | * Smart Array. Suppress noisy complaint. | |
1514 | */ | |
1515 | if (cp->Request.CDB[0] == REPORT_LUNS) | |
1516 | break; | |
1517 | ||
1518 | /* If ASC/ASCQ indicate Logical Unit | |
1519 | * Not Supported condition, | |
1520 | */ | |
1521 | if ((asc == 0x25) && (ascq == 0x0)) { | |
1522 | dev_warn(&h->pdev->dev, "cp %p " | |
1523 | "has check condition\n", cp); | |
1524 | break; | |
1525 | } | |
1526 | } | |
1527 | ||
1528 | if (sense_key == NOT_READY) { | |
1529 | /* If Sense is Not Ready, Logical Unit | |
1530 | * Not ready, Manual Intervention | |
1531 | * required | |
1532 | */ | |
1533 | if ((asc == 0x04) && (ascq == 0x03)) { | |
edd16368 SC |
1534 | dev_warn(&h->pdev->dev, "cp %p " |
1535 | "has check condition: unit " | |
1536 | "not ready, manual " | |
1537 | "intervention required\n", cp); | |
1538 | break; | |
1539 | } | |
1540 | } | |
1d3b3609 MG |
1541 | if (sense_key == ABORTED_COMMAND) { |
1542 | /* Aborted command is retryable */ | |
1543 | dev_warn(&h->pdev->dev, "cp %p " | |
1544 | "has check condition: aborted command: " | |
1545 | "ASC: 0x%x, ASCQ: 0x%x\n", | |
1546 | cp, asc, ascq); | |
2e311fba | 1547 | cmd->result |= DID_SOFT_ERROR << 16; |
1d3b3609 MG |
1548 | break; |
1549 | } | |
edd16368 | 1550 | /* Must be some other type of check condition */ |
21b8e4ef | 1551 | dev_dbg(&h->pdev->dev, "cp %p has check condition: " |
edd16368 SC |
1552 | "unknown type: " |
1553 | "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, " | |
1554 | "Returning result: 0x%x, " | |
1555 | "cmd=[%02x %02x %02x %02x %02x " | |
807be732 | 1556 | "%02x %02x %02x %02x %02x %02x " |
edd16368 SC |
1557 | "%02x %02x %02x %02x %02x]\n", |
1558 | cp, sense_key, asc, ascq, | |
1559 | cmd->result, | |
1560 | cmd->cmnd[0], cmd->cmnd[1], | |
1561 | cmd->cmnd[2], cmd->cmnd[3], | |
1562 | cmd->cmnd[4], cmd->cmnd[5], | |
1563 | cmd->cmnd[6], cmd->cmnd[7], | |
807be732 MM |
1564 | cmd->cmnd[8], cmd->cmnd[9], |
1565 | cmd->cmnd[10], cmd->cmnd[11], | |
1566 | cmd->cmnd[12], cmd->cmnd[13], | |
1567 | cmd->cmnd[14], cmd->cmnd[15]); | |
edd16368 SC |
1568 | break; |
1569 | } | |
1570 | ||
1571 | ||
1572 | /* Problem was not a check condition | |
1573 | * Pass it up to the upper layers... | |
1574 | */ | |
1575 | if (ei->ScsiStatus) { | |
1576 | dev_warn(&h->pdev->dev, "cp %p has status 0x%x " | |
1577 | "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, " | |
1578 | "Returning result: 0x%x\n", | |
1579 | cp, ei->ScsiStatus, | |
1580 | sense_key, asc, ascq, | |
1581 | cmd->result); | |
1582 | } else { /* scsi status is zero??? How??? */ | |
1583 | dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. " | |
1584 | "Returning no connection.\n", cp), | |
1585 | ||
1586 | /* Ordinarily, this case should never happen, | |
1587 | * but there is a bug in some released firmware | |
1588 | * revisions that allows it to happen if, for | |
1589 | * example, a 4100 backplane loses power and | |
1590 | * the tape drive is in it. We assume that | |
1591 | * it's a fatal error of some kind because we | |
1592 | * can't show that it wasn't. We will make it | |
1593 | * look like selection timeout since that is | |
1594 | * the most common reason for this to occur, | |
1595 | * and it's severe enough. | |
1596 | */ | |
1597 | ||
1598 | cmd->result = DID_NO_CONNECT << 16; | |
1599 | } | |
1600 | break; | |
1601 | ||
1602 | case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ | |
1603 | break; | |
1604 | case CMD_DATA_OVERRUN: | |
1605 | dev_warn(&h->pdev->dev, "cp %p has" | |
1606 | " completed with data overrun " | |
1607 | "reported\n", cp); | |
1608 | break; | |
1609 | case CMD_INVALID: { | |
1610 | /* print_bytes(cp, sizeof(*cp), 1, 0); | |
1611 | print_cmd(cp); */ | |
1612 | /* We get CMD_INVALID if you address a non-existent device | |
1613 | * instead of a selection timeout (no response). You will | |
1614 | * see this if you yank out a drive, then try to access it. | |
1615 | * This is kind of a shame because it means that any other | |
1616 | * CMD_INVALID (e.g. driver bug) will get interpreted as a | |
1617 | * missing target. */ | |
1618 | cmd->result = DID_NO_CONNECT << 16; | |
1619 | } | |
1620 | break; | |
1621 | case CMD_PROTOCOL_ERR: | |
256d0eaa | 1622 | cmd->result = DID_ERROR << 16; |
edd16368 | 1623 | dev_warn(&h->pdev->dev, "cp %p has " |
256d0eaa | 1624 | "protocol error\n", cp); |
edd16368 SC |
1625 | break; |
1626 | case CMD_HARDWARE_ERR: | |
1627 | cmd->result = DID_ERROR << 16; | |
1628 | dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp); | |
1629 | break; | |
1630 | case CMD_CONNECTION_LOST: | |
1631 | cmd->result = DID_ERROR << 16; | |
1632 | dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp); | |
1633 | break; | |
1634 | case CMD_ABORTED: | |
1635 | cmd->result = DID_ABORT << 16; | |
1636 | dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n", | |
1637 | cp, ei->ScsiStatus); | |
1638 | break; | |
1639 | case CMD_ABORT_FAILED: | |
1640 | cmd->result = DID_ERROR << 16; | |
1641 | dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp); | |
1642 | break; | |
1643 | case CMD_UNSOLICITED_ABORT: | |
f6e76055 SC |
1644 | cmd->result = DID_SOFT_ERROR << 16; /* retry the command */ |
1645 | dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited " | |
edd16368 SC |
1646 | "abort\n", cp); |
1647 | break; | |
1648 | case CMD_TIMEOUT: | |
1649 | cmd->result = DID_TIME_OUT << 16; | |
1650 | dev_warn(&h->pdev->dev, "cp %p timedout\n", cp); | |
1651 | break; | |
1d5e2ed0 SC |
1652 | case CMD_UNABORTABLE: |
1653 | cmd->result = DID_ERROR << 16; | |
1654 | dev_warn(&h->pdev->dev, "Command unabortable\n"); | |
1655 | break; | |
283b4a9b SC |
1656 | case CMD_IOACCEL_DISABLED: |
1657 | /* This only handles the direct pass-through case since RAID | |
1658 | * offload is handled above. Just attempt a retry. | |
1659 | */ | |
1660 | cmd->result = DID_SOFT_ERROR << 16; | |
1661 | dev_warn(&h->pdev->dev, | |
1662 | "cp %p had HP SSD Smart Path error\n", cp); | |
1663 | break; | |
edd16368 SC |
1664 | default: |
1665 | cmd->result = DID_ERROR << 16; | |
1666 | dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n", | |
1667 | cp, ei->CommandStatus); | |
1668 | } | |
edd16368 | 1669 | cmd_free(h, cp); |
2cc5bfaf | 1670 | cmd->scsi_done(cmd); |
edd16368 SC |
1671 | } |
1672 | ||
edd16368 SC |
1673 | static void hpsa_pci_unmap(struct pci_dev *pdev, |
1674 | struct CommandList *c, int sg_used, int data_direction) | |
1675 | { | |
1676 | int i; | |
1677 | union u64bit addr64; | |
1678 | ||
1679 | for (i = 0; i < sg_used; i++) { | |
1680 | addr64.val32.lower = c->SG[i].Addr.lower; | |
1681 | addr64.val32.upper = c->SG[i].Addr.upper; | |
1682 | pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len, | |
1683 | data_direction); | |
1684 | } | |
1685 | } | |
1686 | ||
a2dac136 | 1687 | static int hpsa_map_one(struct pci_dev *pdev, |
edd16368 SC |
1688 | struct CommandList *cp, |
1689 | unsigned char *buf, | |
1690 | size_t buflen, | |
1691 | int data_direction) | |
1692 | { | |
01a02ffc | 1693 | u64 addr64; |
edd16368 SC |
1694 | |
1695 | if (buflen == 0 || data_direction == PCI_DMA_NONE) { | |
1696 | cp->Header.SGList = 0; | |
1697 | cp->Header.SGTotal = 0; | |
a2dac136 | 1698 | return 0; |
edd16368 SC |
1699 | } |
1700 | ||
01a02ffc | 1701 | addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction); |
eceaae18 | 1702 | if (dma_mapping_error(&pdev->dev, addr64)) { |
a2dac136 | 1703 | /* Prevent subsequent unmap of something never mapped */ |
eceaae18 SK |
1704 | cp->Header.SGList = 0; |
1705 | cp->Header.SGTotal = 0; | |
a2dac136 | 1706 | return -1; |
eceaae18 | 1707 | } |
edd16368 | 1708 | cp->SG[0].Addr.lower = |
01a02ffc | 1709 | (u32) (addr64 & (u64) 0x00000000FFFFFFFF); |
edd16368 | 1710 | cp->SG[0].Addr.upper = |
01a02ffc | 1711 | (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF); |
edd16368 | 1712 | cp->SG[0].Len = buflen; |
e1d9cbfa | 1713 | cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */ |
01a02ffc SC |
1714 | cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */ |
1715 | cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */ | |
a2dac136 | 1716 | return 0; |
edd16368 SC |
1717 | } |
1718 | ||
1719 | static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h, | |
1720 | struct CommandList *c) | |
1721 | { | |
1722 | DECLARE_COMPLETION_ONSTACK(wait); | |
1723 | ||
1724 | c->waiting = &wait; | |
1725 | enqueue_cmd_and_start_io(h, c); | |
1726 | wait_for_completion(&wait); | |
1727 | } | |
1728 | ||
a0c12413 SC |
1729 | static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h, |
1730 | struct CommandList *c) | |
1731 | { | |
1732 | unsigned long flags; | |
1733 | ||
1734 | /* If controller lockup detected, fake a hardware error. */ | |
1735 | spin_lock_irqsave(&h->lock, flags); | |
1736 | if (unlikely(h->lockup_detected)) { | |
1737 | spin_unlock_irqrestore(&h->lock, flags); | |
1738 | c->err_info->CommandStatus = CMD_HARDWARE_ERR; | |
1739 | } else { | |
1740 | spin_unlock_irqrestore(&h->lock, flags); | |
1741 | hpsa_scsi_do_simple_cmd_core(h, c); | |
1742 | } | |
1743 | } | |
1744 | ||
9c2fc160 | 1745 | #define MAX_DRIVER_CMD_RETRIES 25 |
edd16368 SC |
1746 | static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h, |
1747 | struct CommandList *c, int data_direction) | |
1748 | { | |
9c2fc160 | 1749 | int backoff_time = 10, retry_count = 0; |
edd16368 SC |
1750 | |
1751 | do { | |
7630abd0 | 1752 | memset(c->err_info, 0, sizeof(*c->err_info)); |
edd16368 SC |
1753 | hpsa_scsi_do_simple_cmd_core(h, c); |
1754 | retry_count++; | |
9c2fc160 SC |
1755 | if (retry_count > 3) { |
1756 | msleep(backoff_time); | |
1757 | if (backoff_time < 1000) | |
1758 | backoff_time *= 2; | |
1759 | } | |
852af20a | 1760 | } while ((check_for_unit_attention(h, c) || |
9c2fc160 SC |
1761 | check_for_busy(h, c)) && |
1762 | retry_count <= MAX_DRIVER_CMD_RETRIES); | |
edd16368 SC |
1763 | hpsa_pci_unmap(h->pdev, c, 1, data_direction); |
1764 | } | |
1765 | ||
1766 | static void hpsa_scsi_interpret_error(struct CommandList *cp) | |
1767 | { | |
1768 | struct ErrorInfo *ei; | |
1769 | struct device *d = &cp->h->pdev->dev; | |
1770 | ||
1771 | ei = cp->err_info; | |
1772 | switch (ei->CommandStatus) { | |
1773 | case CMD_TARGET_STATUS: | |
1774 | dev_warn(d, "cmd %p has completed with errors\n", cp); | |
1775 | dev_warn(d, "cmd %p has SCSI Status = %x\n", cp, | |
1776 | ei->ScsiStatus); | |
1777 | if (ei->ScsiStatus == 0) | |
1778 | dev_warn(d, "SCSI status is abnormally zero. " | |
1779 | "(probably indicates selection timeout " | |
1780 | "reported incorrectly due to a known " | |
1781 | "firmware bug, circa July, 2001.)\n"); | |
1782 | break; | |
1783 | case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ | |
1784 | dev_info(d, "UNDERRUN\n"); | |
1785 | break; | |
1786 | case CMD_DATA_OVERRUN: | |
1787 | dev_warn(d, "cp %p has completed with data overrun\n", cp); | |
1788 | break; | |
1789 | case CMD_INVALID: { | |
1790 | /* controller unfortunately reports SCSI passthru's | |
1791 | * to non-existent targets as invalid commands. | |
1792 | */ | |
1793 | dev_warn(d, "cp %p is reported invalid (probably means " | |
1794 | "target device no longer present)\n", cp); | |
1795 | /* print_bytes((unsigned char *) cp, sizeof(*cp), 1, 0); | |
1796 | print_cmd(cp); */ | |
1797 | } | |
1798 | break; | |
1799 | case CMD_PROTOCOL_ERR: | |
1800 | dev_warn(d, "cp %p has protocol error \n", cp); | |
1801 | break; | |
1802 | case CMD_HARDWARE_ERR: | |
1803 | /* cmd->result = DID_ERROR << 16; */ | |
1804 | dev_warn(d, "cp %p had hardware error\n", cp); | |
1805 | break; | |
1806 | case CMD_CONNECTION_LOST: | |
1807 | dev_warn(d, "cp %p had connection lost\n", cp); | |
1808 | break; | |
1809 | case CMD_ABORTED: | |
1810 | dev_warn(d, "cp %p was aborted\n", cp); | |
1811 | break; | |
1812 | case CMD_ABORT_FAILED: | |
1813 | dev_warn(d, "cp %p reports abort failed\n", cp); | |
1814 | break; | |
1815 | case CMD_UNSOLICITED_ABORT: | |
1816 | dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp); | |
1817 | break; | |
1818 | case CMD_TIMEOUT: | |
1819 | dev_warn(d, "cp %p timed out\n", cp); | |
1820 | break; | |
1d5e2ed0 SC |
1821 | case CMD_UNABORTABLE: |
1822 | dev_warn(d, "Command unabortable\n"); | |
1823 | break; | |
edd16368 SC |
1824 | default: |
1825 | dev_warn(d, "cp %p returned unknown status %x\n", cp, | |
1826 | ei->CommandStatus); | |
1827 | } | |
1828 | } | |
1829 | ||
1830 | static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr, | |
1831 | unsigned char page, unsigned char *buf, | |
1832 | unsigned char bufsize) | |
1833 | { | |
1834 | int rc = IO_OK; | |
1835 | struct CommandList *c; | |
1836 | struct ErrorInfo *ei; | |
1837 | ||
1838 | c = cmd_special_alloc(h); | |
1839 | ||
1840 | if (c == NULL) { /* trouble... */ | |
1841 | dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n"); | |
ecd9aad4 | 1842 | return -ENOMEM; |
edd16368 SC |
1843 | } |
1844 | ||
a2dac136 SC |
1845 | if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize, |
1846 | page, scsi3addr, TYPE_CMD)) { | |
1847 | rc = -1; | |
1848 | goto out; | |
1849 | } | |
edd16368 SC |
1850 | hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE); |
1851 | ei = c->err_info; | |
1852 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
1853 | hpsa_scsi_interpret_error(c); | |
1854 | rc = -1; | |
1855 | } | |
a2dac136 | 1856 | out: |
edd16368 SC |
1857 | cmd_special_free(h, c); |
1858 | return rc; | |
1859 | } | |
1860 | ||
bf711ac6 ST |
1861 | static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr, |
1862 | u8 reset_type) | |
edd16368 SC |
1863 | { |
1864 | int rc = IO_OK; | |
1865 | struct CommandList *c; | |
1866 | struct ErrorInfo *ei; | |
1867 | ||
1868 | c = cmd_special_alloc(h); | |
1869 | ||
1870 | if (c == NULL) { /* trouble... */ | |
1871 | dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n"); | |
e9ea04a6 | 1872 | return -ENOMEM; |
edd16368 SC |
1873 | } |
1874 | ||
a2dac136 | 1875 | /* fill_cmd can't fail here, no data buffer to map. */ |
bf711ac6 ST |
1876 | (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0, |
1877 | scsi3addr, TYPE_MSG); | |
1878 | c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */ | |
edd16368 SC |
1879 | hpsa_scsi_do_simple_cmd_core(h, c); |
1880 | /* no unmap needed here because no data xfer. */ | |
1881 | ||
1882 | ei = c->err_info; | |
1883 | if (ei->CommandStatus != 0) { | |
1884 | hpsa_scsi_interpret_error(c); | |
1885 | rc = -1; | |
1886 | } | |
1887 | cmd_special_free(h, c); | |
1888 | return rc; | |
1889 | } | |
1890 | ||
1891 | static void hpsa_get_raid_level(struct ctlr_info *h, | |
1892 | unsigned char *scsi3addr, unsigned char *raid_level) | |
1893 | { | |
1894 | int rc; | |
1895 | unsigned char *buf; | |
1896 | ||
1897 | *raid_level = RAID_UNKNOWN; | |
1898 | buf = kzalloc(64, GFP_KERNEL); | |
1899 | if (!buf) | |
1900 | return; | |
1901 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0xC1, buf, 64); | |
1902 | if (rc == 0) | |
1903 | *raid_level = buf[8]; | |
1904 | if (*raid_level > RAID_UNKNOWN) | |
1905 | *raid_level = RAID_UNKNOWN; | |
1906 | kfree(buf); | |
1907 | return; | |
1908 | } | |
1909 | ||
283b4a9b SC |
1910 | #define HPSA_MAP_DEBUG |
1911 | #ifdef HPSA_MAP_DEBUG | |
1912 | static void hpsa_debug_map_buff(struct ctlr_info *h, int rc, | |
1913 | struct raid_map_data *map_buff) | |
1914 | { | |
1915 | struct raid_map_disk_data *dd = &map_buff->data[0]; | |
1916 | int map, row, col; | |
1917 | u16 map_cnt, row_cnt, disks_per_row; | |
1918 | ||
1919 | if (rc != 0) | |
1920 | return; | |
1921 | ||
1922 | dev_info(&h->pdev->dev, "structure_size = %u\n", | |
1923 | le32_to_cpu(map_buff->structure_size)); | |
1924 | dev_info(&h->pdev->dev, "volume_blk_size = %u\n", | |
1925 | le32_to_cpu(map_buff->volume_blk_size)); | |
1926 | dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n", | |
1927 | le64_to_cpu(map_buff->volume_blk_cnt)); | |
1928 | dev_info(&h->pdev->dev, "physicalBlockShift = %u\n", | |
1929 | map_buff->phys_blk_shift); | |
1930 | dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n", | |
1931 | map_buff->parity_rotation_shift); | |
1932 | dev_info(&h->pdev->dev, "strip_size = %u\n", | |
1933 | le16_to_cpu(map_buff->strip_size)); | |
1934 | dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n", | |
1935 | le64_to_cpu(map_buff->disk_starting_blk)); | |
1936 | dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n", | |
1937 | le64_to_cpu(map_buff->disk_blk_cnt)); | |
1938 | dev_info(&h->pdev->dev, "data_disks_per_row = %u\n", | |
1939 | le16_to_cpu(map_buff->data_disks_per_row)); | |
1940 | dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n", | |
1941 | le16_to_cpu(map_buff->metadata_disks_per_row)); | |
1942 | dev_info(&h->pdev->dev, "row_cnt = %u\n", | |
1943 | le16_to_cpu(map_buff->row_cnt)); | |
1944 | dev_info(&h->pdev->dev, "layout_map_count = %u\n", | |
1945 | le16_to_cpu(map_buff->layout_map_count)); | |
1946 | ||
1947 | map_cnt = le16_to_cpu(map_buff->layout_map_count); | |
1948 | for (map = 0; map < map_cnt; map++) { | |
1949 | dev_info(&h->pdev->dev, "Map%u:\n", map); | |
1950 | row_cnt = le16_to_cpu(map_buff->row_cnt); | |
1951 | for (row = 0; row < row_cnt; row++) { | |
1952 | dev_info(&h->pdev->dev, " Row%u:\n", row); | |
1953 | disks_per_row = | |
1954 | le16_to_cpu(map_buff->data_disks_per_row); | |
1955 | for (col = 0; col < disks_per_row; col++, dd++) | |
1956 | dev_info(&h->pdev->dev, | |
1957 | " D%02u: h=0x%04x xor=%u,%u\n", | |
1958 | col, dd->ioaccel_handle, | |
1959 | dd->xor_mult[0], dd->xor_mult[1]); | |
1960 | disks_per_row = | |
1961 | le16_to_cpu(map_buff->metadata_disks_per_row); | |
1962 | for (col = 0; col < disks_per_row; col++, dd++) | |
1963 | dev_info(&h->pdev->dev, | |
1964 | " M%02u: h=0x%04x xor=%u,%u\n", | |
1965 | col, dd->ioaccel_handle, | |
1966 | dd->xor_mult[0], dd->xor_mult[1]); | |
1967 | } | |
1968 | } | |
1969 | } | |
1970 | #else | |
1971 | static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h, | |
1972 | __attribute__((unused)) int rc, | |
1973 | __attribute__((unused)) struct raid_map_data *map_buff) | |
1974 | { | |
1975 | } | |
1976 | #endif | |
1977 | ||
1978 | static int hpsa_get_raid_map(struct ctlr_info *h, | |
1979 | unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) | |
1980 | { | |
1981 | int rc = 0; | |
1982 | struct CommandList *c; | |
1983 | struct ErrorInfo *ei; | |
1984 | ||
1985 | c = cmd_special_alloc(h); | |
1986 | if (c == NULL) { | |
1987 | dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n"); | |
1988 | return -ENOMEM; | |
1989 | } | |
1990 | if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map, | |
1991 | sizeof(this_device->raid_map), 0, | |
1992 | scsi3addr, TYPE_CMD)) { | |
1993 | dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n"); | |
1994 | cmd_special_free(h, c); | |
1995 | return -ENOMEM; | |
1996 | } | |
1997 | hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE); | |
1998 | ei = c->err_info; | |
1999 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
2000 | hpsa_scsi_interpret_error(c); | |
2001 | cmd_special_free(h, c); | |
2002 | return -1; | |
2003 | } | |
2004 | cmd_special_free(h, c); | |
2005 | ||
2006 | /* @todo in the future, dynamically allocate RAID map memory */ | |
2007 | if (le32_to_cpu(this_device->raid_map.structure_size) > | |
2008 | sizeof(this_device->raid_map)) { | |
2009 | dev_warn(&h->pdev->dev, "RAID map size is too large!\n"); | |
2010 | rc = -1; | |
2011 | } | |
2012 | hpsa_debug_map_buff(h, rc, &this_device->raid_map); | |
2013 | return rc; | |
2014 | } | |
2015 | ||
2016 | static void hpsa_get_ioaccel_status(struct ctlr_info *h, | |
2017 | unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) | |
2018 | { | |
2019 | int rc; | |
2020 | unsigned char *buf; | |
2021 | u8 ioaccel_status; | |
2022 | ||
2023 | this_device->offload_config = 0; | |
2024 | this_device->offload_enabled = 0; | |
2025 | ||
2026 | buf = kzalloc(64, GFP_KERNEL); | |
2027 | if (!buf) | |
2028 | return; | |
2029 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, | |
2030 | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64); | |
2031 | if (rc != 0) | |
2032 | goto out; | |
2033 | ||
2034 | #define IOACCEL_STATUS_BYTE 4 | |
2035 | #define OFFLOAD_CONFIGURED_BIT 0x01 | |
2036 | #define OFFLOAD_ENABLED_BIT 0x02 | |
2037 | ioaccel_status = buf[IOACCEL_STATUS_BYTE]; | |
2038 | this_device->offload_config = | |
2039 | !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT); | |
2040 | if (this_device->offload_config) { | |
2041 | this_device->offload_enabled = | |
2042 | !!(ioaccel_status & OFFLOAD_ENABLED_BIT); | |
2043 | if (hpsa_get_raid_map(h, scsi3addr, this_device)) | |
2044 | this_device->offload_enabled = 0; | |
2045 | } | |
2046 | out: | |
2047 | kfree(buf); | |
2048 | return; | |
2049 | } | |
2050 | ||
edd16368 SC |
2051 | /* Get the device id from inquiry page 0x83 */ |
2052 | static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr, | |
2053 | unsigned char *device_id, int buflen) | |
2054 | { | |
2055 | int rc; | |
2056 | unsigned char *buf; | |
2057 | ||
2058 | if (buflen > 16) | |
2059 | buflen = 16; | |
2060 | buf = kzalloc(64, GFP_KERNEL); | |
2061 | if (!buf) | |
2062 | return -1; | |
2063 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0x83, buf, 64); | |
2064 | if (rc == 0) | |
2065 | memcpy(device_id, &buf[8], buflen); | |
2066 | kfree(buf); | |
2067 | return rc != 0; | |
2068 | } | |
2069 | ||
2070 | static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical, | |
2071 | struct ReportLUNdata *buf, int bufsize, | |
2072 | int extended_response) | |
2073 | { | |
2074 | int rc = IO_OK; | |
2075 | struct CommandList *c; | |
2076 | unsigned char scsi3addr[8]; | |
2077 | struct ErrorInfo *ei; | |
2078 | ||
2079 | c = cmd_special_alloc(h); | |
2080 | if (c == NULL) { /* trouble... */ | |
2081 | dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n"); | |
2082 | return -1; | |
2083 | } | |
e89c0ae7 SC |
2084 | /* address the controller */ |
2085 | memset(scsi3addr, 0, sizeof(scsi3addr)); | |
a2dac136 SC |
2086 | if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h, |
2087 | buf, bufsize, 0, scsi3addr, TYPE_CMD)) { | |
2088 | rc = -1; | |
2089 | goto out; | |
2090 | } | |
edd16368 SC |
2091 | if (extended_response) |
2092 | c->Request.CDB[1] = extended_response; | |
2093 | hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE); | |
2094 | ei = c->err_info; | |
2095 | if (ei->CommandStatus != 0 && | |
2096 | ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
2097 | hpsa_scsi_interpret_error(c); | |
2098 | rc = -1; | |
283b4a9b SC |
2099 | } else { |
2100 | if (buf->extended_response_flag != extended_response) { | |
2101 | dev_err(&h->pdev->dev, | |
2102 | "report luns requested format %u, got %u\n", | |
2103 | extended_response, | |
2104 | buf->extended_response_flag); | |
2105 | rc = -1; | |
2106 | } | |
edd16368 | 2107 | } |
a2dac136 | 2108 | out: |
edd16368 SC |
2109 | cmd_special_free(h, c); |
2110 | return rc; | |
2111 | } | |
2112 | ||
2113 | static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h, | |
2114 | struct ReportLUNdata *buf, | |
2115 | int bufsize, int extended_response) | |
2116 | { | |
2117 | return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response); | |
2118 | } | |
2119 | ||
2120 | static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h, | |
2121 | struct ReportLUNdata *buf, int bufsize) | |
2122 | { | |
2123 | return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0); | |
2124 | } | |
2125 | ||
2126 | static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device, | |
2127 | int bus, int target, int lun) | |
2128 | { | |
2129 | device->bus = bus; | |
2130 | device->target = target; | |
2131 | device->lun = lun; | |
2132 | } | |
2133 | ||
2134 | static int hpsa_update_device_info(struct ctlr_info *h, | |
0b0e1d6c SC |
2135 | unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device, |
2136 | unsigned char *is_OBDR_device) | |
edd16368 | 2137 | { |
0b0e1d6c SC |
2138 | |
2139 | #define OBDR_SIG_OFFSET 43 | |
2140 | #define OBDR_TAPE_SIG "$DR-10" | |
2141 | #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1) | |
2142 | #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN) | |
2143 | ||
ea6d3bc3 | 2144 | unsigned char *inq_buff; |
0b0e1d6c | 2145 | unsigned char *obdr_sig; |
edd16368 | 2146 | |
ea6d3bc3 | 2147 | inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL); |
edd16368 SC |
2148 | if (!inq_buff) |
2149 | goto bail_out; | |
2150 | ||
edd16368 SC |
2151 | /* Do an inquiry to the device to see what it is. */ |
2152 | if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff, | |
2153 | (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) { | |
2154 | /* Inquiry failed (msg printed already) */ | |
2155 | dev_err(&h->pdev->dev, | |
2156 | "hpsa_update_device_info: inquiry failed\n"); | |
2157 | goto bail_out; | |
2158 | } | |
2159 | ||
edd16368 SC |
2160 | this_device->devtype = (inq_buff[0] & 0x1f); |
2161 | memcpy(this_device->scsi3addr, scsi3addr, 8); | |
2162 | memcpy(this_device->vendor, &inq_buff[8], | |
2163 | sizeof(this_device->vendor)); | |
2164 | memcpy(this_device->model, &inq_buff[16], | |
2165 | sizeof(this_device->model)); | |
edd16368 SC |
2166 | memset(this_device->device_id, 0, |
2167 | sizeof(this_device->device_id)); | |
2168 | hpsa_get_device_id(h, scsi3addr, this_device->device_id, | |
2169 | sizeof(this_device->device_id)); | |
2170 | ||
2171 | if (this_device->devtype == TYPE_DISK && | |
283b4a9b | 2172 | is_logical_dev_addr_mode(scsi3addr)) { |
edd16368 | 2173 | hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level); |
283b4a9b SC |
2174 | if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC) |
2175 | hpsa_get_ioaccel_status(h, scsi3addr, this_device); | |
2176 | } else { | |
edd16368 | 2177 | this_device->raid_level = RAID_UNKNOWN; |
283b4a9b SC |
2178 | this_device->offload_config = 0; |
2179 | this_device->offload_enabled = 0; | |
2180 | } | |
edd16368 | 2181 | |
0b0e1d6c SC |
2182 | if (is_OBDR_device) { |
2183 | /* See if this is a One-Button-Disaster-Recovery device | |
2184 | * by looking for "$DR-10" at offset 43 in inquiry data. | |
2185 | */ | |
2186 | obdr_sig = &inq_buff[OBDR_SIG_OFFSET]; | |
2187 | *is_OBDR_device = (this_device->devtype == TYPE_ROM && | |
2188 | strncmp(obdr_sig, OBDR_TAPE_SIG, | |
2189 | OBDR_SIG_LEN) == 0); | |
2190 | } | |
2191 | ||
edd16368 SC |
2192 | kfree(inq_buff); |
2193 | return 0; | |
2194 | ||
2195 | bail_out: | |
2196 | kfree(inq_buff); | |
2197 | return 1; | |
2198 | } | |
2199 | ||
4f4eb9f1 | 2200 | static unsigned char *ext_target_model[] = { |
edd16368 SC |
2201 | "MSA2012", |
2202 | "MSA2024", | |
2203 | "MSA2312", | |
2204 | "MSA2324", | |
fda38518 | 2205 | "P2000 G3 SAS", |
e06c8e5c | 2206 | "MSA 2040 SAS", |
edd16368 SC |
2207 | NULL, |
2208 | }; | |
2209 | ||
4f4eb9f1 | 2210 | static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device) |
edd16368 SC |
2211 | { |
2212 | int i; | |
2213 | ||
4f4eb9f1 ST |
2214 | for (i = 0; ext_target_model[i]; i++) |
2215 | if (strncmp(device->model, ext_target_model[i], | |
2216 | strlen(ext_target_model[i])) == 0) | |
edd16368 SC |
2217 | return 1; |
2218 | return 0; | |
2219 | } | |
2220 | ||
2221 | /* Helper function to assign bus, target, lun mapping of devices. | |
4f4eb9f1 | 2222 | * Puts non-external target logical volumes on bus 0, external target logical |
edd16368 SC |
2223 | * volumes on bus 1, physical devices on bus 2. and the hba on bus 3. |
2224 | * Logical drive target and lun are assigned at this time, but | |
2225 | * physical device lun and target assignment are deferred (assigned | |
2226 | * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.) | |
2227 | */ | |
2228 | static void figure_bus_target_lun(struct ctlr_info *h, | |
1f310bde | 2229 | u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device) |
edd16368 | 2230 | { |
1f310bde SC |
2231 | u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes)); |
2232 | ||
2233 | if (!is_logical_dev_addr_mode(lunaddrbytes)) { | |
2234 | /* physical device, target and lun filled in later */ | |
edd16368 | 2235 | if (is_hba_lunid(lunaddrbytes)) |
1f310bde | 2236 | hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff); |
edd16368 | 2237 | else |
1f310bde SC |
2238 | /* defer target, lun assignment for physical devices */ |
2239 | hpsa_set_bus_target_lun(device, 2, -1, -1); | |
2240 | return; | |
2241 | } | |
2242 | /* It's a logical device */ | |
4f4eb9f1 ST |
2243 | if (is_ext_target(h, device)) { |
2244 | /* external target way, put logicals on bus 1 | |
1f310bde SC |
2245 | * and match target/lun numbers box |
2246 | * reports, other smart array, bus 0, target 0, match lunid | |
2247 | */ | |
2248 | hpsa_set_bus_target_lun(device, | |
2249 | 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff); | |
2250 | return; | |
edd16368 | 2251 | } |
1f310bde | 2252 | hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff); |
edd16368 SC |
2253 | } |
2254 | ||
2255 | /* | |
2256 | * If there is no lun 0 on a target, linux won't find any devices. | |
4f4eb9f1 | 2257 | * For the external targets (arrays), we have to manually detect the enclosure |
edd16368 SC |
2258 | * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report |
2259 | * it for some reason. *tmpdevice is the target we're adding, | |
2260 | * this_device is a pointer into the current element of currentsd[] | |
2261 | * that we're building up in update_scsi_devices(), below. | |
2262 | * lunzerobits is a bitmap that tracks which targets already have a | |
2263 | * lun 0 assigned. | |
2264 | * Returns 1 if an enclosure was added, 0 if not. | |
2265 | */ | |
4f4eb9f1 | 2266 | static int add_ext_target_dev(struct ctlr_info *h, |
edd16368 | 2267 | struct hpsa_scsi_dev_t *tmpdevice, |
01a02ffc | 2268 | struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes, |
4f4eb9f1 | 2269 | unsigned long lunzerobits[], int *n_ext_target_devs) |
edd16368 SC |
2270 | { |
2271 | unsigned char scsi3addr[8]; | |
2272 | ||
1f310bde | 2273 | if (test_bit(tmpdevice->target, lunzerobits)) |
edd16368 SC |
2274 | return 0; /* There is already a lun 0 on this target. */ |
2275 | ||
2276 | if (!is_logical_dev_addr_mode(lunaddrbytes)) | |
2277 | return 0; /* It's the logical targets that may lack lun 0. */ | |
2278 | ||
4f4eb9f1 ST |
2279 | if (!is_ext_target(h, tmpdevice)) |
2280 | return 0; /* Only external target devices have this problem. */ | |
edd16368 | 2281 | |
1f310bde | 2282 | if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */ |
edd16368 SC |
2283 | return 0; |
2284 | ||
c4f8a299 | 2285 | memset(scsi3addr, 0, 8); |
1f310bde | 2286 | scsi3addr[3] = tmpdevice->target; |
edd16368 SC |
2287 | if (is_hba_lunid(scsi3addr)) |
2288 | return 0; /* Don't add the RAID controller here. */ | |
2289 | ||
339b2b14 SC |
2290 | if (is_scsi_rev_5(h)) |
2291 | return 0; /* p1210m doesn't need to do this. */ | |
2292 | ||
4f4eb9f1 | 2293 | if (*n_ext_target_devs >= MAX_EXT_TARGETS) { |
aca4a520 ST |
2294 | dev_warn(&h->pdev->dev, "Maximum number of external " |
2295 | "target devices exceeded. Check your hardware " | |
edd16368 SC |
2296 | "configuration."); |
2297 | return 0; | |
2298 | } | |
2299 | ||
0b0e1d6c | 2300 | if (hpsa_update_device_info(h, scsi3addr, this_device, NULL)) |
edd16368 | 2301 | return 0; |
4f4eb9f1 | 2302 | (*n_ext_target_devs)++; |
1f310bde SC |
2303 | hpsa_set_bus_target_lun(this_device, |
2304 | tmpdevice->bus, tmpdevice->target, 0); | |
2305 | set_bit(tmpdevice->target, lunzerobits); | |
edd16368 SC |
2306 | return 1; |
2307 | } | |
2308 | ||
2309 | /* | |
2310 | * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev, | |
2311 | * logdev. The number of luns in physdev and logdev are returned in | |
2312 | * *nphysicals and *nlogicals, respectively. | |
2313 | * Returns 0 on success, -1 otherwise. | |
2314 | */ | |
2315 | static int hpsa_gather_lun_info(struct ctlr_info *h, | |
2316 | int reportlunsize, | |
283b4a9b | 2317 | struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode, |
01a02ffc | 2318 | struct ReportLUNdata *logdev, u32 *nlogicals) |
edd16368 | 2319 | { |
283b4a9b SC |
2320 | int physical_entry_size = 8; |
2321 | ||
2322 | *physical_mode = 0; | |
2323 | ||
2324 | /* For I/O accelerator mode we need to read physical device handles */ | |
317d4adf MM |
2325 | if (h->transMethod & CFGTBL_Trans_io_accel1 || |
2326 | h->transMethod & CFGTBL_Trans_io_accel2) { | |
283b4a9b SC |
2327 | *physical_mode = HPSA_REPORT_PHYS_EXTENDED; |
2328 | physical_entry_size = 24; | |
2329 | } | |
a93aa1fe | 2330 | if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize, |
283b4a9b | 2331 | *physical_mode)) { |
edd16368 SC |
2332 | dev_err(&h->pdev->dev, "report physical LUNs failed.\n"); |
2333 | return -1; | |
2334 | } | |
283b4a9b SC |
2335 | *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / |
2336 | physical_entry_size; | |
edd16368 SC |
2337 | if (*nphysicals > HPSA_MAX_PHYS_LUN) { |
2338 | dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded." | |
2339 | " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN, | |
2340 | *nphysicals - HPSA_MAX_PHYS_LUN); | |
2341 | *nphysicals = HPSA_MAX_PHYS_LUN; | |
2342 | } | |
2343 | if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) { | |
2344 | dev_err(&h->pdev->dev, "report logical LUNs failed.\n"); | |
2345 | return -1; | |
2346 | } | |
6df1e954 | 2347 | *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8; |
edd16368 SC |
2348 | /* Reject Logicals in excess of our max capability. */ |
2349 | if (*nlogicals > HPSA_MAX_LUN) { | |
2350 | dev_warn(&h->pdev->dev, | |
2351 | "maximum logical LUNs (%d) exceeded. " | |
2352 | "%d LUNs ignored.\n", HPSA_MAX_LUN, | |
2353 | *nlogicals - HPSA_MAX_LUN); | |
2354 | *nlogicals = HPSA_MAX_LUN; | |
2355 | } | |
2356 | if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) { | |
2357 | dev_warn(&h->pdev->dev, | |
2358 | "maximum logical + physical LUNs (%d) exceeded. " | |
2359 | "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN, | |
2360 | *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN); | |
2361 | *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals; | |
2362 | } | |
2363 | return 0; | |
2364 | } | |
2365 | ||
339b2b14 | 2366 | u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i, |
a93aa1fe MG |
2367 | int nphysicals, int nlogicals, |
2368 | struct ReportExtendedLUNdata *physdev_list, | |
339b2b14 SC |
2369 | struct ReportLUNdata *logdev_list) |
2370 | { | |
2371 | /* Helper function, figure out where the LUN ID info is coming from | |
2372 | * given index i, lists of physical and logical devices, where in | |
2373 | * the list the raid controller is supposed to appear (first or last) | |
2374 | */ | |
2375 | ||
2376 | int logicals_start = nphysicals + (raid_ctlr_position == 0); | |
2377 | int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0); | |
2378 | ||
2379 | if (i == raid_ctlr_position) | |
2380 | return RAID_CTLR_LUNID; | |
2381 | ||
2382 | if (i < logicals_start) | |
2383 | return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0]; | |
2384 | ||
2385 | if (i < last_device) | |
2386 | return &logdev_list->LUN[i - nphysicals - | |
2387 | (raid_ctlr_position == 0)][0]; | |
2388 | BUG(); | |
2389 | return NULL; | |
2390 | } | |
2391 | ||
edd16368 SC |
2392 | static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno) |
2393 | { | |
2394 | /* the idea here is we could get notified | |
2395 | * that some devices have changed, so we do a report | |
2396 | * physical luns and report logical luns cmd, and adjust | |
2397 | * our list of devices accordingly. | |
2398 | * | |
2399 | * The scsi3addr's of devices won't change so long as the | |
2400 | * adapter is not reset. That means we can rescan and | |
2401 | * tell which devices we already know about, vs. new | |
2402 | * devices, vs. disappearing devices. | |
2403 | */ | |
a93aa1fe | 2404 | struct ReportExtendedLUNdata *physdev_list = NULL; |
edd16368 | 2405 | struct ReportLUNdata *logdev_list = NULL; |
01a02ffc SC |
2406 | u32 nphysicals = 0; |
2407 | u32 nlogicals = 0; | |
283b4a9b | 2408 | int physical_mode = 0; |
01a02ffc | 2409 | u32 ndev_allocated = 0; |
edd16368 SC |
2410 | struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice; |
2411 | int ncurrent = 0; | |
283b4a9b | 2412 | int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 24; |
4f4eb9f1 | 2413 | int i, n_ext_target_devs, ndevs_to_allocate; |
339b2b14 | 2414 | int raid_ctlr_position; |
aca4a520 | 2415 | DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS); |
edd16368 | 2416 | |
cfe5badc | 2417 | currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL); |
edd16368 SC |
2418 | physdev_list = kzalloc(reportlunsize, GFP_KERNEL); |
2419 | logdev_list = kzalloc(reportlunsize, GFP_KERNEL); | |
edd16368 SC |
2420 | tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL); |
2421 | ||
0b0e1d6c | 2422 | if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) { |
edd16368 SC |
2423 | dev_err(&h->pdev->dev, "out of memory\n"); |
2424 | goto out; | |
2425 | } | |
2426 | memset(lunzerobits, 0, sizeof(lunzerobits)); | |
2427 | ||
a93aa1fe MG |
2428 | if (hpsa_gather_lun_info(h, reportlunsize, |
2429 | (struct ReportLUNdata *) physdev_list, &nphysicals, | |
283b4a9b | 2430 | &physical_mode, logdev_list, &nlogicals)) |
edd16368 SC |
2431 | goto out; |
2432 | ||
aca4a520 ST |
2433 | /* We might see up to the maximum number of logical and physical disks |
2434 | * plus external target devices, and a device for the local RAID | |
2435 | * controller. | |
edd16368 | 2436 | */ |
aca4a520 | 2437 | ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1; |
edd16368 SC |
2438 | |
2439 | /* Allocate the per device structures */ | |
2440 | for (i = 0; i < ndevs_to_allocate; i++) { | |
b7ec021f ST |
2441 | if (i >= HPSA_MAX_DEVICES) { |
2442 | dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded." | |
2443 | " %d devices ignored.\n", HPSA_MAX_DEVICES, | |
2444 | ndevs_to_allocate - HPSA_MAX_DEVICES); | |
2445 | break; | |
2446 | } | |
2447 | ||
edd16368 SC |
2448 | currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL); |
2449 | if (!currentsd[i]) { | |
2450 | dev_warn(&h->pdev->dev, "out of memory at %s:%d\n", | |
2451 | __FILE__, __LINE__); | |
2452 | goto out; | |
2453 | } | |
2454 | ndev_allocated++; | |
2455 | } | |
2456 | ||
339b2b14 SC |
2457 | if (unlikely(is_scsi_rev_5(h))) |
2458 | raid_ctlr_position = 0; | |
2459 | else | |
2460 | raid_ctlr_position = nphysicals + nlogicals; | |
2461 | ||
edd16368 | 2462 | /* adjust our table of devices */ |
4f4eb9f1 | 2463 | n_ext_target_devs = 0; |
edd16368 | 2464 | for (i = 0; i < nphysicals + nlogicals + 1; i++) { |
0b0e1d6c | 2465 | u8 *lunaddrbytes, is_OBDR = 0; |
edd16368 SC |
2466 | |
2467 | /* Figure out where the LUN ID info is coming from */ | |
339b2b14 SC |
2468 | lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position, |
2469 | i, nphysicals, nlogicals, physdev_list, logdev_list); | |
edd16368 | 2470 | /* skip masked physical devices. */ |
339b2b14 SC |
2471 | if (lunaddrbytes[3] & 0xC0 && |
2472 | i < nphysicals + (raid_ctlr_position == 0)) | |
edd16368 SC |
2473 | continue; |
2474 | ||
2475 | /* Get device type, vendor, model, device id */ | |
0b0e1d6c SC |
2476 | if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice, |
2477 | &is_OBDR)) | |
edd16368 | 2478 | continue; /* skip it if we can't talk to it. */ |
1f310bde | 2479 | figure_bus_target_lun(h, lunaddrbytes, tmpdevice); |
edd16368 SC |
2480 | this_device = currentsd[ncurrent]; |
2481 | ||
2482 | /* | |
4f4eb9f1 | 2483 | * For external target devices, we have to insert a LUN 0 which |
edd16368 SC |
2484 | * doesn't show up in CCISS_REPORT_PHYSICAL data, but there |
2485 | * is nonetheless an enclosure device there. We have to | |
2486 | * present that otherwise linux won't find anything if | |
2487 | * there is no lun 0. | |
2488 | */ | |
4f4eb9f1 | 2489 | if (add_ext_target_dev(h, tmpdevice, this_device, |
1f310bde | 2490 | lunaddrbytes, lunzerobits, |
4f4eb9f1 | 2491 | &n_ext_target_devs)) { |
edd16368 SC |
2492 | ncurrent++; |
2493 | this_device = currentsd[ncurrent]; | |
2494 | } | |
2495 | ||
2496 | *this_device = *tmpdevice; | |
edd16368 SC |
2497 | |
2498 | switch (this_device->devtype) { | |
0b0e1d6c | 2499 | case TYPE_ROM: |
edd16368 SC |
2500 | /* We don't *really* support actual CD-ROM devices, |
2501 | * just "One Button Disaster Recovery" tape drive | |
2502 | * which temporarily pretends to be a CD-ROM drive. | |
2503 | * So we check that the device is really an OBDR tape | |
2504 | * device by checking for "$DR-10" in bytes 43-48 of | |
2505 | * the inquiry data. | |
2506 | */ | |
0b0e1d6c SC |
2507 | if (is_OBDR) |
2508 | ncurrent++; | |
edd16368 SC |
2509 | break; |
2510 | case TYPE_DISK: | |
283b4a9b SC |
2511 | if (i >= nphysicals) { |
2512 | ncurrent++; | |
edd16368 | 2513 | break; |
283b4a9b SC |
2514 | } |
2515 | if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) { | |
2516 | memcpy(&this_device->ioaccel_handle, | |
2517 | &lunaddrbytes[20], | |
2518 | sizeof(this_device->ioaccel_handle)); | |
2519 | ncurrent++; | |
2520 | } | |
edd16368 SC |
2521 | break; |
2522 | case TYPE_TAPE: | |
2523 | case TYPE_MEDIUM_CHANGER: | |
2524 | ncurrent++; | |
2525 | break; | |
2526 | case TYPE_RAID: | |
2527 | /* Only present the Smartarray HBA as a RAID controller. | |
2528 | * If it's a RAID controller other than the HBA itself | |
2529 | * (an external RAID controller, MSA500 or similar) | |
2530 | * don't present it. | |
2531 | */ | |
2532 | if (!is_hba_lunid(lunaddrbytes)) | |
2533 | break; | |
2534 | ncurrent++; | |
2535 | break; | |
2536 | default: | |
2537 | break; | |
2538 | } | |
cfe5badc | 2539 | if (ncurrent >= HPSA_MAX_DEVICES) |
edd16368 SC |
2540 | break; |
2541 | } | |
2542 | adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent); | |
2543 | out: | |
2544 | kfree(tmpdevice); | |
2545 | for (i = 0; i < ndev_allocated; i++) | |
2546 | kfree(currentsd[i]); | |
2547 | kfree(currentsd); | |
edd16368 SC |
2548 | kfree(physdev_list); |
2549 | kfree(logdev_list); | |
edd16368 SC |
2550 | } |
2551 | ||
2552 | /* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci | |
2553 | * dma mapping and fills in the scatter gather entries of the | |
2554 | * hpsa command, cp. | |
2555 | */ | |
33a2ffce | 2556 | static int hpsa_scatter_gather(struct ctlr_info *h, |
edd16368 SC |
2557 | struct CommandList *cp, |
2558 | struct scsi_cmnd *cmd) | |
2559 | { | |
2560 | unsigned int len; | |
2561 | struct scatterlist *sg; | |
01a02ffc | 2562 | u64 addr64; |
33a2ffce SC |
2563 | int use_sg, i, sg_index, chained; |
2564 | struct SGDescriptor *curr_sg; | |
edd16368 | 2565 | |
33a2ffce | 2566 | BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); |
edd16368 SC |
2567 | |
2568 | use_sg = scsi_dma_map(cmd); | |
2569 | if (use_sg < 0) | |
2570 | return use_sg; | |
2571 | ||
2572 | if (!use_sg) | |
2573 | goto sglist_finished; | |
2574 | ||
33a2ffce SC |
2575 | curr_sg = cp->SG; |
2576 | chained = 0; | |
2577 | sg_index = 0; | |
edd16368 | 2578 | scsi_for_each_sg(cmd, sg, use_sg, i) { |
33a2ffce SC |
2579 | if (i == h->max_cmd_sg_entries - 1 && |
2580 | use_sg > h->max_cmd_sg_entries) { | |
2581 | chained = 1; | |
2582 | curr_sg = h->cmd_sg_list[cp->cmdindex]; | |
2583 | sg_index = 0; | |
2584 | } | |
01a02ffc | 2585 | addr64 = (u64) sg_dma_address(sg); |
edd16368 | 2586 | len = sg_dma_len(sg); |
33a2ffce SC |
2587 | curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL); |
2588 | curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL); | |
2589 | curr_sg->Len = len; | |
e1d9cbfa | 2590 | curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST; |
33a2ffce SC |
2591 | curr_sg++; |
2592 | } | |
2593 | ||
2594 | if (use_sg + chained > h->maxSG) | |
2595 | h->maxSG = use_sg + chained; | |
2596 | ||
2597 | if (chained) { | |
2598 | cp->Header.SGList = h->max_cmd_sg_entries; | |
2599 | cp->Header.SGTotal = (u16) (use_sg + 1); | |
e2bea6df SC |
2600 | if (hpsa_map_sg_chain_block(h, cp)) { |
2601 | scsi_dma_unmap(cmd); | |
2602 | return -1; | |
2603 | } | |
33a2ffce | 2604 | return 0; |
edd16368 SC |
2605 | } |
2606 | ||
2607 | sglist_finished: | |
2608 | ||
01a02ffc SC |
2609 | cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */ |
2610 | cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */ | |
edd16368 SC |
2611 | return 0; |
2612 | } | |
2613 | ||
283b4a9b SC |
2614 | #define IO_ACCEL_INELIGIBLE (1) |
2615 | static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len) | |
2616 | { | |
2617 | int is_write = 0; | |
2618 | u32 block; | |
2619 | u32 block_cnt; | |
2620 | ||
2621 | /* Perform some CDB fixups if needed using 10 byte reads/writes only */ | |
2622 | switch (cdb[0]) { | |
2623 | case WRITE_6: | |
2624 | case WRITE_12: | |
2625 | is_write = 1; | |
2626 | case READ_6: | |
2627 | case READ_12: | |
2628 | if (*cdb_len == 6) { | |
2629 | block = (((u32) cdb[2]) << 8) | cdb[3]; | |
2630 | block_cnt = cdb[4]; | |
2631 | } else { | |
2632 | BUG_ON(*cdb_len != 12); | |
2633 | block = (((u32) cdb[2]) << 24) | | |
2634 | (((u32) cdb[3]) << 16) | | |
2635 | (((u32) cdb[4]) << 8) | | |
2636 | cdb[5]; | |
2637 | block_cnt = | |
2638 | (((u32) cdb[6]) << 24) | | |
2639 | (((u32) cdb[7]) << 16) | | |
2640 | (((u32) cdb[8]) << 8) | | |
2641 | cdb[9]; | |
2642 | } | |
2643 | if (block_cnt > 0xffff) | |
2644 | return IO_ACCEL_INELIGIBLE; | |
2645 | ||
2646 | cdb[0] = is_write ? WRITE_10 : READ_10; | |
2647 | cdb[1] = 0; | |
2648 | cdb[2] = (u8) (block >> 24); | |
2649 | cdb[3] = (u8) (block >> 16); | |
2650 | cdb[4] = (u8) (block >> 8); | |
2651 | cdb[5] = (u8) (block); | |
2652 | cdb[6] = 0; | |
2653 | cdb[7] = (u8) (block_cnt >> 8); | |
2654 | cdb[8] = (u8) (block_cnt); | |
2655 | cdb[9] = 0; | |
2656 | *cdb_len = 10; | |
2657 | break; | |
2658 | } | |
2659 | return 0; | |
2660 | } | |
2661 | ||
c349775e | 2662 | static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h, |
283b4a9b SC |
2663 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, |
2664 | u8 *scsi3addr) | |
e1f7de0c MG |
2665 | { |
2666 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
e1f7de0c MG |
2667 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; |
2668 | unsigned int len; | |
2669 | unsigned int total_len = 0; | |
2670 | struct scatterlist *sg; | |
2671 | u64 addr64; | |
2672 | int use_sg, i; | |
2673 | struct SGDescriptor *curr_sg; | |
2674 | u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE; | |
2675 | ||
283b4a9b SC |
2676 | /* TODO: implement chaining support */ |
2677 | if (scsi_sg_count(cmd) > h->ioaccel_maxsg) | |
2678 | return IO_ACCEL_INELIGIBLE; | |
2679 | ||
e1f7de0c MG |
2680 | BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX); |
2681 | ||
283b4a9b SC |
2682 | if (fixup_ioaccel_cdb(cdb, &cdb_len)) |
2683 | return IO_ACCEL_INELIGIBLE; | |
2684 | ||
e1f7de0c MG |
2685 | c->cmd_type = CMD_IOACCEL1; |
2686 | ||
2687 | /* Adjust the DMA address to point to the accelerated command buffer */ | |
2688 | c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle + | |
2689 | (c->cmdindex * sizeof(*cp)); | |
2690 | BUG_ON(c->busaddr & 0x0000007F); | |
2691 | ||
2692 | use_sg = scsi_dma_map(cmd); | |
2693 | if (use_sg < 0) | |
2694 | return use_sg; | |
2695 | ||
2696 | if (use_sg) { | |
2697 | curr_sg = cp->SG; | |
2698 | scsi_for_each_sg(cmd, sg, use_sg, i) { | |
2699 | addr64 = (u64) sg_dma_address(sg); | |
2700 | len = sg_dma_len(sg); | |
2701 | total_len += len; | |
2702 | curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL); | |
2703 | curr_sg->Addr.upper = | |
2704 | (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL); | |
2705 | curr_sg->Len = len; | |
2706 | ||
2707 | if (i == (scsi_sg_count(cmd) - 1)) | |
2708 | curr_sg->Ext = HPSA_SG_LAST; | |
2709 | else | |
2710 | curr_sg->Ext = 0; /* we are not chaining */ | |
2711 | curr_sg++; | |
2712 | } | |
2713 | ||
2714 | switch (cmd->sc_data_direction) { | |
2715 | case DMA_TO_DEVICE: | |
2716 | control |= IOACCEL1_CONTROL_DATA_OUT; | |
2717 | break; | |
2718 | case DMA_FROM_DEVICE: | |
2719 | control |= IOACCEL1_CONTROL_DATA_IN; | |
2720 | break; | |
2721 | case DMA_NONE: | |
2722 | control |= IOACCEL1_CONTROL_NODATAXFER; | |
2723 | break; | |
2724 | default: | |
2725 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
2726 | cmd->sc_data_direction); | |
2727 | BUG(); | |
2728 | break; | |
2729 | } | |
2730 | } else { | |
2731 | control |= IOACCEL1_CONTROL_NODATAXFER; | |
2732 | } | |
2733 | ||
c349775e | 2734 | c->Header.SGList = use_sg; |
e1f7de0c | 2735 | /* Fill out the command structure to submit */ |
283b4a9b | 2736 | cp->dev_handle = ioaccel_handle & 0xFFFF; |
e1f7de0c MG |
2737 | cp->transfer_len = total_len; |
2738 | cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ | | |
283b4a9b | 2739 | (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK); |
e1f7de0c | 2740 | cp->control = control; |
283b4a9b SC |
2741 | memcpy(cp->CDB, cdb, cdb_len); |
2742 | memcpy(cp->CISS_LUN, scsi3addr, 8); | |
c349775e | 2743 | /* Tag was already set at init time. */ |
283b4a9b | 2744 | enqueue_cmd_and_start_io(h, c); |
e1f7de0c MG |
2745 | return 0; |
2746 | } | |
edd16368 | 2747 | |
283b4a9b SC |
2748 | /* |
2749 | * Queue a command directly to a device behind the controller using the | |
2750 | * I/O accelerator path. | |
2751 | */ | |
2752 | static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h, | |
2753 | struct CommandList *c) | |
2754 | { | |
2755 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
2756 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
2757 | ||
2758 | return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle, | |
2759 | cmd->cmnd, cmd->cmd_len, dev->scsi3addr); | |
2760 | } | |
2761 | ||
c349775e ST |
2762 | static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h, |
2763 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, | |
2764 | u8 *scsi3addr) | |
2765 | { | |
2766 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
2767 | struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
2768 | struct ioaccel2_sg_element *curr_sg; | |
2769 | int use_sg, i; | |
2770 | struct scatterlist *sg; | |
2771 | u64 addr64; | |
2772 | u32 len; | |
2773 | u32 total_len = 0; | |
2774 | ||
2775 | if (scsi_sg_count(cmd) > h->ioaccel_maxsg) | |
2776 | return IO_ACCEL_INELIGIBLE; | |
2777 | ||
2778 | if (fixup_ioaccel_cdb(cdb, &cdb_len)) | |
2779 | return IO_ACCEL_INELIGIBLE; | |
2780 | c->cmd_type = CMD_IOACCEL2; | |
2781 | /* Adjust the DMA address to point to the accelerated command buffer */ | |
2782 | c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle + | |
2783 | (c->cmdindex * sizeof(*cp)); | |
2784 | BUG_ON(c->busaddr & 0x0000007F); | |
2785 | ||
2786 | memset(cp, 0, sizeof(*cp)); | |
2787 | cp->IU_type = IOACCEL2_IU_TYPE; | |
2788 | ||
2789 | use_sg = scsi_dma_map(cmd); | |
2790 | if (use_sg < 0) | |
2791 | return use_sg; | |
2792 | ||
2793 | if (use_sg) { | |
2794 | BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES); | |
2795 | curr_sg = cp->sg; | |
2796 | scsi_for_each_sg(cmd, sg, use_sg, i) { | |
2797 | addr64 = (u64) sg_dma_address(sg); | |
2798 | len = sg_dma_len(sg); | |
2799 | total_len += len; | |
2800 | curr_sg->address = cpu_to_le64(addr64); | |
2801 | curr_sg->length = cpu_to_le32(len); | |
2802 | curr_sg->reserved[0] = 0; | |
2803 | curr_sg->reserved[1] = 0; | |
2804 | curr_sg->reserved[2] = 0; | |
2805 | curr_sg->chain_indicator = 0; | |
2806 | curr_sg++; | |
2807 | } | |
2808 | ||
2809 | switch (cmd->sc_data_direction) { | |
2810 | case DMA_TO_DEVICE: | |
2811 | cp->direction = IOACCEL2_DIR_DATA_OUT; | |
2812 | break; | |
2813 | case DMA_FROM_DEVICE: | |
2814 | cp->direction = IOACCEL2_DIR_DATA_IN; | |
2815 | break; | |
2816 | case DMA_NONE: | |
2817 | cp->direction = IOACCEL2_DIR_NO_DATA; | |
2818 | break; | |
2819 | default: | |
2820 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
2821 | cmd->sc_data_direction); | |
2822 | BUG(); | |
2823 | break; | |
2824 | } | |
2825 | } else { | |
2826 | cp->direction = IOACCEL2_DIR_NO_DATA; | |
2827 | } | |
2828 | cp->scsi_nexus = ioaccel_handle; | |
2829 | cp->Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT) | | |
2830 | DIRECT_LOOKUP_BIT; | |
2831 | memcpy(cp->cdb, cdb, sizeof(cp->cdb)); | |
2832 | memset(cp->cciss_lun, 0, sizeof(cp->cciss_lun)); | |
2833 | cp->cmd_priority_task_attr = 0; | |
2834 | ||
2835 | /* fill in sg elements */ | |
2836 | cp->sg_count = (u8) use_sg; | |
2837 | ||
2838 | cp->data_len = cpu_to_le32(total_len); | |
2839 | cp->err_ptr = cpu_to_le64(c->busaddr + | |
2840 | offsetof(struct io_accel2_cmd, error_data)); | |
2841 | cp->err_len = cpu_to_le32((u32) sizeof(cp->error_data)); | |
2842 | ||
2843 | enqueue_cmd_and_start_io(h, c); | |
2844 | return 0; | |
2845 | } | |
2846 | ||
2847 | /* | |
2848 | * Queue a command to the correct I/O accelerator path. | |
2849 | */ | |
2850 | static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, | |
2851 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, | |
2852 | u8 *scsi3addr) | |
2853 | { | |
2854 | if (h->transMethod & CFGTBL_Trans_io_accel1) | |
2855 | return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle, | |
2856 | cdb, cdb_len, scsi3addr); | |
2857 | else | |
2858 | return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle, | |
2859 | cdb, cdb_len, scsi3addr); | |
2860 | } | |
2861 | ||
283b4a9b SC |
2862 | /* |
2863 | * Attempt to perform offload RAID mapping for a logical volume I/O. | |
2864 | */ | |
2865 | static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h, | |
2866 | struct CommandList *c) | |
2867 | { | |
2868 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
2869 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
2870 | struct raid_map_data *map = &dev->raid_map; | |
2871 | struct raid_map_disk_data *dd = &map->data[0]; | |
2872 | int is_write = 0; | |
2873 | u32 map_index; | |
2874 | u64 first_block, last_block; | |
2875 | u32 block_cnt; | |
2876 | u32 blocks_per_row; | |
2877 | u64 first_row, last_row; | |
2878 | u32 first_row_offset, last_row_offset; | |
2879 | u32 first_column, last_column; | |
2880 | u32 map_row; | |
2881 | u32 disk_handle; | |
2882 | u64 disk_block; | |
2883 | u32 disk_block_cnt; | |
2884 | u8 cdb[16]; | |
2885 | u8 cdb_len; | |
2886 | #if BITS_PER_LONG == 32 | |
2887 | u64 tmpdiv; | |
2888 | #endif | |
2889 | ||
2890 | BUG_ON(!(dev->offload_config && dev->offload_enabled)); | |
2891 | ||
2892 | /* check for valid opcode, get LBA and block count */ | |
2893 | switch (cmd->cmnd[0]) { | |
2894 | case WRITE_6: | |
2895 | is_write = 1; | |
2896 | case READ_6: | |
2897 | first_block = | |
2898 | (((u64) cmd->cmnd[2]) << 8) | | |
2899 | cmd->cmnd[3]; | |
2900 | block_cnt = cmd->cmnd[4]; | |
2901 | break; | |
2902 | case WRITE_10: | |
2903 | is_write = 1; | |
2904 | case READ_10: | |
2905 | first_block = | |
2906 | (((u64) cmd->cmnd[2]) << 24) | | |
2907 | (((u64) cmd->cmnd[3]) << 16) | | |
2908 | (((u64) cmd->cmnd[4]) << 8) | | |
2909 | cmd->cmnd[5]; | |
2910 | block_cnt = | |
2911 | (((u32) cmd->cmnd[7]) << 8) | | |
2912 | cmd->cmnd[8]; | |
2913 | break; | |
2914 | case WRITE_12: | |
2915 | is_write = 1; | |
2916 | case READ_12: | |
2917 | first_block = | |
2918 | (((u64) cmd->cmnd[2]) << 24) | | |
2919 | (((u64) cmd->cmnd[3]) << 16) | | |
2920 | (((u64) cmd->cmnd[4]) << 8) | | |
2921 | cmd->cmnd[5]; | |
2922 | block_cnt = | |
2923 | (((u32) cmd->cmnd[6]) << 24) | | |
2924 | (((u32) cmd->cmnd[7]) << 16) | | |
2925 | (((u32) cmd->cmnd[8]) << 8) | | |
2926 | cmd->cmnd[9]; | |
2927 | break; | |
2928 | case WRITE_16: | |
2929 | is_write = 1; | |
2930 | case READ_16: | |
2931 | first_block = | |
2932 | (((u64) cmd->cmnd[2]) << 56) | | |
2933 | (((u64) cmd->cmnd[3]) << 48) | | |
2934 | (((u64) cmd->cmnd[4]) << 40) | | |
2935 | (((u64) cmd->cmnd[5]) << 32) | | |
2936 | (((u64) cmd->cmnd[6]) << 24) | | |
2937 | (((u64) cmd->cmnd[7]) << 16) | | |
2938 | (((u64) cmd->cmnd[8]) << 8) | | |
2939 | cmd->cmnd[9]; | |
2940 | block_cnt = | |
2941 | (((u32) cmd->cmnd[10]) << 24) | | |
2942 | (((u32) cmd->cmnd[11]) << 16) | | |
2943 | (((u32) cmd->cmnd[12]) << 8) | | |
2944 | cmd->cmnd[13]; | |
2945 | break; | |
2946 | default: | |
2947 | return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */ | |
2948 | } | |
2949 | BUG_ON(block_cnt == 0); | |
2950 | last_block = first_block + block_cnt - 1; | |
2951 | ||
2952 | /* check for write to non-RAID-0 */ | |
2953 | if (is_write && dev->raid_level != 0) | |
2954 | return IO_ACCEL_INELIGIBLE; | |
2955 | ||
2956 | /* check for invalid block or wraparound */ | |
2957 | if (last_block >= map->volume_blk_cnt || last_block < first_block) | |
2958 | return IO_ACCEL_INELIGIBLE; | |
2959 | ||
2960 | /* calculate stripe information for the request */ | |
2961 | blocks_per_row = map->data_disks_per_row * map->strip_size; | |
2962 | #if BITS_PER_LONG == 32 | |
2963 | tmpdiv = first_block; | |
2964 | (void) do_div(tmpdiv, blocks_per_row); | |
2965 | first_row = tmpdiv; | |
2966 | tmpdiv = last_block; | |
2967 | (void) do_div(tmpdiv, blocks_per_row); | |
2968 | last_row = tmpdiv; | |
2969 | first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); | |
2970 | last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); | |
2971 | tmpdiv = first_row_offset; | |
2972 | (void) do_div(tmpdiv, map->strip_size); | |
2973 | first_column = tmpdiv; | |
2974 | tmpdiv = last_row_offset; | |
2975 | (void) do_div(tmpdiv, map->strip_size); | |
2976 | last_column = tmpdiv; | |
2977 | #else | |
2978 | first_row = first_block / blocks_per_row; | |
2979 | last_row = last_block / blocks_per_row; | |
2980 | first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); | |
2981 | last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); | |
2982 | first_column = first_row_offset / map->strip_size; | |
2983 | last_column = last_row_offset / map->strip_size; | |
2984 | #endif | |
2985 | ||
2986 | /* if this isn't a single row/column then give to the controller */ | |
2987 | if ((first_row != last_row) || (first_column != last_column)) | |
2988 | return IO_ACCEL_INELIGIBLE; | |
2989 | ||
2990 | /* proceeding with driver mapping */ | |
2991 | map_row = ((u32)(first_row >> map->parity_rotation_shift)) % | |
2992 | map->row_cnt; | |
2993 | map_index = (map_row * (map->data_disks_per_row + | |
2994 | map->metadata_disks_per_row)) + first_column; | |
2995 | if (dev->raid_level == 2) { | |
2996 | /* simple round-robin balancing of RAID 1+0 reads across | |
2997 | * primary and mirror members. this is appropriate for SSD | |
2998 | * but not optimal for HDD. | |
2999 | */ | |
3000 | if (dev->offload_to_mirror) | |
3001 | map_index += map->data_disks_per_row; | |
3002 | dev->offload_to_mirror = !dev->offload_to_mirror; | |
3003 | } | |
3004 | disk_handle = dd[map_index].ioaccel_handle; | |
3005 | disk_block = map->disk_starting_blk + (first_row * map->strip_size) + | |
3006 | (first_row_offset - (first_column * map->strip_size)); | |
3007 | disk_block_cnt = block_cnt; | |
3008 | ||
3009 | /* handle differing logical/physical block sizes */ | |
3010 | if (map->phys_blk_shift) { | |
3011 | disk_block <<= map->phys_blk_shift; | |
3012 | disk_block_cnt <<= map->phys_blk_shift; | |
3013 | } | |
3014 | BUG_ON(disk_block_cnt > 0xffff); | |
3015 | ||
3016 | /* build the new CDB for the physical disk I/O */ | |
3017 | if (disk_block > 0xffffffff) { | |
3018 | cdb[0] = is_write ? WRITE_16 : READ_16; | |
3019 | cdb[1] = 0; | |
3020 | cdb[2] = (u8) (disk_block >> 56); | |
3021 | cdb[3] = (u8) (disk_block >> 48); | |
3022 | cdb[4] = (u8) (disk_block >> 40); | |
3023 | cdb[5] = (u8) (disk_block >> 32); | |
3024 | cdb[6] = (u8) (disk_block >> 24); | |
3025 | cdb[7] = (u8) (disk_block >> 16); | |
3026 | cdb[8] = (u8) (disk_block >> 8); | |
3027 | cdb[9] = (u8) (disk_block); | |
3028 | cdb[10] = (u8) (disk_block_cnt >> 24); | |
3029 | cdb[11] = (u8) (disk_block_cnt >> 16); | |
3030 | cdb[12] = (u8) (disk_block_cnt >> 8); | |
3031 | cdb[13] = (u8) (disk_block_cnt); | |
3032 | cdb[14] = 0; | |
3033 | cdb[15] = 0; | |
3034 | cdb_len = 16; | |
3035 | } else { | |
3036 | cdb[0] = is_write ? WRITE_10 : READ_10; | |
3037 | cdb[1] = 0; | |
3038 | cdb[2] = (u8) (disk_block >> 24); | |
3039 | cdb[3] = (u8) (disk_block >> 16); | |
3040 | cdb[4] = (u8) (disk_block >> 8); | |
3041 | cdb[5] = (u8) (disk_block); | |
3042 | cdb[6] = 0; | |
3043 | cdb[7] = (u8) (disk_block_cnt >> 8); | |
3044 | cdb[8] = (u8) (disk_block_cnt); | |
3045 | cdb[9] = 0; | |
3046 | cdb_len = 10; | |
3047 | } | |
3048 | return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len, | |
3049 | dev->scsi3addr); | |
3050 | } | |
3051 | ||
f281233d | 3052 | static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd, |
edd16368 SC |
3053 | void (*done)(struct scsi_cmnd *)) |
3054 | { | |
3055 | struct ctlr_info *h; | |
3056 | struct hpsa_scsi_dev_t *dev; | |
3057 | unsigned char scsi3addr[8]; | |
3058 | struct CommandList *c; | |
3059 | unsigned long flags; | |
283b4a9b | 3060 | int rc = 0; |
edd16368 SC |
3061 | |
3062 | /* Get the ptr to our adapter structure out of cmd->host. */ | |
3063 | h = sdev_to_hba(cmd->device); | |
3064 | dev = cmd->device->hostdata; | |
3065 | if (!dev) { | |
3066 | cmd->result = DID_NO_CONNECT << 16; | |
3067 | done(cmd); | |
3068 | return 0; | |
3069 | } | |
3070 | memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr)); | |
3071 | ||
edd16368 | 3072 | spin_lock_irqsave(&h->lock, flags); |
a0c12413 SC |
3073 | if (unlikely(h->lockup_detected)) { |
3074 | spin_unlock_irqrestore(&h->lock, flags); | |
3075 | cmd->result = DID_ERROR << 16; | |
3076 | done(cmd); | |
3077 | return 0; | |
3078 | } | |
edd16368 | 3079 | spin_unlock_irqrestore(&h->lock, flags); |
e16a33ad | 3080 | c = cmd_alloc(h); |
edd16368 SC |
3081 | if (c == NULL) { /* trouble... */ |
3082 | dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n"); | |
3083 | return SCSI_MLQUEUE_HOST_BUSY; | |
3084 | } | |
3085 | ||
3086 | /* Fill in the command list header */ | |
3087 | ||
3088 | cmd->scsi_done = done; /* save this for use by completion code */ | |
3089 | ||
3090 | /* save c in case we have to abort it */ | |
3091 | cmd->host_scribble = (unsigned char *) c; | |
3092 | ||
3093 | c->cmd_type = CMD_SCSI; | |
3094 | c->scsi_cmd = cmd; | |
e1f7de0c | 3095 | |
283b4a9b SC |
3096 | /* Call alternate submit routine for I/O accelerated commands. |
3097 | * Retries always go down the normal I/O path. | |
3098 | */ | |
3099 | if (likely(cmd->retries == 0 && | |
3100 | cmd->request->cmd_type == REQ_TYPE_FS)) { | |
3101 | if (dev->offload_enabled) { | |
3102 | rc = hpsa_scsi_ioaccel_raid_map(h, c); | |
3103 | if (rc == 0) | |
3104 | return 0; /* Sent on ioaccel path */ | |
3105 | if (rc < 0) { /* scsi_dma_map failed. */ | |
3106 | cmd_free(h, c); | |
3107 | return SCSI_MLQUEUE_HOST_BUSY; | |
3108 | } | |
3109 | } else if (dev->ioaccel_handle) { | |
3110 | rc = hpsa_scsi_ioaccel_direct_map(h, c); | |
3111 | if (rc == 0) | |
3112 | return 0; /* Sent on direct map path */ | |
3113 | if (rc < 0) { /* scsi_dma_map failed. */ | |
3114 | cmd_free(h, c); | |
3115 | return SCSI_MLQUEUE_HOST_BUSY; | |
3116 | } | |
3117 | } | |
3118 | } | |
e1f7de0c | 3119 | |
edd16368 SC |
3120 | c->Header.ReplyQueue = 0; /* unused in simple mode */ |
3121 | memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8); | |
303932fd DB |
3122 | c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT); |
3123 | c->Header.Tag.lower |= DIRECT_LOOKUP_BIT; | |
edd16368 SC |
3124 | |
3125 | /* Fill in the request block... */ | |
3126 | ||
3127 | c->Request.Timeout = 0; | |
3128 | memset(c->Request.CDB, 0, sizeof(c->Request.CDB)); | |
3129 | BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB)); | |
3130 | c->Request.CDBLen = cmd->cmd_len; | |
3131 | memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len); | |
3132 | c->Request.Type.Type = TYPE_CMD; | |
3133 | c->Request.Type.Attribute = ATTR_SIMPLE; | |
3134 | switch (cmd->sc_data_direction) { | |
3135 | case DMA_TO_DEVICE: | |
3136 | c->Request.Type.Direction = XFER_WRITE; | |
3137 | break; | |
3138 | case DMA_FROM_DEVICE: | |
3139 | c->Request.Type.Direction = XFER_READ; | |
3140 | break; | |
3141 | case DMA_NONE: | |
3142 | c->Request.Type.Direction = XFER_NONE; | |
3143 | break; | |
3144 | case DMA_BIDIRECTIONAL: | |
3145 | /* This can happen if a buggy application does a scsi passthru | |
3146 | * and sets both inlen and outlen to non-zero. ( see | |
3147 | * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() ) | |
3148 | */ | |
3149 | ||
3150 | c->Request.Type.Direction = XFER_RSVD; | |
3151 | /* This is technically wrong, and hpsa controllers should | |
3152 | * reject it with CMD_INVALID, which is the most correct | |
3153 | * response, but non-fibre backends appear to let it | |
3154 | * slide by, and give the same results as if this field | |
3155 | * were set correctly. Either way is acceptable for | |
3156 | * our purposes here. | |
3157 | */ | |
3158 | ||
3159 | break; | |
3160 | ||
3161 | default: | |
3162 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
3163 | cmd->sc_data_direction); | |
3164 | BUG(); | |
3165 | break; | |
3166 | } | |
3167 | ||
33a2ffce | 3168 | if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */ |
edd16368 SC |
3169 | cmd_free(h, c); |
3170 | return SCSI_MLQUEUE_HOST_BUSY; | |
3171 | } | |
3172 | enqueue_cmd_and_start_io(h, c); | |
3173 | /* the cmd'll come back via intr handler in complete_scsi_command() */ | |
3174 | return 0; | |
3175 | } | |
3176 | ||
f281233d JG |
3177 | static DEF_SCSI_QCMD(hpsa_scsi_queue_command) |
3178 | ||
5f389360 SC |
3179 | static int do_not_scan_if_controller_locked_up(struct ctlr_info *h) |
3180 | { | |
3181 | unsigned long flags; | |
3182 | ||
3183 | /* | |
3184 | * Don't let rescans be initiated on a controller known | |
3185 | * to be locked up. If the controller locks up *during* | |
3186 | * a rescan, that thread is probably hosed, but at least | |
3187 | * we can prevent new rescan threads from piling up on a | |
3188 | * locked up controller. | |
3189 | */ | |
3190 | spin_lock_irqsave(&h->lock, flags); | |
3191 | if (unlikely(h->lockup_detected)) { | |
3192 | spin_unlock_irqrestore(&h->lock, flags); | |
3193 | spin_lock_irqsave(&h->scan_lock, flags); | |
3194 | h->scan_finished = 1; | |
3195 | wake_up_all(&h->scan_wait_queue); | |
3196 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
3197 | return 1; | |
3198 | } | |
3199 | spin_unlock_irqrestore(&h->lock, flags); | |
3200 | return 0; | |
3201 | } | |
3202 | ||
a08a8471 SC |
3203 | static void hpsa_scan_start(struct Scsi_Host *sh) |
3204 | { | |
3205 | struct ctlr_info *h = shost_to_hba(sh); | |
3206 | unsigned long flags; | |
3207 | ||
5f389360 SC |
3208 | if (do_not_scan_if_controller_locked_up(h)) |
3209 | return; | |
3210 | ||
a08a8471 SC |
3211 | /* wait until any scan already in progress is finished. */ |
3212 | while (1) { | |
3213 | spin_lock_irqsave(&h->scan_lock, flags); | |
3214 | if (h->scan_finished) | |
3215 | break; | |
3216 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
3217 | wait_event(h->scan_wait_queue, h->scan_finished); | |
3218 | /* Note: We don't need to worry about a race between this | |
3219 | * thread and driver unload because the midlayer will | |
3220 | * have incremented the reference count, so unload won't | |
3221 | * happen if we're in here. | |
3222 | */ | |
3223 | } | |
3224 | h->scan_finished = 0; /* mark scan as in progress */ | |
3225 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
3226 | ||
5f389360 SC |
3227 | if (do_not_scan_if_controller_locked_up(h)) |
3228 | return; | |
3229 | ||
a08a8471 SC |
3230 | hpsa_update_scsi_devices(h, h->scsi_host->host_no); |
3231 | ||
3232 | spin_lock_irqsave(&h->scan_lock, flags); | |
3233 | h->scan_finished = 1; /* mark scan as finished. */ | |
3234 | wake_up_all(&h->scan_wait_queue); | |
3235 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
3236 | } | |
3237 | ||
3238 | static int hpsa_scan_finished(struct Scsi_Host *sh, | |
3239 | unsigned long elapsed_time) | |
3240 | { | |
3241 | struct ctlr_info *h = shost_to_hba(sh); | |
3242 | unsigned long flags; | |
3243 | int finished; | |
3244 | ||
3245 | spin_lock_irqsave(&h->scan_lock, flags); | |
3246 | finished = h->scan_finished; | |
3247 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
3248 | return finished; | |
3249 | } | |
3250 | ||
667e23d4 SC |
3251 | static int hpsa_change_queue_depth(struct scsi_device *sdev, |
3252 | int qdepth, int reason) | |
3253 | { | |
3254 | struct ctlr_info *h = sdev_to_hba(sdev); | |
3255 | ||
3256 | if (reason != SCSI_QDEPTH_DEFAULT) | |
3257 | return -ENOTSUPP; | |
3258 | ||
3259 | if (qdepth < 1) | |
3260 | qdepth = 1; | |
3261 | else | |
3262 | if (qdepth > h->nr_cmds) | |
3263 | qdepth = h->nr_cmds; | |
3264 | scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth); | |
3265 | return sdev->queue_depth; | |
3266 | } | |
3267 | ||
edd16368 SC |
3268 | static void hpsa_unregister_scsi(struct ctlr_info *h) |
3269 | { | |
3270 | /* we are being forcibly unloaded, and may not refuse. */ | |
3271 | scsi_remove_host(h->scsi_host); | |
3272 | scsi_host_put(h->scsi_host); | |
3273 | h->scsi_host = NULL; | |
3274 | } | |
3275 | ||
3276 | static int hpsa_register_scsi(struct ctlr_info *h) | |
3277 | { | |
b705690d SC |
3278 | struct Scsi_Host *sh; |
3279 | int error; | |
edd16368 | 3280 | |
b705690d SC |
3281 | sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h)); |
3282 | if (sh == NULL) | |
3283 | goto fail; | |
3284 | ||
3285 | sh->io_port = 0; | |
3286 | sh->n_io_port = 0; | |
3287 | sh->this_id = -1; | |
3288 | sh->max_channel = 3; | |
3289 | sh->max_cmd_len = MAX_COMMAND_SIZE; | |
3290 | sh->max_lun = HPSA_MAX_LUN; | |
3291 | sh->max_id = HPSA_MAX_LUN; | |
3292 | sh->can_queue = h->nr_cmds; | |
3293 | sh->cmd_per_lun = h->nr_cmds; | |
3294 | sh->sg_tablesize = h->maxsgentries; | |
3295 | h->scsi_host = sh; | |
3296 | sh->hostdata[0] = (unsigned long) h; | |
3297 | sh->irq = h->intr[h->intr_mode]; | |
3298 | sh->unique_id = sh->irq; | |
3299 | error = scsi_add_host(sh, &h->pdev->dev); | |
3300 | if (error) | |
3301 | goto fail_host_put; | |
3302 | scsi_scan_host(sh); | |
3303 | return 0; | |
3304 | ||
3305 | fail_host_put: | |
3306 | dev_err(&h->pdev->dev, "%s: scsi_add_host" | |
3307 | " failed for controller %d\n", __func__, h->ctlr); | |
3308 | scsi_host_put(sh); | |
3309 | return error; | |
3310 | fail: | |
3311 | dev_err(&h->pdev->dev, "%s: scsi_host_alloc" | |
3312 | " failed for controller %d\n", __func__, h->ctlr); | |
3313 | return -ENOMEM; | |
edd16368 SC |
3314 | } |
3315 | ||
3316 | static int wait_for_device_to_become_ready(struct ctlr_info *h, | |
3317 | unsigned char lunaddr[]) | |
3318 | { | |
3319 | int rc = 0; | |
3320 | int count = 0; | |
3321 | int waittime = 1; /* seconds */ | |
3322 | struct CommandList *c; | |
3323 | ||
3324 | c = cmd_special_alloc(h); | |
3325 | if (!c) { | |
3326 | dev_warn(&h->pdev->dev, "out of memory in " | |
3327 | "wait_for_device_to_become_ready.\n"); | |
3328 | return IO_ERROR; | |
3329 | } | |
3330 | ||
3331 | /* Send test unit ready until device ready, or give up. */ | |
3332 | while (count < HPSA_TUR_RETRY_LIMIT) { | |
3333 | ||
3334 | /* Wait for a bit. do this first, because if we send | |
3335 | * the TUR right away, the reset will just abort it. | |
3336 | */ | |
3337 | msleep(1000 * waittime); | |
3338 | count++; | |
3339 | ||
3340 | /* Increase wait time with each try, up to a point. */ | |
3341 | if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS) | |
3342 | waittime = waittime * 2; | |
3343 | ||
a2dac136 SC |
3344 | /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */ |
3345 | (void) fill_cmd(c, TEST_UNIT_READY, h, | |
3346 | NULL, 0, 0, lunaddr, TYPE_CMD); | |
edd16368 SC |
3347 | hpsa_scsi_do_simple_cmd_core(h, c); |
3348 | /* no unmap needed here because no data xfer. */ | |
3349 | ||
3350 | if (c->err_info->CommandStatus == CMD_SUCCESS) | |
3351 | break; | |
3352 | ||
3353 | if (c->err_info->CommandStatus == CMD_TARGET_STATUS && | |
3354 | c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION && | |
3355 | (c->err_info->SenseInfo[2] == NO_SENSE || | |
3356 | c->err_info->SenseInfo[2] == UNIT_ATTENTION)) | |
3357 | break; | |
3358 | ||
3359 | dev_warn(&h->pdev->dev, "waiting %d secs " | |
3360 | "for device to become ready.\n", waittime); | |
3361 | rc = 1; /* device not ready. */ | |
3362 | } | |
3363 | ||
3364 | if (rc) | |
3365 | dev_warn(&h->pdev->dev, "giving up on device.\n"); | |
3366 | else | |
3367 | dev_warn(&h->pdev->dev, "device is ready.\n"); | |
3368 | ||
3369 | cmd_special_free(h, c); | |
3370 | return rc; | |
3371 | } | |
3372 | ||
3373 | /* Need at least one of these error handlers to keep ../scsi/hosts.c from | |
3374 | * complaining. Doing a host- or bus-reset can't do anything good here. | |
3375 | */ | |
3376 | static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd) | |
3377 | { | |
3378 | int rc; | |
3379 | struct ctlr_info *h; | |
3380 | struct hpsa_scsi_dev_t *dev; | |
3381 | ||
3382 | /* find the controller to which the command to be aborted was sent */ | |
3383 | h = sdev_to_hba(scsicmd->device); | |
3384 | if (h == NULL) /* paranoia */ | |
3385 | return FAILED; | |
edd16368 SC |
3386 | dev = scsicmd->device->hostdata; |
3387 | if (!dev) { | |
3388 | dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: " | |
3389 | "device lookup failed.\n"); | |
3390 | return FAILED; | |
3391 | } | |
d416b0c7 SC |
3392 | dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n", |
3393 | h->scsi_host->host_no, dev->bus, dev->target, dev->lun); | |
edd16368 | 3394 | /* send a reset to the SCSI LUN which the command was sent to */ |
bf711ac6 | 3395 | rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN); |
edd16368 SC |
3396 | if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0) |
3397 | return SUCCESS; | |
3398 | ||
3399 | dev_warn(&h->pdev->dev, "resetting device failed.\n"); | |
3400 | return FAILED; | |
3401 | } | |
3402 | ||
6cba3f19 SC |
3403 | static void swizzle_abort_tag(u8 *tag) |
3404 | { | |
3405 | u8 original_tag[8]; | |
3406 | ||
3407 | memcpy(original_tag, tag, 8); | |
3408 | tag[0] = original_tag[3]; | |
3409 | tag[1] = original_tag[2]; | |
3410 | tag[2] = original_tag[1]; | |
3411 | tag[3] = original_tag[0]; | |
3412 | tag[4] = original_tag[7]; | |
3413 | tag[5] = original_tag[6]; | |
3414 | tag[6] = original_tag[5]; | |
3415 | tag[7] = original_tag[4]; | |
3416 | } | |
3417 | ||
17eb87d2 ST |
3418 | static void hpsa_get_tag(struct ctlr_info *h, |
3419 | struct CommandList *c, u32 *taglower, u32 *tagupper) | |
3420 | { | |
3421 | if (c->cmd_type == CMD_IOACCEL1) { | |
3422 | struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *) | |
3423 | &h->ioaccel_cmd_pool[c->cmdindex]; | |
3424 | *tagupper = cm1->Tag.upper; | |
3425 | *taglower = cm1->Tag.lower; | |
3426 | } else { | |
3427 | *tagupper = c->Header.Tag.upper; | |
3428 | *taglower = c->Header.Tag.lower; | |
3429 | } | |
3430 | } | |
3431 | ||
75167d2c | 3432 | static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr, |
6cba3f19 | 3433 | struct CommandList *abort, int swizzle) |
75167d2c SC |
3434 | { |
3435 | int rc = IO_OK; | |
3436 | struct CommandList *c; | |
3437 | struct ErrorInfo *ei; | |
17eb87d2 | 3438 | u32 tagupper, taglower; |
75167d2c SC |
3439 | |
3440 | c = cmd_special_alloc(h); | |
3441 | if (c == NULL) { /* trouble... */ | |
3442 | dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n"); | |
3443 | return -ENOMEM; | |
3444 | } | |
3445 | ||
a2dac136 SC |
3446 | /* fill_cmd can't fail here, no buffer to map */ |
3447 | (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort, | |
3448 | 0, 0, scsi3addr, TYPE_MSG); | |
6cba3f19 SC |
3449 | if (swizzle) |
3450 | swizzle_abort_tag(&c->Request.CDB[4]); | |
75167d2c | 3451 | hpsa_scsi_do_simple_cmd_core(h, c); |
17eb87d2 | 3452 | hpsa_get_tag(h, abort, &taglower, &tagupper); |
75167d2c | 3453 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n", |
17eb87d2 | 3454 | __func__, tagupper, taglower); |
75167d2c SC |
3455 | /* no unmap needed here because no data xfer. */ |
3456 | ||
3457 | ei = c->err_info; | |
3458 | switch (ei->CommandStatus) { | |
3459 | case CMD_SUCCESS: | |
3460 | break; | |
3461 | case CMD_UNABORTABLE: /* Very common, don't make noise. */ | |
3462 | rc = -1; | |
3463 | break; | |
3464 | default: | |
3465 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n", | |
17eb87d2 | 3466 | __func__, tagupper, taglower); |
75167d2c SC |
3467 | hpsa_scsi_interpret_error(c); |
3468 | rc = -1; | |
3469 | break; | |
3470 | } | |
3471 | cmd_special_free(h, c); | |
3472 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__, | |
3473 | abort->Header.Tag.upper, abort->Header.Tag.lower); | |
3474 | return rc; | |
3475 | } | |
3476 | ||
3477 | /* | |
3478 | * hpsa_find_cmd_in_queue | |
3479 | * | |
3480 | * Used to determine whether a command (find) is still present | |
3481 | * in queue_head. Optionally excludes the last element of queue_head. | |
3482 | * | |
3483 | * This is used to avoid unnecessary aborts. Commands in h->reqQ have | |
3484 | * not yet been submitted, and so can be aborted by the driver without | |
3485 | * sending an abort to the hardware. | |
3486 | * | |
3487 | * Returns pointer to command if found in queue, NULL otherwise. | |
3488 | */ | |
3489 | static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h, | |
3490 | struct scsi_cmnd *find, struct list_head *queue_head) | |
3491 | { | |
3492 | unsigned long flags; | |
3493 | struct CommandList *c = NULL; /* ptr into cmpQ */ | |
3494 | ||
3495 | if (!find) | |
3496 | return 0; | |
3497 | spin_lock_irqsave(&h->lock, flags); | |
3498 | list_for_each_entry(c, queue_head, list) { | |
3499 | if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */ | |
3500 | continue; | |
3501 | if (c->scsi_cmd == find) { | |
3502 | spin_unlock_irqrestore(&h->lock, flags); | |
3503 | return c; | |
3504 | } | |
3505 | } | |
3506 | spin_unlock_irqrestore(&h->lock, flags); | |
3507 | return NULL; | |
3508 | } | |
3509 | ||
6cba3f19 SC |
3510 | static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h, |
3511 | u8 *tag, struct list_head *queue_head) | |
3512 | { | |
3513 | unsigned long flags; | |
3514 | struct CommandList *c; | |
3515 | ||
3516 | spin_lock_irqsave(&h->lock, flags); | |
3517 | list_for_each_entry(c, queue_head, list) { | |
3518 | if (memcmp(&c->Header.Tag, tag, 8) != 0) | |
3519 | continue; | |
3520 | spin_unlock_irqrestore(&h->lock, flags); | |
3521 | return c; | |
3522 | } | |
3523 | spin_unlock_irqrestore(&h->lock, flags); | |
3524 | return NULL; | |
3525 | } | |
3526 | ||
3527 | /* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to | |
3528 | * tell which kind we're dealing with, so we send the abort both ways. There | |
3529 | * shouldn't be any collisions between swizzled and unswizzled tags due to the | |
3530 | * way we construct our tags but we check anyway in case the assumptions which | |
3531 | * make this true someday become false. | |
3532 | */ | |
3533 | static int hpsa_send_abort_both_ways(struct ctlr_info *h, | |
3534 | unsigned char *scsi3addr, struct CommandList *abort) | |
3535 | { | |
3536 | u8 swizzled_tag[8]; | |
3537 | struct CommandList *c; | |
3538 | int rc = 0, rc2 = 0; | |
3539 | ||
3540 | /* we do not expect to find the swizzled tag in our queue, but | |
3541 | * check anyway just to be sure the assumptions which make this | |
3542 | * the case haven't become wrong. | |
3543 | */ | |
3544 | memcpy(swizzled_tag, &abort->Request.CDB[4], 8); | |
3545 | swizzle_abort_tag(swizzled_tag); | |
3546 | c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ); | |
3547 | if (c != NULL) { | |
3548 | dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n"); | |
3549 | return hpsa_send_abort(h, scsi3addr, abort, 0); | |
3550 | } | |
3551 | rc = hpsa_send_abort(h, scsi3addr, abort, 0); | |
3552 | ||
3553 | /* if the command is still in our queue, we can't conclude that it was | |
3554 | * aborted (it might have just completed normally) but in any case | |
3555 | * we don't need to try to abort it another way. | |
3556 | */ | |
3557 | c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ); | |
3558 | if (c) | |
3559 | rc2 = hpsa_send_abort(h, scsi3addr, abort, 1); | |
3560 | return rc && rc2; | |
3561 | } | |
3562 | ||
75167d2c SC |
3563 | /* Send an abort for the specified command. |
3564 | * If the device and controller support it, | |
3565 | * send a task abort request. | |
3566 | */ | |
3567 | static int hpsa_eh_abort_handler(struct scsi_cmnd *sc) | |
3568 | { | |
3569 | ||
3570 | int i, rc; | |
3571 | struct ctlr_info *h; | |
3572 | struct hpsa_scsi_dev_t *dev; | |
3573 | struct CommandList *abort; /* pointer to command to be aborted */ | |
3574 | struct CommandList *found; | |
3575 | struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */ | |
3576 | char msg[256]; /* For debug messaging. */ | |
3577 | int ml = 0; | |
17eb87d2 | 3578 | u32 tagupper, taglower; |
75167d2c SC |
3579 | |
3580 | /* Find the controller of the command to be aborted */ | |
3581 | h = sdev_to_hba(sc->device); | |
3582 | if (WARN(h == NULL, | |
3583 | "ABORT REQUEST FAILED, Controller lookup failed.\n")) | |
3584 | return FAILED; | |
3585 | ||
3586 | /* Check that controller supports some kind of task abort */ | |
3587 | if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) && | |
3588 | !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags)) | |
3589 | return FAILED; | |
3590 | ||
3591 | memset(msg, 0, sizeof(msg)); | |
3592 | ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ", | |
3593 | h->scsi_host->host_no, sc->device->channel, | |
3594 | sc->device->id, sc->device->lun); | |
3595 | ||
3596 | /* Find the device of the command to be aborted */ | |
3597 | dev = sc->device->hostdata; | |
3598 | if (!dev) { | |
3599 | dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n", | |
3600 | msg); | |
3601 | return FAILED; | |
3602 | } | |
3603 | ||
3604 | /* Get SCSI command to be aborted */ | |
3605 | abort = (struct CommandList *) sc->host_scribble; | |
3606 | if (abort == NULL) { | |
3607 | dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n", | |
3608 | msg); | |
3609 | return FAILED; | |
3610 | } | |
17eb87d2 ST |
3611 | hpsa_get_tag(h, abort, &taglower, &tagupper); |
3612 | ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower); | |
75167d2c SC |
3613 | as = (struct scsi_cmnd *) abort->scsi_cmd; |
3614 | if (as != NULL) | |
3615 | ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ", | |
3616 | as->cmnd[0], as->serial_number); | |
3617 | dev_dbg(&h->pdev->dev, "%s\n", msg); | |
3618 | dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n", | |
3619 | h->scsi_host->host_no, dev->bus, dev->target, dev->lun); | |
3620 | ||
3621 | /* Search reqQ to See if command is queued but not submitted, | |
3622 | * if so, complete the command with aborted status and remove | |
3623 | * it from the reqQ. | |
3624 | */ | |
3625 | found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ); | |
3626 | if (found) { | |
3627 | found->err_info->CommandStatus = CMD_ABORTED; | |
3628 | finish_cmd(found); | |
3629 | dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n", | |
3630 | msg); | |
3631 | return SUCCESS; | |
3632 | } | |
3633 | ||
3634 | /* not in reqQ, if also not in cmpQ, must have already completed */ | |
3635 | found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ); | |
3636 | if (!found) { | |
d6ebd0f7 | 3637 | dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n", |
75167d2c SC |
3638 | msg); |
3639 | return SUCCESS; | |
3640 | } | |
3641 | ||
3642 | /* | |
3643 | * Command is in flight, or possibly already completed | |
3644 | * by the firmware (but not to the scsi mid layer) but we can't | |
3645 | * distinguish which. Send the abort down. | |
3646 | */ | |
6cba3f19 | 3647 | rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort); |
75167d2c SC |
3648 | if (rc != 0) { |
3649 | dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg); | |
3650 | dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n", | |
3651 | h->scsi_host->host_no, | |
3652 | dev->bus, dev->target, dev->lun); | |
3653 | return FAILED; | |
3654 | } | |
3655 | dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg); | |
3656 | ||
3657 | /* If the abort(s) above completed and actually aborted the | |
3658 | * command, then the command to be aborted should already be | |
3659 | * completed. If not, wait around a bit more to see if they | |
3660 | * manage to complete normally. | |
3661 | */ | |
3662 | #define ABORT_COMPLETE_WAIT_SECS 30 | |
3663 | for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) { | |
3664 | found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ); | |
3665 | if (!found) | |
3666 | return SUCCESS; | |
3667 | msleep(100); | |
3668 | } | |
3669 | dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n", | |
3670 | msg, ABORT_COMPLETE_WAIT_SECS); | |
3671 | return FAILED; | |
3672 | } | |
3673 | ||
3674 | ||
edd16368 SC |
3675 | /* |
3676 | * For operations that cannot sleep, a command block is allocated at init, | |
3677 | * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track | |
3678 | * which ones are free or in use. Lock must be held when calling this. | |
3679 | * cmd_free() is the complement. | |
3680 | */ | |
3681 | static struct CommandList *cmd_alloc(struct ctlr_info *h) | |
3682 | { | |
3683 | struct CommandList *c; | |
3684 | int i; | |
3685 | union u64bit temp64; | |
3686 | dma_addr_t cmd_dma_handle, err_dma_handle; | |
e16a33ad | 3687 | unsigned long flags; |
edd16368 | 3688 | |
e16a33ad | 3689 | spin_lock_irqsave(&h->lock, flags); |
edd16368 SC |
3690 | do { |
3691 | i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds); | |
e16a33ad MG |
3692 | if (i == h->nr_cmds) { |
3693 | spin_unlock_irqrestore(&h->lock, flags); | |
edd16368 | 3694 | return NULL; |
e16a33ad | 3695 | } |
edd16368 SC |
3696 | } while (test_and_set_bit |
3697 | (i & (BITS_PER_LONG - 1), | |
3698 | h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0); | |
e16a33ad MG |
3699 | spin_unlock_irqrestore(&h->lock, flags); |
3700 | ||
edd16368 SC |
3701 | c = h->cmd_pool + i; |
3702 | memset(c, 0, sizeof(*c)); | |
3703 | cmd_dma_handle = h->cmd_pool_dhandle | |
3704 | + i * sizeof(*c); | |
3705 | c->err_info = h->errinfo_pool + i; | |
3706 | memset(c->err_info, 0, sizeof(*c->err_info)); | |
3707 | err_dma_handle = h->errinfo_pool_dhandle | |
3708 | + i * sizeof(*c->err_info); | |
edd16368 SC |
3709 | |
3710 | c->cmdindex = i; | |
3711 | ||
9e0fc764 | 3712 | INIT_LIST_HEAD(&c->list); |
01a02ffc SC |
3713 | c->busaddr = (u32) cmd_dma_handle; |
3714 | temp64.val = (u64) err_dma_handle; | |
edd16368 SC |
3715 | c->ErrDesc.Addr.lower = temp64.val32.lower; |
3716 | c->ErrDesc.Addr.upper = temp64.val32.upper; | |
3717 | c->ErrDesc.Len = sizeof(*c->err_info); | |
3718 | ||
3719 | c->h = h; | |
3720 | return c; | |
3721 | } | |
3722 | ||
3723 | /* For operations that can wait for kmalloc to possibly sleep, | |
3724 | * this routine can be called. Lock need not be held to call | |
3725 | * cmd_special_alloc. cmd_special_free() is the complement. | |
3726 | */ | |
3727 | static struct CommandList *cmd_special_alloc(struct ctlr_info *h) | |
3728 | { | |
3729 | struct CommandList *c; | |
3730 | union u64bit temp64; | |
3731 | dma_addr_t cmd_dma_handle, err_dma_handle; | |
3732 | ||
3733 | c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle); | |
3734 | if (c == NULL) | |
3735 | return NULL; | |
3736 | memset(c, 0, sizeof(*c)); | |
3737 | ||
e1f7de0c | 3738 | c->cmd_type = CMD_SCSI; |
edd16368 SC |
3739 | c->cmdindex = -1; |
3740 | ||
3741 | c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info), | |
3742 | &err_dma_handle); | |
3743 | ||
3744 | if (c->err_info == NULL) { | |
3745 | pci_free_consistent(h->pdev, | |
3746 | sizeof(*c), c, cmd_dma_handle); | |
3747 | return NULL; | |
3748 | } | |
3749 | memset(c->err_info, 0, sizeof(*c->err_info)); | |
3750 | ||
9e0fc764 | 3751 | INIT_LIST_HEAD(&c->list); |
01a02ffc SC |
3752 | c->busaddr = (u32) cmd_dma_handle; |
3753 | temp64.val = (u64) err_dma_handle; | |
edd16368 SC |
3754 | c->ErrDesc.Addr.lower = temp64.val32.lower; |
3755 | c->ErrDesc.Addr.upper = temp64.val32.upper; | |
3756 | c->ErrDesc.Len = sizeof(*c->err_info); | |
3757 | ||
3758 | c->h = h; | |
3759 | return c; | |
3760 | } | |
3761 | ||
3762 | static void cmd_free(struct ctlr_info *h, struct CommandList *c) | |
3763 | { | |
3764 | int i; | |
e16a33ad | 3765 | unsigned long flags; |
edd16368 SC |
3766 | |
3767 | i = c - h->cmd_pool; | |
e16a33ad | 3768 | spin_lock_irqsave(&h->lock, flags); |
edd16368 SC |
3769 | clear_bit(i & (BITS_PER_LONG - 1), |
3770 | h->cmd_pool_bits + (i / BITS_PER_LONG)); | |
e16a33ad | 3771 | spin_unlock_irqrestore(&h->lock, flags); |
edd16368 SC |
3772 | } |
3773 | ||
3774 | static void cmd_special_free(struct ctlr_info *h, struct CommandList *c) | |
3775 | { | |
3776 | union u64bit temp64; | |
3777 | ||
3778 | temp64.val32.lower = c->ErrDesc.Addr.lower; | |
3779 | temp64.val32.upper = c->ErrDesc.Addr.upper; | |
3780 | pci_free_consistent(h->pdev, sizeof(*c->err_info), | |
3781 | c->err_info, (dma_addr_t) temp64.val); | |
3782 | pci_free_consistent(h->pdev, sizeof(*c), | |
d896f3f3 | 3783 | c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK)); |
edd16368 SC |
3784 | } |
3785 | ||
3786 | #ifdef CONFIG_COMPAT | |
3787 | ||
edd16368 SC |
3788 | static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg) |
3789 | { | |
3790 | IOCTL32_Command_struct __user *arg32 = | |
3791 | (IOCTL32_Command_struct __user *) arg; | |
3792 | IOCTL_Command_struct arg64; | |
3793 | IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64)); | |
3794 | int err; | |
3795 | u32 cp; | |
3796 | ||
938abd84 | 3797 | memset(&arg64, 0, sizeof(arg64)); |
edd16368 SC |
3798 | err = 0; |
3799 | err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, | |
3800 | sizeof(arg64.LUN_info)); | |
3801 | err |= copy_from_user(&arg64.Request, &arg32->Request, | |
3802 | sizeof(arg64.Request)); | |
3803 | err |= copy_from_user(&arg64.error_info, &arg32->error_info, | |
3804 | sizeof(arg64.error_info)); | |
3805 | err |= get_user(arg64.buf_size, &arg32->buf_size); | |
3806 | err |= get_user(cp, &arg32->buf); | |
3807 | arg64.buf = compat_ptr(cp); | |
3808 | err |= copy_to_user(p, &arg64, sizeof(arg64)); | |
3809 | ||
3810 | if (err) | |
3811 | return -EFAULT; | |
3812 | ||
e39eeaed | 3813 | err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p); |
edd16368 SC |
3814 | if (err) |
3815 | return err; | |
3816 | err |= copy_in_user(&arg32->error_info, &p->error_info, | |
3817 | sizeof(arg32->error_info)); | |
3818 | if (err) | |
3819 | return -EFAULT; | |
3820 | return err; | |
3821 | } | |
3822 | ||
3823 | static int hpsa_ioctl32_big_passthru(struct scsi_device *dev, | |
3824 | int cmd, void *arg) | |
3825 | { | |
3826 | BIG_IOCTL32_Command_struct __user *arg32 = | |
3827 | (BIG_IOCTL32_Command_struct __user *) arg; | |
3828 | BIG_IOCTL_Command_struct arg64; | |
3829 | BIG_IOCTL_Command_struct __user *p = | |
3830 | compat_alloc_user_space(sizeof(arg64)); | |
3831 | int err; | |
3832 | u32 cp; | |
3833 | ||
938abd84 | 3834 | memset(&arg64, 0, sizeof(arg64)); |
edd16368 SC |
3835 | err = 0; |
3836 | err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, | |
3837 | sizeof(arg64.LUN_info)); | |
3838 | err |= copy_from_user(&arg64.Request, &arg32->Request, | |
3839 | sizeof(arg64.Request)); | |
3840 | err |= copy_from_user(&arg64.error_info, &arg32->error_info, | |
3841 | sizeof(arg64.error_info)); | |
3842 | err |= get_user(arg64.buf_size, &arg32->buf_size); | |
3843 | err |= get_user(arg64.malloc_size, &arg32->malloc_size); | |
3844 | err |= get_user(cp, &arg32->buf); | |
3845 | arg64.buf = compat_ptr(cp); | |
3846 | err |= copy_to_user(p, &arg64, sizeof(arg64)); | |
3847 | ||
3848 | if (err) | |
3849 | return -EFAULT; | |
3850 | ||
e39eeaed | 3851 | err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p); |
edd16368 SC |
3852 | if (err) |
3853 | return err; | |
3854 | err |= copy_in_user(&arg32->error_info, &p->error_info, | |
3855 | sizeof(arg32->error_info)); | |
3856 | if (err) | |
3857 | return -EFAULT; | |
3858 | return err; | |
3859 | } | |
71fe75a7 SC |
3860 | |
3861 | static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg) | |
3862 | { | |
3863 | switch (cmd) { | |
3864 | case CCISS_GETPCIINFO: | |
3865 | case CCISS_GETINTINFO: | |
3866 | case CCISS_SETINTINFO: | |
3867 | case CCISS_GETNODENAME: | |
3868 | case CCISS_SETNODENAME: | |
3869 | case CCISS_GETHEARTBEAT: | |
3870 | case CCISS_GETBUSTYPES: | |
3871 | case CCISS_GETFIRMVER: | |
3872 | case CCISS_GETDRIVVER: | |
3873 | case CCISS_REVALIDVOLS: | |
3874 | case CCISS_DEREGDISK: | |
3875 | case CCISS_REGNEWDISK: | |
3876 | case CCISS_REGNEWD: | |
3877 | case CCISS_RESCANDISK: | |
3878 | case CCISS_GETLUNINFO: | |
3879 | return hpsa_ioctl(dev, cmd, arg); | |
3880 | ||
3881 | case CCISS_PASSTHRU32: | |
3882 | return hpsa_ioctl32_passthru(dev, cmd, arg); | |
3883 | case CCISS_BIG_PASSTHRU32: | |
3884 | return hpsa_ioctl32_big_passthru(dev, cmd, arg); | |
3885 | ||
3886 | default: | |
3887 | return -ENOIOCTLCMD; | |
3888 | } | |
3889 | } | |
edd16368 SC |
3890 | #endif |
3891 | ||
3892 | static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp) | |
3893 | { | |
3894 | struct hpsa_pci_info pciinfo; | |
3895 | ||
3896 | if (!argp) | |
3897 | return -EINVAL; | |
3898 | pciinfo.domain = pci_domain_nr(h->pdev->bus); | |
3899 | pciinfo.bus = h->pdev->bus->number; | |
3900 | pciinfo.dev_fn = h->pdev->devfn; | |
3901 | pciinfo.board_id = h->board_id; | |
3902 | if (copy_to_user(argp, &pciinfo, sizeof(pciinfo))) | |
3903 | return -EFAULT; | |
3904 | return 0; | |
3905 | } | |
3906 | ||
3907 | static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp) | |
3908 | { | |
3909 | DriverVer_type DriverVer; | |
3910 | unsigned char vmaj, vmin, vsubmin; | |
3911 | int rc; | |
3912 | ||
3913 | rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu", | |
3914 | &vmaj, &vmin, &vsubmin); | |
3915 | if (rc != 3) { | |
3916 | dev_info(&h->pdev->dev, "driver version string '%s' " | |
3917 | "unrecognized.", HPSA_DRIVER_VERSION); | |
3918 | vmaj = 0; | |
3919 | vmin = 0; | |
3920 | vsubmin = 0; | |
3921 | } | |
3922 | DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin; | |
3923 | if (!argp) | |
3924 | return -EINVAL; | |
3925 | if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type))) | |
3926 | return -EFAULT; | |
3927 | return 0; | |
3928 | } | |
3929 | ||
3930 | static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp) | |
3931 | { | |
3932 | IOCTL_Command_struct iocommand; | |
3933 | struct CommandList *c; | |
3934 | char *buff = NULL; | |
3935 | union u64bit temp64; | |
c1f63c8f | 3936 | int rc = 0; |
edd16368 SC |
3937 | |
3938 | if (!argp) | |
3939 | return -EINVAL; | |
3940 | if (!capable(CAP_SYS_RAWIO)) | |
3941 | return -EPERM; | |
3942 | if (copy_from_user(&iocommand, argp, sizeof(iocommand))) | |
3943 | return -EFAULT; | |
3944 | if ((iocommand.buf_size < 1) && | |
3945 | (iocommand.Request.Type.Direction != XFER_NONE)) { | |
3946 | return -EINVAL; | |
3947 | } | |
3948 | if (iocommand.buf_size > 0) { | |
3949 | buff = kmalloc(iocommand.buf_size, GFP_KERNEL); | |
3950 | if (buff == NULL) | |
3951 | return -EFAULT; | |
b03a7771 SC |
3952 | if (iocommand.Request.Type.Direction == XFER_WRITE) { |
3953 | /* Copy the data into the buffer we created */ | |
3954 | if (copy_from_user(buff, iocommand.buf, | |
3955 | iocommand.buf_size)) { | |
c1f63c8f SC |
3956 | rc = -EFAULT; |
3957 | goto out_kfree; | |
b03a7771 SC |
3958 | } |
3959 | } else { | |
3960 | memset(buff, 0, iocommand.buf_size); | |
edd16368 | 3961 | } |
b03a7771 | 3962 | } |
edd16368 SC |
3963 | c = cmd_special_alloc(h); |
3964 | if (c == NULL) { | |
c1f63c8f SC |
3965 | rc = -ENOMEM; |
3966 | goto out_kfree; | |
edd16368 SC |
3967 | } |
3968 | /* Fill in the command type */ | |
3969 | c->cmd_type = CMD_IOCTL_PEND; | |
3970 | /* Fill in Command Header */ | |
3971 | c->Header.ReplyQueue = 0; /* unused in simple mode */ | |
3972 | if (iocommand.buf_size > 0) { /* buffer to fill */ | |
3973 | c->Header.SGList = 1; | |
3974 | c->Header.SGTotal = 1; | |
3975 | } else { /* no buffers to fill */ | |
3976 | c->Header.SGList = 0; | |
3977 | c->Header.SGTotal = 0; | |
3978 | } | |
3979 | memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN)); | |
3980 | /* use the kernel address the cmd block for tag */ | |
3981 | c->Header.Tag.lower = c->busaddr; | |
3982 | ||
3983 | /* Fill in Request block */ | |
3984 | memcpy(&c->Request, &iocommand.Request, | |
3985 | sizeof(c->Request)); | |
3986 | ||
3987 | /* Fill in the scatter gather information */ | |
3988 | if (iocommand.buf_size > 0) { | |
3989 | temp64.val = pci_map_single(h->pdev, buff, | |
3990 | iocommand.buf_size, PCI_DMA_BIDIRECTIONAL); | |
bcc48ffa SC |
3991 | if (dma_mapping_error(&h->pdev->dev, temp64.val)) { |
3992 | c->SG[0].Addr.lower = 0; | |
3993 | c->SG[0].Addr.upper = 0; | |
3994 | c->SG[0].Len = 0; | |
3995 | rc = -ENOMEM; | |
3996 | goto out; | |
3997 | } | |
edd16368 SC |
3998 | c->SG[0].Addr.lower = temp64.val32.lower; |
3999 | c->SG[0].Addr.upper = temp64.val32.upper; | |
4000 | c->SG[0].Len = iocommand.buf_size; | |
e1d9cbfa | 4001 | c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/ |
edd16368 | 4002 | } |
a0c12413 | 4003 | hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c); |
c2dd32e0 SC |
4004 | if (iocommand.buf_size > 0) |
4005 | hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL); | |
edd16368 SC |
4006 | check_ioctl_unit_attention(h, c); |
4007 | ||
4008 | /* Copy the error information out */ | |
4009 | memcpy(&iocommand.error_info, c->err_info, | |
4010 | sizeof(iocommand.error_info)); | |
4011 | if (copy_to_user(argp, &iocommand, sizeof(iocommand))) { | |
c1f63c8f SC |
4012 | rc = -EFAULT; |
4013 | goto out; | |
edd16368 | 4014 | } |
b03a7771 SC |
4015 | if (iocommand.Request.Type.Direction == XFER_READ && |
4016 | iocommand.buf_size > 0) { | |
edd16368 SC |
4017 | /* Copy the data out of the buffer we created */ |
4018 | if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) { | |
c1f63c8f SC |
4019 | rc = -EFAULT; |
4020 | goto out; | |
edd16368 SC |
4021 | } |
4022 | } | |
c1f63c8f | 4023 | out: |
edd16368 | 4024 | cmd_special_free(h, c); |
c1f63c8f SC |
4025 | out_kfree: |
4026 | kfree(buff); | |
4027 | return rc; | |
edd16368 SC |
4028 | } |
4029 | ||
4030 | static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp) | |
4031 | { | |
4032 | BIG_IOCTL_Command_struct *ioc; | |
4033 | struct CommandList *c; | |
4034 | unsigned char **buff = NULL; | |
4035 | int *buff_size = NULL; | |
4036 | union u64bit temp64; | |
4037 | BYTE sg_used = 0; | |
4038 | int status = 0; | |
4039 | int i; | |
01a02ffc SC |
4040 | u32 left; |
4041 | u32 sz; | |
edd16368 SC |
4042 | BYTE __user *data_ptr; |
4043 | ||
4044 | if (!argp) | |
4045 | return -EINVAL; | |
4046 | if (!capable(CAP_SYS_RAWIO)) | |
4047 | return -EPERM; | |
4048 | ioc = (BIG_IOCTL_Command_struct *) | |
4049 | kmalloc(sizeof(*ioc), GFP_KERNEL); | |
4050 | if (!ioc) { | |
4051 | status = -ENOMEM; | |
4052 | goto cleanup1; | |
4053 | } | |
4054 | if (copy_from_user(ioc, argp, sizeof(*ioc))) { | |
4055 | status = -EFAULT; | |
4056 | goto cleanup1; | |
4057 | } | |
4058 | if ((ioc->buf_size < 1) && | |
4059 | (ioc->Request.Type.Direction != XFER_NONE)) { | |
4060 | status = -EINVAL; | |
4061 | goto cleanup1; | |
4062 | } | |
4063 | /* Check kmalloc limits using all SGs */ | |
4064 | if (ioc->malloc_size > MAX_KMALLOC_SIZE) { | |
4065 | status = -EINVAL; | |
4066 | goto cleanup1; | |
4067 | } | |
d66ae08b | 4068 | if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) { |
edd16368 SC |
4069 | status = -EINVAL; |
4070 | goto cleanup1; | |
4071 | } | |
d66ae08b | 4072 | buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL); |
edd16368 SC |
4073 | if (!buff) { |
4074 | status = -ENOMEM; | |
4075 | goto cleanup1; | |
4076 | } | |
d66ae08b | 4077 | buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL); |
edd16368 SC |
4078 | if (!buff_size) { |
4079 | status = -ENOMEM; | |
4080 | goto cleanup1; | |
4081 | } | |
4082 | left = ioc->buf_size; | |
4083 | data_ptr = ioc->buf; | |
4084 | while (left) { | |
4085 | sz = (left > ioc->malloc_size) ? ioc->malloc_size : left; | |
4086 | buff_size[sg_used] = sz; | |
4087 | buff[sg_used] = kmalloc(sz, GFP_KERNEL); | |
4088 | if (buff[sg_used] == NULL) { | |
4089 | status = -ENOMEM; | |
4090 | goto cleanup1; | |
4091 | } | |
4092 | if (ioc->Request.Type.Direction == XFER_WRITE) { | |
4093 | if (copy_from_user(buff[sg_used], data_ptr, sz)) { | |
4094 | status = -ENOMEM; | |
4095 | goto cleanup1; | |
4096 | } | |
4097 | } else | |
4098 | memset(buff[sg_used], 0, sz); | |
4099 | left -= sz; | |
4100 | data_ptr += sz; | |
4101 | sg_used++; | |
4102 | } | |
4103 | c = cmd_special_alloc(h); | |
4104 | if (c == NULL) { | |
4105 | status = -ENOMEM; | |
4106 | goto cleanup1; | |
4107 | } | |
4108 | c->cmd_type = CMD_IOCTL_PEND; | |
4109 | c->Header.ReplyQueue = 0; | |
b03a7771 | 4110 | c->Header.SGList = c->Header.SGTotal = sg_used; |
edd16368 SC |
4111 | memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN)); |
4112 | c->Header.Tag.lower = c->busaddr; | |
4113 | memcpy(&c->Request, &ioc->Request, sizeof(c->Request)); | |
4114 | if (ioc->buf_size > 0) { | |
4115 | int i; | |
4116 | for (i = 0; i < sg_used; i++) { | |
4117 | temp64.val = pci_map_single(h->pdev, buff[i], | |
4118 | buff_size[i], PCI_DMA_BIDIRECTIONAL); | |
bcc48ffa SC |
4119 | if (dma_mapping_error(&h->pdev->dev, temp64.val)) { |
4120 | c->SG[i].Addr.lower = 0; | |
4121 | c->SG[i].Addr.upper = 0; | |
4122 | c->SG[i].Len = 0; | |
4123 | hpsa_pci_unmap(h->pdev, c, i, | |
4124 | PCI_DMA_BIDIRECTIONAL); | |
4125 | status = -ENOMEM; | |
e2d4a1f6 | 4126 | goto cleanup0; |
bcc48ffa | 4127 | } |
edd16368 SC |
4128 | c->SG[i].Addr.lower = temp64.val32.lower; |
4129 | c->SG[i].Addr.upper = temp64.val32.upper; | |
4130 | c->SG[i].Len = buff_size[i]; | |
e1d9cbfa | 4131 | c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST; |
edd16368 SC |
4132 | } |
4133 | } | |
a0c12413 | 4134 | hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c); |
b03a7771 SC |
4135 | if (sg_used) |
4136 | hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL); | |
edd16368 SC |
4137 | check_ioctl_unit_attention(h, c); |
4138 | /* Copy the error information out */ | |
4139 | memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info)); | |
4140 | if (copy_to_user(argp, ioc, sizeof(*ioc))) { | |
edd16368 | 4141 | status = -EFAULT; |
e2d4a1f6 | 4142 | goto cleanup0; |
edd16368 | 4143 | } |
b03a7771 | 4144 | if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) { |
edd16368 SC |
4145 | /* Copy the data out of the buffer we created */ |
4146 | BYTE __user *ptr = ioc->buf; | |
4147 | for (i = 0; i < sg_used; i++) { | |
4148 | if (copy_to_user(ptr, buff[i], buff_size[i])) { | |
edd16368 | 4149 | status = -EFAULT; |
e2d4a1f6 | 4150 | goto cleanup0; |
edd16368 SC |
4151 | } |
4152 | ptr += buff_size[i]; | |
4153 | } | |
4154 | } | |
edd16368 | 4155 | status = 0; |
e2d4a1f6 SC |
4156 | cleanup0: |
4157 | cmd_special_free(h, c); | |
edd16368 SC |
4158 | cleanup1: |
4159 | if (buff) { | |
4160 | for (i = 0; i < sg_used; i++) | |
4161 | kfree(buff[i]); | |
4162 | kfree(buff); | |
4163 | } | |
4164 | kfree(buff_size); | |
4165 | kfree(ioc); | |
4166 | return status; | |
4167 | } | |
4168 | ||
4169 | static void check_ioctl_unit_attention(struct ctlr_info *h, | |
4170 | struct CommandList *c) | |
4171 | { | |
4172 | if (c->err_info->CommandStatus == CMD_TARGET_STATUS && | |
4173 | c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION) | |
4174 | (void) check_for_unit_attention(h, c); | |
4175 | } | |
0390f0c0 SC |
4176 | |
4177 | static int increment_passthru_count(struct ctlr_info *h) | |
4178 | { | |
4179 | unsigned long flags; | |
4180 | ||
4181 | spin_lock_irqsave(&h->passthru_count_lock, flags); | |
4182 | if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) { | |
4183 | spin_unlock_irqrestore(&h->passthru_count_lock, flags); | |
4184 | return -1; | |
4185 | } | |
4186 | h->passthru_count++; | |
4187 | spin_unlock_irqrestore(&h->passthru_count_lock, flags); | |
4188 | return 0; | |
4189 | } | |
4190 | ||
4191 | static void decrement_passthru_count(struct ctlr_info *h) | |
4192 | { | |
4193 | unsigned long flags; | |
4194 | ||
4195 | spin_lock_irqsave(&h->passthru_count_lock, flags); | |
4196 | if (h->passthru_count <= 0) { | |
4197 | spin_unlock_irqrestore(&h->passthru_count_lock, flags); | |
4198 | /* not expecting to get here. */ | |
4199 | dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n"); | |
4200 | return; | |
4201 | } | |
4202 | h->passthru_count--; | |
4203 | spin_unlock_irqrestore(&h->passthru_count_lock, flags); | |
4204 | } | |
4205 | ||
edd16368 SC |
4206 | /* |
4207 | * ioctl | |
4208 | */ | |
4209 | static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg) | |
4210 | { | |
4211 | struct ctlr_info *h; | |
4212 | void __user *argp = (void __user *)arg; | |
0390f0c0 | 4213 | int rc; |
edd16368 SC |
4214 | |
4215 | h = sdev_to_hba(dev); | |
4216 | ||
4217 | switch (cmd) { | |
4218 | case CCISS_DEREGDISK: | |
4219 | case CCISS_REGNEWDISK: | |
4220 | case CCISS_REGNEWD: | |
a08a8471 | 4221 | hpsa_scan_start(h->scsi_host); |
edd16368 SC |
4222 | return 0; |
4223 | case CCISS_GETPCIINFO: | |
4224 | return hpsa_getpciinfo_ioctl(h, argp); | |
4225 | case CCISS_GETDRIVVER: | |
4226 | return hpsa_getdrivver_ioctl(h, argp); | |
4227 | case CCISS_PASSTHRU: | |
0390f0c0 SC |
4228 | if (increment_passthru_count(h)) |
4229 | return -EAGAIN; | |
4230 | rc = hpsa_passthru_ioctl(h, argp); | |
4231 | decrement_passthru_count(h); | |
4232 | return rc; | |
edd16368 | 4233 | case CCISS_BIG_PASSTHRU: |
0390f0c0 SC |
4234 | if (increment_passthru_count(h)) |
4235 | return -EAGAIN; | |
4236 | rc = hpsa_big_passthru_ioctl(h, argp); | |
4237 | decrement_passthru_count(h); | |
4238 | return rc; | |
edd16368 SC |
4239 | default: |
4240 | return -ENOTTY; | |
4241 | } | |
4242 | } | |
4243 | ||
6f039790 GKH |
4244 | static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr, |
4245 | u8 reset_type) | |
64670ac8 SC |
4246 | { |
4247 | struct CommandList *c; | |
4248 | ||
4249 | c = cmd_alloc(h); | |
4250 | if (!c) | |
4251 | return -ENOMEM; | |
a2dac136 SC |
4252 | /* fill_cmd can't fail here, no data buffer to map */ |
4253 | (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0, | |
64670ac8 SC |
4254 | RAID_CTLR_LUNID, TYPE_MSG); |
4255 | c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */ | |
4256 | c->waiting = NULL; | |
4257 | enqueue_cmd_and_start_io(h, c); | |
4258 | /* Don't wait for completion, the reset won't complete. Don't free | |
4259 | * the command either. This is the last command we will send before | |
4260 | * re-initializing everything, so it doesn't matter and won't leak. | |
4261 | */ | |
4262 | return 0; | |
4263 | } | |
4264 | ||
a2dac136 | 4265 | static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, |
01a02ffc | 4266 | void *buff, size_t size, u8 page_code, unsigned char *scsi3addr, |
edd16368 SC |
4267 | int cmd_type) |
4268 | { | |
4269 | int pci_dir = XFER_NONE; | |
75167d2c | 4270 | struct CommandList *a; /* for commands to be aborted */ |
edd16368 SC |
4271 | |
4272 | c->cmd_type = CMD_IOCTL_PEND; | |
4273 | c->Header.ReplyQueue = 0; | |
4274 | if (buff != NULL && size > 0) { | |
4275 | c->Header.SGList = 1; | |
4276 | c->Header.SGTotal = 1; | |
4277 | } else { | |
4278 | c->Header.SGList = 0; | |
4279 | c->Header.SGTotal = 0; | |
4280 | } | |
4281 | c->Header.Tag.lower = c->busaddr; | |
4282 | memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8); | |
4283 | ||
4284 | c->Request.Type.Type = cmd_type; | |
4285 | if (cmd_type == TYPE_CMD) { | |
4286 | switch (cmd) { | |
4287 | case HPSA_INQUIRY: | |
4288 | /* are we trying to read a vital product page */ | |
4289 | if (page_code != 0) { | |
4290 | c->Request.CDB[1] = 0x01; | |
4291 | c->Request.CDB[2] = page_code; | |
4292 | } | |
4293 | c->Request.CDBLen = 6; | |
4294 | c->Request.Type.Attribute = ATTR_SIMPLE; | |
4295 | c->Request.Type.Direction = XFER_READ; | |
4296 | c->Request.Timeout = 0; | |
4297 | c->Request.CDB[0] = HPSA_INQUIRY; | |
4298 | c->Request.CDB[4] = size & 0xFF; | |
4299 | break; | |
4300 | case HPSA_REPORT_LOG: | |
4301 | case HPSA_REPORT_PHYS: | |
4302 | /* Talking to controller so It's a physical command | |
4303 | mode = 00 target = 0. Nothing to write. | |
4304 | */ | |
4305 | c->Request.CDBLen = 12; | |
4306 | c->Request.Type.Attribute = ATTR_SIMPLE; | |
4307 | c->Request.Type.Direction = XFER_READ; | |
4308 | c->Request.Timeout = 0; | |
4309 | c->Request.CDB[0] = cmd; | |
4310 | c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ | |
4311 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
4312 | c->Request.CDB[8] = (size >> 8) & 0xFF; | |
4313 | c->Request.CDB[9] = size & 0xFF; | |
4314 | break; | |
edd16368 SC |
4315 | case HPSA_CACHE_FLUSH: |
4316 | c->Request.CDBLen = 12; | |
4317 | c->Request.Type.Attribute = ATTR_SIMPLE; | |
4318 | c->Request.Type.Direction = XFER_WRITE; | |
4319 | c->Request.Timeout = 0; | |
4320 | c->Request.CDB[0] = BMIC_WRITE; | |
4321 | c->Request.CDB[6] = BMIC_CACHE_FLUSH; | |
bb158eab SC |
4322 | c->Request.CDB[7] = (size >> 8) & 0xFF; |
4323 | c->Request.CDB[8] = size & 0xFF; | |
edd16368 SC |
4324 | break; |
4325 | case TEST_UNIT_READY: | |
4326 | c->Request.CDBLen = 6; | |
4327 | c->Request.Type.Attribute = ATTR_SIMPLE; | |
4328 | c->Request.Type.Direction = XFER_NONE; | |
4329 | c->Request.Timeout = 0; | |
4330 | break; | |
283b4a9b SC |
4331 | case HPSA_GET_RAID_MAP: |
4332 | c->Request.CDBLen = 12; | |
4333 | c->Request.Type.Attribute = ATTR_SIMPLE; | |
4334 | c->Request.Type.Direction = XFER_READ; | |
4335 | c->Request.Timeout = 0; | |
4336 | c->Request.CDB[0] = HPSA_CISS_READ; | |
4337 | c->Request.CDB[1] = cmd; | |
4338 | c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ | |
4339 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
4340 | c->Request.CDB[8] = (size >> 8) & 0xFF; | |
4341 | c->Request.CDB[9] = size & 0xFF; | |
4342 | break; | |
edd16368 SC |
4343 | default: |
4344 | dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd); | |
4345 | BUG(); | |
a2dac136 | 4346 | return -1; |
edd16368 SC |
4347 | } |
4348 | } else if (cmd_type == TYPE_MSG) { | |
4349 | switch (cmd) { | |
4350 | ||
4351 | case HPSA_DEVICE_RESET_MSG: | |
4352 | c->Request.CDBLen = 16; | |
4353 | c->Request.Type.Type = 1; /* It is a MSG not a CMD */ | |
4354 | c->Request.Type.Attribute = ATTR_SIMPLE; | |
4355 | c->Request.Type.Direction = XFER_NONE; | |
4356 | c->Request.Timeout = 0; /* Don't time out */ | |
64670ac8 SC |
4357 | memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB)); |
4358 | c->Request.CDB[0] = cmd; | |
21e89afd | 4359 | c->Request.CDB[1] = HPSA_RESET_TYPE_LUN; |
edd16368 SC |
4360 | /* If bytes 4-7 are zero, it means reset the */ |
4361 | /* LunID device */ | |
4362 | c->Request.CDB[4] = 0x00; | |
4363 | c->Request.CDB[5] = 0x00; | |
4364 | c->Request.CDB[6] = 0x00; | |
4365 | c->Request.CDB[7] = 0x00; | |
75167d2c SC |
4366 | break; |
4367 | case HPSA_ABORT_MSG: | |
4368 | a = buff; /* point to command to be aborted */ | |
4369 | dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n", | |
4370 | a->Header.Tag.upper, a->Header.Tag.lower, | |
4371 | c->Header.Tag.upper, c->Header.Tag.lower); | |
4372 | c->Request.CDBLen = 16; | |
4373 | c->Request.Type.Type = TYPE_MSG; | |
4374 | c->Request.Type.Attribute = ATTR_SIMPLE; | |
4375 | c->Request.Type.Direction = XFER_WRITE; | |
4376 | c->Request.Timeout = 0; /* Don't time out */ | |
4377 | c->Request.CDB[0] = HPSA_TASK_MANAGEMENT; | |
4378 | c->Request.CDB[1] = HPSA_TMF_ABORT_TASK; | |
4379 | c->Request.CDB[2] = 0x00; /* reserved */ | |
4380 | c->Request.CDB[3] = 0x00; /* reserved */ | |
4381 | /* Tag to abort goes in CDB[4]-CDB[11] */ | |
4382 | c->Request.CDB[4] = a->Header.Tag.lower & 0xFF; | |
4383 | c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF; | |
4384 | c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF; | |
4385 | c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF; | |
4386 | c->Request.CDB[8] = a->Header.Tag.upper & 0xFF; | |
4387 | c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF; | |
4388 | c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF; | |
4389 | c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF; | |
4390 | c->Request.CDB[12] = 0x00; /* reserved */ | |
4391 | c->Request.CDB[13] = 0x00; /* reserved */ | |
4392 | c->Request.CDB[14] = 0x00; /* reserved */ | |
4393 | c->Request.CDB[15] = 0x00; /* reserved */ | |
edd16368 | 4394 | break; |
edd16368 SC |
4395 | default: |
4396 | dev_warn(&h->pdev->dev, "unknown message type %d\n", | |
4397 | cmd); | |
4398 | BUG(); | |
4399 | } | |
4400 | } else { | |
4401 | dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type); | |
4402 | BUG(); | |
4403 | } | |
4404 | ||
4405 | switch (c->Request.Type.Direction) { | |
4406 | case XFER_READ: | |
4407 | pci_dir = PCI_DMA_FROMDEVICE; | |
4408 | break; | |
4409 | case XFER_WRITE: | |
4410 | pci_dir = PCI_DMA_TODEVICE; | |
4411 | break; | |
4412 | case XFER_NONE: | |
4413 | pci_dir = PCI_DMA_NONE; | |
4414 | break; | |
4415 | default: | |
4416 | pci_dir = PCI_DMA_BIDIRECTIONAL; | |
4417 | } | |
a2dac136 SC |
4418 | if (hpsa_map_one(h->pdev, c, buff, size, pci_dir)) |
4419 | return -1; | |
4420 | return 0; | |
edd16368 SC |
4421 | } |
4422 | ||
4423 | /* | |
4424 | * Map (physical) PCI mem into (virtual) kernel space | |
4425 | */ | |
4426 | static void __iomem *remap_pci_mem(ulong base, ulong size) | |
4427 | { | |
4428 | ulong page_base = ((ulong) base) & PAGE_MASK; | |
4429 | ulong page_offs = ((ulong) base) - page_base; | |
088ba34c SC |
4430 | void __iomem *page_remapped = ioremap_nocache(page_base, |
4431 | page_offs + size); | |
edd16368 SC |
4432 | |
4433 | return page_remapped ? (page_remapped + page_offs) : NULL; | |
4434 | } | |
4435 | ||
4436 | /* Takes cmds off the submission queue and sends them to the hardware, | |
4437 | * then puts them on the queue of cmds waiting for completion. | |
4438 | */ | |
4439 | static void start_io(struct ctlr_info *h) | |
4440 | { | |
4441 | struct CommandList *c; | |
e16a33ad | 4442 | unsigned long flags; |
edd16368 | 4443 | |
e16a33ad | 4444 | spin_lock_irqsave(&h->lock, flags); |
9e0fc764 SC |
4445 | while (!list_empty(&h->reqQ)) { |
4446 | c = list_entry(h->reqQ.next, struct CommandList, list); | |
edd16368 SC |
4447 | /* can't do anything if fifo is full */ |
4448 | if ((h->access.fifo_full(h))) { | |
396883e2 | 4449 | h->fifo_recently_full = 1; |
edd16368 SC |
4450 | dev_warn(&h->pdev->dev, "fifo full\n"); |
4451 | break; | |
4452 | } | |
396883e2 | 4453 | h->fifo_recently_full = 0; |
edd16368 SC |
4454 | |
4455 | /* Get the first entry from the Request Q */ | |
4456 | removeQ(c); | |
4457 | h->Qdepth--; | |
4458 | ||
edd16368 SC |
4459 | /* Put job onto the completed Q */ |
4460 | addQ(&h->cmpQ, c); | |
e16a33ad MG |
4461 | |
4462 | /* Must increment commands_outstanding before unlocking | |
4463 | * and submitting to avoid race checking for fifo full | |
4464 | * condition. | |
4465 | */ | |
4466 | h->commands_outstanding++; | |
4467 | if (h->commands_outstanding > h->max_outstanding) | |
4468 | h->max_outstanding = h->commands_outstanding; | |
4469 | ||
4470 | /* Tell the controller execute command */ | |
4471 | spin_unlock_irqrestore(&h->lock, flags); | |
4472 | h->access.submit_command(h, c); | |
4473 | spin_lock_irqsave(&h->lock, flags); | |
edd16368 | 4474 | } |
e16a33ad | 4475 | spin_unlock_irqrestore(&h->lock, flags); |
edd16368 SC |
4476 | } |
4477 | ||
254f796b | 4478 | static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q) |
edd16368 | 4479 | { |
254f796b | 4480 | return h->access.command_completed(h, q); |
edd16368 SC |
4481 | } |
4482 | ||
900c5440 | 4483 | static inline bool interrupt_pending(struct ctlr_info *h) |
edd16368 SC |
4484 | { |
4485 | return h->access.intr_pending(h); | |
4486 | } | |
4487 | ||
4488 | static inline long interrupt_not_for_us(struct ctlr_info *h) | |
4489 | { | |
10f66018 SC |
4490 | return (h->access.intr_pending(h) == 0) || |
4491 | (h->interrupts_enabled == 0); | |
edd16368 SC |
4492 | } |
4493 | ||
01a02ffc SC |
4494 | static inline int bad_tag(struct ctlr_info *h, u32 tag_index, |
4495 | u32 raw_tag) | |
edd16368 SC |
4496 | { |
4497 | if (unlikely(tag_index >= h->nr_cmds)) { | |
4498 | dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag); | |
4499 | return 1; | |
4500 | } | |
4501 | return 0; | |
4502 | } | |
4503 | ||
5a3d16f5 | 4504 | static inline void finish_cmd(struct CommandList *c) |
edd16368 | 4505 | { |
e16a33ad | 4506 | unsigned long flags; |
396883e2 SC |
4507 | int io_may_be_stalled = 0; |
4508 | struct ctlr_info *h = c->h; | |
e16a33ad | 4509 | |
396883e2 | 4510 | spin_lock_irqsave(&h->lock, flags); |
edd16368 | 4511 | removeQ(c); |
396883e2 SC |
4512 | |
4513 | /* | |
4514 | * Check for possibly stalled i/o. | |
4515 | * | |
4516 | * If a fifo_full condition is encountered, requests will back up | |
4517 | * in h->reqQ. This queue is only emptied out by start_io which is | |
4518 | * only called when a new i/o request comes in. If no i/o's are | |
4519 | * forthcoming, the i/o's in h->reqQ can get stuck. So we call | |
4520 | * start_io from here if we detect such a danger. | |
4521 | * | |
4522 | * Normally, we shouldn't hit this case, but pounding on the | |
4523 | * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if | |
4524 | * commands_outstanding is low. We want to avoid calling | |
4525 | * start_io from in here as much as possible, and esp. don't | |
4526 | * want to get in a cycle where we call start_io every time | |
4527 | * through here. | |
4528 | */ | |
4529 | if (unlikely(h->fifo_recently_full) && | |
4530 | h->commands_outstanding < 5) | |
4531 | io_may_be_stalled = 1; | |
4532 | ||
4533 | spin_unlock_irqrestore(&h->lock, flags); | |
4534 | ||
e85c5974 | 4535 | dial_up_lockup_detection_on_fw_flash_complete(c->h, c); |
c349775e ST |
4536 | if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI |
4537 | || c->cmd_type == CMD_IOACCEL2)) | |
1fb011fb | 4538 | complete_scsi_command(c); |
edd16368 SC |
4539 | else if (c->cmd_type == CMD_IOCTL_PEND) |
4540 | complete(c->waiting); | |
396883e2 SC |
4541 | if (unlikely(io_may_be_stalled)) |
4542 | start_io(h); | |
edd16368 SC |
4543 | } |
4544 | ||
a104c99f SC |
4545 | static inline u32 hpsa_tag_contains_index(u32 tag) |
4546 | { | |
a104c99f SC |
4547 | return tag & DIRECT_LOOKUP_BIT; |
4548 | } | |
4549 | ||
4550 | static inline u32 hpsa_tag_to_index(u32 tag) | |
4551 | { | |
a104c99f SC |
4552 | return tag >> DIRECT_LOOKUP_SHIFT; |
4553 | } | |
4554 | ||
a9a3a273 SC |
4555 | |
4556 | static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag) | |
a104c99f | 4557 | { |
a9a3a273 SC |
4558 | #define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1) |
4559 | #define HPSA_SIMPLE_ERROR_BITS 0x03 | |
960a30e7 | 4560 | if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant))) |
a9a3a273 SC |
4561 | return tag & ~HPSA_SIMPLE_ERROR_BITS; |
4562 | return tag & ~HPSA_PERF_ERROR_BITS; | |
a104c99f SC |
4563 | } |
4564 | ||
303932fd | 4565 | /* process completion of an indexed ("direct lookup") command */ |
1d94f94d | 4566 | static inline void process_indexed_cmd(struct ctlr_info *h, |
303932fd DB |
4567 | u32 raw_tag) |
4568 | { | |
4569 | u32 tag_index; | |
4570 | struct CommandList *c; | |
4571 | ||
4572 | tag_index = hpsa_tag_to_index(raw_tag); | |
1d94f94d SC |
4573 | if (!bad_tag(h, tag_index, raw_tag)) { |
4574 | c = h->cmd_pool + tag_index; | |
4575 | finish_cmd(c); | |
4576 | } | |
303932fd DB |
4577 | } |
4578 | ||
4579 | /* process completion of a non-indexed command */ | |
1d94f94d | 4580 | static inline void process_nonindexed_cmd(struct ctlr_info *h, |
303932fd DB |
4581 | u32 raw_tag) |
4582 | { | |
4583 | u32 tag; | |
4584 | struct CommandList *c = NULL; | |
e16a33ad | 4585 | unsigned long flags; |
303932fd | 4586 | |
a9a3a273 | 4587 | tag = hpsa_tag_discard_error_bits(h, raw_tag); |
e16a33ad | 4588 | spin_lock_irqsave(&h->lock, flags); |
9e0fc764 | 4589 | list_for_each_entry(c, &h->cmpQ, list) { |
303932fd | 4590 | if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) { |
e16a33ad | 4591 | spin_unlock_irqrestore(&h->lock, flags); |
5a3d16f5 | 4592 | finish_cmd(c); |
1d94f94d | 4593 | return; |
303932fd DB |
4594 | } |
4595 | } | |
e16a33ad | 4596 | spin_unlock_irqrestore(&h->lock, flags); |
303932fd | 4597 | bad_tag(h, h->nr_cmds + 1, raw_tag); |
303932fd DB |
4598 | } |
4599 | ||
64670ac8 SC |
4600 | /* Some controllers, like p400, will give us one interrupt |
4601 | * after a soft reset, even if we turned interrupts off. | |
4602 | * Only need to check for this in the hpsa_xxx_discard_completions | |
4603 | * functions. | |
4604 | */ | |
4605 | static int ignore_bogus_interrupt(struct ctlr_info *h) | |
4606 | { | |
4607 | if (likely(!reset_devices)) | |
4608 | return 0; | |
4609 | ||
4610 | if (likely(h->interrupts_enabled)) | |
4611 | return 0; | |
4612 | ||
4613 | dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled " | |
4614 | "(known firmware bug.) Ignoring.\n"); | |
4615 | ||
4616 | return 1; | |
4617 | } | |
4618 | ||
254f796b MG |
4619 | /* |
4620 | * Convert &h->q[x] (passed to interrupt handlers) back to h. | |
4621 | * Relies on (h-q[x] == x) being true for x such that | |
4622 | * 0 <= x < MAX_REPLY_QUEUES. | |
4623 | */ | |
4624 | static struct ctlr_info *queue_to_hba(u8 *queue) | |
64670ac8 | 4625 | { |
254f796b MG |
4626 | return container_of((queue - *queue), struct ctlr_info, q[0]); |
4627 | } | |
4628 | ||
4629 | static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue) | |
4630 | { | |
4631 | struct ctlr_info *h = queue_to_hba(queue); | |
4632 | u8 q = *(u8 *) queue; | |
64670ac8 SC |
4633 | u32 raw_tag; |
4634 | ||
4635 | if (ignore_bogus_interrupt(h)) | |
4636 | return IRQ_NONE; | |
4637 | ||
4638 | if (interrupt_not_for_us(h)) | |
4639 | return IRQ_NONE; | |
a0c12413 | 4640 | h->last_intr_timestamp = get_jiffies_64(); |
64670ac8 | 4641 | while (interrupt_pending(h)) { |
254f796b | 4642 | raw_tag = get_next_completion(h, q); |
64670ac8 | 4643 | while (raw_tag != FIFO_EMPTY) |
254f796b | 4644 | raw_tag = next_command(h, q); |
64670ac8 | 4645 | } |
64670ac8 SC |
4646 | return IRQ_HANDLED; |
4647 | } | |
4648 | ||
254f796b | 4649 | static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue) |
64670ac8 | 4650 | { |
254f796b | 4651 | struct ctlr_info *h = queue_to_hba(queue); |
64670ac8 | 4652 | u32 raw_tag; |
254f796b | 4653 | u8 q = *(u8 *) queue; |
64670ac8 SC |
4654 | |
4655 | if (ignore_bogus_interrupt(h)) | |
4656 | return IRQ_NONE; | |
4657 | ||
a0c12413 | 4658 | h->last_intr_timestamp = get_jiffies_64(); |
254f796b | 4659 | raw_tag = get_next_completion(h, q); |
64670ac8 | 4660 | while (raw_tag != FIFO_EMPTY) |
254f796b | 4661 | raw_tag = next_command(h, q); |
64670ac8 SC |
4662 | return IRQ_HANDLED; |
4663 | } | |
4664 | ||
254f796b | 4665 | static irqreturn_t do_hpsa_intr_intx(int irq, void *queue) |
edd16368 | 4666 | { |
254f796b | 4667 | struct ctlr_info *h = queue_to_hba((u8 *) queue); |
303932fd | 4668 | u32 raw_tag; |
254f796b | 4669 | u8 q = *(u8 *) queue; |
edd16368 SC |
4670 | |
4671 | if (interrupt_not_for_us(h)) | |
4672 | return IRQ_NONE; | |
a0c12413 | 4673 | h->last_intr_timestamp = get_jiffies_64(); |
10f66018 | 4674 | while (interrupt_pending(h)) { |
254f796b | 4675 | raw_tag = get_next_completion(h, q); |
10f66018 | 4676 | while (raw_tag != FIFO_EMPTY) { |
1d94f94d SC |
4677 | if (likely(hpsa_tag_contains_index(raw_tag))) |
4678 | process_indexed_cmd(h, raw_tag); | |
10f66018 | 4679 | else |
1d94f94d | 4680 | process_nonindexed_cmd(h, raw_tag); |
254f796b | 4681 | raw_tag = next_command(h, q); |
10f66018 SC |
4682 | } |
4683 | } | |
10f66018 SC |
4684 | return IRQ_HANDLED; |
4685 | } | |
4686 | ||
254f796b | 4687 | static irqreturn_t do_hpsa_intr_msi(int irq, void *queue) |
10f66018 | 4688 | { |
254f796b | 4689 | struct ctlr_info *h = queue_to_hba(queue); |
10f66018 | 4690 | u32 raw_tag; |
254f796b | 4691 | u8 q = *(u8 *) queue; |
10f66018 | 4692 | |
a0c12413 | 4693 | h->last_intr_timestamp = get_jiffies_64(); |
254f796b | 4694 | raw_tag = get_next_completion(h, q); |
303932fd | 4695 | while (raw_tag != FIFO_EMPTY) { |
1d94f94d SC |
4696 | if (likely(hpsa_tag_contains_index(raw_tag))) |
4697 | process_indexed_cmd(h, raw_tag); | |
303932fd | 4698 | else |
1d94f94d | 4699 | process_nonindexed_cmd(h, raw_tag); |
254f796b | 4700 | raw_tag = next_command(h, q); |
edd16368 | 4701 | } |
edd16368 SC |
4702 | return IRQ_HANDLED; |
4703 | } | |
4704 | ||
a9a3a273 SC |
4705 | /* Send a message CDB to the firmware. Careful, this only works |
4706 | * in simple mode, not performant mode due to the tag lookup. | |
4707 | * We only ever use this immediately after a controller reset. | |
4708 | */ | |
6f039790 GKH |
4709 | static int hpsa_message(struct pci_dev *pdev, unsigned char opcode, |
4710 | unsigned char type) | |
edd16368 SC |
4711 | { |
4712 | struct Command { | |
4713 | struct CommandListHeader CommandHeader; | |
4714 | struct RequestBlock Request; | |
4715 | struct ErrDescriptor ErrorDescriptor; | |
4716 | }; | |
4717 | struct Command *cmd; | |
4718 | static const size_t cmd_sz = sizeof(*cmd) + | |
4719 | sizeof(cmd->ErrorDescriptor); | |
4720 | dma_addr_t paddr64; | |
4721 | uint32_t paddr32, tag; | |
4722 | void __iomem *vaddr; | |
4723 | int i, err; | |
4724 | ||
4725 | vaddr = pci_ioremap_bar(pdev, 0); | |
4726 | if (vaddr == NULL) | |
4727 | return -ENOMEM; | |
4728 | ||
4729 | /* The Inbound Post Queue only accepts 32-bit physical addresses for the | |
4730 | * CCISS commands, so they must be allocated from the lower 4GiB of | |
4731 | * memory. | |
4732 | */ | |
4733 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
4734 | if (err) { | |
4735 | iounmap(vaddr); | |
4736 | return -ENOMEM; | |
4737 | } | |
4738 | ||
4739 | cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64); | |
4740 | if (cmd == NULL) { | |
4741 | iounmap(vaddr); | |
4742 | return -ENOMEM; | |
4743 | } | |
4744 | ||
4745 | /* This must fit, because of the 32-bit consistent DMA mask. Also, | |
4746 | * although there's no guarantee, we assume that the address is at | |
4747 | * least 4-byte aligned (most likely, it's page-aligned). | |
4748 | */ | |
4749 | paddr32 = paddr64; | |
4750 | ||
4751 | cmd->CommandHeader.ReplyQueue = 0; | |
4752 | cmd->CommandHeader.SGList = 0; | |
4753 | cmd->CommandHeader.SGTotal = 0; | |
4754 | cmd->CommandHeader.Tag.lower = paddr32; | |
4755 | cmd->CommandHeader.Tag.upper = 0; | |
4756 | memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8); | |
4757 | ||
4758 | cmd->Request.CDBLen = 16; | |
4759 | cmd->Request.Type.Type = TYPE_MSG; | |
4760 | cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE; | |
4761 | cmd->Request.Type.Direction = XFER_NONE; | |
4762 | cmd->Request.Timeout = 0; /* Don't time out */ | |
4763 | cmd->Request.CDB[0] = opcode; | |
4764 | cmd->Request.CDB[1] = type; | |
4765 | memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */ | |
4766 | cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd); | |
4767 | cmd->ErrorDescriptor.Addr.upper = 0; | |
4768 | cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo); | |
4769 | ||
4770 | writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET); | |
4771 | ||
4772 | for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) { | |
4773 | tag = readl(vaddr + SA5_REPLY_PORT_OFFSET); | |
a9a3a273 | 4774 | if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32) |
edd16368 SC |
4775 | break; |
4776 | msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS); | |
4777 | } | |
4778 | ||
4779 | iounmap(vaddr); | |
4780 | ||
4781 | /* we leak the DMA buffer here ... no choice since the controller could | |
4782 | * still complete the command. | |
4783 | */ | |
4784 | if (i == HPSA_MSG_SEND_RETRY_LIMIT) { | |
4785 | dev_err(&pdev->dev, "controller message %02x:%02x timed out\n", | |
4786 | opcode, type); | |
4787 | return -ETIMEDOUT; | |
4788 | } | |
4789 | ||
4790 | pci_free_consistent(pdev, cmd_sz, cmd, paddr64); | |
4791 | ||
4792 | if (tag & HPSA_ERROR_BIT) { | |
4793 | dev_err(&pdev->dev, "controller message %02x:%02x failed\n", | |
4794 | opcode, type); | |
4795 | return -EIO; | |
4796 | } | |
4797 | ||
4798 | dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n", | |
4799 | opcode, type); | |
4800 | return 0; | |
4801 | } | |
4802 | ||
edd16368 SC |
4803 | #define hpsa_noop(p) hpsa_message(p, 3, 0) |
4804 | ||
1df8552a | 4805 | static int hpsa_controller_hard_reset(struct pci_dev *pdev, |
cf0b08d0 | 4806 | void * __iomem vaddr, u32 use_doorbell) |
1df8552a SC |
4807 | { |
4808 | u16 pmcsr; | |
4809 | int pos; | |
4810 | ||
4811 | if (use_doorbell) { | |
4812 | /* For everything after the P600, the PCI power state method | |
4813 | * of resetting the controller doesn't work, so we have this | |
4814 | * other way using the doorbell register. | |
4815 | */ | |
4816 | dev_info(&pdev->dev, "using doorbell to reset controller\n"); | |
cf0b08d0 | 4817 | writel(use_doorbell, vaddr + SA5_DOORBELL); |
85009239 SC |
4818 | |
4819 | /* PMC hardware guys tell us we need a 5 second delay after | |
4820 | * doorbell reset and before any attempt to talk to the board | |
4821 | * at all to ensure that this actually works and doesn't fall | |
4822 | * over in some weird corner cases. | |
4823 | */ | |
4824 | msleep(5000); | |
1df8552a SC |
4825 | } else { /* Try to do it the PCI power state way */ |
4826 | ||
4827 | /* Quoting from the Open CISS Specification: "The Power | |
4828 | * Management Control/Status Register (CSR) controls the power | |
4829 | * state of the device. The normal operating state is D0, | |
4830 | * CSR=00h. The software off state is D3, CSR=03h. To reset | |
4831 | * the controller, place the interface device in D3 then to D0, | |
4832 | * this causes a secondary PCI reset which will reset the | |
4833 | * controller." */ | |
4834 | ||
4835 | pos = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
4836 | if (pos == 0) { | |
4837 | dev_err(&pdev->dev, | |
4838 | "hpsa_reset_controller: " | |
4839 | "PCI PM not supported\n"); | |
4840 | return -ENODEV; | |
4841 | } | |
4842 | dev_info(&pdev->dev, "using PCI PM to reset controller\n"); | |
4843 | /* enter the D3hot power management state */ | |
4844 | pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr); | |
4845 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
4846 | pmcsr |= PCI_D3hot; | |
4847 | pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr); | |
4848 | ||
4849 | msleep(500); | |
4850 | ||
4851 | /* enter the D0 power management state */ | |
4852 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
4853 | pmcsr |= PCI_D0; | |
4854 | pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr); | |
c4853efe MM |
4855 | |
4856 | /* | |
4857 | * The P600 requires a small delay when changing states. | |
4858 | * Otherwise we may think the board did not reset and we bail. | |
4859 | * This for kdump only and is particular to the P600. | |
4860 | */ | |
4861 | msleep(500); | |
1df8552a SC |
4862 | } |
4863 | return 0; | |
4864 | } | |
4865 | ||
6f039790 | 4866 | static void init_driver_version(char *driver_version, int len) |
580ada3c SC |
4867 | { |
4868 | memset(driver_version, 0, len); | |
f79cfec6 | 4869 | strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1); |
580ada3c SC |
4870 | } |
4871 | ||
6f039790 | 4872 | static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable) |
580ada3c SC |
4873 | { |
4874 | char *driver_version; | |
4875 | int i, size = sizeof(cfgtable->driver_version); | |
4876 | ||
4877 | driver_version = kmalloc(size, GFP_KERNEL); | |
4878 | if (!driver_version) | |
4879 | return -ENOMEM; | |
4880 | ||
4881 | init_driver_version(driver_version, size); | |
4882 | for (i = 0; i < size; i++) | |
4883 | writeb(driver_version[i], &cfgtable->driver_version[i]); | |
4884 | kfree(driver_version); | |
4885 | return 0; | |
4886 | } | |
4887 | ||
6f039790 GKH |
4888 | static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable, |
4889 | unsigned char *driver_ver) | |
580ada3c SC |
4890 | { |
4891 | int i; | |
4892 | ||
4893 | for (i = 0; i < sizeof(cfgtable->driver_version); i++) | |
4894 | driver_ver[i] = readb(&cfgtable->driver_version[i]); | |
4895 | } | |
4896 | ||
6f039790 | 4897 | static int controller_reset_failed(struct CfgTable __iomem *cfgtable) |
580ada3c SC |
4898 | { |
4899 | ||
4900 | char *driver_ver, *old_driver_ver; | |
4901 | int rc, size = sizeof(cfgtable->driver_version); | |
4902 | ||
4903 | old_driver_ver = kmalloc(2 * size, GFP_KERNEL); | |
4904 | if (!old_driver_ver) | |
4905 | return -ENOMEM; | |
4906 | driver_ver = old_driver_ver + size; | |
4907 | ||
4908 | /* After a reset, the 32 bytes of "driver version" in the cfgtable | |
4909 | * should have been changed, otherwise we know the reset failed. | |
4910 | */ | |
4911 | init_driver_version(old_driver_ver, size); | |
4912 | read_driver_ver_from_cfgtable(cfgtable, driver_ver); | |
4913 | rc = !memcmp(driver_ver, old_driver_ver, size); | |
4914 | kfree(old_driver_ver); | |
4915 | return rc; | |
4916 | } | |
edd16368 | 4917 | /* This does a hard reset of the controller using PCI power management |
1df8552a | 4918 | * states or the using the doorbell register. |
edd16368 | 4919 | */ |
6f039790 | 4920 | static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev) |
edd16368 | 4921 | { |
1df8552a SC |
4922 | u64 cfg_offset; |
4923 | u32 cfg_base_addr; | |
4924 | u64 cfg_base_addr_index; | |
4925 | void __iomem *vaddr; | |
4926 | unsigned long paddr; | |
580ada3c | 4927 | u32 misc_fw_support; |
270d05de | 4928 | int rc; |
1df8552a | 4929 | struct CfgTable __iomem *cfgtable; |
cf0b08d0 | 4930 | u32 use_doorbell; |
18867659 | 4931 | u32 board_id; |
270d05de | 4932 | u16 command_register; |
edd16368 | 4933 | |
1df8552a SC |
4934 | /* For controllers as old as the P600, this is very nearly |
4935 | * the same thing as | |
edd16368 SC |
4936 | * |
4937 | * pci_save_state(pci_dev); | |
4938 | * pci_set_power_state(pci_dev, PCI_D3hot); | |
4939 | * pci_set_power_state(pci_dev, PCI_D0); | |
4940 | * pci_restore_state(pci_dev); | |
4941 | * | |
1df8552a SC |
4942 | * For controllers newer than the P600, the pci power state |
4943 | * method of resetting doesn't work so we have another way | |
4944 | * using the doorbell register. | |
edd16368 | 4945 | */ |
18867659 | 4946 | |
25c1e56a | 4947 | rc = hpsa_lookup_board_id(pdev, &board_id); |
46380786 | 4948 | if (rc < 0 || !ctlr_is_resettable(board_id)) { |
25c1e56a SC |
4949 | dev_warn(&pdev->dev, "Not resetting device.\n"); |
4950 | return -ENODEV; | |
4951 | } | |
46380786 SC |
4952 | |
4953 | /* if controller is soft- but not hard resettable... */ | |
4954 | if (!ctlr_is_hard_resettable(board_id)) | |
4955 | return -ENOTSUPP; /* try soft reset later. */ | |
18867659 | 4956 | |
270d05de SC |
4957 | /* Save the PCI command register */ |
4958 | pci_read_config_word(pdev, 4, &command_register); | |
4959 | /* Turn the board off. This is so that later pci_restore_state() | |
4960 | * won't turn the board on before the rest of config space is ready. | |
4961 | */ | |
4962 | pci_disable_device(pdev); | |
4963 | pci_save_state(pdev); | |
edd16368 | 4964 | |
1df8552a SC |
4965 | /* find the first memory BAR, so we can find the cfg table */ |
4966 | rc = hpsa_pci_find_memory_BAR(pdev, &paddr); | |
4967 | if (rc) | |
4968 | return rc; | |
4969 | vaddr = remap_pci_mem(paddr, 0x250); | |
4970 | if (!vaddr) | |
4971 | return -ENOMEM; | |
edd16368 | 4972 | |
1df8552a SC |
4973 | /* find cfgtable in order to check if reset via doorbell is supported */ |
4974 | rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr, | |
4975 | &cfg_base_addr_index, &cfg_offset); | |
4976 | if (rc) | |
4977 | goto unmap_vaddr; | |
4978 | cfgtable = remap_pci_mem(pci_resource_start(pdev, | |
4979 | cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable)); | |
4980 | if (!cfgtable) { | |
4981 | rc = -ENOMEM; | |
4982 | goto unmap_vaddr; | |
4983 | } | |
580ada3c SC |
4984 | rc = write_driver_ver_to_cfgtable(cfgtable); |
4985 | if (rc) | |
4986 | goto unmap_vaddr; | |
edd16368 | 4987 | |
cf0b08d0 SC |
4988 | /* If reset via doorbell register is supported, use that. |
4989 | * There are two such methods. Favor the newest method. | |
4990 | */ | |
1df8552a | 4991 | misc_fw_support = readl(&cfgtable->misc_fw_support); |
cf0b08d0 SC |
4992 | use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2; |
4993 | if (use_doorbell) { | |
4994 | use_doorbell = DOORBELL_CTLR_RESET2; | |
4995 | } else { | |
4996 | use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET; | |
4997 | if (use_doorbell) { | |
fba63097 MM |
4998 | dev_warn(&pdev->dev, "Soft reset not supported. " |
4999 | "Firmware update is required.\n"); | |
64670ac8 | 5000 | rc = -ENOTSUPP; /* try soft reset */ |
cf0b08d0 SC |
5001 | goto unmap_cfgtable; |
5002 | } | |
5003 | } | |
edd16368 | 5004 | |
1df8552a SC |
5005 | rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell); |
5006 | if (rc) | |
5007 | goto unmap_cfgtable; | |
edd16368 | 5008 | |
270d05de SC |
5009 | pci_restore_state(pdev); |
5010 | rc = pci_enable_device(pdev); | |
5011 | if (rc) { | |
5012 | dev_warn(&pdev->dev, "failed to enable device.\n"); | |
5013 | goto unmap_cfgtable; | |
edd16368 | 5014 | } |
270d05de | 5015 | pci_write_config_word(pdev, 4, command_register); |
edd16368 | 5016 | |
1df8552a SC |
5017 | /* Some devices (notably the HP Smart Array 5i Controller) |
5018 | need a little pause here */ | |
5019 | msleep(HPSA_POST_RESET_PAUSE_MSECS); | |
5020 | ||
fe5389c8 SC |
5021 | rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY); |
5022 | if (rc) { | |
5023 | dev_warn(&pdev->dev, | |
64670ac8 SC |
5024 | "failed waiting for board to become ready " |
5025 | "after hard reset\n"); | |
fe5389c8 SC |
5026 | goto unmap_cfgtable; |
5027 | } | |
fe5389c8 | 5028 | |
580ada3c SC |
5029 | rc = controller_reset_failed(vaddr); |
5030 | if (rc < 0) | |
5031 | goto unmap_cfgtable; | |
5032 | if (rc) { | |
64670ac8 SC |
5033 | dev_warn(&pdev->dev, "Unable to successfully reset " |
5034 | "controller. Will try soft reset.\n"); | |
5035 | rc = -ENOTSUPP; | |
580ada3c | 5036 | } else { |
64670ac8 | 5037 | dev_info(&pdev->dev, "board ready after hard reset.\n"); |
1df8552a SC |
5038 | } |
5039 | ||
5040 | unmap_cfgtable: | |
5041 | iounmap(cfgtable); | |
5042 | ||
5043 | unmap_vaddr: | |
5044 | iounmap(vaddr); | |
5045 | return rc; | |
edd16368 SC |
5046 | } |
5047 | ||
5048 | /* | |
5049 | * We cannot read the structure directly, for portability we must use | |
5050 | * the io functions. | |
5051 | * This is for debug only. | |
5052 | */ | |
edd16368 SC |
5053 | static void print_cfg_table(struct device *dev, struct CfgTable *tb) |
5054 | { | |
58f8665c | 5055 | #ifdef HPSA_DEBUG |
edd16368 SC |
5056 | int i; |
5057 | char temp_name[17]; | |
5058 | ||
5059 | dev_info(dev, "Controller Configuration information\n"); | |
5060 | dev_info(dev, "------------------------------------\n"); | |
5061 | for (i = 0; i < 4; i++) | |
5062 | temp_name[i] = readb(&(tb->Signature[i])); | |
5063 | temp_name[4] = '\0'; | |
5064 | dev_info(dev, " Signature = %s\n", temp_name); | |
5065 | dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence))); | |
5066 | dev_info(dev, " Transport methods supported = 0x%x\n", | |
5067 | readl(&(tb->TransportSupport))); | |
5068 | dev_info(dev, " Transport methods active = 0x%x\n", | |
5069 | readl(&(tb->TransportActive))); | |
5070 | dev_info(dev, " Requested transport Method = 0x%x\n", | |
5071 | readl(&(tb->HostWrite.TransportRequest))); | |
5072 | dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n", | |
5073 | readl(&(tb->HostWrite.CoalIntDelay))); | |
5074 | dev_info(dev, " Coalesce Interrupt Count = 0x%x\n", | |
5075 | readl(&(tb->HostWrite.CoalIntCount))); | |
5076 | dev_info(dev, " Max outstanding commands = 0x%d\n", | |
5077 | readl(&(tb->CmdsOutMax))); | |
5078 | dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes))); | |
5079 | for (i = 0; i < 16; i++) | |
5080 | temp_name[i] = readb(&(tb->ServerName[i])); | |
5081 | temp_name[16] = '\0'; | |
5082 | dev_info(dev, " Server Name = %s\n", temp_name); | |
5083 | dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n", | |
5084 | readl(&(tb->HeartBeat))); | |
edd16368 | 5085 | #endif /* HPSA_DEBUG */ |
58f8665c | 5086 | } |
edd16368 SC |
5087 | |
5088 | static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr) | |
5089 | { | |
5090 | int i, offset, mem_type, bar_type; | |
5091 | ||
5092 | if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */ | |
5093 | return 0; | |
5094 | offset = 0; | |
5095 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
5096 | bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE; | |
5097 | if (bar_type == PCI_BASE_ADDRESS_SPACE_IO) | |
5098 | offset += 4; | |
5099 | else { | |
5100 | mem_type = pci_resource_flags(pdev, i) & | |
5101 | PCI_BASE_ADDRESS_MEM_TYPE_MASK; | |
5102 | switch (mem_type) { | |
5103 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
5104 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
5105 | offset += 4; /* 32 bit */ | |
5106 | break; | |
5107 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
5108 | offset += 8; | |
5109 | break; | |
5110 | default: /* reserved in PCI 2.2 */ | |
5111 | dev_warn(&pdev->dev, | |
5112 | "base address is invalid\n"); | |
5113 | return -1; | |
5114 | break; | |
5115 | } | |
5116 | } | |
5117 | if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0) | |
5118 | return i + 1; | |
5119 | } | |
5120 | return -1; | |
5121 | } | |
5122 | ||
5123 | /* If MSI/MSI-X is supported by the kernel we will try to enable it on | |
5124 | * controllers that are capable. If not, we use IO-APIC mode. | |
5125 | */ | |
5126 | ||
6f039790 | 5127 | static void hpsa_interrupt_mode(struct ctlr_info *h) |
edd16368 SC |
5128 | { |
5129 | #ifdef CONFIG_PCI_MSI | |
254f796b MG |
5130 | int err, i; |
5131 | struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES]; | |
5132 | ||
5133 | for (i = 0; i < MAX_REPLY_QUEUES; i++) { | |
5134 | hpsa_msix_entries[i].vector = 0; | |
5135 | hpsa_msix_entries[i].entry = i; | |
5136 | } | |
edd16368 SC |
5137 | |
5138 | /* Some boards advertise MSI but don't really support it */ | |
6b3f4c52 SC |
5139 | if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) || |
5140 | (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11)) | |
edd16368 | 5141 | goto default_int_mode; |
55c06c71 SC |
5142 | if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) { |
5143 | dev_info(&h->pdev->dev, "MSIX\n"); | |
eee0f03a | 5144 | h->msix_vector = MAX_REPLY_QUEUES; |
254f796b | 5145 | err = pci_enable_msix(h->pdev, hpsa_msix_entries, |
eee0f03a | 5146 | h->msix_vector); |
edd16368 | 5147 | if (err > 0) { |
55c06c71 | 5148 | dev_warn(&h->pdev->dev, "only %d MSI-X vectors " |
edd16368 | 5149 | "available\n", err); |
eee0f03a HR |
5150 | h->msix_vector = err; |
5151 | err = pci_enable_msix(h->pdev, hpsa_msix_entries, | |
5152 | h->msix_vector); | |
5153 | } | |
5154 | if (!err) { | |
5155 | for (i = 0; i < h->msix_vector; i++) | |
5156 | h->intr[i] = hpsa_msix_entries[i].vector; | |
5157 | return; | |
edd16368 | 5158 | } else { |
55c06c71 | 5159 | dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", |
edd16368 | 5160 | err); |
eee0f03a | 5161 | h->msix_vector = 0; |
edd16368 SC |
5162 | goto default_int_mode; |
5163 | } | |
5164 | } | |
55c06c71 SC |
5165 | if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) { |
5166 | dev_info(&h->pdev->dev, "MSI\n"); | |
5167 | if (!pci_enable_msi(h->pdev)) | |
edd16368 SC |
5168 | h->msi_vector = 1; |
5169 | else | |
55c06c71 | 5170 | dev_warn(&h->pdev->dev, "MSI init failed\n"); |
edd16368 SC |
5171 | } |
5172 | default_int_mode: | |
5173 | #endif /* CONFIG_PCI_MSI */ | |
5174 | /* if we get here we're going to use the default interrupt mode */ | |
a9a3a273 | 5175 | h->intr[h->intr_mode] = h->pdev->irq; |
edd16368 SC |
5176 | } |
5177 | ||
6f039790 | 5178 | static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id) |
e5c880d1 SC |
5179 | { |
5180 | int i; | |
5181 | u32 subsystem_vendor_id, subsystem_device_id; | |
5182 | ||
5183 | subsystem_vendor_id = pdev->subsystem_vendor; | |
5184 | subsystem_device_id = pdev->subsystem_device; | |
5185 | *board_id = ((subsystem_device_id << 16) & 0xffff0000) | | |
5186 | subsystem_vendor_id; | |
5187 | ||
5188 | for (i = 0; i < ARRAY_SIZE(products); i++) | |
5189 | if (*board_id == products[i].board_id) | |
5190 | return i; | |
5191 | ||
6798cc0a SC |
5192 | if ((subsystem_vendor_id != PCI_VENDOR_ID_HP && |
5193 | subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) || | |
5194 | !hpsa_allow_any) { | |
e5c880d1 SC |
5195 | dev_warn(&pdev->dev, "unrecognized board ID: " |
5196 | "0x%08x, ignoring.\n", *board_id); | |
5197 | return -ENODEV; | |
5198 | } | |
5199 | return ARRAY_SIZE(products) - 1; /* generic unknown smart array */ | |
5200 | } | |
5201 | ||
6f039790 GKH |
5202 | static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, |
5203 | unsigned long *memory_bar) | |
3a7774ce SC |
5204 | { |
5205 | int i; | |
5206 | ||
5207 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
12d2cd47 | 5208 | if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { |
3a7774ce | 5209 | /* addressing mode bits already removed */ |
12d2cd47 SC |
5210 | *memory_bar = pci_resource_start(pdev, i); |
5211 | dev_dbg(&pdev->dev, "memory BAR = %lx\n", | |
3a7774ce SC |
5212 | *memory_bar); |
5213 | return 0; | |
5214 | } | |
12d2cd47 | 5215 | dev_warn(&pdev->dev, "no memory BAR found\n"); |
3a7774ce SC |
5216 | return -ENODEV; |
5217 | } | |
5218 | ||
6f039790 GKH |
5219 | static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, |
5220 | int wait_for_ready) | |
2c4c8c8b | 5221 | { |
fe5389c8 | 5222 | int i, iterations; |
2c4c8c8b | 5223 | u32 scratchpad; |
fe5389c8 SC |
5224 | if (wait_for_ready) |
5225 | iterations = HPSA_BOARD_READY_ITERATIONS; | |
5226 | else | |
5227 | iterations = HPSA_BOARD_NOT_READY_ITERATIONS; | |
2c4c8c8b | 5228 | |
fe5389c8 SC |
5229 | for (i = 0; i < iterations; i++) { |
5230 | scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET); | |
5231 | if (wait_for_ready) { | |
5232 | if (scratchpad == HPSA_FIRMWARE_READY) | |
5233 | return 0; | |
5234 | } else { | |
5235 | if (scratchpad != HPSA_FIRMWARE_READY) | |
5236 | return 0; | |
5237 | } | |
2c4c8c8b SC |
5238 | msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS); |
5239 | } | |
fe5389c8 | 5240 | dev_warn(&pdev->dev, "board not ready, timed out.\n"); |
2c4c8c8b SC |
5241 | return -ENODEV; |
5242 | } | |
5243 | ||
6f039790 GKH |
5244 | static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, |
5245 | u32 *cfg_base_addr, u64 *cfg_base_addr_index, | |
5246 | u64 *cfg_offset) | |
a51fd47f SC |
5247 | { |
5248 | *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET); | |
5249 | *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET); | |
5250 | *cfg_base_addr &= (u32) 0x0000ffff; | |
5251 | *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr); | |
5252 | if (*cfg_base_addr_index == -1) { | |
5253 | dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n"); | |
5254 | return -ENODEV; | |
5255 | } | |
5256 | return 0; | |
5257 | } | |
5258 | ||
6f039790 | 5259 | static int hpsa_find_cfgtables(struct ctlr_info *h) |
edd16368 | 5260 | { |
01a02ffc SC |
5261 | u64 cfg_offset; |
5262 | u32 cfg_base_addr; | |
5263 | u64 cfg_base_addr_index; | |
303932fd | 5264 | u32 trans_offset; |
a51fd47f | 5265 | int rc; |
77c4495c | 5266 | |
a51fd47f SC |
5267 | rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, |
5268 | &cfg_base_addr_index, &cfg_offset); | |
5269 | if (rc) | |
5270 | return rc; | |
77c4495c | 5271 | h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev, |
a51fd47f | 5272 | cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable)); |
77c4495c SC |
5273 | if (!h->cfgtable) |
5274 | return -ENOMEM; | |
580ada3c SC |
5275 | rc = write_driver_ver_to_cfgtable(h->cfgtable); |
5276 | if (rc) | |
5277 | return rc; | |
77c4495c | 5278 | /* Find performant mode table. */ |
a51fd47f | 5279 | trans_offset = readl(&h->cfgtable->TransMethodOffset); |
77c4495c SC |
5280 | h->transtable = remap_pci_mem(pci_resource_start(h->pdev, |
5281 | cfg_base_addr_index)+cfg_offset+trans_offset, | |
5282 | sizeof(*h->transtable)); | |
5283 | if (!h->transtable) | |
5284 | return -ENOMEM; | |
5285 | return 0; | |
5286 | } | |
5287 | ||
6f039790 | 5288 | static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h) |
cba3d38b SC |
5289 | { |
5290 | h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands)); | |
72ceeaec SC |
5291 | |
5292 | /* Limit commands in memory limited kdump scenario. */ | |
5293 | if (reset_devices && h->max_commands > 32) | |
5294 | h->max_commands = 32; | |
5295 | ||
cba3d38b SC |
5296 | if (h->max_commands < 16) { |
5297 | dev_warn(&h->pdev->dev, "Controller reports " | |
5298 | "max supported commands of %d, an obvious lie. " | |
5299 | "Using 16. Ensure that firmware is up to date.\n", | |
5300 | h->max_commands); | |
5301 | h->max_commands = 16; | |
5302 | } | |
5303 | } | |
5304 | ||
b93d7536 SC |
5305 | /* Interrogate the hardware for some limits: |
5306 | * max commands, max SG elements without chaining, and with chaining, | |
5307 | * SG chain block size, etc. | |
5308 | */ | |
6f039790 | 5309 | static void hpsa_find_board_params(struct ctlr_info *h) |
b93d7536 | 5310 | { |
cba3d38b | 5311 | hpsa_get_max_perf_mode_cmds(h); |
b93d7536 SC |
5312 | h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */ |
5313 | h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements)); | |
283b4a9b | 5314 | h->fw_support = readl(&(h->cfgtable->misc_fw_support)); |
b93d7536 SC |
5315 | /* |
5316 | * Limit in-command s/g elements to 32 save dma'able memory. | |
5317 | * Howvever spec says if 0, use 31 | |
5318 | */ | |
5319 | h->max_cmd_sg_entries = 31; | |
5320 | if (h->maxsgentries > 512) { | |
5321 | h->max_cmd_sg_entries = 32; | |
5322 | h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1; | |
5323 | h->maxsgentries--; /* save one for chain pointer */ | |
5324 | } else { | |
5325 | h->maxsgentries = 31; /* default to traditional values */ | |
5326 | h->chainsize = 0; | |
5327 | } | |
75167d2c SC |
5328 | |
5329 | /* Find out what task management functions are supported and cache */ | |
5330 | h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags)); | |
0e7a7fce ST |
5331 | if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags)) |
5332 | dev_warn(&h->pdev->dev, "Physical aborts not supported\n"); | |
5333 | if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags)) | |
5334 | dev_warn(&h->pdev->dev, "Logical aborts not supported\n"); | |
b93d7536 SC |
5335 | } |
5336 | ||
76c46e49 SC |
5337 | static inline bool hpsa_CISS_signature_present(struct ctlr_info *h) |
5338 | { | |
0fc9fd40 | 5339 | if (!check_signature(h->cfgtable->Signature, "CISS", 4)) { |
76c46e49 SC |
5340 | dev_warn(&h->pdev->dev, "not a valid CISS config table\n"); |
5341 | return false; | |
5342 | } | |
5343 | return true; | |
5344 | } | |
5345 | ||
97a5e98c | 5346 | static inline void hpsa_set_driver_support_bits(struct ctlr_info *h) |
f7c39101 | 5347 | { |
97a5e98c | 5348 | u32 driver_support; |
f7c39101 | 5349 | |
28e13446 SC |
5350 | #ifdef CONFIG_X86 |
5351 | /* Need to enable prefetch in the SCSI core for 6400 in x86 */ | |
97a5e98c SC |
5352 | driver_support = readl(&(h->cfgtable->driver_support)); |
5353 | driver_support |= ENABLE_SCSI_PREFETCH; | |
f7c39101 | 5354 | #endif |
28e13446 SC |
5355 | driver_support |= ENABLE_UNIT_ATTN; |
5356 | writel(driver_support, &(h->cfgtable->driver_support)); | |
f7c39101 SC |
5357 | } |
5358 | ||
3d0eab67 SC |
5359 | /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result |
5360 | * in a prefetch beyond physical memory. | |
5361 | */ | |
5362 | static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h) | |
5363 | { | |
5364 | u32 dma_prefetch; | |
5365 | ||
5366 | if (h->board_id != 0x3225103C) | |
5367 | return; | |
5368 | dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG); | |
5369 | dma_prefetch |= 0x8000; | |
5370 | writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG); | |
5371 | } | |
5372 | ||
76438d08 SC |
5373 | static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h) |
5374 | { | |
5375 | int i; | |
5376 | u32 doorbell_value; | |
5377 | unsigned long flags; | |
5378 | /* wait until the clear_event_notify bit 6 is cleared by controller. */ | |
5379 | for (i = 0; i < MAX_CONFIG_WAIT; i++) { | |
5380 | spin_lock_irqsave(&h->lock, flags); | |
5381 | doorbell_value = readl(h->vaddr + SA5_DOORBELL); | |
5382 | spin_unlock_irqrestore(&h->lock, flags); | |
5383 | if (!(doorbell_value & DOORBELL_CLEAR_EVENTS)) | |
5384 | break; | |
5385 | /* delay and try again */ | |
5386 | msleep(20); | |
5387 | } | |
5388 | } | |
5389 | ||
6f039790 | 5390 | static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h) |
eb6b2ae9 SC |
5391 | { |
5392 | int i; | |
6eaf46fd SC |
5393 | u32 doorbell_value; |
5394 | unsigned long flags; | |
eb6b2ae9 SC |
5395 | |
5396 | /* under certain very rare conditions, this can take awhile. | |
5397 | * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right | |
5398 | * as we enter this code.) | |
5399 | */ | |
5400 | for (i = 0; i < MAX_CONFIG_WAIT; i++) { | |
6eaf46fd SC |
5401 | spin_lock_irqsave(&h->lock, flags); |
5402 | doorbell_value = readl(h->vaddr + SA5_DOORBELL); | |
5403 | spin_unlock_irqrestore(&h->lock, flags); | |
382be668 | 5404 | if (!(doorbell_value & CFGTBL_ChangeReq)) |
eb6b2ae9 SC |
5405 | break; |
5406 | /* delay and try again */ | |
60d3f5b0 | 5407 | usleep_range(10000, 20000); |
eb6b2ae9 | 5408 | } |
3f4336f3 SC |
5409 | } |
5410 | ||
6f039790 | 5411 | static int hpsa_enter_simple_mode(struct ctlr_info *h) |
3f4336f3 SC |
5412 | { |
5413 | u32 trans_support; | |
5414 | ||
5415 | trans_support = readl(&(h->cfgtable->TransportSupport)); | |
5416 | if (!(trans_support & SIMPLE_MODE)) | |
5417 | return -ENOTSUPP; | |
5418 | ||
5419 | h->max_commands = readl(&(h->cfgtable->CmdsOutMax)); | |
283b4a9b | 5420 | |
3f4336f3 SC |
5421 | /* Update the field, and then ring the doorbell */ |
5422 | writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest)); | |
b9af4937 | 5423 | writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); |
3f4336f3 SC |
5424 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
5425 | hpsa_wait_for_mode_change_ack(h); | |
eb6b2ae9 | 5426 | print_cfg_table(&h->pdev->dev, h->cfgtable); |
283b4a9b SC |
5427 | if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) |
5428 | goto error; | |
960a30e7 | 5429 | h->transMethod = CFGTBL_Trans_Simple; |
eb6b2ae9 | 5430 | return 0; |
283b4a9b SC |
5431 | error: |
5432 | dev_warn(&h->pdev->dev, "unable to get board into simple mode\n"); | |
5433 | return -ENODEV; | |
eb6b2ae9 SC |
5434 | } |
5435 | ||
6f039790 | 5436 | static int hpsa_pci_init(struct ctlr_info *h) |
77c4495c | 5437 | { |
eb6b2ae9 | 5438 | int prod_index, err; |
edd16368 | 5439 | |
e5c880d1 SC |
5440 | prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id); |
5441 | if (prod_index < 0) | |
5442 | return -ENODEV; | |
5443 | h->product_name = products[prod_index].product_name; | |
5444 | h->access = *(products[prod_index].access); | |
edd16368 | 5445 | |
e5a44df8 MG |
5446 | pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S | |
5447 | PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM); | |
5448 | ||
55c06c71 | 5449 | err = pci_enable_device(h->pdev); |
edd16368 | 5450 | if (err) { |
55c06c71 | 5451 | dev_warn(&h->pdev->dev, "unable to enable PCI device\n"); |
edd16368 SC |
5452 | return err; |
5453 | } | |
5454 | ||
5cb460a6 SC |
5455 | /* Enable bus mastering (pci_disable_device may disable this) */ |
5456 | pci_set_master(h->pdev); | |
5457 | ||
f79cfec6 | 5458 | err = pci_request_regions(h->pdev, HPSA); |
edd16368 | 5459 | if (err) { |
55c06c71 SC |
5460 | dev_err(&h->pdev->dev, |
5461 | "cannot obtain PCI resources, aborting\n"); | |
edd16368 SC |
5462 | return err; |
5463 | } | |
6b3f4c52 | 5464 | hpsa_interrupt_mode(h); |
12d2cd47 | 5465 | err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr); |
3a7774ce | 5466 | if (err) |
edd16368 | 5467 | goto err_out_free_res; |
edd16368 | 5468 | h->vaddr = remap_pci_mem(h->paddr, 0x250); |
204892e9 SC |
5469 | if (!h->vaddr) { |
5470 | err = -ENOMEM; | |
5471 | goto err_out_free_res; | |
5472 | } | |
fe5389c8 | 5473 | err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY); |
2c4c8c8b | 5474 | if (err) |
edd16368 | 5475 | goto err_out_free_res; |
77c4495c SC |
5476 | err = hpsa_find_cfgtables(h); |
5477 | if (err) | |
edd16368 | 5478 | goto err_out_free_res; |
b93d7536 | 5479 | hpsa_find_board_params(h); |
edd16368 | 5480 | |
76c46e49 | 5481 | if (!hpsa_CISS_signature_present(h)) { |
edd16368 SC |
5482 | err = -ENODEV; |
5483 | goto err_out_free_res; | |
5484 | } | |
97a5e98c | 5485 | hpsa_set_driver_support_bits(h); |
3d0eab67 | 5486 | hpsa_p600_dma_prefetch_quirk(h); |
eb6b2ae9 SC |
5487 | err = hpsa_enter_simple_mode(h); |
5488 | if (err) | |
edd16368 | 5489 | goto err_out_free_res; |
edd16368 SC |
5490 | return 0; |
5491 | ||
5492 | err_out_free_res: | |
204892e9 SC |
5493 | if (h->transtable) |
5494 | iounmap(h->transtable); | |
5495 | if (h->cfgtable) | |
5496 | iounmap(h->cfgtable); | |
5497 | if (h->vaddr) | |
5498 | iounmap(h->vaddr); | |
f0bd0b68 | 5499 | pci_disable_device(h->pdev); |
55c06c71 | 5500 | pci_release_regions(h->pdev); |
edd16368 SC |
5501 | return err; |
5502 | } | |
5503 | ||
6f039790 | 5504 | static void hpsa_hba_inquiry(struct ctlr_info *h) |
339b2b14 SC |
5505 | { |
5506 | int rc; | |
5507 | ||
5508 | #define HBA_INQUIRY_BYTE_COUNT 64 | |
5509 | h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL); | |
5510 | if (!h->hba_inquiry_data) | |
5511 | return; | |
5512 | rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0, | |
5513 | h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT); | |
5514 | if (rc != 0) { | |
5515 | kfree(h->hba_inquiry_data); | |
5516 | h->hba_inquiry_data = NULL; | |
5517 | } | |
5518 | } | |
5519 | ||
6f039790 | 5520 | static int hpsa_init_reset_devices(struct pci_dev *pdev) |
4c2a8c40 | 5521 | { |
1df8552a | 5522 | int rc, i; |
4c2a8c40 SC |
5523 | |
5524 | if (!reset_devices) | |
5525 | return 0; | |
5526 | ||
1df8552a SC |
5527 | /* Reset the controller with a PCI power-cycle or via doorbell */ |
5528 | rc = hpsa_kdump_hard_reset_controller(pdev); | |
4c2a8c40 | 5529 | |
1df8552a SC |
5530 | /* -ENOTSUPP here means we cannot reset the controller |
5531 | * but it's already (and still) up and running in | |
18867659 SC |
5532 | * "performant mode". Or, it might be 640x, which can't reset |
5533 | * due to concerns about shared bbwc between 6402/6404 pair. | |
1df8552a SC |
5534 | */ |
5535 | if (rc == -ENOTSUPP) | |
64670ac8 | 5536 | return rc; /* just try to do the kdump anyhow. */ |
1df8552a SC |
5537 | if (rc) |
5538 | return -ENODEV; | |
4c2a8c40 SC |
5539 | |
5540 | /* Now try to get the controller to respond to a no-op */ | |
2b870cb3 | 5541 | dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n"); |
4c2a8c40 SC |
5542 | for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) { |
5543 | if (hpsa_noop(pdev) == 0) | |
5544 | break; | |
5545 | else | |
5546 | dev_warn(&pdev->dev, "no-op failed%s\n", | |
5547 | (i < 11 ? "; re-trying" : "")); | |
5548 | } | |
5549 | return 0; | |
5550 | } | |
5551 | ||
6f039790 | 5552 | static int hpsa_allocate_cmd_pool(struct ctlr_info *h) |
2e9d1b36 SC |
5553 | { |
5554 | h->cmd_pool_bits = kzalloc( | |
5555 | DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) * | |
5556 | sizeof(unsigned long), GFP_KERNEL); | |
5557 | h->cmd_pool = pci_alloc_consistent(h->pdev, | |
5558 | h->nr_cmds * sizeof(*h->cmd_pool), | |
5559 | &(h->cmd_pool_dhandle)); | |
5560 | h->errinfo_pool = pci_alloc_consistent(h->pdev, | |
5561 | h->nr_cmds * sizeof(*h->errinfo_pool), | |
5562 | &(h->errinfo_pool_dhandle)); | |
5563 | if ((h->cmd_pool_bits == NULL) | |
5564 | || (h->cmd_pool == NULL) | |
5565 | || (h->errinfo_pool == NULL)) { | |
5566 | dev_err(&h->pdev->dev, "out of memory in %s", __func__); | |
5567 | return -ENOMEM; | |
5568 | } | |
5569 | return 0; | |
5570 | } | |
5571 | ||
5572 | static void hpsa_free_cmd_pool(struct ctlr_info *h) | |
5573 | { | |
5574 | kfree(h->cmd_pool_bits); | |
5575 | if (h->cmd_pool) | |
5576 | pci_free_consistent(h->pdev, | |
5577 | h->nr_cmds * sizeof(struct CommandList), | |
5578 | h->cmd_pool, h->cmd_pool_dhandle); | |
aca9012a SC |
5579 | if (h->ioaccel2_cmd_pool) |
5580 | pci_free_consistent(h->pdev, | |
5581 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), | |
5582 | h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle); | |
2e9d1b36 SC |
5583 | if (h->errinfo_pool) |
5584 | pci_free_consistent(h->pdev, | |
5585 | h->nr_cmds * sizeof(struct ErrorInfo), | |
5586 | h->errinfo_pool, | |
5587 | h->errinfo_pool_dhandle); | |
e1f7de0c MG |
5588 | if (h->ioaccel_cmd_pool) |
5589 | pci_free_consistent(h->pdev, | |
5590 | h->nr_cmds * sizeof(struct io_accel1_cmd), | |
5591 | h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle); | |
2e9d1b36 SC |
5592 | } |
5593 | ||
0ae01a32 SC |
5594 | static int hpsa_request_irq(struct ctlr_info *h, |
5595 | irqreturn_t (*msixhandler)(int, void *), | |
5596 | irqreturn_t (*intxhandler)(int, void *)) | |
5597 | { | |
254f796b | 5598 | int rc, i; |
0ae01a32 | 5599 | |
254f796b MG |
5600 | /* |
5601 | * initialize h->q[x] = x so that interrupt handlers know which | |
5602 | * queue to process. | |
5603 | */ | |
5604 | for (i = 0; i < MAX_REPLY_QUEUES; i++) | |
5605 | h->q[i] = (u8) i; | |
5606 | ||
eee0f03a | 5607 | if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) { |
254f796b | 5608 | /* If performant mode and MSI-X, use multiple reply queues */ |
eee0f03a | 5609 | for (i = 0; i < h->msix_vector; i++) |
254f796b MG |
5610 | rc = request_irq(h->intr[i], msixhandler, |
5611 | 0, h->devname, | |
5612 | &h->q[i]); | |
5613 | } else { | |
5614 | /* Use single reply pool */ | |
eee0f03a | 5615 | if (h->msix_vector > 0 || h->msi_vector) { |
254f796b MG |
5616 | rc = request_irq(h->intr[h->intr_mode], |
5617 | msixhandler, 0, h->devname, | |
5618 | &h->q[h->intr_mode]); | |
5619 | } else { | |
5620 | rc = request_irq(h->intr[h->intr_mode], | |
5621 | intxhandler, IRQF_SHARED, h->devname, | |
5622 | &h->q[h->intr_mode]); | |
5623 | } | |
5624 | } | |
0ae01a32 SC |
5625 | if (rc) { |
5626 | dev_err(&h->pdev->dev, "unable to get irq %d for %s\n", | |
5627 | h->intr[h->intr_mode], h->devname); | |
5628 | return -ENODEV; | |
5629 | } | |
5630 | return 0; | |
5631 | } | |
5632 | ||
6f039790 | 5633 | static int hpsa_kdump_soft_reset(struct ctlr_info *h) |
64670ac8 SC |
5634 | { |
5635 | if (hpsa_send_host_reset(h, RAID_CTLR_LUNID, | |
5636 | HPSA_RESET_TYPE_CONTROLLER)) { | |
5637 | dev_warn(&h->pdev->dev, "Resetting array controller failed.\n"); | |
5638 | return -EIO; | |
5639 | } | |
5640 | ||
5641 | dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n"); | |
5642 | if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) { | |
5643 | dev_warn(&h->pdev->dev, "Soft reset had no effect.\n"); | |
5644 | return -1; | |
5645 | } | |
5646 | ||
5647 | dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n"); | |
5648 | if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) { | |
5649 | dev_warn(&h->pdev->dev, "Board failed to become ready " | |
5650 | "after soft reset.\n"); | |
5651 | return -1; | |
5652 | } | |
5653 | ||
5654 | return 0; | |
5655 | } | |
5656 | ||
254f796b MG |
5657 | static void free_irqs(struct ctlr_info *h) |
5658 | { | |
5659 | int i; | |
5660 | ||
5661 | if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) { | |
5662 | /* Single reply queue, only one irq to free */ | |
5663 | i = h->intr_mode; | |
5664 | free_irq(h->intr[i], &h->q[i]); | |
5665 | return; | |
5666 | } | |
5667 | ||
eee0f03a | 5668 | for (i = 0; i < h->msix_vector; i++) |
254f796b MG |
5669 | free_irq(h->intr[i], &h->q[i]); |
5670 | } | |
5671 | ||
0097f0f4 | 5672 | static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h) |
64670ac8 | 5673 | { |
254f796b | 5674 | free_irqs(h); |
64670ac8 | 5675 | #ifdef CONFIG_PCI_MSI |
0097f0f4 SC |
5676 | if (h->msix_vector) { |
5677 | if (h->pdev->msix_enabled) | |
5678 | pci_disable_msix(h->pdev); | |
5679 | } else if (h->msi_vector) { | |
5680 | if (h->pdev->msi_enabled) | |
5681 | pci_disable_msi(h->pdev); | |
5682 | } | |
64670ac8 | 5683 | #endif /* CONFIG_PCI_MSI */ |
0097f0f4 SC |
5684 | } |
5685 | ||
5686 | static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h) | |
5687 | { | |
5688 | hpsa_free_irqs_and_disable_msix(h); | |
64670ac8 SC |
5689 | hpsa_free_sg_chain_blocks(h); |
5690 | hpsa_free_cmd_pool(h); | |
e1f7de0c | 5691 | kfree(h->ioaccel1_blockFetchTable); |
64670ac8 SC |
5692 | kfree(h->blockFetchTable); |
5693 | pci_free_consistent(h->pdev, h->reply_pool_size, | |
5694 | h->reply_pool, h->reply_pool_dhandle); | |
5695 | if (h->vaddr) | |
5696 | iounmap(h->vaddr); | |
5697 | if (h->transtable) | |
5698 | iounmap(h->transtable); | |
5699 | if (h->cfgtable) | |
5700 | iounmap(h->cfgtable); | |
5701 | pci_release_regions(h->pdev); | |
5702 | kfree(h); | |
5703 | } | |
5704 | ||
a0c12413 SC |
5705 | /* Called when controller lockup detected. */ |
5706 | static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list) | |
5707 | { | |
5708 | struct CommandList *c = NULL; | |
5709 | ||
5710 | assert_spin_locked(&h->lock); | |
5711 | /* Mark all outstanding commands as failed and complete them. */ | |
5712 | while (!list_empty(list)) { | |
5713 | c = list_entry(list->next, struct CommandList, list); | |
5714 | c->err_info->CommandStatus = CMD_HARDWARE_ERR; | |
5a3d16f5 | 5715 | finish_cmd(c); |
a0c12413 SC |
5716 | } |
5717 | } | |
5718 | ||
5719 | static void controller_lockup_detected(struct ctlr_info *h) | |
5720 | { | |
5721 | unsigned long flags; | |
5722 | ||
a0c12413 SC |
5723 | h->access.set_intr_mask(h, HPSA_INTR_OFF); |
5724 | spin_lock_irqsave(&h->lock, flags); | |
5725 | h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); | |
5726 | spin_unlock_irqrestore(&h->lock, flags); | |
5727 | dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n", | |
5728 | h->lockup_detected); | |
5729 | pci_disable_device(h->pdev); | |
5730 | spin_lock_irqsave(&h->lock, flags); | |
5731 | fail_all_cmds_on_list(h, &h->cmpQ); | |
5732 | fail_all_cmds_on_list(h, &h->reqQ); | |
5733 | spin_unlock_irqrestore(&h->lock, flags); | |
5734 | } | |
5735 | ||
a0c12413 SC |
5736 | static void detect_controller_lockup(struct ctlr_info *h) |
5737 | { | |
5738 | u64 now; | |
5739 | u32 heartbeat; | |
5740 | unsigned long flags; | |
5741 | ||
a0c12413 SC |
5742 | now = get_jiffies_64(); |
5743 | /* If we've received an interrupt recently, we're ok. */ | |
5744 | if (time_after64(h->last_intr_timestamp + | |
e85c5974 | 5745 | (h->heartbeat_sample_interval), now)) |
a0c12413 SC |
5746 | return; |
5747 | ||
5748 | /* | |
5749 | * If we've already checked the heartbeat recently, we're ok. | |
5750 | * This could happen if someone sends us a signal. We | |
5751 | * otherwise don't care about signals in this thread. | |
5752 | */ | |
5753 | if (time_after64(h->last_heartbeat_timestamp + | |
e85c5974 | 5754 | (h->heartbeat_sample_interval), now)) |
a0c12413 SC |
5755 | return; |
5756 | ||
5757 | /* If heartbeat has not changed since we last looked, we're not ok. */ | |
5758 | spin_lock_irqsave(&h->lock, flags); | |
5759 | heartbeat = readl(&h->cfgtable->HeartBeat); | |
5760 | spin_unlock_irqrestore(&h->lock, flags); | |
5761 | if (h->last_heartbeat == heartbeat) { | |
5762 | controller_lockup_detected(h); | |
5763 | return; | |
5764 | } | |
5765 | ||
5766 | /* We're ok. */ | |
5767 | h->last_heartbeat = heartbeat; | |
5768 | h->last_heartbeat_timestamp = now; | |
5769 | } | |
5770 | ||
76438d08 SC |
5771 | static int hpsa_kickoff_rescan(struct ctlr_info *h) |
5772 | { | |
5773 | int i; | |
5774 | char *event_type; | |
5775 | ||
5776 | /* Ask the controller to clear the events we're handling. */ | |
1f7cee8c SC |
5777 | if ((h->transMethod & (CFGTBL_Trans_io_accel1 |
5778 | | CFGTBL_Trans_io_accel2)) && | |
76438d08 SC |
5779 | (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE || |
5780 | h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) { | |
5781 | ||
5782 | if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE) | |
5783 | event_type = "state change"; | |
5784 | if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE) | |
5785 | event_type = "configuration change"; | |
5786 | /* Stop sending new RAID offload reqs via the IO accelerator */ | |
5787 | scsi_block_requests(h->scsi_host); | |
5788 | for (i = 0; i < h->ndevices; i++) | |
5789 | h->dev[i]->offload_enabled = 0; | |
5790 | hpsa_drain_commands(h); | |
5791 | /* Set 'accelerator path config change' bit */ | |
5792 | dev_warn(&h->pdev->dev, | |
5793 | "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n", | |
5794 | h->events, event_type); | |
5795 | writel(h->events, &(h->cfgtable->clear_event_notify)); | |
5796 | /* Set the "clear event notify field update" bit 6 */ | |
5797 | writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); | |
5798 | /* Wait until ctlr clears 'clear event notify field', bit 6 */ | |
5799 | hpsa_wait_for_clear_event_notify_ack(h); | |
5800 | scsi_unblock_requests(h->scsi_host); | |
5801 | } else { | |
5802 | /* Acknowledge controller notification events. */ | |
5803 | writel(h->events, &(h->cfgtable->clear_event_notify)); | |
5804 | writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); | |
5805 | hpsa_wait_for_clear_event_notify_ack(h); | |
5806 | #if 0 | |
5807 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); | |
5808 | hpsa_wait_for_mode_change_ack(h); | |
5809 | #endif | |
5810 | } | |
5811 | ||
5812 | /* Something in the device list may have changed to trigger | |
5813 | * the event, so do a rescan. | |
5814 | */ | |
5815 | hpsa_scan_start(h->scsi_host); | |
5816 | /* release reference taken on scsi host in check_controller_events */ | |
5817 | scsi_host_put(h->scsi_host); | |
5818 | return 0; | |
5819 | } | |
5820 | ||
5821 | /* Check a register on the controller to see if there are configuration | |
5822 | * changes (added/changed/removed logical drives, etc.) which mean that | |
5823 | * we should rescan the controller for devices. If so, add the controller | |
5824 | * to the list of controllers needing to be rescanned, and gets a | |
5825 | * reference to the associated scsi_host. | |
5826 | */ | |
5827 | static void hpsa_ctlr_needs_rescan(struct ctlr_info *h) | |
5828 | { | |
5829 | if (!(h->fw_support & MISC_FW_EVENT_NOTIFY)) | |
5830 | return; | |
5831 | ||
5832 | h->events = readl(&(h->cfgtable->event_notify)); | |
5833 | if (!h->events) | |
5834 | return; | |
5835 | ||
5836 | /* | |
5837 | * Take a reference on scsi host for the duration of the scan | |
5838 | * Release in hpsa_kickoff_rescan(). No lock needed for scan_list | |
5839 | * as only a single thread accesses this list. | |
5840 | */ | |
5841 | scsi_host_get(h->scsi_host); | |
5842 | hpsa_kickoff_rescan(h); | |
5843 | } | |
5844 | ||
8a98db73 | 5845 | static void hpsa_monitor_ctlr_worker(struct work_struct *work) |
a0c12413 SC |
5846 | { |
5847 | unsigned long flags; | |
8a98db73 SC |
5848 | struct ctlr_info *h = container_of(to_delayed_work(work), |
5849 | struct ctlr_info, monitor_ctlr_work); | |
5850 | detect_controller_lockup(h); | |
5851 | if (h->lockup_detected) | |
5852 | return; | |
76438d08 | 5853 | hpsa_ctlr_needs_rescan(h); |
8a98db73 SC |
5854 | spin_lock_irqsave(&h->lock, flags); |
5855 | if (h->remove_in_progress) { | |
5856 | spin_unlock_irqrestore(&h->lock, flags); | |
a0c12413 SC |
5857 | return; |
5858 | } | |
8a98db73 SC |
5859 | schedule_delayed_work(&h->monitor_ctlr_work, |
5860 | h->heartbeat_sample_interval); | |
5861 | spin_unlock_irqrestore(&h->lock, flags); | |
a0c12413 SC |
5862 | } |
5863 | ||
6f039790 | 5864 | static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
edd16368 | 5865 | { |
4c2a8c40 | 5866 | int dac, rc; |
edd16368 | 5867 | struct ctlr_info *h; |
64670ac8 SC |
5868 | int try_soft_reset = 0; |
5869 | unsigned long flags; | |
edd16368 SC |
5870 | |
5871 | if (number_of_controllers == 0) | |
5872 | printk(KERN_INFO DRIVER_NAME "\n"); | |
edd16368 | 5873 | |
4c2a8c40 | 5874 | rc = hpsa_init_reset_devices(pdev); |
64670ac8 SC |
5875 | if (rc) { |
5876 | if (rc != -ENOTSUPP) | |
5877 | return rc; | |
5878 | /* If the reset fails in a particular way (it has no way to do | |
5879 | * a proper hard reset, so returns -ENOTSUPP) we can try to do | |
5880 | * a soft reset once we get the controller configured up to the | |
5881 | * point that it can accept a command. | |
5882 | */ | |
5883 | try_soft_reset = 1; | |
5884 | rc = 0; | |
5885 | } | |
5886 | ||
5887 | reinit_after_soft_reset: | |
edd16368 | 5888 | |
303932fd DB |
5889 | /* Command structures must be aligned on a 32-byte boundary because |
5890 | * the 5 lower bits of the address are used by the hardware. and by | |
5891 | * the driver. See comments in hpsa.h for more info. | |
5892 | */ | |
283b4a9b | 5893 | #define COMMANDLIST_ALIGNMENT 128 |
303932fd | 5894 | BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT); |
edd16368 SC |
5895 | h = kzalloc(sizeof(*h), GFP_KERNEL); |
5896 | if (!h) | |
ecd9aad4 | 5897 | return -ENOMEM; |
edd16368 | 5898 | |
55c06c71 | 5899 | h->pdev = pdev; |
a9a3a273 | 5900 | h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT; |
9e0fc764 SC |
5901 | INIT_LIST_HEAD(&h->cmpQ); |
5902 | INIT_LIST_HEAD(&h->reqQ); | |
6eaf46fd SC |
5903 | spin_lock_init(&h->lock); |
5904 | spin_lock_init(&h->scan_lock); | |
0390f0c0 | 5905 | spin_lock_init(&h->passthru_count_lock); |
55c06c71 | 5906 | rc = hpsa_pci_init(h); |
ecd9aad4 | 5907 | if (rc != 0) |
edd16368 SC |
5908 | goto clean1; |
5909 | ||
f79cfec6 | 5910 | sprintf(h->devname, HPSA "%d", number_of_controllers); |
edd16368 SC |
5911 | h->ctlr = number_of_controllers; |
5912 | number_of_controllers++; | |
edd16368 SC |
5913 | |
5914 | /* configure PCI DMA stuff */ | |
ecd9aad4 SC |
5915 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
5916 | if (rc == 0) { | |
edd16368 | 5917 | dac = 1; |
ecd9aad4 SC |
5918 | } else { |
5919 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
5920 | if (rc == 0) { | |
5921 | dac = 0; | |
5922 | } else { | |
5923 | dev_err(&pdev->dev, "no suitable DMA available\n"); | |
5924 | goto clean1; | |
5925 | } | |
edd16368 SC |
5926 | } |
5927 | ||
5928 | /* make sure the board interrupts are off */ | |
5929 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
10f66018 | 5930 | |
0ae01a32 | 5931 | if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx)) |
edd16368 | 5932 | goto clean2; |
303932fd DB |
5933 | dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n", |
5934 | h->devname, pdev->device, | |
a9a3a273 | 5935 | h->intr[h->intr_mode], dac ? "" : " not"); |
2e9d1b36 | 5936 | if (hpsa_allocate_cmd_pool(h)) |
edd16368 | 5937 | goto clean4; |
33a2ffce SC |
5938 | if (hpsa_allocate_sg_chain_blocks(h)) |
5939 | goto clean4; | |
a08a8471 SC |
5940 | init_waitqueue_head(&h->scan_wait_queue); |
5941 | h->scan_finished = 1; /* no scan currently in progress */ | |
edd16368 SC |
5942 | |
5943 | pci_set_drvdata(pdev, h); | |
9a41338e SC |
5944 | h->ndevices = 0; |
5945 | h->scsi_host = NULL; | |
5946 | spin_lock_init(&h->devlock); | |
64670ac8 SC |
5947 | hpsa_put_ctlr_into_performant_mode(h); |
5948 | ||
5949 | /* At this point, the controller is ready to take commands. | |
5950 | * Now, if reset_devices and the hard reset didn't work, try | |
5951 | * the soft reset and see if that works. | |
5952 | */ | |
5953 | if (try_soft_reset) { | |
5954 | ||
5955 | /* This is kind of gross. We may or may not get a completion | |
5956 | * from the soft reset command, and if we do, then the value | |
5957 | * from the fifo may or may not be valid. So, we wait 10 secs | |
5958 | * after the reset throwing away any completions we get during | |
5959 | * that time. Unregister the interrupt handler and register | |
5960 | * fake ones to scoop up any residual completions. | |
5961 | */ | |
5962 | spin_lock_irqsave(&h->lock, flags); | |
5963 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
5964 | spin_unlock_irqrestore(&h->lock, flags); | |
254f796b | 5965 | free_irqs(h); |
64670ac8 SC |
5966 | rc = hpsa_request_irq(h, hpsa_msix_discard_completions, |
5967 | hpsa_intx_discard_completions); | |
5968 | if (rc) { | |
5969 | dev_warn(&h->pdev->dev, "Failed to request_irq after " | |
5970 | "soft reset.\n"); | |
5971 | goto clean4; | |
5972 | } | |
5973 | ||
5974 | rc = hpsa_kdump_soft_reset(h); | |
5975 | if (rc) | |
5976 | /* Neither hard nor soft reset worked, we're hosed. */ | |
5977 | goto clean4; | |
5978 | ||
5979 | dev_info(&h->pdev->dev, "Board READY.\n"); | |
5980 | dev_info(&h->pdev->dev, | |
5981 | "Waiting for stale completions to drain.\n"); | |
5982 | h->access.set_intr_mask(h, HPSA_INTR_ON); | |
5983 | msleep(10000); | |
5984 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
5985 | ||
5986 | rc = controller_reset_failed(h->cfgtable); | |
5987 | if (rc) | |
5988 | dev_info(&h->pdev->dev, | |
5989 | "Soft reset appears to have failed.\n"); | |
5990 | ||
5991 | /* since the controller's reset, we have to go back and re-init | |
5992 | * everything. Easiest to just forget what we've done and do it | |
5993 | * all over again. | |
5994 | */ | |
5995 | hpsa_undo_allocations_after_kdump_soft_reset(h); | |
5996 | try_soft_reset = 0; | |
5997 | if (rc) | |
5998 | /* don't go to clean4, we already unallocated */ | |
5999 | return -ENODEV; | |
6000 | ||
6001 | goto reinit_after_soft_reset; | |
6002 | } | |
edd16368 SC |
6003 | |
6004 | /* Turn the interrupts on so we can service requests */ | |
6005 | h->access.set_intr_mask(h, HPSA_INTR_ON); | |
6006 | ||
339b2b14 | 6007 | hpsa_hba_inquiry(h); |
edd16368 | 6008 | hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */ |
8a98db73 SC |
6009 | |
6010 | /* Monitor the controller for firmware lockups */ | |
6011 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; | |
6012 | INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker); | |
6013 | schedule_delayed_work(&h->monitor_ctlr_work, | |
6014 | h->heartbeat_sample_interval); | |
88bf6d62 | 6015 | return 0; |
edd16368 SC |
6016 | |
6017 | clean4: | |
33a2ffce | 6018 | hpsa_free_sg_chain_blocks(h); |
2e9d1b36 | 6019 | hpsa_free_cmd_pool(h); |
254f796b | 6020 | free_irqs(h); |
edd16368 SC |
6021 | clean2: |
6022 | clean1: | |
edd16368 | 6023 | kfree(h); |
ecd9aad4 | 6024 | return rc; |
edd16368 SC |
6025 | } |
6026 | ||
6027 | static void hpsa_flush_cache(struct ctlr_info *h) | |
6028 | { | |
6029 | char *flush_buf; | |
6030 | struct CommandList *c; | |
702890e3 SC |
6031 | unsigned long flags; |
6032 | ||
6033 | /* Don't bother trying to flush the cache if locked up */ | |
6034 | spin_lock_irqsave(&h->lock, flags); | |
6035 | if (unlikely(h->lockup_detected)) { | |
6036 | spin_unlock_irqrestore(&h->lock, flags); | |
6037 | return; | |
6038 | } | |
6039 | spin_unlock_irqrestore(&h->lock, flags); | |
edd16368 SC |
6040 | |
6041 | flush_buf = kzalloc(4, GFP_KERNEL); | |
6042 | if (!flush_buf) | |
6043 | return; | |
6044 | ||
6045 | c = cmd_special_alloc(h); | |
6046 | if (!c) { | |
6047 | dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n"); | |
6048 | goto out_of_memory; | |
6049 | } | |
a2dac136 SC |
6050 | if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0, |
6051 | RAID_CTLR_LUNID, TYPE_CMD)) { | |
6052 | goto out; | |
6053 | } | |
edd16368 SC |
6054 | hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE); |
6055 | if (c->err_info->CommandStatus != 0) | |
a2dac136 | 6056 | out: |
edd16368 SC |
6057 | dev_warn(&h->pdev->dev, |
6058 | "error flushing cache on controller\n"); | |
6059 | cmd_special_free(h, c); | |
6060 | out_of_memory: | |
6061 | kfree(flush_buf); | |
6062 | } | |
6063 | ||
6064 | static void hpsa_shutdown(struct pci_dev *pdev) | |
6065 | { | |
6066 | struct ctlr_info *h; | |
6067 | ||
6068 | h = pci_get_drvdata(pdev); | |
6069 | /* Turn board interrupts off and send the flush cache command | |
6070 | * sendcmd will turn off interrupt, and send the flush... | |
6071 | * To write all data in the battery backed cache to disks | |
6072 | */ | |
6073 | hpsa_flush_cache(h); | |
6074 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
0097f0f4 | 6075 | hpsa_free_irqs_and_disable_msix(h); |
edd16368 SC |
6076 | } |
6077 | ||
6f039790 | 6078 | static void hpsa_free_device_info(struct ctlr_info *h) |
55e14e76 SC |
6079 | { |
6080 | int i; | |
6081 | ||
6082 | for (i = 0; i < h->ndevices; i++) | |
6083 | kfree(h->dev[i]); | |
6084 | } | |
6085 | ||
6f039790 | 6086 | static void hpsa_remove_one(struct pci_dev *pdev) |
edd16368 SC |
6087 | { |
6088 | struct ctlr_info *h; | |
8a98db73 | 6089 | unsigned long flags; |
edd16368 SC |
6090 | |
6091 | if (pci_get_drvdata(pdev) == NULL) { | |
a0c12413 | 6092 | dev_err(&pdev->dev, "unable to remove device\n"); |
edd16368 SC |
6093 | return; |
6094 | } | |
6095 | h = pci_get_drvdata(pdev); | |
8a98db73 SC |
6096 | |
6097 | /* Get rid of any controller monitoring work items */ | |
6098 | spin_lock_irqsave(&h->lock, flags); | |
6099 | h->remove_in_progress = 1; | |
6100 | cancel_delayed_work(&h->monitor_ctlr_work); | |
6101 | spin_unlock_irqrestore(&h->lock, flags); | |
6102 | ||
edd16368 SC |
6103 | hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */ |
6104 | hpsa_shutdown(pdev); | |
6105 | iounmap(h->vaddr); | |
204892e9 SC |
6106 | iounmap(h->transtable); |
6107 | iounmap(h->cfgtable); | |
55e14e76 | 6108 | hpsa_free_device_info(h); |
33a2ffce | 6109 | hpsa_free_sg_chain_blocks(h); |
edd16368 SC |
6110 | pci_free_consistent(h->pdev, |
6111 | h->nr_cmds * sizeof(struct CommandList), | |
6112 | h->cmd_pool, h->cmd_pool_dhandle); | |
6113 | pci_free_consistent(h->pdev, | |
6114 | h->nr_cmds * sizeof(struct ErrorInfo), | |
6115 | h->errinfo_pool, h->errinfo_pool_dhandle); | |
303932fd DB |
6116 | pci_free_consistent(h->pdev, h->reply_pool_size, |
6117 | h->reply_pool, h->reply_pool_dhandle); | |
edd16368 | 6118 | kfree(h->cmd_pool_bits); |
303932fd | 6119 | kfree(h->blockFetchTable); |
e1f7de0c | 6120 | kfree(h->ioaccel1_blockFetchTable); |
aca9012a | 6121 | kfree(h->ioaccel2_blockFetchTable); |
339b2b14 | 6122 | kfree(h->hba_inquiry_data); |
f0bd0b68 | 6123 | pci_disable_device(pdev); |
edd16368 | 6124 | pci_release_regions(pdev); |
edd16368 SC |
6125 | kfree(h); |
6126 | } | |
6127 | ||
6128 | static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev, | |
6129 | __attribute__((unused)) pm_message_t state) | |
6130 | { | |
6131 | return -ENOSYS; | |
6132 | } | |
6133 | ||
6134 | static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev) | |
6135 | { | |
6136 | return -ENOSYS; | |
6137 | } | |
6138 | ||
6139 | static struct pci_driver hpsa_pci_driver = { | |
f79cfec6 | 6140 | .name = HPSA, |
edd16368 | 6141 | .probe = hpsa_init_one, |
6f039790 | 6142 | .remove = hpsa_remove_one, |
edd16368 SC |
6143 | .id_table = hpsa_pci_device_id, /* id_table */ |
6144 | .shutdown = hpsa_shutdown, | |
6145 | .suspend = hpsa_suspend, | |
6146 | .resume = hpsa_resume, | |
6147 | }; | |
6148 | ||
303932fd DB |
6149 | /* Fill in bucket_map[], given nsgs (the max number of |
6150 | * scatter gather elements supported) and bucket[], | |
6151 | * which is an array of 8 integers. The bucket[] array | |
6152 | * contains 8 different DMA transfer sizes (in 16 | |
6153 | * byte increments) which the controller uses to fetch | |
6154 | * commands. This function fills in bucket_map[], which | |
6155 | * maps a given number of scatter gather elements to one of | |
6156 | * the 8 DMA transfer sizes. The point of it is to allow the | |
6157 | * controller to only do as much DMA as needed to fetch the | |
6158 | * command, with the DMA transfer size encoded in the lower | |
6159 | * bits of the command address. | |
6160 | */ | |
6161 | static void calc_bucket_map(int bucket[], int num_buckets, | |
e1f7de0c | 6162 | int nsgs, int min_blocks, int *bucket_map) |
303932fd DB |
6163 | { |
6164 | int i, j, b, size; | |
6165 | ||
303932fd DB |
6166 | /* Note, bucket_map must have nsgs+1 entries. */ |
6167 | for (i = 0; i <= nsgs; i++) { | |
6168 | /* Compute size of a command with i SG entries */ | |
e1f7de0c | 6169 | size = i + min_blocks; |
303932fd DB |
6170 | b = num_buckets; /* Assume the biggest bucket */ |
6171 | /* Find the bucket that is just big enough */ | |
e1f7de0c | 6172 | for (j = 0; j < num_buckets; j++) { |
303932fd DB |
6173 | if (bucket[j] >= size) { |
6174 | b = j; | |
6175 | break; | |
6176 | } | |
6177 | } | |
6178 | /* for a command with i SG entries, use bucket b. */ | |
6179 | bucket_map[i] = b; | |
6180 | } | |
6181 | } | |
6182 | ||
e1f7de0c | 6183 | static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support) |
303932fd | 6184 | { |
6c311b57 SC |
6185 | int i; |
6186 | unsigned long register_value; | |
e1f7de0c MG |
6187 | unsigned long transMethod = CFGTBL_Trans_Performant | |
6188 | (trans_support & CFGTBL_Trans_use_short_tags) | | |
b9af4937 SC |
6189 | CFGTBL_Trans_enable_directed_msix | |
6190 | (trans_support & (CFGTBL_Trans_io_accel1 | | |
6191 | CFGTBL_Trans_io_accel2)); | |
e1f7de0c | 6192 | struct access_method access = SA5_performant_access; |
def342bd SC |
6193 | |
6194 | /* This is a bit complicated. There are 8 registers on | |
6195 | * the controller which we write to to tell it 8 different | |
6196 | * sizes of commands which there may be. It's a way of | |
6197 | * reducing the DMA done to fetch each command. Encoded into | |
6198 | * each command's tag are 3 bits which communicate to the controller | |
6199 | * which of the eight sizes that command fits within. The size of | |
6200 | * each command depends on how many scatter gather entries there are. | |
6201 | * Each SG entry requires 16 bytes. The eight registers are programmed | |
6202 | * with the number of 16-byte blocks a command of that size requires. | |
6203 | * The smallest command possible requires 5 such 16 byte blocks. | |
d66ae08b | 6204 | * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte |
def342bd SC |
6205 | * blocks. Note, this only extends to the SG entries contained |
6206 | * within the command block, and does not extend to chained blocks | |
6207 | * of SG elements. bft[] contains the eight values we write to | |
6208 | * the registers. They are not evenly distributed, but have more | |
6209 | * sizes for small commands, and fewer sizes for larger commands. | |
6210 | */ | |
d66ae08b | 6211 | int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4}; |
b9af4937 SC |
6212 | #define MIN_IOACCEL2_BFT_ENTRY 5 |
6213 | #define HPSA_IOACCEL2_HEADER_SZ 4 | |
6214 | int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12, | |
6215 | 13, 14, 15, 16, 17, 18, 19, | |
6216 | HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES}; | |
6217 | BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16); | |
6218 | BUILD_BUG_ON(ARRAY_SIZE(bft) != 8); | |
6219 | BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) > | |
6220 | 16 * MIN_IOACCEL2_BFT_ENTRY); | |
6221 | BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16); | |
d66ae08b | 6222 | BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4); |
303932fd DB |
6223 | /* 5 = 1 s/g entry or 4k |
6224 | * 6 = 2 s/g entry or 8k | |
6225 | * 8 = 4 s/g entry or 16k | |
6226 | * 10 = 6 s/g entry or 24k | |
6227 | */ | |
303932fd | 6228 | |
303932fd DB |
6229 | /* Controller spec: zero out this buffer. */ |
6230 | memset(h->reply_pool, 0, h->reply_pool_size); | |
303932fd | 6231 | |
d66ae08b SC |
6232 | bft[7] = SG_ENTRIES_IN_CMD + 4; |
6233 | calc_bucket_map(bft, ARRAY_SIZE(bft), | |
e1f7de0c | 6234 | SG_ENTRIES_IN_CMD, 4, h->blockFetchTable); |
303932fd DB |
6235 | for (i = 0; i < 8; i++) |
6236 | writel(bft[i], &h->transtable->BlockFetch[i]); | |
6237 | ||
6238 | /* size of controller ring buffer */ | |
6239 | writel(h->max_commands, &h->transtable->RepQSize); | |
254f796b | 6240 | writel(h->nreply_queues, &h->transtable->RepQCount); |
303932fd DB |
6241 | writel(0, &h->transtable->RepQCtrAddrLow32); |
6242 | writel(0, &h->transtable->RepQCtrAddrHigh32); | |
254f796b MG |
6243 | |
6244 | for (i = 0; i < h->nreply_queues; i++) { | |
6245 | writel(0, &h->transtable->RepQAddr[i].upper); | |
6246 | writel(h->reply_pool_dhandle + | |
6247 | (h->max_commands * sizeof(u64) * i), | |
6248 | &h->transtable->RepQAddr[i].lower); | |
6249 | } | |
6250 | ||
b9af4937 | 6251 | writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); |
e1f7de0c MG |
6252 | writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest)); |
6253 | /* | |
6254 | * enable outbound interrupt coalescing in accelerator mode; | |
6255 | */ | |
6256 | if (trans_support & CFGTBL_Trans_io_accel1) { | |
6257 | access = SA5_ioaccel_mode1_access; | |
6258 | writel(10, &h->cfgtable->HostWrite.CoalIntDelay); | |
6259 | writel(4, &h->cfgtable->HostWrite.CoalIntCount); | |
c349775e ST |
6260 | } else { |
6261 | if (trans_support & CFGTBL_Trans_io_accel2) { | |
6262 | access = SA5_ioaccel_mode2_access; | |
6263 | writel(10, &h->cfgtable->HostWrite.CoalIntDelay); | |
6264 | writel(4, &h->cfgtable->HostWrite.CoalIntCount); | |
6265 | } | |
e1f7de0c | 6266 | } |
303932fd | 6267 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
3f4336f3 | 6268 | hpsa_wait_for_mode_change_ack(h); |
303932fd DB |
6269 | register_value = readl(&(h->cfgtable->TransportActive)); |
6270 | if (!(register_value & CFGTBL_Trans_Performant)) { | |
6271 | dev_warn(&h->pdev->dev, "unable to get board into" | |
6272 | " performant mode\n"); | |
6273 | return; | |
6274 | } | |
960a30e7 | 6275 | /* Change the access methods to the performant access methods */ |
e1f7de0c MG |
6276 | h->access = access; |
6277 | h->transMethod = transMethod; | |
6278 | ||
b9af4937 SC |
6279 | if (!((trans_support & CFGTBL_Trans_io_accel1) || |
6280 | (trans_support & CFGTBL_Trans_io_accel2))) | |
e1f7de0c MG |
6281 | return; |
6282 | ||
b9af4937 SC |
6283 | if (trans_support & CFGTBL_Trans_io_accel1) { |
6284 | /* Set up I/O accelerator mode */ | |
6285 | for (i = 0; i < h->nreply_queues; i++) { | |
6286 | writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX); | |
6287 | h->reply_queue[i].current_entry = | |
6288 | readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX); | |
6289 | } | |
6290 | bft[7] = h->ioaccel_maxsg + 8; | |
6291 | calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8, | |
6292 | h->ioaccel1_blockFetchTable); | |
e1f7de0c | 6293 | |
b9af4937 SC |
6294 | /* initialize all reply queue entries to unused */ |
6295 | memset(h->reply_pool, (u8) IOACCEL_MODE1_REPLY_UNUSED, | |
6296 | h->reply_pool_size); | |
e1f7de0c | 6297 | |
b9af4937 SC |
6298 | /* set all the constant fields in the accelerator command |
6299 | * frames once at init time to save CPU cycles later. | |
6300 | */ | |
6301 | for (i = 0; i < h->nr_cmds; i++) { | |
6302 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i]; | |
6303 | ||
6304 | cp->function = IOACCEL1_FUNCTION_SCSIIO; | |
6305 | cp->err_info = (u32) (h->errinfo_pool_dhandle + | |
6306 | (i * sizeof(struct ErrorInfo))); | |
6307 | cp->err_info_len = sizeof(struct ErrorInfo); | |
6308 | cp->sgl_offset = IOACCEL1_SGLOFFSET; | |
6309 | cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT; | |
6310 | cp->timeout_sec = 0; | |
6311 | cp->ReplyQueue = 0; | |
6312 | cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) | | |
6313 | DIRECT_LOOKUP_BIT; | |
6314 | cp->Tag.upper = 0; | |
6315 | cp->host_addr.lower = | |
6316 | (u32) (h->ioaccel_cmd_pool_dhandle + | |
6317 | (i * sizeof(struct io_accel1_cmd))); | |
6318 | cp->host_addr.upper = 0; | |
6319 | } | |
6320 | } else if (trans_support & CFGTBL_Trans_io_accel2) { | |
6321 | u64 cfg_offset, cfg_base_addr_index; | |
6322 | u32 bft2_offset, cfg_base_addr; | |
6323 | int rc; | |
6324 | ||
6325 | rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, | |
6326 | &cfg_base_addr_index, &cfg_offset); | |
6327 | BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64); | |
6328 | bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ; | |
6329 | calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg, | |
6330 | 4, h->ioaccel2_blockFetchTable); | |
6331 | bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset); | |
6332 | BUILD_BUG_ON(offsetof(struct CfgTable, | |
6333 | io_accel_request_size_offset) != 0xb8); | |
6334 | h->ioaccel2_bft2_regs = | |
6335 | remap_pci_mem(pci_resource_start(h->pdev, | |
6336 | cfg_base_addr_index) + | |
6337 | cfg_offset + bft2_offset, | |
6338 | ARRAY_SIZE(bft2) * | |
6339 | sizeof(*h->ioaccel2_bft2_regs)); | |
6340 | for (i = 0; i < ARRAY_SIZE(bft2); i++) | |
6341 | writel(bft2[i], &h->ioaccel2_bft2_regs[i]); | |
e1f7de0c | 6342 | } |
b9af4937 SC |
6343 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
6344 | hpsa_wait_for_mode_change_ack(h); | |
e1f7de0c MG |
6345 | } |
6346 | ||
6347 | static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h) | |
6348 | { | |
283b4a9b SC |
6349 | h->ioaccel_maxsg = |
6350 | readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); | |
6351 | if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES) | |
6352 | h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES; | |
6353 | ||
e1f7de0c MG |
6354 | /* Command structures must be aligned on a 128-byte boundary |
6355 | * because the 7 lower bits of the address are used by the | |
6356 | * hardware. | |
6357 | */ | |
6358 | #define IOACCEL1_COMMANDLIST_ALIGNMENT 128 | |
6359 | BUILD_BUG_ON(sizeof(struct io_accel1_cmd) % | |
6360 | IOACCEL1_COMMANDLIST_ALIGNMENT); | |
6361 | h->ioaccel_cmd_pool = | |
6362 | pci_alloc_consistent(h->pdev, | |
6363 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), | |
6364 | &(h->ioaccel_cmd_pool_dhandle)); | |
6365 | ||
6366 | h->ioaccel1_blockFetchTable = | |
283b4a9b | 6367 | kmalloc(((h->ioaccel_maxsg + 1) * |
e1f7de0c MG |
6368 | sizeof(u32)), GFP_KERNEL); |
6369 | ||
6370 | if ((h->ioaccel_cmd_pool == NULL) || | |
6371 | (h->ioaccel1_blockFetchTable == NULL)) | |
6372 | goto clean_up; | |
6373 | ||
6374 | memset(h->ioaccel_cmd_pool, 0, | |
6375 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool)); | |
6376 | return 0; | |
6377 | ||
6378 | clean_up: | |
6379 | if (h->ioaccel_cmd_pool) | |
6380 | pci_free_consistent(h->pdev, | |
6381 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), | |
6382 | h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle); | |
6383 | kfree(h->ioaccel1_blockFetchTable); | |
6384 | return 1; | |
6c311b57 SC |
6385 | } |
6386 | ||
aca9012a SC |
6387 | static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h) |
6388 | { | |
6389 | /* Allocate ioaccel2 mode command blocks and block fetch table */ | |
6390 | ||
6391 | h->ioaccel_maxsg = | |
6392 | readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); | |
6393 | if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES) | |
6394 | h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES; | |
6395 | ||
6396 | #define IOACCEL2_COMMANDLIST_ALIGNMENT 128 | |
6397 | BUILD_BUG_ON(sizeof(struct io_accel2_cmd) % | |
6398 | IOACCEL2_COMMANDLIST_ALIGNMENT); | |
6399 | h->ioaccel2_cmd_pool = | |
6400 | pci_alloc_consistent(h->pdev, | |
6401 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), | |
6402 | &(h->ioaccel2_cmd_pool_dhandle)); | |
6403 | ||
6404 | h->ioaccel2_blockFetchTable = | |
6405 | kmalloc(((h->ioaccel_maxsg + 1) * | |
6406 | sizeof(u32)), GFP_KERNEL); | |
6407 | ||
6408 | if ((h->ioaccel2_cmd_pool == NULL) || | |
6409 | (h->ioaccel2_blockFetchTable == NULL)) | |
6410 | goto clean_up; | |
6411 | ||
6412 | memset(h->ioaccel2_cmd_pool, 0, | |
6413 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool)); | |
6414 | return 0; | |
6415 | ||
6416 | clean_up: | |
6417 | if (h->ioaccel2_cmd_pool) | |
6418 | pci_free_consistent(h->pdev, | |
6419 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), | |
6420 | h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle); | |
6421 | kfree(h->ioaccel2_blockFetchTable); | |
6422 | return 1; | |
6423 | } | |
6424 | ||
6f039790 | 6425 | static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h) |
6c311b57 SC |
6426 | { |
6427 | u32 trans_support; | |
e1f7de0c MG |
6428 | unsigned long transMethod = CFGTBL_Trans_Performant | |
6429 | CFGTBL_Trans_use_short_tags; | |
254f796b | 6430 | int i; |
6c311b57 | 6431 | |
02ec19c8 SC |
6432 | if (hpsa_simple_mode) |
6433 | return; | |
6434 | ||
e1f7de0c MG |
6435 | /* Check for I/O accelerator mode support */ |
6436 | if (trans_support & CFGTBL_Trans_io_accel1) { | |
6437 | transMethod |= CFGTBL_Trans_io_accel1 | | |
6438 | CFGTBL_Trans_enable_directed_msix; | |
6439 | if (hpsa_alloc_ioaccel_cmd_and_bft(h)) | |
6440 | goto clean_up; | |
aca9012a SC |
6441 | } else { |
6442 | if (trans_support & CFGTBL_Trans_io_accel2) { | |
6443 | transMethod |= CFGTBL_Trans_io_accel2 | | |
6444 | CFGTBL_Trans_enable_directed_msix; | |
6445 | if (ioaccel2_alloc_cmds_and_bft(h)) | |
6446 | goto clean_up; | |
6447 | } | |
e1f7de0c MG |
6448 | } |
6449 | ||
6450 | /* TODO, check that this next line h->nreply_queues is correct */ | |
6c311b57 SC |
6451 | trans_support = readl(&(h->cfgtable->TransportSupport)); |
6452 | if (!(trans_support & PERFORMANT_MODE)) | |
6453 | return; | |
6454 | ||
eee0f03a | 6455 | h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1; |
cba3d38b | 6456 | hpsa_get_max_perf_mode_cmds(h); |
6c311b57 | 6457 | /* Performant mode ring buffer and supporting data structures */ |
254f796b | 6458 | h->reply_pool_size = h->max_commands * sizeof(u64) * h->nreply_queues; |
6c311b57 SC |
6459 | h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size, |
6460 | &(h->reply_pool_dhandle)); | |
6461 | ||
254f796b MG |
6462 | for (i = 0; i < h->nreply_queues; i++) { |
6463 | h->reply_queue[i].head = &h->reply_pool[h->max_commands * i]; | |
6464 | h->reply_queue[i].size = h->max_commands; | |
6465 | h->reply_queue[i].wraparound = 1; /* spec: init to 1 */ | |
6466 | h->reply_queue[i].current_entry = 0; | |
6467 | } | |
6468 | ||
6c311b57 | 6469 | /* Need a block fetch table for performant mode */ |
d66ae08b | 6470 | h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) * |
6c311b57 SC |
6471 | sizeof(u32)), GFP_KERNEL); |
6472 | ||
6473 | if ((h->reply_pool == NULL) | |
6474 | || (h->blockFetchTable == NULL)) | |
6475 | goto clean_up; | |
6476 | ||
e1f7de0c | 6477 | hpsa_enter_performant_mode(h, trans_support); |
303932fd DB |
6478 | return; |
6479 | ||
6480 | clean_up: | |
6481 | if (h->reply_pool) | |
6482 | pci_free_consistent(h->pdev, h->reply_pool_size, | |
6483 | h->reply_pool, h->reply_pool_dhandle); | |
6484 | kfree(h->blockFetchTable); | |
6485 | } | |
6486 | ||
76438d08 SC |
6487 | static void hpsa_drain_commands(struct ctlr_info *h) |
6488 | { | |
6489 | int cmds_out; | |
6490 | unsigned long flags; | |
6491 | ||
6492 | do { /* wait for all outstanding commands to drain out */ | |
6493 | spin_lock_irqsave(&h->lock, flags); | |
6494 | cmds_out = h->commands_outstanding; | |
6495 | spin_unlock_irqrestore(&h->lock, flags); | |
6496 | if (cmds_out <= 0) | |
6497 | break; | |
6498 | msleep(100); | |
6499 | } while (1); | |
6500 | } | |
6501 | ||
edd16368 SC |
6502 | /* |
6503 | * This is it. Register the PCI driver information for the cards we control | |
6504 | * the OS will call our registered routines when it finds one of our cards. | |
6505 | */ | |
6506 | static int __init hpsa_init(void) | |
6507 | { | |
31468401 | 6508 | return pci_register_driver(&hpsa_pci_driver); |
edd16368 SC |
6509 | } |
6510 | ||
6511 | static void __exit hpsa_cleanup(void) | |
6512 | { | |
6513 | pci_unregister_driver(&hpsa_pci_driver); | |
edd16368 SC |
6514 | } |
6515 | ||
e1f7de0c MG |
6516 | static void __attribute__((unused)) verify_offsets(void) |
6517 | { | |
b66cc250 MM |
6518 | #define VERIFY_OFFSET(member, offset) \ |
6519 | BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset) | |
6520 | ||
6521 | VERIFY_OFFSET(IU_type, 0); | |
6522 | VERIFY_OFFSET(direction, 1); | |
6523 | VERIFY_OFFSET(reply_queue, 2); | |
6524 | /* VERIFY_OFFSET(reserved1, 3); */ | |
6525 | VERIFY_OFFSET(scsi_nexus, 4); | |
6526 | VERIFY_OFFSET(Tag, 8); | |
6527 | VERIFY_OFFSET(cdb, 16); | |
6528 | VERIFY_OFFSET(cciss_lun, 32); | |
6529 | VERIFY_OFFSET(data_len, 40); | |
6530 | VERIFY_OFFSET(cmd_priority_task_attr, 44); | |
6531 | VERIFY_OFFSET(sg_count, 45); | |
6532 | /* VERIFY_OFFSET(reserved3 */ | |
6533 | VERIFY_OFFSET(err_ptr, 48); | |
6534 | VERIFY_OFFSET(err_len, 56); | |
6535 | /* VERIFY_OFFSET(reserved4 */ | |
6536 | VERIFY_OFFSET(sg, 64); | |
6537 | ||
6538 | #undef VERIFY_OFFSET | |
6539 | ||
e1f7de0c MG |
6540 | #define VERIFY_OFFSET(member, offset) \ |
6541 | BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset) | |
6542 | ||
6543 | VERIFY_OFFSET(dev_handle, 0x00); | |
6544 | VERIFY_OFFSET(reserved1, 0x02); | |
6545 | VERIFY_OFFSET(function, 0x03); | |
6546 | VERIFY_OFFSET(reserved2, 0x04); | |
6547 | VERIFY_OFFSET(err_info, 0x0C); | |
6548 | VERIFY_OFFSET(reserved3, 0x10); | |
6549 | VERIFY_OFFSET(err_info_len, 0x12); | |
6550 | VERIFY_OFFSET(reserved4, 0x13); | |
6551 | VERIFY_OFFSET(sgl_offset, 0x14); | |
6552 | VERIFY_OFFSET(reserved5, 0x15); | |
6553 | VERIFY_OFFSET(transfer_len, 0x1C); | |
6554 | VERIFY_OFFSET(reserved6, 0x20); | |
6555 | VERIFY_OFFSET(io_flags, 0x24); | |
6556 | VERIFY_OFFSET(reserved7, 0x26); | |
6557 | VERIFY_OFFSET(LUN, 0x34); | |
6558 | VERIFY_OFFSET(control, 0x3C); | |
6559 | VERIFY_OFFSET(CDB, 0x40); | |
6560 | VERIFY_OFFSET(reserved8, 0x50); | |
6561 | VERIFY_OFFSET(host_context_flags, 0x60); | |
6562 | VERIFY_OFFSET(timeout_sec, 0x62); | |
6563 | VERIFY_OFFSET(ReplyQueue, 0x64); | |
6564 | VERIFY_OFFSET(reserved9, 0x65); | |
6565 | VERIFY_OFFSET(Tag, 0x68); | |
6566 | VERIFY_OFFSET(host_addr, 0x70); | |
6567 | VERIFY_OFFSET(CISS_LUN, 0x78); | |
6568 | VERIFY_OFFSET(SG, 0x78 + 8); | |
6569 | #undef VERIFY_OFFSET | |
6570 | } | |
6571 | ||
edd16368 SC |
6572 | module_init(hpsa_init); |
6573 | module_exit(hpsa_cleanup); |