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hpsa: break hpsa_free_irqs_and_disable_msix into two functions
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
9437ac43 46#include <scsi/scsi_eh.h>
edd16368
SC		 47#include <linux/cciss_ioctl.h>
48#include <linux/string.h>
49#include <linux/bitmap.h>
60063497 50#include <linux/atomic.h>
a0c12413 51#include <linux/jiffies.h>
42a91641 52#include <linux/percpu-defs.h>
094963da 53#include <linux/percpu.h>
2b08b3e9 54#include <asm/unaligned.h>
283b4a9b 55#include <asm/div64.h>
edd16368
SC		 56#include "hpsa_cmd.h"
57#include "hpsa.h"
58
59/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
9a993302 60#define HPSA_DRIVER_VERSION "3.4.4-1"
edd16368 61#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 62#define HPSA "hpsa"
edd16368 63
007e7aa9
RE		 64/* How long to wait for CISS doorbell communication */
65#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
66#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
67#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
68#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 69#define MAX_IOCTL_CONFIG_WAIT 1000
70
71/*define how many times we will try a command because of bus resets */
72#define MAX_CMD_RETRIES 3
73
74/* Embedded module documentation macros - see modules.h */
75MODULE_AUTHOR("Hewlett-Packard Company");
76MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
77 HPSA_DRIVER_VERSION);
78MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
79MODULE_VERSION(HPSA_DRIVER_VERSION);
80MODULE_LICENSE("GPL");
81
82static int hpsa_allow_any;
83module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
84MODULE_PARM_DESC(hpsa_allow_any,
85 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 86static int hpsa_simple_mode;
87module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
88MODULE_PARM_DESC(hpsa_simple_mode,
89 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 90
91/* define the PCI info for the cards we can control */
92static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
131 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
132 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
8e616a5e
SC		 133 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
134 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
135 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
136 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
137 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 138 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 139 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 140 {0,}
141};
142
143MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
144
145/* board_id = Subsystem Device ID & Vendor ID
146 * product = Marketing Name for the board
147 * access = Address of the struct of function pointers
148 */
149static struct board_type products[] = {
edd16368
SC		 150 {0x3241103C, "Smart Array P212", &SA5_access},
151 {0x3243103C, "Smart Array P410", &SA5_access},
152 {0x3245103C, "Smart Array P410i", &SA5_access},
153 {0x3247103C, "Smart Array P411", &SA5_access},
154 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 155 {0x324A103C, "Smart Array P712m", &SA5_access},
156 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 157 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 158 {0x3350103C, "Smart Array P222", &SA5_access},
159 {0x3351103C, "Smart Array P420", &SA5_access},
160 {0x3352103C, "Smart Array P421", &SA5_access},
161 {0x3353103C, "Smart Array P822", &SA5_access},
162 {0x3354103C, "Smart Array P420i", &SA5_access},
163 {0x3355103C, "Smart Array P220i", &SA5_access},
164 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 165 {0x1921103C, "Smart Array P830i", &SA5_access},
166 {0x1922103C, "Smart Array P430", &SA5_access},
167 {0x1923103C, "Smart Array P431", &SA5_access},
168 {0x1924103C, "Smart Array P830", &SA5_access},
169 {0x1926103C, "Smart Array P731m", &SA5_access},
170 {0x1928103C, "Smart Array P230i", &SA5_access},
171 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 172 {0x21BD103C, "Smart Array P244br", &SA5_access},
173 {0x21BE103C, "Smart Array P741m", &SA5_access},
174 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
175 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 176 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 177 {0x21C2103C, "Smart Array P440", &SA5_access},
178 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 179 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 180 {0x21C5103C, "Smart Array P841", &SA5_access},
181 {0x21C6103C, "Smart HBA H244br", &SA5_access},
182 {0x21C7103C, "Smart HBA H240", &SA5_access},
183 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 184 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 185 {0x21CA103C, "Smart Array P246br", &SA5_access},
186 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 187 {0x21CC103C, "Smart Array", &SA5_access},
188 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 189 {0x21CE103C, "Smart HBA", &SA5_access},
8e616a5e
SC		 190 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
191 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
192 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
193 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
194 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 195 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
196};
197
198static int number_of_controllers;
199
10f66018
SC		 200static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
201static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 202static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 203
204#ifdef CONFIG_COMPAT
42a91641
DB		 205static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
206 void __user *arg);
edd16368
SC		 207#endif
208
209static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 210static struct CommandList *cmd_alloc(struct ctlr_info *h);
a2dac136 211static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 212 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 213 int cmd_type);
2c143342 214static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 215#define VPD_PAGE (1 << 8)
edd16368 216
f281233d 217static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 218static void hpsa_scan_start(struct Scsi_Host *);
219static int hpsa_scan_finished(struct Scsi_Host *sh,
220 unsigned long elapsed_time);
7c0a0229 221static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 222
223static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 224static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 225static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 226static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 227static void hpsa_slave_destroy(struct scsi_device *sdev);
228
edd16368 229static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 230static int check_for_unit_attention(struct ctlr_info *h,
231 struct CommandList *c);
232static void check_ioctl_unit_attention(struct ctlr_info *h,
233 struct CommandList *c);
303932fd
DB		 234/* performant mode helper functions */
235static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 236 int nsgs, int min_blocks, u32 *bucket_map);
6f039790 237static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 238static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 239static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
240 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
241 u64 *cfg_offset);
242static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
243 unsigned long *memory_bar);
244static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
245static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
246 int wait_for_ready);
75167d2c 247static inline void finish_cmd(struct CommandList *c);
c706a795 248static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 249#define BOARD_NOT_READY 0
250#define BOARD_READY 1
23100dd9 251static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 252static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 253static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
254 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 255 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 256static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 257static u32 lockup_detected(struct ctlr_info *h);
258static int detect_controller_lockup(struct ctlr_info *h);
edd16368 259
edd16368
SC		 260static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
261{
262 unsigned long *priv = shost_priv(sdev->host);
263 return (struct ctlr_info *) *priv;
264}
265
a23513e8
SC		 266static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
267{
268 unsigned long *priv = shost_priv(sh);
269 return (struct ctlr_info *) *priv;
270}
271
9437ac43
SC		 272/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
273static void decode_sense_data(const u8 *sense_data, int sense_data_len,
274 u8 *sense_key, u8 *asc, u8 *ascq)
275{
276 struct scsi_sense_hdr sshdr;
277 bool rc;
278
279 *sense_key = -1;
280 *asc = -1;
281 *ascq = -1;
282
283 if (sense_data_len < 1)
284 return;
285
286 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
287 if (rc) {
288 *sense_key = sshdr.sense_key;
289 *asc = sshdr.asc;
290 *ascq = sshdr.ascq;
291 }
292}
293
edd16368
SC		 294static int check_for_unit_attention(struct ctlr_info *h,
295 struct CommandList *c)
296{
9437ac43
SC		 297 u8 sense_key, asc, ascq;
298 int sense_len;
299
300 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
301 sense_len = sizeof(c->err_info->SenseInfo);
302 else
303 sense_len = c->err_info->SenseLen;
304
305 decode_sense_data(c->err_info->SenseInfo, sense_len,
306 &sense_key, &asc, &ascq);
307 if (sense_key != UNIT_ATTENTION || asc == -1)
edd16368
SC		 308 return 0;
309
9437ac43 310 switch (asc) {
edd16368 311 case STATE_CHANGED:
9437ac43
SC		 312 dev_warn(&h->pdev->dev,
313 HPSA "%d: a state change detected, command retried\n",
314 h->ctlr);
edd16368
SC		 315 break;
316 case LUN_FAILED:
7f73695a
SC		 317 dev_warn(&h->pdev->dev,
318 HPSA "%d: LUN failure detected\n", h->ctlr);
edd16368
SC		 319 break;
320 case REPORT_LUNS_CHANGED:
7f73695a
SC		 321 dev_warn(&h->pdev->dev,
322 HPSA "%d: report LUN data changed\n", h->ctlr);
edd16368 323 /*
4f4eb9f1
ST		 324 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
325 * target (array) devices.
edd16368
SC		 326 */
327 break;
328 case POWER_OR_RESET:
f79cfec6 329 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 330 "or device reset detected\n", h->ctlr);
331 break;
332 case UNIT_ATTENTION_CLEARED:
f79cfec6 333 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 334 "cleared by another initiator\n", h->ctlr);
335 break;
336 default:
f79cfec6 337 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 338 "unit attention detected\n", h->ctlr);
339 break;
340 }
341 return 1;
342}
343
852af20a
MB		 344static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
345{
346 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
347 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
348 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
349 return 0;
350 dev_warn(&h->pdev->dev, HPSA "device busy");
351 return 1;
352}
353
e985c58f
SC		 354static u32 lockup_detected(struct ctlr_info *h);
355static ssize_t host_show_lockup_detected(struct device *dev,
356 struct device_attribute *attr, char *buf)
357{
358 int ld;
359 struct ctlr_info *h;
360 struct Scsi_Host *shost = class_to_shost(dev);
361
362 h = shost_to_hba(shost);
363 ld = lockup_detected(h);
364
365 return sprintf(buf, "ld=%d\n", ld);
366}
367
da0697bd
ST		 368static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
369 struct device_attribute *attr,
370 const char *buf, size_t count)
371{
372 int status, len;
373 struct ctlr_info *h;
374 struct Scsi_Host *shost = class_to_shost(dev);
375 char tmpbuf[10];
376
377 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
378 return -EACCES;
379 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
380 strncpy(tmpbuf, buf, len);
381 tmpbuf[len] = '\0';
382 if (sscanf(tmpbuf, "%d", &status) != 1)
383 return -EINVAL;
384 h = shost_to_hba(shost);
385 h->acciopath_status = !!status;
386 dev_warn(&h->pdev->dev,
387 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
388 h->acciopath_status ? "enabled" : "disabled");
389 return count;
390}
391
2ba8bfc8
SC		 392static ssize_t host_store_raid_offload_debug(struct device *dev,
393 struct device_attribute *attr,
394 const char *buf, size_t count)
395{
396 int debug_level, len;
397 struct ctlr_info *h;
398 struct Scsi_Host *shost = class_to_shost(dev);
399 char tmpbuf[10];
400
401 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
402 return -EACCES;
403 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
404 strncpy(tmpbuf, buf, len);
405 tmpbuf[len] = '\0';
406 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
407 return -EINVAL;
408 if (debug_level < 0)
409 debug_level = 0;
410 h = shost_to_hba(shost);
411 h->raid_offload_debug = debug_level;
412 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
413 h->raid_offload_debug);
414 return count;
415}
416
edd16368
SC		 417static ssize_t host_store_rescan(struct device *dev,
418 struct device_attribute *attr,
419 const char *buf, size_t count)
420{
421 struct ctlr_info *h;
422 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 423 h = shost_to_hba(shost);
31468401 424 hpsa_scan_start(h->scsi_host);
edd16368
SC		 425 return count;
426}
427
d28ce020
SC		 428static ssize_t host_show_firmware_revision(struct device *dev,
429 struct device_attribute *attr, char *buf)
430{
431 struct ctlr_info *h;
432 struct Scsi_Host *shost = class_to_shost(dev);
433 unsigned char *fwrev;
434
435 h = shost_to_hba(shost);
436 if (!h->hba_inquiry_data)
437 return 0;
438 fwrev = &h->hba_inquiry_data[32];
439 return snprintf(buf, 20, "%c%c%c%c\n",
440 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
441}
442
94a13649
SC		 443static ssize_t host_show_commands_outstanding(struct device *dev,
444 struct device_attribute *attr, char *buf)
445{
446 struct Scsi_Host *shost = class_to_shost(dev);
447 struct ctlr_info *h = shost_to_hba(shost);
448
0cbf768e
SC		 449 return snprintf(buf, 20, "%d\n",
450 atomic_read(&h->commands_outstanding));
94a13649
SC		 451}
452
745a7a25
SC		 453static ssize_t host_show_transport_mode(struct device *dev,
454 struct device_attribute *attr, char *buf)
455{
456 struct ctlr_info *h;
457 struct Scsi_Host *shost = class_to_shost(dev);
458
459 h = shost_to_hba(shost);
460 return snprintf(buf, 20, "%s\n",
960a30e7 461 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 462 "performant" : "simple");
463}
464
da0697bd
ST		 465static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
466 struct device_attribute *attr, char *buf)
467{
468 struct ctlr_info *h;
469 struct Scsi_Host *shost = class_to_shost(dev);
470
471 h = shost_to_hba(shost);
472 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
473 (h->acciopath_status == 1) ? "enabled" : "disabled");
474}
475
46380786 476/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 477static u32 unresettable_controller[] = {
478 0x324a103C, /* Smart Array P712m */
9b5c48c2 479 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 480 0x3223103C, /* Smart Array P800 */
481 0x3234103C, /* Smart Array P400 */
482 0x3235103C, /* Smart Array P400i */
483 0x3211103C, /* Smart Array E200i */
484 0x3212103C, /* Smart Array E200 */
485 0x3213103C, /* Smart Array E200i */
486 0x3214103C, /* Smart Array E200i */
487 0x3215103C, /* Smart Array E200i */
488 0x3237103C, /* Smart Array E500 */
489 0x323D103C, /* Smart Array P700m */
7af0abbc 490 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 491 0x409C0E11, /* Smart Array 6400 */
492 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 493 0x40700E11, /* Smart Array 5300 */
494 0x40820E11, /* Smart Array 532 */
495 0x40830E11, /* Smart Array 5312 */
496 0x409A0E11, /* Smart Array 641 */
497 0x409B0E11, /* Smart Array 642 */
498 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 499};
500
46380786
SC		 501/* List of controllers which cannot even be soft reset */
502static u32 soft_unresettable_controller[] = {
7af0abbc 503 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 504 0x40700E11, /* Smart Array 5300 */
505 0x40820E11, /* Smart Array 532 */
506 0x40830E11, /* Smart Array 5312 */
507 0x409A0E11, /* Smart Array 641 */
508 0x409B0E11, /* Smart Array 642 */
509 0x40910E11, /* Smart Array 6i */
46380786
SC		 510 /* Exclude 640x boards. These are two pci devices in one slot
511 * which share a battery backed cache module. One controls the
512 * cache, the other accesses the cache through the one that controls
513 * it. If we reset the one controlling the cache, the other will
514 * likely not be happy. Just forbid resetting this conjoined mess.
515 * The 640x isn't really supported by hpsa anyway.
516 */
517 0x409C0E11, /* Smart Array 6400 */
518 0x409D0E11, /* Smart Array 6400 EM */
519};
520
9b5c48c2
SC		 521static u32 needs_abort_tags_swizzled[] = {
522 0x323D103C, /* Smart Array P700m */
523 0x324a103C, /* Smart Array P712m */
524 0x324b103C, /* SmartArray P711m */
525};
526
527static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 528{
529 int i;
530
9b5c48c2
SC		 531 for (i = 0; i < nelems; i++)
532 if (a[i] == board_id)
533 return 1;
534 return 0;
46380786
SC		 535}
536
9b5c48c2 537static int ctlr_is_hard_resettable(u32 board_id)
46380786 538{
9b5c48c2
SC		 539 return !board_id_in_array(unresettable_controller,
540 ARRAY_SIZE(unresettable_controller), board_id);
541}
46380786 542
9b5c48c2
SC		 543static int ctlr_is_soft_resettable(u32 board_id)
544{
545 return !board_id_in_array(soft_unresettable_controller,
546 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 547}
548
46380786
SC		 549static int ctlr_is_resettable(u32 board_id)
550{
551 return ctlr_is_hard_resettable(board_id) ||
552 ctlr_is_soft_resettable(board_id);
553}
554
9b5c48c2
SC		 555static int ctlr_needs_abort_tags_swizzled(u32 board_id)
556{
557 return board_id_in_array(needs_abort_tags_swizzled,
558 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
559}
560
941b1cda
SC		 561static ssize_t host_show_resettable(struct device *dev,
562 struct device_attribute *attr, char *buf)
563{
564 struct ctlr_info *h;
565 struct Scsi_Host *shost = class_to_shost(dev);
566
567 h = shost_to_hba(shost);
46380786 568 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 569}
570
edd16368
SC		 571static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
572{
573 return (scsi3addr[3] & 0xC0) == 0x40;
574}
575
f2ef0ce7
RE		 576static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
577 "1(+0)ADM", "UNKNOWN"
edd16368 578};
6b80b18f
ST		 579#define HPSA_RAID_0 0
580#define HPSA_RAID_4 1
581#define HPSA_RAID_1 2 /* also used for RAID 10 */
582#define HPSA_RAID_5 3 /* also used for RAID 50 */
583#define HPSA_RAID_51 4
584#define HPSA_RAID_6 5 /* also used for RAID 60 */
585#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 586#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
587
588static ssize_t raid_level_show(struct device *dev,
589 struct device_attribute *attr, char *buf)
590{
591 ssize_t l = 0;
82a72c0a 592 unsigned char rlevel;
edd16368
SC		 593 struct ctlr_info *h;
594 struct scsi_device *sdev;
595 struct hpsa_scsi_dev_t *hdev;
596 unsigned long flags;
597
598 sdev = to_scsi_device(dev);
599 h = sdev_to_hba(sdev);
600 spin_lock_irqsave(&h->lock, flags);
601 hdev = sdev->hostdata;
602 if (!hdev) {
603 spin_unlock_irqrestore(&h->lock, flags);
604 return -ENODEV;
605 }
606
607 /* Is this even a logical drive? */
608 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
609 spin_unlock_irqrestore(&h->lock, flags);
610 l = snprintf(buf, PAGE_SIZE, "N/A\n");
611 return l;
612 }
613
614 rlevel = hdev->raid_level;
615 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 616 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 617 rlevel = RAID_UNKNOWN;
618 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
619 return l;
620}
621
622static ssize_t lunid_show(struct device *dev,
623 struct device_attribute *attr, char *buf)
624{
625 struct ctlr_info *h;
626 struct scsi_device *sdev;
627 struct hpsa_scsi_dev_t *hdev;
628 unsigned long flags;
629 unsigned char lunid[8];
630
631 sdev = to_scsi_device(dev);
632 h = sdev_to_hba(sdev);
633 spin_lock_irqsave(&h->lock, flags);
634 hdev = sdev->hostdata;
635 if (!hdev) {
636 spin_unlock_irqrestore(&h->lock, flags);
637 return -ENODEV;
638 }
639 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
640 spin_unlock_irqrestore(&h->lock, flags);
641 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
642 lunid[0], lunid[1], lunid[2], lunid[3],
643 lunid[4], lunid[5], lunid[6], lunid[7]);
644}
645
646static ssize_t unique_id_show(struct device *dev,
647 struct device_attribute *attr, char *buf)
648{
649 struct ctlr_info *h;
650 struct scsi_device *sdev;
651 struct hpsa_scsi_dev_t *hdev;
652 unsigned long flags;
653 unsigned char sn[16];
654
655 sdev = to_scsi_device(dev);
656 h = sdev_to_hba(sdev);
657 spin_lock_irqsave(&h->lock, flags);
658 hdev = sdev->hostdata;
659 if (!hdev) {
660 spin_unlock_irqrestore(&h->lock, flags);
661 return -ENODEV;
662 }
663 memcpy(sn, hdev->device_id, sizeof(sn));
664 spin_unlock_irqrestore(&h->lock, flags);
665 return snprintf(buf, 16 * 2 + 2,
666 "%02X%02X%02X%02X%02X%02X%02X%02X"
667 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
668 sn[0], sn[1], sn[2], sn[3],
669 sn[4], sn[5], sn[6], sn[7],
670 sn[8], sn[9], sn[10], sn[11],
671 sn[12], sn[13], sn[14], sn[15]);
672}
673
c1988684
ST		 674static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
675 struct device_attribute *attr, char *buf)
676{
677 struct ctlr_info *h;
678 struct scsi_device *sdev;
679 struct hpsa_scsi_dev_t *hdev;
680 unsigned long flags;
681 int offload_enabled;
682
683 sdev = to_scsi_device(dev);
684 h = sdev_to_hba(sdev);
685 spin_lock_irqsave(&h->lock, flags);
686 hdev = sdev->hostdata;
687 if (!hdev) {
688 spin_unlock_irqrestore(&h->lock, flags);
689 return -ENODEV;
690 }
691 offload_enabled = hdev->offload_enabled;
692 spin_unlock_irqrestore(&h->lock, flags);
693 return snprintf(buf, 20, "%d\n", offload_enabled);
694}
695
3f5eac3a
SC		 696static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
697static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
698static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
699static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 700static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
701 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 702static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
703 host_show_hp_ssd_smart_path_status,
704 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 705static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
706 host_store_raid_offload_debug);
3f5eac3a
SC		 707static DEVICE_ATTR(firmware_revision, S_IRUGO,
708 host_show_firmware_revision, NULL);
709static DEVICE_ATTR(commands_outstanding, S_IRUGO,
710 host_show_commands_outstanding, NULL);
711static DEVICE_ATTR(transport_mode, S_IRUGO,
712 host_show_transport_mode, NULL);
941b1cda
SC		 713static DEVICE_ATTR(resettable, S_IRUGO,
714 host_show_resettable, NULL);
e985c58f
SC		 715static DEVICE_ATTR(lockup_detected, S_IRUGO,
716 host_show_lockup_detected, NULL);
3f5eac3a
SC		 717
718static struct device_attribute *hpsa_sdev_attrs[] = {
719 &dev_attr_raid_level,
720 &dev_attr_lunid,
721 &dev_attr_unique_id,
c1988684 722 &dev_attr_hp_ssd_smart_path_enabled,
e985c58f 723 &dev_attr_lockup_detected,
3f5eac3a
SC		 724 NULL,
725};
726
727static struct device_attribute *hpsa_shost_attrs[] = {
728 &dev_attr_rescan,
729 &dev_attr_firmware_revision,
730 &dev_attr_commands_outstanding,
731 &dev_attr_transport_mode,
941b1cda 732 &dev_attr_resettable,
da0697bd 733 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 734 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 735 NULL,
736};
737
41ce4c35
SC		 738#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
739 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
740
3f5eac3a
SC		 741static struct scsi_host_template hpsa_driver_template = {
742 .module = THIS_MODULE,
f79cfec6
SC		 743 .name = HPSA,
744 .proc_name = HPSA,
3f5eac3a
SC		 745 .queuecommand = hpsa_scsi_queue_command,
746 .scan_start = hpsa_scan_start,
747 .scan_finished = hpsa_scan_finished,
7c0a0229 748 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 749 .this_id = -1,
750 .use_clustering = ENABLE_CLUSTERING,
75167d2c 751 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 752 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
753 .ioctl = hpsa_ioctl,
754 .slave_alloc = hpsa_slave_alloc,
41ce4c35 755 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 756 .slave_destroy = hpsa_slave_destroy,
757#ifdef CONFIG_COMPAT
758 .compat_ioctl = hpsa_compat_ioctl,
759#endif
760 .sdev_attrs = hpsa_sdev_attrs,
761 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 762 .max_sectors = 8192,
54b2b50c 763 .no_write_same = 1,
3f5eac3a
SC		 764};
765
254f796b 766static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 767{
768 u32 a;
072b0518 769 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 770
e1f7de0c
MG		 771 if (h->transMethod & CFGTBL_Trans_io_accel1)
772 return h->access.command_completed(h, q);
773
3f5eac3a 774 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 775 return h->access.command_completed(h, q);
3f5eac3a 776
254f796b
MG		 777 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
778 a = rq->head[rq->current_entry];
779 rq->current_entry++;
0cbf768e 780 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 781 } else {
782 a = FIFO_EMPTY;
783 }
784 /* Check for wraparound */
254f796b
MG		 785 if (rq->current_entry == h->max_commands) {
786 rq->current_entry = 0;
787 rq->wraparound ^= 1;
3f5eac3a
SC		 788 }
789 return a;
790}
791
c349775e
ST		 792/*
793 * There are some special bits in the bus address of the
794 * command that we have to set for the controller to know
795 * how to process the command:
796 *
797 * Normal performant mode:
798 * bit 0: 1 means performant mode, 0 means simple mode.
799 * bits 1-3 = block fetch table entry
800 * bits 4-6 = command type (== 0)
801 *
802 * ioaccel1 mode:
803 * bit 0 = "performant mode" bit.
804 * bits 1-3 = block fetch table entry
805 * bits 4-6 = command type (== 110)
806 * (command type is needed because ioaccel1 mode
807 * commands are submitted through the same register as normal
808 * mode commands, so this is how the controller knows whether
809 * the command is normal mode or ioaccel1 mode.)
810 *
811 * ioaccel2 mode:
812 * bit 0 = "performant mode" bit.
813 * bits 1-4 = block fetch table entry (note extra bit)
814 * bits 4-6 = not needed, because ioaccel2 mode has
815 * a separate special register for submitting commands.
816 */
817
25163bd5
WS		 818/*
819 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 820 * set bit 0 for pull model, bits 3-1 for block fetch
821 * register number
822 */
25163bd5
WS		 823#define DEFAULT_REPLY_QUEUE (-1)
824static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
825 int reply_queue)
3f5eac3a 826{
254f796b 827 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 828 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 829 if (unlikely(!h->msix_vector))
830 return;
831 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 832 c->Header.ReplyQueue =
804a5cb5 833 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 834 else
835 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 836 }
3f5eac3a
SC		 837}
838
c349775e 839static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 840 struct CommandList *c,
841 int reply_queue)
c349775e
ST		 842{
843 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
844
25163bd5
WS		 845 /*
846 * Tell the controller to post the reply to the queue for this
c349775e
ST		 847 * processor. This seems to give the best I/O throughput.
848 */
25163bd5
WS		 849 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
850 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
851 else
852 cp->ReplyQueue = reply_queue % h->nreply_queues;
853 /*
854 * Set the bits in the address sent down to include:
c349775e
ST		 855 * - performant mode bit (bit 0)
856 * - pull count (bits 1-3)
857 * - command type (bits 4-6)
858 */
859 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
860 IOACCEL1_BUSADDR_CMDTYPE;
861}
862
863static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 864 struct CommandList *c,
865 int reply_queue)
c349775e
ST		 866{
867 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
868
25163bd5
WS		 869 /*
870 * Tell the controller to post the reply to the queue for this
c349775e
ST		 871 * processor. This seems to give the best I/O throughput.
872 */
25163bd5
WS		 873 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
874 cp->reply_queue = smp_processor_id() % h->nreply_queues;
875 else
876 cp->reply_queue = reply_queue % h->nreply_queues;
877 /*
878 * Set the bits in the address sent down to include:
c349775e
ST		 879 * - performant mode bit not used in ioaccel mode 2
880 * - pull count (bits 0-3)
881 * - command type isn't needed for ioaccel2
882 */
883 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
884}
885
e85c5974
SC		 886static int is_firmware_flash_cmd(u8 *cdb)
887{
888 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
889}
890
891/*
892 * During firmware flash, the heartbeat register may not update as frequently
893 * as it should. So we dial down lockup detection during firmware flash. and
894 * dial it back up when firmware flash completes.
895 */
896#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
897#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
898static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
899 struct CommandList *c)
900{
901 if (!is_firmware_flash_cmd(c->Request.CDB))
902 return;
903 atomic_inc(&h->firmware_flash_in_progress);
904 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
905}
906
907static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
908 struct CommandList *c)
909{
910 if (is_firmware_flash_cmd(c->Request.CDB) &&
911 atomic_dec_and_test(&h->firmware_flash_in_progress))
912 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
913}
914
25163bd5
WS		 915static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
916 struct CommandList *c, int reply_queue)
3f5eac3a 917{
c05e8866
SC		 918 dial_down_lockup_detection_during_fw_flash(h, c);
919 atomic_inc(&h->commands_outstanding);
c349775e
ST		 920 switch (c->cmd_type) {
921 case CMD_IOACCEL1:
25163bd5 922 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 923 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 924 break;
925 case CMD_IOACCEL2:
25163bd5 926 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 927 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e
ST		 928 break;
929 default:
25163bd5 930 set_performant_mode(h, c, reply_queue);
c05e8866 931 h->access.submit_command(h, c);
c349775e 932 }
3f5eac3a
SC		 933}
934
25163bd5
WS		 935static void enqueue_cmd_and_start_io(struct ctlr_info *h,
936 struct CommandList *c)
937{
938 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
939}
940
3f5eac3a
SC		 941static inline int is_hba_lunid(unsigned char scsi3addr[])
942{
943 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
944}
945
946static inline int is_scsi_rev_5(struct ctlr_info *h)
947{
948 if (!h->hba_inquiry_data)
949 return 0;
950 if ((h->hba_inquiry_data[2] & 0x07) == 5)
951 return 1;
952 return 0;
953}
954
edd16368
SC		 955static int hpsa_find_target_lun(struct ctlr_info *h,
956 unsigned char scsi3addr[], int bus, int *target, int *lun)
957{
958 /* finds an unused bus, target, lun for a new physical device
959 * assumes h->devlock is held
960 */
961 int i, found = 0;
cfe5badc 962 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 963
263d9401 964 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 965
966 for (i = 0; i < h->ndevices; i++) {
967 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 968 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 969 }
970
263d9401
AM		 971 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
972 if (i < HPSA_MAX_DEVICES) {
973 /* *bus = 1; */
974 *target = i;
975 *lun = 0;
976 found = 1;
edd16368
SC		 977 }
978 return !found;
979}
980
0d96ef5f
WS		 981static inline void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
982 struct hpsa_scsi_dev_t *dev, char *description)
983{
984 dev_printk(level, &h->pdev->dev,
985 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
986 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
987 description,
988 scsi_device_type(dev->devtype),
989 dev->vendor,
990 dev->model,
991 dev->raid_level > RAID_UNKNOWN ?
992 "RAID-?" : raid_label[dev->raid_level],
993 dev->offload_config ? '+' : '-',
994 dev->offload_enabled ? '+' : '-',
995 dev->expose_state);
996}
997
edd16368
SC		 998/* Add an entry into h->dev[] array. */
999static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
1000 struct hpsa_scsi_dev_t *device,
1001 struct hpsa_scsi_dev_t *added[], int *nadded)
1002{
1003 /* assumes h->devlock is held */
1004 int n = h->ndevices;
1005 int i;
1006 unsigned char addr1[8], addr2[8];
1007 struct hpsa_scsi_dev_t *sd;
1008
cfe5badc 1009 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1010 dev_err(&h->pdev->dev, "too many devices, some will be "
1011 "inaccessible.\n");
1012 return -1;
1013 }
1014
1015 /* physical devices do not have lun or target assigned until now. */
1016 if (device->lun != -1)
1017 /* Logical device, lun is already assigned. */
1018 goto lun_assigned;
1019
1020 /* If this device a non-zero lun of a multi-lun device
1021 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1022 * unit no, zero otherwise.
edd16368
SC		 1023 */
1024 if (device->scsi3addr[4] == 0) {
1025 /* This is not a non-zero lun of a multi-lun device */
1026 if (hpsa_find_target_lun(h, device->scsi3addr,
1027 device->bus, &device->target, &device->lun) != 0)
1028 return -1;
1029 goto lun_assigned;
1030 }
1031
1032 /* This is a non-zero lun of a multi-lun device.
1033 * Search through our list and find the device which
1034 * has the same 8 byte LUN address, excepting byte 4.
1035 * Assign the same bus and target for this new LUN.
1036 * Use the logical unit number from the firmware.
1037 */
1038 memcpy(addr1, device->scsi3addr, 8);
1039 addr1[4] = 0;
1040 for (i = 0; i < n; i++) {
1041 sd = h->dev[i];
1042 memcpy(addr2, sd->scsi3addr, 8);
1043 addr2[4] = 0;
1044 /* differ only in byte 4? */
1045 if (memcmp(addr1, addr2, 8) == 0) {
1046 device->bus = sd->bus;
1047 device->target = sd->target;
1048 device->lun = device->scsi3addr[4];
1049 break;
1050 }
1051 }
1052 if (device->lun == -1) {
1053 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1054 " suspect firmware bug or unsupported hardware "
1055 "configuration.\n");
1056 return -1;
1057 }
1058
1059lun_assigned:
1060
1061 h->dev[n] = device;
1062 h->ndevices++;
1063 added[*nadded] = device;
1064 (*nadded)++;
0d96ef5f
WS		 1065 hpsa_show_dev_msg(KERN_INFO, h, device,
1066 device->expose_state & HPSA_SCSI_ADD ? "added" : "masked");
a473d86c
RE		 1067 device->offload_to_be_enabled = device->offload_enabled;
1068 device->offload_enabled = 0;
edd16368
SC		 1069 return 0;
1070}
1071
bd9244f7
ST		 1072/* Update an entry in h->dev[] array. */
1073static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
1074 int entry, struct hpsa_scsi_dev_t *new_entry)
1075{
a473d86c 1076 int offload_enabled;
bd9244f7
ST		 1077 /* assumes h->devlock is held */
1078 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1079
1080 /* Raid level changed. */
1081 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1082
03383736
DB		 1083 /* Raid offload parameters changed. Careful about the ordering. */
1084 if (new_entry->offload_config && new_entry->offload_enabled) {
1085 /*
1086 * if drive is newly offload_enabled, we want to copy the
1087 * raid map data first. If previously offload_enabled and
1088 * offload_config were set, raid map data had better be
1089 * the same as it was before. if raid map data is changed
1090 * then it had better be the case that
1091 * h->dev[entry]->offload_enabled is currently 0.
1092 */
1093 h->dev[entry]->raid_map = new_entry->raid_map;
1094 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1095 }
a3144e0b
JH		 1096 if (new_entry->hba_ioaccel_enabled) {
1097 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1098 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1099 }
1100 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1101 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1102 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1103 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1104
41ce4c35
SC		 1105 /*
1106 * We can turn off ioaccel offload now, but need to delay turning
1107 * it on until we can update h->dev[entry]->phys_disk[], but we
1108 * can't do that until all the devices are updated.
1109 */
1110 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1111 if (!new_entry->offload_enabled)
1112 h->dev[entry]->offload_enabled = 0;
1113
a473d86c
RE		 1114 offload_enabled = h->dev[entry]->offload_enabled;
1115 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1116 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1117 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1118}
1119
2a8ccf31
SC		 1120/* Replace an entry from h->dev[] array. */
1121static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
1122 int entry, struct hpsa_scsi_dev_t *new_entry,
1123 struct hpsa_scsi_dev_t *added[], int *nadded,
1124 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1125{
1126 /* assumes h->devlock is held */
cfe5badc 1127 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1128 removed[*nremoved] = h->dev[entry];
1129 (*nremoved)++;
01350d05
SC		 1130
1131 /*
1132 * New physical devices won't have target/lun assigned yet
1133 * so we need to preserve the values in the slot we are replacing.
1134 */
1135 if (new_entry->target == -1) {
1136 new_entry->target = h->dev[entry]->target;
1137 new_entry->lun = h->dev[entry]->lun;
1138 }
1139
2a8ccf31
SC		 1140 h->dev[entry] = new_entry;
1141 added[*nadded] = new_entry;
1142 (*nadded)++;
0d96ef5f 1143 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1144 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1145 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1146}
1147
edd16368
SC		 1148/* Remove an entry from h->dev[] array. */
1149static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1150 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1151{
1152 /* assumes h->devlock is held */
1153 int i;
1154 struct hpsa_scsi_dev_t *sd;
1155
cfe5badc 1156 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1157
1158 sd = h->dev[entry];
1159 removed[*nremoved] = h->dev[entry];
1160 (*nremoved)++;
1161
1162 for (i = entry; i < h->ndevices-1; i++)
1163 h->dev[i] = h->dev[i+1];
1164 h->ndevices--;
0d96ef5f 1165 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1166}
1167
1168#define SCSI3ADDR_EQ(a, b) ( \
1169 (a)[7] == (b)[7] && \
1170 (a)[6] == (b)[6] && \
1171 (a)[5] == (b)[5] && \
1172 (a)[4] == (b)[4] && \
1173 (a)[3] == (b)[3] && \
1174 (a)[2] == (b)[2] && \
1175 (a)[1] == (b)[1] && \
1176 (a)[0] == (b)[0])
1177
1178static void fixup_botched_add(struct ctlr_info *h,
1179 struct hpsa_scsi_dev_t *added)
1180{
1181 /* called when scsi_add_device fails in order to re-adjust
1182 * h->dev[] to match the mid layer's view.
1183 */
1184 unsigned long flags;
1185 int i, j;
1186
1187 spin_lock_irqsave(&h->lock, flags);
1188 for (i = 0; i < h->ndevices; i++) {
1189 if (h->dev[i] == added) {
1190 for (j = i; j < h->ndevices-1; j++)
1191 h->dev[j] = h->dev[j+1];
1192 h->ndevices--;
1193 break;
1194 }
1195 }
1196 spin_unlock_irqrestore(&h->lock, flags);
1197 kfree(added);
1198}
1199
1200static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1201 struct hpsa_scsi_dev_t *dev2)
1202{
edd16368
SC		 1203 /* we compare everything except lun and target as these
1204 * are not yet assigned. Compare parts likely
1205 * to differ first
1206 */
1207 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1208 sizeof(dev1->scsi3addr)) != 0)
1209 return 0;
1210 if (memcmp(dev1->device_id, dev2->device_id,
1211 sizeof(dev1->device_id)) != 0)
1212 return 0;
1213 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1214 return 0;
1215 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1216 return 0;
edd16368
SC		 1217 if (dev1->devtype != dev2->devtype)
1218 return 0;
edd16368
SC		 1219 if (dev1->bus != dev2->bus)
1220 return 0;
1221 return 1;
1222}
1223
bd9244f7
ST		 1224static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1225 struct hpsa_scsi_dev_t *dev2)
1226{
1227 /* Device attributes that can change, but don't mean
1228 * that the device is a different device, nor that the OS
1229 * needs to be told anything about the change.
1230 */
1231 if (dev1->raid_level != dev2->raid_level)
1232 return 1;
250fb125
SC		 1233 if (dev1->offload_config != dev2->offload_config)
1234 return 1;
1235 if (dev1->offload_enabled != dev2->offload_enabled)
1236 return 1;
03383736
DB		 1237 if (dev1->queue_depth != dev2->queue_depth)
1238 return 1;
bd9244f7
ST		 1239 return 0;
1240}
1241
edd16368
SC		 1242/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1243 * and return needle location in *index. If scsi3addr matches, but not
1244 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1245 * location in *index.
1246 * In the case of a minor device attribute change, such as RAID level, just
1247 * return DEVICE_UPDATED, along with the updated device's location in index.
1248 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1249 */
1250static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1251 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1252 int *index)
1253{
1254 int i;
1255#define DEVICE_NOT_FOUND 0
1256#define DEVICE_CHANGED 1
1257#define DEVICE_SAME 2
bd9244f7 1258#define DEVICE_UPDATED 3
edd16368 1259 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1260 if (haystack[i] == NULL) /* previously removed. */
1261 continue;
edd16368
SC		 1262 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1263 *index = i;
bd9244f7
ST		 1264 if (device_is_the_same(needle, haystack[i])) {
1265 if (device_updated(needle, haystack[i]))
1266 return DEVICE_UPDATED;
edd16368 1267 return DEVICE_SAME;
bd9244f7 1268 } else {
9846590e
SC		 1269 /* Keep offline devices offline */
1270 if (needle->volume_offline)
1271 return DEVICE_NOT_FOUND;
edd16368 1272 return DEVICE_CHANGED;
bd9244f7 1273 }
edd16368
SC		 1274 }
1275 }
1276 *index = -1;
1277 return DEVICE_NOT_FOUND;
1278}
1279
9846590e
SC		 1280static void hpsa_monitor_offline_device(struct ctlr_info *h,
1281 unsigned char scsi3addr[])
1282{
1283 struct offline_device_entry *device;
1284 unsigned long flags;
1285
1286 /* Check to see if device is already on the list */
1287 spin_lock_irqsave(&h->offline_device_lock, flags);
1288 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1289 if (memcmp(device->scsi3addr, scsi3addr,
1290 sizeof(device->scsi3addr)) == 0) {
1291 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1292 return;
1293 }
1294 }
1295 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1296
1297 /* Device is not on the list, add it. */
1298 device = kmalloc(sizeof(*device), GFP_KERNEL);
1299 if (!device) {
1300 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1301 return;
1302 }
1303 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1304 spin_lock_irqsave(&h->offline_device_lock, flags);
1305 list_add_tail(&device->offline_list, &h->offline_device_list);
1306 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1307}
1308
1309/* Print a message explaining various offline volume states */
1310static void hpsa_show_volume_status(struct ctlr_info *h,
1311 struct hpsa_scsi_dev_t *sd)
1312{
1313 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1314 dev_info(&h->pdev->dev,
1315 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1316 h->scsi_host->host_no,
1317 sd->bus, sd->target, sd->lun);
1318 switch (sd->volume_offline) {
1319 case HPSA_LV_OK:
1320 break;
1321 case HPSA_LV_UNDERGOING_ERASE:
1322 dev_info(&h->pdev->dev,
1323 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1324 h->scsi_host->host_no,
1325 sd->bus, sd->target, sd->lun);
1326 break;
1327 case HPSA_LV_UNDERGOING_RPI:
1328 dev_info(&h->pdev->dev,
1329 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1330 h->scsi_host->host_no,
1331 sd->bus, sd->target, sd->lun);
1332 break;
1333 case HPSA_LV_PENDING_RPI:
1334 dev_info(&h->pdev->dev,
1335 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1336 h->scsi_host->host_no,
1337 sd->bus, sd->target, sd->lun);
1338 break;
1339 case HPSA_LV_ENCRYPTED_NO_KEY:
1340 dev_info(&h->pdev->dev,
1341 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1342 h->scsi_host->host_no,
1343 sd->bus, sd->target, sd->lun);
1344 break;
1345 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1346 dev_info(&h->pdev->dev,
1347 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1348 h->scsi_host->host_no,
1349 sd->bus, sd->target, sd->lun);
1350 break;
1351 case HPSA_LV_UNDERGOING_ENCRYPTION:
1352 dev_info(&h->pdev->dev,
1353 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1354 h->scsi_host->host_no,
1355 sd->bus, sd->target, sd->lun);
1356 break;
1357 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1358 dev_info(&h->pdev->dev,
1359 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1360 h->scsi_host->host_no,
1361 sd->bus, sd->target, sd->lun);
1362 break;
1363 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1364 dev_info(&h->pdev->dev,
1365 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1366 h->scsi_host->host_no,
1367 sd->bus, sd->target, sd->lun);
1368 break;
1369 case HPSA_LV_PENDING_ENCRYPTION:
1370 dev_info(&h->pdev->dev,
1371 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1372 h->scsi_host->host_no,
1373 sd->bus, sd->target, sd->lun);
1374 break;
1375 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1376 dev_info(&h->pdev->dev,
1377 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1378 h->scsi_host->host_no,
1379 sd->bus, sd->target, sd->lun);
1380 break;
1381 }
1382}
1383
03383736
DB		 1384/*
1385 * Figure the list of physical drive pointers for a logical drive with
1386 * raid offload configured.
1387 */
1388static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1389 struct hpsa_scsi_dev_t *dev[], int ndevices,
1390 struct hpsa_scsi_dev_t *logical_drive)
1391{
1392 struct raid_map_data *map = &logical_drive->raid_map;
1393 struct raid_map_disk_data *dd = &map->data[0];
1394 int i, j;
1395 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1396 le16_to_cpu(map->metadata_disks_per_row);
1397 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1398 le16_to_cpu(map->layout_map_count) *
1399 total_disks_per_row;
1400 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1401 total_disks_per_row;
1402 int qdepth;
1403
1404 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1405 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1406
1407 qdepth = 0;
1408 for (i = 0; i < nraid_map_entries; i++) {
1409 logical_drive->phys_disk[i] = NULL;
1410 if (!logical_drive->offload_config)
1411 continue;
1412 for (j = 0; j < ndevices; j++) {
1413 if (dev[j]->devtype != TYPE_DISK)
1414 continue;
1415 if (is_logical_dev_addr_mode(dev[j]->scsi3addr))
1416 continue;
1417 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1418 continue;
1419
1420 logical_drive->phys_disk[i] = dev[j];
1421 if (i < nphys_disk)
1422 qdepth = min(h->nr_cmds, qdepth +
1423 logical_drive->phys_disk[i]->queue_depth);
1424 break;
1425 }
1426
1427 /*
1428 * This can happen if a physical drive is removed and
1429 * the logical drive is degraded. In that case, the RAID
1430 * map data will refer to a physical disk which isn't actually
1431 * present. And in that case offload_enabled should already
1432 * be 0, but we'll turn it off here just in case
1433 */
1434 if (!logical_drive->phys_disk[i]) {
1435 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1436 logical_drive->offload_to_be_enabled = 0;
1437 logical_drive->queue_depth = 8;
03383736
DB		 1438 }
1439 }
1440 if (nraid_map_entries)
1441 /*
1442 * This is correct for reads, too high for full stripe writes,
1443 * way too high for partial stripe writes
1444 */
1445 logical_drive->queue_depth = qdepth;
1446 else
1447 logical_drive->queue_depth = h->nr_cmds;
1448}
1449
1450static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1451 struct hpsa_scsi_dev_t *dev[], int ndevices)
1452{
1453 int i;
1454
1455 for (i = 0; i < ndevices; i++) {
1456 if (dev[i]->devtype != TYPE_DISK)
1457 continue;
1458 if (!is_logical_dev_addr_mode(dev[i]->scsi3addr))
1459 continue;
41ce4c35
SC		 1460
1461 /*
1462 * If offload is currently enabled, the RAID map and
1463 * phys_disk[] assignment *better* not be changing
1464 * and since it isn't changing, we do not need to
1465 * update it.
1466 */
1467 if (dev[i]->offload_enabled)
1468 continue;
1469
03383736
DB		 1470 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1471 }
1472}
1473
4967bd3e 1474static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1475 struct hpsa_scsi_dev_t *sd[], int nsds)
1476{
1477 /* sd contains scsi3 addresses and devtypes, and inquiry
1478 * data. This function takes what's in sd to be the current
1479 * reality and updates h->dev[] to reflect that reality.
1480 */
1481 int i, entry, device_change, changes = 0;
1482 struct hpsa_scsi_dev_t *csd;
1483 unsigned long flags;
1484 struct hpsa_scsi_dev_t **added, **removed;
1485 int nadded, nremoved;
1486 struct Scsi_Host *sh = NULL;
1487
cfe5badc
ST		 1488 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1489 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1490
1491 if (!added || !removed) {
1492 dev_warn(&h->pdev->dev, "out of memory in "
1493 "adjust_hpsa_scsi_table\n");
1494 goto free_and_out;
1495 }
1496
1497 spin_lock_irqsave(&h->devlock, flags);
1498
1499 /* find any devices in h->dev[] that are not in
1500 * sd[] and remove them from h->dev[], and for any
1501 * devices which have changed, remove the old device
1502 * info and add the new device info.
bd9244f7
ST		 1503 * If minor device attributes change, just update
1504 * the existing device structure.
edd16368
SC		 1505 */
1506 i = 0;
1507 nremoved = 0;
1508 nadded = 0;
1509 while (i < h->ndevices) {
1510 csd = h->dev[i];
1511 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1512 if (device_change == DEVICE_NOT_FOUND) {
1513 changes++;
1514 hpsa_scsi_remove_entry(h, hostno, i,
1515 removed, &nremoved);
1516 continue; /* remove ^^^, hence i not incremented */
1517 } else if (device_change == DEVICE_CHANGED) {
1518 changes++;
2a8ccf31
SC		 1519 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1520 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1521 /* Set it to NULL to prevent it from being freed
1522 * at the bottom of hpsa_update_scsi_devices()
1523 */
1524 sd[entry] = NULL;
bd9244f7
ST		 1525 } else if (device_change == DEVICE_UPDATED) {
1526 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1527 }
1528 i++;
1529 }
1530
1531 /* Now, make sure every device listed in sd[] is also
1532 * listed in h->dev[], adding them if they aren't found
1533 */
1534
1535 for (i = 0; i < nsds; i++) {
1536 if (!sd[i]) /* if already added above. */
1537 continue;
9846590e
SC		 1538
1539 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1540 * as the SCSI mid-layer does not handle such devices well.
1541 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1542 * at 160Hz, and prevents the system from coming up.
1543 */
1544 if (sd[i]->volume_offline) {
1545 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1546 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1547 continue;
1548 }
1549
edd16368
SC		 1550 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1551 h->ndevices, &entry);
1552 if (device_change == DEVICE_NOT_FOUND) {
1553 changes++;
1554 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1555 added, &nadded) != 0)
1556 break;
1557 sd[i] = NULL; /* prevent from being freed later. */
1558 } else if (device_change == DEVICE_CHANGED) {
1559 /* should never happen... */
1560 changes++;
1561 dev_warn(&h->pdev->dev,
1562 "device unexpectedly changed.\n");
1563 /* but if it does happen, we just ignore that device */
1564 }
1565 }
41ce4c35
SC		 1566 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1567
1568 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1569 * any logical drives that need it enabled.
1570 */
1571 for (i = 0; i < h->ndevices; i++)
1572 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1573
edd16368
SC		 1574 spin_unlock_irqrestore(&h->devlock, flags);
1575
9846590e
SC		 1576 /* Monitor devices which are in one of several NOT READY states to be
1577 * brought online later. This must be done without holding h->devlock,
1578 * so don't touch h->dev[]
1579 */
1580 for (i = 0; i < nsds; i++) {
1581 if (!sd[i]) /* if already added above. */
1582 continue;
1583 if (sd[i]->volume_offline)
1584 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1585 }
1586
edd16368
SC		 1587 /* Don't notify scsi mid layer of any changes the first time through
1588 * (or if there are no changes) scsi_scan_host will do it later the
1589 * first time through.
1590 */
1591 if (hostno == -1 || !changes)
1592 goto free_and_out;
1593
1594 sh = h->scsi_host;
1595 /* Notify scsi mid layer of any removed devices */
1596 for (i = 0; i < nremoved; i++) {
41ce4c35
SC		 1597 if (removed[i]->expose_state & HPSA_SCSI_ADD) {
1598 struct scsi_device *sdev =
1599 scsi_device_lookup(sh, removed[i]->bus,
1600 removed[i]->target, removed[i]->lun);
1601 if (sdev != NULL) {
1602 scsi_remove_device(sdev);
1603 scsi_device_put(sdev);
1604 } else {
1605 /*
1606 * We don't expect to get here.
1607 * future cmds to this device will get selection
1608 * timeout as if the device was gone.
1609 */
0d96ef5f
WS		 1610 hpsa_show_dev_msg(KERN_WARNING, h, removed[i],
1611 "didn't find device for removal.");
41ce4c35 1612 }
edd16368
SC		 1613 }
1614 kfree(removed[i]);
1615 removed[i] = NULL;
1616 }
1617
1618 /* Notify scsi mid layer of any added devices */
1619 for (i = 0; i < nadded; i++) {
41ce4c35
SC		 1620 if (!(added[i]->expose_state & HPSA_SCSI_ADD))
1621 continue;
edd16368
SC		 1622 if (scsi_add_device(sh, added[i]->bus,
1623 added[i]->target, added[i]->lun) == 0)
1624 continue;
0d96ef5f
WS		 1625 hpsa_show_dev_msg(KERN_WARNING, h, added[i],
1626 "addition failed, device not added.");
edd16368
SC		 1627 /* now we have to remove it from h->dev,
1628 * since it didn't get added to scsi mid layer
1629 */
1630 fixup_botched_add(h, added[i]);
1631 }
1632
1633free_and_out:
1634 kfree(added);
1635 kfree(removed);
edd16368
SC		 1636}
1637
1638/*
9e03aa2f 1639 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1640 * Assume's h->devlock is held.
1641 */
1642static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1643 int bus, int target, int lun)
1644{
1645 int i;
1646 struct hpsa_scsi_dev_t *sd;
1647
1648 for (i = 0; i < h->ndevices; i++) {
1649 sd = h->dev[i];
1650 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1651 return sd;
1652 }
1653 return NULL;
1654}
1655
edd16368
SC		 1656static int hpsa_slave_alloc(struct scsi_device *sdev)
1657{
1658 struct hpsa_scsi_dev_t *sd;
1659 unsigned long flags;
1660 struct ctlr_info *h;
1661
1662 h = sdev_to_hba(sdev);
1663 spin_lock_irqsave(&h->devlock, flags);
1664 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1665 sdev_id(sdev), sdev->lun);
41ce4c35 1666 if (likely(sd)) {
03383736 1667 atomic_set(&sd->ioaccel_cmds_out, 0);
41ce4c35
SC		 1668 sdev->hostdata = (sd->expose_state & HPSA_SCSI_ADD) ? sd : NULL;
1669 } else
1670 sdev->hostdata = NULL;
edd16368
SC		 1671 spin_unlock_irqrestore(&h->devlock, flags);
1672 return 0;
1673}
1674
41ce4c35
SC		 1675/* configure scsi device based on internal per-device structure */
1676static int hpsa_slave_configure(struct scsi_device *sdev)
1677{
1678 struct hpsa_scsi_dev_t *sd;
1679 int queue_depth;
1680
1681 sd = sdev->hostdata;
1682 sdev->no_uld_attach = !sd || !(sd->expose_state & HPSA_ULD_ATTACH);
1683
1684 if (sd)
1685 queue_depth = sd->queue_depth != 0 ?
1686 sd->queue_depth : sdev->host->can_queue;
1687 else
1688 queue_depth = sdev->host->can_queue;
1689
1690 scsi_change_queue_depth(sdev, queue_depth);
1691
1692 return 0;
1693}
1694
edd16368
SC		 1695static void hpsa_slave_destroy(struct scsi_device *sdev)
1696{
bcc44255 1697 /* nothing to do. */
edd16368
SC		 1698}
1699
33a2ffce
SC		 1700static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1701{
1702 int i;
1703
1704 if (!h->cmd_sg_list)
1705 return;
1706 for (i = 0; i < h->nr_cmds; i++) {
1707 kfree(h->cmd_sg_list[i]);
1708 h->cmd_sg_list[i] = NULL;
1709 }
1710 kfree(h->cmd_sg_list);
1711 h->cmd_sg_list = NULL;
1712}
1713
1714static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1715{
1716 int i;
1717
1718 if (h->chainsize <= 0)
1719 return 0;
1720
1721 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1722 GFP_KERNEL);
3d4e6af8
RE		 1723 if (!h->cmd_sg_list) {
1724 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1725 return -ENOMEM;
3d4e6af8 1726 }
33a2ffce
SC		 1727 for (i = 0; i < h->nr_cmds; i++) {
1728 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1729 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1730 if (!h->cmd_sg_list[i]) {
1731 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1732 goto clean;
3d4e6af8 1733 }
33a2ffce
SC		 1734 }
1735 return 0;
1736
1737clean:
1738 hpsa_free_sg_chain_blocks(h);
1739 return -ENOMEM;
1740}
1741
e2bea6df 1742static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1743 struct CommandList *c)
1744{
1745 struct SGDescriptor *chain_sg, *chain_block;
1746 u64 temp64;
50a0decf 1747 u32 chain_len;
33a2ffce
SC		 1748
1749 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1750 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 1751 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1752 chain_len = sizeof(*chain_sg) *
2b08b3e9 1753 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 1754 chain_sg->Len = cpu_to_le32(chain_len);
1755 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 1756 PCI_DMA_TODEVICE);
e2bea6df
SC		 1757 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1758 /* prevent subsequent unmapping */
50a0decf 1759 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 1760 return -1;
1761 }
50a0decf 1762 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 1763 return 0;
33a2ffce
SC		 1764}
1765
1766static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1767 struct CommandList *c)
1768{
1769 struct SGDescriptor *chain_sg;
33a2ffce 1770
50a0decf 1771 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 1772 return;
1773
1774 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 1775 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
1776 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 1777}
1778
a09c1441
ST		 1779
1780/* Decode the various types of errors on ioaccel2 path.
1781 * Return 1 for any error that should generate a RAID path retry.
1782 * Return 0 for errors that don't require a RAID path retry.
1783 */
1784static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1785 struct CommandList *c,
1786 struct scsi_cmnd *cmd,
1787 struct io_accel2_cmd *c2)
1788{
1789 int data_len;
a09c1441 1790 int retry = 0;
c349775e
ST		 1791
1792 switch (c2->error_data.serv_response) {
1793 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1794 switch (c2->error_data.status) {
1795 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1796 break;
1797 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1798 dev_warn(&h->pdev->dev,
1799 "%s: task complete with check condition.\n",
1800 "HP SSD Smart Path");
ee6b1889 1801 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 1802 if (c2->error_data.data_present !=
ee6b1889
SC		 1803 IOACCEL2_SENSE_DATA_PRESENT) {
1804 memset(cmd->sense_buffer, 0,
1805 SCSI_SENSE_BUFFERSIZE);
c349775e 1806 break;
ee6b1889 1807 }
c349775e
ST		 1808 /* copy the sense data */
1809 data_len = c2->error_data.sense_data_len;
1810 if (data_len > SCSI_SENSE_BUFFERSIZE)
1811 data_len = SCSI_SENSE_BUFFERSIZE;
1812 if (data_len > sizeof(c2->error_data.sense_data_buff))
1813 data_len =
1814 sizeof(c2->error_data.sense_data_buff);
1815 memcpy(cmd->sense_buffer,
1816 c2->error_data.sense_data_buff, data_len);
a09c1441 1817 retry = 1;
c349775e
ST		 1818 break;
1819 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1820 dev_warn(&h->pdev->dev,
1821 "%s: task complete with BUSY status.\n",
1822 "HP SSD Smart Path");
a09c1441 1823 retry = 1;
c349775e
ST		 1824 break;
1825 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1826 dev_warn(&h->pdev->dev,
1827 "%s: task complete with reservation conflict.\n",
1828 "HP SSD Smart Path");
a09c1441 1829 retry = 1;
c349775e
ST		 1830 break;
1831 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 1832 retry = 1;
c349775e
ST		 1833 break;
1834 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1835 dev_warn(&h->pdev->dev,
1836 "%s: task complete with aborted status.\n",
1837 "HP SSD Smart Path");
a09c1441 1838 retry = 1;
c349775e
ST		 1839 break;
1840 default:
1841 dev_warn(&h->pdev->dev,
1842 "%s: task complete with unrecognized status: 0x%02x\n",
1843 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1844 retry = 1;
c349775e
ST		 1845 break;
1846 }
1847 break;
1848 case IOACCEL2_SERV_RESPONSE_FAILURE:
1849 /* don't expect to get here. */
1850 dev_warn(&h->pdev->dev,
1851 "unexpected delivery or target failure, status = 0x%02x\n",
1852 c2->error_data.status);
a09c1441 1853 retry = 1;
c349775e
ST		 1854 break;
1855 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1856 break;
1857 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1858 break;
1859 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1860 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1861 retry = 1;
c349775e
ST		 1862 break;
1863 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1864 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1865 break;
1866 default:
1867 dev_warn(&h->pdev->dev,
1868 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1869 "HP SSD Smart Path",
1870 c2->error_data.serv_response);
1871 retry = 1;
c349775e
ST		 1872 break;
1873 }
a09c1441
ST		 1874
1875 return retry; /* retry on raid path? */
c349775e
ST		 1876}
1877
1878static void process_ioaccel2_completion(struct ctlr_info *h,
1879 struct CommandList *c, struct scsi_cmnd *cmd,
1880 struct hpsa_scsi_dev_t *dev)
1881{
1882 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
1883
1884 /* check for good status */
1885 if (likely(c2->error_data.serv_response == 0 &&
1886 c2->error_data.status == 0)) {
1887 cmd_free(h, c);
1888 cmd->scsi_done(cmd);
1889 return;
1890 }
1891
1892 /* Any RAID offload error results in retry which will use
1893 * the normal I/O path so the controller can handle whatever's
1894 * wrong.
1895 */
1896 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1897 c2->error_data.serv_response ==
1898 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 1899 if (c2->error_data.status ==
1900 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1901 dev->offload_enabled = 0;
1902 goto retry_cmd;
a09c1441 1903 }
080ef1cc
DB		 1904
1905 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
1906 goto retry_cmd;
1907
c349775e
ST		 1908 cmd_free(h, c);
1909 cmd->scsi_done(cmd);
080ef1cc
DB		 1910 return;
1911
1912retry_cmd:
1913 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
1914 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
c349775e
ST		 1915}
1916
9437ac43
SC		 1917/* Returns 0 on success, < 0 otherwise. */
1918static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
1919 struct CommandList *cp)
1920{
1921 u8 tmf_status = cp->err_info->ScsiStatus;
1922
1923 switch (tmf_status) {
1924 case CISS_TMF_COMPLETE:
1925 /*
1926 * CISS_TMF_COMPLETE never happens, instead,
1927 * ei->CommandStatus == 0 for this case.
1928 */
1929 case CISS_TMF_SUCCESS:
1930 return 0;
1931 case CISS_TMF_INVALID_FRAME:
1932 case CISS_TMF_NOT_SUPPORTED:
1933 case CISS_TMF_FAILED:
1934 case CISS_TMF_WRONG_LUN:
1935 case CISS_TMF_OVERLAPPED_TAG:
1936 break;
1937 default:
1938 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
1939 tmf_status);
1940 break;
1941 }
1942 return -tmf_status;
1943}
1944
1fb011fb 1945static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1946{
1947 struct scsi_cmnd *cmd;
1948 struct ctlr_info *h;
1949 struct ErrorInfo *ei;
283b4a9b 1950 struct hpsa_scsi_dev_t *dev;
edd16368 1951
9437ac43
SC		 1952 u8 sense_key;
1953 u8 asc; /* additional sense code */
1954 u8 ascq; /* additional sense code qualifier */
db111e18 1955 unsigned long sense_data_size;
edd16368
SC		 1956
1957 ei = cp->err_info;
7fa3030c 1958 cmd = cp->scsi_cmd;
edd16368 1959 h = cp->h;
283b4a9b 1960 dev = cmd->device->hostdata;
edd16368
SC		 1961
1962 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 1963 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 1964 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 1965 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1966
1967 cmd->result = (DID_OK << 16); /* host byte */
1968 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 1969
03383736
DB		 1970 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
1971 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
1972
25163bd5
WS		 1973 /*
1974 * We check for lockup status here as it may be set for
1975 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
1976 * fail_all_oustanding_cmds()
1977 */
1978 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
1979 /* DID_NO_CONNECT will prevent a retry */
1980 cmd->result = DID_NO_CONNECT << 16;
1981 cmd_free(h, cp);
1982 cmd->scsi_done(cmd);
1983 return;
1984 }
1985
c349775e
ST		 1986 if (cp->cmd_type == CMD_IOACCEL2)
1987 return process_ioaccel2_completion(h, cp, cmd, dev);
1988
6aa4c361
RE		 1989 scsi_set_resid(cmd, ei->ResidualCnt);
1990 if (ei->CommandStatus == 0) {
03383736
DB		 1991 if (cp->cmd_type == CMD_IOACCEL1)
1992 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
6aa4c361
RE		 1993 cmd_free(h, cp);
1994 cmd->scsi_done(cmd);
1995 return;
1996 }
1997
e1f7de0c
MG		 1998 /* For I/O accelerator commands, copy over some fields to the normal
1999 * CISS header used below for error handling.
2000 */
2001 if (cp->cmd_type == CMD_IOACCEL1) {
2002 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2003 cp->Header.SGList = scsi_sg_count(cmd);
2004 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2005 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2006 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2007 cp->Header.tag = c->tag;
e1f7de0c
MG		 2008 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2009 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2010
2011 /* Any RAID offload error results in retry which will use
2012 * the normal I/O path so the controller can handle whatever's
2013 * wrong.
2014 */
2015 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
2016 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2017 dev->offload_enabled = 0;
080ef1cc
DB		 2018 INIT_WORK(&cp->work, hpsa_command_resubmit_worker);
2019 queue_work_on(raw_smp_processor_id(),
2020 h->resubmit_wq, &cp->work);
283b4a9b
SC		 2021 return;
2022 }
e1f7de0c
MG		 2023 }
2024
edd16368
SC		 2025 /* an error has occurred */
2026 switch (ei->CommandStatus) {
2027
2028 case CMD_TARGET_STATUS:
9437ac43
SC		 2029 cmd->result |= ei->ScsiStatus;
2030 /* copy the sense data */
2031 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2032 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2033 else
2034 sense_data_size = sizeof(ei->SenseInfo);
2035 if (ei->SenseLen < sense_data_size)
2036 sense_data_size = ei->SenseLen;
2037 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2038 if (ei->ScsiStatus)
2039 decode_sense_data(ei->SenseInfo, sense_data_size,
2040 &sense_key, &asc, &ascq);
edd16368 2041 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2042 if (sense_key == ABORTED_COMMAND) {
2e311fba 2043 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2044 break;
2045 }
edd16368
SC		 2046 break;
2047 }
edd16368
SC		 2048 /* Problem was not a check condition
2049 * Pass it up to the upper layers...
2050 */
2051 if (ei->ScsiStatus) {
2052 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2053 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2054 "Returning result: 0x%x\n",
2055 cp, ei->ScsiStatus,
2056 sense_key, asc, ascq,
2057 cmd->result);
2058 } else { /* scsi status is zero??? How??? */
2059 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2060 "Returning no connection.\n", cp),
2061
2062 /* Ordinarily, this case should never happen,
2063 * but there is a bug in some released firmware
2064 * revisions that allows it to happen if, for
2065 * example, a 4100 backplane loses power and
2066 * the tape drive is in it. We assume that
2067 * it's a fatal error of some kind because we
2068 * can't show that it wasn't. We will make it
2069 * look like selection timeout since that is
2070 * the most common reason for this to occur,
2071 * and it's severe enough.
2072 */
2073
2074 cmd->result = DID_NO_CONNECT << 16;
2075 }
2076 break;
2077
2078 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2079 break;
2080 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2081 dev_warn(&h->pdev->dev,
2082 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2083 break;
2084 case CMD_INVALID: {
2085 /* print_bytes(cp, sizeof(*cp), 1, 0);
2086 print_cmd(cp); */
2087 /* We get CMD_INVALID if you address a non-existent device
2088 * instead of a selection timeout (no response). You will
2089 * see this if you yank out a drive, then try to access it.
2090 * This is kind of a shame because it means that any other
2091 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2092 * missing target. */
2093 cmd->result = DID_NO_CONNECT << 16;
2094 }
2095 break;
2096 case CMD_PROTOCOL_ERR:
256d0eaa 2097 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2098 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2099 cp->Request.CDB);
edd16368
SC		 2100 break;
2101 case CMD_HARDWARE_ERR:
2102 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2103 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2104 cp->Request.CDB);
edd16368
SC		 2105 break;
2106 case CMD_CONNECTION_LOST:
2107 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2108 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2109 cp->Request.CDB);
edd16368
SC		 2110 break;
2111 case CMD_ABORTED:
2112 cmd->result = DID_ABORT << 16;
f42e81e1
SC		 2113 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2114 cp->Request.CDB, ei->ScsiStatus);
edd16368
SC		 2115 break;
2116 case CMD_ABORT_FAILED:
2117 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2118 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2119 cp->Request.CDB);
edd16368
SC		 2120 break;
2121 case CMD_UNSOLICITED_ABORT:
f6e76055 2122 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2123 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2124 cp->Request.CDB);
edd16368
SC		 2125 break;
2126 case CMD_TIMEOUT:
2127 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2128 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2129 cp->Request.CDB);
edd16368 2130 break;
1d5e2ed0
SC		 2131 case CMD_UNABORTABLE:
2132 cmd->result = DID_ERROR << 16;
2133 dev_warn(&h->pdev->dev, "Command unabortable\n");
2134 break;
9437ac43
SC		 2135 case CMD_TMF_STATUS:
2136 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2137 cmd->result = DID_ERROR << 16;
2138 break;
283b4a9b
SC		 2139 case CMD_IOACCEL_DISABLED:
2140 /* This only handles the direct pass-through case since RAID
2141 * offload is handled above. Just attempt a retry.
2142 */
2143 cmd->result = DID_SOFT_ERROR << 16;
2144 dev_warn(&h->pdev->dev,
2145 "cp %p had HP SSD Smart Path error\n", cp);
2146 break;
edd16368
SC		 2147 default:
2148 cmd->result = DID_ERROR << 16;
2149 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2150 cp, ei->CommandStatus);
2151 }
edd16368 2152 cmd_free(h, cp);
2cc5bfaf 2153 cmd->scsi_done(cmd);
edd16368
SC		 2154}
2155
edd16368
SC		 2156static void hpsa_pci_unmap(struct pci_dev *pdev,
2157 struct CommandList *c, int sg_used, int data_direction)
2158{
2159 int i;
edd16368 2160
50a0decf
SC		 2161 for (i = 0; i < sg_used; i++)
2162 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2163 le32_to_cpu(c->SG[i].Len),
2164 data_direction);
edd16368
SC		 2165}
2166
a2dac136 2167static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2168 struct CommandList *cp,
2169 unsigned char *buf,
2170 size_t buflen,
2171 int data_direction)
2172{
01a02ffc 2173 u64 addr64;
edd16368
SC		 2174
2175 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2176 cp->Header.SGList = 0;
50a0decf 2177 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2178 return 0;
edd16368
SC		 2179 }
2180
50a0decf 2181 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2182 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2183 /* Prevent subsequent unmap of something never mapped */
eceaae18 2184 cp->Header.SGList = 0;
50a0decf 2185 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2186 return -1;
eceaae18 2187 }
50a0decf
SC		 2188 cp->SG[0].Addr = cpu_to_le64(addr64);
2189 cp->SG[0].Len = cpu_to_le32(buflen);
2190 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2191 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2192 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2193 return 0;
edd16368
SC		 2194}
2195
25163bd5
WS		 2196#define NO_TIMEOUT ((unsigned long) -1)
2197#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2198static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2199 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2200{
2201 DECLARE_COMPLETION_ONSTACK(wait);
2202
2203 c->waiting = &wait;
25163bd5
WS		 2204 __enqueue_cmd_and_start_io(h, c, reply_queue);
2205 if (timeout_msecs == NO_TIMEOUT) {
2206 /* TODO: get rid of this no-timeout thing */
2207 wait_for_completion_io(&wait);
2208 return IO_OK;
2209 }
2210 if (!wait_for_completion_io_timeout(&wait,
2211 msecs_to_jiffies(timeout_msecs))) {
2212 dev_warn(&h->pdev->dev, "Command timed out.\n");
2213 return -ETIMEDOUT;
2214 }
2215 return IO_OK;
2216}
2217
2218static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2219 int reply_queue, unsigned long timeout_msecs)
2220{
2221 if (unlikely(lockup_detected(h))) {
2222 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2223 return IO_OK;
2224 }
2225 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2226}
2227
094963da
SC		 2228static u32 lockup_detected(struct ctlr_info *h)
2229{
2230 int cpu;
2231 u32 rc, *lockup_detected;
2232
2233 cpu = get_cpu();
2234 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2235 rc = *lockup_detected;
2236 put_cpu();
2237 return rc;
2238}
2239
9c2fc160 2240#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2241static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2242 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2243{
9c2fc160 2244 int backoff_time = 10, retry_count = 0;
25163bd5 2245 int rc;
edd16368
SC		 2246
2247 do {
7630abd0 2248 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2249 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2250 timeout_msecs);
2251 if (rc)
2252 break;
edd16368 2253 retry_count++;
9c2fc160
SC		 2254 if (retry_count > 3) {
2255 msleep(backoff_time);
2256 if (backoff_time < 1000)
2257 backoff_time *= 2;
2258 }
852af20a 2259 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2260 check_for_busy(h, c)) &&
2261 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2262 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2263 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2264 rc = -EIO;
2265 return rc;
edd16368
SC		 2266}
2267
d1e8beac
SC		 2268static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2269 struct CommandList *c)
edd16368 2270{
d1e8beac
SC		 2271 const u8 *cdb = c->Request.CDB;
2272 const u8 *lun = c->Header.LUN.LunAddrBytes;
2273
2274 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2275 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2276 txt, lun[0], lun[1], lun[2], lun[3],
2277 lun[4], lun[5], lun[6], lun[7],
2278 cdb[0], cdb[1], cdb[2], cdb[3],
2279 cdb[4], cdb[5], cdb[6], cdb[7],
2280 cdb[8], cdb[9], cdb[10], cdb[11],
2281 cdb[12], cdb[13], cdb[14], cdb[15]);
2282}
2283
2284static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2285 struct CommandList *cp)
2286{
2287 const struct ErrorInfo *ei = cp->err_info;
edd16368 2288 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2289 u8 sense_key, asc, ascq;
2290 int sense_len;
edd16368 2291
edd16368
SC		 2292 switch (ei->CommandStatus) {
2293 case CMD_TARGET_STATUS:
9437ac43
SC		 2294 if (ei->SenseLen > sizeof(ei->SenseInfo))
2295 sense_len = sizeof(ei->SenseInfo);
2296 else
2297 sense_len = ei->SenseLen;
2298 decode_sense_data(ei->SenseInfo, sense_len,
2299 &sense_key, &asc, &ascq);
d1e8beac
SC		 2300 hpsa_print_cmd(h, "SCSI status", cp);
2301 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2302 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2303 sense_key, asc, ascq);
d1e8beac 2304 else
9437ac43 2305 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2306 if (ei->ScsiStatus == 0)
2307 dev_warn(d, "SCSI status is abnormally zero. "
2308 "(probably indicates selection timeout "
2309 "reported incorrectly due to a known "
2310 "firmware bug, circa July, 2001.)\n");
2311 break;
2312 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2313 break;
2314 case CMD_DATA_OVERRUN:
d1e8beac 2315 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2316 break;
2317 case CMD_INVALID: {
2318 /* controller unfortunately reports SCSI passthru's
2319 * to non-existent targets as invalid commands.
2320 */
d1e8beac
SC		 2321 hpsa_print_cmd(h, "invalid command", cp);
2322 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2323 }
2324 break;
2325 case CMD_PROTOCOL_ERR:
d1e8beac 2326 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2327 break;
2328 case CMD_HARDWARE_ERR:
d1e8beac 2329 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2330 break;
2331 case CMD_CONNECTION_LOST:
d1e8beac 2332 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2333 break;
2334 case CMD_ABORTED:
d1e8beac 2335 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2336 break;
2337 case CMD_ABORT_FAILED:
d1e8beac 2338 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2339 break;
2340 case CMD_UNSOLICITED_ABORT:
d1e8beac 2341 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2342 break;
2343 case CMD_TIMEOUT:
d1e8beac 2344 hpsa_print_cmd(h, "timed out", cp);
edd16368 2345 break;
1d5e2ed0 2346 case CMD_UNABORTABLE:
d1e8beac 2347 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2348 break;
25163bd5
WS		 2349 case CMD_CTLR_LOCKUP:
2350 hpsa_print_cmd(h, "controller lockup detected", cp);
2351 break;
edd16368 2352 default:
d1e8beac
SC		 2353 hpsa_print_cmd(h, "unknown status", cp);
2354 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2355 ei->CommandStatus);
2356 }
2357}
2358
2359static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2360 u16 page, unsigned char *buf,
edd16368
SC		 2361 unsigned char bufsize)
2362{
2363 int rc = IO_OK;
2364 struct CommandList *c;
2365 struct ErrorInfo *ei;
2366
45fcb86e 2367 c = cmd_alloc(h);
edd16368 2368
574f05d3 2369 if (c == NULL) {
45fcb86e 2370 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
ecd9aad4 2371 return -ENOMEM;
edd16368
SC		 2372 }
2373
a2dac136
SC		 2374 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2375 page, scsi3addr, TYPE_CMD)) {
2376 rc = -1;
2377 goto out;
2378 }
25163bd5
WS		 2379 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2380 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2381 if (rc)
2382 goto out;
edd16368
SC		 2383 ei = c->err_info;
2384 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2385 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2386 rc = -1;
2387 }
a2dac136 2388out:
45fcb86e 2389 cmd_free(h, c);
edd16368
SC		 2390 return rc;
2391}
2392
316b221a
SC		 2393static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2394 unsigned char *scsi3addr, unsigned char page,
2395 struct bmic_controller_parameters *buf, size_t bufsize)
2396{
2397 int rc = IO_OK;
2398 struct CommandList *c;
2399 struct ErrorInfo *ei;
2400
45fcb86e 2401 c = cmd_alloc(h);
316b221a 2402 if (c == NULL) { /* trouble... */
45fcb86e 2403 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
316b221a
SC		 2404 return -ENOMEM;
2405 }
2406
2407 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2408 page, scsi3addr, TYPE_CMD)) {
2409 rc = -1;
2410 goto out;
2411 }
25163bd5
WS		 2412 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2413 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2414 if (rc)
2415 goto out;
316b221a
SC		 2416 ei = c->err_info;
2417 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2418 hpsa_scsi_interpret_error(h, c);
2419 rc = -1;
2420 }
2421out:
45fcb86e 2422 cmd_free(h, c);
316b221a
SC		 2423 return rc;
2424 }
2425
bf711ac6 2426static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2427 u8 reset_type, int reply_queue)
edd16368
SC		 2428{
2429 int rc = IO_OK;
2430 struct CommandList *c;
2431 struct ErrorInfo *ei;
2432
45fcb86e 2433 c = cmd_alloc(h);
edd16368
SC		 2434
2435 if (c == NULL) { /* trouble... */
45fcb86e 2436 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
e9ea04a6 2437 return -ENOMEM;
edd16368
SC		 2438 }
2439
a2dac136 2440 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2441 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2442 scsi3addr, TYPE_MSG);
2443 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
25163bd5
WS		 2444 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2445 if (rc) {
2446 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2447 goto out;
2448 }
edd16368
SC		 2449 /* no unmap needed here because no data xfer. */
2450
2451 ei = c->err_info;
2452 if (ei->CommandStatus != 0) {
d1e8beac 2453 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2454 rc = -1;
2455 }
25163bd5 2456out:
45fcb86e 2457 cmd_free(h, c);
edd16368
SC		 2458 return rc;
2459}
2460
2461static void hpsa_get_raid_level(struct ctlr_info *h,
2462 unsigned char *scsi3addr, unsigned char *raid_level)
2463{
2464 int rc;
2465 unsigned char *buf;
2466
2467 *raid_level = RAID_UNKNOWN;
2468 buf = kzalloc(64, GFP_KERNEL);
2469 if (!buf)
2470 return;
b7bb24eb 2471 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2472 if (rc == 0)
2473 *raid_level = buf[8];
2474 if (*raid_level > RAID_UNKNOWN)
2475 *raid_level = RAID_UNKNOWN;
2476 kfree(buf);
2477 return;
2478}
2479
283b4a9b
SC		 2480#define HPSA_MAP_DEBUG
2481#ifdef HPSA_MAP_DEBUG
2482static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2483 struct raid_map_data *map_buff)
2484{
2485 struct raid_map_disk_data *dd = &map_buff->data[0];
2486 int map, row, col;
2487 u16 map_cnt, row_cnt, disks_per_row;
2488
2489 if (rc != 0)
2490 return;
2491
2ba8bfc8
SC		 2492 /* Show details only if debugging has been activated. */
2493 if (h->raid_offload_debug < 2)
2494 return;
2495
283b4a9b
SC		 2496 dev_info(&h->pdev->dev, "structure_size = %u\n",
2497 le32_to_cpu(map_buff->structure_size));
2498 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2499 le32_to_cpu(map_buff->volume_blk_size));
2500 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2501 le64_to_cpu(map_buff->volume_blk_cnt));
2502 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2503 map_buff->phys_blk_shift);
2504 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2505 map_buff->parity_rotation_shift);
2506 dev_info(&h->pdev->dev, "strip_size = %u\n",
2507 le16_to_cpu(map_buff->strip_size));
2508 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2509 le64_to_cpu(map_buff->disk_starting_blk));
2510 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2511 le64_to_cpu(map_buff->disk_blk_cnt));
2512 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2513 le16_to_cpu(map_buff->data_disks_per_row));
2514 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2515 le16_to_cpu(map_buff->metadata_disks_per_row));
2516 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2517 le16_to_cpu(map_buff->row_cnt));
2518 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2519 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2520 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2521 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2522 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2523 le16_to_cpu(map_buff->flags) &
2524 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2525 dev_info(&h->pdev->dev, "dekindex = %u\n",
2526 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2527 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2528 for (map = 0; map < map_cnt; map++) {
2529 dev_info(&h->pdev->dev, "Map%u:\n", map);
2530 row_cnt = le16_to_cpu(map_buff->row_cnt);
2531 for (row = 0; row < row_cnt; row++) {
2532 dev_info(&h->pdev->dev, " Row%u:\n", row);
2533 disks_per_row =
2534 le16_to_cpu(map_buff->data_disks_per_row);
2535 for (col = 0; col < disks_per_row; col++, dd++)
2536 dev_info(&h->pdev->dev,
2537 " D%02u: h=0x%04x xor=%u,%u\n",
2538 col, dd->ioaccel_handle,
2539 dd->xor_mult[0], dd->xor_mult[1]);
2540 disks_per_row =
2541 le16_to_cpu(map_buff->metadata_disks_per_row);
2542 for (col = 0; col < disks_per_row; col++, dd++)
2543 dev_info(&h->pdev->dev,
2544 " M%02u: h=0x%04x xor=%u,%u\n",
2545 col, dd->ioaccel_handle,
2546 dd->xor_mult[0], dd->xor_mult[1]);
2547 }
2548 }
2549}
2550#else
2551static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2552 __attribute__((unused)) int rc,
2553 __attribute__((unused)) struct raid_map_data *map_buff)
2554{
2555}
2556#endif
2557
2558static int hpsa_get_raid_map(struct ctlr_info *h,
2559 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2560{
2561 int rc = 0;
2562 struct CommandList *c;
2563 struct ErrorInfo *ei;
2564
45fcb86e 2565 c = cmd_alloc(h);
283b4a9b 2566 if (c == NULL) {
45fcb86e 2567 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
283b4a9b
SC		 2568 return -ENOMEM;
2569 }
2570 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2571 sizeof(this_device->raid_map), 0,
2572 scsi3addr, TYPE_CMD)) {
2573 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
25163bd5
WS		 2574 rc = -ENOMEM;
2575 goto out;
283b4a9b 2576 }
25163bd5
WS		 2577 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2578 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2579 if (rc)
2580 goto out;
283b4a9b
SC		 2581 ei = c->err_info;
2582 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2583 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 2584 rc = -1;
2585 goto out;
283b4a9b 2586 }
45fcb86e 2587 cmd_free(h, c);
283b4a9b
SC		 2588
2589 /* @todo in the future, dynamically allocate RAID map memory */
2590 if (le32_to_cpu(this_device->raid_map.structure_size) >
2591 sizeof(this_device->raid_map)) {
2592 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2593 rc = -1;
2594 }
2595 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2596 return rc;
25163bd5
WS		 2597out:
2598 cmd_free(h, c);
2599 return rc;
283b4a9b
SC		 2600}
2601
03383736
DB		 2602static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
2603 unsigned char scsi3addr[], u16 bmic_device_index,
2604 struct bmic_identify_physical_device *buf, size_t bufsize)
2605{
2606 int rc = IO_OK;
2607 struct CommandList *c;
2608 struct ErrorInfo *ei;
2609
2610 c = cmd_alloc(h);
2611 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
2612 0, RAID_CTLR_LUNID, TYPE_CMD);
2613 if (rc)
2614 goto out;
2615
2616 c->Request.CDB[2] = bmic_device_index & 0xff;
2617 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
2618
25163bd5
WS		 2619 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
2620 NO_TIMEOUT);
03383736
DB		 2621 ei = c->err_info;
2622 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2623 hpsa_scsi_interpret_error(h, c);
2624 rc = -1;
2625 }
2626out:
2627 cmd_free(h, c);
2628 return rc;
2629}
2630
1b70150a
SC		 2631static int hpsa_vpd_page_supported(struct ctlr_info *h,
2632 unsigned char scsi3addr[], u8 page)
2633{
2634 int rc;
2635 int i;
2636 int pages;
2637 unsigned char *buf, bufsize;
2638
2639 buf = kzalloc(256, GFP_KERNEL);
2640 if (!buf)
2641 return 0;
2642
2643 /* Get the size of the page list first */
2644 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2645 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2646 buf, HPSA_VPD_HEADER_SZ);
2647 if (rc != 0)
2648 goto exit_unsupported;
2649 pages = buf[3];
2650 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2651 bufsize = pages + HPSA_VPD_HEADER_SZ;
2652 else
2653 bufsize = 255;
2654
2655 /* Get the whole VPD page list */
2656 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2657 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2658 buf, bufsize);
2659 if (rc != 0)
2660 goto exit_unsupported;
2661
2662 pages = buf[3];
2663 for (i = 1; i <= pages; i++)
2664 if (buf[3 + i] == page)
2665 goto exit_supported;
2666exit_unsupported:
2667 kfree(buf);
2668 return 0;
2669exit_supported:
2670 kfree(buf);
2671 return 1;
2672}
2673
283b4a9b
SC		 2674static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2675 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2676{
2677 int rc;
2678 unsigned char *buf;
2679 u8 ioaccel_status;
2680
2681 this_device->offload_config = 0;
2682 this_device->offload_enabled = 0;
41ce4c35 2683 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 2684
2685 buf = kzalloc(64, GFP_KERNEL);
2686 if (!buf)
2687 return;
1b70150a
SC		 2688 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2689 goto out;
283b4a9b 2690 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2691 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2692 if (rc != 0)
2693 goto out;
2694
2695#define IOACCEL_STATUS_BYTE 4
2696#define OFFLOAD_CONFIGURED_BIT 0x01
2697#define OFFLOAD_ENABLED_BIT 0x02
2698 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2699 this_device->offload_config =
2700 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2701 if (this_device->offload_config) {
2702 this_device->offload_enabled =
2703 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2704 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2705 this_device->offload_enabled = 0;
2706 }
41ce4c35 2707 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 2708out:
2709 kfree(buf);
2710 return;
2711}
2712
edd16368
SC		 2713/* Get the device id from inquiry page 0x83 */
2714static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2715 unsigned char *device_id, int buflen)
2716{
2717 int rc;
2718 unsigned char *buf;
2719
2720 if (buflen > 16)
2721 buflen = 16;
2722 buf = kzalloc(64, GFP_KERNEL);
2723 if (!buf)
a84d794d 2724 return -ENOMEM;
b7bb24eb 2725 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2726 if (rc == 0)
2727 memcpy(device_id, &buf[8], buflen);
2728 kfree(buf);
2729 return rc != 0;
2730}
2731
2732static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 2733 void *buf, int bufsize,
edd16368
SC		 2734 int extended_response)
2735{
2736 int rc = IO_OK;
2737 struct CommandList *c;
2738 unsigned char scsi3addr[8];
2739 struct ErrorInfo *ei;
2740
45fcb86e 2741 c = cmd_alloc(h);
edd16368 2742 if (c == NULL) { /* trouble... */
45fcb86e 2743 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 2744 return -1;
2745 }
e89c0ae7
SC		 2746 /* address the controller */
2747 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2748 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2749 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2750 rc = -1;
2751 goto out;
2752 }
edd16368
SC		 2753 if (extended_response)
2754 c->Request.CDB[1] = extended_response;
25163bd5
WS		 2755 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2756 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2757 if (rc)
2758 goto out;
edd16368
SC		 2759 ei = c->err_info;
2760 if (ei->CommandStatus != 0 &&
2761 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2762 hpsa_scsi_interpret_error(h, c);
edd16368 2763 rc = -1;
283b4a9b 2764 } else {
03383736
DB		 2765 struct ReportLUNdata *rld = buf;
2766
2767 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 2768 dev_err(&h->pdev->dev,
2769 "report luns requested format %u, got %u\n",
2770 extended_response,
03383736 2771 rld->extended_response_flag);
283b4a9b
SC		 2772 rc = -1;
2773 }
edd16368 2774 }
a2dac136 2775out:
45fcb86e 2776 cmd_free(h, c);
edd16368
SC		 2777 return rc;
2778}
2779
2780static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 2781 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 2782{
03383736
DB		 2783 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
2784 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 2785}
2786
2787static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2788 struct ReportLUNdata *buf, int bufsize)
2789{
2790 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2791}
2792
2793static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2794 int bus, int target, int lun)
2795{
2796 device->bus = bus;
2797 device->target = target;
2798 device->lun = lun;
2799}
2800
9846590e
SC		 2801/* Use VPD inquiry to get details of volume status */
2802static int hpsa_get_volume_status(struct ctlr_info *h,
2803 unsigned char scsi3addr[])
2804{
2805 int rc;
2806 int status;
2807 int size;
2808 unsigned char *buf;
2809
2810 buf = kzalloc(64, GFP_KERNEL);
2811 if (!buf)
2812 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2813
2814 /* Does controller have VPD for logical volume status? */
24a4b078 2815 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 2816 goto exit_failed;
9846590e
SC		 2817
2818 /* Get the size of the VPD return buffer */
2819 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2820 buf, HPSA_VPD_HEADER_SZ);
24a4b078 2821 if (rc != 0)
9846590e 2822 goto exit_failed;
9846590e
SC		 2823 size = buf[3];
2824
2825 /* Now get the whole VPD buffer */
2826 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2827 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 2828 if (rc != 0)
9846590e 2829 goto exit_failed;
9846590e
SC		 2830 status = buf[4]; /* status byte */
2831
2832 kfree(buf);
2833 return status;
2834exit_failed:
2835 kfree(buf);
2836 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2837}
2838
2839/* Determine offline status of a volume.
2840 * Return either:
2841 * 0 (not offline)
67955ba3 2842 * 0xff (offline for unknown reasons)
9846590e
SC		 2843 * # (integer code indicating one of several NOT READY states
2844 * describing why a volume is to be kept offline)
2845 */
67955ba3 2846static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 2847 unsigned char scsi3addr[])
2848{
2849 struct CommandList *c;
9437ac43
SC		 2850 unsigned char *sense;
2851 u8 sense_key, asc, ascq;
2852 int sense_len;
25163bd5 2853 int rc, ldstat = 0;
9846590e
SC		 2854 u16 cmd_status;
2855 u8 scsi_status;
2856#define ASC_LUN_NOT_READY 0x04
2857#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
2858#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
2859
2860 c = cmd_alloc(h);
2861 if (!c)
2862 return 0;
2863 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
25163bd5
WS		 2864 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
2865 if (rc) {
2866 cmd_free(h, c);
2867 return 0;
2868 }
9846590e 2869 sense = c->err_info->SenseInfo;
9437ac43
SC		 2870 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
2871 sense_len = sizeof(c->err_info->SenseInfo);
2872 else
2873 sense_len = c->err_info->SenseLen;
2874 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 2875 cmd_status = c->err_info->CommandStatus;
2876 scsi_status = c->err_info->ScsiStatus;
2877 cmd_free(h, c);
2878 /* Is the volume 'not ready'? */
2879 if (cmd_status != CMD_TARGET_STATUS ||
2880 scsi_status != SAM_STAT_CHECK_CONDITION ||
2881 sense_key != NOT_READY ||
2882 asc != ASC_LUN_NOT_READY) {
2883 return 0;
2884 }
2885
2886 /* Determine the reason for not ready state */
2887 ldstat = hpsa_get_volume_status(h, scsi3addr);
2888
2889 /* Keep volume offline in certain cases: */
2890 switch (ldstat) {
2891 case HPSA_LV_UNDERGOING_ERASE:
2892 case HPSA_LV_UNDERGOING_RPI:
2893 case HPSA_LV_PENDING_RPI:
2894 case HPSA_LV_ENCRYPTED_NO_KEY:
2895 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
2896 case HPSA_LV_UNDERGOING_ENCRYPTION:
2897 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
2898 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
2899 return ldstat;
2900 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
2901 /* If VPD status page isn't available,
2902 * use ASC/ASCQ to determine state
2903 */
2904 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
2905 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
2906 return ldstat;
2907 break;
2908 default:
2909 break;
2910 }
2911 return 0;
2912}
2913
9b5c48c2
SC		 2914/*
2915 * Find out if a logical device supports aborts by simply trying one.
2916 * Smart Array may claim not to support aborts on logical drives, but
2917 * if a MSA2000 * is connected, the drives on that will be presented
2918 * by the Smart Array as logical drives, and aborts may be sent to
2919 * those devices successfully. So the simplest way to find out is
2920 * to simply try an abort and see how the device responds.
2921 */
2922static int hpsa_device_supports_aborts(struct ctlr_info *h,
2923 unsigned char *scsi3addr)
2924{
2925 struct CommandList *c;
2926 struct ErrorInfo *ei;
2927 int rc = 0;
2928
2929 u64 tag = (u64) -1; /* bogus tag */
2930
2931 /* Assume that physical devices support aborts */
2932 if (!is_logical_dev_addr_mode(scsi3addr))
2933 return 1;
2934
2935 c = cmd_alloc(h);
2936 if (!c)
2937 return -ENOMEM;
2938 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
2939 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
2940 /* no unmap needed here because no data xfer. */
2941 ei = c->err_info;
2942 switch (ei->CommandStatus) {
2943 case CMD_INVALID:
2944 rc = 0;
2945 break;
2946 case CMD_UNABORTABLE:
2947 case CMD_ABORT_FAILED:
2948 rc = 1;
2949 break;
9437ac43
SC		 2950 case CMD_TMF_STATUS:
2951 rc = hpsa_evaluate_tmf_status(h, c);
2952 break;
9b5c48c2
SC		 2953 default:
2954 rc = 0;
2955 break;
2956 }
2957 cmd_free(h, c);
2958 return rc;
2959}
2960
edd16368 2961static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2962 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2963 unsigned char *is_OBDR_device)
edd16368 2964{
0b0e1d6c
SC		 2965
2966#define OBDR_SIG_OFFSET 43
2967#define OBDR_TAPE_SIG "$DR-10"
2968#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2969#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2970
ea6d3bc3 2971 unsigned char *inq_buff;
0b0e1d6c 2972 unsigned char *obdr_sig;
edd16368 2973
ea6d3bc3 2974 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2975 if (!inq_buff)
2976 goto bail_out;
2977
edd16368
SC		 2978 /* Do an inquiry to the device to see what it is. */
2979 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2980 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2981 /* Inquiry failed (msg printed already) */
2982 dev_err(&h->pdev->dev,
2983 "hpsa_update_device_info: inquiry failed\n");
2984 goto bail_out;
2985 }
2986
edd16368
SC		 2987 this_device->devtype = (inq_buff[0] & 0x1f);
2988 memcpy(this_device->scsi3addr, scsi3addr, 8);
2989 memcpy(this_device->vendor, &inq_buff[8],
2990 sizeof(this_device->vendor));
2991 memcpy(this_device->model, &inq_buff[16],
2992 sizeof(this_device->model));
edd16368
SC		 2993 memset(this_device->device_id, 0,
2994 sizeof(this_device->device_id));
2995 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2996 sizeof(this_device->device_id));
2997
2998 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2999 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3000 int volume_offline;
3001
edd16368 3002 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3003 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3004 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3005 volume_offline = hpsa_volume_offline(h, scsi3addr);
3006 if (volume_offline < 0 || volume_offline > 0xff)
3007 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3008 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3009 } else {
edd16368 3010 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3011 this_device->offload_config = 0;
3012 this_device->offload_enabled = 0;
41ce4c35 3013 this_device->offload_to_be_enabled = 0;
a3144e0b 3014 this_device->hba_ioaccel_enabled = 0;
9846590e 3015 this_device->volume_offline = 0;
03383736 3016 this_device->queue_depth = h->nr_cmds;
283b4a9b 3017 }
edd16368 3018
0b0e1d6c
SC		 3019 if (is_OBDR_device) {
3020 /* See if this is a One-Button-Disaster-Recovery device
3021 * by looking for "$DR-10" at offset 43 in inquiry data.
3022 */
3023 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3024 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3025 strncmp(obdr_sig, OBDR_TAPE_SIG,
3026 OBDR_SIG_LEN) == 0);
3027 }
edd16368
SC		 3028 kfree(inq_buff);
3029 return 0;
3030
3031bail_out:
3032 kfree(inq_buff);
3033 return 1;
3034}
3035
9b5c48c2
SC		 3036static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3037 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3038{
3039 unsigned long flags;
3040 int rc, entry;
3041 /*
3042 * See if this device supports aborts. If we already know
3043 * the device, we already know if it supports aborts, otherwise
3044 * we have to find out if it supports aborts by trying one.
3045 */
3046 spin_lock_irqsave(&h->devlock, flags);
3047 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3048 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3049 entry >= 0 && entry < h->ndevices) {
3050 dev->supports_aborts = h->dev[entry]->supports_aborts;
3051 spin_unlock_irqrestore(&h->devlock, flags);
3052 } else {
3053 spin_unlock_irqrestore(&h->devlock, flags);
3054 dev->supports_aborts =
3055 hpsa_device_supports_aborts(h, scsi3addr);
3056 if (dev->supports_aborts < 0)
3057 dev->supports_aborts = 0;
3058 }
3059}
3060
4f4eb9f1 3061static unsigned char *ext_target_model[] = {
edd16368
SC		 3062 "MSA2012",
3063 "MSA2024",
3064 "MSA2312",
3065 "MSA2324",
fda38518 3066 "P2000 G3 SAS",
e06c8e5c 3067 "MSA 2040 SAS",
edd16368
SC		 3068 NULL,
3069};
3070
4f4eb9f1 3071static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 3072{
3073 int i;
3074
4f4eb9f1
ST		 3075 for (i = 0; ext_target_model[i]; i++)
3076 if (strncmp(device->model, ext_target_model[i],
3077 strlen(ext_target_model[i])) == 0)
edd16368
SC		 3078 return 1;
3079 return 0;
3080}
3081
3082/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 3083 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 3084 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
3085 * Logical drive target and lun are assigned at this time, but
3086 * physical device lun and target assignment are deferred (assigned
3087 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
3088 */
3089static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3090 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3091{
1f310bde
SC		 3092 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
3093
3094 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3095 /* physical device, target and lun filled in later */
edd16368 3096 if (is_hba_lunid(lunaddrbytes))
1f310bde 3097 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 3098 else
1f310bde
SC		 3099 /* defer target, lun assignment for physical devices */
3100 hpsa_set_bus_target_lun(device, 2, -1, -1);
3101 return;
3102 }
3103 /* It's a logical device */
4f4eb9f1
ST		 3104 if (is_ext_target(h, device)) {
3105 /* external target way, put logicals on bus 1
1f310bde
SC		 3106 * and match target/lun numbers box
3107 * reports, other smart array, bus 0, target 0, match lunid
3108 */
3109 hpsa_set_bus_target_lun(device,
3110 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
3111 return;
edd16368 3112 }
1f310bde 3113 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 3114}
3115
3116/*
3117 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 3118 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 3119 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
3120 * it for some reason. *tmpdevice is the target we're adding,
3121 * this_device is a pointer into the current element of currentsd[]
3122 * that we're building up in update_scsi_devices(), below.
3123 * lunzerobits is a bitmap that tracks which targets already have a
3124 * lun 0 assigned.
3125 * Returns 1 if an enclosure was added, 0 if not.
3126 */
4f4eb9f1 3127static int add_ext_target_dev(struct ctlr_info *h,
edd16368 3128 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 3129 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 3130 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 3131{
3132 unsigned char scsi3addr[8];
3133
1f310bde 3134 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 3135 return 0; /* There is already a lun 0 on this target. */
3136
3137 if (!is_logical_dev_addr_mode(lunaddrbytes))
3138 return 0; /* It's the logical targets that may lack lun 0. */
3139
4f4eb9f1
ST		 3140 if (!is_ext_target(h, tmpdevice))
3141 return 0; /* Only external target devices have this problem. */
edd16368 3142
1f310bde 3143 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 3144 return 0;
3145
c4f8a299 3146 memset(scsi3addr, 0, 8);
1f310bde 3147 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 3148 if (is_hba_lunid(scsi3addr))
3149 return 0; /* Don't add the RAID controller here. */
3150
339b2b14
SC		 3151 if (is_scsi_rev_5(h))
3152 return 0; /* p1210m doesn't need to do this. */
3153
4f4eb9f1 3154 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 3155 dev_warn(&h->pdev->dev, "Maximum number of external "
3156 "target devices exceeded. Check your hardware "
edd16368
SC		 3157 "configuration.");
3158 return 0;
3159 }
3160
0b0e1d6c 3161 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 3162 return 0;
4f4eb9f1 3163 (*n_ext_target_devs)++;
1f310bde
SC		 3164 hpsa_set_bus_target_lun(this_device,
3165 tmpdevice->bus, tmpdevice->target, 0);
9b5c48c2 3166 hpsa_update_device_supports_aborts(h, this_device, scsi3addr);
1f310bde 3167 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 3168 return 1;
3169}
3170
54b6e9e9
ST		 3171/*
3172 * Get address of physical disk used for an ioaccel2 mode command:
3173 * 1. Extract ioaccel2 handle from the command.
3174 * 2. Find a matching ioaccel2 handle from list of physical disks.
3175 * 3. Return:
3176 * 1 and set scsi3addr to address of matching physical
3177 * 0 if no matching physical disk was found.
3178 */
3179static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3180 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3181{
41ce4c35
SC		 3182 struct io_accel2_cmd *c2 =
3183 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3184 unsigned long flags;
54b6e9e9 3185 int i;
54b6e9e9 3186
41ce4c35
SC		 3187 spin_lock_irqsave(&h->devlock, flags);
3188 for (i = 0; i < h->ndevices; i++)
3189 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3190 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3191 sizeof(h->dev[i]->scsi3addr));
3192 spin_unlock_irqrestore(&h->devlock, flags);
3193 return 1;
3194 }
3195 spin_unlock_irqrestore(&h->devlock, flags);
3196 return 0;
54b6e9e9 3197}
41ce4c35 3198
edd16368
SC		 3199/*
3200 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3201 * logdev. The number of luns in physdev and logdev are returned in
3202 * *nphysicals and *nlogicals, respectively.
3203 * Returns 0 on success, -1 otherwise.
3204 */
3205static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3206 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3207 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3208{
03383736 3209 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3210 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3211 return -1;
3212 }
03383736 3213 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3214 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3215 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3216 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3217 *nphysicals = HPSA_MAX_PHYS_LUN;
3218 }
03383736 3219 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3220 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3221 return -1;
3222 }
6df1e954 3223 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3224 /* Reject Logicals in excess of our max capability. */
3225 if (*nlogicals > HPSA_MAX_LUN) {
3226 dev_warn(&h->pdev->dev,
3227 "maximum logical LUNs (%d) exceeded. "
3228 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3229 *nlogicals - HPSA_MAX_LUN);
3230 *nlogicals = HPSA_MAX_LUN;
3231 }
3232 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3233 dev_warn(&h->pdev->dev,
3234 "maximum logical + physical LUNs (%d) exceeded. "
3235 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3236 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3237 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3238 }
3239 return 0;
3240}
3241
42a91641
DB		 3242static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3243 int i, int nphysicals, int nlogicals,
a93aa1fe 3244 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3245 struct ReportLUNdata *logdev_list)
3246{
3247 /* Helper function, figure out where the LUN ID info is coming from
3248 * given index i, lists of physical and logical devices, where in
3249 * the list the raid controller is supposed to appear (first or last)
3250 */
3251
3252 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3253 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3254
3255 if (i == raid_ctlr_position)
3256 return RAID_CTLR_LUNID;
3257
3258 if (i < logicals_start)
d5b5d964
SC		 3259 return &physdev_list->LUN[i -
3260 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3261
3262 if (i < last_device)
3263 return &logdev_list->LUN[i - nphysicals -
3264 (raid_ctlr_position == 0)][0];
3265 BUG();
3266 return NULL;
3267}
3268
316b221a
SC		 3269static int hpsa_hba_mode_enabled(struct ctlr_info *h)
3270{
3271 int rc;
6e8e8088 3272 int hba_mode_enabled;
316b221a
SC		 3273 struct bmic_controller_parameters *ctlr_params;
3274 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
3275 GFP_KERNEL);
3276
3277 if (!ctlr_params)
96444fbb 3278 return -ENOMEM;
316b221a
SC		 3279 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
3280 sizeof(struct bmic_controller_parameters));
96444fbb 3281 if (rc) {
316b221a 3282 kfree(ctlr_params);
96444fbb 3283 return rc;
316b221a 3284 }
6e8e8088
JH		 3285
3286 hba_mode_enabled =
3287 ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0);
3288 kfree(ctlr_params);
3289 return hba_mode_enabled;
316b221a
SC		 3290}
3291
03383736
DB		 3292/* get physical drive ioaccel handle and queue depth */
3293static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3294 struct hpsa_scsi_dev_t *dev,
3295 u8 *lunaddrbytes,
3296 struct bmic_identify_physical_device *id_phys)
3297{
3298 int rc;
3299 struct ext_report_lun_entry *rle =
3300 (struct ext_report_lun_entry *) lunaddrbytes;
3301
3302 dev->ioaccel_handle = rle->ioaccel_handle;
a3144e0b
JH		 3303 if (PHYS_IOACCEL(lunaddrbytes) && dev->ioaccel_handle)
3304 dev->hba_ioaccel_enabled = 1;
03383736
DB		 3305 memset(id_phys, 0, sizeof(*id_phys));
3306 rc = hpsa_bmic_id_physical_device(h, lunaddrbytes,
3307 GET_BMIC_DRIVE_NUMBER(lunaddrbytes), id_phys,
3308 sizeof(*id_phys));
3309 if (!rc)
3310 /* Reserve space for FW operations */
3311#define DRIVE_CMDS_RESERVED_FOR_FW 2
3312#define DRIVE_QUEUE_DEPTH 7
3313 dev->queue_depth =
3314 le16_to_cpu(id_phys->current_queue_depth_limit) -
3315 DRIVE_CMDS_RESERVED_FOR_FW;
3316 else
3317 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
3318 atomic_set(&dev->ioaccel_cmds_out, 0);
3319}
3320
edd16368
SC		 3321static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
3322{
3323 /* the idea here is we could get notified
3324 * that some devices have changed, so we do a report
3325 * physical luns and report logical luns cmd, and adjust
3326 * our list of devices accordingly.
3327 *
3328 * The scsi3addr's of devices won't change so long as the
3329 * adapter is not reset. That means we can rescan and
3330 * tell which devices we already know about, vs. new
3331 * devices, vs. disappearing devices.
3332 */
a93aa1fe 3333 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3334 struct ReportLUNdata *logdev_list = NULL;
03383736 3335 struct bmic_identify_physical_device *id_phys = NULL;
01a02ffc
SC		 3336 u32 nphysicals = 0;
3337 u32 nlogicals = 0;
3338 u32 ndev_allocated = 0;
edd16368
SC		 3339 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3340 int ncurrent = 0;
4f4eb9f1 3341 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3342 int raid_ctlr_position;
2bbf5c7f 3343 int rescan_hba_mode;
aca4a520 3344 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3345
cfe5badc 3346 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 3347 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3348 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 3349 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 3350 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
edd16368 3351
03383736
DB		 3352 if (!currentsd || !physdev_list || !logdev_list ||
3353 !tmpdevice || !id_phys) {
edd16368
SC		 3354 dev_err(&h->pdev->dev, "out of memory\n");
3355 goto out;
3356 }
3357 memset(lunzerobits, 0, sizeof(lunzerobits));
3358
316b221a 3359 rescan_hba_mode = hpsa_hba_mode_enabled(h);
96444fbb
JH		 3360 if (rescan_hba_mode < 0)
3361 goto out;
316b221a
SC		 3362
3363 if (!h->hba_mode_enabled && rescan_hba_mode)
3364 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
3365 else if (h->hba_mode_enabled && !rescan_hba_mode)
3366 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
3367
3368 h->hba_mode_enabled = rescan_hba_mode;
3369
03383736
DB		 3370 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
3371 logdev_list, &nlogicals))
edd16368
SC		 3372 goto out;
3373
aca4a520
ST		 3374 /* We might see up to the maximum number of logical and physical disks
3375 * plus external target devices, and a device for the local RAID
3376 * controller.
edd16368 3377 */
aca4a520 3378 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3379
3380 /* Allocate the per device structures */
3381 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3382 if (i >= HPSA_MAX_DEVICES) {
3383 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3384 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3385 ndevs_to_allocate - HPSA_MAX_DEVICES);
3386 break;
3387 }
3388
edd16368
SC		 3389 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3390 if (!currentsd[i]) {
3391 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3392 __FILE__, __LINE__);
3393 goto out;
3394 }
3395 ndev_allocated++;
3396 }
3397
8645291b 3398 if (is_scsi_rev_5(h))
339b2b14
SC		 3399 raid_ctlr_position = 0;
3400 else
3401 raid_ctlr_position = nphysicals + nlogicals;
3402
edd16368 3403 /* adjust our table of devices */
4f4eb9f1 3404 n_ext_target_devs = 0;
edd16368 3405 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3406 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3407
3408 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3409 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3410 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 3411
3412 /* skip masked non-disk devices */
3413 if (MASKED_DEVICE(lunaddrbytes))
3414 if (i < nphysicals + (raid_ctlr_position == 0) &&
3415 NON_DISK_PHYS_DEV(lunaddrbytes))
3416 continue;
edd16368
SC		 3417
3418 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3419 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3420 &is_OBDR))
edd16368 3421 continue; /* skip it if we can't talk to it. */
1f310bde 3422 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 3423 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 3424 this_device = currentsd[ncurrent];
3425
3426 /*
4f4eb9f1 3427 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3428 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3429 * is nonetheless an enclosure device there. We have to
3430 * present that otherwise linux won't find anything if
3431 * there is no lun 0.
3432 */
4f4eb9f1 3433 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3434 lunaddrbytes, lunzerobits,
4f4eb9f1 3435 &n_ext_target_devs)) {
edd16368
SC		 3436 ncurrent++;
3437 this_device = currentsd[ncurrent];
3438 }
3439
3440 *this_device = *tmpdevice;
edd16368 3441
41ce4c35
SC		 3442 /* do not expose masked devices */
3443 if (MASKED_DEVICE(lunaddrbytes) &&
3444 i < nphysicals + (raid_ctlr_position == 0)) {
3445 if (h->hba_mode_enabled)
3446 dev_warn(&h->pdev->dev,
3447 "Masked physical device detected\n");
3448 this_device->expose_state = HPSA_DO_NOT_EXPOSE;
3449 } else {
3450 this_device->expose_state =
3451 HPSA_SG_ATTACH | HPSA_ULD_ATTACH;
3452 }
3453
edd16368 3454 switch (this_device->devtype) {
0b0e1d6c 3455 case TYPE_ROM:
edd16368
SC		 3456 /* We don't *really* support actual CD-ROM devices,
3457 * just "One Button Disaster Recovery" tape drive
3458 * which temporarily pretends to be a CD-ROM drive.
3459 * So we check that the device is really an OBDR tape
3460 * device by checking for "$DR-10" in bytes 43-48 of
3461 * the inquiry data.
3462 */
0b0e1d6c
SC		 3463 if (is_OBDR)
3464 ncurrent++;
edd16368
SC		 3465 break;
3466 case TYPE_DISK:
ecf418d1 3467 if (i >= nphysicals) {
316b221a
SC		 3468 ncurrent++;
3469 break;
283b4a9b 3470 }
ecf418d1
JH		 3471
3472 if (h->hba_mode_enabled)
3473 /* never use raid mapper in HBA mode */
3474 this_device->offload_enabled = 0;
3475 else if (!(h->transMethod & CFGTBL_Trans_io_accel1 ||
3476 h->transMethod & CFGTBL_Trans_io_accel2))
3477 break;
3478
3479 hpsa_get_ioaccel_drive_info(h, this_device,
3480 lunaddrbytes, id_phys);
3481 atomic_set(&this_device->ioaccel_cmds_out, 0);
3482 ncurrent++;
edd16368
SC		 3483 break;
3484 case TYPE_TAPE:
3485 case TYPE_MEDIUM_CHANGER:
3486 ncurrent++;
3487 break;
41ce4c35
SC		 3488 case TYPE_ENCLOSURE:
3489 if (h->hba_mode_enabled)
3490 ncurrent++;
3491 break;
edd16368
SC		 3492 case TYPE_RAID:
3493 /* Only present the Smartarray HBA as a RAID controller.
3494 * If it's a RAID controller other than the HBA itself
3495 * (an external RAID controller, MSA500 or similar)
3496 * don't present it.
3497 */
3498 if (!is_hba_lunid(lunaddrbytes))
3499 break;
3500 ncurrent++;
3501 break;
3502 default:
3503 break;
3504 }
cfe5badc 3505 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3506 break;
3507 }
3508 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3509out:
3510 kfree(tmpdevice);
3511 for (i = 0; i < ndev_allocated; i++)
3512 kfree(currentsd[i]);
3513 kfree(currentsd);
edd16368
SC		 3514 kfree(physdev_list);
3515 kfree(logdev_list);
03383736 3516 kfree(id_phys);
edd16368
SC		 3517}
3518
ec5cbf04
WS		 3519static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3520 struct scatterlist *sg)
3521{
3522 u64 addr64 = (u64) sg_dma_address(sg);
3523 unsigned int len = sg_dma_len(sg);
3524
3525 desc->Addr = cpu_to_le64(addr64);
3526 desc->Len = cpu_to_le32(len);
3527 desc->Ext = 0;
3528}
3529
c7ee65b3
WS		 3530/*
3531 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3532 * dma mapping and fills in the scatter gather entries of the
3533 * hpsa command, cp.
3534 */
33a2ffce 3535static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3536 struct CommandList *cp,
3537 struct scsi_cmnd *cmd)
3538{
edd16368 3539 struct scatterlist *sg;
33a2ffce
SC		 3540 int use_sg, i, sg_index, chained;
3541 struct SGDescriptor *curr_sg;
edd16368 3542
33a2ffce 3543 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3544
3545 use_sg = scsi_dma_map(cmd);
3546 if (use_sg < 0)
3547 return use_sg;
3548
3549 if (!use_sg)
3550 goto sglist_finished;
3551
33a2ffce
SC		 3552 curr_sg = cp->SG;
3553 chained = 0;
3554 sg_index = 0;
edd16368 3555 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 3556 if (i == h->max_cmd_sg_entries - 1 &&
3557 use_sg > h->max_cmd_sg_entries) {
3558 chained = 1;
3559 curr_sg = h->cmd_sg_list[cp->cmdindex];
3560 sg_index = 0;
3561 }
ec5cbf04 3562 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 3563 curr_sg++;
3564 }
ec5cbf04
WS		 3565
3566 /* Back the pointer up to the last entry and mark it as "last". */
50a0decf 3567 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3568
3569 if (use_sg + chained > h->maxSG)
3570 h->maxSG = use_sg + chained;
3571
3572 if (chained) {
3573 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3574 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3575 if (hpsa_map_sg_chain_block(h, cp)) {
3576 scsi_dma_unmap(cmd);
3577 return -1;
3578 }
33a2ffce 3579 return 0;
edd16368
SC		 3580 }
3581
3582sglist_finished:
3583
01a02ffc 3584 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 3585 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 3586 return 0;
3587}
3588
283b4a9b
SC		 3589#define IO_ACCEL_INELIGIBLE (1)
3590static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3591{
3592 int is_write = 0;
3593 u32 block;
3594 u32 block_cnt;
3595
3596 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3597 switch (cdb[0]) {
3598 case WRITE_6:
3599 case WRITE_12:
3600 is_write = 1;
3601 case READ_6:
3602 case READ_12:
3603 if (*cdb_len == 6) {
3604 block = (((u32) cdb[2]) << 8) | cdb[3];
3605 block_cnt = cdb[4];
3606 } else {
3607 BUG_ON(*cdb_len != 12);
3608 block = (((u32) cdb[2]) << 24) |
3609 (((u32) cdb[3]) << 16) |
3610 (((u32) cdb[4]) << 8) |
3611 cdb[5];
3612 block_cnt =
3613 (((u32) cdb[6]) << 24) |
3614 (((u32) cdb[7]) << 16) |
3615 (((u32) cdb[8]) << 8) |
3616 cdb[9];
3617 }
3618 if (block_cnt > 0xffff)
3619 return IO_ACCEL_INELIGIBLE;
3620
3621 cdb[0] = is_write ? WRITE_10 : READ_10;
3622 cdb[1] = 0;
3623 cdb[2] = (u8) (block >> 24);
3624 cdb[3] = (u8) (block >> 16);
3625 cdb[4] = (u8) (block >> 8);
3626 cdb[5] = (u8) (block);
3627 cdb[6] = 0;
3628 cdb[7] = (u8) (block_cnt >> 8);
3629 cdb[8] = (u8) (block_cnt);
3630 cdb[9] = 0;
3631 *cdb_len = 10;
3632 break;
3633 }
3634 return 0;
3635}
3636
c349775e 3637static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 3638 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3639 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 3640{
3641 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3642 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3643 unsigned int len;
3644 unsigned int total_len = 0;
3645 struct scatterlist *sg;
3646 u64 addr64;
3647 int use_sg, i;
3648 struct SGDescriptor *curr_sg;
3649 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3650
283b4a9b 3651 /* TODO: implement chaining support */
03383736
DB		 3652 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
3653 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3654 return IO_ACCEL_INELIGIBLE;
03383736 3655 }
283b4a9b 3656
e1f7de0c
MG		 3657 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3658
03383736
DB		 3659 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
3660 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3661 return IO_ACCEL_INELIGIBLE;
03383736 3662 }
283b4a9b 3663
e1f7de0c
MG		 3664 c->cmd_type = CMD_IOACCEL1;
3665
3666 /* Adjust the DMA address to point to the accelerated command buffer */
3667 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3668 (c->cmdindex * sizeof(*cp));
3669 BUG_ON(c->busaddr & 0x0000007F);
3670
3671 use_sg = scsi_dma_map(cmd);
03383736
DB		 3672 if (use_sg < 0) {
3673 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 3674 return use_sg;
03383736 3675 }
e1f7de0c
MG		 3676
3677 if (use_sg) {
3678 curr_sg = cp->SG;
3679 scsi_for_each_sg(cmd, sg, use_sg, i) {
3680 addr64 = (u64) sg_dma_address(sg);
3681 len = sg_dma_len(sg);
3682 total_len += len;
50a0decf
SC		 3683 curr_sg->Addr = cpu_to_le64(addr64);
3684 curr_sg->Len = cpu_to_le32(len);
3685 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 3686 curr_sg++;
3687 }
50a0decf 3688 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 3689
3690 switch (cmd->sc_data_direction) {
3691 case DMA_TO_DEVICE:
3692 control |= IOACCEL1_CONTROL_DATA_OUT;
3693 break;
3694 case DMA_FROM_DEVICE:
3695 control |= IOACCEL1_CONTROL_DATA_IN;
3696 break;
3697 case DMA_NONE:
3698 control |= IOACCEL1_CONTROL_NODATAXFER;
3699 break;
3700 default:
3701 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3702 cmd->sc_data_direction);
3703 BUG();
3704 break;
3705 }
3706 } else {
3707 control |= IOACCEL1_CONTROL_NODATAXFER;
3708 }
3709
c349775e 3710 c->Header.SGList = use_sg;
e1f7de0c 3711 /* Fill out the command structure to submit */
2b08b3e9
DB		 3712 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
3713 cp->transfer_len = cpu_to_le32(total_len);
3714 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
3715 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
3716 cp->control = cpu_to_le32(control);
283b4a9b
SC		 3717 memcpy(cp->CDB, cdb, cdb_len);
3718 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3719 /* Tag was already set at init time. */
283b4a9b 3720 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3721 return 0;
3722}
edd16368 3723
283b4a9b
SC		 3724/*
3725 * Queue a command directly to a device behind the controller using the
3726 * I/O accelerator path.
3727 */
3728static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3729 struct CommandList *c)
3730{
3731 struct scsi_cmnd *cmd = c->scsi_cmd;
3732 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3733
03383736
DB		 3734 c->phys_disk = dev;
3735
283b4a9b 3736 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 3737 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 3738}
3739
dd0e19f3
ST		 3740/*
3741 * Set encryption parameters for the ioaccel2 request
3742 */
3743static void set_encrypt_ioaccel2(struct ctlr_info *h,
3744 struct CommandList *c, struct io_accel2_cmd *cp)
3745{
3746 struct scsi_cmnd *cmd = c->scsi_cmd;
3747 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3748 struct raid_map_data *map = &dev->raid_map;
3749 u64 first_block;
3750
dd0e19f3 3751 /* Are we doing encryption on this device */
2b08b3e9 3752 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 3753 return;
3754 /* Set the data encryption key index. */
3755 cp->dekindex = map->dekindex;
3756
3757 /* Set the encryption enable flag, encoded into direction field. */
3758 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3759
3760 /* Set encryption tweak values based on logical block address
3761 * If block size is 512, tweak value is LBA.
3762 * For other block sizes, tweak is (LBA * block size)/ 512)
3763 */
3764 switch (cmd->cmnd[0]) {
3765 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3766 case WRITE_6:
3767 case READ_6:
2b08b3e9 3768 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 3769 break;
3770 case WRITE_10:
3771 case READ_10:
dd0e19f3
ST		 3772 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3773 case WRITE_12:
3774 case READ_12:
2b08b3e9 3775 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 3776 break;
3777 case WRITE_16:
3778 case READ_16:
2b08b3e9 3779 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 3780 break;
3781 default:
3782 dev_err(&h->pdev->dev,
2b08b3e9
DB		 3783 "ERROR: %s: size (0x%x) not supported for encryption\n",
3784 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 3785 BUG();
3786 break;
3787 }
2b08b3e9
DB		 3788
3789 if (le32_to_cpu(map->volume_blk_size) != 512)
3790 first_block = first_block *
3791 le32_to_cpu(map->volume_blk_size)/512;
3792
3793 cp->tweak_lower = cpu_to_le32(first_block);
3794 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 3795}
3796
c349775e
ST		 3797static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3798 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3799 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 3800{
3801 struct scsi_cmnd *cmd = c->scsi_cmd;
3802 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3803 struct ioaccel2_sg_element *curr_sg;
3804 int use_sg, i;
3805 struct scatterlist *sg;
3806 u64 addr64;
3807 u32 len;
3808 u32 total_len = 0;
3809
03383736
DB		 3810 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
3811 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3812 return IO_ACCEL_INELIGIBLE;
03383736 3813 }
c349775e 3814
03383736
DB		 3815 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
3816 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3817 return IO_ACCEL_INELIGIBLE;
03383736
DB		 3818 }
3819
c349775e
ST		 3820 c->cmd_type = CMD_IOACCEL2;
3821 /* Adjust the DMA address to point to the accelerated command buffer */
3822 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3823 (c->cmdindex * sizeof(*cp));
3824 BUG_ON(c->busaddr & 0x0000007F);
3825
3826 memset(cp, 0, sizeof(*cp));
3827 cp->IU_type = IOACCEL2_IU_TYPE;
3828
3829 use_sg = scsi_dma_map(cmd);
03383736
DB		 3830 if (use_sg < 0) {
3831 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3832 return use_sg;
03383736 3833 }
c349775e
ST		 3834
3835 if (use_sg) {
3836 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
3837 curr_sg = cp->sg;
3838 scsi_for_each_sg(cmd, sg, use_sg, i) {
3839 addr64 = (u64) sg_dma_address(sg);
3840 len = sg_dma_len(sg);
3841 total_len += len;
3842 curr_sg->address = cpu_to_le64(addr64);
3843 curr_sg->length = cpu_to_le32(len);
3844 curr_sg->reserved[0] = 0;
3845 curr_sg->reserved[1] = 0;
3846 curr_sg->reserved[2] = 0;
3847 curr_sg->chain_indicator = 0;
3848 curr_sg++;
3849 }
3850
3851 switch (cmd->sc_data_direction) {
3852 case DMA_TO_DEVICE:
dd0e19f3
ST		 3853 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3854 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3855 break;
3856 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3857 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3858 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3859 break;
3860 case DMA_NONE:
dd0e19f3
ST		 3861 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3862 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3863 break;
3864 default:
3865 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3866 cmd->sc_data_direction);
3867 BUG();
3868 break;
3869 }
3870 } else {
dd0e19f3
ST		 3871 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3872 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3873 }
dd0e19f3
ST		 3874
3875 /* Set encryption parameters, if necessary */
3876 set_encrypt_ioaccel2(h, c, cp);
3877
2b08b3e9 3878 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 3879 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 3880 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e
ST		 3881
3882 /* fill in sg elements */
3883 cp->sg_count = (u8) use_sg;
3884
3885 cp->data_len = cpu_to_le32(total_len);
3886 cp->err_ptr = cpu_to_le64(c->busaddr +
3887 offsetof(struct io_accel2_cmd, error_data));
50a0decf 3888 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e
ST		 3889
3890 enqueue_cmd_and_start_io(h, c);
3891 return 0;
3892}
3893
3894/*
3895 * Queue a command to the correct I/O accelerator path.
3896 */
3897static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3898 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3899 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 3900{
03383736
DB		 3901 /* Try to honor the device's queue depth */
3902 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
3903 phys_disk->queue_depth) {
3904 atomic_dec(&phys_disk->ioaccel_cmds_out);
3905 return IO_ACCEL_INELIGIBLE;
3906 }
c349775e
ST		 3907 if (h->transMethod & CFGTBL_Trans_io_accel1)
3908 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 3909 cdb, cdb_len, scsi3addr,
3910 phys_disk);
c349775e
ST		 3911 else
3912 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 3913 cdb, cdb_len, scsi3addr,
3914 phys_disk);
c349775e
ST		 3915}
3916
6b80b18f
ST		 3917static void raid_map_helper(struct raid_map_data *map,
3918 int offload_to_mirror, u32 *map_index, u32 *current_group)
3919{
3920 if (offload_to_mirror == 0) {
3921 /* use physical disk in the first mirrored group. */
2b08b3e9 3922 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3923 return;
3924 }
3925 do {
3926 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 3927 *current_group = *map_index /
3928 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3929 if (offload_to_mirror == *current_group)
3930 continue;
2b08b3e9 3931 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 3932 /* select map index from next group */
2b08b3e9 3933 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3934 (*current_group)++;
3935 } else {
3936 /* select map index from first group */
2b08b3e9 3937 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3938 *current_group = 0;
3939 }
3940 } while (offload_to_mirror != *current_group);
3941}
3942
283b4a9b
SC		 3943/*
3944 * Attempt to perform offload RAID mapping for a logical volume I/O.
3945 */
3946static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3947 struct CommandList *c)
3948{
3949 struct scsi_cmnd *cmd = c->scsi_cmd;
3950 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3951 struct raid_map_data *map = &dev->raid_map;
3952 struct raid_map_disk_data *dd = &map->data[0];
3953 int is_write = 0;
3954 u32 map_index;
3955 u64 first_block, last_block;
3956 u32 block_cnt;
3957 u32 blocks_per_row;
3958 u64 first_row, last_row;
3959 u32 first_row_offset, last_row_offset;
3960 u32 first_column, last_column;
6b80b18f
ST		 3961 u64 r0_first_row, r0_last_row;
3962 u32 r5or6_blocks_per_row;
3963 u64 r5or6_first_row, r5or6_last_row;
3964 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3965 u32 r5or6_first_column, r5or6_last_column;
3966 u32 total_disks_per_row;
3967 u32 stripesize;
3968 u32 first_group, last_group, current_group;
283b4a9b
SC		 3969 u32 map_row;
3970 u32 disk_handle;
3971 u64 disk_block;
3972 u32 disk_block_cnt;
3973 u8 cdb[16];
3974 u8 cdb_len;
2b08b3e9 3975 u16 strip_size;
283b4a9b
SC		 3976#if BITS_PER_LONG == 32
3977 u64 tmpdiv;
3978#endif
6b80b18f 3979 int offload_to_mirror;
283b4a9b 3980
283b4a9b
SC		 3981 /* check for valid opcode, get LBA and block count */
3982 switch (cmd->cmnd[0]) {
3983 case WRITE_6:
3984 is_write = 1;
3985 case READ_6:
3986 first_block =
3987 (((u64) cmd->cmnd[2]) << 8) |
3988 cmd->cmnd[3];
3989 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 3990 if (block_cnt == 0)
3991 block_cnt = 256;
283b4a9b
SC		 3992 break;
3993 case WRITE_10:
3994 is_write = 1;
3995 case READ_10:
3996 first_block =
3997 (((u64) cmd->cmnd[2]) << 24) |
3998 (((u64) cmd->cmnd[3]) << 16) |
3999 (((u64) cmd->cmnd[4]) << 8) |
4000 cmd->cmnd[5];
4001 block_cnt =
4002 (((u32) cmd->cmnd[7]) << 8) |
4003 cmd->cmnd[8];
4004 break;
4005 case WRITE_12:
4006 is_write = 1;
4007 case READ_12:
4008 first_block =
4009 (((u64) cmd->cmnd[2]) << 24) |
4010 (((u64) cmd->cmnd[3]) << 16) |
4011 (((u64) cmd->cmnd[4]) << 8) |
4012 cmd->cmnd[5];
4013 block_cnt =
4014 (((u32) cmd->cmnd[6]) << 24) |
4015 (((u32) cmd->cmnd[7]) << 16) |
4016 (((u32) cmd->cmnd[8]) << 8) |
4017 cmd->cmnd[9];
4018 break;
4019 case WRITE_16:
4020 is_write = 1;
4021 case READ_16:
4022 first_block =
4023 (((u64) cmd->cmnd[2]) << 56) |
4024 (((u64) cmd->cmnd[3]) << 48) |
4025 (((u64) cmd->cmnd[4]) << 40) |
4026 (((u64) cmd->cmnd[5]) << 32) |
4027 (((u64) cmd->cmnd[6]) << 24) |
4028 (((u64) cmd->cmnd[7]) << 16) |
4029 (((u64) cmd->cmnd[8]) << 8) |
4030 cmd->cmnd[9];
4031 block_cnt =
4032 (((u32) cmd->cmnd[10]) << 24) |
4033 (((u32) cmd->cmnd[11]) << 16) |
4034 (((u32) cmd->cmnd[12]) << 8) |
4035 cmd->cmnd[13];
4036 break;
4037 default:
4038 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4039 }
283b4a9b
SC		 4040 last_block = first_block + block_cnt - 1;
4041
4042 /* check for write to non-RAID-0 */
4043 if (is_write && dev->raid_level != 0)
4044 return IO_ACCEL_INELIGIBLE;
4045
4046 /* check for invalid block or wraparound */
2b08b3e9
DB		 4047 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4048 last_block < first_block)
283b4a9b
SC		 4049 return IO_ACCEL_INELIGIBLE;
4050
4051 /* calculate stripe information for the request */
2b08b3e9
DB		 4052 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4053 le16_to_cpu(map->strip_size);
4054 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4055#if BITS_PER_LONG == 32
4056 tmpdiv = first_block;
4057 (void) do_div(tmpdiv, blocks_per_row);
4058 first_row = tmpdiv;
4059 tmpdiv = last_block;
4060 (void) do_div(tmpdiv, blocks_per_row);
4061 last_row = tmpdiv;
4062 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4063 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4064 tmpdiv = first_row_offset;
2b08b3e9 4065 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4066 first_column = tmpdiv;
4067 tmpdiv = last_row_offset;
2b08b3e9 4068 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4069 last_column = tmpdiv;
4070#else
4071 first_row = first_block / blocks_per_row;
4072 last_row = last_block / blocks_per_row;
4073 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4074 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4075 first_column = first_row_offset / strip_size;
4076 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4077#endif
4078
4079 /* if this isn't a single row/column then give to the controller */
4080 if ((first_row != last_row) || (first_column != last_column))
4081 return IO_ACCEL_INELIGIBLE;
4082
4083 /* proceeding with driver mapping */
2b08b3e9
DB		 4084 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4085 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4086 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4087 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4088 map_index = (map_row * total_disks_per_row) + first_column;
4089
4090 switch (dev->raid_level) {
4091 case HPSA_RAID_0:
4092 break; /* nothing special to do */
4093 case HPSA_RAID_1:
4094 /* Handles load balance across RAID 1 members.
4095 * (2-drive R1 and R10 with even # of drives.)
4096 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4097 */
2b08b3e9 4098 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4099 if (dev->offload_to_mirror)
2b08b3e9 4100 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4101 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4102 break;
4103 case HPSA_RAID_ADM:
4104 /* Handles N-way mirrors (R1-ADM)
4105 * and R10 with # of drives divisible by 3.)
4106 */
2b08b3e9 4107 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4108
4109 offload_to_mirror = dev->offload_to_mirror;
4110 raid_map_helper(map, offload_to_mirror,
4111 &map_index, &current_group);
4112 /* set mirror group to use next time */
4113 offload_to_mirror =
2b08b3e9
DB		 4114 (offload_to_mirror >=
4115 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4116 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4117 dev->offload_to_mirror = offload_to_mirror;
4118 /* Avoid direct use of dev->offload_to_mirror within this
4119 * function since multiple threads might simultaneously
4120 * increment it beyond the range of dev->layout_map_count -1.
4121 */
4122 break;
4123 case HPSA_RAID_5:
4124 case HPSA_RAID_6:
2b08b3e9 4125 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4126 break;
4127
4128 /* Verify first and last block are in same RAID group */
4129 r5or6_blocks_per_row =
2b08b3e9
DB		 4130 le16_to_cpu(map->strip_size) *
4131 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4132 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4133 stripesize = r5or6_blocks_per_row *
4134 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4135#if BITS_PER_LONG == 32
4136 tmpdiv = first_block;
4137 first_group = do_div(tmpdiv, stripesize);
4138 tmpdiv = first_group;
4139 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4140 first_group = tmpdiv;
4141 tmpdiv = last_block;
4142 last_group = do_div(tmpdiv, stripesize);
4143 tmpdiv = last_group;
4144 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4145 last_group = tmpdiv;
4146#else
4147 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4148 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4149#endif
000ff7c2 4150 if (first_group != last_group)
6b80b18f
ST		 4151 return IO_ACCEL_INELIGIBLE;
4152
4153 /* Verify request is in a single row of RAID 5/6 */
4154#if BITS_PER_LONG == 32
4155 tmpdiv = first_block;
4156 (void) do_div(tmpdiv, stripesize);
4157 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4158 tmpdiv = last_block;
4159 (void) do_div(tmpdiv, stripesize);
4160 r5or6_last_row = r0_last_row = tmpdiv;
4161#else
4162 first_row = r5or6_first_row = r0_first_row =
4163 first_block / stripesize;
4164 r5or6_last_row = r0_last_row = last_block / stripesize;
4165#endif
4166 if (r5or6_first_row != r5or6_last_row)
4167 return IO_ACCEL_INELIGIBLE;
4168
4169
4170 /* Verify request is in a single column */
4171#if BITS_PER_LONG == 32
4172 tmpdiv = first_block;
4173 first_row_offset = do_div(tmpdiv, stripesize);
4174 tmpdiv = first_row_offset;
4175 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4176 r5or6_first_row_offset = first_row_offset;
4177 tmpdiv = last_block;
4178 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4179 tmpdiv = r5or6_last_row_offset;
4180 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4181 tmpdiv = r5or6_first_row_offset;
4182 (void) do_div(tmpdiv, map->strip_size);
4183 first_column = r5or6_first_column = tmpdiv;
4184 tmpdiv = r5or6_last_row_offset;
4185 (void) do_div(tmpdiv, map->strip_size);
4186 r5or6_last_column = tmpdiv;
4187#else
4188 first_row_offset = r5or6_first_row_offset =
4189 (u32)((first_block % stripesize) %
4190 r5or6_blocks_per_row);
4191
4192 r5or6_last_row_offset =
4193 (u32)((last_block % stripesize) %
4194 r5or6_blocks_per_row);
4195
4196 first_column = r5or6_first_column =
2b08b3e9 4197 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4198 r5or6_last_column =
2b08b3e9 4199 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4200#endif
4201 if (r5or6_first_column != r5or6_last_column)
4202 return IO_ACCEL_INELIGIBLE;
4203
4204 /* Request is eligible */
4205 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4206 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4207
4208 map_index = (first_group *
2b08b3e9 4209 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4210 (map_row * total_disks_per_row) + first_column;
4211 break;
4212 default:
4213 return IO_ACCEL_INELIGIBLE;
283b4a9b 4214 }
6b80b18f 4215
07543e0c
SC		 4216 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4217 return IO_ACCEL_INELIGIBLE;
4218
03383736
DB		 4219 c->phys_disk = dev->phys_disk[map_index];
4220
283b4a9b 4221 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 4222 disk_block = le64_to_cpu(map->disk_starting_blk) +
4223 first_row * le16_to_cpu(map->strip_size) +
4224 (first_row_offset - first_column *
4225 le16_to_cpu(map->strip_size));
283b4a9b
SC		 4226 disk_block_cnt = block_cnt;
4227
4228 /* handle differing logical/physical block sizes */
4229 if (map->phys_blk_shift) {
4230 disk_block <<= map->phys_blk_shift;
4231 disk_block_cnt <<= map->phys_blk_shift;
4232 }
4233 BUG_ON(disk_block_cnt > 0xffff);
4234
4235 /* build the new CDB for the physical disk I/O */
4236 if (disk_block > 0xffffffff) {
4237 cdb[0] = is_write ? WRITE_16 : READ_16;
4238 cdb[1] = 0;
4239 cdb[2] = (u8) (disk_block >> 56);
4240 cdb[3] = (u8) (disk_block >> 48);
4241 cdb[4] = (u8) (disk_block >> 40);
4242 cdb[5] = (u8) (disk_block >> 32);
4243 cdb[6] = (u8) (disk_block >> 24);
4244 cdb[7] = (u8) (disk_block >> 16);
4245 cdb[8] = (u8) (disk_block >> 8);
4246 cdb[9] = (u8) (disk_block);
4247 cdb[10] = (u8) (disk_block_cnt >> 24);
4248 cdb[11] = (u8) (disk_block_cnt >> 16);
4249 cdb[12] = (u8) (disk_block_cnt >> 8);
4250 cdb[13] = (u8) (disk_block_cnt);
4251 cdb[14] = 0;
4252 cdb[15] = 0;
4253 cdb_len = 16;
4254 } else {
4255 cdb[0] = is_write ? WRITE_10 : READ_10;
4256 cdb[1] = 0;
4257 cdb[2] = (u8) (disk_block >> 24);
4258 cdb[3] = (u8) (disk_block >> 16);
4259 cdb[4] = (u8) (disk_block >> 8);
4260 cdb[5] = (u8) (disk_block);
4261 cdb[6] = 0;
4262 cdb[7] = (u8) (disk_block_cnt >> 8);
4263 cdb[8] = (u8) (disk_block_cnt);
4264 cdb[9] = 0;
4265 cdb_len = 10;
4266 }
4267 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 4268 dev->scsi3addr,
4269 dev->phys_disk[map_index]);
283b4a9b
SC		 4270}
4271
25163bd5
WS		 4272/*
4273 * Submit commands down the "normal" RAID stack path
4274 * All callers to hpsa_ciss_submit must check lockup_detected
4275 * beforehand, before (opt.) and after calling cmd_alloc
4276 */
574f05d3
SC		 4277static int hpsa_ciss_submit(struct ctlr_info *h,
4278 struct CommandList *c, struct scsi_cmnd *cmd,
4279 unsigned char scsi3addr[])
edd16368 4280{
edd16368 4281 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 4282 c->cmd_type = CMD_SCSI;
4283 c->scsi_cmd = cmd;
4284 c->Header.ReplyQueue = 0; /* unused in simple mode */
4285 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 4286 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 4287
4288 /* Fill in the request block... */
4289
4290 c->Request.Timeout = 0;
edd16368
SC		 4291 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4292 c->Request.CDBLen = cmd->cmd_len;
4293 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 4294 switch (cmd->sc_data_direction) {
4295 case DMA_TO_DEVICE:
a505b86f
SC		 4296 c->Request.type_attr_dir =
4297 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 4298 break;
4299 case DMA_FROM_DEVICE:
a505b86f
SC		 4300 c->Request.type_attr_dir =
4301 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 4302 break;
4303 case DMA_NONE:
a505b86f
SC		 4304 c->Request.type_attr_dir =
4305 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 4306 break;
4307 case DMA_BIDIRECTIONAL:
4308 /* This can happen if a buggy application does a scsi passthru
4309 * and sets both inlen and outlen to non-zero. ( see
4310 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4311 */
4312
a505b86f
SC		 4313 c->Request.type_attr_dir =
4314 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 4315 /* This is technically wrong, and hpsa controllers should
4316 * reject it with CMD_INVALID, which is the most correct
4317 * response, but non-fibre backends appear to let it
4318 * slide by, and give the same results as if this field
4319 * were set correctly. Either way is acceptable for
4320 * our purposes here.
4321 */
4322
4323 break;
4324
4325 default:
4326 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4327 cmd->sc_data_direction);
4328 BUG();
4329 break;
4330 }
4331
33a2ffce 4332 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 4333 cmd_free(h, c);
4334 return SCSI_MLQUEUE_HOST_BUSY;
4335 }
4336 enqueue_cmd_and_start_io(h, c);
4337 /* the cmd'll come back via intr handler in complete_scsi_command() */
4338 return 0;
4339}
4340
360c73bd
SC		 4341static void hpsa_cmd_init(struct ctlr_info *h, int index,
4342 struct CommandList *c)
4343{
4344 dma_addr_t cmd_dma_handle, err_dma_handle;
4345
4346 /* Zero out all of commandlist except the last field, refcount */
4347 memset(c, 0, offsetof(struct CommandList, refcount));
4348 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
4349 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4350 c->err_info = h->errinfo_pool + index;
4351 memset(c->err_info, 0, sizeof(*c->err_info));
4352 err_dma_handle = h->errinfo_pool_dhandle
4353 + index * sizeof(*c->err_info);
4354 c->cmdindex = index;
4355 c->busaddr = (u32) cmd_dma_handle;
4356 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4357 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
4358 c->h = h;
4359}
4360
4361static void hpsa_preinitialize_commands(struct ctlr_info *h)
4362{
4363 int i;
4364
4365 for (i = 0; i < h->nr_cmds; i++) {
4366 struct CommandList *c = h->cmd_pool + i;
4367
4368 hpsa_cmd_init(h, i, c);
4369 atomic_set(&c->refcount, 0);
4370 }
4371}
4372
4373static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
4374 struct CommandList *c)
4375{
4376 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4377
4378 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4379 memset(c->err_info, 0, sizeof(*c->err_info));
4380 c->busaddr = (u32) cmd_dma_handle;
4381}
4382
592a0ad5
WS		 4383static int hpsa_ioaccel_submit(struct ctlr_info *h,
4384 struct CommandList *c, struct scsi_cmnd *cmd,
4385 unsigned char *scsi3addr)
4386{
4387 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4388 int rc = IO_ACCEL_INELIGIBLE;
4389
4390 cmd->host_scribble = (unsigned char *) c;
4391
4392 if (dev->offload_enabled) {
4393 hpsa_cmd_init(h, c->cmdindex, c);
4394 c->cmd_type = CMD_SCSI;
4395 c->scsi_cmd = cmd;
4396 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4397 if (rc < 0) /* scsi_dma_map failed. */
4398 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 4399 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 4400 hpsa_cmd_init(h, c->cmdindex, c);
4401 c->cmd_type = CMD_SCSI;
4402 c->scsi_cmd = cmd;
4403 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4404 if (rc < 0) /* scsi_dma_map failed. */
4405 rc = SCSI_MLQUEUE_HOST_BUSY;
4406 }
4407 return rc;
4408}
4409
080ef1cc
DB		 4410static void hpsa_command_resubmit_worker(struct work_struct *work)
4411{
4412 struct scsi_cmnd *cmd;
4413 struct hpsa_scsi_dev_t *dev;
4414 struct CommandList *c =
4415 container_of(work, struct CommandList, work);
4416
4417 cmd = c->scsi_cmd;
4418 dev = cmd->device->hostdata;
4419 if (!dev) {
4420 cmd->result = DID_NO_CONNECT << 16;
592a0ad5 4421 cmd_free(c->h, c);
080ef1cc
DB		 4422 cmd->scsi_done(cmd);
4423 return;
4424 }
592a0ad5
WS		 4425 if (c->cmd_type == CMD_IOACCEL2) {
4426 struct ctlr_info *h = c->h;
4427 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
4428 int rc;
4429
4430 if (c2->error_data.serv_response ==
4431 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
4432 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
4433 if (rc == 0)
4434 return;
4435 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4436 /*
4437 * If we get here, it means dma mapping failed.
4438 * Try again via scsi mid layer, which will
4439 * then get SCSI_MLQUEUE_HOST_BUSY.
4440 */
4441 cmd->result = DID_IMM_RETRY << 16;
4442 cmd->scsi_done(cmd);
4443 cmd_free(h, c); /* FIX-ME: on merge, change
4444 * to cmd_tagged_free() and
4445 * ultimately to
4446 * hpsa_cmd_free_and_done(). */
4447 return;
4448 }
4449 /* else, fall thru and resubmit down CISS path */
4450 }
4451 }
360c73bd 4452 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 4453 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4454 /*
4455 * If we get here, it means dma mapping failed. Try
4456 * again via scsi mid layer, which will then get
4457 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 4458 *
4459 * hpsa_ciss_submit will have already freed c
4460 * if it encountered a dma mapping failure.
080ef1cc
DB		 4461 */
4462 cmd->result = DID_IMM_RETRY << 16;
4463 cmd->scsi_done(cmd);
4464 }
4465}
4466
574f05d3
SC		 4467/* Running in struct Scsi_Host->host_lock less mode */
4468static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4469{
4470 struct ctlr_info *h;
4471 struct hpsa_scsi_dev_t *dev;
4472 unsigned char scsi3addr[8];
4473 struct CommandList *c;
4474 int rc = 0;
4475
4476 /* Get the ptr to our adapter structure out of cmd->host. */
4477 h = sdev_to_hba(cmd->device);
4478 dev = cmd->device->hostdata;
4479 if (!dev) {
4480 cmd->result = DID_NO_CONNECT << 16;
4481 cmd->scsi_done(cmd);
4482 return 0;
4483 }
4484 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
4485
4486 if (unlikely(lockup_detected(h))) {
25163bd5 4487 cmd->result = DID_NO_CONNECT << 16;
574f05d3
SC		 4488 cmd->scsi_done(cmd);
4489 return 0;
4490 }
4491 c = cmd_alloc(h);
4492 if (c == NULL) { /* trouble... */
4493 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
4494 return SCSI_MLQUEUE_HOST_BUSY;
4495 }
407863cb 4496 if (unlikely(lockup_detected(h))) {
25163bd5 4497 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 4498 cmd_free(h, c);
4499 cmd->scsi_done(cmd);
4500 return 0;
4501 }
574f05d3 4502
407863cb
SC		 4503 /*
4504 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 4505 * Retries always go down the normal I/O path.
4506 */
4507 if (likely(cmd->retries == 0 &&
4508 cmd->request->cmd_type == REQ_TYPE_FS &&
4509 h->acciopath_status)) {
592a0ad5
WS		 4510 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
4511 if (rc == 0)
4512 return 0;
4513 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4514 cmd_free(h, c); /* FIX-ME: on merge, change to
4515 * cmd_tagged_free(), and ultimately
4516 * to hpsa_cmd_resolve_and_free(). */
4517 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 4518 }
4519 }
4520 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4521}
4522
8ebc9248 4523static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 4524{
4525 unsigned long flags;
4526
8ebc9248
WS		 4527 spin_lock_irqsave(&h->scan_lock, flags);
4528 h->scan_finished = 1;
4529 wake_up_all(&h->scan_wait_queue);
4530 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 4531}
4532
a08a8471
SC		 4533static void hpsa_scan_start(struct Scsi_Host *sh)
4534{
4535 struct ctlr_info *h = shost_to_hba(sh);
4536 unsigned long flags;
4537
8ebc9248
WS		 4538 /*
4539 * Don't let rescans be initiated on a controller known to be locked
4540 * up. If the controller locks up *during* a rescan, that thread is
4541 * probably hosed, but at least we can prevent new rescan threads from
4542 * piling up on a locked up controller.
4543 */
4544 if (unlikely(lockup_detected(h)))
4545 return hpsa_scan_complete(h);
5f389360 4546
a08a8471
SC		 4547 /* wait until any scan already in progress is finished. */
4548 while (1) {
4549 spin_lock_irqsave(&h->scan_lock, flags);
4550 if (h->scan_finished)
4551 break;
4552 spin_unlock_irqrestore(&h->scan_lock, flags);
4553 wait_event(h->scan_wait_queue, h->scan_finished);
4554 /* Note: We don't need to worry about a race between this
4555 * thread and driver unload because the midlayer will
4556 * have incremented the reference count, so unload won't
4557 * happen if we're in here.
4558 */
4559 }
4560 h->scan_finished = 0; /* mark scan as in progress */
4561 spin_unlock_irqrestore(&h->scan_lock, flags);
4562
8ebc9248
WS		 4563 if (unlikely(lockup_detected(h)))
4564 return hpsa_scan_complete(h);
5f389360 4565
a08a8471
SC		 4566 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4567
8ebc9248 4568 hpsa_scan_complete(h);
a08a8471
SC		 4569}
4570
7c0a0229
DB		 4571static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4572{
03383736
DB		 4573 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
4574
4575 if (!logical_drive)
4576 return -ENODEV;
7c0a0229
DB		 4577
4578 if (qdepth < 1)
4579 qdepth = 1;
03383736
DB		 4580 else if (qdepth > logical_drive->queue_depth)
4581 qdepth = logical_drive->queue_depth;
4582
4583 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 4584}
4585
a08a8471
SC		 4586static int hpsa_scan_finished(struct Scsi_Host *sh,
4587 unsigned long elapsed_time)
4588{
4589 struct ctlr_info *h = shost_to_hba(sh);
4590 unsigned long flags;
4591 int finished;
4592
4593 spin_lock_irqsave(&h->scan_lock, flags);
4594 finished = h->scan_finished;
4595 spin_unlock_irqrestore(&h->scan_lock, flags);
4596 return finished;
4597}
4598
edd16368
SC		 4599static void hpsa_unregister_scsi(struct ctlr_info *h)
4600{
4601 /* we are being forcibly unloaded, and may not refuse. */
4602 scsi_remove_host(h->scsi_host);
4603 scsi_host_put(h->scsi_host);
4604 h->scsi_host = NULL;
4605}
4606
4607static int hpsa_register_scsi(struct ctlr_info *h)
4608{
b705690d
SC		 4609 struct Scsi_Host *sh;
4610 int error;
edd16368 4611
b705690d
SC		 4612 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4613 if (sh == NULL)
4614 goto fail;
4615
4616 sh->io_port = 0;
4617 sh->n_io_port = 0;
4618 sh->this_id = -1;
4619 sh->max_channel = 3;
4620 sh->max_cmd_len = MAX_COMMAND_SIZE;
4621 sh->max_lun = HPSA_MAX_LUN;
4622 sh->max_id = HPSA_MAX_LUN;
41ce4c35 4623 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 4624 sh->cmd_per_lun = sh->can_queue;
b705690d
SC		 4625 sh->sg_tablesize = h->maxsgentries;
4626 h->scsi_host = sh;
4627 sh->hostdata[0] = (unsigned long) h;
4628 sh->irq = h->intr[h->intr_mode];
4629 sh->unique_id = sh->irq;
4630 error = scsi_add_host(sh, &h->pdev->dev);
4631 if (error)
4632 goto fail_host_put;
4633 scsi_scan_host(sh);
4634 return 0;
4635
4636 fail_host_put:
4637 dev_err(&h->pdev->dev, "%s: scsi_add_host"
4638 " failed for controller %d\n", __func__, h->ctlr);
4639 scsi_host_put(sh);
4640 return error;
4641 fail:
4642 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
4643 " failed for controller %d\n", __func__, h->ctlr);
4644 return -ENOMEM;
edd16368
SC		 4645}
4646
4647static int wait_for_device_to_become_ready(struct ctlr_info *h,
4648 unsigned char lunaddr[])
4649{
8919358e 4650 int rc;
edd16368
SC		 4651 int count = 0;
4652 int waittime = 1; /* seconds */
4653 struct CommandList *c;
4654
45fcb86e 4655 c = cmd_alloc(h);
edd16368
SC		 4656 if (!c) {
4657 dev_warn(&h->pdev->dev, "out of memory in "
4658 "wait_for_device_to_become_ready.\n");
4659 return IO_ERROR;
4660 }
4661
4662 /* Send test unit ready until device ready, or give up. */
4663 while (count < HPSA_TUR_RETRY_LIMIT) {
4664
4665 /* Wait for a bit. do this first, because if we send
4666 * the TUR right away, the reset will just abort it.
4667 */
4668 msleep(1000 * waittime);
4669 count++;
8919358e 4670 rc = 0; /* Device ready. */
edd16368
SC		 4671
4672 /* Increase wait time with each try, up to a point. */
4673 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
4674 waittime = waittime * 2;
4675
a2dac136
SC		 4676 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4677 (void) fill_cmd(c, TEST_UNIT_READY, h,
4678 NULL, 0, 0, lunaddr, TYPE_CMD);
25163bd5
WS		 4679 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
4680 NO_TIMEOUT);
4681 if (rc)
4682 goto do_it_again;
edd16368
SC		 4683 /* no unmap needed here because no data xfer. */
4684
4685 if (c->err_info->CommandStatus == CMD_SUCCESS)
4686 break;
4687
4688 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4689 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
4690 (c->err_info->SenseInfo[2] == NO_SENSE ||
4691 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
4692 break;
25163bd5 4693do_it_again:
edd16368
SC		 4694 dev_warn(&h->pdev->dev, "waiting %d secs "
4695 "for device to become ready.\n", waittime);
4696 rc = 1; /* device not ready. */
4697 }
4698
4699 if (rc)
4700 dev_warn(&h->pdev->dev, "giving up on device.\n");
4701 else
4702 dev_warn(&h->pdev->dev, "device is ready.\n");
4703
45fcb86e 4704 cmd_free(h, c);
edd16368
SC		 4705 return rc;
4706}
4707
4708/* Need at least one of these error handlers to keep ../scsi/hosts.c from
4709 * complaining. Doing a host- or bus-reset can't do anything good here.
4710 */
4711static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
4712{
4713 int rc;
4714 struct ctlr_info *h;
4715 struct hpsa_scsi_dev_t *dev;
4716
4717 /* find the controller to which the command to be aborted was sent */
4718 h = sdev_to_hba(scsicmd->device);
4719 if (h == NULL) /* paranoia */
4720 return FAILED;
e345893b
DB		 4721
4722 if (lockup_detected(h))
4723 return FAILED;
4724
edd16368
SC		 4725 dev = scsicmd->device->hostdata;
4726 if (!dev) {
4727 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
4728 "device lookup failed.\n");
4729 return FAILED;
4730 }
25163bd5
WS		 4731
4732 /* if controller locked up, we can guarantee command won't complete */
4733 if (lockup_detected(h)) {
4734 dev_warn(&h->pdev->dev,
4735 "scsi %d:%d:%d:%d RESET FAILED, lockup detected\n",
4736 h->scsi_host->host_no, dev->bus, dev->target,
4737 dev->lun);
4738 return FAILED;
4739 }
4740
4741 /* this reset request might be the result of a lockup; check */
4742 if (detect_controller_lockup(h)) {
4743 dev_warn(&h->pdev->dev,
4744 "scsi %d:%d:%d:%d RESET FAILED, new lockup detected\n",
4745 h->scsi_host->host_no, dev->bus, dev->target,
4746 dev->lun);
4747 return FAILED;
4748 }
4749
4750 hpsa_show_dev_msg(KERN_WARNING, h, dev, "resetting");
4751
edd16368 4752 /* send a reset to the SCSI LUN which the command was sent to */
25163bd5
WS		 4753 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN,
4754 DEFAULT_REPLY_QUEUE);
edd16368
SC		 4755 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
4756 return SUCCESS;
4757
25163bd5
WS		 4758 dev_warn(&h->pdev->dev,
4759 "scsi %d:%d:%d:%d reset failed\n",
4760 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368
SC		 4761 return FAILED;
4762}
4763
6cba3f19
SC		 4764static void swizzle_abort_tag(u8 *tag)
4765{
4766 u8 original_tag[8];
4767
4768 memcpy(original_tag, tag, 8);
4769 tag[0] = original_tag[3];
4770 tag[1] = original_tag[2];
4771 tag[2] = original_tag[1];
4772 tag[3] = original_tag[0];
4773 tag[4] = original_tag[7];
4774 tag[5] = original_tag[6];
4775 tag[6] = original_tag[5];
4776 tag[7] = original_tag[4];
4777}
4778
17eb87d2 4779static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 4780 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 4781{
2b08b3e9 4782 u64 tag;
17eb87d2
ST		 4783 if (c->cmd_type == CMD_IOACCEL1) {
4784 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4785 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 4786 tag = le64_to_cpu(cm1->tag);
4787 *tagupper = cpu_to_le32(tag >> 32);
4788 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 4789 return;
4790 }
4791 if (c->cmd_type == CMD_IOACCEL2) {
4792 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4793 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4794 /* upper tag not used in ioaccel2 mode */
4795 memset(tagupper, 0, sizeof(*tagupper));
4796 *taglower = cm2->Tag;
54b6e9e9 4797 return;
17eb87d2 4798 }
2b08b3e9
DB		 4799 tag = le64_to_cpu(c->Header.tag);
4800 *tagupper = cpu_to_le32(tag >> 32);
4801 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 4802}
4803
75167d2c 4804static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 4805 struct CommandList *abort, int reply_queue)
75167d2c
SC		 4806{
4807 int rc = IO_OK;
4808 struct CommandList *c;
4809 struct ErrorInfo *ei;
2b08b3e9 4810 __le32 tagupper, taglower;
75167d2c 4811
45fcb86e 4812 c = cmd_alloc(h);
75167d2c 4813 if (c == NULL) { /* trouble... */
45fcb86e 4814 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
75167d2c
SC		 4815 return -ENOMEM;
4816 }
4817
a2dac136 4818 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 4819 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 4820 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 4821 if (h->needs_abort_tags_swizzled)
6cba3f19 4822 swizzle_abort_tag(&c->Request.CDB[4]);
25163bd5 4823 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
17eb87d2 4824 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 4825 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 4826 __func__, tagupper, taglower);
75167d2c
SC		 4827 /* no unmap needed here because no data xfer. */
4828
4829 ei = c->err_info;
4830 switch (ei->CommandStatus) {
4831 case CMD_SUCCESS:
4832 break;
9437ac43
SC		 4833 case CMD_TMF_STATUS:
4834 rc = hpsa_evaluate_tmf_status(h, c);
4835 break;
75167d2c
SC		 4836 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4837 rc = -1;
4838 break;
4839 default:
4840 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4841 __func__, tagupper, taglower);
d1e8beac 4842 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4843 rc = -1;
4844 break;
4845 }
45fcb86e 4846 cmd_free(h, c);
dd0e19f3
ST		 4847 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4848 __func__, tagupper, taglower);
75167d2c
SC		 4849 return rc;
4850}
4851
54b6e9e9
ST		 4852/* ioaccel2 path firmware cannot handle abort task requests.
4853 * Change abort requests to physical target reset, and send to the
4854 * address of the physical disk used for the ioaccel 2 command.
4855 * Return 0 on success (IO_OK)
4856 * -1 on failure
4857 */
4858
4859static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 4860 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 4861{
4862 int rc = IO_OK;
4863 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4864 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4865 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4866 unsigned char *psa = &phys_scsi3addr[0];
4867
4868 /* Get a pointer to the hpsa logical device. */
7fa3030c 4869 scmd = abort->scsi_cmd;
54b6e9e9
ST		 4870 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4871 if (dev == NULL) {
4872 dev_warn(&h->pdev->dev,
4873 "Cannot abort: no device pointer for command.\n");
4874 return -1; /* not abortable */
4875 }
4876
2ba8bfc8
SC		 4877 if (h->raid_offload_debug > 0)
4878 dev_info(&h->pdev->dev,
0d96ef5f 4879 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 4880 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 4881 "Reset as abort",
2ba8bfc8
SC		 4882 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
4883 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
4884
54b6e9e9
ST		 4885 if (!dev->offload_enabled) {
4886 dev_warn(&h->pdev->dev,
4887 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4888 return -1; /* not abortable */
4889 }
4890
4891 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4892 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4893 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4894 return -1; /* not abortable */
4895 }
4896
4897 /* send the reset */
2ba8bfc8
SC		 4898 if (h->raid_offload_debug > 0)
4899 dev_info(&h->pdev->dev,
4900 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4901 psa[0], psa[1], psa[2], psa[3],
4902 psa[4], psa[5], psa[6], psa[7]);
25163bd5 4903 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 4904 if (rc != 0) {
4905 dev_warn(&h->pdev->dev,
4906 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4907 psa[0], psa[1], psa[2], psa[3],
4908 psa[4], psa[5], psa[6], psa[7]);
4909 return rc; /* failed to reset */
4910 }
4911
4912 /* wait for device to recover */
4913 if (wait_for_device_to_become_ready(h, psa) != 0) {
4914 dev_warn(&h->pdev->dev,
4915 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4916 psa[0], psa[1], psa[2], psa[3],
4917 psa[4], psa[5], psa[6], psa[7]);
4918 return -1; /* failed to recover */
4919 }
4920
4921 /* device recovered */
4922 dev_info(&h->pdev->dev,
4923 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4924 psa[0], psa[1], psa[2], psa[3],
4925 psa[4], psa[5], psa[6], psa[7]);
4926
4927 return rc; /* success */
4928}
4929
6cba3f19 4930static int hpsa_send_abort_both_ways(struct ctlr_info *h,
25163bd5 4931 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
6cba3f19 4932{
54b6e9e9
ST		 4933 /* ioccelerator mode 2 commands should be aborted via the
4934 * accelerated path, since RAID path is unaware of these commands,
4935 * but underlying firmware can't handle abort TMF.
4936 * Change abort to physical device reset.
4937 */
4938 if (abort->cmd_type == CMD_IOACCEL2)
25163bd5
WS		 4939 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
4940 abort, reply_queue);
9b5c48c2 4941 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
25163bd5 4942}
54b6e9e9 4943
25163bd5
WS		 4944/* Find out which reply queue a command was meant to return on */
4945static int hpsa_extract_reply_queue(struct ctlr_info *h,
4946 struct CommandList *c)
4947{
4948 if (c->cmd_type == CMD_IOACCEL2)
4949 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
4950 return c->Header.ReplyQueue;
6cba3f19
SC		 4951}
4952
9b5c48c2
SC		 4953/*
4954 * Limit concurrency of abort commands to prevent
4955 * over-subscription of commands
4956 */
4957static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
4958{
4959#define ABORT_CMD_WAIT_MSECS 5000
4960 return !wait_event_timeout(h->abort_cmd_wait_queue,
4961 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
4962 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
4963}
4964
75167d2c
SC		 4965/* Send an abort for the specified command.
4966 * If the device and controller support it,
4967 * send a task abort request.
4968 */
4969static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
4970{
4971
4972 int i, rc;
4973 struct ctlr_info *h;
4974 struct hpsa_scsi_dev_t *dev;
4975 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 4976 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
4977 char msg[256]; /* For debug messaging. */
4978 int ml = 0;
2b08b3e9 4979 __le32 tagupper, taglower;
25163bd5
WS		 4980 int refcount, reply_queue;
4981
4982 if (sc == NULL)
4983 return FAILED;
75167d2c 4984
9b5c48c2
SC		 4985 if (sc->device == NULL)
4986 return FAILED;
4987
75167d2c
SC		 4988 /* Find the controller of the command to be aborted */
4989 h = sdev_to_hba(sc->device);
9b5c48c2 4990 if (h == NULL)
75167d2c
SC		 4991 return FAILED;
4992
25163bd5
WS		 4993 /* Find the device of the command to be aborted */
4994 dev = sc->device->hostdata;
4995 if (!dev) {
4996 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
4997 msg);
e345893b 4998 return FAILED;
25163bd5
WS		 4999 }
5000
5001 /* If controller locked up, we can guarantee command won't complete */
5002 if (lockup_detected(h)) {
5003 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5004 "ABORT FAILED, lockup detected");
5005 return FAILED;
5006 }
5007
5008 /* This is a good time to check if controller lockup has occurred */
5009 if (detect_controller_lockup(h)) {
5010 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5011 "ABORT FAILED, new lockup detected");
5012 return FAILED;
5013 }
e345893b 5014
75167d2c
SC		 5015 /* Check that controller supports some kind of task abort */
5016 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5017 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5018 return FAILED;
5019
5020 memset(msg, 0, sizeof(msg));
0d96ef5f 5021 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s",
75167d2c 5022 h->scsi_host->host_no, sc->device->channel,
0d96ef5f
WS		 5023 sc->device->id, sc->device->lun,
5024 "Aborting command");
75167d2c 5025
75167d2c
SC		 5026 /* Get SCSI command to be aborted */
5027 abort = (struct CommandList *) sc->host_scribble;
5028 if (abort == NULL) {
281a7fd0
WS		 5029 /* This can happen if the command already completed. */
5030 return SUCCESS;
5031 }
5032 refcount = atomic_inc_return(&abort->refcount);
5033 if (refcount == 1) { /* Command is done already. */
5034 cmd_free(h, abort);
5035 return SUCCESS;
75167d2c 5036 }
9b5c48c2
SC		 5037
5038 /* Don't bother trying the abort if we know it won't work. */
5039 if (abort->cmd_type != CMD_IOACCEL2 &&
5040 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5041 cmd_free(h, abort);
5042 return FAILED;
5043 }
5044
17eb87d2 5045 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5046 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 5047 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 5048 as = abort->scsi_cmd;
75167d2c
SC		 5049 if (as != NULL)
5050 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
5051 as->cmnd[0], as->serial_number);
5052 dev_dbg(&h->pdev->dev, "%s\n", msg);
0d96ef5f 5053 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
75167d2c
SC		 5054 /*
5055 * Command is in flight, or possibly already completed
5056 * by the firmware (but not to the scsi mid layer) but we can't
5057 * distinguish which. Send the abort down.
5058 */
9b5c48c2
SC		 5059 if (wait_for_available_abort_cmd(h)) {
5060 dev_warn(&h->pdev->dev,
5061 "Timed out waiting for an abort command to become available.\n");
5062 cmd_free(h, abort);
5063 return FAILED;
5064 }
25163bd5 5065 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
9b5c48c2
SC		 5066 atomic_inc(&h->abort_cmds_available);
5067 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 5068 if (rc != 0) {
0d96ef5f
WS		 5069 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5070 "FAILED to abort command");
281a7fd0 5071 cmd_free(h, abort);
75167d2c
SC		 5072 return FAILED;
5073 }
5074 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
5075
5076 /* If the abort(s) above completed and actually aborted the
5077 * command, then the command to be aborted should already be
5078 * completed. If not, wait around a bit more to see if they
5079 * manage to complete normally.
5080 */
5081#define ABORT_COMPLETE_WAIT_SECS 30
5082 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
281a7fd0
WS		 5083 refcount = atomic_read(&abort->refcount);
5084 if (refcount < 2) {
5085 cmd_free(h, abort);
75167d2c 5086 return SUCCESS;
281a7fd0
WS		 5087 } else {
5088 msleep(100);
5089 }
75167d2c
SC		 5090 }
5091 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
5092 msg, ABORT_COMPLETE_WAIT_SECS);
281a7fd0 5093 cmd_free(h, abort);
75167d2c
SC		 5094 return FAILED;
5095}
5096
edd16368
SC		 5097/*
5098 * For operations that cannot sleep, a command block is allocated at init,
5099 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
5100 * which ones are free or in use. Lock must be held when calling this.
5101 * cmd_free() is the complement.
5102 */
281a7fd0 5103
edd16368
SC		 5104static struct CommandList *cmd_alloc(struct ctlr_info *h)
5105{
5106 struct CommandList *c;
360c73bd 5107 int refcount, i;
33811026 5108 unsigned long offset;
4c413128 5109
33811026
RE		 5110 /*
5111 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 5112 * multiple threads could get in here, and one thread could
5113 * be scanning through the list of bits looking for a free
5114 * one, but the free ones are always behind him, and other
5115 * threads sneak in behind him and eat them before he can
5116 * get to them, so that while there is always a free one, a
5117 * very unlucky thread might be starved anyway, never able to
5118 * beat the other threads. In reality, this happens so
5119 * infrequently as to be indistinguishable from never.
5120 */
edd16368 5121
33811026 5122 offset = h->last_allocation; /* benignly racy */
281a7fd0
WS		 5123 for (;;) {
5124 i = find_next_zero_bit(h->cmd_pool_bits, h->nr_cmds, offset);
5125 if (unlikely(i == h->nr_cmds)) {
5126 offset = 0;
5127 continue;
5128 }
5129 c = h->cmd_pool + i;
5130 refcount = atomic_inc_return(&c->refcount);
5131 if (unlikely(refcount > 1)) {
5132 cmd_free(h, c); /* already in use */
5133 offset = (i + 1) % h->nr_cmds;
5134 continue;
5135 }
5136 set_bit(i & (BITS_PER_LONG - 1),
5137 h->cmd_pool_bits + (i / BITS_PER_LONG));
5138 break; /* it's ours now. */
5139 }
33811026 5140 h->last_allocation = i; /* benignly racy */
360c73bd 5141 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 5142 return c;
5143}
5144
edd16368
SC		 5145static void cmd_free(struct ctlr_info *h, struct CommandList *c)
5146{
281a7fd0
WS		 5147 if (atomic_dec_and_test(&c->refcount)) {
5148 int i;
edd16368 5149
281a7fd0
WS		 5150 i = c - h->cmd_pool;
5151 clear_bit(i & (BITS_PER_LONG - 1),
5152 h->cmd_pool_bits + (i / BITS_PER_LONG));
5153 }
edd16368
SC		 5154}
5155
edd16368
SC		 5156#ifdef CONFIG_COMPAT
5157
42a91641
DB		 5158static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
5159 void __user *arg)
edd16368
SC		 5160{
5161 IOCTL32_Command_struct __user *arg32 =
5162 (IOCTL32_Command_struct __user *) arg;
5163 IOCTL_Command_struct arg64;
5164 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5165 int err;
5166 u32 cp;
5167
938abd84 5168 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5169 err = 0;
5170 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5171 sizeof(arg64.LUN_info));
5172 err |= copy_from_user(&arg64.Request, &arg32->Request,
5173 sizeof(arg64.Request));
5174 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5175 sizeof(arg64.error_info));
5176 err |= get_user(arg64.buf_size, &arg32->buf_size);
5177 err |= get_user(cp, &arg32->buf);
5178 arg64.buf = compat_ptr(cp);
5179 err |= copy_to_user(p, &arg64, sizeof(arg64));
5180
5181 if (err)
5182 return -EFAULT;
5183
42a91641 5184 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 5185 if (err)
5186 return err;
5187 err |= copy_in_user(&arg32->error_info, &p->error_info,
5188 sizeof(arg32->error_info));
5189 if (err)
5190 return -EFAULT;
5191 return err;
5192}
5193
5194static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 5195 int cmd, void __user *arg)
edd16368
SC		 5196{
5197 BIG_IOCTL32_Command_struct __user *arg32 =
5198 (BIG_IOCTL32_Command_struct __user *) arg;
5199 BIG_IOCTL_Command_struct arg64;
5200 BIG_IOCTL_Command_struct __user *p =
5201 compat_alloc_user_space(sizeof(arg64));
5202 int err;
5203 u32 cp;
5204
938abd84 5205 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5206 err = 0;
5207 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5208 sizeof(arg64.LUN_info));
5209 err |= copy_from_user(&arg64.Request, &arg32->Request,
5210 sizeof(arg64.Request));
5211 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5212 sizeof(arg64.error_info));
5213 err |= get_user(arg64.buf_size, &arg32->buf_size);
5214 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5215 err |= get_user(cp, &arg32->buf);
5216 arg64.buf = compat_ptr(cp);
5217 err |= copy_to_user(p, &arg64, sizeof(arg64));
5218
5219 if (err)
5220 return -EFAULT;
5221
42a91641 5222 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 5223 if (err)
5224 return err;
5225 err |= copy_in_user(&arg32->error_info, &p->error_info,
5226 sizeof(arg32->error_info));
5227 if (err)
5228 return -EFAULT;
5229 return err;
5230}
71fe75a7 5231
42a91641 5232static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 5233{
5234 switch (cmd) {
5235 case CCISS_GETPCIINFO:
5236 case CCISS_GETINTINFO:
5237 case CCISS_SETINTINFO:
5238 case CCISS_GETNODENAME:
5239 case CCISS_SETNODENAME:
5240 case CCISS_GETHEARTBEAT:
5241 case CCISS_GETBUSTYPES:
5242 case CCISS_GETFIRMVER:
5243 case CCISS_GETDRIVVER:
5244 case CCISS_REVALIDVOLS:
5245 case CCISS_DEREGDISK:
5246 case CCISS_REGNEWDISK:
5247 case CCISS_REGNEWD:
5248 case CCISS_RESCANDISK:
5249 case CCISS_GETLUNINFO:
5250 return hpsa_ioctl(dev, cmd, arg);
5251
5252 case CCISS_PASSTHRU32:
5253 return hpsa_ioctl32_passthru(dev, cmd, arg);
5254 case CCISS_BIG_PASSTHRU32:
5255 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5256
5257 default:
5258 return -ENOIOCTLCMD;
5259 }
5260}
edd16368
SC		 5261#endif
5262
5263static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5264{
5265 struct hpsa_pci_info pciinfo;
5266
5267 if (!argp)
5268 return -EINVAL;
5269 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5270 pciinfo.bus = h->pdev->bus->number;
5271 pciinfo.dev_fn = h->pdev->devfn;
5272 pciinfo.board_id = h->board_id;
5273 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5274 return -EFAULT;
5275 return 0;
5276}
5277
5278static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
5279{
5280 DriverVer_type DriverVer;
5281 unsigned char vmaj, vmin, vsubmin;
5282 int rc;
5283
5284 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
5285 &vmaj, &vmin, &vsubmin);
5286 if (rc != 3) {
5287 dev_info(&h->pdev->dev, "driver version string '%s' "
5288 "unrecognized.", HPSA_DRIVER_VERSION);
5289 vmaj = 0;
5290 vmin = 0;
5291 vsubmin = 0;
5292 }
5293 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
5294 if (!argp)
5295 return -EINVAL;
5296 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
5297 return -EFAULT;
5298 return 0;
5299}
5300
5301static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5302{
5303 IOCTL_Command_struct iocommand;
5304 struct CommandList *c;
5305 char *buff = NULL;
50a0decf 5306 u64 temp64;
c1f63c8f 5307 int rc = 0;
edd16368
SC		 5308
5309 if (!argp)
5310 return -EINVAL;
5311 if (!capable(CAP_SYS_RAWIO))
5312 return -EPERM;
5313 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
5314 return -EFAULT;
5315 if ((iocommand.buf_size < 1) &&
5316 (iocommand.Request.Type.Direction != XFER_NONE)) {
5317 return -EINVAL;
5318 }
5319 if (iocommand.buf_size > 0) {
5320 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
5321 if (buff == NULL)
5322 return -EFAULT;
9233fb10 5323 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 5324 /* Copy the data into the buffer we created */
5325 if (copy_from_user(buff, iocommand.buf,
5326 iocommand.buf_size)) {
c1f63c8f
SC		 5327 rc = -EFAULT;
5328 goto out_kfree;
b03a7771
SC		 5329 }
5330 } else {
5331 memset(buff, 0, iocommand.buf_size);
edd16368 5332 }
b03a7771 5333 }
45fcb86e 5334 c = cmd_alloc(h);
edd16368 5335 if (c == NULL) {
c1f63c8f
SC		 5336 rc = -ENOMEM;
5337 goto out_kfree;
edd16368
SC		 5338 }
5339 /* Fill in the command type */
5340 c->cmd_type = CMD_IOCTL_PEND;
5341 /* Fill in Command Header */
5342 c->Header.ReplyQueue = 0; /* unused in simple mode */
5343 if (iocommand.buf_size > 0) { /* buffer to fill */
5344 c->Header.SGList = 1;
50a0decf 5345 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5346 } else { /* no buffers to fill */
5347 c->Header.SGList = 0;
50a0decf 5348 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 5349 }
5350 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5351
5352 /* Fill in Request block */
5353 memcpy(&c->Request, &iocommand.Request,
5354 sizeof(c->Request));
5355
5356 /* Fill in the scatter gather information */
5357 if (iocommand.buf_size > 0) {
50a0decf 5358 temp64 = pci_map_single(h->pdev, buff,
edd16368 5359 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5360 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
5361 c->SG[0].Addr = cpu_to_le64(0);
5362 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 5363 rc = -ENOMEM;
5364 goto out;
5365 }
50a0decf
SC		 5366 c->SG[0].Addr = cpu_to_le64(temp64);
5367 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
5368 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 5369 }
25163bd5 5370 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
c2dd32e0
SC		 5371 if (iocommand.buf_size > 0)
5372 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 5373 check_ioctl_unit_attention(h, c);
25163bd5
WS		 5374 if (rc) {
5375 rc = -EIO;
5376 goto out;
5377 }
edd16368
SC		 5378
5379 /* Copy the error information out */
5380 memcpy(&iocommand.error_info, c->err_info,
5381 sizeof(iocommand.error_info));
5382 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 5383 rc = -EFAULT;
5384 goto out;
edd16368 5385 }
9233fb10 5386 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 5387 iocommand.buf_size > 0) {
edd16368
SC		 5388 /* Copy the data out of the buffer we created */
5389 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 5390 rc = -EFAULT;
5391 goto out;
edd16368
SC		 5392 }
5393 }
c1f63c8f 5394out:
45fcb86e 5395 cmd_free(h, c);
c1f63c8f
SC		 5396out_kfree:
5397 kfree(buff);
5398 return rc;
edd16368
SC		 5399}
5400
5401static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5402{
5403 BIG_IOCTL_Command_struct *ioc;
5404 struct CommandList *c;
5405 unsigned char **buff = NULL;
5406 int *buff_size = NULL;
50a0decf 5407 u64 temp64;
edd16368
SC		 5408 BYTE sg_used = 0;
5409 int status = 0;
01a02ffc
SC		 5410 u32 left;
5411 u32 sz;
edd16368
SC		 5412 BYTE __user *data_ptr;
5413
5414 if (!argp)
5415 return -EINVAL;
5416 if (!capable(CAP_SYS_RAWIO))
5417 return -EPERM;
5418 ioc = (BIG_IOCTL_Command_struct *)
5419 kmalloc(sizeof(*ioc), GFP_KERNEL);
5420 if (!ioc) {
5421 status = -ENOMEM;
5422 goto cleanup1;
5423 }
5424 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
5425 status = -EFAULT;
5426 goto cleanup1;
5427 }
5428 if ((ioc->buf_size < 1) &&
5429 (ioc->Request.Type.Direction != XFER_NONE)) {
5430 status = -EINVAL;
5431 goto cleanup1;
5432 }
5433 /* Check kmalloc limits using all SGs */
5434 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
5435 status = -EINVAL;
5436 goto cleanup1;
5437 }
d66ae08b 5438 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 5439 status = -EINVAL;
5440 goto cleanup1;
5441 }
d66ae08b 5442 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 5443 if (!buff) {
5444 status = -ENOMEM;
5445 goto cleanup1;
5446 }
d66ae08b 5447 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 5448 if (!buff_size) {
5449 status = -ENOMEM;
5450 goto cleanup1;
5451 }
5452 left = ioc->buf_size;
5453 data_ptr = ioc->buf;
5454 while (left) {
5455 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
5456 buff_size[sg_used] = sz;
5457 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
5458 if (buff[sg_used] == NULL) {
5459 status = -ENOMEM;
5460 goto cleanup1;
5461 }
9233fb10 5462 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 5463 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 5464 status = -EFAULT;
edd16368
SC		 5465 goto cleanup1;
5466 }
5467 } else
5468 memset(buff[sg_used], 0, sz);
5469 left -= sz;
5470 data_ptr += sz;
5471 sg_used++;
5472 }
45fcb86e 5473 c = cmd_alloc(h);
edd16368
SC		 5474 if (c == NULL) {
5475 status = -ENOMEM;
5476 goto cleanup1;
5477 }
5478 c->cmd_type = CMD_IOCTL_PEND;
5479 c->Header.ReplyQueue = 0;
50a0decf
SC		 5480 c->Header.SGList = (u8) sg_used;
5481 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 5482 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5483 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
5484 if (ioc->buf_size > 0) {
5485 int i;
5486 for (i = 0; i < sg_used; i++) {
50a0decf 5487 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 5488 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5489 if (dma_mapping_error(&h->pdev->dev,
5490 (dma_addr_t) temp64)) {
5491 c->SG[i].Addr = cpu_to_le64(0);
5492 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 5493 hpsa_pci_unmap(h->pdev, c, i,
5494 PCI_DMA_BIDIRECTIONAL);
5495 status = -ENOMEM;
e2d4a1f6 5496 goto cleanup0;
bcc48ffa 5497 }
50a0decf
SC		 5498 c->SG[i].Addr = cpu_to_le64(temp64);
5499 c->SG[i].Len = cpu_to_le32(buff_size[i]);
5500 c->SG[i].Ext = cpu_to_le32(0);
edd16368 5501 }
50a0decf 5502 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 5503 }
25163bd5 5504 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
b03a7771
SC		 5505 if (sg_used)
5506 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 5507 check_ioctl_unit_attention(h, c);
25163bd5
WS		 5508 if (status) {
5509 status = -EIO;
5510 goto cleanup0;
5511 }
5512
edd16368
SC		 5513 /* Copy the error information out */
5514 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
5515 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 5516 status = -EFAULT;
e2d4a1f6 5517 goto cleanup0;
edd16368 5518 }
9233fb10 5519 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 5520 int i;
5521
edd16368
SC		 5522 /* Copy the data out of the buffer we created */
5523 BYTE __user *ptr = ioc->buf;
5524 for (i = 0; i < sg_used; i++) {
5525 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 5526 status = -EFAULT;
e2d4a1f6 5527 goto cleanup0;
edd16368
SC		 5528 }
5529 ptr += buff_size[i];
5530 }
5531 }
edd16368 5532 status = 0;
e2d4a1f6 5533cleanup0:
45fcb86e 5534 cmd_free(h, c);
edd16368
SC		 5535cleanup1:
5536 if (buff) {
2b08b3e9
DB		 5537 int i;
5538
edd16368
SC		 5539 for (i = 0; i < sg_used; i++)
5540 kfree(buff[i]);
5541 kfree(buff);
5542 }
5543 kfree(buff_size);
5544 kfree(ioc);
5545 return status;
5546}
5547
5548static void check_ioctl_unit_attention(struct ctlr_info *h,
5549 struct CommandList *c)
5550{
5551 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5552 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
5553 (void) check_for_unit_attention(h, c);
5554}
0390f0c0 5555
edd16368
SC		 5556/*
5557 * ioctl
5558 */
42a91641 5559static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 5560{
5561 struct ctlr_info *h;
5562 void __user *argp = (void __user *)arg;
0390f0c0 5563 int rc;
edd16368
SC		 5564
5565 h = sdev_to_hba(dev);
5566
5567 switch (cmd) {
5568 case CCISS_DEREGDISK:
5569 case CCISS_REGNEWDISK:
5570 case CCISS_REGNEWD:
a08a8471 5571 hpsa_scan_start(h->scsi_host);
edd16368
SC		 5572 return 0;
5573 case CCISS_GETPCIINFO:
5574 return hpsa_getpciinfo_ioctl(h, argp);
5575 case CCISS_GETDRIVVER:
5576 return hpsa_getdrivver_ioctl(h, argp);
5577 case CCISS_PASSTHRU:
34f0c627 5578 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 5579 return -EAGAIN;
5580 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 5581 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 5582 return rc;
edd16368 5583 case CCISS_BIG_PASSTHRU:
34f0c627 5584 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 5585 return -EAGAIN;
5586 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 5587 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 5588 return rc;
edd16368
SC		 5589 default:
5590 return -ENOTTY;
5591 }
5592}
5593
6f039790
GKH		 5594static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
5595 u8 reset_type)
64670ac8
SC		 5596{
5597 struct CommandList *c;
5598
5599 c = cmd_alloc(h);
5600 if (!c)
5601 return -ENOMEM;
a2dac136
SC		 5602 /* fill_cmd can't fail here, no data buffer to map */
5603 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 5604 RAID_CTLR_LUNID, TYPE_MSG);
5605 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
5606 c->waiting = NULL;
5607 enqueue_cmd_and_start_io(h, c);
5608 /* Don't wait for completion, the reset won't complete. Don't free
5609 * the command either. This is the last command we will send before
5610 * re-initializing everything, so it doesn't matter and won't leak.
5611 */
5612 return 0;
5613}
5614
a2dac136 5615static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 5616 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 5617 int cmd_type)
5618{
5619 int pci_dir = XFER_NONE;
9b5c48c2 5620 u64 tag; /* for commands to be aborted */
edd16368
SC		 5621
5622 c->cmd_type = CMD_IOCTL_PEND;
5623 c->Header.ReplyQueue = 0;
5624 if (buff != NULL && size > 0) {
5625 c->Header.SGList = 1;
50a0decf 5626 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5627 } else {
5628 c->Header.SGList = 0;
50a0decf 5629 c->Header.SGTotal = cpu_to_le16(0);
edd16368 5630 }
edd16368
SC		 5631 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
5632
edd16368
SC		 5633 if (cmd_type == TYPE_CMD) {
5634 switch (cmd) {
5635 case HPSA_INQUIRY:
5636 /* are we trying to read a vital product page */
b7bb24eb 5637 if (page_code & VPD_PAGE) {
edd16368 5638 c->Request.CDB[1] = 0x01;
b7bb24eb 5639 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 5640 }
5641 c->Request.CDBLen = 6;
a505b86f
SC		 5642 c->Request.type_attr_dir =
5643 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5644 c->Request.Timeout = 0;
5645 c->Request.CDB[0] = HPSA_INQUIRY;
5646 c->Request.CDB[4] = size & 0xFF;
5647 break;
5648 case HPSA_REPORT_LOG:
5649 case HPSA_REPORT_PHYS:
5650 /* Talking to controller so It's a physical command
5651 mode = 00 target = 0. Nothing to write.
5652 */
5653 c->Request.CDBLen = 12;
a505b86f
SC		 5654 c->Request.type_attr_dir =
5655 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5656 c->Request.Timeout = 0;
5657 c->Request.CDB[0] = cmd;
5658 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5659 c->Request.CDB[7] = (size >> 16) & 0xFF;
5660 c->Request.CDB[8] = (size >> 8) & 0xFF;
5661 c->Request.CDB[9] = size & 0xFF;
5662 break;
edd16368
SC		 5663 case HPSA_CACHE_FLUSH:
5664 c->Request.CDBLen = 12;
a505b86f
SC		 5665 c->Request.type_attr_dir =
5666 TYPE_ATTR_DIR(cmd_type,
5667 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5668 c->Request.Timeout = 0;
5669 c->Request.CDB[0] = BMIC_WRITE;
5670 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 5671 c->Request.CDB[7] = (size >> 8) & 0xFF;
5672 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 5673 break;
5674 case TEST_UNIT_READY:
5675 c->Request.CDBLen = 6;
a505b86f
SC		 5676 c->Request.type_attr_dir =
5677 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5678 c->Request.Timeout = 0;
5679 break;
283b4a9b
SC		 5680 case HPSA_GET_RAID_MAP:
5681 c->Request.CDBLen = 12;
a505b86f
SC		 5682 c->Request.type_attr_dir =
5683 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 5684 c->Request.Timeout = 0;
5685 c->Request.CDB[0] = HPSA_CISS_READ;
5686 c->Request.CDB[1] = cmd;
5687 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5688 c->Request.CDB[7] = (size >> 16) & 0xFF;
5689 c->Request.CDB[8] = (size >> 8) & 0xFF;
5690 c->Request.CDB[9] = size & 0xFF;
5691 break;
316b221a
SC		 5692 case BMIC_SENSE_CONTROLLER_PARAMETERS:
5693 c->Request.CDBLen = 10;
a505b86f
SC		 5694 c->Request.type_attr_dir =
5695 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 5696 c->Request.Timeout = 0;
5697 c->Request.CDB[0] = BMIC_READ;
5698 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
5699 c->Request.CDB[7] = (size >> 16) & 0xFF;
5700 c->Request.CDB[8] = (size >> 8) & 0xFF;
5701 break;
03383736
DB		 5702 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
5703 c->Request.CDBLen = 10;
5704 c->Request.type_attr_dir =
5705 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
5706 c->Request.Timeout = 0;
5707 c->Request.CDB[0] = BMIC_READ;
5708 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
5709 c->Request.CDB[7] = (size >> 16) & 0xFF;
5710 c->Request.CDB[8] = (size >> 8) & 0XFF;
5711 break;
edd16368
SC		 5712 default:
5713 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5714 BUG();
a2dac136 5715 return -1;
edd16368
SC		 5716 }
5717 } else if (cmd_type == TYPE_MSG) {
5718 switch (cmd) {
5719
5720 case HPSA_DEVICE_RESET_MSG:
5721 c->Request.CDBLen = 16;
a505b86f
SC		 5722 c->Request.type_attr_dir =
5723 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 5724 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5725 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5726 c->Request.CDB[0] = cmd;
21e89afd 5727 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5728 /* If bytes 4-7 are zero, it means reset the */
5729 /* LunID device */
5730 c->Request.CDB[4] = 0x00;
5731 c->Request.CDB[5] = 0x00;
5732 c->Request.CDB[6] = 0x00;
5733 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5734 break;
5735 case HPSA_ABORT_MSG:
9b5c48c2 5736 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 5737 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 5738 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
5739 tag, c->Header.tag);
75167d2c 5740 c->Request.CDBLen = 16;
a505b86f
SC		 5741 c->Request.type_attr_dir =
5742 TYPE_ATTR_DIR(cmd_type,
5743 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 5744 c->Request.Timeout = 0; /* Don't time out */
5745 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5746 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5747 c->Request.CDB[2] = 0x00; /* reserved */
5748 c->Request.CDB[3] = 0x00; /* reserved */
5749 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 5750 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 5751 c->Request.CDB[12] = 0x00; /* reserved */
5752 c->Request.CDB[13] = 0x00; /* reserved */
5753 c->Request.CDB[14] = 0x00; /* reserved */
5754 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5755 break;
edd16368
SC		 5756 default:
5757 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5758 cmd);
5759 BUG();
5760 }
5761 } else {
5762 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5763 BUG();
5764 }
5765
a505b86f 5766 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 5767 case XFER_READ:
5768 pci_dir = PCI_DMA_FROMDEVICE;
5769 break;
5770 case XFER_WRITE:
5771 pci_dir = PCI_DMA_TODEVICE;
5772 break;
5773 case XFER_NONE:
5774 pci_dir = PCI_DMA_NONE;
5775 break;
5776 default:
5777 pci_dir = PCI_DMA_BIDIRECTIONAL;
5778 }
a2dac136
SC		 5779 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5780 return -1;
5781 return 0;
edd16368
SC		 5782}
5783
5784/*
5785 * Map (physical) PCI mem into (virtual) kernel space
5786 */
5787static void __iomem *remap_pci_mem(ulong base, ulong size)
5788{
5789 ulong page_base = ((ulong) base) & PAGE_MASK;
5790 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5791 void __iomem *page_remapped = ioremap_nocache(page_base,
5792 page_offs + size);
edd16368
SC		 5793
5794 return page_remapped ? (page_remapped + page_offs) : NULL;
5795}
5796
254f796b 5797static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5798{
254f796b 5799 return h->access.command_completed(h, q);
edd16368
SC		 5800}
5801
900c5440 5802static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5803{
5804 return h->access.intr_pending(h);
5805}
5806
5807static inline long interrupt_not_for_us(struct ctlr_info *h)
5808{
10f66018
SC		 5809 return (h->access.intr_pending(h) == 0) ||
5810 (h->interrupts_enabled == 0);
edd16368
SC		 5811}
5812
01a02ffc
SC		 5813static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5814 u32 raw_tag)
edd16368
SC		 5815{
5816 if (unlikely(tag_index >= h->nr_cmds)) {
5817 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5818 return 1;
5819 }
5820 return 0;
5821}
5822
5a3d16f5 5823static inline void finish_cmd(struct CommandList *c)
edd16368 5824{
e85c5974 5825 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5826 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5827 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5828 complete_scsi_command(c);
edd16368
SC		 5829 else if (c->cmd_type == CMD_IOCTL_PEND)
5830 complete(c->waiting);
a104c99f
SC		 5831}
5832
a9a3a273
SC		 5833
5834static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5835{
a9a3a273
SC		 5836#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5837#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5838 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5839 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5840 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5841}
5842
303932fd 5843/* process completion of an indexed ("direct lookup") command */
1d94f94d 5844static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5845 u32 raw_tag)
5846{
5847 u32 tag_index;
5848 struct CommandList *c;
5849
f2405db8 5850 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 5851 if (!bad_tag(h, tag_index, raw_tag)) {
5852 c = h->cmd_pool + tag_index;
5853 finish_cmd(c);
5854 }
303932fd
DB		 5855}
5856
64670ac8
SC		 5857/* Some controllers, like p400, will give us one interrupt
5858 * after a soft reset, even if we turned interrupts off.
5859 * Only need to check for this in the hpsa_xxx_discard_completions
5860 * functions.
5861 */
5862static int ignore_bogus_interrupt(struct ctlr_info *h)
5863{
5864 if (likely(!reset_devices))
5865 return 0;
5866
5867 if (likely(h->interrupts_enabled))
5868 return 0;
5869
5870 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5871 "(known firmware bug.) Ignoring.\n");
5872
5873 return 1;
5874}
5875
254f796b
MG		 5876/*
5877 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5878 * Relies on (h-q[x] == x) being true for x such that
5879 * 0 <= x < MAX_REPLY_QUEUES.
5880 */
5881static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5882{
254f796b
MG		 5883 return container_of((queue - *queue), struct ctlr_info, q[0]);
5884}
5885
5886static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5887{
5888 struct ctlr_info *h = queue_to_hba(queue);
5889 u8 q = *(u8 *) queue;
64670ac8
SC		 5890 u32 raw_tag;
5891
5892 if (ignore_bogus_interrupt(h))
5893 return IRQ_NONE;
5894
5895 if (interrupt_not_for_us(h))
5896 return IRQ_NONE;
a0c12413 5897 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5898 while (interrupt_pending(h)) {
254f796b 5899 raw_tag = get_next_completion(h, q);
64670ac8 5900 while (raw_tag != FIFO_EMPTY)
254f796b 5901 raw_tag = next_command(h, q);
64670ac8 5902 }
64670ac8
SC		 5903 return IRQ_HANDLED;
5904}
5905
254f796b 5906static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5907{
254f796b 5908 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5909 u32 raw_tag;
254f796b 5910 u8 q = *(u8 *) queue;
64670ac8
SC		 5911
5912 if (ignore_bogus_interrupt(h))
5913 return IRQ_NONE;
5914
a0c12413 5915 h->last_intr_timestamp = get_jiffies_64();
254f796b 5916 raw_tag = get_next_completion(h, q);
64670ac8 5917 while (raw_tag != FIFO_EMPTY)
254f796b 5918 raw_tag = next_command(h, q);
64670ac8
SC		 5919 return IRQ_HANDLED;
5920}
5921
254f796b 5922static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5923{
254f796b 5924 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5925 u32 raw_tag;
254f796b 5926 u8 q = *(u8 *) queue;
edd16368
SC		 5927
5928 if (interrupt_not_for_us(h))
5929 return IRQ_NONE;
a0c12413 5930 h->last_intr_timestamp = get_jiffies_64();
10f66018 5931 while (interrupt_pending(h)) {
254f796b 5932 raw_tag = get_next_completion(h, q);
10f66018 5933 while (raw_tag != FIFO_EMPTY) {
f2405db8 5934 process_indexed_cmd(h, raw_tag);
254f796b 5935 raw_tag = next_command(h, q);
10f66018
SC		 5936 }
5937 }
10f66018
SC		 5938 return IRQ_HANDLED;
5939}
5940
254f796b 5941static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5942{
254f796b 5943 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5944 u32 raw_tag;
254f796b 5945 u8 q = *(u8 *) queue;
10f66018 5946
a0c12413 5947 h->last_intr_timestamp = get_jiffies_64();
254f796b 5948 raw_tag = get_next_completion(h, q);
303932fd 5949 while (raw_tag != FIFO_EMPTY) {
f2405db8 5950 process_indexed_cmd(h, raw_tag);
254f796b 5951 raw_tag = next_command(h, q);
edd16368 5952 }
edd16368
SC		 5953 return IRQ_HANDLED;
5954}
5955
a9a3a273
SC		 5956/* Send a message CDB to the firmware. Careful, this only works
5957 * in simple mode, not performant mode due to the tag lookup.
5958 * We only ever use this immediately after a controller reset.
5959 */
6f039790
GKH		 5960static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5961 unsigned char type)
edd16368
SC		 5962{
5963 struct Command {
5964 struct CommandListHeader CommandHeader;
5965 struct RequestBlock Request;
5966 struct ErrDescriptor ErrorDescriptor;
5967 };
5968 struct Command *cmd;
5969 static const size_t cmd_sz = sizeof(*cmd) +
5970 sizeof(cmd->ErrorDescriptor);
5971 dma_addr_t paddr64;
2b08b3e9
DB		 5972 __le32 paddr32;
5973 u32 tag;
edd16368
SC		 5974 void __iomem *vaddr;
5975 int i, err;
5976
5977 vaddr = pci_ioremap_bar(pdev, 0);
5978 if (vaddr == NULL)
5979 return -ENOMEM;
5980
5981 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5982 * CCISS commands, so they must be allocated from the lower 4GiB of
5983 * memory.
5984 */
5985 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5986 if (err) {
5987 iounmap(vaddr);
1eaec8f3 5988 return err;
edd16368
SC		 5989 }
5990
5991 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5992 if (cmd == NULL) {
5993 iounmap(vaddr);
5994 return -ENOMEM;
5995 }
5996
5997 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5998 * although there's no guarantee, we assume that the address is at
5999 * least 4-byte aligned (most likely, it's page-aligned).
6000 */
2b08b3e9 6001 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 6002
6003 cmd->CommandHeader.ReplyQueue = 0;
6004 cmd->CommandHeader.SGList = 0;
50a0decf 6005 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 6006 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 6007 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
6008
6009 cmd->Request.CDBLen = 16;
a505b86f
SC		 6010 cmd->Request.type_attr_dir =
6011 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 6012 cmd->Request.Timeout = 0; /* Don't time out */
6013 cmd->Request.CDB[0] = opcode;
6014 cmd->Request.CDB[1] = type;
6015 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 6016 cmd->ErrorDescriptor.Addr =
2b08b3e9 6017 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 6018 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 6019
2b08b3e9 6020 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 6021
6022 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
6023 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 6024 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 6025 break;
6026 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
6027 }
6028
6029 iounmap(vaddr);
6030
6031 /* we leak the DMA buffer here ... no choice since the controller could
6032 * still complete the command.
6033 */
6034 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
6035 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
6036 opcode, type);
6037 return -ETIMEDOUT;
6038 }
6039
6040 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
6041
6042 if (tag & HPSA_ERROR_BIT) {
6043 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
6044 opcode, type);
6045 return -EIO;
6046 }
6047
6048 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
6049 opcode, type);
6050 return 0;
6051}
6052
edd16368
SC		 6053#define hpsa_noop(p) hpsa_message(p, 3, 0)
6054
1df8552a 6055static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 6056 void __iomem *vaddr, u32 use_doorbell)
1df8552a 6057{
1df8552a
SC		 6058
6059 if (use_doorbell) {
6060 /* For everything after the P600, the PCI power state method
6061 * of resetting the controller doesn't work, so we have this
6062 * other way using the doorbell register.
6063 */
6064 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 6065 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 6066
00701a96 6067 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 6068 * doorbell reset and before any attempt to talk to the board
6069 * at all to ensure that this actually works and doesn't fall
6070 * over in some weird corner cases.
6071 */
00701a96 6072 msleep(10000);
1df8552a
SC		 6073 } else { /* Try to do it the PCI power state way */
6074
6075 /* Quoting from the Open CISS Specification: "The Power
6076 * Management Control/Status Register (CSR) controls the power
6077 * state of the device. The normal operating state is D0,
6078 * CSR=00h. The software off state is D3, CSR=03h. To reset
6079 * the controller, place the interface device in D3 then to D0,
6080 * this causes a secondary PCI reset which will reset the
6081 * controller." */
2662cab8
DB		 6082
6083 int rc = 0;
6084
1df8552a 6085 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 6086
1df8552a 6087 /* enter the D3hot power management state */
2662cab8
DB		 6088 rc = pci_set_power_state(pdev, PCI_D3hot);
6089 if (rc)
6090 return rc;
1df8552a
SC		 6091
6092 msleep(500);
6093
6094 /* enter the D0 power management state */
2662cab8
DB		 6095 rc = pci_set_power_state(pdev, PCI_D0);
6096 if (rc)
6097 return rc;
c4853efe
MM		 6098
6099 /*
6100 * The P600 requires a small delay when changing states.
6101 * Otherwise we may think the board did not reset and we bail.
6102 * This for kdump only and is particular to the P600.
6103 */
6104 msleep(500);
1df8552a
SC		 6105 }
6106 return 0;
6107}
6108
6f039790 6109static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 6110{
6111 memset(driver_version, 0, len);
f79cfec6 6112 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 6113}
6114
6f039790 6115static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6116{
6117 char *driver_version;
6118 int i, size = sizeof(cfgtable->driver_version);
6119
6120 driver_version = kmalloc(size, GFP_KERNEL);
6121 if (!driver_version)
6122 return -ENOMEM;
6123
6124 init_driver_version(driver_version, size);
6125 for (i = 0; i < size; i++)
6126 writeb(driver_version[i], &cfgtable->driver_version[i]);
6127 kfree(driver_version);
6128 return 0;
6129}
6130
6f039790
GKH		 6131static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
6132 unsigned char *driver_ver)
580ada3c
SC		 6133{
6134 int i;
6135
6136 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
6137 driver_ver[i] = readb(&cfgtable->driver_version[i]);
6138}
6139
6f039790 6140static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6141{
6142
6143 char *driver_ver, *old_driver_ver;
6144 int rc, size = sizeof(cfgtable->driver_version);
6145
6146 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
6147 if (!old_driver_ver)
6148 return -ENOMEM;
6149 driver_ver = old_driver_ver + size;
6150
6151 /* After a reset, the 32 bytes of "driver version" in the cfgtable
6152 * should have been changed, otherwise we know the reset failed.
6153 */
6154 init_driver_version(old_driver_ver, size);
6155 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
6156 rc = !memcmp(driver_ver, old_driver_ver, size);
6157 kfree(old_driver_ver);
6158 return rc;
6159}
edd16368 6160/* This does a hard reset of the controller using PCI power management
1df8552a 6161 * states or the using the doorbell register.
edd16368 6162 */
6b6c1cd7 6163static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 6164{
1df8552a
SC		 6165 u64 cfg_offset;
6166 u32 cfg_base_addr;
6167 u64 cfg_base_addr_index;
6168 void __iomem *vaddr;
6169 unsigned long paddr;
580ada3c 6170 u32 misc_fw_support;
270d05de 6171 int rc;
1df8552a 6172 struct CfgTable __iomem *cfgtable;
cf0b08d0 6173 u32 use_doorbell;
270d05de 6174 u16 command_register;
edd16368 6175
1df8552a
SC		 6176 /* For controllers as old as the P600, this is very nearly
6177 * the same thing as
edd16368
SC		 6178 *
6179 * pci_save_state(pci_dev);
6180 * pci_set_power_state(pci_dev, PCI_D3hot);
6181 * pci_set_power_state(pci_dev, PCI_D0);
6182 * pci_restore_state(pci_dev);
6183 *
1df8552a
SC		 6184 * For controllers newer than the P600, the pci power state
6185 * method of resetting doesn't work so we have another way
6186 * using the doorbell register.
edd16368 6187 */
18867659 6188
60f923b9
RE		 6189 if (!ctlr_is_resettable(board_id)) {
6190 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 6191 return -ENODEV;
6192 }
46380786
SC		 6193
6194 /* if controller is soft- but not hard resettable... */
6195 if (!ctlr_is_hard_resettable(board_id))
6196 return -ENOTSUPP; /* try soft reset later. */
18867659 6197
270d05de
SC		 6198 /* Save the PCI command register */
6199 pci_read_config_word(pdev, 4, &command_register);
270d05de 6200 pci_save_state(pdev);
edd16368 6201
1df8552a
SC		 6202 /* find the first memory BAR, so we can find the cfg table */
6203 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6204 if (rc)
6205 return rc;
6206 vaddr = remap_pci_mem(paddr, 0x250);
6207 if (!vaddr)
6208 return -ENOMEM;
edd16368 6209
1df8552a
SC		 6210 /* find cfgtable in order to check if reset via doorbell is supported */
6211 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6212 &cfg_base_addr_index, &cfg_offset);
6213 if (rc)
6214 goto unmap_vaddr;
6215 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6216 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6217 if (!cfgtable) {
6218 rc = -ENOMEM;
6219 goto unmap_vaddr;
6220 }
580ada3c
SC		 6221 rc = write_driver_ver_to_cfgtable(cfgtable);
6222 if (rc)
03741d95 6223 goto unmap_cfgtable;
edd16368 6224
cf0b08d0
SC		 6225 /* If reset via doorbell register is supported, use that.
6226 * There are two such methods. Favor the newest method.
6227 */
1df8552a 6228 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6229 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6230 if (use_doorbell) {
6231 use_doorbell = DOORBELL_CTLR_RESET2;
6232 } else {
6233 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6234 if (use_doorbell) {
050f7147
SC		 6235 dev_warn(&pdev->dev,
6236 "Soft reset not supported. Firmware update is required.\n");
64670ac8 6237 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6238 goto unmap_cfgtable;
6239 }
6240 }
edd16368 6241
1df8552a
SC		 6242 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6243 if (rc)
6244 goto unmap_cfgtable;
edd16368 6245
270d05de 6246 pci_restore_state(pdev);
270d05de 6247 pci_write_config_word(pdev, 4, command_register);
edd16368 6248
1df8552a
SC		 6249 /* Some devices (notably the HP Smart Array 5i Controller)
6250 need a little pause here */
6251 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6252
fe5389c8
SC		 6253 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6254 if (rc) {
6255 dev_warn(&pdev->dev,
050f7147 6256 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 6257 goto unmap_cfgtable;
6258 }
fe5389c8 6259
580ada3c
SC		 6260 rc = controller_reset_failed(vaddr);
6261 if (rc < 0)
6262 goto unmap_cfgtable;
6263 if (rc) {
64670ac8
SC		 6264 dev_warn(&pdev->dev, "Unable to successfully reset "
6265 "controller. Will try soft reset.\n");
6266 rc = -ENOTSUPP;
580ada3c 6267 } else {
64670ac8 6268 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6269 }
6270
6271unmap_cfgtable:
6272 iounmap(cfgtable);
6273
6274unmap_vaddr:
6275 iounmap(vaddr);
6276 return rc;
edd16368
SC		 6277}
6278
6279/*
6280 * We cannot read the structure directly, for portability we must use
6281 * the io functions.
6282 * This is for debug only.
6283 */
42a91641 6284static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 6285{
58f8665c 6286#ifdef HPSA_DEBUG
edd16368
SC		 6287 int i;
6288 char temp_name[17];
6289
6290 dev_info(dev, "Controller Configuration information\n");
6291 dev_info(dev, "------------------------------------\n");
6292 for (i = 0; i < 4; i++)
6293 temp_name[i] = readb(&(tb->Signature[i]));
6294 temp_name[4] = '\0';
6295 dev_info(dev, " Signature = %s\n", temp_name);
6296 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6297 dev_info(dev, " Transport methods supported = 0x%x\n",
6298 readl(&(tb->TransportSupport)));
6299 dev_info(dev, " Transport methods active = 0x%x\n",
6300 readl(&(tb->TransportActive)));
6301 dev_info(dev, " Requested transport Method = 0x%x\n",
6302 readl(&(tb->HostWrite.TransportRequest)));
6303 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6304 readl(&(tb->HostWrite.CoalIntDelay)));
6305 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6306 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 6307 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 6308 readl(&(tb->CmdsOutMax)));
6309 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6310 for (i = 0; i < 16; i++)
6311 temp_name[i] = readb(&(tb->ServerName[i]));
6312 temp_name[16] = '\0';
6313 dev_info(dev, " Server Name = %s\n", temp_name);
6314 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6315 readl(&(tb->HeartBeat)));
edd16368 6316#endif /* HPSA_DEBUG */
58f8665c 6317}
edd16368
SC		 6318
6319static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6320{
6321 int i, offset, mem_type, bar_type;
6322
6323 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6324 return 0;
6325 offset = 0;
6326 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6327 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6328 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6329 offset += 4;
6330 else {
6331 mem_type = pci_resource_flags(pdev, i) &
6332 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6333 switch (mem_type) {
6334 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6335 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6336 offset += 4; /* 32 bit */
6337 break;
6338 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6339 offset += 8;
6340 break;
6341 default: /* reserved in PCI 2.2 */
6342 dev_warn(&pdev->dev,
6343 "base address is invalid\n");
6344 return -1;
6345 break;
6346 }
6347 }
6348 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6349 return i + 1;
6350 }
6351 return -1;
6352}
6353
cc64c817
RE		 6354static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
6355{
6356 if (h->msix_vector) {
6357 if (h->pdev->msix_enabled)
6358 pci_disable_msix(h->pdev);
6359 } else if (h->msi_vector) {
6360 if (h->pdev->msi_enabled)
6361 pci_disable_msi(h->pdev);
6362 }
6363}
6364
edd16368 6365/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 6366 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 6367 */
6f039790 6368static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6369{
6370#ifdef CONFIG_PCI_MSI
254f796b
MG		 6371 int err, i;
6372 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6373
6374 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6375 hpsa_msix_entries[i].vector = 0;
6376 hpsa_msix_entries[i].entry = i;
6377 }
edd16368
SC		 6378
6379 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6380 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6381 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6382 goto default_int_mode;
55c06c71 6383 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 6384 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 6385 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 6386 if (h->msix_vector > num_online_cpus())
6387 h->msix_vector = num_online_cpus();
18fce3c4
AG		 6388 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
6389 1, h->msix_vector);
6390 if (err < 0) {
6391 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
6392 h->msix_vector = 0;
6393 goto single_msi_mode;
6394 } else if (err < h->msix_vector) {
55c06c71 6395 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 6396 "available\n", err);
edd16368 6397 }
18fce3c4
AG		 6398 h->msix_vector = err;
6399 for (i = 0; i < h->msix_vector; i++)
6400 h->intr[i] = hpsa_msix_entries[i].vector;
6401 return;
edd16368 6402 }
18fce3c4 6403single_msi_mode:
55c06c71 6404 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 6405 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 6406 if (!pci_enable_msi(h->pdev))
edd16368
SC		 6407 h->msi_vector = 1;
6408 else
55c06c71 6409 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 6410 }
6411default_int_mode:
6412#endif /* CONFIG_PCI_MSI */
6413 /* if we get here we're going to use the default interrupt mode */
a9a3a273 6414 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 6415}
6416
6f039790 6417static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 6418{
6419 int i;
6420 u32 subsystem_vendor_id, subsystem_device_id;
6421
6422 subsystem_vendor_id = pdev->subsystem_vendor;
6423 subsystem_device_id = pdev->subsystem_device;
6424 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
6425 subsystem_vendor_id;
6426
6427 for (i = 0; i < ARRAY_SIZE(products); i++)
6428 if (*board_id == products[i].board_id)
6429 return i;
6430
6798cc0a
SC		 6431 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
6432 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
6433 !hpsa_allow_any) {
e5c880d1
SC		 6434 dev_warn(&pdev->dev, "unrecognized board ID: "
6435 "0x%08x, ignoring.\n", *board_id);
6436 return -ENODEV;
6437 }
6438 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
6439}
6440
6f039790
GKH		 6441static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
6442 unsigned long *memory_bar)
3a7774ce
SC		 6443{
6444 int i;
6445
6446 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 6447 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 6448 /* addressing mode bits already removed */
12d2cd47
SC		 6449 *memory_bar = pci_resource_start(pdev, i);
6450 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 6451 *memory_bar);
6452 return 0;
6453 }
12d2cd47 6454 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 6455 return -ENODEV;
6456}
6457
6f039790
GKH		 6458static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
6459 int wait_for_ready)
2c4c8c8b 6460{
fe5389c8 6461 int i, iterations;
2c4c8c8b 6462 u32 scratchpad;
fe5389c8
SC		 6463 if (wait_for_ready)
6464 iterations = HPSA_BOARD_READY_ITERATIONS;
6465 else
6466 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 6467
fe5389c8
SC		 6468 for (i = 0; i < iterations; i++) {
6469 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
6470 if (wait_for_ready) {
6471 if (scratchpad == HPSA_FIRMWARE_READY)
6472 return 0;
6473 } else {
6474 if (scratchpad != HPSA_FIRMWARE_READY)
6475 return 0;
6476 }
2c4c8c8b
SC		 6477 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
6478 }
fe5389c8 6479 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 6480 return -ENODEV;
6481}
6482
6f039790
GKH		 6483static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
6484 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
6485 u64 *cfg_offset)
a51fd47f
SC		 6486{
6487 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
6488 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
6489 *cfg_base_addr &= (u32) 0x0000ffff;
6490 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
6491 if (*cfg_base_addr_index == -1) {
6492 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
6493 return -ENODEV;
6494 }
6495 return 0;
6496}
6497
6f039790 6498static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 6499{
01a02ffc
SC		 6500 u64 cfg_offset;
6501 u32 cfg_base_addr;
6502 u64 cfg_base_addr_index;
303932fd 6503 u32 trans_offset;
a51fd47f 6504 int rc;
77c4495c 6505
a51fd47f
SC		 6506 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6507 &cfg_base_addr_index, &cfg_offset);
6508 if (rc)
6509 return rc;
77c4495c 6510 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 6511 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 6512 if (!h->cfgtable) {
6513 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 6514 return -ENOMEM;
cd3c81c4 6515 }
580ada3c
SC		 6516 rc = write_driver_ver_to_cfgtable(h->cfgtable);
6517 if (rc)
6518 return rc;
77c4495c 6519 /* Find performant mode table. */
a51fd47f 6520 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 6521 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
6522 cfg_base_addr_index)+cfg_offset+trans_offset,
6523 sizeof(*h->transtable));
6524 if (!h->transtable)
6525 return -ENOMEM;
6526 return 0;
6527}
6528
6f039790 6529static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 6530{
41ce4c35
SC		 6531#define MIN_MAX_COMMANDS 16
6532 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
6533
6534 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 6535
6536 /* Limit commands in memory limited kdump scenario. */
6537 if (reset_devices && h->max_commands > 32)
6538 h->max_commands = 32;
6539
41ce4c35
SC		 6540 if (h->max_commands < MIN_MAX_COMMANDS) {
6541 dev_warn(&h->pdev->dev,
6542 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
6543 h->max_commands,
6544 MIN_MAX_COMMANDS);
6545 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 6546 }
6547}
6548
c7ee65b3
WS		 6549/* If the controller reports that the total max sg entries is greater than 512,
6550 * then we know that chained SG blocks work. (Original smart arrays did not
6551 * support chained SG blocks and would return zero for max sg entries.)
6552 */
6553static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
6554{
6555 return h->maxsgentries > 512;
6556}
6557
b93d7536
SC		 6558/* Interrogate the hardware for some limits:
6559 * max commands, max SG elements without chaining, and with chaining,
6560 * SG chain block size, etc.
6561 */
6f039790 6562static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 6563{
cba3d38b 6564 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 6565 h->nr_cmds = h->max_commands;
b93d7536 6566 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 6567 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 6568 if (hpsa_supports_chained_sg_blocks(h)) {
6569 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 6570 h->max_cmd_sg_entries = 32;
1a63ea6f 6571 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 6572 h->maxsgentries--; /* save one for chain pointer */
6573 } else {
c7ee65b3
WS		 6574 /*
6575 * Original smart arrays supported at most 31 s/g entries
6576 * embedded inline in the command (trying to use more
6577 * would lock up the controller)
6578 */
6579 h->max_cmd_sg_entries = 31;
1a63ea6f 6580 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 6581 h->chainsize = 0;
b93d7536 6582 }
75167d2c
SC		 6583
6584 /* Find out what task management functions are supported and cache */
6585 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 6586 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
6587 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
6588 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6589 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 6590}
6591
76c46e49
SC		 6592static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
6593{
0fc9fd40 6594 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 6595 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 6596 return false;
6597 }
6598 return true;
6599}
6600
97a5e98c 6601static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 6602{
97a5e98c 6603 u32 driver_support;
f7c39101 6604
97a5e98c 6605 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 6606 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
6607#ifdef CONFIG_X86
97a5e98c 6608 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 6609#endif
28e13446
SC		 6610 driver_support |= ENABLE_UNIT_ATTN;
6611 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 6612}
6613
3d0eab67
SC		 6614/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
6615 * in a prefetch beyond physical memory.
6616 */
6617static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
6618{
6619 u32 dma_prefetch;
6620
6621 if (h->board_id != 0x3225103C)
6622 return;
6623 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
6624 dma_prefetch |= 0x8000;
6625 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
6626}
6627
c706a795 6628static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 6629{
6630 int i;
6631 u32 doorbell_value;
6632 unsigned long flags;
6633 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 6634 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 6635 spin_lock_irqsave(&h->lock, flags);
6636 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6637 spin_unlock_irqrestore(&h->lock, flags);
6638 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 6639 goto done;
76438d08 6640 /* delay and try again */
007e7aa9 6641 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 6642 }
c706a795
RE		 6643 return -ENODEV;
6644done:
6645 return 0;
76438d08
SC		 6646}
6647
c706a795 6648static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 6649{
6650 int i;
6eaf46fd
SC		 6651 u32 doorbell_value;
6652 unsigned long flags;
eb6b2ae9
SC		 6653
6654 /* under certain very rare conditions, this can take awhile.
6655 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
6656 * as we enter this code.)
6657 */
007e7aa9 6658 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 6659 if (h->remove_in_progress)
6660 goto done;
6eaf46fd
SC		 6661 spin_lock_irqsave(&h->lock, flags);
6662 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6663 spin_unlock_irqrestore(&h->lock, flags);
382be668 6664 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 6665 goto done;
eb6b2ae9 6666 /* delay and try again */
007e7aa9 6667 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 6668 }
c706a795
RE		 6669 return -ENODEV;
6670done:
6671 return 0;
3f4336f3
SC		 6672}
6673
c706a795 6674/* return -ENODEV or other reason on error, 0 on success */
6f039790 6675static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6676{
6677 u32 trans_support;
6678
6679 trans_support = readl(&(h->cfgtable->TransportSupport));
6680 if (!(trans_support & SIMPLE_MODE))
6681 return -ENOTSUPP;
6682
6683 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6684
3f4336f3
SC		 6685 /* Update the field, and then ring the doorbell */
6686 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6687 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 6688 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 6689 if (hpsa_wait_for_mode_change_ack(h))
6690 goto error;
eb6b2ae9 6691 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6692 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6693 goto error;
960a30e7 6694 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6695 return 0;
283b4a9b 6696error:
050f7147 6697 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 6698 return -ENODEV;
eb6b2ae9
SC		 6699}
6700
6f039790 6701static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6702{
eb6b2ae9 6703 int prod_index, err;
edd16368 6704
e5c880d1
SC		 6705 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6706 if (prod_index < 0)
60f923b9 6707 return prod_index;
e5c880d1
SC		 6708 h->product_name = products[prod_index].product_name;
6709 h->access = *(products[prod_index].access);
edd16368 6710
9b5c48c2
SC		 6711 h->needs_abort_tags_swizzled =
6712 ctlr_needs_abort_tags_swizzled(h->board_id);
6713
e5a44df8
MG		 6714 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6715 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6716
55c06c71 6717 err = pci_enable_device(h->pdev);
edd16368 6718 if (err) {
55c06c71 6719 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 6720 return err;
6721 }
6722
f79cfec6 6723 err = pci_request_regions(h->pdev, HPSA);
edd16368 6724 if (err) {
55c06c71
SC		 6725 dev_err(&h->pdev->dev,
6726 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 6727 return err;
6728 }
4fa604e1
RE		 6729
6730 pci_set_master(h->pdev);
6731
6b3f4c52 6732 hpsa_interrupt_mode(h);
12d2cd47 6733 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6734 if (err)
edd16368 6735 goto err_out_free_res;
edd16368 6736 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 6737 if (!h->vaddr) {
6738 err = -ENOMEM;
6739 goto err_out_free_res;
6740 }
fe5389c8 6741 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6742 if (err)
edd16368 6743 goto err_out_free_res;
77c4495c
SC		 6744 err = hpsa_find_cfgtables(h);
6745 if (err)
edd16368 6746 goto err_out_free_res;
b93d7536 6747 hpsa_find_board_params(h);
edd16368 6748
76c46e49 6749 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 6750 err = -ENODEV;
6751 goto err_out_free_res;
6752 }
97a5e98c 6753 hpsa_set_driver_support_bits(h);
3d0eab67 6754 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6755 err = hpsa_enter_simple_mode(h);
6756 if (err)
edd16368 6757 goto err_out_free_res;
edd16368
SC		 6758 return 0;
6759
6760err_out_free_res:
204892e9
SC		 6761 if (h->transtable)
6762 iounmap(h->transtable);
6763 if (h->cfgtable)
6764 iounmap(h->cfgtable);
6765 if (h->vaddr)
6766 iounmap(h->vaddr);
f0bd0b68 6767 pci_disable_device(h->pdev);
55c06c71 6768 pci_release_regions(h->pdev);
edd16368
SC		 6769 return err;
6770}
6771
6f039790 6772static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6773{
6774 int rc;
6775
6776#define HBA_INQUIRY_BYTE_COUNT 64
6777 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6778 if (!h->hba_inquiry_data)
6779 return;
6780 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6781 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6782 if (rc != 0) {
6783 kfree(h->hba_inquiry_data);
6784 h->hba_inquiry_data = NULL;
6785 }
6786}
6787
6b6c1cd7 6788static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 6789{
1df8552a 6790 int rc, i;
3b747298 6791 void __iomem *vaddr;
4c2a8c40
SC		 6792
6793 if (!reset_devices)
6794 return 0;
6795
132aa220
TH		 6796 /* kdump kernel is loading, we don't know in which state is
6797 * the pci interface. The dev->enable_cnt is equal zero
6798 * so we call enable+disable, wait a while and switch it on.
6799 */
6800 rc = pci_enable_device(pdev);
6801 if (rc) {
6802 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
6803 return -ENODEV;
6804 }
6805 pci_disable_device(pdev);
6806 msleep(260); /* a randomly chosen number */
6807 rc = pci_enable_device(pdev);
6808 if (rc) {
6809 dev_warn(&pdev->dev, "failed to enable device.\n");
6810 return -ENODEV;
6811 }
4fa604e1 6812
859c75ab 6813 pci_set_master(pdev);
4fa604e1 6814
3b747298
TH		 6815 vaddr = pci_ioremap_bar(pdev, 0);
6816 if (vaddr == NULL) {
6817 rc = -ENOMEM;
6818 goto out_disable;
6819 }
6820 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
6821 iounmap(vaddr);
6822
1df8552a 6823 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 6824 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 6825
1df8552a
SC		 6826 /* -ENOTSUPP here means we cannot reset the controller
6827 * but it's already (and still) up and running in
18867659
SC		 6828 * "performant mode". Or, it might be 640x, which can't reset
6829 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 6830 */
adf1b3a3 6831 if (rc)
132aa220 6832 goto out_disable;
4c2a8c40
SC		 6833
6834 /* Now try to get the controller to respond to a no-op */
1ba66c9c 6835 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6836 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6837 if (hpsa_noop(pdev) == 0)
6838 break;
6839 else
6840 dev_warn(&pdev->dev, "no-op failed%s\n",
6841 (i < 11 ? "; re-trying" : ""));
6842 }
132aa220
TH		 6843
6844out_disable:
6845
6846 pci_disable_device(pdev);
6847 return rc;
4c2a8c40
SC		 6848}
6849
d37ffbe4 6850static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6851{
6852 h->cmd_pool_bits = kzalloc(
6853 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6854 sizeof(unsigned long), GFP_KERNEL);
6855 h->cmd_pool = pci_alloc_consistent(h->pdev,
6856 h->nr_cmds * sizeof(*h->cmd_pool),
6857 &(h->cmd_pool_dhandle));
6858 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6859 h->nr_cmds * sizeof(*h->errinfo_pool),
6860 &(h->errinfo_pool_dhandle));
6861 if ((h->cmd_pool_bits == NULL)
6862 || (h->cmd_pool == NULL)
6863 || (h->errinfo_pool == NULL)) {
6864 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 6865 goto clean_up;
2e9d1b36 6866 }
360c73bd 6867 hpsa_preinitialize_commands(h);
2e9d1b36 6868 return 0;
2c143342
RE		 6869clean_up:
6870 hpsa_free_cmd_pool(h);
6871 return -ENOMEM;
2e9d1b36
SC		 6872}
6873
6874static void hpsa_free_cmd_pool(struct ctlr_info *h)
6875{
6876 kfree(h->cmd_pool_bits);
6877 if (h->cmd_pool)
6878 pci_free_consistent(h->pdev,
6879 h->nr_cmds * sizeof(struct CommandList),
6880 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 6881 if (h->ioaccel2_cmd_pool)
6882 pci_free_consistent(h->pdev,
6883 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6884 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 6885 if (h->errinfo_pool)
6886 pci_free_consistent(h->pdev,
6887 h->nr_cmds * sizeof(struct ErrorInfo),
6888 h->errinfo_pool,
6889 h->errinfo_pool_dhandle);
e1f7de0c
MG		 6890 if (h->ioaccel_cmd_pool)
6891 pci_free_consistent(h->pdev,
6892 h->nr_cmds * sizeof(struct io_accel1_cmd),
6893 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 6894}
6895
41b3cf08
SC		 6896static void hpsa_irq_affinity_hints(struct ctlr_info *h)
6897{
ec429952 6898 int i, cpu;
41b3cf08
SC		 6899
6900 cpu = cpumask_first(cpu_online_mask);
6901 for (i = 0; i < h->msix_vector; i++) {
ec429952 6902 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 6903 cpu = cpumask_next(cpu, cpu_online_mask);
6904 }
6905}
6906
ec501a18
RE		 6907/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
6908static void hpsa_free_irqs(struct ctlr_info *h)
6909{
6910 int i;
6911
6912 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6913 /* Single reply queue, only one irq to free */
6914 i = h->intr_mode;
6915 irq_set_affinity_hint(h->intr[i], NULL);
6916 free_irq(h->intr[i], &h->q[i]);
6917 return;
6918 }
6919
6920 for (i = 0; i < h->msix_vector; i++) {
6921 irq_set_affinity_hint(h->intr[i], NULL);
6922 free_irq(h->intr[i], &h->q[i]);
6923 }
a4e17fc1
RE		 6924 for (; i < MAX_REPLY_QUEUES; i++)
6925 h->q[i] = 0;
ec501a18
RE		 6926}
6927
9ee61794
RE		 6928/* returns 0 on success; cleans up and returns -Enn on error */
6929static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 6930 irqreturn_t (*msixhandler)(int, void *),
6931 irqreturn_t (*intxhandler)(int, void *))
6932{
254f796b 6933 int rc, i;
0ae01a32 6934
254f796b
MG		 6935 /*
6936 * initialize h->q[x] = x so that interrupt handlers know which
6937 * queue to process.
6938 */
6939 for (i = 0; i < MAX_REPLY_QUEUES; i++)
6940 h->q[i] = (u8) i;
6941
eee0f03a 6942 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 6943 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 6944 for (i = 0; i < h->msix_vector; i++) {
254f796b
MG		 6945 rc = request_irq(h->intr[i], msixhandler,
6946 0, h->devname,
6947 &h->q[i]);
a4e17fc1
RE		 6948 if (rc) {
6949 int j;
6950
6951 dev_err(&h->pdev->dev,
6952 "failed to get irq %d for %s\n",
6953 h->intr[i], h->devname);
6954 for (j = 0; j < i; j++) {
6955 free_irq(h->intr[j], &h->q[j]);
6956 h->q[j] = 0;
6957 }
6958 for (; j < MAX_REPLY_QUEUES; j++)
6959 h->q[j] = 0;
6960 return rc;
6961 }
6962 }
41b3cf08 6963 hpsa_irq_affinity_hints(h);
254f796b
MG		 6964 } else {
6965 /* Use single reply pool */
eee0f03a 6966 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 6967 rc = request_irq(h->intr[h->intr_mode],
6968 msixhandler, 0, h->devname,
6969 &h->q[h->intr_mode]);
6970 } else {
6971 rc = request_irq(h->intr[h->intr_mode],
6972 intxhandler, IRQF_SHARED, h->devname,
6973 &h->q[h->intr_mode]);
6974 }
6975 }
0ae01a32
SC		 6976 if (rc) {
6977 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
6978 h->intr[h->intr_mode], h->devname);
6979 return -ENODEV;
6980 }
6981 return 0;
6982}
6983
6f039790 6984static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 6985{
6986 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6987 HPSA_RESET_TYPE_CONTROLLER)) {
6988 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6989 return -EIO;
6990 }
6991
6992 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6993 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6994 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6995 return -1;
6996 }
6997
6998 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6999 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
7000 dev_warn(&h->pdev->dev, "Board failed to become ready "
7001 "after soft reset.\n");
7002 return -1;
7003 }
7004
7005 return 0;
7006}
7007
072b0518
SC		 7008static void hpsa_free_reply_queues(struct ctlr_info *h)
7009{
7010 int i;
7011
7012 for (i = 0; i < h->nreply_queues; i++) {
7013 if (!h->reply_queue[i].head)
7014 continue;
7015 pci_free_consistent(h->pdev, h->reply_queue_size,
7016 h->reply_queue[i].head, h->reply_queue[i].busaddr);
7017 h->reply_queue[i].head = NULL;
7018 h->reply_queue[i].busaddr = 0;
7019 }
7020}
7021
0097f0f4
SC		 7022static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
7023{
cc64c817 7024 hpsa_free_irqs(h);
64670ac8
SC		 7025 hpsa_free_sg_chain_blocks(h);
7026 hpsa_free_cmd_pool(h);
e1f7de0c 7027 kfree(h->ioaccel1_blockFetchTable);
64670ac8 7028 kfree(h->blockFetchTable);
072b0518 7029 hpsa_free_reply_queues(h);
64670ac8
SC		 7030 if (h->vaddr)
7031 iounmap(h->vaddr);
7032 if (h->transtable)
7033 iounmap(h->transtable);
7034 if (h->cfgtable)
7035 iounmap(h->cfgtable);
cc64c817 7036 hpsa_disable_interrupt_mode(h);
132aa220 7037 pci_disable_device(h->pdev);
64670ac8
SC		 7038 pci_release_regions(h->pdev);
7039 kfree(h);
7040}
7041
a0c12413 7042/* Called when controller lockup detected. */
f2405db8 7043static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 7044{
281a7fd0
WS		 7045 int i, refcount;
7046 struct CommandList *c;
25163bd5 7047 int failcount = 0;
a0c12413 7048
080ef1cc 7049 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 7050 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7051 c = h->cmd_pool + i;
281a7fd0
WS		 7052 refcount = atomic_inc_return(&c->refcount);
7053 if (refcount > 1) {
25163bd5 7054 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 7055 finish_cmd(c);
433b5f4d 7056 atomic_dec(&h->commands_outstanding);
25163bd5 7057 failcount++;
281a7fd0
WS		 7058 }
7059 cmd_free(h, c);
a0c12413 7060 }
25163bd5
WS		 7061 dev_warn(&h->pdev->dev,
7062 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 7063}
7064
094963da
SC		 7065static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
7066{
c8ed0010 7067 int cpu;
094963da 7068
c8ed0010 7069 for_each_online_cpu(cpu) {
094963da
SC		 7070 u32 *lockup_detected;
7071 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
7072 *lockup_detected = value;
094963da
SC		 7073 }
7074 wmb(); /* be sure the per-cpu variables are out to memory */
7075}
7076
a0c12413
SC		 7077static void controller_lockup_detected(struct ctlr_info *h)
7078{
7079 unsigned long flags;
094963da 7080 u32 lockup_detected;
a0c12413 7081
a0c12413
SC		 7082 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7083 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 7084 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
7085 if (!lockup_detected) {
7086 /* no heartbeat, but controller gave us a zero. */
7087 dev_warn(&h->pdev->dev,
25163bd5
WS		 7088 "lockup detected after %d but scratchpad register is zero\n",
7089 h->heartbeat_sample_interval / HZ);
094963da
SC		 7090 lockup_detected = 0xffffffff;
7091 }
7092 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 7093 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 7094 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
7095 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 7096 pci_disable_device(h->pdev);
f2405db8 7097 fail_all_outstanding_cmds(h);
a0c12413
SC		 7098}
7099
25163bd5 7100static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 7101{
7102 u64 now;
7103 u32 heartbeat;
7104 unsigned long flags;
7105
a0c12413
SC		 7106 now = get_jiffies_64();
7107 /* If we've received an interrupt recently, we're ok. */
7108 if (time_after64(h->last_intr_timestamp +
e85c5974 7109 (h->heartbeat_sample_interval), now))
25163bd5 7110 return false;
a0c12413
SC		 7111
7112 /*
7113 * If we've already checked the heartbeat recently, we're ok.
7114 * This could happen if someone sends us a signal. We
7115 * otherwise don't care about signals in this thread.
7116 */
7117 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 7118 (h->heartbeat_sample_interval), now))
25163bd5 7119 return false;
a0c12413
SC		 7120
7121 /* If heartbeat has not changed since we last looked, we're not ok. */
7122 spin_lock_irqsave(&h->lock, flags);
7123 heartbeat = readl(&h->cfgtable->HeartBeat);
7124 spin_unlock_irqrestore(&h->lock, flags);
7125 if (h->last_heartbeat == heartbeat) {
7126 controller_lockup_detected(h);
25163bd5 7127 return true;
a0c12413
SC		 7128 }
7129
7130 /* We're ok. */
7131 h->last_heartbeat = heartbeat;
7132 h->last_heartbeat_timestamp = now;
25163bd5 7133 return false;
a0c12413
SC		 7134}
7135
9846590e 7136static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 7137{
7138 int i;
7139 char *event_type;
7140
e4aa3e6a
SC		 7141 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7142 return;
7143
76438d08 7144 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 7145 if ((h->transMethod & (CFGTBL_Trans_io_accel1
7146 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 7147 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
7148 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
7149
7150 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
7151 event_type = "state change";
7152 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
7153 event_type = "configuration change";
7154 /* Stop sending new RAID offload reqs via the IO accelerator */
7155 scsi_block_requests(h->scsi_host);
7156 for (i = 0; i < h->ndevices; i++)
7157 h->dev[i]->offload_enabled = 0;
23100dd9 7158 hpsa_drain_accel_commands(h);
76438d08
SC		 7159 /* Set 'accelerator path config change' bit */
7160 dev_warn(&h->pdev->dev,
7161 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7162 h->events, event_type);
7163 writel(h->events, &(h->cfgtable->clear_event_notify));
7164 /* Set the "clear event notify field update" bit 6 */
7165 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7166 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7167 hpsa_wait_for_clear_event_notify_ack(h);
7168 scsi_unblock_requests(h->scsi_host);
7169 } else {
7170 /* Acknowledge controller notification events. */
7171 writel(h->events, &(h->cfgtable->clear_event_notify));
7172 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7173 hpsa_wait_for_clear_event_notify_ack(h);
7174#if 0
7175 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7176 hpsa_wait_for_mode_change_ack(h);
7177#endif
7178 }
9846590e 7179 return;
76438d08
SC		 7180}
7181
7182/* Check a register on the controller to see if there are configuration
7183 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 7184 * we should rescan the controller for devices.
7185 * Also check flag for driver-initiated rescan.
76438d08 7186 */
9846590e 7187static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08
SC		 7188{
7189 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 7190 return 0;
76438d08
SC		 7191
7192 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 7193 return h->events & RESCAN_REQUIRED_EVENT_BITS;
7194}
76438d08 7195
9846590e
SC		 7196/*
7197 * Check if any of the offline devices have become ready
7198 */
7199static int hpsa_offline_devices_ready(struct ctlr_info *h)
7200{
7201 unsigned long flags;
7202 struct offline_device_entry *d;
7203 struct list_head *this, *tmp;
7204
7205 spin_lock_irqsave(&h->offline_device_lock, flags);
7206 list_for_each_safe(this, tmp, &h->offline_device_list) {
7207 d = list_entry(this, struct offline_device_entry,
7208 offline_list);
7209 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 7210 if (!hpsa_volume_offline(h, d->scsi3addr)) {
7211 spin_lock_irqsave(&h->offline_device_lock, flags);
7212 list_del(&d->offline_list);
7213 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 7214 return 1;
d1fea47c 7215 }
9846590e
SC		 7216 spin_lock_irqsave(&h->offline_device_lock, flags);
7217 }
7218 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7219 return 0;
76438d08
SC		 7220}
7221
6636e7f4 7222static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 7223{
7224 unsigned long flags;
8a98db73 7225 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 7226 struct ctlr_info, rescan_ctlr_work);
7227
7228
7229 if (h->remove_in_progress)
8a98db73 7230 return;
9846590e
SC		 7231
7232 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
7233 scsi_host_get(h->scsi_host);
9846590e
SC		 7234 hpsa_ack_ctlr_events(h);
7235 hpsa_scan_start(h->scsi_host);
7236 scsi_host_put(h->scsi_host);
7237 }
8a98db73 7238 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 7239 if (!h->remove_in_progress)
7240 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7241 h->heartbeat_sample_interval);
7242 spin_unlock_irqrestore(&h->lock, flags);
7243}
7244
7245static void hpsa_monitor_ctlr_worker(struct work_struct *work)
7246{
7247 unsigned long flags;
7248 struct ctlr_info *h = container_of(to_delayed_work(work),
7249 struct ctlr_info, monitor_ctlr_work);
7250
7251 detect_controller_lockup(h);
7252 if (lockup_detected(h))
a0c12413 7253 return;
6636e7f4
DB		 7254
7255 spin_lock_irqsave(&h->lock, flags);
7256 if (!h->remove_in_progress)
7257 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 7258 h->heartbeat_sample_interval);
7259 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 7260}
7261
6636e7f4
DB		 7262static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
7263 char *name)
7264{
7265 struct workqueue_struct *wq = NULL;
6636e7f4 7266
397ea9cb 7267 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 7268 if (!wq)
7269 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
7270
7271 return wq;
7272}
7273
6f039790 7274static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 7275{
4c2a8c40 7276 int dac, rc;
edd16368 7277 struct ctlr_info *h;
64670ac8
SC		 7278 int try_soft_reset = 0;
7279 unsigned long flags;
6b6c1cd7 7280 u32 board_id;
edd16368
SC		 7281
7282 if (number_of_controllers == 0)
7283 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 7284
6b6c1cd7
TH		 7285 rc = hpsa_lookup_board_id(pdev, &board_id);
7286 if (rc < 0) {
7287 dev_warn(&pdev->dev, "Board ID not found\n");
7288 return rc;
7289 }
7290
7291 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 7292 if (rc) {
7293 if (rc != -ENOTSUPP)
7294 return rc;
7295 /* If the reset fails in a particular way (it has no way to do
7296 * a proper hard reset, so returns -ENOTSUPP) we can try to do
7297 * a soft reset once we get the controller configured up to the
7298 * point that it can accept a command.
7299 */
7300 try_soft_reset = 1;
7301 rc = 0;
7302 }
7303
7304reinit_after_soft_reset:
edd16368 7305
303932fd
DB		 7306 /* Command structures must be aligned on a 32-byte boundary because
7307 * the 5 lower bits of the address are used by the hardware. and by
7308 * the driver. See comments in hpsa.h for more info.
7309 */
303932fd 7310 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 7311 h = kzalloc(sizeof(*h), GFP_KERNEL);
7312 if (!h)
ecd9aad4 7313 return -ENOMEM;
edd16368 7314
55c06c71 7315 h->pdev = pdev;
a9a3a273 7316 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 7317 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 7318 spin_lock_init(&h->lock);
9846590e 7319 spin_lock_init(&h->offline_device_lock);
6eaf46fd 7320 spin_lock_init(&h->scan_lock);
34f0c627 7321 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 7322 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da 7323
6636e7f4
DB		 7324 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
7325 if (!h->rescan_ctlr_wq) {
7326 rc = -ENOMEM;
7327 goto clean1;
7328 }
7329
7330 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
080ef1cc 7331 if (!h->resubmit_wq) {
080ef1cc
DB		 7332 rc = -ENOMEM;
7333 goto clean1;
7334 }
6636e7f4 7335
094963da
SC		 7336 /* Allocate and clear per-cpu variable lockup_detected */
7337 h->lockup_detected = alloc_percpu(u32);
2a5ac326
SC		 7338 if (!h->lockup_detected) {
7339 rc = -ENOMEM;
094963da 7340 goto clean1;
2a5ac326 7341 }
094963da
SC		 7342 set_lockup_detected_for_all_cpus(h, 0);
7343
55c06c71 7344 rc = hpsa_pci_init(h);
ecd9aad4 7345 if (rc != 0)
edd16368
SC		 7346 goto clean1;
7347
f79cfec6 7348 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 7349 h->ctlr = number_of_controllers;
7350 number_of_controllers++;
edd16368
SC		 7351
7352 /* configure PCI DMA stuff */
ecd9aad4
SC		 7353 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
7354 if (rc == 0) {
edd16368 7355 dac = 1;
ecd9aad4
SC		 7356 } else {
7357 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7358 if (rc == 0) {
7359 dac = 0;
7360 } else {
7361 dev_err(&pdev->dev, "no suitable DMA available\n");
7362 goto clean1;
7363 }
edd16368
SC		 7364 }
7365
7366 /* make sure the board interrupts are off */
7367 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 7368
9ee61794 7369 if (hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 7370 goto clean2;
303932fd
DB		 7371 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
7372 h->devname, pdev->device,
a9a3a273 7373 h->intr[h->intr_mode], dac ? "" : " not");
d37ffbe4 7374 rc = hpsa_alloc_cmd_pool(h);
8947fd10
RE		 7375 if (rc)
7376 goto clean2_and_free_irqs;
33a2ffce
SC		 7377 if (hpsa_allocate_sg_chain_blocks(h))
7378 goto clean4;
a08a8471 7379 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 7380 init_waitqueue_head(&h->abort_cmd_wait_queue);
a08a8471 7381 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 7382
7383 pci_set_drvdata(pdev, h);
9a41338e 7384 h->ndevices = 0;
316b221a 7385 h->hba_mode_enabled = 0;
9a41338e
SC		 7386 h->scsi_host = NULL;
7387 spin_lock_init(&h->devlock);
64670ac8
SC		 7388 hpsa_put_ctlr_into_performant_mode(h);
7389
7390 /* At this point, the controller is ready to take commands.
7391 * Now, if reset_devices and the hard reset didn't work, try
7392 * the soft reset and see if that works.
7393 */
7394 if (try_soft_reset) {
7395
7396 /* This is kind of gross. We may or may not get a completion
7397 * from the soft reset command, and if we do, then the value
7398 * from the fifo may or may not be valid. So, we wait 10 secs
7399 * after the reset throwing away any completions we get during
7400 * that time. Unregister the interrupt handler and register
7401 * fake ones to scoop up any residual completions.
7402 */
7403 spin_lock_irqsave(&h->lock, flags);
7404 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7405 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 7406 hpsa_free_irqs(h);
9ee61794 7407 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 7408 hpsa_intx_discard_completions);
7409 if (rc) {
9ee61794
RE		 7410 dev_warn(&h->pdev->dev,
7411 "Failed to request_irq after soft reset.\n");
64670ac8
SC		 7412 goto clean4;
7413 }
7414
7415 rc = hpsa_kdump_soft_reset(h);
7416 if (rc)
7417 /* Neither hard nor soft reset worked, we're hosed. */
7418 goto clean4;
7419
7420 dev_info(&h->pdev->dev, "Board READY.\n");
7421 dev_info(&h->pdev->dev,
7422 "Waiting for stale completions to drain.\n");
7423 h->access.set_intr_mask(h, HPSA_INTR_ON);
7424 msleep(10000);
7425 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7426
7427 rc = controller_reset_failed(h->cfgtable);
7428 if (rc)
7429 dev_info(&h->pdev->dev,
7430 "Soft reset appears to have failed.\n");
7431
7432 /* since the controller's reset, we have to go back and re-init
7433 * everything. Easiest to just forget what we've done and do it
7434 * all over again.
7435 */
7436 hpsa_undo_allocations_after_kdump_soft_reset(h);
7437 try_soft_reset = 0;
7438 if (rc)
7439 /* don't go to clean4, we already unallocated */
7440 return -ENODEV;
7441
7442 goto reinit_after_soft_reset;
7443 }
edd16368 7444
316b221a
SC		 7445 /* Enable Accelerated IO path at driver layer */
7446 h->acciopath_status = 1;
da0697bd 7447
e863d68e 7448
edd16368
SC		 7449 /* Turn the interrupts on so we can service requests */
7450 h->access.set_intr_mask(h, HPSA_INTR_ON);
7451
339b2b14 7452 hpsa_hba_inquiry(h);
4a4384ce
SC		 7453 rc = hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
7454 if (rc)
7455 goto clean4;
8a98db73
SC		 7456
7457 /* Monitor the controller for firmware lockups */
7458 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
7459 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
7460 schedule_delayed_work(&h->monitor_ctlr_work,
7461 h->heartbeat_sample_interval);
6636e7f4
DB		 7462 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
7463 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7464 h->heartbeat_sample_interval);
88bf6d62 7465 return 0;
edd16368
SC		 7466
7467clean4:
33a2ffce 7468 hpsa_free_sg_chain_blocks(h);
2e9d1b36 7469 hpsa_free_cmd_pool(h);
8947fd10 7470clean2_and_free_irqs:
ec501a18 7471 hpsa_free_irqs(h);
edd16368
SC		 7472clean2:
7473clean1:
080ef1cc
DB		 7474 if (h->resubmit_wq)
7475 destroy_workqueue(h->resubmit_wq);
6636e7f4
DB		 7476 if (h->rescan_ctlr_wq)
7477 destroy_workqueue(h->rescan_ctlr_wq);
094963da
SC		 7478 if (h->lockup_detected)
7479 free_percpu(h->lockup_detected);
edd16368 7480 kfree(h);
ecd9aad4 7481 return rc;
edd16368
SC		 7482}
7483
7484static void hpsa_flush_cache(struct ctlr_info *h)
7485{
7486 char *flush_buf;
7487 struct CommandList *c;
25163bd5 7488 int rc;
702890e3
SC		 7489
7490 /* Don't bother trying to flush the cache if locked up */
25163bd5 7491 /* FIXME not necessary if do_simple_cmd does the check */
094963da 7492 if (unlikely(lockup_detected(h)))
702890e3 7493 return;
edd16368
SC		 7494 flush_buf = kzalloc(4, GFP_KERNEL);
7495 if (!flush_buf)
7496 return;
7497
45fcb86e 7498 c = cmd_alloc(h);
edd16368 7499 if (!c) {
45fcb86e 7500 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 7501 goto out_of_memory;
7502 }
a2dac136
SC		 7503 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
7504 RAID_CTLR_LUNID, TYPE_CMD)) {
7505 goto out;
7506 }
25163bd5
WS		 7507 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
7508 PCI_DMA_TODEVICE, NO_TIMEOUT);
7509 if (rc)
7510 goto out;
edd16368 7511 if (c->err_info->CommandStatus != 0)
a2dac136 7512out:
edd16368
SC		 7513 dev_warn(&h->pdev->dev,
7514 "error flushing cache on controller\n");
45fcb86e 7515 cmd_free(h, c);
edd16368
SC		 7516out_of_memory:
7517 kfree(flush_buf);
7518}
7519
7520static void hpsa_shutdown(struct pci_dev *pdev)
7521{
7522 struct ctlr_info *h;
7523
7524 h = pci_get_drvdata(pdev);
7525 /* Turn board interrupts off and send the flush cache command
7526 * sendcmd will turn off interrupt, and send the flush...
7527 * To write all data in the battery backed cache to disks
7528 */
7529 hpsa_flush_cache(h);
7530 h->access.set_intr_mask(h, HPSA_INTR_OFF);
cc64c817
RE		 7531 hpsa_free_irqs(h);
7532 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 7533}
7534
6f039790 7535static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 7536{
7537 int i;
7538
7539 for (i = 0; i < h->ndevices; i++)
7540 kfree(h->dev[i]);
7541}
7542
6f039790 7543static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 7544{
7545 struct ctlr_info *h;
8a98db73 7546 unsigned long flags;
edd16368
SC		 7547
7548 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 7549 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 7550 return;
7551 }
7552 h = pci_get_drvdata(pdev);
8a98db73
SC		 7553
7554 /* Get rid of any controller monitoring work items */
7555 spin_lock_irqsave(&h->lock, flags);
7556 h->remove_in_progress = 1;
8a98db73 7557 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 7558 cancel_delayed_work_sync(&h->monitor_ctlr_work);
7559 cancel_delayed_work_sync(&h->rescan_ctlr_work);
7560 destroy_workqueue(h->rescan_ctlr_wq);
7561 destroy_workqueue(h->resubmit_wq);
edd16368 7562 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
cc64c817
RE		 7563
7564 /* includes hpsa_free_irqs and hpsa_disable_interrupt_mode */
edd16368 7565 hpsa_shutdown(pdev);
cc64c817 7566
edd16368 7567 iounmap(h->vaddr);
204892e9
SC		 7568 iounmap(h->transtable);
7569 iounmap(h->cfgtable);
55e14e76 7570 hpsa_free_device_info(h);
33a2ffce 7571 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 7572 pci_free_consistent(h->pdev,
7573 h->nr_cmds * sizeof(struct CommandList),
7574 h->cmd_pool, h->cmd_pool_dhandle);
7575 pci_free_consistent(h->pdev,
7576 h->nr_cmds * sizeof(struct ErrorInfo),
7577 h->errinfo_pool, h->errinfo_pool_dhandle);
072b0518 7578 hpsa_free_reply_queues(h);
edd16368 7579 kfree(h->cmd_pool_bits);
303932fd 7580 kfree(h->blockFetchTable);
e1f7de0c 7581 kfree(h->ioaccel1_blockFetchTable);
aca9012a 7582 kfree(h->ioaccel2_blockFetchTable);
339b2b14 7583 kfree(h->hba_inquiry_data);
f0bd0b68 7584 pci_disable_device(pdev);
edd16368 7585 pci_release_regions(pdev);
094963da 7586 free_percpu(h->lockup_detected);
edd16368
SC		 7587 kfree(h);
7588}
7589
7590static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
7591 __attribute__((unused)) pm_message_t state)
7592{
7593 return -ENOSYS;
7594}
7595
7596static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
7597{
7598 return -ENOSYS;
7599}
7600
7601static struct pci_driver hpsa_pci_driver = {
f79cfec6 7602 .name = HPSA,
edd16368 7603 .probe = hpsa_init_one,
6f039790 7604 .remove = hpsa_remove_one,
edd16368
SC		 7605 .id_table = hpsa_pci_device_id, /* id_table */
7606 .shutdown = hpsa_shutdown,
7607 .suspend = hpsa_suspend,
7608 .resume = hpsa_resume,
7609};
7610
303932fd
DB		 7611/* Fill in bucket_map[], given nsgs (the max number of
7612 * scatter gather elements supported) and bucket[],
7613 * which is an array of 8 integers. The bucket[] array
7614 * contains 8 different DMA transfer sizes (in 16
7615 * byte increments) which the controller uses to fetch
7616 * commands. This function fills in bucket_map[], which
7617 * maps a given number of scatter gather elements to one of
7618 * the 8 DMA transfer sizes. The point of it is to allow the
7619 * controller to only do as much DMA as needed to fetch the
7620 * command, with the DMA transfer size encoded in the lower
7621 * bits of the command address.
7622 */
7623static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 7624 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 7625{
7626 int i, j, b, size;
7627
303932fd
DB		 7628 /* Note, bucket_map must have nsgs+1 entries. */
7629 for (i = 0; i <= nsgs; i++) {
7630 /* Compute size of a command with i SG entries */
e1f7de0c 7631 size = i + min_blocks;
303932fd
DB		 7632 b = num_buckets; /* Assume the biggest bucket */
7633 /* Find the bucket that is just big enough */
e1f7de0c 7634 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 7635 if (bucket[j] >= size) {
7636 b = j;
7637 break;
7638 }
7639 }
7640 /* for a command with i SG entries, use bucket b. */
7641 bucket_map[i] = b;
7642 }
7643}
7644
c706a795
RE		 7645/* return -ENODEV or other reason on error, 0 on success */
7646static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 7647{
6c311b57
SC		 7648 int i;
7649 unsigned long register_value;
e1f7de0c
MG		 7650 unsigned long transMethod = CFGTBL_Trans_Performant |
7651 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 7652 CFGTBL_Trans_enable_directed_msix |
7653 (trans_support & (CFGTBL_Trans_io_accel1 |
7654 CFGTBL_Trans_io_accel2));
e1f7de0c 7655 struct access_method access = SA5_performant_access;
def342bd
SC		 7656
7657 /* This is a bit complicated. There are 8 registers on
7658 * the controller which we write to to tell it 8 different
7659 * sizes of commands which there may be. It's a way of
7660 * reducing the DMA done to fetch each command. Encoded into
7661 * each command's tag are 3 bits which communicate to the controller
7662 * which of the eight sizes that command fits within. The size of
7663 * each command depends on how many scatter gather entries there are.
7664 * Each SG entry requires 16 bytes. The eight registers are programmed
7665 * with the number of 16-byte blocks a command of that size requires.
7666 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 7667 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 7668 * blocks. Note, this only extends to the SG entries contained
7669 * within the command block, and does not extend to chained blocks
7670 * of SG elements. bft[] contains the eight values we write to
7671 * the registers. They are not evenly distributed, but have more
7672 * sizes for small commands, and fewer sizes for larger commands.
7673 */
d66ae08b 7674 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 7675#define MIN_IOACCEL2_BFT_ENTRY 5
7676#define HPSA_IOACCEL2_HEADER_SZ 4
7677 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
7678 13, 14, 15, 16, 17, 18, 19,
7679 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
7680 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
7681 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
7682 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
7683 16 * MIN_IOACCEL2_BFT_ENTRY);
7684 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 7685 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 7686 /* 5 = 1 s/g entry or 4k
7687 * 6 = 2 s/g entry or 8k
7688 * 8 = 4 s/g entry or 16k
7689 * 10 = 6 s/g entry or 24k
7690 */
303932fd 7691
b3a52e79
SC		 7692 /* If the controller supports either ioaccel method then
7693 * we can also use the RAID stack submit path that does not
7694 * perform the superfluous readl() after each command submission.
7695 */
7696 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
7697 access = SA5_performant_access_no_read;
7698
303932fd 7699 /* Controller spec: zero out this buffer. */
072b0518
SC		 7700 for (i = 0; i < h->nreply_queues; i++)
7701 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 7702
d66ae08b
SC		 7703 bft[7] = SG_ENTRIES_IN_CMD + 4;
7704 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 7705 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 7706 for (i = 0; i < 8; i++)
7707 writel(bft[i], &h->transtable->BlockFetch[i]);
7708
7709 /* size of controller ring buffer */
7710 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 7711 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 7712 writel(0, &h->transtable->RepQCtrAddrLow32);
7713 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 7714
7715 for (i = 0; i < h->nreply_queues; i++) {
7716 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 7717 writel(h->reply_queue[i].busaddr,
254f796b
MG		 7718 &h->transtable->RepQAddr[i].lower);
7719 }
7720
b9af4937 7721 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 7722 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
7723 /*
7724 * enable outbound interrupt coalescing in accelerator mode;
7725 */
7726 if (trans_support & CFGTBL_Trans_io_accel1) {
7727 access = SA5_ioaccel_mode1_access;
7728 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7729 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 7730 } else {
7731 if (trans_support & CFGTBL_Trans_io_accel2) {
7732 access = SA5_ioaccel_mode2_access;
7733 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7734 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
7735 }
e1f7de0c 7736 }
303932fd 7737 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7738 if (hpsa_wait_for_mode_change_ack(h)) {
7739 dev_err(&h->pdev->dev,
7740 "performant mode problem - doorbell timeout\n");
7741 return -ENODEV;
7742 }
303932fd
DB		 7743 register_value = readl(&(h->cfgtable->TransportActive));
7744 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 7745 dev_err(&h->pdev->dev,
7746 "performant mode problem - transport not active\n");
c706a795 7747 return -ENODEV;
303932fd 7748 }
960a30e7 7749 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 7750 h->access = access;
7751 h->transMethod = transMethod;
7752
b9af4937
SC		 7753 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
7754 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 7755 return 0;
e1f7de0c 7756
b9af4937
SC		 7757 if (trans_support & CFGTBL_Trans_io_accel1) {
7758 /* Set up I/O accelerator mode */
7759 for (i = 0; i < h->nreply_queues; i++) {
7760 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
7761 h->reply_queue[i].current_entry =
7762 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
7763 }
7764 bft[7] = h->ioaccel_maxsg + 8;
7765 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
7766 h->ioaccel1_blockFetchTable);
e1f7de0c 7767
b9af4937 7768 /* initialize all reply queue entries to unused */
072b0518
SC		 7769 for (i = 0; i < h->nreply_queues; i++)
7770 memset(h->reply_queue[i].head,
7771 (u8) IOACCEL_MODE1_REPLY_UNUSED,
7772 h->reply_queue_size);
e1f7de0c 7773
b9af4937
SC		 7774 /* set all the constant fields in the accelerator command
7775 * frames once at init time to save CPU cycles later.
7776 */
7777 for (i = 0; i < h->nr_cmds; i++) {
7778 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
7779
7780 cp->function = IOACCEL1_FUNCTION_SCSIIO;
7781 cp->err_info = (u32) (h->errinfo_pool_dhandle +
7782 (i * sizeof(struct ErrorInfo)));
7783 cp->err_info_len = sizeof(struct ErrorInfo);
7784 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 7785 cp->host_context_flags =
7786 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 7787 cp->timeout_sec = 0;
7788 cp->ReplyQueue = 0;
50a0decf 7789 cp->tag =
f2405db8 7790 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 7791 cp->host_addr =
7792 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 7793 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 7794 }
7795 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7796 u64 cfg_offset, cfg_base_addr_index;
7797 u32 bft2_offset, cfg_base_addr;
7798 int rc;
7799
7800 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7801 &cfg_base_addr_index, &cfg_offset);
7802 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7803 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7804 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7805 4, h->ioaccel2_blockFetchTable);
7806 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7807 BUILD_BUG_ON(offsetof(struct CfgTable,
7808 io_accel_request_size_offset) != 0xb8);
7809 h->ioaccel2_bft2_regs =
7810 remap_pci_mem(pci_resource_start(h->pdev,
7811 cfg_base_addr_index) +
7812 cfg_offset + bft2_offset,
7813 ARRAY_SIZE(bft2) *
7814 sizeof(*h->ioaccel2_bft2_regs));
7815 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7816 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7817 }
b9af4937 7818 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7819 if (hpsa_wait_for_mode_change_ack(h)) {
7820 dev_err(&h->pdev->dev,
7821 "performant mode problem - enabling ioaccel mode\n");
7822 return -ENODEV;
7823 }
7824 return 0;
e1f7de0c
MG		 7825}
7826
d37ffbe4
RE		 7827/* Allocate ioaccel1 mode command blocks and block fetch table */
7828static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 7829{
283b4a9b
SC		 7830 h->ioaccel_maxsg =
7831 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7832 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7833 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7834
e1f7de0c
MG		 7835 /* Command structures must be aligned on a 128-byte boundary
7836 * because the 7 lower bits of the address are used by the
7837 * hardware.
7838 */
e1f7de0c
MG		 7839 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7840 IOACCEL1_COMMANDLIST_ALIGNMENT);
7841 h->ioaccel_cmd_pool =
7842 pci_alloc_consistent(h->pdev,
7843 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7844 &(h->ioaccel_cmd_pool_dhandle));
7845
7846 h->ioaccel1_blockFetchTable =
283b4a9b 7847 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7848 sizeof(u32)), GFP_KERNEL);
7849
7850 if ((h->ioaccel_cmd_pool == NULL) ||
7851 (h->ioaccel1_blockFetchTable == NULL))
7852 goto clean_up;
7853
7854 memset(h->ioaccel_cmd_pool, 0,
7855 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
7856 return 0;
7857
7858clean_up:
7859 if (h->ioaccel_cmd_pool)
7860 pci_free_consistent(h->pdev,
7861 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7862 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
7863 kfree(h->ioaccel1_blockFetchTable);
7864 return 1;
6c311b57
SC		 7865}
7866
d37ffbe4
RE		 7867/* Allocate ioaccel2 mode command blocks and block fetch table */
7868static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a
SC		 7869{
7870 /* Allocate ioaccel2 mode command blocks and block fetch table */
7871
7872 h->ioaccel_maxsg =
7873 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7874 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
7875 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
7876
aca9012a
SC		 7877 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
7878 IOACCEL2_COMMANDLIST_ALIGNMENT);
7879 h->ioaccel2_cmd_pool =
7880 pci_alloc_consistent(h->pdev,
7881 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7882 &(h->ioaccel2_cmd_pool_dhandle));
7883
7884 h->ioaccel2_blockFetchTable =
7885 kmalloc(((h->ioaccel_maxsg + 1) *
7886 sizeof(u32)), GFP_KERNEL);
7887
7888 if ((h->ioaccel2_cmd_pool == NULL) ||
7889 (h->ioaccel2_blockFetchTable == NULL))
7890 goto clean_up;
7891
7892 memset(h->ioaccel2_cmd_pool, 0,
7893 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
7894 return 0;
7895
7896clean_up:
7897 if (h->ioaccel2_cmd_pool)
7898 pci_free_consistent(h->pdev,
7899 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7900 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
7901 kfree(h->ioaccel2_blockFetchTable);
7902 return 1;
7903}
7904
6f039790 7905static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 7906{
7907 u32 trans_support;
e1f7de0c
MG		 7908 unsigned long transMethod = CFGTBL_Trans_Performant |
7909 CFGTBL_Trans_use_short_tags;
254f796b 7910 int i;
6c311b57 7911
02ec19c8
SC		 7912 if (hpsa_simple_mode)
7913 return;
7914
67c99a72 7915 trans_support = readl(&(h->cfgtable->TransportSupport));
7916 if (!(trans_support & PERFORMANT_MODE))
7917 return;
7918
e1f7de0c
MG		 7919 /* Check for I/O accelerator mode support */
7920 if (trans_support & CFGTBL_Trans_io_accel1) {
7921 transMethod |= CFGTBL_Trans_io_accel1 |
7922 CFGTBL_Trans_enable_directed_msix;
d37ffbe4 7923 if (hpsa_alloc_ioaccel1_cmd_and_bft(h))
e1f7de0c 7924 goto clean_up;
aca9012a
SC		 7925 } else {
7926 if (trans_support & CFGTBL_Trans_io_accel2) {
7927 transMethod |= CFGTBL_Trans_io_accel2 |
7928 CFGTBL_Trans_enable_directed_msix;
d37ffbe4 7929 if (hpsa_alloc_ioaccel2_cmd_and_bft(h))
aca9012a
SC		 7930 goto clean_up;
7931 }
e1f7de0c
MG		 7932 }
7933
eee0f03a 7934 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 7935 hpsa_get_max_perf_mode_cmds(h);
6c311b57 7936 /* Performant mode ring buffer and supporting data structures */
072b0518 7937 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 7938
254f796b 7939 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 7940 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
7941 h->reply_queue_size,
7942 &(h->reply_queue[i].busaddr));
7943 if (!h->reply_queue[i].head)
7944 goto clean_up;
254f796b
MG		 7945 h->reply_queue[i].size = h->max_commands;
7946 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
7947 h->reply_queue[i].current_entry = 0;
7948 }
7949
6c311b57 7950 /* Need a block fetch table for performant mode */
d66ae08b 7951 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 7952 sizeof(u32)), GFP_KERNEL);
072b0518 7953 if (!h->blockFetchTable)
6c311b57
SC		 7954 goto clean_up;
7955
e1f7de0c 7956 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 7957 return;
7958
7959clean_up:
072b0518 7960 hpsa_free_reply_queues(h);
303932fd
DB		 7961 kfree(h->blockFetchTable);
7962}
7963
23100dd9 7964static int is_accelerated_cmd(struct CommandList *c)
76438d08 7965{
23100dd9
SC		 7966 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
7967}
7968
7969static void hpsa_drain_accel_commands(struct ctlr_info *h)
7970{
7971 struct CommandList *c = NULL;
f2405db8 7972 int i, accel_cmds_out;
281a7fd0 7973 int refcount;
76438d08 7974
f2405db8 7975 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 7976 accel_cmds_out = 0;
f2405db8 7977 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7978 c = h->cmd_pool + i;
281a7fd0
WS		 7979 refcount = atomic_inc_return(&c->refcount);
7980 if (refcount > 1) /* Command is allocated */
7981 accel_cmds_out += is_accelerated_cmd(c);
7982 cmd_free(h, c);
f2405db8 7983 }
23100dd9 7984 if (accel_cmds_out <= 0)
281a7fd0 7985 break;
76438d08
SC		 7986 msleep(100);
7987 } while (1);
7988}
7989
edd16368
SC		 7990/*
7991 * This is it. Register the PCI driver information for the cards we control
7992 * the OS will call our registered routines when it finds one of our cards.
7993 */
7994static int __init hpsa_init(void)
7995{
31468401 7996 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 7997}
7998
7999static void __exit hpsa_cleanup(void)
8000{
8001 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 8002}
8003
e1f7de0c
MG		 8004static void __attribute__((unused)) verify_offsets(void)
8005{
dd0e19f3
ST		 8006#define VERIFY_OFFSET(member, offset) \
8007 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
8008
8009 VERIFY_OFFSET(structure_size, 0);
8010 VERIFY_OFFSET(volume_blk_size, 4);
8011 VERIFY_OFFSET(volume_blk_cnt, 8);
8012 VERIFY_OFFSET(phys_blk_shift, 16);
8013 VERIFY_OFFSET(parity_rotation_shift, 17);
8014 VERIFY_OFFSET(strip_size, 18);
8015 VERIFY_OFFSET(disk_starting_blk, 20);
8016 VERIFY_OFFSET(disk_blk_cnt, 28);
8017 VERIFY_OFFSET(data_disks_per_row, 36);
8018 VERIFY_OFFSET(metadata_disks_per_row, 38);
8019 VERIFY_OFFSET(row_cnt, 40);
8020 VERIFY_OFFSET(layout_map_count, 42);
8021 VERIFY_OFFSET(flags, 44);
8022 VERIFY_OFFSET(dekindex, 46);
8023 /* VERIFY_OFFSET(reserved, 48 */
8024 VERIFY_OFFSET(data, 64);
8025
8026#undef VERIFY_OFFSET
8027
b66cc250
MM		 8028#define VERIFY_OFFSET(member, offset) \
8029 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
8030
8031 VERIFY_OFFSET(IU_type, 0);
8032 VERIFY_OFFSET(direction, 1);
8033 VERIFY_OFFSET(reply_queue, 2);
8034 /* VERIFY_OFFSET(reserved1, 3); */
8035 VERIFY_OFFSET(scsi_nexus, 4);
8036 VERIFY_OFFSET(Tag, 8);
8037 VERIFY_OFFSET(cdb, 16);
8038 VERIFY_OFFSET(cciss_lun, 32);
8039 VERIFY_OFFSET(data_len, 40);
8040 VERIFY_OFFSET(cmd_priority_task_attr, 44);
8041 VERIFY_OFFSET(sg_count, 45);
8042 /* VERIFY_OFFSET(reserved3 */
8043 VERIFY_OFFSET(err_ptr, 48);
8044 VERIFY_OFFSET(err_len, 56);
8045 /* VERIFY_OFFSET(reserved4 */
8046 VERIFY_OFFSET(sg, 64);
8047
8048#undef VERIFY_OFFSET
8049
e1f7de0c
MG		 8050#define VERIFY_OFFSET(member, offset) \
8051 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
8052
8053 VERIFY_OFFSET(dev_handle, 0x00);
8054 VERIFY_OFFSET(reserved1, 0x02);
8055 VERIFY_OFFSET(function, 0x03);
8056 VERIFY_OFFSET(reserved2, 0x04);
8057 VERIFY_OFFSET(err_info, 0x0C);
8058 VERIFY_OFFSET(reserved3, 0x10);
8059 VERIFY_OFFSET(err_info_len, 0x12);
8060 VERIFY_OFFSET(reserved4, 0x13);
8061 VERIFY_OFFSET(sgl_offset, 0x14);
8062 VERIFY_OFFSET(reserved5, 0x15);
8063 VERIFY_OFFSET(transfer_len, 0x1C);
8064 VERIFY_OFFSET(reserved6, 0x20);
8065 VERIFY_OFFSET(io_flags, 0x24);
8066 VERIFY_OFFSET(reserved7, 0x26);
8067 VERIFY_OFFSET(LUN, 0x34);
8068 VERIFY_OFFSET(control, 0x3C);
8069 VERIFY_OFFSET(CDB, 0x40);
8070 VERIFY_OFFSET(reserved8, 0x50);
8071 VERIFY_OFFSET(host_context_flags, 0x60);
8072 VERIFY_OFFSET(timeout_sec, 0x62);
8073 VERIFY_OFFSET(ReplyQueue, 0x64);
8074 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 8075 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 8076 VERIFY_OFFSET(host_addr, 0x70);
8077 VERIFY_OFFSET(CISS_LUN, 0x78);
8078 VERIFY_OFFSET(SG, 0x78 + 8);
8079#undef VERIFY_OFFSET
8080}
8081
edd16368
SC		 8082module_init(hpsa_init);
8083module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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