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scsi_lib: Decode T10 vendor IDs
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
94c7bc31 3 * Copyright 2016 Microsemi Corporation
1358f6dc
DB		 4 * Copyright 2014-2015 PMC-Sierra, Inc.
5 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
edd16368
SC		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
14 * NON INFRINGEMENT. See the GNU General Public License for more details.
15 *
94c7bc31 16 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
edd16368
SC		 17 *
18 */
19
20#include <linux/module.h>
21#include <linux/interrupt.h>
22#include <linux/types.h>
23#include <linux/pci.h>
e5a44df8 24#include <linux/pci-aspm.h>
edd16368
SC		 25#include <linux/kernel.h>
26#include <linux/slab.h>
27#include <linux/delay.h>
28#include <linux/fs.h>
29#include <linux/timer.h>
edd16368
SC		 30#include <linux/init.h>
31#include <linux/spinlock.h>
edd16368
SC		 32#include <linux/compat.h>
33#include <linux/blktrace_api.h>
34#include <linux/uaccess.h>
35#include <linux/io.h>
36#include <linux/dma-mapping.h>
37#include <linux/completion.h>
38#include <linux/moduleparam.h>
39#include <scsi/scsi.h>
40#include <scsi/scsi_cmnd.h>
41#include <scsi/scsi_device.h>
42#include <scsi/scsi_host.h>
667e23d4 43#include <scsi/scsi_tcq.h>
9437ac43 44#include <scsi/scsi_eh.h>
d04e62b9 45#include <scsi/scsi_transport_sas.h>
73153fe5 46#include <scsi/scsi_dbg.h>
edd16368
SC		 47#include <linux/cciss_ioctl.h>
48#include <linux/string.h>
49#include <linux/bitmap.h>
60063497 50#include <linux/atomic.h>
a0c12413 51#include <linux/jiffies.h>
42a91641 52#include <linux/percpu-defs.h>
094963da 53#include <linux/percpu.h>
2b08b3e9 54#include <asm/unaligned.h>
283b4a9b 55#include <asm/div64.h>
edd16368
SC		 56#include "hpsa_cmd.h"
57#include "hpsa.h"
58
ec2c3aa9
DB		 59/*
60 * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.'
61 * with an optional trailing '-' followed by a byte value (0-255).
62 */
ff54aee4 63#define HPSA_DRIVER_VERSION "3.4.16-0"
edd16368 64#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 65#define HPSA "hpsa"
edd16368 66
007e7aa9
RE		 67/* How long to wait for CISS doorbell communication */
68#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
69#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
70#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
71#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 72#define MAX_IOCTL_CONFIG_WAIT 1000
73
74/*define how many times we will try a command because of bus resets */
75#define MAX_CMD_RETRIES 3
76
77/* Embedded module documentation macros - see modules.h */
78MODULE_AUTHOR("Hewlett-Packard Company");
79MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
80 HPSA_DRIVER_VERSION);
81MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
82MODULE_VERSION(HPSA_DRIVER_VERSION);
83MODULE_LICENSE("GPL");
84
85static int hpsa_allow_any;
86module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
87MODULE_PARM_DESC(hpsa_allow_any,
88 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 89static int hpsa_simple_mode;
90module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
91MODULE_PARM_DESC(hpsa_simple_mode,
92 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 93
94/* define the PCI info for the cards we can control */
95static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 131 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
132 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
133 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
134 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
135 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
fdfa4b6d 136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
cbb47dcb
DB		 137 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
138 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
139 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
140 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
141 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
8e616a5e
SC		 142 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
143 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
144 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
145 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
146 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 147 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 148 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 149 {0,}
150};
151
152MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
153
154/* board_id = Subsystem Device ID & Vendor ID
155 * product = Marketing Name for the board
156 * access = Address of the struct of function pointers
157 */
158static struct board_type products[] = {
edd16368
SC		 159 {0x3241103C, "Smart Array P212", &SA5_access},
160 {0x3243103C, "Smart Array P410", &SA5_access},
161 {0x3245103C, "Smart Array P410i", &SA5_access},
162 {0x3247103C, "Smart Array P411", &SA5_access},
163 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 164 {0x324A103C, "Smart Array P712m", &SA5_access},
165 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 166 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 167 {0x3350103C, "Smart Array P222", &SA5_access},
168 {0x3351103C, "Smart Array P420", &SA5_access},
169 {0x3352103C, "Smart Array P421", &SA5_access},
170 {0x3353103C, "Smart Array P822", &SA5_access},
171 {0x3354103C, "Smart Array P420i", &SA5_access},
172 {0x3355103C, "Smart Array P220i", &SA5_access},
173 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 174 {0x1921103C, "Smart Array P830i", &SA5_access},
175 {0x1922103C, "Smart Array P430", &SA5_access},
176 {0x1923103C, "Smart Array P431", &SA5_access},
177 {0x1924103C, "Smart Array P830", &SA5_access},
178 {0x1926103C, "Smart Array P731m", &SA5_access},
179 {0x1928103C, "Smart Array P230i", &SA5_access},
180 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 181 {0x21BD103C, "Smart Array P244br", &SA5_access},
182 {0x21BE103C, "Smart Array P741m", &SA5_access},
183 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
184 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 185 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 186 {0x21C2103C, "Smart Array P440", &SA5_access},
187 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 188 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 189 {0x21C5103C, "Smart Array P841", &SA5_access},
190 {0x21C6103C, "Smart HBA H244br", &SA5_access},
191 {0x21C7103C, "Smart HBA H240", &SA5_access},
192 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 193 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 194 {0x21CA103C, "Smart Array P246br", &SA5_access},
195 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 196 {0x21CC103C, "Smart Array", &SA5_access},
197 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 198 {0x21CE103C, "Smart HBA", &SA5_access},
fdfa4b6d 199 {0x05809005, "SmartHBA-SA", &SA5_access},
cbb47dcb
DB		 200 {0x05819005, "SmartHBA-SA 8i", &SA5_access},
201 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
202 {0x05839005, "SmartHBA-SA 8e", &SA5_access},
203 {0x05849005, "SmartHBA-SA 16i", &SA5_access},
204 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
8e616a5e
SC		 205 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
206 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
207 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
208 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
209 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 210 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
211};
212
d04e62b9
KB		 213static struct scsi_transport_template *hpsa_sas_transport_template;
214static int hpsa_add_sas_host(struct ctlr_info *h);
215static void hpsa_delete_sas_host(struct ctlr_info *h);
216static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
217 struct hpsa_scsi_dev_t *device);
218static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device);
219static struct hpsa_scsi_dev_t
220 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
221 struct sas_rphy *rphy);
222
a58e7e53
WS		 223#define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
224static const struct scsi_cmnd hpsa_cmd_busy;
225#define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
226static const struct scsi_cmnd hpsa_cmd_idle;
edd16368
SC		 227static int number_of_controllers;
228
10f66018
SC		 229static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
230static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 231static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 232
233#ifdef CONFIG_COMPAT
42a91641
DB		 234static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
235 void __user *arg);
edd16368
SC		 236#endif
237
238static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 239static struct CommandList *cmd_alloc(struct ctlr_info *h);
73153fe5
WS		 240static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
241static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
242 struct scsi_cmnd *scmd);
a2dac136 243static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 244 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 245 int cmd_type);
2c143342 246static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 247#define VPD_PAGE (1 << 8)
b48d9804 248#define HPSA_SIMPLE_ERROR_BITS 0x03
edd16368 249
f281233d 250static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 251static void hpsa_scan_start(struct Scsi_Host *);
252static int hpsa_scan_finished(struct Scsi_Host *sh,
253 unsigned long elapsed_time);
7c0a0229 254static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 255
256static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 257static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 258static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 259static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 260static void hpsa_slave_destroy(struct scsi_device *sdev);
261
8aa60681 262static void hpsa_update_scsi_devices(struct ctlr_info *h);
edd16368
SC		 263static int check_for_unit_attention(struct ctlr_info *h,
264 struct CommandList *c);
265static void check_ioctl_unit_attention(struct ctlr_info *h,
266 struct CommandList *c);
303932fd
DB		 267/* performant mode helper functions */
268static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 269 int nsgs, int min_blocks, u32 *bucket_map);
105a3dbc
RE		 270static void hpsa_free_performant_mode(struct ctlr_info *h);
271static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 272static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 273static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
274 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
275 u64 *cfg_offset);
276static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
277 unsigned long *memory_bar);
278static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
279static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
280 int wait_for_ready);
75167d2c 281static inline void finish_cmd(struct CommandList *c);
c706a795 282static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 283#define BOARD_NOT_READY 0
284#define BOARD_READY 1
23100dd9 285static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 286static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 287static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
288 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 289 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 290static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 291static u32 lockup_detected(struct ctlr_info *h);
292static int detect_controller_lockup(struct ctlr_info *h);
c2adae44 293static void hpsa_disable_rld_caching(struct ctlr_info *h);
d04e62b9
KB		 294static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
295 struct ReportExtendedLUNdata *buf, int bufsize);
34592254 296static int hpsa_luns_changed(struct ctlr_info *h);
ba74fdc4
DB		 297static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
298 struct hpsa_scsi_dev_t *dev,
299 unsigned char *scsi3addr);
edd16368 300
edd16368
SC		 301static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
302{
303 unsigned long *priv = shost_priv(sdev->host);
304 return (struct ctlr_info *) *priv;
305}
306
a23513e8
SC		 307static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
308{
309 unsigned long *priv = shost_priv(sh);
310 return (struct ctlr_info *) *priv;
311}
312
a58e7e53
WS		 313static inline bool hpsa_is_cmd_idle(struct CommandList *c)
314{
315 return c->scsi_cmd == SCSI_CMD_IDLE;
316}
317
d604f533
WS		 318static inline bool hpsa_is_pending_event(struct CommandList *c)
319{
320 return c->abort_pending || c->reset_pending;
321}
322
9437ac43
SC		 323/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
324static void decode_sense_data(const u8 *sense_data, int sense_data_len,
325 u8 *sense_key, u8 *asc, u8 *ascq)
326{
327 struct scsi_sense_hdr sshdr;
328 bool rc;
329
330 *sense_key = -1;
331 *asc = -1;
332 *ascq = -1;
333
334 if (sense_data_len < 1)
335 return;
336
337 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
338 if (rc) {
339 *sense_key = sshdr.sense_key;
340 *asc = sshdr.asc;
341 *ascq = sshdr.ascq;
342 }
343}
344
edd16368
SC		 345static int check_for_unit_attention(struct ctlr_info *h,
346 struct CommandList *c)
347{
9437ac43
SC		 348 u8 sense_key, asc, ascq;
349 int sense_len;
350
351 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
352 sense_len = sizeof(c->err_info->SenseInfo);
353 else
354 sense_len = c->err_info->SenseLen;
355
356 decode_sense_data(c->err_info->SenseInfo, sense_len,
357 &sense_key, &asc, &ascq);
81c27557 358 if (sense_key != UNIT_ATTENTION || asc == 0xff)
edd16368
SC		 359 return 0;
360
9437ac43 361 switch (asc) {
edd16368 362 case STATE_CHANGED:
9437ac43 363 dev_warn(&h->pdev->dev,
2946e82b
RE		 364 "%s: a state change detected, command retried\n",
365 h->devname);
edd16368
SC		 366 break;
367 case LUN_FAILED:
7f73695a 368 dev_warn(&h->pdev->dev,
2946e82b 369 "%s: LUN failure detected\n", h->devname);
edd16368
SC		 370 break;
371 case REPORT_LUNS_CHANGED:
7f73695a 372 dev_warn(&h->pdev->dev,
2946e82b 373 "%s: report LUN data changed\n", h->devname);
edd16368 374 /*
4f4eb9f1
ST		 375 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
376 * target (array) devices.
edd16368
SC		 377 */
378 break;
379 case POWER_OR_RESET:
2946e82b
RE		 380 dev_warn(&h->pdev->dev,
381 "%s: a power on or device reset detected\n",
382 h->devname);
edd16368
SC		 383 break;
384 case UNIT_ATTENTION_CLEARED:
2946e82b
RE		 385 dev_warn(&h->pdev->dev,
386 "%s: unit attention cleared by another initiator\n",
387 h->devname);
edd16368
SC		 388 break;
389 default:
2946e82b
RE		 390 dev_warn(&h->pdev->dev,
391 "%s: unknown unit attention detected\n",
392 h->devname);
edd16368
SC		 393 break;
394 }
395 return 1;
396}
397
852af20a
MB		 398static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
399{
400 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
401 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
402 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
403 return 0;
404 dev_warn(&h->pdev->dev, HPSA "device busy");
405 return 1;
406}
407
e985c58f
SC		 408static u32 lockup_detected(struct ctlr_info *h);
409static ssize_t host_show_lockup_detected(struct device *dev,
410 struct device_attribute *attr, char *buf)
411{
412 int ld;
413 struct ctlr_info *h;
414 struct Scsi_Host *shost = class_to_shost(dev);
415
416 h = shost_to_hba(shost);
417 ld = lockup_detected(h);
418
419 return sprintf(buf, "ld=%d\n", ld);
420}
421
da0697bd
ST		 422static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
423 struct device_attribute *attr,
424 const char *buf, size_t count)
425{
426 int status, len;
427 struct ctlr_info *h;
428 struct Scsi_Host *shost = class_to_shost(dev);
429 char tmpbuf[10];
430
431 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
432 return -EACCES;
433 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
434 strncpy(tmpbuf, buf, len);
435 tmpbuf[len] = '\0';
436 if (sscanf(tmpbuf, "%d", &status) != 1)
437 return -EINVAL;
438 h = shost_to_hba(shost);
439 h->acciopath_status = !!status;
440 dev_warn(&h->pdev->dev,
441 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
442 h->acciopath_status ? "enabled" : "disabled");
443 return count;
444}
445
2ba8bfc8
SC		 446static ssize_t host_store_raid_offload_debug(struct device *dev,
447 struct device_attribute *attr,
448 const char *buf, size_t count)
449{
450 int debug_level, len;
451 struct ctlr_info *h;
452 struct Scsi_Host *shost = class_to_shost(dev);
453 char tmpbuf[10];
454
455 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
456 return -EACCES;
457 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
458 strncpy(tmpbuf, buf, len);
459 tmpbuf[len] = '\0';
460 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
461 return -EINVAL;
462 if (debug_level < 0)
463 debug_level = 0;
464 h = shost_to_hba(shost);
465 h->raid_offload_debug = debug_level;
466 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
467 h->raid_offload_debug);
468 return count;
469}
470
edd16368
SC		 471static ssize_t host_store_rescan(struct device *dev,
472 struct device_attribute *attr,
473 const char *buf, size_t count)
474{
475 struct ctlr_info *h;
476 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 477 h = shost_to_hba(shost);
31468401 478 hpsa_scan_start(h->scsi_host);
edd16368
SC		 479 return count;
480}
481
d28ce020
SC		 482static ssize_t host_show_firmware_revision(struct device *dev,
483 struct device_attribute *attr, char *buf)
484{
485 struct ctlr_info *h;
486 struct Scsi_Host *shost = class_to_shost(dev);
487 unsigned char *fwrev;
488
489 h = shost_to_hba(shost);
490 if (!h->hba_inquiry_data)
491 return 0;
492 fwrev = &h->hba_inquiry_data[32];
493 return snprintf(buf, 20, "%c%c%c%c\n",
494 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
495}
496
94a13649
SC		 497static ssize_t host_show_commands_outstanding(struct device *dev,
498 struct device_attribute *attr, char *buf)
499{
500 struct Scsi_Host *shost = class_to_shost(dev);
501 struct ctlr_info *h = shost_to_hba(shost);
502
0cbf768e
SC		 503 return snprintf(buf, 20, "%d\n",
504 atomic_read(&h->commands_outstanding));
94a13649
SC		 505}
506
745a7a25
SC		 507static ssize_t host_show_transport_mode(struct device *dev,
508 struct device_attribute *attr, char *buf)
509{
510 struct ctlr_info *h;
511 struct Scsi_Host *shost = class_to_shost(dev);
512
513 h = shost_to_hba(shost);
514 return snprintf(buf, 20, "%s\n",
960a30e7 515 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 516 "performant" : "simple");
517}
518
da0697bd
ST		 519static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
520 struct device_attribute *attr, char *buf)
521{
522 struct ctlr_info *h;
523 struct Scsi_Host *shost = class_to_shost(dev);
524
525 h = shost_to_hba(shost);
526 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
527 (h->acciopath_status == 1) ? "enabled" : "disabled");
528}
529
46380786 530/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 531static u32 unresettable_controller[] = {
532 0x324a103C, /* Smart Array P712m */
9b5c48c2 533 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 534 0x3223103C, /* Smart Array P800 */
535 0x3234103C, /* Smart Array P400 */
536 0x3235103C, /* Smart Array P400i */
537 0x3211103C, /* Smart Array E200i */
538 0x3212103C, /* Smart Array E200 */
539 0x3213103C, /* Smart Array E200i */
540 0x3214103C, /* Smart Array E200i */
541 0x3215103C, /* Smart Array E200i */
542 0x3237103C, /* Smart Array E500 */
543 0x323D103C, /* Smart Array P700m */
7af0abbc 544 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 545 0x409C0E11, /* Smart Array 6400 */
546 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 547 0x40700E11, /* Smart Array 5300 */
548 0x40820E11, /* Smart Array 532 */
549 0x40830E11, /* Smart Array 5312 */
550 0x409A0E11, /* Smart Array 641 */
551 0x409B0E11, /* Smart Array 642 */
552 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 553};
554
46380786
SC		 555/* List of controllers which cannot even be soft reset */
556static u32 soft_unresettable_controller[] = {
7af0abbc 557 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 558 0x40700E11, /* Smart Array 5300 */
559 0x40820E11, /* Smart Array 532 */
560 0x40830E11, /* Smart Array 5312 */
561 0x409A0E11, /* Smart Array 641 */
562 0x409B0E11, /* Smart Array 642 */
563 0x40910E11, /* Smart Array 6i */
46380786
SC		 564 /* Exclude 640x boards. These are two pci devices in one slot
565 * which share a battery backed cache module. One controls the
566 * cache, the other accesses the cache through the one that controls
567 * it. If we reset the one controlling the cache, the other will
568 * likely not be happy. Just forbid resetting this conjoined mess.
569 * The 640x isn't really supported by hpsa anyway.
570 */
571 0x409C0E11, /* Smart Array 6400 */
572 0x409D0E11, /* Smart Array 6400 EM */
573};
574
9b5c48c2
SC		 575static u32 needs_abort_tags_swizzled[] = {
576 0x323D103C, /* Smart Array P700m */
577 0x324a103C, /* Smart Array P712m */
578 0x324b103C, /* SmartArray P711m */
579};
580
581static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 582{
583 int i;
584
9b5c48c2
SC		 585 for (i = 0; i < nelems; i++)
586 if (a[i] == board_id)
587 return 1;
588 return 0;
46380786
SC		 589}
590
9b5c48c2 591static int ctlr_is_hard_resettable(u32 board_id)
46380786 592{
9b5c48c2
SC		 593 return !board_id_in_array(unresettable_controller,
594 ARRAY_SIZE(unresettable_controller), board_id);
595}
46380786 596
9b5c48c2
SC		 597static int ctlr_is_soft_resettable(u32 board_id)
598{
599 return !board_id_in_array(soft_unresettable_controller,
600 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 601}
602
46380786
SC		 603static int ctlr_is_resettable(u32 board_id)
604{
605 return ctlr_is_hard_resettable(board_id) ||
606 ctlr_is_soft_resettable(board_id);
607}
608
9b5c48c2
SC		 609static int ctlr_needs_abort_tags_swizzled(u32 board_id)
610{
611 return board_id_in_array(needs_abort_tags_swizzled,
612 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
613}
614
941b1cda
SC		 615static ssize_t host_show_resettable(struct device *dev,
616 struct device_attribute *attr, char *buf)
617{
618 struct ctlr_info *h;
619 struct Scsi_Host *shost = class_to_shost(dev);
620
621 h = shost_to_hba(shost);
46380786 622 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 623}
624
edd16368
SC		 625static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
626{
627 return (scsi3addr[3] & 0xC0) == 0x40;
628}
629
f2ef0ce7 630static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
7c59a0d4 631 "1(+0)ADM", "UNKNOWN", "PHYS DRV"
edd16368 632};
6b80b18f
ST		 633#define HPSA_RAID_0 0
634#define HPSA_RAID_4 1
635#define HPSA_RAID_1 2 /* also used for RAID 10 */
636#define HPSA_RAID_5 3 /* also used for RAID 50 */
637#define HPSA_RAID_51 4
638#define HPSA_RAID_6 5 /* also used for RAID 60 */
639#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
7c59a0d4
DB		 640#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2)
641#define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1)
edd16368 642
f3f01730
KB		 643static inline bool is_logical_device(struct hpsa_scsi_dev_t *device)
644{
645 return !device->physical_device;
646}
edd16368
SC		 647
648static ssize_t raid_level_show(struct device *dev,
649 struct device_attribute *attr, char *buf)
650{
651 ssize_t l = 0;
82a72c0a 652 unsigned char rlevel;
edd16368
SC		 653 struct ctlr_info *h;
654 struct scsi_device *sdev;
655 struct hpsa_scsi_dev_t *hdev;
656 unsigned long flags;
657
658 sdev = to_scsi_device(dev);
659 h = sdev_to_hba(sdev);
660 spin_lock_irqsave(&h->lock, flags);
661 hdev = sdev->hostdata;
662 if (!hdev) {
663 spin_unlock_irqrestore(&h->lock, flags);
664 return -ENODEV;
665 }
666
667 /* Is this even a logical drive? */
f3f01730 668 if (!is_logical_device(hdev)) {
edd16368
SC		 669 spin_unlock_irqrestore(&h->lock, flags);
670 l = snprintf(buf, PAGE_SIZE, "N/A\n");
671 return l;
672 }
673
674 rlevel = hdev->raid_level;
675 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 676 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 677 rlevel = RAID_UNKNOWN;
678 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
679 return l;
680}
681
682static ssize_t lunid_show(struct device *dev,
683 struct device_attribute *attr, char *buf)
684{
685 struct ctlr_info *h;
686 struct scsi_device *sdev;
687 struct hpsa_scsi_dev_t *hdev;
688 unsigned long flags;
689 unsigned char lunid[8];
690
691 sdev = to_scsi_device(dev);
692 h = sdev_to_hba(sdev);
693 spin_lock_irqsave(&h->lock, flags);
694 hdev = sdev->hostdata;
695 if (!hdev) {
696 spin_unlock_irqrestore(&h->lock, flags);
697 return -ENODEV;
698 }
699 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
700 spin_unlock_irqrestore(&h->lock, flags);
701 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
702 lunid[0], lunid[1], lunid[2], lunid[3],
703 lunid[4], lunid[5], lunid[6], lunid[7]);
704}
705
706static ssize_t unique_id_show(struct device *dev,
707 struct device_attribute *attr, char *buf)
708{
709 struct ctlr_info *h;
710 struct scsi_device *sdev;
711 struct hpsa_scsi_dev_t *hdev;
712 unsigned long flags;
713 unsigned char sn[16];
714
715 sdev = to_scsi_device(dev);
716 h = sdev_to_hba(sdev);
717 spin_lock_irqsave(&h->lock, flags);
718 hdev = sdev->hostdata;
719 if (!hdev) {
720 spin_unlock_irqrestore(&h->lock, flags);
721 return -ENODEV;
722 }
723 memcpy(sn, hdev->device_id, sizeof(sn));
724 spin_unlock_irqrestore(&h->lock, flags);
725 return snprintf(buf, 16 * 2 + 2,
726 "%02X%02X%02X%02X%02X%02X%02X%02X"
727 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
728 sn[0], sn[1], sn[2], sn[3],
729 sn[4], sn[5], sn[6], sn[7],
730 sn[8], sn[9], sn[10], sn[11],
731 sn[12], sn[13], sn[14], sn[15]);
732}
733
ded1be4a
JH		 734static ssize_t sas_address_show(struct device *dev,
735 struct device_attribute *attr, char *buf)
736{
737 struct ctlr_info *h;
738 struct scsi_device *sdev;
739 struct hpsa_scsi_dev_t *hdev;
740 unsigned long flags;
741 u64 sas_address;
742
743 sdev = to_scsi_device(dev);
744 h = sdev_to_hba(sdev);
745 spin_lock_irqsave(&h->lock, flags);
746 hdev = sdev->hostdata;
747 if (!hdev || is_logical_device(hdev) || !hdev->expose_device) {
748 spin_unlock_irqrestore(&h->lock, flags);
749 return -ENODEV;
750 }
751 sas_address = hdev->sas_address;
752 spin_unlock_irqrestore(&h->lock, flags);
753
754 return snprintf(buf, PAGE_SIZE, "0x%016llx\n", sas_address);
755}
756
c1988684
ST		 757static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
758 struct device_attribute *attr, char *buf)
759{
760 struct ctlr_info *h;
761 struct scsi_device *sdev;
762 struct hpsa_scsi_dev_t *hdev;
763 unsigned long flags;
764 int offload_enabled;
765
766 sdev = to_scsi_device(dev);
767 h = sdev_to_hba(sdev);
768 spin_lock_irqsave(&h->lock, flags);
769 hdev = sdev->hostdata;
770 if (!hdev) {
771 spin_unlock_irqrestore(&h->lock, flags);
772 return -ENODEV;
773 }
774 offload_enabled = hdev->offload_enabled;
775 spin_unlock_irqrestore(&h->lock, flags);
776 return snprintf(buf, 20, "%d\n", offload_enabled);
777}
778
8270b862 779#define MAX_PATHS 8
8270b862
JH		 780static ssize_t path_info_show(struct device *dev,
781 struct device_attribute *attr, char *buf)
782{
783 struct ctlr_info *h;
784 struct scsi_device *sdev;
785 struct hpsa_scsi_dev_t *hdev;
786 unsigned long flags;
787 int i;
788 int output_len = 0;
789 u8 box;
790 u8 bay;
791 u8 path_map_index = 0;
792 char *active;
793 unsigned char phys_connector[2];
8270b862 794
8270b862
JH		 795 sdev = to_scsi_device(dev);
796 h = sdev_to_hba(sdev);
797 spin_lock_irqsave(&h->devlock, flags);
798 hdev = sdev->hostdata;
799 if (!hdev) {
800 spin_unlock_irqrestore(&h->devlock, flags);
801 return -ENODEV;
802 }
803
804 bay = hdev->bay;
805 for (i = 0; i < MAX_PATHS; i++) {
806 path_map_index = 1<<i;
807 if (i == hdev->active_path_index)
808 active = "Active";
809 else if (hdev->path_map & path_map_index)
810 active = "Inactive";
811 else
812 continue;
813
1faf072c
RV		 814 output_len += scnprintf(buf + output_len,
815 PAGE_SIZE - output_len,
816 "[%d:%d:%d:%d] %20.20s ",
8270b862
JH		 817 h->scsi_host->host_no,
818 hdev->bus, hdev->target, hdev->lun,
819 scsi_device_type(hdev->devtype));
820
cca8f13b 821 if (hdev->devtype == TYPE_RAID || is_logical_device(hdev)) {
2708f295 822 output_len += scnprintf(buf + output_len,
1faf072c
RV		 823 PAGE_SIZE - output_len,
824 "%s\n", active);
8270b862
JH		 825 continue;
826 }
827
828 box = hdev->box[i];
829 memcpy(&phys_connector, &hdev->phys_connector[i],
830 sizeof(phys_connector));
831 if (phys_connector[0] < '0')
832 phys_connector[0] = '0';
833 if (phys_connector[1] < '0')
834 phys_connector[1] = '0';
cca8f13b 835 output_len += scnprintf(buf + output_len,
1faf072c 836 PAGE_SIZE - output_len,
8270b862
JH		 837 "PORT: %.2s ",
838 phys_connector);
af15ed36
DB		 839 if ((hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) &&
840 hdev->expose_device) {
8270b862 841 if (box == 0 || box == 0xFF) {
2708f295 842 output_len += scnprintf(buf + output_len,
1faf072c 843 PAGE_SIZE - output_len,
8270b862
JH		 844 "BAY: %hhu %s\n",
845 bay, active);
846 } else {
2708f295 847 output_len += scnprintf(buf + output_len,
1faf072c 848 PAGE_SIZE - output_len,
8270b862
JH		 849 "BOX: %hhu BAY: %hhu %s\n",
850 box, bay, active);
851 }
852 } else if (box != 0 && box != 0xFF) {
2708f295 853 output_len += scnprintf(buf + output_len,
1faf072c 854 PAGE_SIZE - output_len, "BOX: %hhu %s\n",
8270b862
JH		 855 box, active);
856 } else
2708f295 857 output_len += scnprintf(buf + output_len,
1faf072c 858 PAGE_SIZE - output_len, "%s\n", active);
8270b862
JH		 859 }
860
861 spin_unlock_irqrestore(&h->devlock, flags);
1faf072c 862 return output_len;
8270b862
JH		 863}
864
3f5eac3a
SC		 865static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
866static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
867static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
868static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
ded1be4a 869static DEVICE_ATTR(sas_address, S_IRUGO, sas_address_show, NULL);
c1988684
ST		 870static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
871 host_show_hp_ssd_smart_path_enabled, NULL);
8270b862 872static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
da0697bd
ST		 873static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
874 host_show_hp_ssd_smart_path_status,
875 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 876static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
877 host_store_raid_offload_debug);
3f5eac3a
SC		 878static DEVICE_ATTR(firmware_revision, S_IRUGO,
879 host_show_firmware_revision, NULL);
880static DEVICE_ATTR(commands_outstanding, S_IRUGO,
881 host_show_commands_outstanding, NULL);
882static DEVICE_ATTR(transport_mode, S_IRUGO,
883 host_show_transport_mode, NULL);
941b1cda
SC		 884static DEVICE_ATTR(resettable, S_IRUGO,
885 host_show_resettable, NULL);
e985c58f
SC		 886static DEVICE_ATTR(lockup_detected, S_IRUGO,
887 host_show_lockup_detected, NULL);
3f5eac3a
SC		 888
889static struct device_attribute *hpsa_sdev_attrs[] = {
890 &dev_attr_raid_level,
891 &dev_attr_lunid,
892 &dev_attr_unique_id,
c1988684 893 &dev_attr_hp_ssd_smart_path_enabled,
8270b862 894 &dev_attr_path_info,
ded1be4a 895 &dev_attr_sas_address,
3f5eac3a
SC		 896 NULL,
897};
898
899static struct device_attribute *hpsa_shost_attrs[] = {
900 &dev_attr_rescan,
901 &dev_attr_firmware_revision,
902 &dev_attr_commands_outstanding,
903 &dev_attr_transport_mode,
941b1cda 904 &dev_attr_resettable,
da0697bd 905 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 906 &dev_attr_raid_offload_debug,
fb53c439 907 &dev_attr_lockup_detected,
3f5eac3a
SC		 908 NULL,
909};
910
41ce4c35
SC		 911#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
912 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
913
3f5eac3a
SC		 914static struct scsi_host_template hpsa_driver_template = {
915 .module = THIS_MODULE,
f79cfec6
SC		 916 .name = HPSA,
917 .proc_name = HPSA,
3f5eac3a
SC		 918 .queuecommand = hpsa_scsi_queue_command,
919 .scan_start = hpsa_scan_start,
920 .scan_finished = hpsa_scan_finished,
7c0a0229 921 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 922 .this_id = -1,
923 .use_clustering = ENABLE_CLUSTERING,
75167d2c 924 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 925 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
926 .ioctl = hpsa_ioctl,
927 .slave_alloc = hpsa_slave_alloc,
41ce4c35 928 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 929 .slave_destroy = hpsa_slave_destroy,
930#ifdef CONFIG_COMPAT
931 .compat_ioctl = hpsa_compat_ioctl,
932#endif
933 .sdev_attrs = hpsa_sdev_attrs,
934 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 935 .max_sectors = 8192,
54b2b50c 936 .no_write_same = 1,
3f5eac3a
SC		 937};
938
254f796b 939static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 940{
941 u32 a;
072b0518 942 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 943
e1f7de0c
MG		 944 if (h->transMethod & CFGTBL_Trans_io_accel1)
945 return h->access.command_completed(h, q);
946
3f5eac3a 947 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 948 return h->access.command_completed(h, q);
3f5eac3a 949
254f796b
MG		 950 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
951 a = rq->head[rq->current_entry];
952 rq->current_entry++;
0cbf768e 953 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 954 } else {
955 a = FIFO_EMPTY;
956 }
957 /* Check for wraparound */
254f796b
MG		 958 if (rq->current_entry == h->max_commands) {
959 rq->current_entry = 0;
960 rq->wraparound ^= 1;
3f5eac3a
SC		 961 }
962 return a;
963}
964
c349775e
ST		 965/*
966 * There are some special bits in the bus address of the
967 * command that we have to set for the controller to know
968 * how to process the command:
969 *
970 * Normal performant mode:
971 * bit 0: 1 means performant mode, 0 means simple mode.
972 * bits 1-3 = block fetch table entry
973 * bits 4-6 = command type (== 0)
974 *
975 * ioaccel1 mode:
976 * bit 0 = "performant mode" bit.
977 * bits 1-3 = block fetch table entry
978 * bits 4-6 = command type (== 110)
979 * (command type is needed because ioaccel1 mode
980 * commands are submitted through the same register as normal
981 * mode commands, so this is how the controller knows whether
982 * the command is normal mode or ioaccel1 mode.)
983 *
984 * ioaccel2 mode:
985 * bit 0 = "performant mode" bit.
986 * bits 1-4 = block fetch table entry (note extra bit)
987 * bits 4-6 = not needed, because ioaccel2 mode has
988 * a separate special register for submitting commands.
989 */
990
25163bd5
WS		 991/*
992 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 993 * set bit 0 for pull model, bits 3-1 for block fetch
994 * register number
995 */
25163bd5
WS		 996#define DEFAULT_REPLY_QUEUE (-1)
997static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
998 int reply_queue)
3f5eac3a 999{
254f796b 1000 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 1001 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 1002 if (unlikely(!h->msix_vector))
1003 return;
1004 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 1005 c->Header.ReplyQueue =
804a5cb5 1006 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 1007 else
1008 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 1009 }
3f5eac3a
SC		 1010}
1011
c349775e 1012static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1013 struct CommandList *c,
1014 int reply_queue)
c349775e
ST		 1015{
1016 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
1017
25163bd5
WS		 1018 /*
1019 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1020 * processor. This seems to give the best I/O throughput.
1021 */
25163bd5
WS		 1022 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1023 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
1024 else
1025 cp->ReplyQueue = reply_queue % h->nreply_queues;
1026 /*
1027 * Set the bits in the address sent down to include:
c349775e
ST		 1028 * - performant mode bit (bit 0)
1029 * - pull count (bits 1-3)
1030 * - command type (bits 4-6)
1031 */
1032 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
1033 IOACCEL1_BUSADDR_CMDTYPE;
1034}
1035
8be986cc
SC		 1036static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
1037 struct CommandList *c,
1038 int reply_queue)
1039{
1040 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
1041 &h->ioaccel2_cmd_pool[c->cmdindex];
1042
1043 /* Tell the controller to post the reply to the queue for this
1044 * processor. This seems to give the best I/O throughput.
1045 */
1046 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1047 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1048 else
1049 cp->reply_queue = reply_queue % h->nreply_queues;
1050 /* Set the bits in the address sent down to include:
1051 * - performant mode bit not used in ioaccel mode 2
1052 * - pull count (bits 0-3)
1053 * - command type isn't needed for ioaccel2
1054 */
1055 c->busaddr |= h->ioaccel2_blockFetchTable[0];
1056}
1057
c349775e 1058static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1059 struct CommandList *c,
1060 int reply_queue)
c349775e
ST		 1061{
1062 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
1063
25163bd5
WS		 1064 /*
1065 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1066 * processor. This seems to give the best I/O throughput.
1067 */
25163bd5
WS		 1068 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1069 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1070 else
1071 cp->reply_queue = reply_queue % h->nreply_queues;
1072 /*
1073 * Set the bits in the address sent down to include:
c349775e
ST		 1074 * - performant mode bit not used in ioaccel mode 2
1075 * - pull count (bits 0-3)
1076 * - command type isn't needed for ioaccel2
1077 */
1078 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
1079}
1080
e85c5974
SC		 1081static int is_firmware_flash_cmd(u8 *cdb)
1082{
1083 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
1084}
1085
1086/*
1087 * During firmware flash, the heartbeat register may not update as frequently
1088 * as it should. So we dial down lockup detection during firmware flash. and
1089 * dial it back up when firmware flash completes.
1090 */
1091#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
1092#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
1093static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
1094 struct CommandList *c)
1095{
1096 if (!is_firmware_flash_cmd(c->Request.CDB))
1097 return;
1098 atomic_inc(&h->firmware_flash_in_progress);
1099 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
1100}
1101
1102static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
1103 struct CommandList *c)
1104{
1105 if (is_firmware_flash_cmd(c->Request.CDB) &&
1106 atomic_dec_and_test(&h->firmware_flash_in_progress))
1107 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
1108}
1109
25163bd5
WS		 1110static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
1111 struct CommandList *c, int reply_queue)
3f5eac3a 1112{
c05e8866
SC		 1113 dial_down_lockup_detection_during_fw_flash(h, c);
1114 atomic_inc(&h->commands_outstanding);
c349775e
ST		 1115 switch (c->cmd_type) {
1116 case CMD_IOACCEL1:
25163bd5 1117 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 1118 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 1119 break;
1120 case CMD_IOACCEL2:
25163bd5 1121 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 1122 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e 1123 break;
8be986cc
SC		 1124 case IOACCEL2_TMF:
1125 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
1126 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1127 break;
c349775e 1128 default:
25163bd5 1129 set_performant_mode(h, c, reply_queue);
c05e8866 1130 h->access.submit_command(h, c);
c349775e 1131 }
3f5eac3a
SC		 1132}
1133
a58e7e53 1134static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
25163bd5 1135{
d604f533 1136 if (unlikely(hpsa_is_pending_event(c)))
a58e7e53
WS		 1137 return finish_cmd(c);
1138
25163bd5
WS		 1139 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
1140}
1141
3f5eac3a
SC		 1142static inline int is_hba_lunid(unsigned char scsi3addr[])
1143{
1144 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
1145}
1146
1147static inline int is_scsi_rev_5(struct ctlr_info *h)
1148{
1149 if (!h->hba_inquiry_data)
1150 return 0;
1151 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1152 return 1;
1153 return 0;
1154}
1155
edd16368
SC		 1156static int hpsa_find_target_lun(struct ctlr_info *h,
1157 unsigned char scsi3addr[], int bus, int *target, int *lun)
1158{
1159 /* finds an unused bus, target, lun for a new physical device
1160 * assumes h->devlock is held
1161 */
1162 int i, found = 0;
cfe5badc 1163 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 1164
263d9401 1165 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 1166
1167 for (i = 0; i < h->ndevices; i++) {
1168 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 1169 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 1170 }
1171
263d9401
AM		 1172 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1173 if (i < HPSA_MAX_DEVICES) {
1174 /* *bus = 1; */
1175 *target = i;
1176 *lun = 0;
1177 found = 1;
edd16368
SC		 1178 }
1179 return !found;
1180}
1181
1d33d85d 1182static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
0d96ef5f
WS		 1183 struct hpsa_scsi_dev_t *dev, char *description)
1184{
7c59a0d4
DB		 1185#define LABEL_SIZE 25
1186 char label[LABEL_SIZE];
1187
9975ec9d
DB		 1188 if (h == NULL || h->pdev == NULL || h->scsi_host == NULL)
1189 return;
1190
7c59a0d4
DB		 1191 switch (dev->devtype) {
1192 case TYPE_RAID:
1193 snprintf(label, LABEL_SIZE, "controller");
1194 break;
1195 case TYPE_ENCLOSURE:
1196 snprintf(label, LABEL_SIZE, "enclosure");
1197 break;
1198 case TYPE_DISK:
af15ed36 1199 case TYPE_ZBC:
7c59a0d4
DB		 1200 if (dev->external)
1201 snprintf(label, LABEL_SIZE, "external");
1202 else if (!is_logical_dev_addr_mode(dev->scsi3addr))
1203 snprintf(label, LABEL_SIZE, "%s",
1204 raid_label[PHYSICAL_DRIVE]);
1205 else
1206 snprintf(label, LABEL_SIZE, "RAID-%s",
1207 dev->raid_level > RAID_UNKNOWN ? "?" :
1208 raid_label[dev->raid_level]);
1209 break;
1210 case TYPE_ROM:
1211 snprintf(label, LABEL_SIZE, "rom");
1212 break;
1213 case TYPE_TAPE:
1214 snprintf(label, LABEL_SIZE, "tape");
1215 break;
1216 case TYPE_MEDIUM_CHANGER:
1217 snprintf(label, LABEL_SIZE, "changer");
1218 break;
1219 default:
1220 snprintf(label, LABEL_SIZE, "UNKNOWN");
1221 break;
1222 }
1223
0d96ef5f 1224 dev_printk(level, &h->pdev->dev,
7c59a0d4 1225 "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n",
0d96ef5f
WS		 1226 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1227 description,
1228 scsi_device_type(dev->devtype),
1229 dev->vendor,
1230 dev->model,
7c59a0d4 1231 label,
0d96ef5f
WS		 1232 dev->offload_config ? '+' : '-',
1233 dev->offload_enabled ? '+' : '-',
2a168208 1234 dev->expose_device);
0d96ef5f
WS		 1235}
1236
edd16368 1237/* Add an entry into h->dev[] array. */
8aa60681 1238static int hpsa_scsi_add_entry(struct ctlr_info *h,
edd16368
SC		 1239 struct hpsa_scsi_dev_t *device,
1240 struct hpsa_scsi_dev_t *added[], int *nadded)
1241{
1242 /* assumes h->devlock is held */
1243 int n = h->ndevices;
1244 int i;
1245 unsigned char addr1[8], addr2[8];
1246 struct hpsa_scsi_dev_t *sd;
1247
cfe5badc 1248 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1249 dev_err(&h->pdev->dev, "too many devices, some will be "
1250 "inaccessible.\n");
1251 return -1;
1252 }
1253
1254 /* physical devices do not have lun or target assigned until now. */
1255 if (device->lun != -1)
1256 /* Logical device, lun is already assigned. */
1257 goto lun_assigned;
1258
1259 /* If this device a non-zero lun of a multi-lun device
1260 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1261 * unit no, zero otherwise.
edd16368
SC		 1262 */
1263 if (device->scsi3addr[4] == 0) {
1264 /* This is not a non-zero lun of a multi-lun device */
1265 if (hpsa_find_target_lun(h, device->scsi3addr,
1266 device->bus, &device->target, &device->lun) != 0)
1267 return -1;
1268 goto lun_assigned;
1269 }
1270
1271 /* This is a non-zero lun of a multi-lun device.
1272 * Search through our list and find the device which
9a4178b7 1273 * has the same 8 byte LUN address, excepting byte 4 and 5.
edd16368
SC		 1274 * Assign the same bus and target for this new LUN.
1275 * Use the logical unit number from the firmware.
1276 */
1277 memcpy(addr1, device->scsi3addr, 8);
1278 addr1[4] = 0;
9a4178b7 1279 addr1[5] = 0;
edd16368
SC		 1280 for (i = 0; i < n; i++) {
1281 sd = h->dev[i];
1282 memcpy(addr2, sd->scsi3addr, 8);
1283 addr2[4] = 0;
9a4178b7 1284 addr2[5] = 0;
1285 /* differ only in byte 4 and 5? */
edd16368
SC		 1286 if (memcmp(addr1, addr2, 8) == 0) {
1287 device->bus = sd->bus;
1288 device->target = sd->target;
1289 device->lun = device->scsi3addr[4];
1290 break;
1291 }
1292 }
1293 if (device->lun == -1) {
1294 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1295 " suspect firmware bug or unsupported hardware "
1296 "configuration.\n");
1297 return -1;
1298 }
1299
1300lun_assigned:
1301
1302 h->dev[n] = device;
1303 h->ndevices++;
1304 added[*nadded] = device;
1305 (*nadded)++;
0d96ef5f 1306 hpsa_show_dev_msg(KERN_INFO, h, device,
2a168208 1307 device->expose_device ? "added" : "masked");
a473d86c
RE		 1308 device->offload_to_be_enabled = device->offload_enabled;
1309 device->offload_enabled = 0;
edd16368
SC		 1310 return 0;
1311}
1312
bd9244f7 1313/* Update an entry in h->dev[] array. */
8aa60681 1314static void hpsa_scsi_update_entry(struct ctlr_info *h,
bd9244f7
ST		 1315 int entry, struct hpsa_scsi_dev_t *new_entry)
1316{
a473d86c 1317 int offload_enabled;
bd9244f7
ST		 1318 /* assumes h->devlock is held */
1319 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1320
1321 /* Raid level changed. */
1322 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1323
03383736
DB		 1324 /* Raid offload parameters changed. Careful about the ordering. */
1325 if (new_entry->offload_config && new_entry->offload_enabled) {
1326 /*
1327 * if drive is newly offload_enabled, we want to copy the
1328 * raid map data first. If previously offload_enabled and
1329 * offload_config were set, raid map data had better be
1330 * the same as it was before. if raid map data is changed
1331 * then it had better be the case that
1332 * h->dev[entry]->offload_enabled is currently 0.
1333 */
1334 h->dev[entry]->raid_map = new_entry->raid_map;
1335 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1336 }
a3144e0b
JH		 1337 if (new_entry->hba_ioaccel_enabled) {
1338 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1339 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1340 }
1341 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1342 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1343 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1344 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1345
41ce4c35
SC		 1346 /*
1347 * We can turn off ioaccel offload now, but need to delay turning
1348 * it on until we can update h->dev[entry]->phys_disk[], but we
1349 * can't do that until all the devices are updated.
1350 */
1351 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1352 if (!new_entry->offload_enabled)
1353 h->dev[entry]->offload_enabled = 0;
1354
a473d86c
RE		 1355 offload_enabled = h->dev[entry]->offload_enabled;
1356 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1357 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1358 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1359}
1360
2a8ccf31 1361/* Replace an entry from h->dev[] array. */
8aa60681 1362static void hpsa_scsi_replace_entry(struct ctlr_info *h,
2a8ccf31
SC		 1363 int entry, struct hpsa_scsi_dev_t *new_entry,
1364 struct hpsa_scsi_dev_t *added[], int *nadded,
1365 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1366{
1367 /* assumes h->devlock is held */
cfe5badc 1368 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1369 removed[*nremoved] = h->dev[entry];
1370 (*nremoved)++;
01350d05
SC		 1371
1372 /*
1373 * New physical devices won't have target/lun assigned yet
1374 * so we need to preserve the values in the slot we are replacing.
1375 */
1376 if (new_entry->target == -1) {
1377 new_entry->target = h->dev[entry]->target;
1378 new_entry->lun = h->dev[entry]->lun;
1379 }
1380
2a8ccf31
SC		 1381 h->dev[entry] = new_entry;
1382 added[*nadded] = new_entry;
1383 (*nadded)++;
0d96ef5f 1384 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1385 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1386 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1387}
1388
edd16368 1389/* Remove an entry from h->dev[] array. */
8aa60681 1390static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
edd16368
SC		 1391 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1392{
1393 /* assumes h->devlock is held */
1394 int i;
1395 struct hpsa_scsi_dev_t *sd;
1396
cfe5badc 1397 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1398
1399 sd = h->dev[entry];
1400 removed[*nremoved] = h->dev[entry];
1401 (*nremoved)++;
1402
1403 for (i = entry; i < h->ndevices-1; i++)
1404 h->dev[i] = h->dev[i+1];
1405 h->ndevices--;
0d96ef5f 1406 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1407}
1408
1409#define SCSI3ADDR_EQ(a, b) ( \
1410 (a)[7] == (b)[7] && \
1411 (a)[6] == (b)[6] && \
1412 (a)[5] == (b)[5] && \
1413 (a)[4] == (b)[4] && \
1414 (a)[3] == (b)[3] && \
1415 (a)[2] == (b)[2] && \
1416 (a)[1] == (b)[1] && \
1417 (a)[0] == (b)[0])
1418
1419static void fixup_botched_add(struct ctlr_info *h,
1420 struct hpsa_scsi_dev_t *added)
1421{
1422 /* called when scsi_add_device fails in order to re-adjust
1423 * h->dev[] to match the mid layer's view.
1424 */
1425 unsigned long flags;
1426 int i, j;
1427
1428 spin_lock_irqsave(&h->lock, flags);
1429 for (i = 0; i < h->ndevices; i++) {
1430 if (h->dev[i] == added) {
1431 for (j = i; j < h->ndevices-1; j++)
1432 h->dev[j] = h->dev[j+1];
1433 h->ndevices--;
1434 break;
1435 }
1436 }
1437 spin_unlock_irqrestore(&h->lock, flags);
1438 kfree(added);
1439}
1440
1441static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1442 struct hpsa_scsi_dev_t *dev2)
1443{
edd16368
SC		 1444 /* we compare everything except lun and target as these
1445 * are not yet assigned. Compare parts likely
1446 * to differ first
1447 */
1448 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1449 sizeof(dev1->scsi3addr)) != 0)
1450 return 0;
1451 if (memcmp(dev1->device_id, dev2->device_id,
1452 sizeof(dev1->device_id)) != 0)
1453 return 0;
1454 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1455 return 0;
1456 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1457 return 0;
edd16368
SC		 1458 if (dev1->devtype != dev2->devtype)
1459 return 0;
edd16368
SC		 1460 if (dev1->bus != dev2->bus)
1461 return 0;
1462 return 1;
1463}
1464
bd9244f7
ST		 1465static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1466 struct hpsa_scsi_dev_t *dev2)
1467{
1468 /* Device attributes that can change, but don't mean
1469 * that the device is a different device, nor that the OS
1470 * needs to be told anything about the change.
1471 */
1472 if (dev1->raid_level != dev2->raid_level)
1473 return 1;
250fb125
SC		 1474 if (dev1->offload_config != dev2->offload_config)
1475 return 1;
1476 if (dev1->offload_enabled != dev2->offload_enabled)
1477 return 1;
93849508
DB		 1478 if (!is_logical_dev_addr_mode(dev1->scsi3addr))
1479 if (dev1->queue_depth != dev2->queue_depth)
1480 return 1;
bd9244f7
ST		 1481 return 0;
1482}
1483
edd16368
SC		 1484/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1485 * and return needle location in *index. If scsi3addr matches, but not
1486 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1487 * location in *index.
1488 * In the case of a minor device attribute change, such as RAID level, just
1489 * return DEVICE_UPDATED, along with the updated device's location in index.
1490 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1491 */
1492static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1493 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1494 int *index)
1495{
1496 int i;
1497#define DEVICE_NOT_FOUND 0
1498#define DEVICE_CHANGED 1
1499#define DEVICE_SAME 2
bd9244f7 1500#define DEVICE_UPDATED 3
1d33d85d
DB		 1501 if (needle == NULL)
1502 return DEVICE_NOT_FOUND;
1503
edd16368 1504 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1505 if (haystack[i] == NULL) /* previously removed. */
1506 continue;
edd16368
SC		 1507 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1508 *index = i;
bd9244f7
ST		 1509 if (device_is_the_same(needle, haystack[i])) {
1510 if (device_updated(needle, haystack[i]))
1511 return DEVICE_UPDATED;
edd16368 1512 return DEVICE_SAME;
bd9244f7 1513 } else {
9846590e
SC		 1514 /* Keep offline devices offline */
1515 if (needle->volume_offline)
1516 return DEVICE_NOT_FOUND;
edd16368 1517 return DEVICE_CHANGED;
bd9244f7 1518 }
edd16368
SC		 1519 }
1520 }
1521 *index = -1;
1522 return DEVICE_NOT_FOUND;
1523}
1524
9846590e
SC		 1525static void hpsa_monitor_offline_device(struct ctlr_info *h,
1526 unsigned char scsi3addr[])
1527{
1528 struct offline_device_entry *device;
1529 unsigned long flags;
1530
1531 /* Check to see if device is already on the list */
1532 spin_lock_irqsave(&h->offline_device_lock, flags);
1533 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1534 if (memcmp(device->scsi3addr, scsi3addr,
1535 sizeof(device->scsi3addr)) == 0) {
1536 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1537 return;
1538 }
1539 }
1540 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1541
1542 /* Device is not on the list, add it. */
1543 device = kmalloc(sizeof(*device), GFP_KERNEL);
1544 if (!device) {
1545 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1546 return;
1547 }
1548 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1549 spin_lock_irqsave(&h->offline_device_lock, flags);
1550 list_add_tail(&device->offline_list, &h->offline_device_list);
1551 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1552}
1553
1554/* Print a message explaining various offline volume states */
1555static void hpsa_show_volume_status(struct ctlr_info *h,
1556 struct hpsa_scsi_dev_t *sd)
1557{
1558 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1559 dev_info(&h->pdev->dev,
1560 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1561 h->scsi_host->host_no,
1562 sd->bus, sd->target, sd->lun);
1563 switch (sd->volume_offline) {
1564 case HPSA_LV_OK:
1565 break;
1566 case HPSA_LV_UNDERGOING_ERASE:
1567 dev_info(&h->pdev->dev,
1568 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1569 h->scsi_host->host_no,
1570 sd->bus, sd->target, sd->lun);
1571 break;
5ca01204
SB		 1572 case HPSA_LV_NOT_AVAILABLE:
1573 dev_info(&h->pdev->dev,
1574 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
1575 h->scsi_host->host_no,
1576 sd->bus, sd->target, sd->lun);
1577 break;
9846590e
SC		 1578 case HPSA_LV_UNDERGOING_RPI:
1579 dev_info(&h->pdev->dev,
5ca01204 1580 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
9846590e
SC		 1581 h->scsi_host->host_no,
1582 sd->bus, sd->target, sd->lun);
1583 break;
1584 case HPSA_LV_PENDING_RPI:
1585 dev_info(&h->pdev->dev,
5ca01204
SB		 1586 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1587 h->scsi_host->host_no,
1588 sd->bus, sd->target, sd->lun);
9846590e
SC		 1589 break;
1590 case HPSA_LV_ENCRYPTED_NO_KEY:
1591 dev_info(&h->pdev->dev,
1592 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1593 h->scsi_host->host_no,
1594 sd->bus, sd->target, sd->lun);
1595 break;
1596 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1597 dev_info(&h->pdev->dev,
1598 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1599 h->scsi_host->host_no,
1600 sd->bus, sd->target, sd->lun);
1601 break;
1602 case HPSA_LV_UNDERGOING_ENCRYPTION:
1603 dev_info(&h->pdev->dev,
1604 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1605 h->scsi_host->host_no,
1606 sd->bus, sd->target, sd->lun);
1607 break;
1608 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1609 dev_info(&h->pdev->dev,
1610 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1611 h->scsi_host->host_no,
1612 sd->bus, sd->target, sd->lun);
1613 break;
1614 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1615 dev_info(&h->pdev->dev,
1616 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1617 h->scsi_host->host_no,
1618 sd->bus, sd->target, sd->lun);
1619 break;
1620 case HPSA_LV_PENDING_ENCRYPTION:
1621 dev_info(&h->pdev->dev,
1622 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1623 h->scsi_host->host_no,
1624 sd->bus, sd->target, sd->lun);
1625 break;
1626 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1627 dev_info(&h->pdev->dev,
1628 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1629 h->scsi_host->host_no,
1630 sd->bus, sd->target, sd->lun);
1631 break;
1632 }
1633}
1634
03383736
DB		 1635/*
1636 * Figure the list of physical drive pointers for a logical drive with
1637 * raid offload configured.
1638 */
1639static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1640 struct hpsa_scsi_dev_t *dev[], int ndevices,
1641 struct hpsa_scsi_dev_t *logical_drive)
1642{
1643 struct raid_map_data *map = &logical_drive->raid_map;
1644 struct raid_map_disk_data *dd = &map->data[0];
1645 int i, j;
1646 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1647 le16_to_cpu(map->metadata_disks_per_row);
1648 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1649 le16_to_cpu(map->layout_map_count) *
1650 total_disks_per_row;
1651 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1652 total_disks_per_row;
1653 int qdepth;
1654
1655 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1656 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1657
d604f533
WS		 1658 logical_drive->nphysical_disks = nraid_map_entries;
1659
03383736
DB		 1660 qdepth = 0;
1661 for (i = 0; i < nraid_map_entries; i++) {
1662 logical_drive->phys_disk[i] = NULL;
1663 if (!logical_drive->offload_config)
1664 continue;
1665 for (j = 0; j < ndevices; j++) {
1d33d85d
DB		 1666 if (dev[j] == NULL)
1667 continue;
03383736
DB		 1668 if (dev[j]->devtype != TYPE_DISK)
1669 continue;
af15ed36
DB		 1670 if (dev[j]->devtype != TYPE_ZBC)
1671 continue;
f3f01730 1672 if (is_logical_device(dev[j]))
03383736
DB		 1673 continue;
1674 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1675 continue;
1676
1677 logical_drive->phys_disk[i] = dev[j];
1678 if (i < nphys_disk)
1679 qdepth = min(h->nr_cmds, qdepth +
1680 logical_drive->phys_disk[i]->queue_depth);
1681 break;
1682 }
1683
1684 /*
1685 * This can happen if a physical drive is removed and
1686 * the logical drive is degraded. In that case, the RAID
1687 * map data will refer to a physical disk which isn't actually
1688 * present. And in that case offload_enabled should already
1689 * be 0, but we'll turn it off here just in case
1690 */
1691 if (!logical_drive->phys_disk[i]) {
1692 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1693 logical_drive->offload_to_be_enabled = 0;
1694 logical_drive->queue_depth = 8;
03383736
DB		 1695 }
1696 }
1697 if (nraid_map_entries)
1698 /*
1699 * This is correct for reads, too high for full stripe writes,
1700 * way too high for partial stripe writes
1701 */
1702 logical_drive->queue_depth = qdepth;
1703 else
1704 logical_drive->queue_depth = h->nr_cmds;
1705}
1706
1707static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1708 struct hpsa_scsi_dev_t *dev[], int ndevices)
1709{
1710 int i;
1711
1712 for (i = 0; i < ndevices; i++) {
1d33d85d
DB		 1713 if (dev[i] == NULL)
1714 continue;
03383736
DB		 1715 if (dev[i]->devtype != TYPE_DISK)
1716 continue;
af15ed36
DB		 1717 if (dev[i]->devtype != TYPE_ZBC)
1718 continue;
f3f01730 1719 if (!is_logical_device(dev[i]))
03383736 1720 continue;
41ce4c35
SC		 1721
1722 /*
1723 * If offload is currently enabled, the RAID map and
1724 * phys_disk[] assignment *better* not be changing
1725 * and since it isn't changing, we do not need to
1726 * update it.
1727 */
1728 if (dev[i]->offload_enabled)
1729 continue;
1730
03383736
DB		 1731 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1732 }
1733}
1734
096ccff4
KB		 1735static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
1736{
1737 int rc = 0;
1738
1739 if (!h->scsi_host)
1740 return 1;
1741
d04e62b9
KB		 1742 if (is_logical_device(device)) /* RAID */
1743 rc = scsi_add_device(h->scsi_host, device->bus,
096ccff4 1744 device->target, device->lun);
d04e62b9
KB		 1745 else /* HBA */
1746 rc = hpsa_add_sas_device(h->sas_host, device);
1747
096ccff4
KB		 1748 return rc;
1749}
1750
ba74fdc4
DB		 1751static int hpsa_find_outstanding_commands_for_dev(struct ctlr_info *h,
1752 struct hpsa_scsi_dev_t *dev)
1753{
1754 int i;
1755 int count = 0;
1756
1757 for (i = 0; i < h->nr_cmds; i++) {
1758 struct CommandList *c = h->cmd_pool + i;
1759 int refcount = atomic_inc_return(&c->refcount);
1760
1761 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev,
1762 dev->scsi3addr)) {
1763 unsigned long flags;
1764
1765 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
1766 if (!hpsa_is_cmd_idle(c))
1767 ++count;
1768 spin_unlock_irqrestore(&h->lock, flags);
1769 }
1770
1771 cmd_free(h, c);
1772 }
1773
1774 return count;
1775}
1776
1777static void hpsa_wait_for_outstanding_commands_for_dev(struct ctlr_info *h,
1778 struct hpsa_scsi_dev_t *device)
1779{
1780 int cmds = 0;
1781 int waits = 0;
1782
1783 while (1) {
1784 cmds = hpsa_find_outstanding_commands_for_dev(h, device);
1785 if (cmds == 0)
1786 break;
1787 if (++waits > 20)
1788 break;
1789 dev_warn(&h->pdev->dev,
1790 "%s: removing device with %d outstanding commands!\n",
1791 __func__, cmds);
1792 msleep(1000);
1793 }
1794}
1795
096ccff4
KB		 1796static void hpsa_remove_device(struct ctlr_info *h,
1797 struct hpsa_scsi_dev_t *device)
1798{
1799 struct scsi_device *sdev = NULL;
1800
1801 if (!h->scsi_host)
1802 return;
1803
d04e62b9
KB		 1804 if (is_logical_device(device)) { /* RAID */
1805 sdev = scsi_device_lookup(h->scsi_host, device->bus,
096ccff4 1806 device->target, device->lun);
d04e62b9
KB		 1807 if (sdev) {
1808 scsi_remove_device(sdev);
1809 scsi_device_put(sdev);
1810 } else {
1811 /*
1812 * We don't expect to get here. Future commands
1813 * to this device will get a selection timeout as
1814 * if the device were gone.
1815 */
1816 hpsa_show_dev_msg(KERN_WARNING, h, device,
096ccff4 1817 "didn't find device for removal.");
d04e62b9 1818 }
ba74fdc4
DB		 1819 } else { /* HBA */
1820
1821 device->removed = 1;
1822 hpsa_wait_for_outstanding_commands_for_dev(h, device);
1823
d04e62b9 1824 hpsa_remove_sas_device(device);
ba74fdc4 1825 }
096ccff4
KB		 1826}
1827
8aa60681 1828static void adjust_hpsa_scsi_table(struct ctlr_info *h,
edd16368
SC		 1829 struct hpsa_scsi_dev_t *sd[], int nsds)
1830{
1831 /* sd contains scsi3 addresses and devtypes, and inquiry
1832 * data. This function takes what's in sd to be the current
1833 * reality and updates h->dev[] to reflect that reality.
1834 */
1835 int i, entry, device_change, changes = 0;
1836 struct hpsa_scsi_dev_t *csd;
1837 unsigned long flags;
1838 struct hpsa_scsi_dev_t **added, **removed;
1839 int nadded, nremoved;
edd16368 1840
da03ded0
DB		 1841 /*
1842 * A reset can cause a device status to change
1843 * re-schedule the scan to see what happened.
1844 */
1845 if (h->reset_in_progress) {
1846 h->drv_req_rescan = 1;
1847 return;
1848 }
edd16368 1849
cfe5badc
ST		 1850 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1851 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1852
1853 if (!added || !removed) {
1854 dev_warn(&h->pdev->dev, "out of memory in "
1855 "adjust_hpsa_scsi_table\n");
1856 goto free_and_out;
1857 }
1858
1859 spin_lock_irqsave(&h->devlock, flags);
1860
1861 /* find any devices in h->dev[] that are not in
1862 * sd[] and remove them from h->dev[], and for any
1863 * devices which have changed, remove the old device
1864 * info and add the new device info.
bd9244f7
ST		 1865 * If minor device attributes change, just update
1866 * the existing device structure.
edd16368
SC		 1867 */
1868 i = 0;
1869 nremoved = 0;
1870 nadded = 0;
1871 while (i < h->ndevices) {
1872 csd = h->dev[i];
1873 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1874 if (device_change == DEVICE_NOT_FOUND) {
1875 changes++;
8aa60681 1876 hpsa_scsi_remove_entry(h, i, removed, &nremoved);
edd16368
SC		 1877 continue; /* remove ^^^, hence i not incremented */
1878 } else if (device_change == DEVICE_CHANGED) {
1879 changes++;
8aa60681 1880 hpsa_scsi_replace_entry(h, i, sd[entry],
2a8ccf31 1881 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1882 /* Set it to NULL to prevent it from being freed
1883 * at the bottom of hpsa_update_scsi_devices()
1884 */
1885 sd[entry] = NULL;
bd9244f7 1886 } else if (device_change == DEVICE_UPDATED) {
8aa60681 1887 hpsa_scsi_update_entry(h, i, sd[entry]);
edd16368
SC		 1888 }
1889 i++;
1890 }
1891
1892 /* Now, make sure every device listed in sd[] is also
1893 * listed in h->dev[], adding them if they aren't found
1894 */
1895
1896 for (i = 0; i < nsds; i++) {
1897 if (!sd[i]) /* if already added above. */
1898 continue;
9846590e
SC		 1899
1900 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1901 * as the SCSI mid-layer does not handle such devices well.
1902 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1903 * at 160Hz, and prevents the system from coming up.
1904 */
1905 if (sd[i]->volume_offline) {
1906 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1907 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1908 continue;
1909 }
1910
edd16368
SC		 1911 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1912 h->ndevices, &entry);
1913 if (device_change == DEVICE_NOT_FOUND) {
1914 changes++;
8aa60681 1915 if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
edd16368
SC		 1916 break;
1917 sd[i] = NULL; /* prevent from being freed later. */
1918 } else if (device_change == DEVICE_CHANGED) {
1919 /* should never happen... */
1920 changes++;
1921 dev_warn(&h->pdev->dev,
1922 "device unexpectedly changed.\n");
1923 /* but if it does happen, we just ignore that device */
1924 }
1925 }
41ce4c35
SC		 1926 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1927
1928 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1929 * any logical drives that need it enabled.
1930 */
1d33d85d
DB		 1931 for (i = 0; i < h->ndevices; i++) {
1932 if (h->dev[i] == NULL)
1933 continue;
41ce4c35 1934 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1d33d85d 1935 }
41ce4c35 1936
edd16368
SC		 1937 spin_unlock_irqrestore(&h->devlock, flags);
1938
9846590e
SC		 1939 /* Monitor devices which are in one of several NOT READY states to be
1940 * brought online later. This must be done without holding h->devlock,
1941 * so don't touch h->dev[]
1942 */
1943 for (i = 0; i < nsds; i++) {
1944 if (!sd[i]) /* if already added above. */
1945 continue;
1946 if (sd[i]->volume_offline)
1947 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1948 }
1949
edd16368
SC		 1950 /* Don't notify scsi mid layer of any changes the first time through
1951 * (or if there are no changes) scsi_scan_host will do it later the
1952 * first time through.
1953 */
8aa60681 1954 if (!changes)
edd16368
SC		 1955 goto free_and_out;
1956
edd16368
SC		 1957 /* Notify scsi mid layer of any removed devices */
1958 for (i = 0; i < nremoved; i++) {
1d33d85d
DB		 1959 if (removed[i] == NULL)
1960 continue;
096ccff4
KB		 1961 if (removed[i]->expose_device)
1962 hpsa_remove_device(h, removed[i]);
edd16368
SC		 1963 kfree(removed[i]);
1964 removed[i] = NULL;
1965 }
1966
1967 /* Notify scsi mid layer of any added devices */
1968 for (i = 0; i < nadded; i++) {
096ccff4
KB		 1969 int rc = 0;
1970
1d33d85d
DB		 1971 if (added[i] == NULL)
1972 continue;
2a168208 1973 if (!(added[i]->expose_device))
41ce4c35 1974 continue;
096ccff4
KB		 1975 rc = hpsa_add_device(h, added[i]);
1976 if (!rc)
edd16368 1977 continue;
096ccff4
KB		 1978 dev_warn(&h->pdev->dev,
1979 "addition failed %d, device not added.", rc);
edd16368
SC		 1980 /* now we have to remove it from h->dev,
1981 * since it didn't get added to scsi mid layer
1982 */
1983 fixup_botched_add(h, added[i]);
853633e8 1984 h->drv_req_rescan = 1;
edd16368
SC		 1985 }
1986
1987free_and_out:
1988 kfree(added);
1989 kfree(removed);
edd16368
SC		 1990}
1991
1992/*
9e03aa2f 1993 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1994 * Assume's h->devlock is held.
1995 */
1996static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1997 int bus, int target, int lun)
1998{
1999 int i;
2000 struct hpsa_scsi_dev_t *sd;
2001
2002 for (i = 0; i < h->ndevices; i++) {
2003 sd = h->dev[i];
2004 if (sd->bus == bus && sd->target == target && sd->lun == lun)
2005 return sd;
2006 }
2007 return NULL;
2008}
2009
edd16368
SC		 2010static int hpsa_slave_alloc(struct scsi_device *sdev)
2011{
2012 struct hpsa_scsi_dev_t *sd;
2013 unsigned long flags;
2014 struct ctlr_info *h;
2015
2016 h = sdev_to_hba(sdev);
2017 spin_lock_irqsave(&h->devlock, flags);
d04e62b9
KB		 2018 if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) {
2019 struct scsi_target *starget;
2020 struct sas_rphy *rphy;
2021
2022 starget = scsi_target(sdev);
2023 rphy = target_to_rphy(starget);
2024 sd = hpsa_find_device_by_sas_rphy(h, rphy);
2025 if (sd) {
2026 sd->target = sdev_id(sdev);
2027 sd->lun = sdev->lun;
2028 }
2029 } else
2030 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
2031 sdev_id(sdev), sdev->lun);
2032
2033 if (sd && sd->expose_device) {
03383736 2034 atomic_set(&sd->ioaccel_cmds_out, 0);
d04e62b9 2035 sdev->hostdata = sd;
41ce4c35
SC		 2036 } else
2037 sdev->hostdata = NULL;
edd16368
SC		 2038 spin_unlock_irqrestore(&h->devlock, flags);
2039 return 0;
2040}
2041
41ce4c35
SC		 2042/* configure scsi device based on internal per-device structure */
2043static int hpsa_slave_configure(struct scsi_device *sdev)
2044{
2045 struct hpsa_scsi_dev_t *sd;
2046 int queue_depth;
2047
2048 sd = sdev->hostdata;
2a168208 2049 sdev->no_uld_attach = !sd || !sd->expose_device;
41ce4c35
SC		 2050
2051 if (sd)
2052 queue_depth = sd->queue_depth != 0 ?
2053 sd->queue_depth : sdev->host->can_queue;
2054 else
2055 queue_depth = sdev->host->can_queue;
2056
2057 scsi_change_queue_depth(sdev, queue_depth);
2058
2059 return 0;
2060}
2061
edd16368
SC		 2062static void hpsa_slave_destroy(struct scsi_device *sdev)
2063{
bcc44255 2064 /* nothing to do. */
edd16368
SC		 2065}
2066
d9a729f3
WS		 2067static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
2068{
2069 int i;
2070
2071 if (!h->ioaccel2_cmd_sg_list)
2072 return;
2073 for (i = 0; i < h->nr_cmds; i++) {
2074 kfree(h->ioaccel2_cmd_sg_list[i]);
2075 h->ioaccel2_cmd_sg_list[i] = NULL;
2076 }
2077 kfree(h->ioaccel2_cmd_sg_list);
2078 h->ioaccel2_cmd_sg_list = NULL;
2079}
2080
2081static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
2082{
2083 int i;
2084
2085 if (h->chainsize <= 0)
2086 return 0;
2087
2088 h->ioaccel2_cmd_sg_list =
2089 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
2090 GFP_KERNEL);
2091 if (!h->ioaccel2_cmd_sg_list)
2092 return -ENOMEM;
2093 for (i = 0; i < h->nr_cmds; i++) {
2094 h->ioaccel2_cmd_sg_list[i] =
2095 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
2096 h->maxsgentries, GFP_KERNEL);
2097 if (!h->ioaccel2_cmd_sg_list[i])
2098 goto clean;
2099 }
2100 return 0;
2101
2102clean:
2103 hpsa_free_ioaccel2_sg_chain_blocks(h);
2104 return -ENOMEM;
2105}
2106
33a2ffce
SC		 2107static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
2108{
2109 int i;
2110
2111 if (!h->cmd_sg_list)
2112 return;
2113 for (i = 0; i < h->nr_cmds; i++) {
2114 kfree(h->cmd_sg_list[i]);
2115 h->cmd_sg_list[i] = NULL;
2116 }
2117 kfree(h->cmd_sg_list);
2118 h->cmd_sg_list = NULL;
2119}
2120
105a3dbc 2121static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
33a2ffce
SC		 2122{
2123 int i;
2124
2125 if (h->chainsize <= 0)
2126 return 0;
2127
2128 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
2129 GFP_KERNEL);
3d4e6af8
RE		 2130 if (!h->cmd_sg_list) {
2131 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 2132 return -ENOMEM;
3d4e6af8 2133 }
33a2ffce
SC		 2134 for (i = 0; i < h->nr_cmds; i++) {
2135 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
2136 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 2137 if (!h->cmd_sg_list[i]) {
2138 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 2139 goto clean;
3d4e6af8 2140 }
33a2ffce
SC		 2141 }
2142 return 0;
2143
2144clean:
2145 hpsa_free_sg_chain_blocks(h);
2146 return -ENOMEM;
2147}
2148
d9a729f3
WS		 2149static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
2150 struct io_accel2_cmd *cp, struct CommandList *c)
2151{
2152 struct ioaccel2_sg_element *chain_block;
2153 u64 temp64;
2154 u32 chain_size;
2155
2156 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
a736e9b6 2157 chain_size = le32_to_cpu(cp->sg[0].length);
d9a729f3
WS		 2158 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
2159 PCI_DMA_TODEVICE);
2160 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2161 /* prevent subsequent unmapping */
2162 cp->sg->address = 0;
2163 return -1;
2164 }
2165 cp->sg->address = cpu_to_le64(temp64);
2166 return 0;
2167}
2168
2169static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
2170 struct io_accel2_cmd *cp)
2171{
2172 struct ioaccel2_sg_element *chain_sg;
2173 u64 temp64;
2174 u32 chain_size;
2175
2176 chain_sg = cp->sg;
2177 temp64 = le64_to_cpu(chain_sg->address);
a736e9b6 2178 chain_size = le32_to_cpu(cp->sg[0].length);
d9a729f3
WS		 2179 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
2180}
2181
e2bea6df 2182static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 2183 struct CommandList *c)
2184{
2185 struct SGDescriptor *chain_sg, *chain_block;
2186 u64 temp64;
50a0decf 2187 u32 chain_len;
33a2ffce
SC		 2188
2189 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
2190 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 2191 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
2192 chain_len = sizeof(*chain_sg) *
2b08b3e9 2193 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 2194 chain_sg->Len = cpu_to_le32(chain_len);
2195 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 2196 PCI_DMA_TODEVICE);
e2bea6df
SC		 2197 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2198 /* prevent subsequent unmapping */
50a0decf 2199 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 2200 return -1;
2201 }
50a0decf 2202 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 2203 return 0;
33a2ffce
SC		 2204}
2205
2206static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
2207 struct CommandList *c)
2208{
2209 struct SGDescriptor *chain_sg;
33a2ffce 2210
50a0decf 2211 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 2212 return;
2213
2214 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 2215 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
2216 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 2217}
2218
a09c1441
ST		 2219
2220/* Decode the various types of errors on ioaccel2 path.
2221 * Return 1 for any error that should generate a RAID path retry.
2222 * Return 0 for errors that don't require a RAID path retry.
2223 */
2224static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 2225 struct CommandList *c,
2226 struct scsi_cmnd *cmd,
ba74fdc4
DB		 2227 struct io_accel2_cmd *c2,
2228 struct hpsa_scsi_dev_t *dev)
c349775e
ST		 2229{
2230 int data_len;
a09c1441 2231 int retry = 0;
c40820d5 2232 u32 ioaccel2_resid = 0;
c349775e
ST		 2233
2234 switch (c2->error_data.serv_response) {
2235 case IOACCEL2_SERV_RESPONSE_COMPLETE:
2236 switch (c2->error_data.status) {
2237 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
2238 break;
2239 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
ee6b1889 2240 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 2241 if (c2->error_data.data_present !=
ee6b1889
SC		 2242 IOACCEL2_SENSE_DATA_PRESENT) {
2243 memset(cmd->sense_buffer, 0,
2244 SCSI_SENSE_BUFFERSIZE);
c349775e 2245 break;
ee6b1889 2246 }
c349775e
ST		 2247 /* copy the sense data */
2248 data_len = c2->error_data.sense_data_len;
2249 if (data_len > SCSI_SENSE_BUFFERSIZE)
2250 data_len = SCSI_SENSE_BUFFERSIZE;
2251 if (data_len > sizeof(c2->error_data.sense_data_buff))
2252 data_len =
2253 sizeof(c2->error_data.sense_data_buff);
2254 memcpy(cmd->sense_buffer,
2255 c2->error_data.sense_data_buff, data_len);
a09c1441 2256 retry = 1;
c349775e
ST		 2257 break;
2258 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
a09c1441 2259 retry = 1;
c349775e
ST		 2260 break;
2261 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
a09c1441 2262 retry = 1;
c349775e
ST		 2263 break;
2264 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 2265 retry = 1;
c349775e
ST		 2266 break;
2267 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
a09c1441 2268 retry = 1;
c349775e
ST		 2269 break;
2270 default:
a09c1441 2271 retry = 1;
c349775e
ST		 2272 break;
2273 }
2274 break;
2275 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 2276 switch (c2->error_data.status) {
2277 case IOACCEL2_STATUS_SR_IO_ERROR:
2278 case IOACCEL2_STATUS_SR_IO_ABORTED:
2279 case IOACCEL2_STATUS_SR_OVERRUN:
2280 retry = 1;
2281 break;
2282 case IOACCEL2_STATUS_SR_UNDERRUN:
2283 cmd->result = (DID_OK << 16); /* host byte */
2284 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2285 ioaccel2_resid = get_unaligned_le32(
2286 &c2->error_data.resid_cnt[0]);
2287 scsi_set_resid(cmd, ioaccel2_resid);
2288 break;
2289 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
2290 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
2291 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
ba74fdc4
DB		 2292 /*
2293 * Did an HBA disk disappear? We will eventually
2294 * get a state change event from the controller but
2295 * in the meantime, we need to tell the OS that the
2296 * HBA disk is no longer there and stop I/O
2297 * from going down. This allows the potential re-insert
2298 * of the disk to get the same device node.
2299 */
2300 if (dev->physical_device && dev->expose_device) {
2301 cmd->result = DID_NO_CONNECT << 16;
2302 dev->removed = 1;
2303 h->drv_req_rescan = 1;
2304 dev_warn(&h->pdev->dev,
2305 "%s: device is gone!\n", __func__);
2306 } else
2307 /*
2308 * Retry by sending down the RAID path.
2309 * We will get an event from ctlr to
2310 * trigger rescan regardless.
2311 */
2312 retry = 1;
c40820d5
JH		 2313 break;
2314 default:
2315 retry = 1;
c40820d5 2316 }
c349775e
ST		 2317 break;
2318 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
2319 break;
2320 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
2321 break;
2322 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
a09c1441 2323 retry = 1;
c349775e
ST		 2324 break;
2325 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
c349775e
ST		 2326 break;
2327 default:
a09c1441 2328 retry = 1;
c349775e
ST		 2329 break;
2330 }
a09c1441
ST		 2331
2332 return retry; /* retry on raid path? */
c349775e
ST		 2333}
2334
a58e7e53
WS		 2335static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2336 struct CommandList *c)
2337{
d604f533
WS		 2338 bool do_wake = false;
2339
a58e7e53
WS		 2340 /*
2341 * Prevent the following race in the abort handler:
2342 *
2343 * 1. LLD is requested to abort a SCSI command
2344 * 2. The SCSI command completes
2345 * 3. The struct CommandList associated with step 2 is made available
2346 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2347 * 5. Abort handler follows scsi_cmnd->host_scribble and
2348 * finds struct CommandList and tries to aborts it
2349 * Now we have aborted the wrong command.
2350 *
d604f533
WS		 2351 * Reset c->scsi_cmd here so that the abort or reset handler will know
2352 * this command has completed. Then, check to see if the handler is
a58e7e53
WS		 2353 * waiting for this command, and, if so, wake it.
2354 */
2355 c->scsi_cmd = SCSI_CMD_IDLE;
d604f533 2356 mb(); /* Declare command idle before checking for pending events. */
a58e7e53 2357 if (c->abort_pending) {
d604f533 2358 do_wake = true;
a58e7e53 2359 c->abort_pending = false;
a58e7e53 2360 }
d604f533
WS		 2361 if (c->reset_pending) {
2362 unsigned long flags;
2363 struct hpsa_scsi_dev_t *dev;
2364
2365 /*
2366 * There appears to be a reset pending; lock the lock and
2367 * reconfirm. If so, then decrement the count of outstanding
2368 * commands and wake the reset command if this is the last one.
2369 */
2370 spin_lock_irqsave(&h->lock, flags);
2371 dev = c->reset_pending; /* Re-fetch under the lock. */
2372 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2373 do_wake = true;
2374 c->reset_pending = NULL;
2375 spin_unlock_irqrestore(&h->lock, flags);
2376 }
2377
2378 if (do_wake)
2379 wake_up_all(&h->event_sync_wait_queue);
a58e7e53
WS		 2380}
2381
73153fe5
WS		 2382static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2383 struct CommandList *c)
2384{
2385 hpsa_cmd_resolve_events(h, c);
2386 cmd_tagged_free(h, c);
2387}
2388
8a0ff92c
WS		 2389static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2390 struct CommandList *c, struct scsi_cmnd *cmd)
2391{
73153fe5 2392 hpsa_cmd_resolve_and_free(h, c);
8a0ff92c
WS		 2393 cmd->scsi_done(cmd);
2394}
2395
2396static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2397{
2398 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2399 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2400}
2401
a58e7e53
WS		 2402static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2403{
2404 cmd->result = DID_ABORT << 16;
2405}
2406
2407static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2408 struct scsi_cmnd *cmd)
2409{
2410 hpsa_set_scsi_cmd_aborted(cmd);
2411 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2412 c->Request.CDB, c->err_info->ScsiStatus);
73153fe5 2413 hpsa_cmd_resolve_and_free(h, c);
a58e7e53
WS		 2414}
2415
c349775e
ST		 2416static void process_ioaccel2_completion(struct ctlr_info *h,
2417 struct CommandList *c, struct scsi_cmnd *cmd,
2418 struct hpsa_scsi_dev_t *dev)
2419{
2420 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2421
2422 /* check for good status */
2423 if (likely(c2->error_data.serv_response == 0 &&
8a0ff92c
WS		 2424 c2->error_data.status == 0))
2425 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e 2426
8a0ff92c
WS		 2427 /*
2428 * Any RAID offload error results in retry which will use
c349775e
ST		 2429 * the normal I/O path so the controller can handle whatever's
2430 * wrong.
2431 */
f3f01730 2432 if (is_logical_device(dev) &&
c349775e
ST		 2433 c2->error_data.serv_response ==
2434 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc 2435 if (c2->error_data.status ==
064d1b1d 2436 IOACCEL2_STATUS_SR_IOACCEL_DISABLED) {
080ef1cc 2437 dev->offload_enabled = 0;
064d1b1d
DB		 2438 dev->offload_to_be_enabled = 0;
2439 }
8a0ff92c
WS		 2440
2441 return hpsa_retry_cmd(h, c);
a09c1441 2442 }
080ef1cc 2443
ba74fdc4 2444 if (handle_ioaccel_mode2_error(h, c, cmd, c2, dev))
8a0ff92c 2445 return hpsa_retry_cmd(h, c);
080ef1cc 2446
8a0ff92c 2447 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e
ST		 2448}
2449
9437ac43
SC		 2450/* Returns 0 on success, < 0 otherwise. */
2451static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2452 struct CommandList *cp)
2453{
2454 u8 tmf_status = cp->err_info->ScsiStatus;
2455
2456 switch (tmf_status) {
2457 case CISS_TMF_COMPLETE:
2458 /*
2459 * CISS_TMF_COMPLETE never happens, instead,
2460 * ei->CommandStatus == 0 for this case.
2461 */
2462 case CISS_TMF_SUCCESS:
2463 return 0;
2464 case CISS_TMF_INVALID_FRAME:
2465 case CISS_TMF_NOT_SUPPORTED:
2466 case CISS_TMF_FAILED:
2467 case CISS_TMF_WRONG_LUN:
2468 case CISS_TMF_OVERLAPPED_TAG:
2469 break;
2470 default:
2471 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2472 tmf_status);
2473 break;
2474 }
2475 return -tmf_status;
2476}
2477
1fb011fb 2478static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2479{
2480 struct scsi_cmnd *cmd;
2481 struct ctlr_info *h;
2482 struct ErrorInfo *ei;
283b4a9b 2483 struct hpsa_scsi_dev_t *dev;
d9a729f3 2484 struct io_accel2_cmd *c2;
edd16368 2485
9437ac43
SC		 2486 u8 sense_key;
2487 u8 asc; /* additional sense code */
2488 u8 ascq; /* additional sense code qualifier */
db111e18 2489 unsigned long sense_data_size;
edd16368
SC		 2490
2491 ei = cp->err_info;
7fa3030c 2492 cmd = cp->scsi_cmd;
edd16368 2493 h = cp->h;
283b4a9b 2494 dev = cmd->device->hostdata;
d9a729f3 2495 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2496
2497 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2498 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2499 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2500 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2501
d9a729f3
WS		 2502 if ((cp->cmd_type == CMD_IOACCEL2) &&
2503 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2504 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2505
edd16368
SC		 2506 cmd->result = (DID_OK << 16); /* host byte */
2507 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2508
03383736
DB		 2509 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2510 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2511
25163bd5
WS		 2512 /*
2513 * We check for lockup status here as it may be set for
2514 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2515 * fail_all_oustanding_cmds()
2516 */
2517 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2518 /* DID_NO_CONNECT will prevent a retry */
2519 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 2520 return hpsa_cmd_free_and_done(h, cp, cmd);
25163bd5
WS		 2521 }
2522
d604f533
WS		 2523 if ((unlikely(hpsa_is_pending_event(cp)))) {
2524 if (cp->reset_pending)
2525 return hpsa_cmd_resolve_and_free(h, cp);
2526 if (cp->abort_pending)
2527 return hpsa_cmd_abort_and_free(h, cp, cmd);
2528 }
2529
c349775e
ST		 2530 if (cp->cmd_type == CMD_IOACCEL2)
2531 return process_ioaccel2_completion(h, cp, cmd, dev);
2532
6aa4c361 2533 scsi_set_resid(cmd, ei->ResidualCnt);
8a0ff92c
WS		 2534 if (ei->CommandStatus == 0)
2535 return hpsa_cmd_free_and_done(h, cp, cmd);
6aa4c361 2536
e1f7de0c
MG		 2537 /* For I/O accelerator commands, copy over some fields to the normal
2538 * CISS header used below for error handling.
2539 */
2540 if (cp->cmd_type == CMD_IOACCEL1) {
2541 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2542 cp->Header.SGList = scsi_sg_count(cmd);
2543 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2544 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2545 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2546 cp->Header.tag = c->tag;
e1f7de0c
MG		 2547 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2548 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2549
2550 /* Any RAID offload error results in retry which will use
2551 * the normal I/O path so the controller can handle whatever's
2552 * wrong.
2553 */
f3f01730 2554 if (is_logical_device(dev)) {
283b4a9b
SC		 2555 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2556 dev->offload_enabled = 0;
d604f533 2557 return hpsa_retry_cmd(h, cp);
283b4a9b 2558 }
e1f7de0c
MG		 2559 }
2560
edd16368
SC		 2561 /* an error has occurred */
2562 switch (ei->CommandStatus) {
2563
2564 case CMD_TARGET_STATUS:
9437ac43
SC		 2565 cmd->result |= ei->ScsiStatus;
2566 /* copy the sense data */
2567 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2568 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2569 else
2570 sense_data_size = sizeof(ei->SenseInfo);
2571 if (ei->SenseLen < sense_data_size)
2572 sense_data_size = ei->SenseLen;
2573 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2574 if (ei->ScsiStatus)
2575 decode_sense_data(ei->SenseInfo, sense_data_size,
2576 &sense_key, &asc, &ascq);
edd16368 2577 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2578 if (sense_key == ABORTED_COMMAND) {
2e311fba 2579 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2580 break;
2581 }
edd16368
SC		 2582 break;
2583 }
edd16368
SC		 2584 /* Problem was not a check condition
2585 * Pass it up to the upper layers...
2586 */
2587 if (ei->ScsiStatus) {
2588 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2589 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2590 "Returning result: 0x%x\n",
2591 cp, ei->ScsiStatus,
2592 sense_key, asc, ascq,
2593 cmd->result);
2594 } else { /* scsi status is zero??? How??? */
2595 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2596 "Returning no connection.\n", cp),
2597
2598 /* Ordinarily, this case should never happen,
2599 * but there is a bug in some released firmware
2600 * revisions that allows it to happen if, for
2601 * example, a 4100 backplane loses power and
2602 * the tape drive is in it. We assume that
2603 * it's a fatal error of some kind because we
2604 * can't show that it wasn't. We will make it
2605 * look like selection timeout since that is
2606 * the most common reason for this to occur,
2607 * and it's severe enough.
2608 */
2609
2610 cmd->result = DID_NO_CONNECT << 16;
2611 }
2612 break;
2613
2614 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2615 break;
2616 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2617 dev_warn(&h->pdev->dev,
2618 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2619 break;
2620 case CMD_INVALID: {
2621 /* print_bytes(cp, sizeof(*cp), 1, 0);
2622 print_cmd(cp); */
2623 /* We get CMD_INVALID if you address a non-existent device
2624 * instead of a selection timeout (no response). You will
2625 * see this if you yank out a drive, then try to access it.
2626 * This is kind of a shame because it means that any other
2627 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2628 * missing target. */
2629 cmd->result = DID_NO_CONNECT << 16;
2630 }
2631 break;
2632 case CMD_PROTOCOL_ERR:
256d0eaa 2633 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2634 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2635 cp->Request.CDB);
edd16368
SC		 2636 break;
2637 case CMD_HARDWARE_ERR:
2638 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2639 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2640 cp->Request.CDB);
edd16368
SC		 2641 break;
2642 case CMD_CONNECTION_LOST:
2643 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2644 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2645 cp->Request.CDB);
edd16368
SC		 2646 break;
2647 case CMD_ABORTED:
a58e7e53
WS		 2648 /* Return now to avoid calling scsi_done(). */
2649 return hpsa_cmd_abort_and_free(h, cp, cmd);
edd16368
SC		 2650 case CMD_ABORT_FAILED:
2651 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2652 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2653 cp->Request.CDB);
edd16368
SC		 2654 break;
2655 case CMD_UNSOLICITED_ABORT:
f6e76055 2656 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2657 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2658 cp->Request.CDB);
edd16368
SC		 2659 break;
2660 case CMD_TIMEOUT:
2661 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2662 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2663 cp->Request.CDB);
edd16368 2664 break;
1d5e2ed0
SC		 2665 case CMD_UNABORTABLE:
2666 cmd->result = DID_ERROR << 16;
2667 dev_warn(&h->pdev->dev, "Command unabortable\n");
2668 break;
9437ac43
SC		 2669 case CMD_TMF_STATUS:
2670 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2671 cmd->result = DID_ERROR << 16;
2672 break;
283b4a9b
SC		 2673 case CMD_IOACCEL_DISABLED:
2674 /* This only handles the direct pass-through case since RAID
2675 * offload is handled above. Just attempt a retry.
2676 */
2677 cmd->result = DID_SOFT_ERROR << 16;
2678 dev_warn(&h->pdev->dev,
2679 "cp %p had HP SSD Smart Path error\n", cp);
2680 break;
edd16368
SC		 2681 default:
2682 cmd->result = DID_ERROR << 16;
2683 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2684 cp, ei->CommandStatus);
2685 }
8a0ff92c
WS		 2686
2687 return hpsa_cmd_free_and_done(h, cp, cmd);
edd16368
SC		 2688}
2689
edd16368
SC		 2690static void hpsa_pci_unmap(struct pci_dev *pdev,
2691 struct CommandList *c, int sg_used, int data_direction)
2692{
2693 int i;
edd16368 2694
50a0decf
SC		 2695 for (i = 0; i < sg_used; i++)
2696 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2697 le32_to_cpu(c->SG[i].Len),
2698 data_direction);
edd16368
SC		 2699}
2700
a2dac136 2701static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2702 struct CommandList *cp,
2703 unsigned char *buf,
2704 size_t buflen,
2705 int data_direction)
2706{
01a02ffc 2707 u64 addr64;
edd16368
SC		 2708
2709 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2710 cp->Header.SGList = 0;
50a0decf 2711 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2712 return 0;
edd16368
SC		 2713 }
2714
50a0decf 2715 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2716 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2717 /* Prevent subsequent unmap of something never mapped */
eceaae18 2718 cp->Header.SGList = 0;
50a0decf 2719 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2720 return -1;
eceaae18 2721 }
50a0decf
SC		 2722 cp->SG[0].Addr = cpu_to_le64(addr64);
2723 cp->SG[0].Len = cpu_to_le32(buflen);
2724 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2725 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2726 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2727 return 0;
edd16368
SC		 2728}
2729
25163bd5
WS		 2730#define NO_TIMEOUT ((unsigned long) -1)
2731#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2732static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2733 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2734{
2735 DECLARE_COMPLETION_ONSTACK(wait);
2736
2737 c->waiting = &wait;
25163bd5
WS		 2738 __enqueue_cmd_and_start_io(h, c, reply_queue);
2739 if (timeout_msecs == NO_TIMEOUT) {
2740 /* TODO: get rid of this no-timeout thing */
2741 wait_for_completion_io(&wait);
2742 return IO_OK;
2743 }
2744 if (!wait_for_completion_io_timeout(&wait,
2745 msecs_to_jiffies(timeout_msecs))) {
2746 dev_warn(&h->pdev->dev, "Command timed out.\n");
2747 return -ETIMEDOUT;
2748 }
2749 return IO_OK;
2750}
2751
2752static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2753 int reply_queue, unsigned long timeout_msecs)
2754{
2755 if (unlikely(lockup_detected(h))) {
2756 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2757 return IO_OK;
2758 }
2759 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2760}
2761
094963da
SC		 2762static u32 lockup_detected(struct ctlr_info *h)
2763{
2764 int cpu;
2765 u32 rc, *lockup_detected;
2766
2767 cpu = get_cpu();
2768 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2769 rc = *lockup_detected;
2770 put_cpu();
2771 return rc;
2772}
2773
9c2fc160 2774#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2775static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2776 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2777{
9c2fc160 2778 int backoff_time = 10, retry_count = 0;
25163bd5 2779 int rc;
edd16368
SC		 2780
2781 do {
7630abd0 2782 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2783 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2784 timeout_msecs);
2785 if (rc)
2786 break;
edd16368 2787 retry_count++;
9c2fc160
SC		 2788 if (retry_count > 3) {
2789 msleep(backoff_time);
2790 if (backoff_time < 1000)
2791 backoff_time *= 2;
2792 }
852af20a 2793 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2794 check_for_busy(h, c)) &&
2795 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2796 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2797 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2798 rc = -EIO;
2799 return rc;
edd16368
SC		 2800}
2801
d1e8beac
SC		 2802static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2803 struct CommandList *c)
edd16368 2804{
d1e8beac
SC		 2805 const u8 *cdb = c->Request.CDB;
2806 const u8 *lun = c->Header.LUN.LunAddrBytes;
2807
2808 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2809 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2810 txt, lun[0], lun[1], lun[2], lun[3],
2811 lun[4], lun[5], lun[6], lun[7],
2812 cdb[0], cdb[1], cdb[2], cdb[3],
2813 cdb[4], cdb[5], cdb[6], cdb[7],
2814 cdb[8], cdb[9], cdb[10], cdb[11],
2815 cdb[12], cdb[13], cdb[14], cdb[15]);
2816}
2817
2818static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2819 struct CommandList *cp)
2820{
2821 const struct ErrorInfo *ei = cp->err_info;
edd16368 2822 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2823 u8 sense_key, asc, ascq;
2824 int sense_len;
edd16368 2825
edd16368
SC		 2826 switch (ei->CommandStatus) {
2827 case CMD_TARGET_STATUS:
9437ac43
SC		 2828 if (ei->SenseLen > sizeof(ei->SenseInfo))
2829 sense_len = sizeof(ei->SenseInfo);
2830 else
2831 sense_len = ei->SenseLen;
2832 decode_sense_data(ei->SenseInfo, sense_len,
2833 &sense_key, &asc, &ascq);
d1e8beac
SC		 2834 hpsa_print_cmd(h, "SCSI status", cp);
2835 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2836 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2837 sense_key, asc, ascq);
d1e8beac 2838 else
9437ac43 2839 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2840 if (ei->ScsiStatus == 0)
2841 dev_warn(d, "SCSI status is abnormally zero. "
2842 "(probably indicates selection timeout "
2843 "reported incorrectly due to a known "
2844 "firmware bug, circa July, 2001.)\n");
2845 break;
2846 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2847 break;
2848 case CMD_DATA_OVERRUN:
d1e8beac 2849 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2850 break;
2851 case CMD_INVALID: {
2852 /* controller unfortunately reports SCSI passthru's
2853 * to non-existent targets as invalid commands.
2854 */
d1e8beac
SC		 2855 hpsa_print_cmd(h, "invalid command", cp);
2856 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2857 }
2858 break;
2859 case CMD_PROTOCOL_ERR:
d1e8beac 2860 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2861 break;
2862 case CMD_HARDWARE_ERR:
d1e8beac 2863 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2864 break;
2865 case CMD_CONNECTION_LOST:
d1e8beac 2866 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2867 break;
2868 case CMD_ABORTED:
d1e8beac 2869 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2870 break;
2871 case CMD_ABORT_FAILED:
d1e8beac 2872 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2873 break;
2874 case CMD_UNSOLICITED_ABORT:
d1e8beac 2875 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2876 break;
2877 case CMD_TIMEOUT:
d1e8beac 2878 hpsa_print_cmd(h, "timed out", cp);
edd16368 2879 break;
1d5e2ed0 2880 case CMD_UNABORTABLE:
d1e8beac 2881 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2882 break;
25163bd5
WS		 2883 case CMD_CTLR_LOCKUP:
2884 hpsa_print_cmd(h, "controller lockup detected", cp);
2885 break;
edd16368 2886 default:
d1e8beac
SC		 2887 hpsa_print_cmd(h, "unknown status", cp);
2888 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2889 ei->CommandStatus);
2890 }
2891}
2892
2893static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2894 u16 page, unsigned char *buf,
edd16368
SC		 2895 unsigned char bufsize)
2896{
2897 int rc = IO_OK;
2898 struct CommandList *c;
2899 struct ErrorInfo *ei;
2900
45fcb86e 2901 c = cmd_alloc(h);
edd16368 2902
a2dac136
SC		 2903 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2904 page, scsi3addr, TYPE_CMD)) {
2905 rc = -1;
2906 goto out;
2907 }
25163bd5 2908 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 2909 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 2910 if (rc)
2911 goto out;
edd16368
SC		 2912 ei = c->err_info;
2913 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2914 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2915 rc = -1;
2916 }
a2dac136 2917out:
45fcb86e 2918 cmd_free(h, c);
edd16368
SC		 2919 return rc;
2920}
2921
bf711ac6 2922static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2923 u8 reset_type, int reply_queue)
edd16368
SC		 2924{
2925 int rc = IO_OK;
2926 struct CommandList *c;
2927 struct ErrorInfo *ei;
2928
45fcb86e 2929 c = cmd_alloc(h);
edd16368 2930
edd16368 2931
a2dac136 2932 /* fill_cmd can't fail here, no data buffer to map. */
0b9b7b6e 2933 (void) fill_cmd(c, reset_type, h, NULL, 0, 0,
bf711ac6 2934 scsi3addr, TYPE_MSG);
c448ecfa 2935 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
25163bd5
WS		 2936 if (rc) {
2937 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2938 goto out;
2939 }
edd16368
SC		 2940 /* no unmap needed here because no data xfer. */
2941
2942 ei = c->err_info;
2943 if (ei->CommandStatus != 0) {
d1e8beac 2944 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2945 rc = -1;
2946 }
25163bd5 2947out:
45fcb86e 2948 cmd_free(h, c);
edd16368
SC		 2949 return rc;
2950}
2951
d604f533
WS		 2952static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2953 struct hpsa_scsi_dev_t *dev,
2954 unsigned char *scsi3addr)
2955{
2956 int i;
2957 bool match = false;
2958 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2959 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2960
2961 if (hpsa_is_cmd_idle(c))
2962 return false;
2963
2964 switch (c->cmd_type) {
2965 case CMD_SCSI:
2966 case CMD_IOCTL_PEND:
2967 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2968 sizeof(c->Header.LUN.LunAddrBytes));
2969 break;
2970
2971 case CMD_IOACCEL1:
2972 case CMD_IOACCEL2:
2973 if (c->phys_disk == dev) {
2974 /* HBA mode match */
2975 match = true;
2976 } else {
2977 /* Possible RAID mode -- check each phys dev. */
2978 /* FIXME: Do we need to take out a lock here? If
2979 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2980 * instead. */
2981 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2982 /* FIXME: an alternate test might be
2983 *
2984 * match = dev->phys_disk[i]->ioaccel_handle
2985 * == c2->scsi_nexus; */
2986 match = dev->phys_disk[i] == c->phys_disk;
2987 }
2988 }
2989 break;
2990
2991 case IOACCEL2_TMF:
2992 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2993 match = dev->phys_disk[i]->ioaccel_handle ==
2994 le32_to_cpu(ac->it_nexus);
2995 }
2996 break;
2997
2998 case 0: /* The command is in the middle of being initialized. */
2999 match = false;
3000 break;
3001
3002 default:
3003 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
3004 c->cmd_type);
3005 BUG();
3006 }
3007
3008 return match;
3009}
3010
3011static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
3012 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
3013{
3014 int i;
3015 int rc = 0;
3016
3017 /* We can really only handle one reset at a time */
3018 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
3019 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
3020 return -EINTR;
3021 }
3022
3023 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
3024
3025 for (i = 0; i < h->nr_cmds; i++) {
3026 struct CommandList *c = h->cmd_pool + i;
3027 int refcount = atomic_inc_return(&c->refcount);
3028
3029 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
3030 unsigned long flags;
3031
3032 /*
3033 * Mark the target command as having a reset pending,
3034 * then lock a lock so that the command cannot complete
3035 * while we're considering it. If the command is not
3036 * idle then count it; otherwise revoke the event.
3037 */
3038 c->reset_pending = dev;
3039 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
3040 if (!hpsa_is_cmd_idle(c))
3041 atomic_inc(&dev->reset_cmds_out);
3042 else
3043 c->reset_pending = NULL;
3044 spin_unlock_irqrestore(&h->lock, flags);
3045 }
3046
3047 cmd_free(h, c);
3048 }
3049
3050 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
3051 if (!rc)
3052 wait_event(h->event_sync_wait_queue,
3053 atomic_read(&dev->reset_cmds_out) == 0 ||
3054 lockup_detected(h));
3055
3056 if (unlikely(lockup_detected(h))) {
77678d3a
DB		 3057 dev_warn(&h->pdev->dev,
3058 "Controller lockup detected during reset wait\n");
3059 rc = -ENODEV;
3060 }
d604f533
WS		 3061
3062 if (unlikely(rc))
3063 atomic_set(&dev->reset_cmds_out, 0);
3064
3065 mutex_unlock(&h->reset_mutex);
3066 return rc;
3067}
3068
edd16368
SC		 3069static void hpsa_get_raid_level(struct ctlr_info *h,
3070 unsigned char *scsi3addr, unsigned char *raid_level)
3071{
3072 int rc;
3073 unsigned char *buf;
3074
3075 *raid_level = RAID_UNKNOWN;
3076 buf = kzalloc(64, GFP_KERNEL);
3077 if (!buf)
3078 return;
b7bb24eb 3079 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 3080 if (rc == 0)
3081 *raid_level = buf[8];
3082 if (*raid_level > RAID_UNKNOWN)
3083 *raid_level = RAID_UNKNOWN;
3084 kfree(buf);
3085 return;
3086}
3087
283b4a9b
SC		 3088#define HPSA_MAP_DEBUG
3089#ifdef HPSA_MAP_DEBUG
3090static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
3091 struct raid_map_data *map_buff)
3092{
3093 struct raid_map_disk_data *dd = &map_buff->data[0];
3094 int map, row, col;
3095 u16 map_cnt, row_cnt, disks_per_row;
3096
3097 if (rc != 0)
3098 return;
3099
2ba8bfc8
SC		 3100 /* Show details only if debugging has been activated. */
3101 if (h->raid_offload_debug < 2)
3102 return;
3103
283b4a9b
SC		 3104 dev_info(&h->pdev->dev, "structure_size = %u\n",
3105 le32_to_cpu(map_buff->structure_size));
3106 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
3107 le32_to_cpu(map_buff->volume_blk_size));
3108 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
3109 le64_to_cpu(map_buff->volume_blk_cnt));
3110 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
3111 map_buff->phys_blk_shift);
3112 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
3113 map_buff->parity_rotation_shift);
3114 dev_info(&h->pdev->dev, "strip_size = %u\n",
3115 le16_to_cpu(map_buff->strip_size));
3116 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
3117 le64_to_cpu(map_buff->disk_starting_blk));
3118 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
3119 le64_to_cpu(map_buff->disk_blk_cnt));
3120 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
3121 le16_to_cpu(map_buff->data_disks_per_row));
3122 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
3123 le16_to_cpu(map_buff->metadata_disks_per_row));
3124 dev_info(&h->pdev->dev, "row_cnt = %u\n",
3125 le16_to_cpu(map_buff->row_cnt));
3126 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
3127 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 3128 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 3129 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 3130 dev_info(&h->pdev->dev, "encrypytion = %s\n",
3131 le16_to_cpu(map_buff->flags) &
3132 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 3133 dev_info(&h->pdev->dev, "dekindex = %u\n",
3134 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 3135 map_cnt = le16_to_cpu(map_buff->layout_map_count);
3136 for (map = 0; map < map_cnt; map++) {
3137 dev_info(&h->pdev->dev, "Map%u:\n", map);
3138 row_cnt = le16_to_cpu(map_buff->row_cnt);
3139 for (row = 0; row < row_cnt; row++) {
3140 dev_info(&h->pdev->dev, " Row%u:\n", row);
3141 disks_per_row =
3142 le16_to_cpu(map_buff->data_disks_per_row);
3143 for (col = 0; col < disks_per_row; col++, dd++)
3144 dev_info(&h->pdev->dev,
3145 " D%02u: h=0x%04x xor=%u,%u\n",
3146 col, dd->ioaccel_handle,
3147 dd->xor_mult[0], dd->xor_mult[1]);
3148 disks_per_row =
3149 le16_to_cpu(map_buff->metadata_disks_per_row);
3150 for (col = 0; col < disks_per_row; col++, dd++)
3151 dev_info(&h->pdev->dev,
3152 " M%02u: h=0x%04x xor=%u,%u\n",
3153 col, dd->ioaccel_handle,
3154 dd->xor_mult[0], dd->xor_mult[1]);
3155 }
3156 }
3157}
3158#else
3159static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
3160 __attribute__((unused)) int rc,
3161 __attribute__((unused)) struct raid_map_data *map_buff)
3162{
3163}
3164#endif
3165
3166static int hpsa_get_raid_map(struct ctlr_info *h,
3167 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3168{
3169 int rc = 0;
3170 struct CommandList *c;
3171 struct ErrorInfo *ei;
3172
45fcb86e 3173 c = cmd_alloc(h);
bf43caf3 3174
283b4a9b
SC		 3175 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
3176 sizeof(this_device->raid_map), 0,
3177 scsi3addr, TYPE_CMD)) {
2dd02d74
RE		 3178 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
3179 cmd_free(h, c);
3180 return -1;
283b4a9b 3181 }
25163bd5 3182 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3183 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 3184 if (rc)
3185 goto out;
283b4a9b
SC		 3186 ei = c->err_info;
3187 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3188 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 3189 rc = -1;
3190 goto out;
283b4a9b 3191 }
45fcb86e 3192 cmd_free(h, c);
283b4a9b
SC		 3193
3194 /* @todo in the future, dynamically allocate RAID map memory */
3195 if (le32_to_cpu(this_device->raid_map.structure_size) >
3196 sizeof(this_device->raid_map)) {
3197 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
3198 rc = -1;
3199 }
3200 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
3201 return rc;
25163bd5
WS		 3202out:
3203 cmd_free(h, c);
3204 return rc;
283b4a9b
SC		 3205}
3206
d04e62b9
KB		 3207static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h,
3208 unsigned char scsi3addr[], u16 bmic_device_index,
3209 struct bmic_sense_subsystem_info *buf, size_t bufsize)
3210{
3211 int rc = IO_OK;
3212 struct CommandList *c;
3213 struct ErrorInfo *ei;
3214
3215 c = cmd_alloc(h);
3216
3217 rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize,
3218 0, RAID_CTLR_LUNID, TYPE_CMD);
3219 if (rc)
3220 goto out;
3221
3222 c->Request.CDB[2] = bmic_device_index & 0xff;
3223 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3224
3225 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3226 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
d04e62b9
KB		 3227 if (rc)
3228 goto out;
3229 ei = c->err_info;
3230 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3231 hpsa_scsi_interpret_error(h, c);
3232 rc = -1;
3233 }
3234out:
3235 cmd_free(h, c);
3236 return rc;
3237}
3238
66749d0d
ST		 3239static int hpsa_bmic_id_controller(struct ctlr_info *h,
3240 struct bmic_identify_controller *buf, size_t bufsize)
3241{
3242 int rc = IO_OK;
3243 struct CommandList *c;
3244 struct ErrorInfo *ei;
3245
3246 c = cmd_alloc(h);
3247
3248 rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize,
3249 0, RAID_CTLR_LUNID, TYPE_CMD);
3250 if (rc)
3251 goto out;
3252
3253 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3254 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
66749d0d
ST		 3255 if (rc)
3256 goto out;
3257 ei = c->err_info;
3258 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3259 hpsa_scsi_interpret_error(h, c);
3260 rc = -1;
3261 }
3262out:
3263 cmd_free(h, c);
3264 return rc;
3265}
3266
03383736
DB		 3267static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
3268 unsigned char scsi3addr[], u16 bmic_device_index,
3269 struct bmic_identify_physical_device *buf, size_t bufsize)
3270{
3271 int rc = IO_OK;
3272 struct CommandList *c;
3273 struct ErrorInfo *ei;
3274
3275 c = cmd_alloc(h);
3276 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
3277 0, RAID_CTLR_LUNID, TYPE_CMD);
3278 if (rc)
3279 goto out;
3280
3281 c->Request.CDB[2] = bmic_device_index & 0xff;
3282 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3283
25163bd5 3284 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
c448ecfa 3285 DEFAULT_TIMEOUT);
03383736
DB		 3286 ei = c->err_info;
3287 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3288 hpsa_scsi_interpret_error(h, c);
3289 rc = -1;
3290 }
3291out:
3292 cmd_free(h, c);
d04e62b9 3293
03383736
DB		 3294 return rc;
3295}
3296
cca8f13b
DB		 3297/*
3298 * get enclosure information
3299 * struct ReportExtendedLUNdata *rlep - Used for BMIC drive number
3300 * struct hpsa_scsi_dev_t *encl_dev - device entry for enclosure
3301 * Uses id_physical_device to determine the box_index.
3302 */
3303static void hpsa_get_enclosure_info(struct ctlr_info *h,
3304 unsigned char *scsi3addr,
3305 struct ReportExtendedLUNdata *rlep, int rle_index,
3306 struct hpsa_scsi_dev_t *encl_dev)
3307{
3308 int rc = -1;
3309 struct CommandList *c = NULL;
3310 struct ErrorInfo *ei = NULL;
3311 struct bmic_sense_storage_box_params *bssbp = NULL;
3312 struct bmic_identify_physical_device *id_phys = NULL;
3313 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
3314 u16 bmic_device_index = 0;
3315
3316 bmic_device_index = GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]);
3317
17a9e54a
DB		 3318 if (bmic_device_index == 0xFF00 || MASKED_DEVICE(&rle->lunid[0])) {
3319 rc = IO_OK;
cca8f13b 3320 goto out;
17a9e54a 3321 }
cca8f13b
DB		 3322
3323 bssbp = kzalloc(sizeof(*bssbp), GFP_KERNEL);
3324 if (!bssbp)
3325 goto out;
3326
3327 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
3328 if (!id_phys)
3329 goto out;
3330
3331 rc = hpsa_bmic_id_physical_device(h, scsi3addr, bmic_device_index,
3332 id_phys, sizeof(*id_phys));
3333 if (rc) {
3334 dev_warn(&h->pdev->dev, "%s: id_phys failed %d bdi[0x%x]\n",
3335 __func__, encl_dev->external, bmic_device_index);
3336 goto out;
3337 }
3338
3339 c = cmd_alloc(h);
3340
3341 rc = fill_cmd(c, BMIC_SENSE_STORAGE_BOX_PARAMS, h, bssbp,
3342 sizeof(*bssbp), 0, RAID_CTLR_LUNID, TYPE_CMD);
3343
3344 if (rc)
3345 goto out;
3346
3347 if (id_phys->phys_connector[1] == 'E')
3348 c->Request.CDB[5] = id_phys->box_index;
3349 else
3350 c->Request.CDB[5] = 0;
3351
3352 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
c448ecfa 3353 DEFAULT_TIMEOUT);
cca8f13b
DB		 3354 if (rc)
3355 goto out;
3356
3357 ei = c->err_info;
3358 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3359 rc = -1;
3360 goto out;
3361 }
3362
3363 encl_dev->box[id_phys->active_path_number] = bssbp->phys_box_on_port;
3364 memcpy(&encl_dev->phys_connector[id_phys->active_path_number],
3365 bssbp->phys_connector, sizeof(bssbp->phys_connector));
3366
3367 rc = IO_OK;
3368out:
3369 kfree(bssbp);
3370 kfree(id_phys);
3371
3372 if (c)
3373 cmd_free(h, c);
3374
3375 if (rc != IO_OK)
3376 hpsa_show_dev_msg(KERN_INFO, h, encl_dev,
3377 "Error, could not get enclosure information\n");
3378}
3379
d04e62b9
KB		 3380static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h,
3381 unsigned char *scsi3addr)
3382{
3383 struct ReportExtendedLUNdata *physdev;
3384 u32 nphysicals;
3385 u64 sa = 0;
3386 int i;
3387
3388 physdev = kzalloc(sizeof(*physdev), GFP_KERNEL);
3389 if (!physdev)
3390 return 0;
3391
3392 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
3393 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3394 kfree(physdev);
3395 return 0;
3396 }
3397 nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24;
3398
3399 for (i = 0; i < nphysicals; i++)
3400 if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) {
3401 sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]);
3402 break;
3403 }
3404
3405 kfree(physdev);
3406
3407 return sa;
3408}
3409
3410static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr,
3411 struct hpsa_scsi_dev_t *dev)
3412{
3413 int rc;
3414 u64 sa = 0;
3415
3416 if (is_hba_lunid(scsi3addr)) {
3417 struct bmic_sense_subsystem_info *ssi;
3418
3419 ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
3420 if (ssi == NULL) {
3421 dev_warn(&h->pdev->dev,
3422 "%s: out of memory\n", __func__);
3423 return;
3424 }
3425
3426 rc = hpsa_bmic_sense_subsystem_information(h,
3427 scsi3addr, 0, ssi, sizeof(*ssi));
3428 if (rc == 0) {
3429 sa = get_unaligned_be64(ssi->primary_world_wide_id);
3430 h->sas_address = sa;
3431 }
3432
3433 kfree(ssi);
3434 } else
3435 sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr);
3436
3437 dev->sas_address = sa;
3438}
3439
3440/* Get a device id from inquiry page 0x83 */
1b70150a
SC		 3441static int hpsa_vpd_page_supported(struct ctlr_info *h,
3442 unsigned char scsi3addr[], u8 page)
3443{
3444 int rc;
3445 int i;
3446 int pages;
3447 unsigned char *buf, bufsize;
3448
3449 buf = kzalloc(256, GFP_KERNEL);
3450 if (!buf)
3451 return 0;
3452
3453 /* Get the size of the page list first */
3454 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3455 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3456 buf, HPSA_VPD_HEADER_SZ);
3457 if (rc != 0)
3458 goto exit_unsupported;
3459 pages = buf[3];
3460 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3461 bufsize = pages + HPSA_VPD_HEADER_SZ;
3462 else
3463 bufsize = 255;
3464
3465 /* Get the whole VPD page list */
3466 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3467 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3468 buf, bufsize);
3469 if (rc != 0)
3470 goto exit_unsupported;
3471
3472 pages = buf[3];
3473 for (i = 1; i <= pages; i++)
3474 if (buf[3 + i] == page)
3475 goto exit_supported;
3476exit_unsupported:
3477 kfree(buf);
3478 return 0;
3479exit_supported:
3480 kfree(buf);
3481 return 1;
3482}
3483
283b4a9b
SC		 3484static void hpsa_get_ioaccel_status(struct ctlr_info *h,
3485 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3486{
3487 int rc;
3488 unsigned char *buf;
3489 u8 ioaccel_status;
3490
3491 this_device->offload_config = 0;
3492 this_device->offload_enabled = 0;
41ce4c35 3493 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 3494
3495 buf = kzalloc(64, GFP_KERNEL);
3496 if (!buf)
3497 return;
1b70150a
SC		 3498 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
3499 goto out;
283b4a9b 3500 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 3501 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 3502 if (rc != 0)
3503 goto out;
3504
3505#define IOACCEL_STATUS_BYTE 4
3506#define OFFLOAD_CONFIGURED_BIT 0x01
3507#define OFFLOAD_ENABLED_BIT 0x02
3508 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
3509 this_device->offload_config =
3510 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3511 if (this_device->offload_config) {
3512 this_device->offload_enabled =
3513 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3514 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3515 this_device->offload_enabled = 0;
3516 }
41ce4c35 3517 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 3518out:
3519 kfree(buf);
3520 return;
3521}
3522
edd16368
SC		 3523/* Get the device id from inquiry page 0x83 */
3524static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
75d23d89 3525 unsigned char *device_id, int index, int buflen)
edd16368
SC		 3526{
3527 int rc;
3528 unsigned char *buf;
3529
3530 if (buflen > 16)
3531 buflen = 16;
3532 buf = kzalloc(64, GFP_KERNEL);
3533 if (!buf)
a84d794d 3534 return -ENOMEM;
b7bb24eb 3535 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368 3536 if (rc == 0)
75d23d89
DB		 3537 memcpy(device_id, &buf[index], buflen);
3538
edd16368 3539 kfree(buf);
75d23d89 3540
edd16368
SC		 3541 return rc != 0;
3542}
3543
3544static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 3545 void *buf, int bufsize,
edd16368
SC		 3546 int extended_response)
3547{
3548 int rc = IO_OK;
3549 struct CommandList *c;
3550 unsigned char scsi3addr[8];
3551 struct ErrorInfo *ei;
3552
45fcb86e 3553 c = cmd_alloc(h);
bf43caf3 3554
e89c0ae7
SC		 3555 /* address the controller */
3556 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 3557 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3558 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3559 rc = -1;
3560 goto out;
3561 }
edd16368
SC		 3562 if (extended_response)
3563 c->Request.CDB[1] = extended_response;
25163bd5 3564 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3565 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 3566 if (rc)
3567 goto out;
edd16368
SC		 3568 ei = c->err_info;
3569 if (ei->CommandStatus != 0 &&
3570 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3571 hpsa_scsi_interpret_error(h, c);
edd16368 3572 rc = -1;
283b4a9b 3573 } else {
03383736
DB		 3574 struct ReportLUNdata *rld = buf;
3575
3576 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 3577 dev_err(&h->pdev->dev,
3578 "report luns requested format %u, got %u\n",
3579 extended_response,
03383736 3580 rld->extended_response_flag);
283b4a9b
SC		 3581 rc = -1;
3582 }
edd16368 3583 }
a2dac136 3584out:
45fcb86e 3585 cmd_free(h, c);
edd16368
SC		 3586 return rc;
3587}
3588
3589static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 3590 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 3591{
03383736
DB		 3592 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3593 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 3594}
3595
3596static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3597 struct ReportLUNdata *buf, int bufsize)
3598{
3599 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3600}
3601
3602static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3603 int bus, int target, int lun)
3604{
3605 device->bus = bus;
3606 device->target = target;
3607 device->lun = lun;
3608}
3609
9846590e
SC		 3610/* Use VPD inquiry to get details of volume status */
3611static int hpsa_get_volume_status(struct ctlr_info *h,
3612 unsigned char scsi3addr[])
3613{
3614 int rc;
3615 int status;
3616 int size;
3617 unsigned char *buf;
3618
3619 buf = kzalloc(64, GFP_KERNEL);
3620 if (!buf)
3621 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3622
3623 /* Does controller have VPD for logical volume status? */
24a4b078 3624 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 3625 goto exit_failed;
9846590e
SC		 3626
3627 /* Get the size of the VPD return buffer */
3628 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3629 buf, HPSA_VPD_HEADER_SZ);
24a4b078 3630 if (rc != 0)
9846590e 3631 goto exit_failed;
9846590e
SC		 3632 size = buf[3];
3633
3634 /* Now get the whole VPD buffer */
3635 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3636 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 3637 if (rc != 0)
9846590e 3638 goto exit_failed;
9846590e
SC		 3639 status = buf[4]; /* status byte */
3640
3641 kfree(buf);
3642 return status;
3643exit_failed:
3644 kfree(buf);
3645 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3646}
3647
3648/* Determine offline status of a volume.
3649 * Return either:
3650 * 0 (not offline)
67955ba3 3651 * 0xff (offline for unknown reasons)
9846590e
SC		 3652 * # (integer code indicating one of several NOT READY states
3653 * describing why a volume is to be kept offline)
3654 */
67955ba3 3655static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 3656 unsigned char scsi3addr[])
3657{
3658 struct CommandList *c;
9437ac43
SC		 3659 unsigned char *sense;
3660 u8 sense_key, asc, ascq;
3661 int sense_len;
25163bd5 3662 int rc, ldstat = 0;
9846590e
SC		 3663 u16 cmd_status;
3664 u8 scsi_status;
3665#define ASC_LUN_NOT_READY 0x04
3666#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3667#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3668
3669 c = cmd_alloc(h);
bf43caf3 3670
9846590e 3671 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
c448ecfa
DB		 3672 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
3673 DEFAULT_TIMEOUT);
25163bd5
WS		 3674 if (rc) {
3675 cmd_free(h, c);
3676 return 0;
3677 }
9846590e 3678 sense = c->err_info->SenseInfo;
9437ac43
SC		 3679 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3680 sense_len = sizeof(c->err_info->SenseInfo);
3681 else
3682 sense_len = c->err_info->SenseLen;
3683 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 3684 cmd_status = c->err_info->CommandStatus;
3685 scsi_status = c->err_info->ScsiStatus;
3686 cmd_free(h, c);
3687 /* Is the volume 'not ready'? */
3688 if (cmd_status != CMD_TARGET_STATUS ||
3689 scsi_status != SAM_STAT_CHECK_CONDITION ||
3690 sense_key != NOT_READY ||
3691 asc != ASC_LUN_NOT_READY) {
3692 return 0;
3693 }
3694
3695 /* Determine the reason for not ready state */
3696 ldstat = hpsa_get_volume_status(h, scsi3addr);
3697
3698 /* Keep volume offline in certain cases: */
3699 switch (ldstat) {
3700 case HPSA_LV_UNDERGOING_ERASE:
5ca01204 3701 case HPSA_LV_NOT_AVAILABLE:
9846590e
SC		 3702 case HPSA_LV_UNDERGOING_RPI:
3703 case HPSA_LV_PENDING_RPI:
3704 case HPSA_LV_ENCRYPTED_NO_KEY:
3705 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3706 case HPSA_LV_UNDERGOING_ENCRYPTION:
3707 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3708 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3709 return ldstat;
3710 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3711 /* If VPD status page isn't available,
3712 * use ASC/ASCQ to determine state
3713 */
3714 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3715 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3716 return ldstat;
3717 break;
3718 default:
3719 break;
3720 }
3721 return 0;
3722}
3723
9b5c48c2
SC		 3724/*
3725 * Find out if a logical device supports aborts by simply trying one.
3726 * Smart Array may claim not to support aborts on logical drives, but
3727 * if a MSA2000 * is connected, the drives on that will be presented
3728 * by the Smart Array as logical drives, and aborts may be sent to
3729 * those devices successfully. So the simplest way to find out is
3730 * to simply try an abort and see how the device responds.
3731 */
3732static int hpsa_device_supports_aborts(struct ctlr_info *h,
3733 unsigned char *scsi3addr)
3734{
3735 struct CommandList *c;
3736 struct ErrorInfo *ei;
3737 int rc = 0;
3738
3739 u64 tag = (u64) -1; /* bogus tag */
3740
3741 /* Assume that physical devices support aborts */
3742 if (!is_logical_dev_addr_mode(scsi3addr))
3743 return 1;
3744
3745 c = cmd_alloc(h);
bf43caf3 3746
9b5c48c2 3747 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
c448ecfa
DB		 3748 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
3749 DEFAULT_TIMEOUT);
9b5c48c2
SC		 3750 /* no unmap needed here because no data xfer. */
3751 ei = c->err_info;
3752 switch (ei->CommandStatus) {
3753 case CMD_INVALID:
3754 rc = 0;
3755 break;
3756 case CMD_UNABORTABLE:
3757 case CMD_ABORT_FAILED:
3758 rc = 1;
3759 break;
9437ac43
SC		 3760 case CMD_TMF_STATUS:
3761 rc = hpsa_evaluate_tmf_status(h, c);
3762 break;
9b5c48c2
SC		 3763 default:
3764 rc = 0;
3765 break;
3766 }
3767 cmd_free(h, c);
3768 return rc;
3769}
3770
edd16368 3771static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3772 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3773 unsigned char *is_OBDR_device)
edd16368 3774{
0b0e1d6c
SC		 3775
3776#define OBDR_SIG_OFFSET 43
3777#define OBDR_TAPE_SIG "$DR-10"
3778#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3779#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3780
ea6d3bc3 3781 unsigned char *inq_buff;
0b0e1d6c 3782 unsigned char *obdr_sig;
683fc444 3783 int rc = 0;
edd16368 3784
ea6d3bc3 3785 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
683fc444
DB		 3786 if (!inq_buff) {
3787 rc = -ENOMEM;
edd16368 3788 goto bail_out;
683fc444 3789 }
edd16368 3790
edd16368
SC		 3791 /* Do an inquiry to the device to see what it is. */
3792 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3793 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3794 /* Inquiry failed (msg printed already) */
3795 dev_err(&h->pdev->dev,
3796 "hpsa_update_device_info: inquiry failed\n");
683fc444 3797 rc = -EIO;
edd16368
SC		 3798 goto bail_out;
3799 }
3800
4af61e4f
DB		 3801 scsi_sanitize_inquiry_string(&inq_buff[8], 8);
3802 scsi_sanitize_inquiry_string(&inq_buff[16], 16);
75d23d89 3803
edd16368
SC		 3804 this_device->devtype = (inq_buff[0] & 0x1f);
3805 memcpy(this_device->scsi3addr, scsi3addr, 8);
3806 memcpy(this_device->vendor, &inq_buff[8],
3807 sizeof(this_device->vendor));
3808 memcpy(this_device->model, &inq_buff[16],
3809 sizeof(this_device->model));
edd16368
SC		 3810 memset(this_device->device_id, 0,
3811 sizeof(this_device->device_id));
75d23d89 3812 hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8,
edd16368
SC		 3813 sizeof(this_device->device_id));
3814
af15ed36
DB		 3815 if ((this_device->devtype == TYPE_DISK ||
3816 this_device->devtype == TYPE_ZBC) &&
283b4a9b 3817 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3818 int volume_offline;
3819
edd16368 3820 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3821 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3822 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3823 volume_offline = hpsa_volume_offline(h, scsi3addr);
3824 if (volume_offline < 0 || volume_offline > 0xff)
3825 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3826 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3827 } else {
edd16368 3828 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3829 this_device->offload_config = 0;
3830 this_device->offload_enabled = 0;
41ce4c35 3831 this_device->offload_to_be_enabled = 0;
a3144e0b 3832 this_device->hba_ioaccel_enabled = 0;
9846590e 3833 this_device->volume_offline = 0;
03383736 3834 this_device->queue_depth = h->nr_cmds;
283b4a9b 3835 }
edd16368 3836
0b0e1d6c
SC		 3837 if (is_OBDR_device) {
3838 /* See if this is a One-Button-Disaster-Recovery device
3839 * by looking for "$DR-10" at offset 43 in inquiry data.
3840 */
3841 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3842 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3843 strncmp(obdr_sig, OBDR_TAPE_SIG,
3844 OBDR_SIG_LEN) == 0);
3845 }
edd16368
SC		 3846 kfree(inq_buff);
3847 return 0;
3848
3849bail_out:
3850 kfree(inq_buff);
683fc444 3851 return rc;
edd16368
SC		 3852}
3853
9b5c48c2
SC		 3854static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3855 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3856{
3857 unsigned long flags;
3858 int rc, entry;
3859 /*
3860 * See if this device supports aborts. If we already know
3861 * the device, we already know if it supports aborts, otherwise
3862 * we have to find out if it supports aborts by trying one.
3863 */
3864 spin_lock_irqsave(&h->devlock, flags);
3865 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3866 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3867 entry >= 0 && entry < h->ndevices) {
3868 dev->supports_aborts = h->dev[entry]->supports_aborts;
3869 spin_unlock_irqrestore(&h->devlock, flags);
3870 } else {
3871 spin_unlock_irqrestore(&h->devlock, flags);
3872 dev->supports_aborts =
3873 hpsa_device_supports_aborts(h, scsi3addr);
3874 if (dev->supports_aborts < 0)
3875 dev->supports_aborts = 0;
3876 }
3877}
3878
c795505a
KB		 3879/*
3880 * Helper function to assign bus, target, lun mapping of devices.
edd16368
SC		 3881 * Logical drive target and lun are assigned at this time, but
3882 * physical device lun and target assignment are deferred (assigned
3883 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
c795505a 3884*/
edd16368 3885static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3886 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3887{
c795505a 3888 u32 lunid = get_unaligned_le32(lunaddrbytes);
1f310bde
SC		 3889
3890 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3891 /* physical device, target and lun filled in later */
edd16368 3892 if (is_hba_lunid(lunaddrbytes))
c795505a
KB		 3893 hpsa_set_bus_target_lun(device,
3894 HPSA_HBA_BUS, 0, lunid & 0x3fff);
edd16368 3895 else
1f310bde 3896 /* defer target, lun assignment for physical devices */
c795505a
KB		 3897 hpsa_set_bus_target_lun(device,
3898 HPSA_PHYSICAL_DEVICE_BUS, -1, -1);
1f310bde
SC		 3899 return;
3900 }
3901 /* It's a logical device */
66749d0d 3902 if (device->external) {
1f310bde 3903 hpsa_set_bus_target_lun(device,
c795505a
KB		 3904 HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff,
3905 lunid & 0x00ff);
1f310bde 3906 return;
edd16368 3907 }
c795505a
KB		 3908 hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS,
3909 0, lunid & 0x3fff);
edd16368
SC		 3910}
3911
edd16368 3912
54b6e9e9
ST		 3913/*
3914 * Get address of physical disk used for an ioaccel2 mode command:
3915 * 1. Extract ioaccel2 handle from the command.
3916 * 2. Find a matching ioaccel2 handle from list of physical disks.
3917 * 3. Return:
3918 * 1 and set scsi3addr to address of matching physical
3919 * 0 if no matching physical disk was found.
3920 */
3921static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3922 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3923{
41ce4c35
SC		 3924 struct io_accel2_cmd *c2 =
3925 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3926 unsigned long flags;
54b6e9e9 3927 int i;
54b6e9e9 3928
41ce4c35
SC		 3929 spin_lock_irqsave(&h->devlock, flags);
3930 for (i = 0; i < h->ndevices; i++)
3931 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3932 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3933 sizeof(h->dev[i]->scsi3addr));
3934 spin_unlock_irqrestore(&h->devlock, flags);
3935 return 1;
3936 }
3937 spin_unlock_irqrestore(&h->devlock, flags);
3938 return 0;
54b6e9e9 3939}
41ce4c35 3940
66749d0d
ST		 3941static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position,
3942 int i, int nphysicals, int nlocal_logicals)
3943{
3944 /* In report logicals, local logicals are listed first,
3945 * then any externals.
3946 */
3947 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3948
3949 if (i == raid_ctlr_position)
3950 return 0;
3951
3952 if (i < logicals_start)
3953 return 0;
3954
3955 /* i is in logicals range, but still within local logicals */
3956 if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals)
3957 return 0;
3958
3959 return 1; /* it's an external lun */
3960}
3961
edd16368
SC		 3962/*
3963 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3964 * logdev. The number of luns in physdev and logdev are returned in
3965 * *nphysicals and *nlogicals, respectively.
3966 * Returns 0 on success, -1 otherwise.
3967 */
3968static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3969 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3970 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3971{
03383736 3972 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3973 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3974 return -1;
3975 }
03383736 3976 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3977 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3978 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3979 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3980 *nphysicals = HPSA_MAX_PHYS_LUN;
3981 }
03383736 3982 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3983 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3984 return -1;
3985 }
6df1e954 3986 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3987 /* Reject Logicals in excess of our max capability. */
3988 if (*nlogicals > HPSA_MAX_LUN) {
3989 dev_warn(&h->pdev->dev,
3990 "maximum logical LUNs (%d) exceeded. "
3991 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3992 *nlogicals - HPSA_MAX_LUN);
3993 *nlogicals = HPSA_MAX_LUN;
3994 }
3995 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3996 dev_warn(&h->pdev->dev,
3997 "maximum logical + physical LUNs (%d) exceeded. "
3998 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3999 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
4000 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
4001 }
4002 return 0;
4003}
4004
42a91641
DB		 4005static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
4006 int i, int nphysicals, int nlogicals,
a93aa1fe 4007 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 4008 struct ReportLUNdata *logdev_list)
4009{
4010 /* Helper function, figure out where the LUN ID info is coming from
4011 * given index i, lists of physical and logical devices, where in
4012 * the list the raid controller is supposed to appear (first or last)
4013 */
4014
4015 int logicals_start = nphysicals + (raid_ctlr_position == 0);
4016 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
4017
4018 if (i == raid_ctlr_position)
4019 return RAID_CTLR_LUNID;
4020
4021 if (i < logicals_start)
d5b5d964
SC		 4022 return &physdev_list->LUN[i -
4023 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 4024
4025 if (i < last_device)
4026 return &logdev_list->LUN[i - nphysicals -
4027 (raid_ctlr_position == 0)][0];
4028 BUG();
4029 return NULL;
4030}
4031
03383736
DB		 4032/* get physical drive ioaccel handle and queue depth */
4033static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
4034 struct hpsa_scsi_dev_t *dev,
f2039b03 4035 struct ReportExtendedLUNdata *rlep, int rle_index,
03383736
DB		 4036 struct bmic_identify_physical_device *id_phys)
4037{
4038 int rc;
f2039b03 4039 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
03383736
DB		 4040
4041 dev->ioaccel_handle = rle->ioaccel_handle;
f2039b03 4042 if ((rle->device_flags & 0x08) && dev->ioaccel_handle)
a3144e0b 4043 dev->hba_ioaccel_enabled = 1;
03383736 4044 memset(id_phys, 0, sizeof(*id_phys));
f2039b03
DB		 4045 rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0],
4046 GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys,
03383736
DB		 4047 sizeof(*id_phys));
4048 if (!rc)
4049 /* Reserve space for FW operations */
4050#define DRIVE_CMDS_RESERVED_FOR_FW 2
4051#define DRIVE_QUEUE_DEPTH 7
4052 dev->queue_depth =
4053 le16_to_cpu(id_phys->current_queue_depth_limit) -
4054 DRIVE_CMDS_RESERVED_FOR_FW;
4055 else
4056 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
03383736
DB		 4057}
4058
8270b862 4059static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
f2039b03 4060 struct ReportExtendedLUNdata *rlep, int rle_index,
8270b862
JH		 4061 struct bmic_identify_physical_device *id_phys)
4062{
f2039b03
DB		 4063 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
4064
4065 if ((rle->device_flags & 0x08) && this_device->ioaccel_handle)
8270b862
JH		 4066 this_device->hba_ioaccel_enabled = 1;
4067
4068 memcpy(&this_device->active_path_index,
4069 &id_phys->active_path_number,
4070 sizeof(this_device->active_path_index));
4071 memcpy(&this_device->path_map,
4072 &id_phys->redundant_path_present_map,
4073 sizeof(this_device->path_map));
4074 memcpy(&this_device->box,
4075 &id_phys->alternate_paths_phys_box_on_port,
4076 sizeof(this_device->box));
4077 memcpy(&this_device->phys_connector,
4078 &id_phys->alternate_paths_phys_connector,
4079 sizeof(this_device->phys_connector));
4080 memcpy(&this_device->bay,
4081 &id_phys->phys_bay_in_box,
4082 sizeof(this_device->bay));
4083}
4084
66749d0d
ST		 4085/* get number of local logical disks. */
4086static int hpsa_set_local_logical_count(struct ctlr_info *h,
4087 struct bmic_identify_controller *id_ctlr,
4088 u32 *nlocals)
4089{
4090 int rc;
4091
4092 if (!id_ctlr) {
4093 dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n",
4094 __func__);
4095 return -ENOMEM;
4096 }
4097 memset(id_ctlr, 0, sizeof(*id_ctlr));
4098 rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr));
4099 if (!rc)
4100 if (id_ctlr->configured_logical_drive_count < 256)
4101 *nlocals = id_ctlr->configured_logical_drive_count;
4102 else
4103 *nlocals = le16_to_cpu(
4104 id_ctlr->extended_logical_unit_count);
4105 else
4106 *nlocals = -1;
4107 return rc;
4108}
4109
4110
8aa60681 4111static void hpsa_update_scsi_devices(struct ctlr_info *h)
edd16368
SC		 4112{
4113 /* the idea here is we could get notified
4114 * that some devices have changed, so we do a report
4115 * physical luns and report logical luns cmd, and adjust
4116 * our list of devices accordingly.
4117 *
4118 * The scsi3addr's of devices won't change so long as the
4119 * adapter is not reset. That means we can rescan and
4120 * tell which devices we already know about, vs. new
4121 * devices, vs. disappearing devices.
4122 */
a93aa1fe 4123 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 4124 struct ReportLUNdata *logdev_list = NULL;
03383736 4125 struct bmic_identify_physical_device *id_phys = NULL;
66749d0d 4126 struct bmic_identify_controller *id_ctlr = NULL;
01a02ffc
SC		 4127 u32 nphysicals = 0;
4128 u32 nlogicals = 0;
66749d0d 4129 u32 nlocal_logicals = 0;
01a02ffc 4130 u32 ndev_allocated = 0;
edd16368
SC		 4131 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
4132 int ncurrent = 0;
4f4eb9f1 4133 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 4134 int raid_ctlr_position;
04fa2f44 4135 bool physical_device;
aca4a520 4136 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 4137
cfe5badc 4138 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 4139 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
4140 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 4141 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 4142 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
66749d0d 4143 id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL);
edd16368 4144
03383736 4145 if (!currentsd || !physdev_list || !logdev_list ||
66749d0d 4146 !tmpdevice || !id_phys || !id_ctlr) {
edd16368
SC		 4147 dev_err(&h->pdev->dev, "out of memory\n");
4148 goto out;
4149 }
4150 memset(lunzerobits, 0, sizeof(lunzerobits));
4151
853633e8
DB		 4152 h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */
4153
03383736 4154 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
853633e8
DB		 4155 logdev_list, &nlogicals)) {
4156 h->drv_req_rescan = 1;
edd16368 4157 goto out;
853633e8 4158 }
edd16368 4159
66749d0d
ST		 4160 /* Set number of local logicals (non PTRAID) */
4161 if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) {
4162 dev_warn(&h->pdev->dev,
4163 "%s: Can't determine number of local logical devices.\n",
4164 __func__);
4165 }
edd16368 4166
aca4a520
ST		 4167 /* We might see up to the maximum number of logical and physical disks
4168 * plus external target devices, and a device for the local RAID
4169 * controller.
edd16368 4170 */
aca4a520 4171 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 4172
4173 /* Allocate the per device structures */
4174 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 4175 if (i >= HPSA_MAX_DEVICES) {
4176 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
4177 " %d devices ignored.\n", HPSA_MAX_DEVICES,
4178 ndevs_to_allocate - HPSA_MAX_DEVICES);
4179 break;
4180 }
4181
edd16368
SC		 4182 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
4183 if (!currentsd[i]) {
4184 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
4185 __FILE__, __LINE__);
853633e8 4186 h->drv_req_rescan = 1;
edd16368
SC		 4187 goto out;
4188 }
4189 ndev_allocated++;
4190 }
4191
8645291b 4192 if (is_scsi_rev_5(h))
339b2b14
SC		 4193 raid_ctlr_position = 0;
4194 else
4195 raid_ctlr_position = nphysicals + nlogicals;
4196
edd16368 4197 /* adjust our table of devices */
4f4eb9f1 4198 n_ext_target_devs = 0;
edd16368 4199 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 4200 u8 *lunaddrbytes, is_OBDR = 0;
683fc444 4201 int rc = 0;
f2039b03 4202 int phys_dev_index = i - (raid_ctlr_position == 0);
edd16368 4203
04fa2f44 4204 physical_device = i < nphysicals + (raid_ctlr_position == 0);
edd16368
SC		 4205
4206 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 4207 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
4208 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 4209
4210 /* skip masked non-disk devices */
04fa2f44 4211 if (MASKED_DEVICE(lunaddrbytes) && physical_device &&
cca8f13b
DB		 4212 (physdev_list->LUN[phys_dev_index].device_type != 0x06) &&
4213 (physdev_list->LUN[phys_dev_index].device_flags & 0x01))
04fa2f44 4214 continue;
edd16368
SC		 4215
4216 /* Get device type, vendor, model, device id */
683fc444
DB		 4217 rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
4218 &is_OBDR);
4219 if (rc == -ENOMEM) {
4220 dev_warn(&h->pdev->dev,
4221 "Out of memory, rescan deferred.\n");
853633e8 4222 h->drv_req_rescan = 1;
683fc444 4223 goto out;
853633e8 4224 }
683fc444
DB		 4225 if (rc) {
4226 dev_warn(&h->pdev->dev,
4227 "Inquiry failed, skipping device.\n");
4228 continue;
4229 }
4230
66749d0d
ST		 4231 /* Determine if this is a lun from an external target array */
4232 tmpdevice->external =
4233 figure_external_status(h, raid_ctlr_position, i,
4234 nphysicals, nlocal_logicals);
4235
1f310bde 4236 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 4237 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 4238 this_device = currentsd[ncurrent];
4239
34592254
ST		 4240 /* Turn on discovery_polling if there are ext target devices.
4241 * Event-based change notification is unreliable for those.
edd16368 4242 */
34592254
ST		 4243 if (!h->discovery_polling) {
4244 if (tmpdevice->external) {
4245 h->discovery_polling = 1;
4246 dev_info(&h->pdev->dev,
4247 "External target, activate discovery polling.\n");
4248 }
edd16368
SC		 4249 }
4250
34592254 4251
edd16368 4252 *this_device = *tmpdevice;
04fa2f44 4253 this_device->physical_device = physical_device;
edd16368 4254
04fa2f44
KB		 4255 /*
4256 * Expose all devices except for physical devices that
4257 * are masked.
4258 */
4259 if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device)
2a168208
KB		 4260 this_device->expose_device = 0;
4261 else
4262 this_device->expose_device = 1;
41ce4c35 4263
d04e62b9
KB		 4264
4265 /*
4266 * Get the SAS address for physical devices that are exposed.
4267 */
4268 if (this_device->physical_device && this_device->expose_device)
4269 hpsa_get_sas_address(h, lunaddrbytes, this_device);
41ce4c35 4270
edd16368 4271 switch (this_device->devtype) {
0b0e1d6c 4272 case TYPE_ROM:
edd16368
SC		 4273 /* We don't *really* support actual CD-ROM devices,
4274 * just "One Button Disaster Recovery" tape drive
4275 * which temporarily pretends to be a CD-ROM drive.
4276 * So we check that the device is really an OBDR tape
4277 * device by checking for "$DR-10" in bytes 43-48 of
4278 * the inquiry data.
4279 */
0b0e1d6c
SC		 4280 if (is_OBDR)
4281 ncurrent++;
edd16368
SC		 4282 break;
4283 case TYPE_DISK:
af15ed36 4284 case TYPE_ZBC:
04fa2f44 4285 if (this_device->physical_device) {
b9092b79
KB		 4286 /* The disk is in HBA mode. */
4287 /* Never use RAID mapper in HBA mode. */
ecf418d1 4288 this_device->offload_enabled = 0;
b9092b79 4289 hpsa_get_ioaccel_drive_info(h, this_device,
f2039b03
DB		 4290 physdev_list, phys_dev_index, id_phys);
4291 hpsa_get_path_info(this_device,
4292 physdev_list, phys_dev_index, id_phys);
b9092b79 4293 }
ecf418d1 4294 ncurrent++;
edd16368
SC		 4295 break;
4296 case TYPE_TAPE:
4297 case TYPE_MEDIUM_CHANGER:
cca8f13b
DB		 4298 ncurrent++;
4299 break;
41ce4c35 4300 case TYPE_ENCLOSURE:
17a9e54a
DB		 4301 if (!this_device->external)
4302 hpsa_get_enclosure_info(h, lunaddrbytes,
cca8f13b
DB		 4303 physdev_list, phys_dev_index,
4304 this_device);
b9092b79 4305 ncurrent++;
41ce4c35 4306 break;
edd16368
SC		 4307 case TYPE_RAID:
4308 /* Only present the Smartarray HBA as a RAID controller.
4309 * If it's a RAID controller other than the HBA itself
4310 * (an external RAID controller, MSA500 or similar)
4311 * don't present it.
4312 */
4313 if (!is_hba_lunid(lunaddrbytes))
4314 break;
4315 ncurrent++;
4316 break;
4317 default:
4318 break;
4319 }
cfe5badc 4320 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 4321 break;
4322 }
d04e62b9
KB		 4323
4324 if (h->sas_host == NULL) {
4325 int rc = 0;
4326
4327 rc = hpsa_add_sas_host(h);
4328 if (rc) {
4329 dev_warn(&h->pdev->dev,
4330 "Could not add sas host %d\n", rc);
4331 goto out;
4332 }
4333 }
4334
8aa60681 4335 adjust_hpsa_scsi_table(h, currentsd, ncurrent);
edd16368
SC		 4336out:
4337 kfree(tmpdevice);
4338 for (i = 0; i < ndev_allocated; i++)
4339 kfree(currentsd[i]);
4340 kfree(currentsd);
edd16368
SC		 4341 kfree(physdev_list);
4342 kfree(logdev_list);
66749d0d 4343 kfree(id_ctlr);
03383736 4344 kfree(id_phys);
edd16368
SC		 4345}
4346
ec5cbf04
WS		 4347static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
4348 struct scatterlist *sg)
4349{
4350 u64 addr64 = (u64) sg_dma_address(sg);
4351 unsigned int len = sg_dma_len(sg);
4352
4353 desc->Addr = cpu_to_le64(addr64);
4354 desc->Len = cpu_to_le32(len);
4355 desc->Ext = 0;
4356}
4357
c7ee65b3
WS		 4358/*
4359 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 4360 * dma mapping and fills in the scatter gather entries of the
4361 * hpsa command, cp.
4362 */
33a2ffce 4363static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 4364 struct CommandList *cp,
4365 struct scsi_cmnd *cmd)
4366{
edd16368 4367 struct scatterlist *sg;
b3a7ba7c 4368 int use_sg, i, sg_limit, chained, last_sg;
33a2ffce 4369 struct SGDescriptor *curr_sg;
edd16368 4370
33a2ffce 4371 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 4372
4373 use_sg = scsi_dma_map(cmd);
4374 if (use_sg < 0)
4375 return use_sg;
4376
4377 if (!use_sg)
4378 goto sglist_finished;
4379
b3a7ba7c
WS		 4380 /*
4381 * If the number of entries is greater than the max for a single list,
4382 * then we have a chained list; we will set up all but one entry in the
4383 * first list (the last entry is saved for link information);
4384 * otherwise, we don't have a chained list and we'll set up at each of
4385 * the entries in the one list.
4386 */
33a2ffce 4387 curr_sg = cp->SG;
b3a7ba7c
WS		 4388 chained = use_sg > h->max_cmd_sg_entries;
4389 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
4390 last_sg = scsi_sg_count(cmd) - 1;
4391 scsi_for_each_sg(cmd, sg, sg_limit, i) {
ec5cbf04 4392 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 4393 curr_sg++;
4394 }
ec5cbf04 4395
b3a7ba7c
WS		 4396 if (chained) {
4397 /*
4398 * Continue with the chained list. Set curr_sg to the chained
4399 * list. Modify the limit to the total count less the entries
4400 * we've already set up. Resume the scan at the list entry
4401 * where the previous loop left off.
4402 */
4403 curr_sg = h->cmd_sg_list[cp->cmdindex];
4404 sg_limit = use_sg - sg_limit;
4405 for_each_sg(sg, sg, sg_limit, i) {
4406 hpsa_set_sg_descriptor(curr_sg, sg);
4407 curr_sg++;
4408 }
4409 }
4410
ec5cbf04 4411 /* Back the pointer up to the last entry and mark it as "last". */
b3a7ba7c 4412 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 4413
4414 if (use_sg + chained > h->maxSG)
4415 h->maxSG = use_sg + chained;
4416
4417 if (chained) {
4418 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 4419 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 4420 if (hpsa_map_sg_chain_block(h, cp)) {
4421 scsi_dma_unmap(cmd);
4422 return -1;
4423 }
33a2ffce 4424 return 0;
edd16368
SC		 4425 }
4426
4427sglist_finished:
4428
01a02ffc 4429 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 4430 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 4431 return 0;
4432}
4433
283b4a9b
SC		 4434#define IO_ACCEL_INELIGIBLE (1)
4435static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
4436{
4437 int is_write = 0;
4438 u32 block;
4439 u32 block_cnt;
4440
4441 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
4442 switch (cdb[0]) {
4443 case WRITE_6:
4444 case WRITE_12:
4445 is_write = 1;
4446 case READ_6:
4447 case READ_12:
4448 if (*cdb_len == 6) {
c8a6c9a6 4449 block = get_unaligned_be16(&cdb[2]);
283b4a9b 4450 block_cnt = cdb[4];
c8a6c9a6
DB		 4451 if (block_cnt == 0)
4452 block_cnt = 256;
283b4a9b
SC		 4453 } else {
4454 BUG_ON(*cdb_len != 12);
c8a6c9a6
DB		 4455 block = get_unaligned_be32(&cdb[2]);
4456 block_cnt = get_unaligned_be32(&cdb[6]);
283b4a9b
SC		 4457 }
4458 if (block_cnt > 0xffff)
4459 return IO_ACCEL_INELIGIBLE;
4460
4461 cdb[0] = is_write ? WRITE_10 : READ_10;
4462 cdb[1] = 0;
4463 cdb[2] = (u8) (block >> 24);
4464 cdb[3] = (u8) (block >> 16);
4465 cdb[4] = (u8) (block >> 8);
4466 cdb[5] = (u8) (block);
4467 cdb[6] = 0;
4468 cdb[7] = (u8) (block_cnt >> 8);
4469 cdb[8] = (u8) (block_cnt);
4470 cdb[9] = 0;
4471 *cdb_len = 10;
4472 break;
4473 }
4474 return 0;
4475}
4476
c349775e 4477static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 4478 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4479 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 4480{
4481 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 4482 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
4483 unsigned int len;
4484 unsigned int total_len = 0;
4485 struct scatterlist *sg;
4486 u64 addr64;
4487 int use_sg, i;
4488 struct SGDescriptor *curr_sg;
4489 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
4490
283b4a9b 4491 /* TODO: implement chaining support */
03383736
DB		 4492 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
4493 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4494 return IO_ACCEL_INELIGIBLE;
03383736 4495 }
283b4a9b 4496
e1f7de0c
MG		 4497 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
4498
03383736
DB		 4499 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4500 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4501 return IO_ACCEL_INELIGIBLE;
03383736 4502 }
283b4a9b 4503
e1f7de0c
MG		 4504 c->cmd_type = CMD_IOACCEL1;
4505
4506 /* Adjust the DMA address to point to the accelerated command buffer */
4507 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
4508 (c->cmdindex * sizeof(*cp));
4509 BUG_ON(c->busaddr & 0x0000007F);
4510
4511 use_sg = scsi_dma_map(cmd);
03383736
DB		 4512 if (use_sg < 0) {
4513 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 4514 return use_sg;
03383736 4515 }
e1f7de0c
MG		 4516
4517 if (use_sg) {
4518 curr_sg = cp->SG;
4519 scsi_for_each_sg(cmd, sg, use_sg, i) {
4520 addr64 = (u64) sg_dma_address(sg);
4521 len = sg_dma_len(sg);
4522 total_len += len;
50a0decf
SC		 4523 curr_sg->Addr = cpu_to_le64(addr64);
4524 curr_sg->Len = cpu_to_le32(len);
4525 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 4526 curr_sg++;
4527 }
50a0decf 4528 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 4529
4530 switch (cmd->sc_data_direction) {
4531 case DMA_TO_DEVICE:
4532 control |= IOACCEL1_CONTROL_DATA_OUT;
4533 break;
4534 case DMA_FROM_DEVICE:
4535 control |= IOACCEL1_CONTROL_DATA_IN;
4536 break;
4537 case DMA_NONE:
4538 control |= IOACCEL1_CONTROL_NODATAXFER;
4539 break;
4540 default:
4541 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4542 cmd->sc_data_direction);
4543 BUG();
4544 break;
4545 }
4546 } else {
4547 control |= IOACCEL1_CONTROL_NODATAXFER;
4548 }
4549
c349775e 4550 c->Header.SGList = use_sg;
e1f7de0c 4551 /* Fill out the command structure to submit */
2b08b3e9
DB		 4552 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4553 cp->transfer_len = cpu_to_le32(total_len);
4554 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4555 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4556 cp->control = cpu_to_le32(control);
283b4a9b
SC		 4557 memcpy(cp->CDB, cdb, cdb_len);
4558 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 4559 /* Tag was already set at init time. */
283b4a9b 4560 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 4561 return 0;
4562}
edd16368 4563
283b4a9b
SC		 4564/*
4565 * Queue a command directly to a device behind the controller using the
4566 * I/O accelerator path.
4567 */
4568static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4569 struct CommandList *c)
4570{
4571 struct scsi_cmnd *cmd = c->scsi_cmd;
4572 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4573
03383736
DB		 4574 c->phys_disk = dev;
4575
283b4a9b 4576 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 4577 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 4578}
4579
dd0e19f3
ST		 4580/*
4581 * Set encryption parameters for the ioaccel2 request
4582 */
4583static void set_encrypt_ioaccel2(struct ctlr_info *h,
4584 struct CommandList *c, struct io_accel2_cmd *cp)
4585{
4586 struct scsi_cmnd *cmd = c->scsi_cmd;
4587 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4588 struct raid_map_data *map = &dev->raid_map;
4589 u64 first_block;
4590
dd0e19f3 4591 /* Are we doing encryption on this device */
2b08b3e9 4592 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 4593 return;
4594 /* Set the data encryption key index. */
4595 cp->dekindex = map->dekindex;
4596
4597 /* Set the encryption enable flag, encoded into direction field. */
4598 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4599
4600 /* Set encryption tweak values based on logical block address
4601 * If block size is 512, tweak value is LBA.
4602 * For other block sizes, tweak is (LBA * block size)/ 512)
4603 */
4604 switch (cmd->cmnd[0]) {
4605 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
4606 case WRITE_6:
4607 case READ_6:
2b08b3e9 4608 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 4609 break;
4610 case WRITE_10:
4611 case READ_10:
dd0e19f3
ST		 4612 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4613 case WRITE_12:
4614 case READ_12:
2b08b3e9 4615 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 4616 break;
4617 case WRITE_16:
4618 case READ_16:
2b08b3e9 4619 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 4620 break;
4621 default:
4622 dev_err(&h->pdev->dev,
2b08b3e9
DB		 4623 "ERROR: %s: size (0x%x) not supported for encryption\n",
4624 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 4625 BUG();
4626 break;
4627 }
2b08b3e9
DB		 4628
4629 if (le32_to_cpu(map->volume_blk_size) != 512)
4630 first_block = first_block *
4631 le32_to_cpu(map->volume_blk_size)/512;
4632
4633 cp->tweak_lower = cpu_to_le32(first_block);
4634 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 4635}
4636
c349775e
ST		 4637static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4638 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4639 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 4640{
4641 struct scsi_cmnd *cmd = c->scsi_cmd;
4642 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4643 struct ioaccel2_sg_element *curr_sg;
4644 int use_sg, i;
4645 struct scatterlist *sg;
4646 u64 addr64;
4647 u32 len;
4648 u32 total_len = 0;
4649
d9a729f3 4650 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 4651
03383736
DB		 4652 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4653 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4654 return IO_ACCEL_INELIGIBLE;
03383736
DB		 4655 }
4656
c349775e
ST		 4657 c->cmd_type = CMD_IOACCEL2;
4658 /* Adjust the DMA address to point to the accelerated command buffer */
4659 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4660 (c->cmdindex * sizeof(*cp));
4661 BUG_ON(c->busaddr & 0x0000007F);
4662
4663 memset(cp, 0, sizeof(*cp));
4664 cp->IU_type = IOACCEL2_IU_TYPE;
4665
4666 use_sg = scsi_dma_map(cmd);
03383736
DB		 4667 if (use_sg < 0) {
4668 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4669 return use_sg;
03383736 4670 }
c349775e
ST		 4671
4672 if (use_sg) {
c349775e 4673 curr_sg = cp->sg;
d9a729f3
WS		 4674 if (use_sg > h->ioaccel_maxsg) {
4675 addr64 = le64_to_cpu(
4676 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4677 curr_sg->address = cpu_to_le64(addr64);
4678 curr_sg->length = 0;
4679 curr_sg->reserved[0] = 0;
4680 curr_sg->reserved[1] = 0;
4681 curr_sg->reserved[2] = 0;
4682 curr_sg->chain_indicator = 0x80;
4683
4684 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4685 }
c349775e
ST		 4686 scsi_for_each_sg(cmd, sg, use_sg, i) {
4687 addr64 = (u64) sg_dma_address(sg);
4688 len = sg_dma_len(sg);
4689 total_len += len;
4690 curr_sg->address = cpu_to_le64(addr64);
4691 curr_sg->length = cpu_to_le32(len);
4692 curr_sg->reserved[0] = 0;
4693 curr_sg->reserved[1] = 0;
4694 curr_sg->reserved[2] = 0;
4695 curr_sg->chain_indicator = 0;
4696 curr_sg++;
4697 }
4698
4699 switch (cmd->sc_data_direction) {
4700 case DMA_TO_DEVICE:
dd0e19f3
ST		 4701 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4702 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 4703 break;
4704 case DMA_FROM_DEVICE:
dd0e19f3
ST		 4705 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4706 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 4707 break;
4708 case DMA_NONE:
dd0e19f3
ST		 4709 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4710 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 4711 break;
4712 default:
4713 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4714 cmd->sc_data_direction);
4715 BUG();
4716 break;
4717 }
4718 } else {
dd0e19f3
ST		 4719 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4720 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 4721 }
dd0e19f3
ST		 4722
4723 /* Set encryption parameters, if necessary */
4724 set_encrypt_ioaccel2(h, c, cp);
4725
2b08b3e9 4726 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 4727 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 4728 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 4729
c349775e
ST		 4730 cp->data_len = cpu_to_le32(total_len);
4731 cp->err_ptr = cpu_to_le64(c->busaddr +
4732 offsetof(struct io_accel2_cmd, error_data));
50a0decf 4733 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 4734
d9a729f3
WS		 4735 /* fill in sg elements */
4736 if (use_sg > h->ioaccel_maxsg) {
4737 cp->sg_count = 1;
a736e9b6 4738 cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0]));
d9a729f3
WS		 4739 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4740 atomic_dec(&phys_disk->ioaccel_cmds_out);
4741 scsi_dma_unmap(cmd);
4742 return -1;
4743 }
4744 } else
4745 cp->sg_count = (u8) use_sg;
4746
c349775e
ST		 4747 enqueue_cmd_and_start_io(h, c);
4748 return 0;
4749}
4750
4751/*
4752 * Queue a command to the correct I/O accelerator path.
4753 */
4754static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4755 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4756 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 4757{
03383736
DB		 4758 /* Try to honor the device's queue depth */
4759 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4760 phys_disk->queue_depth) {
4761 atomic_dec(&phys_disk->ioaccel_cmds_out);
4762 return IO_ACCEL_INELIGIBLE;
4763 }
c349775e
ST		 4764 if (h->transMethod & CFGTBL_Trans_io_accel1)
4765 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4766 cdb, cdb_len, scsi3addr,
4767 phys_disk);
c349775e
ST		 4768 else
4769 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4770 cdb, cdb_len, scsi3addr,
4771 phys_disk);
c349775e
ST		 4772}
4773
6b80b18f
ST		 4774static void raid_map_helper(struct raid_map_data *map,
4775 int offload_to_mirror, u32 *map_index, u32 *current_group)
4776{
4777 if (offload_to_mirror == 0) {
4778 /* use physical disk in the first mirrored group. */
2b08b3e9 4779 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4780 return;
4781 }
4782 do {
4783 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4784 *current_group = *map_index /
4785 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4786 if (offload_to_mirror == *current_group)
4787 continue;
2b08b3e9 4788 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4789 /* select map index from next group */
2b08b3e9 4790 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4791 (*current_group)++;
4792 } else {
4793 /* select map index from first group */
2b08b3e9 4794 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4795 *current_group = 0;
4796 }
4797 } while (offload_to_mirror != *current_group);
4798}
4799
283b4a9b
SC		 4800/*
4801 * Attempt to perform offload RAID mapping for a logical volume I/O.
4802 */
4803static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4804 struct CommandList *c)
4805{
4806 struct scsi_cmnd *cmd = c->scsi_cmd;
4807 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4808 struct raid_map_data *map = &dev->raid_map;
4809 struct raid_map_disk_data *dd = &map->data[0];
4810 int is_write = 0;
4811 u32 map_index;
4812 u64 first_block, last_block;
4813 u32 block_cnt;
4814 u32 blocks_per_row;
4815 u64 first_row, last_row;
4816 u32 first_row_offset, last_row_offset;
4817 u32 first_column, last_column;
6b80b18f
ST		 4818 u64 r0_first_row, r0_last_row;
4819 u32 r5or6_blocks_per_row;
4820 u64 r5or6_first_row, r5or6_last_row;
4821 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4822 u32 r5or6_first_column, r5or6_last_column;
4823 u32 total_disks_per_row;
4824 u32 stripesize;
4825 u32 first_group, last_group, current_group;
283b4a9b
SC		 4826 u32 map_row;
4827 u32 disk_handle;
4828 u64 disk_block;
4829 u32 disk_block_cnt;
4830 u8 cdb[16];
4831 u8 cdb_len;
2b08b3e9 4832 u16 strip_size;
283b4a9b
SC		 4833#if BITS_PER_LONG == 32
4834 u64 tmpdiv;
4835#endif
6b80b18f 4836 int offload_to_mirror;
283b4a9b 4837
283b4a9b
SC		 4838 /* check for valid opcode, get LBA and block count */
4839 switch (cmd->cmnd[0]) {
4840 case WRITE_6:
4841 is_write = 1;
4842 case READ_6:
c8a6c9a6 4843 first_block = get_unaligned_be16(&cmd->cmnd[2]);
283b4a9b 4844 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4845 if (block_cnt == 0)
4846 block_cnt = 256;
283b4a9b
SC		 4847 break;
4848 case WRITE_10:
4849 is_write = 1;
4850 case READ_10:
4851 first_block =
4852 (((u64) cmd->cmnd[2]) << 24) |
4853 (((u64) cmd->cmnd[3]) << 16) |
4854 (((u64) cmd->cmnd[4]) << 8) |
4855 cmd->cmnd[5];
4856 block_cnt =
4857 (((u32) cmd->cmnd[7]) << 8) |
4858 cmd->cmnd[8];
4859 break;
4860 case WRITE_12:
4861 is_write = 1;
4862 case READ_12:
4863 first_block =
4864 (((u64) cmd->cmnd[2]) << 24) |
4865 (((u64) cmd->cmnd[3]) << 16) |
4866 (((u64) cmd->cmnd[4]) << 8) |
4867 cmd->cmnd[5];
4868 block_cnt =
4869 (((u32) cmd->cmnd[6]) << 24) |
4870 (((u32) cmd->cmnd[7]) << 16) |
4871 (((u32) cmd->cmnd[8]) << 8) |
4872 cmd->cmnd[9];
4873 break;
4874 case WRITE_16:
4875 is_write = 1;
4876 case READ_16:
4877 first_block =
4878 (((u64) cmd->cmnd[2]) << 56) |
4879 (((u64) cmd->cmnd[3]) << 48) |
4880 (((u64) cmd->cmnd[4]) << 40) |
4881 (((u64) cmd->cmnd[5]) << 32) |
4882 (((u64) cmd->cmnd[6]) << 24) |
4883 (((u64) cmd->cmnd[7]) << 16) |
4884 (((u64) cmd->cmnd[8]) << 8) |
4885 cmd->cmnd[9];
4886 block_cnt =
4887 (((u32) cmd->cmnd[10]) << 24) |
4888 (((u32) cmd->cmnd[11]) << 16) |
4889 (((u32) cmd->cmnd[12]) << 8) |
4890 cmd->cmnd[13];
4891 break;
4892 default:
4893 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4894 }
283b4a9b
SC		 4895 last_block = first_block + block_cnt - 1;
4896
4897 /* check for write to non-RAID-0 */
4898 if (is_write && dev->raid_level != 0)
4899 return IO_ACCEL_INELIGIBLE;
4900
4901 /* check for invalid block or wraparound */
2b08b3e9
DB		 4902 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4903 last_block < first_block)
283b4a9b
SC		 4904 return IO_ACCEL_INELIGIBLE;
4905
4906 /* calculate stripe information for the request */
2b08b3e9
DB		 4907 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4908 le16_to_cpu(map->strip_size);
4909 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4910#if BITS_PER_LONG == 32
4911 tmpdiv = first_block;
4912 (void) do_div(tmpdiv, blocks_per_row);
4913 first_row = tmpdiv;
4914 tmpdiv = last_block;
4915 (void) do_div(tmpdiv, blocks_per_row);
4916 last_row = tmpdiv;
4917 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4918 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4919 tmpdiv = first_row_offset;
2b08b3e9 4920 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4921 first_column = tmpdiv;
4922 tmpdiv = last_row_offset;
2b08b3e9 4923 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4924 last_column = tmpdiv;
4925#else
4926 first_row = first_block / blocks_per_row;
4927 last_row = last_block / blocks_per_row;
4928 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4929 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4930 first_column = first_row_offset / strip_size;
4931 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4932#endif
4933
4934 /* if this isn't a single row/column then give to the controller */
4935 if ((first_row != last_row) || (first_column != last_column))
4936 return IO_ACCEL_INELIGIBLE;
4937
4938 /* proceeding with driver mapping */
2b08b3e9
DB		 4939 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4940 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4941 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4942 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4943 map_index = (map_row * total_disks_per_row) + first_column;
4944
4945 switch (dev->raid_level) {
4946 case HPSA_RAID_0:
4947 break; /* nothing special to do */
4948 case HPSA_RAID_1:
4949 /* Handles load balance across RAID 1 members.
4950 * (2-drive R1 and R10 with even # of drives.)
4951 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4952 */
2b08b3e9 4953 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4954 if (dev->offload_to_mirror)
2b08b3e9 4955 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4956 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4957 break;
4958 case HPSA_RAID_ADM:
4959 /* Handles N-way mirrors (R1-ADM)
4960 * and R10 with # of drives divisible by 3.)
4961 */
2b08b3e9 4962 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4963
4964 offload_to_mirror = dev->offload_to_mirror;
4965 raid_map_helper(map, offload_to_mirror,
4966 &map_index, &current_group);
4967 /* set mirror group to use next time */
4968 offload_to_mirror =
2b08b3e9
DB		 4969 (offload_to_mirror >=
4970 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4971 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4972 dev->offload_to_mirror = offload_to_mirror;
4973 /* Avoid direct use of dev->offload_to_mirror within this
4974 * function since multiple threads might simultaneously
4975 * increment it beyond the range of dev->layout_map_count -1.
4976 */
4977 break;
4978 case HPSA_RAID_5:
4979 case HPSA_RAID_6:
2b08b3e9 4980 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4981 break;
4982
4983 /* Verify first and last block are in same RAID group */
4984 r5or6_blocks_per_row =
2b08b3e9
DB		 4985 le16_to_cpu(map->strip_size) *
4986 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4987 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4988 stripesize = r5or6_blocks_per_row *
4989 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4990#if BITS_PER_LONG == 32
4991 tmpdiv = first_block;
4992 first_group = do_div(tmpdiv, stripesize);
4993 tmpdiv = first_group;
4994 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4995 first_group = tmpdiv;
4996 tmpdiv = last_block;
4997 last_group = do_div(tmpdiv, stripesize);
4998 tmpdiv = last_group;
4999 (void) do_div(tmpdiv, r5or6_blocks_per_row);
5000 last_group = tmpdiv;
5001#else
5002 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
5003 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 5004#endif
000ff7c2 5005 if (first_group != last_group)
6b80b18f
ST		 5006 return IO_ACCEL_INELIGIBLE;
5007
5008 /* Verify request is in a single row of RAID 5/6 */
5009#if BITS_PER_LONG == 32
5010 tmpdiv = first_block;
5011 (void) do_div(tmpdiv, stripesize);
5012 first_row = r5or6_first_row = r0_first_row = tmpdiv;
5013 tmpdiv = last_block;
5014 (void) do_div(tmpdiv, stripesize);
5015 r5or6_last_row = r0_last_row = tmpdiv;
5016#else
5017 first_row = r5or6_first_row = r0_first_row =
5018 first_block / stripesize;
5019 r5or6_last_row = r0_last_row = last_block / stripesize;
5020#endif
5021 if (r5or6_first_row != r5or6_last_row)
5022 return IO_ACCEL_INELIGIBLE;
5023
5024
5025 /* Verify request is in a single column */
5026#if BITS_PER_LONG == 32
5027 tmpdiv = first_block;
5028 first_row_offset = do_div(tmpdiv, stripesize);
5029 tmpdiv = first_row_offset;
5030 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
5031 r5or6_first_row_offset = first_row_offset;
5032 tmpdiv = last_block;
5033 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
5034 tmpdiv = r5or6_last_row_offset;
5035 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
5036 tmpdiv = r5or6_first_row_offset;
5037 (void) do_div(tmpdiv, map->strip_size);
5038 first_column = r5or6_first_column = tmpdiv;
5039 tmpdiv = r5or6_last_row_offset;
5040 (void) do_div(tmpdiv, map->strip_size);
5041 r5or6_last_column = tmpdiv;
5042#else
5043 first_row_offset = r5or6_first_row_offset =
5044 (u32)((first_block % stripesize) %
5045 r5or6_blocks_per_row);
5046
5047 r5or6_last_row_offset =
5048 (u32)((last_block % stripesize) %
5049 r5or6_blocks_per_row);
5050
5051 first_column = r5or6_first_column =
2b08b3e9 5052 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 5053 r5or6_last_column =
2b08b3e9 5054 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 5055#endif
5056 if (r5or6_first_column != r5or6_last_column)
5057 return IO_ACCEL_INELIGIBLE;
5058
5059 /* Request is eligible */
5060 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 5061 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 5062
5063 map_index = (first_group *
2b08b3e9 5064 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 5065 (map_row * total_disks_per_row) + first_column;
5066 break;
5067 default:
5068 return IO_ACCEL_INELIGIBLE;
283b4a9b 5069 }
6b80b18f 5070
07543e0c
SC		 5071 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
5072 return IO_ACCEL_INELIGIBLE;
5073
03383736 5074 c->phys_disk = dev->phys_disk[map_index];
c3390df4
DB		 5075 if (!c->phys_disk)
5076 return IO_ACCEL_INELIGIBLE;
03383736 5077
283b4a9b 5078 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 5079 disk_block = le64_to_cpu(map->disk_starting_blk) +
5080 first_row * le16_to_cpu(map->strip_size) +
5081 (first_row_offset - first_column *
5082 le16_to_cpu(map->strip_size));
283b4a9b
SC		 5083 disk_block_cnt = block_cnt;
5084
5085 /* handle differing logical/physical block sizes */
5086 if (map->phys_blk_shift) {
5087 disk_block <<= map->phys_blk_shift;
5088 disk_block_cnt <<= map->phys_blk_shift;
5089 }
5090 BUG_ON(disk_block_cnt > 0xffff);
5091
5092 /* build the new CDB for the physical disk I/O */
5093 if (disk_block > 0xffffffff) {
5094 cdb[0] = is_write ? WRITE_16 : READ_16;
5095 cdb[1] = 0;
5096 cdb[2] = (u8) (disk_block >> 56);
5097 cdb[3] = (u8) (disk_block >> 48);
5098 cdb[4] = (u8) (disk_block >> 40);
5099 cdb[5] = (u8) (disk_block >> 32);
5100 cdb[6] = (u8) (disk_block >> 24);
5101 cdb[7] = (u8) (disk_block >> 16);
5102 cdb[8] = (u8) (disk_block >> 8);
5103 cdb[9] = (u8) (disk_block);
5104 cdb[10] = (u8) (disk_block_cnt >> 24);
5105 cdb[11] = (u8) (disk_block_cnt >> 16);
5106 cdb[12] = (u8) (disk_block_cnt >> 8);
5107 cdb[13] = (u8) (disk_block_cnt);
5108 cdb[14] = 0;
5109 cdb[15] = 0;
5110 cdb_len = 16;
5111 } else {
5112 cdb[0] = is_write ? WRITE_10 : READ_10;
5113 cdb[1] = 0;
5114 cdb[2] = (u8) (disk_block >> 24);
5115 cdb[3] = (u8) (disk_block >> 16);
5116 cdb[4] = (u8) (disk_block >> 8);
5117 cdb[5] = (u8) (disk_block);
5118 cdb[6] = 0;
5119 cdb[7] = (u8) (disk_block_cnt >> 8);
5120 cdb[8] = (u8) (disk_block_cnt);
5121 cdb[9] = 0;
5122 cdb_len = 10;
5123 }
5124 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 5125 dev->scsi3addr,
5126 dev->phys_disk[map_index]);
283b4a9b
SC		 5127}
5128
25163bd5
WS		 5129/*
5130 * Submit commands down the "normal" RAID stack path
5131 * All callers to hpsa_ciss_submit must check lockup_detected
5132 * beforehand, before (opt.) and after calling cmd_alloc
5133 */
574f05d3
SC		 5134static int hpsa_ciss_submit(struct ctlr_info *h,
5135 struct CommandList *c, struct scsi_cmnd *cmd,
5136 unsigned char scsi3addr[])
edd16368 5137{
edd16368 5138 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 5139 c->cmd_type = CMD_SCSI;
5140 c->scsi_cmd = cmd;
5141 c->Header.ReplyQueue = 0; /* unused in simple mode */
5142 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 5143 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 5144
5145 /* Fill in the request block... */
5146
5147 c->Request.Timeout = 0;
edd16368
SC		 5148 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
5149 c->Request.CDBLen = cmd->cmd_len;
5150 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 5151 switch (cmd->sc_data_direction) {
5152 case DMA_TO_DEVICE:
a505b86f
SC		 5153 c->Request.type_attr_dir =
5154 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5155 break;
5156 case DMA_FROM_DEVICE:
a505b86f
SC		 5157 c->Request.type_attr_dir =
5158 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5159 break;
5160 case DMA_NONE:
a505b86f
SC		 5161 c->Request.type_attr_dir =
5162 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5163 break;
5164 case DMA_BIDIRECTIONAL:
5165 /* This can happen if a buggy application does a scsi passthru
5166 * and sets both inlen and outlen to non-zero. ( see
5167 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
5168 */
5169
a505b86f
SC		 5170 c->Request.type_attr_dir =
5171 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 5172 /* This is technically wrong, and hpsa controllers should
5173 * reject it with CMD_INVALID, which is the most correct
5174 * response, but non-fibre backends appear to let it
5175 * slide by, and give the same results as if this field
5176 * were set correctly. Either way is acceptable for
5177 * our purposes here.
5178 */
5179
5180 break;
5181
5182 default:
5183 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
5184 cmd->sc_data_direction);
5185 BUG();
5186 break;
5187 }
5188
33a2ffce 5189 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
73153fe5 5190 hpsa_cmd_resolve_and_free(h, c);
edd16368
SC		 5191 return SCSI_MLQUEUE_HOST_BUSY;
5192 }
5193 enqueue_cmd_and_start_io(h, c);
5194 /* the cmd'll come back via intr handler in complete_scsi_command() */
5195 return 0;
5196}
5197
360c73bd
SC		 5198static void hpsa_cmd_init(struct ctlr_info *h, int index,
5199 struct CommandList *c)
5200{
5201 dma_addr_t cmd_dma_handle, err_dma_handle;
5202
5203 /* Zero out all of commandlist except the last field, refcount */
5204 memset(c, 0, offsetof(struct CommandList, refcount));
5205 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
5206 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
5207 c->err_info = h->errinfo_pool + index;
5208 memset(c->err_info, 0, sizeof(*c->err_info));
5209 err_dma_handle = h->errinfo_pool_dhandle
5210 + index * sizeof(*c->err_info);
5211 c->cmdindex = index;
5212 c->busaddr = (u32) cmd_dma_handle;
5213 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
5214 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
5215 c->h = h;
a58e7e53 5216 c->scsi_cmd = SCSI_CMD_IDLE;
360c73bd
SC		 5217}
5218
5219static void hpsa_preinitialize_commands(struct ctlr_info *h)
5220{
5221 int i;
5222
5223 for (i = 0; i < h->nr_cmds; i++) {
5224 struct CommandList *c = h->cmd_pool + i;
5225
5226 hpsa_cmd_init(h, i, c);
5227 atomic_set(&c->refcount, 0);
5228 }
5229}
5230
5231static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
5232 struct CommandList *c)
5233{
5234 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
5235
73153fe5
WS		 5236 BUG_ON(c->cmdindex != index);
5237
360c73bd
SC		 5238 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
5239 memset(c->err_info, 0, sizeof(*c->err_info));
5240 c->busaddr = (u32) cmd_dma_handle;
5241}
5242
592a0ad5
WS		 5243static int hpsa_ioaccel_submit(struct ctlr_info *h,
5244 struct CommandList *c, struct scsi_cmnd *cmd,
5245 unsigned char *scsi3addr)
5246{
5247 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
5248 int rc = IO_ACCEL_INELIGIBLE;
5249
5250 cmd->host_scribble = (unsigned char *) c;
5251
5252 if (dev->offload_enabled) {
5253 hpsa_cmd_init(h, c->cmdindex, c);
5254 c->cmd_type = CMD_SCSI;
5255 c->scsi_cmd = cmd;
5256 rc = hpsa_scsi_ioaccel_raid_map(h, c);
5257 if (rc < 0) /* scsi_dma_map failed. */
5258 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 5259 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 5260 hpsa_cmd_init(h, c->cmdindex, c);
5261 c->cmd_type = CMD_SCSI;
5262 c->scsi_cmd = cmd;
5263 rc = hpsa_scsi_ioaccel_direct_map(h, c);
5264 if (rc < 0) /* scsi_dma_map failed. */
5265 rc = SCSI_MLQUEUE_HOST_BUSY;
5266 }
5267 return rc;
5268}
5269
080ef1cc
DB		 5270static void hpsa_command_resubmit_worker(struct work_struct *work)
5271{
5272 struct scsi_cmnd *cmd;
5273 struct hpsa_scsi_dev_t *dev;
8a0ff92c 5274 struct CommandList *c = container_of(work, struct CommandList, work);
080ef1cc
DB		 5275
5276 cmd = c->scsi_cmd;
5277 dev = cmd->device->hostdata;
5278 if (!dev) {
5279 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 5280 return hpsa_cmd_free_and_done(c->h, c, cmd);
080ef1cc 5281 }
d604f533
WS		 5282 if (c->reset_pending)
5283 return hpsa_cmd_resolve_and_free(c->h, c);
a58e7e53
WS		 5284 if (c->abort_pending)
5285 return hpsa_cmd_abort_and_free(c->h, c, cmd);
592a0ad5
WS		 5286 if (c->cmd_type == CMD_IOACCEL2) {
5287 struct ctlr_info *h = c->h;
5288 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5289 int rc;
5290
5291 if (c2->error_data.serv_response ==
5292 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
5293 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
5294 if (rc == 0)
5295 return;
5296 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
5297 /*
5298 * If we get here, it means dma mapping failed.
5299 * Try again via scsi mid layer, which will
5300 * then get SCSI_MLQUEUE_HOST_BUSY.
5301 */
5302 cmd->result = DID_IMM_RETRY << 16;
8a0ff92c 5303 return hpsa_cmd_free_and_done(h, c, cmd);
592a0ad5
WS		 5304 }
5305 /* else, fall thru and resubmit down CISS path */
5306 }
5307 }
360c73bd 5308 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 5309 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
5310 /*
5311 * If we get here, it means dma mapping failed. Try
5312 * again via scsi mid layer, which will then get
5313 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 5314 *
5315 * hpsa_ciss_submit will have already freed c
5316 * if it encountered a dma mapping failure.
080ef1cc
DB		 5317 */
5318 cmd->result = DID_IMM_RETRY << 16;
5319 cmd->scsi_done(cmd);
5320 }
5321}
5322
574f05d3
SC		 5323/* Running in struct Scsi_Host->host_lock less mode */
5324static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
5325{
5326 struct ctlr_info *h;
5327 struct hpsa_scsi_dev_t *dev;
5328 unsigned char scsi3addr[8];
5329 struct CommandList *c;
5330 int rc = 0;
5331
5332 /* Get the ptr to our adapter structure out of cmd->host. */
5333 h = sdev_to_hba(cmd->device);
73153fe5
WS		 5334
5335 BUG_ON(cmd->request->tag < 0);
5336
574f05d3
SC		 5337 dev = cmd->device->hostdata;
5338 if (!dev) {
ba74fdc4
DB		 5339 cmd->result = NOT_READY << 16; /* host byte */
5340 cmd->scsi_done(cmd);
5341 return 0;
5342 }
5343
5344 if (dev->removed) {
574f05d3
SC		 5345 cmd->result = DID_NO_CONNECT << 16;
5346 cmd->scsi_done(cmd);
5347 return 0;
5348 }
574f05d3 5349
73153fe5 5350 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
bf43caf3 5351
407863cb 5352 if (unlikely(lockup_detected(h))) {
25163bd5 5353 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 5354 cmd->scsi_done(cmd);
5355 return 0;
5356 }
73153fe5 5357 c = cmd_tagged_alloc(h, cmd);
574f05d3 5358
407863cb
SC		 5359 /*
5360 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 5361 * Retries always go down the normal I/O path.
5362 */
5363 if (likely(cmd->retries == 0 &&
5364 cmd->request->cmd_type == REQ_TYPE_FS &&
5365 h->acciopath_status)) {
592a0ad5
WS		 5366 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
5367 if (rc == 0)
5368 return 0;
5369 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
73153fe5 5370 hpsa_cmd_resolve_and_free(h, c);
592a0ad5 5371 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 5372 }
5373 }
5374 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
5375}
5376
8ebc9248 5377static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 5378{
5379 unsigned long flags;
5380
8ebc9248
WS		 5381 spin_lock_irqsave(&h->scan_lock, flags);
5382 h->scan_finished = 1;
5383 wake_up_all(&h->scan_wait_queue);
5384 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 5385}
5386
a08a8471
SC		 5387static void hpsa_scan_start(struct Scsi_Host *sh)
5388{
5389 struct ctlr_info *h = shost_to_hba(sh);
5390 unsigned long flags;
5391
8ebc9248
WS		 5392 /*
5393 * Don't let rescans be initiated on a controller known to be locked
5394 * up. If the controller locks up *during* a rescan, that thread is
5395 * probably hosed, but at least we can prevent new rescan threads from
5396 * piling up on a locked up controller.
5397 */
5398 if (unlikely(lockup_detected(h)))
5399 return hpsa_scan_complete(h);
5f389360 5400
a08a8471
SC		 5401 /* wait until any scan already in progress is finished. */
5402 while (1) {
5403 spin_lock_irqsave(&h->scan_lock, flags);
5404 if (h->scan_finished)
5405 break;
5406 spin_unlock_irqrestore(&h->scan_lock, flags);
5407 wait_event(h->scan_wait_queue, h->scan_finished);
5408 /* Note: We don't need to worry about a race between this
5409 * thread and driver unload because the midlayer will
5410 * have incremented the reference count, so unload won't
5411 * happen if we're in here.
5412 */
5413 }
5414 h->scan_finished = 0; /* mark scan as in progress */
5415 spin_unlock_irqrestore(&h->scan_lock, flags);
5416
8ebc9248
WS		 5417 if (unlikely(lockup_detected(h)))
5418 return hpsa_scan_complete(h);
5f389360 5419
8aa60681 5420 hpsa_update_scsi_devices(h);
a08a8471 5421
8ebc9248 5422 hpsa_scan_complete(h);
a08a8471
SC		 5423}
5424
7c0a0229
DB		 5425static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
5426{
03383736
DB		 5427 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
5428
5429 if (!logical_drive)
5430 return -ENODEV;
7c0a0229
DB		 5431
5432 if (qdepth < 1)
5433 qdepth = 1;
03383736
DB		 5434 else if (qdepth > logical_drive->queue_depth)
5435 qdepth = logical_drive->queue_depth;
5436
5437 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 5438}
5439
a08a8471
SC		 5440static int hpsa_scan_finished(struct Scsi_Host *sh,
5441 unsigned long elapsed_time)
5442{
5443 struct ctlr_info *h = shost_to_hba(sh);
5444 unsigned long flags;
5445 int finished;
5446
5447 spin_lock_irqsave(&h->scan_lock, flags);
5448 finished = h->scan_finished;
5449 spin_unlock_irqrestore(&h->scan_lock, flags);
5450 return finished;
5451}
5452
2946e82b 5453static int hpsa_scsi_host_alloc(struct ctlr_info *h)
edd16368 5454{
b705690d 5455 struct Scsi_Host *sh;
edd16368 5456
b705690d 5457 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2946e82b
RE		 5458 if (sh == NULL) {
5459 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
5460 return -ENOMEM;
5461 }
b705690d
SC		 5462
5463 sh->io_port = 0;
5464 sh->n_io_port = 0;
5465 sh->this_id = -1;
5466 sh->max_channel = 3;
5467 sh->max_cmd_len = MAX_COMMAND_SIZE;
5468 sh->max_lun = HPSA_MAX_LUN;
5469 sh->max_id = HPSA_MAX_LUN;
41ce4c35 5470 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 5471 sh->cmd_per_lun = sh->can_queue;
b705690d 5472 sh->sg_tablesize = h->maxsgentries;
d04e62b9 5473 sh->transportt = hpsa_sas_transport_template;
b705690d
SC		 5474 sh->hostdata[0] = (unsigned long) h;
5475 sh->irq = h->intr[h->intr_mode];
5476 sh->unique_id = sh->irq;
64d513ac 5477
2946e82b 5478 h->scsi_host = sh;
b705690d 5479 return 0;
2946e82b 5480}
b705690d 5481
2946e82b
RE		 5482static int hpsa_scsi_add_host(struct ctlr_info *h)
5483{
5484 int rv;
5485
5486 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
5487 if (rv) {
5488 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
5489 return rv;
5490 }
5491 scsi_scan_host(h->scsi_host);
5492 return 0;
edd16368
SC		 5493}
5494
73153fe5
WS		 5495/*
5496 * The block layer has already gone to the trouble of picking out a unique,
5497 * small-integer tag for this request. We use an offset from that value as
5498 * an index to select our command block. (The offset allows us to reserve the
5499 * low-numbered entries for our own uses.)
5500 */
5501static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
5502{
5503 int idx = scmd->request->tag;
5504
5505 if (idx < 0)
5506 return idx;
5507
5508 /* Offset to leave space for internal cmds. */
5509 return idx += HPSA_NRESERVED_CMDS;
5510}
5511
b69324ff
WS		 5512/*
5513 * Send a TEST_UNIT_READY command to the specified LUN using the specified
5514 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5515 */
5516static int hpsa_send_test_unit_ready(struct ctlr_info *h,
5517 struct CommandList *c, unsigned char lunaddr[],
5518 int reply_queue)
5519{
5520 int rc;
5521
5522 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
5523 (void) fill_cmd(c, TEST_UNIT_READY, h,
5524 NULL, 0, 0, lunaddr, TYPE_CMD);
c448ecfa 5525 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
b69324ff
WS		 5526 if (rc)
5527 return rc;
5528 /* no unmap needed here because no data xfer. */
5529
5530 /* Check if the unit is already ready. */
5531 if (c->err_info->CommandStatus == CMD_SUCCESS)
5532 return 0;
5533
5534 /*
5535 * The first command sent after reset will receive "unit attention" to
5536 * indicate that the LUN has been reset...this is actually what we're
5537 * looking for (but, success is good too).
5538 */
5539 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5540 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5541 (c->err_info->SenseInfo[2] == NO_SENSE ||
5542 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5543 return 0;
5544
5545 return 1;
5546}
5547
5548/*
5549 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5550 * returns zero when the unit is ready, and non-zero when giving up.
5551 */
5552static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5553 struct CommandList *c,
5554 unsigned char lunaddr[], int reply_queue)
edd16368 5555{
8919358e 5556 int rc;
edd16368
SC		 5557 int count = 0;
5558 int waittime = 1; /* seconds */
edd16368
SC		 5559
5560 /* Send test unit ready until device ready, or give up. */
b69324ff 5561 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
edd16368 5562
b69324ff
WS		 5563 /*
5564 * Wait for a bit. do this first, because if we send
edd16368
SC		 5565 * the TUR right away, the reset will just abort it.
5566 */
5567 msleep(1000 * waittime);
b69324ff
WS		 5568
5569 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5570 if (!rc)
5571 break;
edd16368
SC		 5572
5573 /* Increase wait time with each try, up to a point. */
5574 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
b69324ff 5575 waittime *= 2;
edd16368 5576
b69324ff
WS		 5577 dev_warn(&h->pdev->dev,
5578 "waiting %d secs for device to become ready.\n",
5579 waittime);
5580 }
edd16368 5581
b69324ff
WS		 5582 return rc;
5583}
edd16368 5584
b69324ff
WS		 5585static int wait_for_device_to_become_ready(struct ctlr_info *h,
5586 unsigned char lunaddr[],
5587 int reply_queue)
5588{
5589 int first_queue;
5590 int last_queue;
5591 int rq;
5592 int rc = 0;
5593 struct CommandList *c;
5594
5595 c = cmd_alloc(h);
5596
5597 /*
5598 * If no specific reply queue was requested, then send the TUR
5599 * repeatedly, requesting a reply on each reply queue; otherwise execute
5600 * the loop exactly once using only the specified queue.
5601 */
5602 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5603 first_queue = 0;
5604 last_queue = h->nreply_queues - 1;
5605 } else {
5606 first_queue = reply_queue;
5607 last_queue = reply_queue;
5608 }
5609
5610 for (rq = first_queue; rq <= last_queue; rq++) {
5611 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5612 if (rc)
edd16368 5613 break;
edd16368
SC		 5614 }
5615
5616 if (rc)
5617 dev_warn(&h->pdev->dev, "giving up on device.\n");
5618 else
5619 dev_warn(&h->pdev->dev, "device is ready.\n");
5620
45fcb86e 5621 cmd_free(h, c);
edd16368
SC		 5622 return rc;
5623}
5624
5625/* Need at least one of these error handlers to keep ../scsi/hosts.c from
5626 * complaining. Doing a host- or bus-reset can't do anything good here.
5627 */
5628static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5629{
5630 int rc;
5631 struct ctlr_info *h;
5632 struct hpsa_scsi_dev_t *dev;
0b9b7b6e 5633 u8 reset_type;
2dc127bb 5634 char msg[48];
edd16368
SC		 5635
5636 /* find the controller to which the command to be aborted was sent */
5637 h = sdev_to_hba(scsicmd->device);
5638 if (h == NULL) /* paranoia */
5639 return FAILED;
e345893b
DB		 5640
5641 if (lockup_detected(h))
5642 return FAILED;
5643
edd16368
SC		 5644 dev = scsicmd->device->hostdata;
5645 if (!dev) {
d604f533 5646 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
edd16368
SC		 5647 return FAILED;
5648 }
25163bd5
WS		 5649
5650 /* if controller locked up, we can guarantee command won't complete */
5651 if (lockup_detected(h)) {
2dc127bb
DC		 5652 snprintf(msg, sizeof(msg),
5653 "cmd %d RESET FAILED, lockup detected",
5654 hpsa_get_cmd_index(scsicmd));
73153fe5 5655 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5656 return FAILED;
5657 }
5658
5659 /* this reset request might be the result of a lockup; check */
5660 if (detect_controller_lockup(h)) {
2dc127bb
DC		 5661 snprintf(msg, sizeof(msg),
5662 "cmd %d RESET FAILED, new lockup detected",
5663 hpsa_get_cmd_index(scsicmd));
73153fe5 5664 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5665 return FAILED;
5666 }
5667
d604f533
WS		 5668 /* Do not attempt on controller */
5669 if (is_hba_lunid(dev->scsi3addr))
5670 return SUCCESS;
5671
0b9b7b6e
ST		 5672 if (is_logical_dev_addr_mode(dev->scsi3addr))
5673 reset_type = HPSA_DEVICE_RESET_MSG;
5674 else
5675 reset_type = HPSA_PHYS_TARGET_RESET;
5676
5677 sprintf(msg, "resetting %s",
5678 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ");
5679 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5 5680
da03ded0 5681 h->reset_in_progress = 1;
25163bd5 5682
edd16368 5683 /* send a reset to the SCSI LUN which the command was sent to */
0b9b7b6e 5684 rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type,
d604f533 5685 DEFAULT_REPLY_QUEUE);
0b9b7b6e
ST		 5686 sprintf(msg, "reset %s %s",
5687 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ",
5688 rc == 0 ? "completed successfully" : "failed");
d604f533 5689 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
da03ded0 5690 h->reset_in_progress = 0;
d604f533 5691 return rc == 0 ? SUCCESS : FAILED;
edd16368
SC		 5692}
5693
6cba3f19
SC		 5694static void swizzle_abort_tag(u8 *tag)
5695{
5696 u8 original_tag[8];
5697
5698 memcpy(original_tag, tag, 8);
5699 tag[0] = original_tag[3];
5700 tag[1] = original_tag[2];
5701 tag[2] = original_tag[1];
5702 tag[3] = original_tag[0];
5703 tag[4] = original_tag[7];
5704 tag[5] = original_tag[6];
5705 tag[6] = original_tag[5];
5706 tag[7] = original_tag[4];
5707}
5708
17eb87d2 5709static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 5710 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 5711{
2b08b3e9 5712 u64 tag;
17eb87d2
ST		 5713 if (c->cmd_type == CMD_IOACCEL1) {
5714 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5715 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 5716 tag = le64_to_cpu(cm1->tag);
5717 *tagupper = cpu_to_le32(tag >> 32);
5718 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 5719 return;
5720 }
5721 if (c->cmd_type == CMD_IOACCEL2) {
5722 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5723 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 5724 /* upper tag not used in ioaccel2 mode */
5725 memset(tagupper, 0, sizeof(*tagupper));
5726 *taglower = cm2->Tag;
54b6e9e9 5727 return;
17eb87d2 5728 }
2b08b3e9
DB		 5729 tag = le64_to_cpu(c->Header.tag);
5730 *tagupper = cpu_to_le32(tag >> 32);
5731 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 5732}
5733
75167d2c 5734static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 5735 struct CommandList *abort, int reply_queue)
75167d2c
SC		 5736{
5737 int rc = IO_OK;
5738 struct CommandList *c;
5739 struct ErrorInfo *ei;
2b08b3e9 5740 __le32 tagupper, taglower;
75167d2c 5741
45fcb86e 5742 c = cmd_alloc(h);
75167d2c 5743
a2dac136 5744 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 5745 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 5746 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 5747 if (h->needs_abort_tags_swizzled)
6cba3f19 5748 swizzle_abort_tag(&c->Request.CDB[4]);
c448ecfa 5749 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
17eb87d2 5750 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5751 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 5752 __func__, tagupper, taglower);
75167d2c
SC		 5753 /* no unmap needed here because no data xfer. */
5754
5755 ei = c->err_info;
5756 switch (ei->CommandStatus) {
5757 case CMD_SUCCESS:
5758 break;
9437ac43
SC		 5759 case CMD_TMF_STATUS:
5760 rc = hpsa_evaluate_tmf_status(h, c);
5761 break;
75167d2c
SC		 5762 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5763 rc = -1;
5764 break;
5765 default:
5766 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 5767 __func__, tagupper, taglower);
d1e8beac 5768 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 5769 rc = -1;
5770 break;
5771 }
45fcb86e 5772 cmd_free(h, c);
dd0e19f3
ST		 5773 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5774 __func__, tagupper, taglower);
75167d2c
SC		 5775 return rc;
5776}
5777
8be986cc
SC		 5778static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5779 struct CommandList *command_to_abort, int reply_queue)
5780{
5781 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5782 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5783 struct io_accel2_cmd *c2a =
5784 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
a58e7e53 5785 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
8be986cc
SC		 5786 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5787
5788 /*
5789 * We're overlaying struct hpsa_tmf_struct on top of something which
5790 * was allocated as a struct io_accel2_cmd, so we better be sure it
5791 * actually fits, and doesn't overrun the error info space.
5792 */
5793 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5794 sizeof(struct io_accel2_cmd));
5795 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5796 offsetof(struct hpsa_tmf_struct, error_len) +
5797 sizeof(ac->error_len));
5798
5799 c->cmd_type = IOACCEL2_TMF;
a58e7e53
WS		 5800 c->scsi_cmd = SCSI_CMD_BUSY;
5801
8be986cc
SC		 5802 /* Adjust the DMA address to point to the accelerated command buffer */
5803 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5804 (c->cmdindex * sizeof(struct io_accel2_cmd));
5805 BUG_ON(c->busaddr & 0x0000007F);
5806
5807 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5808 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5809 ac->reply_queue = reply_queue;
5810 ac->tmf = IOACCEL2_TMF_ABORT;
5811 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5812 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5813 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5814 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5815 ac->error_ptr = cpu_to_le64(c->busaddr +
5816 offsetof(struct io_accel2_cmd, error_data));
5817 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5818}
5819
54b6e9e9
ST		 5820/* ioaccel2 path firmware cannot handle abort task requests.
5821 * Change abort requests to physical target reset, and send to the
5822 * address of the physical disk used for the ioaccel 2 command.
5823 * Return 0 on success (IO_OK)
5824 * -1 on failure
5825 */
5826
5827static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 5828 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 5829{
5830 int rc = IO_OK;
5831 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5832 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5833 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5834 unsigned char *psa = &phys_scsi3addr[0];
5835
5836 /* Get a pointer to the hpsa logical device. */
7fa3030c 5837 scmd = abort->scsi_cmd;
54b6e9e9
ST		 5838 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5839 if (dev == NULL) {
5840 dev_warn(&h->pdev->dev,
5841 "Cannot abort: no device pointer for command.\n");
5842 return -1; /* not abortable */
5843 }
5844
2ba8bfc8
SC		 5845 if (h->raid_offload_debug > 0)
5846 dev_info(&h->pdev->dev,
0d96ef5f 5847 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 5848 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 5849 "Reset as abort",
2ba8bfc8
SC		 5850 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5851 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5852
54b6e9e9
ST		 5853 if (!dev->offload_enabled) {
5854 dev_warn(&h->pdev->dev,
5855 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5856 return -1; /* not abortable */
5857 }
5858
5859 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5860 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5861 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5862 return -1; /* not abortable */
5863 }
5864
5865 /* send the reset */
2ba8bfc8
SC		 5866 if (h->raid_offload_debug > 0)
5867 dev_info(&h->pdev->dev,
5868 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5869 psa[0], psa[1], psa[2], psa[3],
5870 psa[4], psa[5], psa[6], psa[7]);
d604f533 5871 rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 5872 if (rc != 0) {
5873 dev_warn(&h->pdev->dev,
5874 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5875 psa[0], psa[1], psa[2], psa[3],
5876 psa[4], psa[5], psa[6], psa[7]);
5877 return rc; /* failed to reset */
5878 }
5879
5880 /* wait for device to recover */
b69324ff 5881 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
54b6e9e9
ST		 5882 dev_warn(&h->pdev->dev,
5883 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5884 psa[0], psa[1], psa[2], psa[3],
5885 psa[4], psa[5], psa[6], psa[7]);
5886 return -1; /* failed to recover */
5887 }
5888
5889 /* device recovered */
5890 dev_info(&h->pdev->dev,
5891 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5892 psa[0], psa[1], psa[2], psa[3],
5893 psa[4], psa[5], psa[6], psa[7]);
5894
5895 return rc; /* success */
5896}
5897
8be986cc
SC		 5898static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
5899 struct CommandList *abort, int reply_queue)
5900{
5901 int rc = IO_OK;
5902 struct CommandList *c;
5903 __le32 taglower, tagupper;
5904 struct hpsa_scsi_dev_t *dev;
5905 struct io_accel2_cmd *c2;
5906
5907 dev = abort->scsi_cmd->device->hostdata;
5908 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
5909 return -1;
5910
5911 c = cmd_alloc(h);
5912 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
5913 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
c448ecfa 5914 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
8be986cc
SC		 5915 hpsa_get_tag(h, abort, &taglower, &tagupper);
5916 dev_dbg(&h->pdev->dev,
5917 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
5918 __func__, tagupper, taglower);
5919 /* no unmap needed here because no data xfer. */
5920
5921 dev_dbg(&h->pdev->dev,
5922 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
5923 __func__, tagupper, taglower, c2->error_data.serv_response);
5924 switch (c2->error_data.serv_response) {
5925 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
5926 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
5927 rc = 0;
5928 break;
5929 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
5930 case IOACCEL2_SERV_RESPONSE_FAILURE:
5931 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
5932 rc = -1;
5933 break;
5934 default:
5935 dev_warn(&h->pdev->dev,
5936 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
5937 __func__, tagupper, taglower,
5938 c2->error_data.serv_response);
5939 rc = -1;
5940 }
5941 cmd_free(h, c);
5942 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
5943 tagupper, taglower);
5944 return rc;
5945}
5946
6cba3f19 5947static int hpsa_send_abort_both_ways(struct ctlr_info *h,
39f3deb2 5948 struct hpsa_scsi_dev_t *dev, struct CommandList *abort, int reply_queue)
6cba3f19 5949{
8be986cc
SC		 5950 /*
5951 * ioccelerator mode 2 commands should be aborted via the
54b6e9e9 5952 * accelerated path, since RAID path is unaware of these commands,
8be986cc
SC		 5953 * but not all underlying firmware can handle abort TMF.
5954 * Change abort to physical device reset when abort TMF is unsupported.
54b6e9e9 5955 */
8be986cc 5956 if (abort->cmd_type == CMD_IOACCEL2) {
39f3deb2
DB		 5957 if ((HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags) ||
5958 dev->physical_device)
8be986cc
SC		 5959 return hpsa_send_abort_ioaccel2(h, abort,
5960 reply_queue);
5961 else
39f3deb2
DB		 5962 return hpsa_send_reset_as_abort_ioaccel2(h,
5963 dev->scsi3addr,
25163bd5 5964 abort, reply_queue);
8be986cc 5965 }
39f3deb2 5966 return hpsa_send_abort(h, dev->scsi3addr, abort, reply_queue);
25163bd5 5967}
54b6e9e9 5968
25163bd5
WS		 5969/* Find out which reply queue a command was meant to return on */
5970static int hpsa_extract_reply_queue(struct ctlr_info *h,
5971 struct CommandList *c)
5972{
5973 if (c->cmd_type == CMD_IOACCEL2)
5974 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5975 return c->Header.ReplyQueue;
6cba3f19
SC		 5976}
5977
9b5c48c2
SC		 5978/*
5979 * Limit concurrency of abort commands to prevent
5980 * over-subscription of commands
5981 */
5982static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5983{
5984#define ABORT_CMD_WAIT_MSECS 5000
5985 return !wait_event_timeout(h->abort_cmd_wait_queue,
5986 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5987 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5988}
5989
75167d2c
SC		 5990/* Send an abort for the specified command.
5991 * If the device and controller support it,
5992 * send a task abort request.
5993 */
5994static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5995{
5996
a58e7e53 5997 int rc;
75167d2c
SC		 5998 struct ctlr_info *h;
5999 struct hpsa_scsi_dev_t *dev;
6000 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 6001 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
6002 char msg[256]; /* For debug messaging. */
6003 int ml = 0;
2b08b3e9 6004 __le32 tagupper, taglower;
25163bd5
WS		 6005 int refcount, reply_queue;
6006
6007 if (sc == NULL)
6008 return FAILED;
75167d2c 6009
9b5c48c2
SC		 6010 if (sc->device == NULL)
6011 return FAILED;
6012
75167d2c
SC		 6013 /* Find the controller of the command to be aborted */
6014 h = sdev_to_hba(sc->device);
9b5c48c2 6015 if (h == NULL)
75167d2c
SC		 6016 return FAILED;
6017
25163bd5
WS		 6018 /* Find the device of the command to be aborted */
6019 dev = sc->device->hostdata;
6020 if (!dev) {
6021 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
6022 msg);
e345893b 6023 return FAILED;
25163bd5
WS		 6024 }
6025
6026 /* If controller locked up, we can guarantee command won't complete */
6027 if (lockup_detected(h)) {
6028 hpsa_show_dev_msg(KERN_WARNING, h, dev,
6029 "ABORT FAILED, lockup detected");
6030 return FAILED;
6031 }
6032
6033 /* This is a good time to check if controller lockup has occurred */
6034 if (detect_controller_lockup(h)) {
6035 hpsa_show_dev_msg(KERN_WARNING, h, dev,
6036 "ABORT FAILED, new lockup detected");
6037 return FAILED;
6038 }
e345893b 6039
75167d2c
SC		 6040 /* Check that controller supports some kind of task abort */
6041 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
6042 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6043 return FAILED;
6044
6045 memset(msg, 0, sizeof(msg));
4b761557 6046 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
75167d2c 6047 h->scsi_host->host_no, sc->device->channel,
0d96ef5f 6048 sc->device->id, sc->device->lun,
4b761557 6049 "Aborting command", sc);
75167d2c 6050
75167d2c
SC		 6051 /* Get SCSI command to be aborted */
6052 abort = (struct CommandList *) sc->host_scribble;
6053 if (abort == NULL) {
281a7fd0
WS		 6054 /* This can happen if the command already completed. */
6055 return SUCCESS;
6056 }
6057 refcount = atomic_inc_return(&abort->refcount);
6058 if (refcount == 1) { /* Command is done already. */
6059 cmd_free(h, abort);
6060 return SUCCESS;
75167d2c 6061 }
9b5c48c2
SC		 6062
6063 /* Don't bother trying the abort if we know it won't work. */
6064 if (abort->cmd_type != CMD_IOACCEL2 &&
6065 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
6066 cmd_free(h, abort);
6067 return FAILED;
6068 }
6069
a58e7e53
WS		 6070 /*
6071 * Check that we're aborting the right command.
6072 * It's possible the CommandList already completed and got re-used.
6073 */
6074 if (abort->scsi_cmd != sc) {
6075 cmd_free(h, abort);
6076 return SUCCESS;
6077 }
6078
6079 abort->abort_pending = true;
17eb87d2 6080 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 6081 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 6082 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 6083 as = abort->scsi_cmd;
75167d2c 6084 if (as != NULL)
4b761557
RE		 6085 ml += sprintf(msg+ml,
6086 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
6087 as->cmd_len, as->cmnd[0], as->cmnd[1],
6088 as->serial_number);
6089 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
0d96ef5f 6090 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
4b761557 6091
75167d2c
SC		 6092 /*
6093 * Command is in flight, or possibly already completed
6094 * by the firmware (but not to the scsi mid layer) but we can't
6095 * distinguish which. Send the abort down.
6096 */
9b5c48c2
SC		 6097 if (wait_for_available_abort_cmd(h)) {
6098 dev_warn(&h->pdev->dev,
4b761557
RE		 6099 "%s FAILED, timeout waiting for an abort command to become available.\n",
6100 msg);
9b5c48c2
SC		 6101 cmd_free(h, abort);
6102 return FAILED;
6103 }
39f3deb2 6104 rc = hpsa_send_abort_both_ways(h, dev, abort, reply_queue);
9b5c48c2
SC		 6105 atomic_inc(&h->abort_cmds_available);
6106 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 6107 if (rc != 0) {
4b761557 6108 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
0d96ef5f 6109 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4b761557 6110 "FAILED to abort command");
281a7fd0 6111 cmd_free(h, abort);
75167d2c
SC		 6112 return FAILED;
6113 }
4b761557 6114 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
d604f533 6115 wait_event(h->event_sync_wait_queue,
a58e7e53 6116 abort->scsi_cmd != sc || lockup_detected(h));
281a7fd0 6117 cmd_free(h, abort);
a58e7e53 6118 return !lockup_detected(h) ? SUCCESS : FAILED;
75167d2c
SC		 6119}
6120
73153fe5
WS		 6121/*
6122 * For operations with an associated SCSI command, a command block is allocated
6123 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
6124 * block request tag as an index into a table of entries. cmd_tagged_free() is
6125 * the complement, although cmd_free() may be called instead.
6126 */
6127static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
6128 struct scsi_cmnd *scmd)
6129{
6130 int idx = hpsa_get_cmd_index(scmd);
6131 struct CommandList *c = h->cmd_pool + idx;
6132
6133 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
6134 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
6135 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
6136 /* The index value comes from the block layer, so if it's out of
6137 * bounds, it's probably not our bug.
6138 */
6139 BUG();
6140 }
6141
6142 atomic_inc(&c->refcount);
6143 if (unlikely(!hpsa_is_cmd_idle(c))) {
6144 /*
6145 * We expect that the SCSI layer will hand us a unique tag
6146 * value. Thus, there should never be a collision here between
6147 * two requests...because if the selected command isn't idle
6148 * then someone is going to be very disappointed.
6149 */
6150 dev_err(&h->pdev->dev,
6151 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
6152 idx);
6153 if (c->scsi_cmd != NULL)
6154 scsi_print_command(c->scsi_cmd);
6155 scsi_print_command(scmd);
6156 }
6157
6158 hpsa_cmd_partial_init(h, idx, c);
6159 return c;
6160}
6161
6162static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
6163{
6164 /*
6165 * Release our reference to the block. We don't need to do anything
6166 * else to free it, because it is accessed by index. (There's no point
6167 * in checking the result of the decrement, since we cannot guarantee
6168 * that there isn't a concurrent abort which is also accessing it.)
6169 */
6170 (void)atomic_dec(&c->refcount);
6171}
6172
edd16368
SC		 6173/*
6174 * For operations that cannot sleep, a command block is allocated at init,
6175 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
6176 * which ones are free or in use. Lock must be held when calling this.
6177 * cmd_free() is the complement.
bf43caf3
RE		 6178 * This function never gives up and returns NULL. If it hangs,
6179 * another thread must call cmd_free() to free some tags.
edd16368 6180 */
281a7fd0 6181
edd16368
SC		 6182static struct CommandList *cmd_alloc(struct ctlr_info *h)
6183{
6184 struct CommandList *c;
360c73bd 6185 int refcount, i;
73153fe5 6186 int offset = 0;
4c413128 6187
33811026
RE		 6188 /*
6189 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 6190 * multiple threads could get in here, and one thread could
6191 * be scanning through the list of bits looking for a free
6192 * one, but the free ones are always behind him, and other
6193 * threads sneak in behind him and eat them before he can
6194 * get to them, so that while there is always a free one, a
6195 * very unlucky thread might be starved anyway, never able to
6196 * beat the other threads. In reality, this happens so
6197 * infrequently as to be indistinguishable from never.
73153fe5
WS		 6198 *
6199 * Note that we start allocating commands before the SCSI host structure
6200 * is initialized. Since the search starts at bit zero, this
6201 * all works, since we have at least one command structure available;
6202 * however, it means that the structures with the low indexes have to be
6203 * reserved for driver-initiated requests, while requests from the block
6204 * layer will use the higher indexes.
4c413128 6205 */
edd16368 6206
281a7fd0 6207 for (;;) {
73153fe5
WS		 6208 i = find_next_zero_bit(h->cmd_pool_bits,
6209 HPSA_NRESERVED_CMDS,
6210 offset);
6211 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
281a7fd0
WS		 6212 offset = 0;
6213 continue;
6214 }
6215 c = h->cmd_pool + i;
6216 refcount = atomic_inc_return(&c->refcount);
6217 if (unlikely(refcount > 1)) {
6218 cmd_free(h, c); /* already in use */
73153fe5 6219 offset = (i + 1) % HPSA_NRESERVED_CMDS;
281a7fd0
WS		 6220 continue;
6221 }
6222 set_bit(i & (BITS_PER_LONG - 1),
6223 h->cmd_pool_bits + (i / BITS_PER_LONG));
6224 break; /* it's ours now. */
6225 }
360c73bd 6226 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 6227 return c;
6228}
6229
73153fe5
WS		 6230/*
6231 * This is the complementary operation to cmd_alloc(). Note, however, in some
6232 * corner cases it may also be used to free blocks allocated by
6233 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
6234 * the clear-bit is harmless.
6235 */
edd16368
SC		 6236static void cmd_free(struct ctlr_info *h, struct CommandList *c)
6237{
281a7fd0
WS		 6238 if (atomic_dec_and_test(&c->refcount)) {
6239 int i;
edd16368 6240
281a7fd0
WS		 6241 i = c - h->cmd_pool;
6242 clear_bit(i & (BITS_PER_LONG - 1),
6243 h->cmd_pool_bits + (i / BITS_PER_LONG));
6244 }
edd16368
SC		 6245}
6246
edd16368
SC		 6247#ifdef CONFIG_COMPAT
6248
42a91641
DB		 6249static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
6250 void __user *arg)
edd16368
SC		 6251{
6252 IOCTL32_Command_struct __user *arg32 =
6253 (IOCTL32_Command_struct __user *) arg;
6254 IOCTL_Command_struct arg64;
6255 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
6256 int err;
6257 u32 cp;
6258
938abd84 6259 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 6260 err = 0;
6261 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
6262 sizeof(arg64.LUN_info));
6263 err |= copy_from_user(&arg64.Request, &arg32->Request,
6264 sizeof(arg64.Request));
6265 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
6266 sizeof(arg64.error_info));
6267 err |= get_user(arg64.buf_size, &arg32->buf_size);
6268 err |= get_user(cp, &arg32->buf);
6269 arg64.buf = compat_ptr(cp);
6270 err |= copy_to_user(p, &arg64, sizeof(arg64));
6271
6272 if (err)
6273 return -EFAULT;
6274
42a91641 6275 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 6276 if (err)
6277 return err;
6278 err |= copy_in_user(&arg32->error_info, &p->error_info,
6279 sizeof(arg32->error_info));
6280 if (err)
6281 return -EFAULT;
6282 return err;
6283}
6284
6285static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 6286 int cmd, void __user *arg)
edd16368
SC		 6287{
6288 BIG_IOCTL32_Command_struct __user *arg32 =
6289 (BIG_IOCTL32_Command_struct __user *) arg;
6290 BIG_IOCTL_Command_struct arg64;
6291 BIG_IOCTL_Command_struct __user *p =
6292 compat_alloc_user_space(sizeof(arg64));
6293 int err;
6294 u32 cp;
6295
938abd84 6296 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 6297 err = 0;
6298 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
6299 sizeof(arg64.LUN_info));
6300 err |= copy_from_user(&arg64.Request, &arg32->Request,
6301 sizeof(arg64.Request));
6302 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
6303 sizeof(arg64.error_info));
6304 err |= get_user(arg64.buf_size, &arg32->buf_size);
6305 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
6306 err |= get_user(cp, &arg32->buf);
6307 arg64.buf = compat_ptr(cp);
6308 err |= copy_to_user(p, &arg64, sizeof(arg64));
6309
6310 if (err)
6311 return -EFAULT;
6312
42a91641 6313 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 6314 if (err)
6315 return err;
6316 err |= copy_in_user(&arg32->error_info, &p->error_info,
6317 sizeof(arg32->error_info));
6318 if (err)
6319 return -EFAULT;
6320 return err;
6321}
71fe75a7 6322
42a91641 6323static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 6324{
6325 switch (cmd) {
6326 case CCISS_GETPCIINFO:
6327 case CCISS_GETINTINFO:
6328 case CCISS_SETINTINFO:
6329 case CCISS_GETNODENAME:
6330 case CCISS_SETNODENAME:
6331 case CCISS_GETHEARTBEAT:
6332 case CCISS_GETBUSTYPES:
6333 case CCISS_GETFIRMVER:
6334 case CCISS_GETDRIVVER:
6335 case CCISS_REVALIDVOLS:
6336 case CCISS_DEREGDISK:
6337 case CCISS_REGNEWDISK:
6338 case CCISS_REGNEWD:
6339 case CCISS_RESCANDISK:
6340 case CCISS_GETLUNINFO:
6341 return hpsa_ioctl(dev, cmd, arg);
6342
6343 case CCISS_PASSTHRU32:
6344 return hpsa_ioctl32_passthru(dev, cmd, arg);
6345 case CCISS_BIG_PASSTHRU32:
6346 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
6347
6348 default:
6349 return -ENOIOCTLCMD;
6350 }
6351}
edd16368
SC		 6352#endif
6353
6354static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
6355{
6356 struct hpsa_pci_info pciinfo;
6357
6358 if (!argp)
6359 return -EINVAL;
6360 pciinfo.domain = pci_domain_nr(h->pdev->bus);
6361 pciinfo.bus = h->pdev->bus->number;
6362 pciinfo.dev_fn = h->pdev->devfn;
6363 pciinfo.board_id = h->board_id;
6364 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
6365 return -EFAULT;
6366 return 0;
6367}
6368
6369static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
6370{
6371 DriverVer_type DriverVer;
6372 unsigned char vmaj, vmin, vsubmin;
6373 int rc;
6374
6375 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
6376 &vmaj, &vmin, &vsubmin);
6377 if (rc != 3) {
6378 dev_info(&h->pdev->dev, "driver version string '%s' "
6379 "unrecognized.", HPSA_DRIVER_VERSION);
6380 vmaj = 0;
6381 vmin = 0;
6382 vsubmin = 0;
6383 }
6384 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
6385 if (!argp)
6386 return -EINVAL;
6387 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
6388 return -EFAULT;
6389 return 0;
6390}
6391
6392static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6393{
6394 IOCTL_Command_struct iocommand;
6395 struct CommandList *c;
6396 char *buff = NULL;
50a0decf 6397 u64 temp64;
c1f63c8f 6398 int rc = 0;
edd16368
SC		 6399
6400 if (!argp)
6401 return -EINVAL;
6402 if (!capable(CAP_SYS_RAWIO))
6403 return -EPERM;
6404 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
6405 return -EFAULT;
6406 if ((iocommand.buf_size < 1) &&
6407 (iocommand.Request.Type.Direction != XFER_NONE)) {
6408 return -EINVAL;
6409 }
6410 if (iocommand.buf_size > 0) {
6411 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
6412 if (buff == NULL)
2dd02d74 6413 return -ENOMEM;
9233fb10 6414 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 6415 /* Copy the data into the buffer we created */
6416 if (copy_from_user(buff, iocommand.buf,
6417 iocommand.buf_size)) {
c1f63c8f
SC		 6418 rc = -EFAULT;
6419 goto out_kfree;
b03a7771
SC		 6420 }
6421 } else {
6422 memset(buff, 0, iocommand.buf_size);
edd16368 6423 }
b03a7771 6424 }
45fcb86e 6425 c = cmd_alloc(h);
bf43caf3 6426
edd16368
SC		 6427 /* Fill in the command type */
6428 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6429 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6430 /* Fill in Command Header */
6431 c->Header.ReplyQueue = 0; /* unused in simple mode */
6432 if (iocommand.buf_size > 0) { /* buffer to fill */
6433 c->Header.SGList = 1;
50a0decf 6434 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6435 } else { /* no buffers to fill */
6436 c->Header.SGList = 0;
50a0decf 6437 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 6438 }
6439 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6440
6441 /* Fill in Request block */
6442 memcpy(&c->Request, &iocommand.Request,
6443 sizeof(c->Request));
6444
6445 /* Fill in the scatter gather information */
6446 if (iocommand.buf_size > 0) {
50a0decf 6447 temp64 = pci_map_single(h->pdev, buff,
edd16368 6448 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6449 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
6450 c->SG[0].Addr = cpu_to_le64(0);
6451 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 6452 rc = -ENOMEM;
6453 goto out;
6454 }
50a0decf
SC		 6455 c->SG[0].Addr = cpu_to_le64(temp64);
6456 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
6457 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 6458 }
c448ecfa
DB		 6459 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
6460 DEFAULT_TIMEOUT);
c2dd32e0
SC		 6461 if (iocommand.buf_size > 0)
6462 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 6463 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6464 if (rc) {
6465 rc = -EIO;
6466 goto out;
6467 }
edd16368
SC		 6468
6469 /* Copy the error information out */
6470 memcpy(&iocommand.error_info, c->err_info,
6471 sizeof(iocommand.error_info));
6472 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 6473 rc = -EFAULT;
6474 goto out;
edd16368 6475 }
9233fb10 6476 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 6477 iocommand.buf_size > 0) {
edd16368
SC		 6478 /* Copy the data out of the buffer we created */
6479 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 6480 rc = -EFAULT;
6481 goto out;
edd16368
SC		 6482 }
6483 }
c1f63c8f 6484out:
45fcb86e 6485 cmd_free(h, c);
c1f63c8f
SC		 6486out_kfree:
6487 kfree(buff);
6488 return rc;
edd16368
SC		 6489}
6490
6491static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6492{
6493 BIG_IOCTL_Command_struct *ioc;
6494 struct CommandList *c;
6495 unsigned char **buff = NULL;
6496 int *buff_size = NULL;
50a0decf 6497 u64 temp64;
edd16368
SC		 6498 BYTE sg_used = 0;
6499 int status = 0;
01a02ffc
SC		 6500 u32 left;
6501 u32 sz;
edd16368
SC		 6502 BYTE __user *data_ptr;
6503
6504 if (!argp)
6505 return -EINVAL;
6506 if (!capable(CAP_SYS_RAWIO))
6507 return -EPERM;
6508 ioc = (BIG_IOCTL_Command_struct *)
6509 kmalloc(sizeof(*ioc), GFP_KERNEL);
6510 if (!ioc) {
6511 status = -ENOMEM;
6512 goto cleanup1;
6513 }
6514 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
6515 status = -EFAULT;
6516 goto cleanup1;
6517 }
6518 if ((ioc->buf_size < 1) &&
6519 (ioc->Request.Type.Direction != XFER_NONE)) {
6520 status = -EINVAL;
6521 goto cleanup1;
6522 }
6523 /* Check kmalloc limits using all SGs */
6524 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
6525 status = -EINVAL;
6526 goto cleanup1;
6527 }
d66ae08b 6528 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 6529 status = -EINVAL;
6530 goto cleanup1;
6531 }
d66ae08b 6532 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 6533 if (!buff) {
6534 status = -ENOMEM;
6535 goto cleanup1;
6536 }
d66ae08b 6537 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 6538 if (!buff_size) {
6539 status = -ENOMEM;
6540 goto cleanup1;
6541 }
6542 left = ioc->buf_size;
6543 data_ptr = ioc->buf;
6544 while (left) {
6545 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6546 buff_size[sg_used] = sz;
6547 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6548 if (buff[sg_used] == NULL) {
6549 status = -ENOMEM;
6550 goto cleanup1;
6551 }
9233fb10 6552 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 6553 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 6554 status = -EFAULT;
edd16368
SC		 6555 goto cleanup1;
6556 }
6557 } else
6558 memset(buff[sg_used], 0, sz);
6559 left -= sz;
6560 data_ptr += sz;
6561 sg_used++;
6562 }
45fcb86e 6563 c = cmd_alloc(h);
bf43caf3 6564
edd16368 6565 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6566 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368 6567 c->Header.ReplyQueue = 0;
50a0decf
SC		 6568 c->Header.SGList = (u8) sg_used;
6569 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 6570 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6571 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6572 if (ioc->buf_size > 0) {
6573 int i;
6574 for (i = 0; i < sg_used; i++) {
50a0decf 6575 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 6576 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6577 if (dma_mapping_error(&h->pdev->dev,
6578 (dma_addr_t) temp64)) {
6579 c->SG[i].Addr = cpu_to_le64(0);
6580 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 6581 hpsa_pci_unmap(h->pdev, c, i,
6582 PCI_DMA_BIDIRECTIONAL);
6583 status = -ENOMEM;
e2d4a1f6 6584 goto cleanup0;
bcc48ffa 6585 }
50a0decf
SC		 6586 c->SG[i].Addr = cpu_to_le64(temp64);
6587 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6588 c->SG[i].Ext = cpu_to_le32(0);
edd16368 6589 }
50a0decf 6590 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 6591 }
c448ecfa
DB		 6592 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
6593 DEFAULT_TIMEOUT);
b03a7771
SC		 6594 if (sg_used)
6595 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 6596 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6597 if (status) {
6598 status = -EIO;
6599 goto cleanup0;
6600 }
6601
edd16368
SC		 6602 /* Copy the error information out */
6603 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6604 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 6605 status = -EFAULT;
e2d4a1f6 6606 goto cleanup0;
edd16368 6607 }
9233fb10 6608 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 6609 int i;
6610
edd16368
SC		 6611 /* Copy the data out of the buffer we created */
6612 BYTE __user *ptr = ioc->buf;
6613 for (i = 0; i < sg_used; i++) {
6614 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 6615 status = -EFAULT;
e2d4a1f6 6616 goto cleanup0;
edd16368
SC		 6617 }
6618 ptr += buff_size[i];
6619 }
6620 }
edd16368 6621 status = 0;
e2d4a1f6 6622cleanup0:
45fcb86e 6623 cmd_free(h, c);
edd16368
SC		 6624cleanup1:
6625 if (buff) {
2b08b3e9
DB		 6626 int i;
6627
edd16368
SC		 6628 for (i = 0; i < sg_used; i++)
6629 kfree(buff[i]);
6630 kfree(buff);
6631 }
6632 kfree(buff_size);
6633 kfree(ioc);
6634 return status;
6635}
6636
6637static void check_ioctl_unit_attention(struct ctlr_info *h,
6638 struct CommandList *c)
6639{
6640 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6641 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6642 (void) check_for_unit_attention(h, c);
6643}
0390f0c0 6644
edd16368
SC		 6645/*
6646 * ioctl
6647 */
42a91641 6648static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 6649{
6650 struct ctlr_info *h;
6651 void __user *argp = (void __user *)arg;
0390f0c0 6652 int rc;
edd16368
SC		 6653
6654 h = sdev_to_hba(dev);
6655
6656 switch (cmd) {
6657 case CCISS_DEREGDISK:
6658 case CCISS_REGNEWDISK:
6659 case CCISS_REGNEWD:
a08a8471 6660 hpsa_scan_start(h->scsi_host);
edd16368
SC		 6661 return 0;
6662 case CCISS_GETPCIINFO:
6663 return hpsa_getpciinfo_ioctl(h, argp);
6664 case CCISS_GETDRIVVER:
6665 return hpsa_getdrivver_ioctl(h, argp);
6666 case CCISS_PASSTHRU:
34f0c627 6667 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6668 return -EAGAIN;
6669 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 6670 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6671 return rc;
edd16368 6672 case CCISS_BIG_PASSTHRU:
34f0c627 6673 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6674 return -EAGAIN;
6675 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 6676 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6677 return rc;
edd16368
SC		 6678 default:
6679 return -ENOTTY;
6680 }
6681}
6682
bf43caf3 6683static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6f039790 6684 u8 reset_type)
64670ac8
SC		 6685{
6686 struct CommandList *c;
6687
6688 c = cmd_alloc(h);
bf43caf3 6689
a2dac136
SC		 6690 /* fill_cmd can't fail here, no data buffer to map */
6691 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 6692 RAID_CTLR_LUNID, TYPE_MSG);
6693 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6694 c->waiting = NULL;
6695 enqueue_cmd_and_start_io(h, c);
6696 /* Don't wait for completion, the reset won't complete. Don't free
6697 * the command either. This is the last command we will send before
6698 * re-initializing everything, so it doesn't matter and won't leak.
6699 */
bf43caf3 6700 return;
64670ac8
SC		 6701}
6702
a2dac136 6703static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 6704 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 6705 int cmd_type)
6706{
6707 int pci_dir = XFER_NONE;
9b5c48c2 6708 u64 tag; /* for commands to be aborted */
edd16368
SC		 6709
6710 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6711 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6712 c->Header.ReplyQueue = 0;
6713 if (buff != NULL && size > 0) {
6714 c->Header.SGList = 1;
50a0decf 6715 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6716 } else {
6717 c->Header.SGList = 0;
50a0decf 6718 c->Header.SGTotal = cpu_to_le16(0);
edd16368 6719 }
edd16368
SC		 6720 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6721
edd16368
SC		 6722 if (cmd_type == TYPE_CMD) {
6723 switch (cmd) {
6724 case HPSA_INQUIRY:
6725 /* are we trying to read a vital product page */
b7bb24eb 6726 if (page_code & VPD_PAGE) {
edd16368 6727 c->Request.CDB[1] = 0x01;
b7bb24eb 6728 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 6729 }
6730 c->Request.CDBLen = 6;
a505b86f
SC		 6731 c->Request.type_attr_dir =
6732 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6733 c->Request.Timeout = 0;
6734 c->Request.CDB[0] = HPSA_INQUIRY;
6735 c->Request.CDB[4] = size & 0xFF;
6736 break;
6737 case HPSA_REPORT_LOG:
6738 case HPSA_REPORT_PHYS:
6739 /* Talking to controller so It's a physical command
6740 mode = 00 target = 0. Nothing to write.
6741 */
6742 c->Request.CDBLen = 12;
a505b86f
SC		 6743 c->Request.type_attr_dir =
6744 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6745 c->Request.Timeout = 0;
6746 c->Request.CDB[0] = cmd;
6747 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6748 c->Request.CDB[7] = (size >> 16) & 0xFF;
6749 c->Request.CDB[8] = (size >> 8) & 0xFF;
6750 c->Request.CDB[9] = size & 0xFF;
6751 break;
c2adae44
ST		 6752 case BMIC_SENSE_DIAG_OPTIONS:
6753 c->Request.CDBLen = 16;
6754 c->Request.type_attr_dir =
6755 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6756 c->Request.Timeout = 0;
6757 /* Spec says this should be BMIC_WRITE */
6758 c->Request.CDB[0] = BMIC_READ;
6759 c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS;
6760 break;
6761 case BMIC_SET_DIAG_OPTIONS:
6762 c->Request.CDBLen = 16;
6763 c->Request.type_attr_dir =
6764 TYPE_ATTR_DIR(cmd_type,
6765 ATTR_SIMPLE, XFER_WRITE);
6766 c->Request.Timeout = 0;
6767 c->Request.CDB[0] = BMIC_WRITE;
6768 c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS;
6769 break;
edd16368
SC		 6770 case HPSA_CACHE_FLUSH:
6771 c->Request.CDBLen = 12;
a505b86f
SC		 6772 c->Request.type_attr_dir =
6773 TYPE_ATTR_DIR(cmd_type,
6774 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 6775 c->Request.Timeout = 0;
6776 c->Request.CDB[0] = BMIC_WRITE;
6777 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 6778 c->Request.CDB[7] = (size >> 8) & 0xFF;
6779 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 6780 break;
6781 case TEST_UNIT_READY:
6782 c->Request.CDBLen = 6;
a505b86f
SC		 6783 c->Request.type_attr_dir =
6784 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 6785 c->Request.Timeout = 0;
6786 break;
283b4a9b
SC		 6787 case HPSA_GET_RAID_MAP:
6788 c->Request.CDBLen = 12;
a505b86f
SC		 6789 c->Request.type_attr_dir =
6790 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 6791 c->Request.Timeout = 0;
6792 c->Request.CDB[0] = HPSA_CISS_READ;
6793 c->Request.CDB[1] = cmd;
6794 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6795 c->Request.CDB[7] = (size >> 16) & 0xFF;
6796 c->Request.CDB[8] = (size >> 8) & 0xFF;
6797 c->Request.CDB[9] = size & 0xFF;
6798 break;
316b221a
SC		 6799 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6800 c->Request.CDBLen = 10;
a505b86f
SC		 6801 c->Request.type_attr_dir =
6802 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 6803 c->Request.Timeout = 0;
6804 c->Request.CDB[0] = BMIC_READ;
6805 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6806 c->Request.CDB[7] = (size >> 16) & 0xFF;
6807 c->Request.CDB[8] = (size >> 8) & 0xFF;
6808 break;
03383736
DB		 6809 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6810 c->Request.CDBLen = 10;
6811 c->Request.type_attr_dir =
6812 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6813 c->Request.Timeout = 0;
6814 c->Request.CDB[0] = BMIC_READ;
6815 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6816 c->Request.CDB[7] = (size >> 16) & 0xFF;
6817 c->Request.CDB[8] = (size >> 8) & 0XFF;
6818 break;
d04e62b9
KB		 6819 case BMIC_SENSE_SUBSYSTEM_INFORMATION:
6820 c->Request.CDBLen = 10;
6821 c->Request.type_attr_dir =
6822 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6823 c->Request.Timeout = 0;
6824 c->Request.CDB[0] = BMIC_READ;
6825 c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION;
6826 c->Request.CDB[7] = (size >> 16) & 0xFF;
6827 c->Request.CDB[8] = (size >> 8) & 0XFF;
6828 break;
cca8f13b
DB		 6829 case BMIC_SENSE_STORAGE_BOX_PARAMS:
6830 c->Request.CDBLen = 10;
6831 c->Request.type_attr_dir =
6832 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6833 c->Request.Timeout = 0;
6834 c->Request.CDB[0] = BMIC_READ;
6835 c->Request.CDB[6] = BMIC_SENSE_STORAGE_BOX_PARAMS;
6836 c->Request.CDB[7] = (size >> 16) & 0xFF;
6837 c->Request.CDB[8] = (size >> 8) & 0XFF;
6838 break;
66749d0d
ST		 6839 case BMIC_IDENTIFY_CONTROLLER:
6840 c->Request.CDBLen = 10;
6841 c->Request.type_attr_dir =
6842 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6843 c->Request.Timeout = 0;
6844 c->Request.CDB[0] = BMIC_READ;
6845 c->Request.CDB[1] = 0;
6846 c->Request.CDB[2] = 0;
6847 c->Request.CDB[3] = 0;
6848 c->Request.CDB[4] = 0;
6849 c->Request.CDB[5] = 0;
6850 c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER;
6851 c->Request.CDB[7] = (size >> 16) & 0xFF;
6852 c->Request.CDB[8] = (size >> 8) & 0XFF;
6853 c->Request.CDB[9] = 0;
6854 break;
edd16368
SC		 6855 default:
6856 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6857 BUG();
a2dac136 6858 return -1;
edd16368
SC		 6859 }
6860 } else if (cmd_type == TYPE_MSG) {
6861 switch (cmd) {
6862
0b9b7b6e
ST		 6863 case HPSA_PHYS_TARGET_RESET:
6864 c->Request.CDBLen = 16;
6865 c->Request.type_attr_dir =
6866 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
6867 c->Request.Timeout = 0; /* Don't time out */
6868 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6869 c->Request.CDB[0] = HPSA_RESET;
6870 c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE;
6871 /* Physical target reset needs no control bytes 4-7*/
6872 c->Request.CDB[4] = 0x00;
6873 c->Request.CDB[5] = 0x00;
6874 c->Request.CDB[6] = 0x00;
6875 c->Request.CDB[7] = 0x00;
6876 break;
edd16368
SC		 6877 case HPSA_DEVICE_RESET_MSG:
6878 c->Request.CDBLen = 16;
a505b86f
SC		 6879 c->Request.type_attr_dir =
6880 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 6881 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 6882 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6883 c->Request.CDB[0] = cmd;
21e89afd 6884 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 6885 /* If bytes 4-7 are zero, it means reset the */
6886 /* LunID device */
6887 c->Request.CDB[4] = 0x00;
6888 c->Request.CDB[5] = 0x00;
6889 c->Request.CDB[6] = 0x00;
6890 c->Request.CDB[7] = 0x00;
75167d2c
SC		 6891 break;
6892 case HPSA_ABORT_MSG:
9b5c48c2 6893 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 6894 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 6895 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
6896 tag, c->Header.tag);
75167d2c 6897 c->Request.CDBLen = 16;
a505b86f
SC		 6898 c->Request.type_attr_dir =
6899 TYPE_ATTR_DIR(cmd_type,
6900 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 6901 c->Request.Timeout = 0; /* Don't time out */
6902 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
6903 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
6904 c->Request.CDB[2] = 0x00; /* reserved */
6905 c->Request.CDB[3] = 0x00; /* reserved */
6906 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 6907 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 6908 c->Request.CDB[12] = 0x00; /* reserved */
6909 c->Request.CDB[13] = 0x00; /* reserved */
6910 c->Request.CDB[14] = 0x00; /* reserved */
6911 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 6912 break;
edd16368
SC		 6913 default:
6914 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6915 cmd);
6916 BUG();
6917 }
6918 } else {
6919 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6920 BUG();
6921 }
6922
a505b86f 6923 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 6924 case XFER_READ:
6925 pci_dir = PCI_DMA_FROMDEVICE;
6926 break;
6927 case XFER_WRITE:
6928 pci_dir = PCI_DMA_TODEVICE;
6929 break;
6930 case XFER_NONE:
6931 pci_dir = PCI_DMA_NONE;
6932 break;
6933 default:
6934 pci_dir = PCI_DMA_BIDIRECTIONAL;
6935 }
a2dac136
SC		 6936 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
6937 return -1;
6938 return 0;
edd16368
SC		 6939}
6940
6941/*
6942 * Map (physical) PCI mem into (virtual) kernel space
6943 */
6944static void __iomem *remap_pci_mem(ulong base, ulong size)
6945{
6946 ulong page_base = ((ulong) base) & PAGE_MASK;
6947 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 6948 void __iomem *page_remapped = ioremap_nocache(page_base,
6949 page_offs + size);
edd16368
SC		 6950
6951 return page_remapped ? (page_remapped + page_offs) : NULL;
6952}
6953
254f796b 6954static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 6955{
254f796b 6956 return h->access.command_completed(h, q);
edd16368
SC		 6957}
6958
900c5440 6959static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 6960{
6961 return h->access.intr_pending(h);
6962}
6963
6964static inline long interrupt_not_for_us(struct ctlr_info *h)
6965{
10f66018
SC		 6966 return (h->access.intr_pending(h) == 0) ||
6967 (h->interrupts_enabled == 0);
edd16368
SC		 6968}
6969
01a02ffc
SC		 6970static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6971 u32 raw_tag)
edd16368
SC		 6972{
6973 if (unlikely(tag_index >= h->nr_cmds)) {
6974 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6975 return 1;
6976 }
6977 return 0;
6978}
6979
5a3d16f5 6980static inline void finish_cmd(struct CommandList *c)
edd16368 6981{
e85c5974 6982 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 6983 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6984 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 6985 complete_scsi_command(c);
8be986cc 6986 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
edd16368 6987 complete(c->waiting);
a104c99f
SC		 6988}
6989
303932fd 6990/* process completion of an indexed ("direct lookup") command */
1d94f94d 6991static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 6992 u32 raw_tag)
6993{
6994 u32 tag_index;
6995 struct CommandList *c;
6996
f2405db8 6997 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 6998 if (!bad_tag(h, tag_index, raw_tag)) {
6999 c = h->cmd_pool + tag_index;
7000 finish_cmd(c);
7001 }
303932fd
DB		 7002}
7003
64670ac8
SC		 7004/* Some controllers, like p400, will give us one interrupt
7005 * after a soft reset, even if we turned interrupts off.
7006 * Only need to check for this in the hpsa_xxx_discard_completions
7007 * functions.
7008 */
7009static int ignore_bogus_interrupt(struct ctlr_info *h)
7010{
7011 if (likely(!reset_devices))
7012 return 0;
7013
7014 if (likely(h->interrupts_enabled))
7015 return 0;
7016
7017 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
7018 "(known firmware bug.) Ignoring.\n");
7019
7020 return 1;
7021}
7022
254f796b
MG		 7023/*
7024 * Convert &h->q[x] (passed to interrupt handlers) back to h.
7025 * Relies on (h-q[x] == x) being true for x such that
7026 * 0 <= x < MAX_REPLY_QUEUES.
7027 */
7028static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 7029{
254f796b
MG		 7030 return container_of((queue - *queue), struct ctlr_info, q[0]);
7031}
7032
7033static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
7034{
7035 struct ctlr_info *h = queue_to_hba(queue);
7036 u8 q = *(u8 *) queue;
64670ac8
SC		 7037 u32 raw_tag;
7038
7039 if (ignore_bogus_interrupt(h))
7040 return IRQ_NONE;
7041
7042 if (interrupt_not_for_us(h))
7043 return IRQ_NONE;
a0c12413 7044 h->last_intr_timestamp = get_jiffies_64();
64670ac8 7045 while (interrupt_pending(h)) {
254f796b 7046 raw_tag = get_next_completion(h, q);
64670ac8 7047 while (raw_tag != FIFO_EMPTY)
254f796b 7048 raw_tag = next_command(h, q);
64670ac8 7049 }
64670ac8
SC		 7050 return IRQ_HANDLED;
7051}
7052
254f796b 7053static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 7054{
254f796b 7055 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 7056 u32 raw_tag;
254f796b 7057 u8 q = *(u8 *) queue;
64670ac8
SC		 7058
7059 if (ignore_bogus_interrupt(h))
7060 return IRQ_NONE;
7061
a0c12413 7062 h->last_intr_timestamp = get_jiffies_64();
254f796b 7063 raw_tag = get_next_completion(h, q);
64670ac8 7064 while (raw_tag != FIFO_EMPTY)
254f796b 7065 raw_tag = next_command(h, q);
64670ac8
SC		 7066 return IRQ_HANDLED;
7067}
7068
254f796b 7069static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 7070{
254f796b 7071 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 7072 u32 raw_tag;
254f796b 7073 u8 q = *(u8 *) queue;
edd16368
SC		 7074
7075 if (interrupt_not_for_us(h))
7076 return IRQ_NONE;
a0c12413 7077 h->last_intr_timestamp = get_jiffies_64();
10f66018 7078 while (interrupt_pending(h)) {
254f796b 7079 raw_tag = get_next_completion(h, q);
10f66018 7080 while (raw_tag != FIFO_EMPTY) {
f2405db8 7081 process_indexed_cmd(h, raw_tag);
254f796b 7082 raw_tag = next_command(h, q);
10f66018
SC		 7083 }
7084 }
10f66018
SC		 7085 return IRQ_HANDLED;
7086}
7087
254f796b 7088static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 7089{
254f796b 7090 struct ctlr_info *h = queue_to_hba(queue);
10f66018 7091 u32 raw_tag;
254f796b 7092 u8 q = *(u8 *) queue;
10f66018 7093
a0c12413 7094 h->last_intr_timestamp = get_jiffies_64();
254f796b 7095 raw_tag = get_next_completion(h, q);
303932fd 7096 while (raw_tag != FIFO_EMPTY) {
f2405db8 7097 process_indexed_cmd(h, raw_tag);
254f796b 7098 raw_tag = next_command(h, q);
edd16368 7099 }
edd16368
SC		 7100 return IRQ_HANDLED;
7101}
7102
a9a3a273
SC		 7103/* Send a message CDB to the firmware. Careful, this only works
7104 * in simple mode, not performant mode due to the tag lookup.
7105 * We only ever use this immediately after a controller reset.
7106 */
6f039790
GKH		 7107static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
7108 unsigned char type)
edd16368
SC		 7109{
7110 struct Command {
7111 struct CommandListHeader CommandHeader;
7112 struct RequestBlock Request;
7113 struct ErrDescriptor ErrorDescriptor;
7114 };
7115 struct Command *cmd;
7116 static const size_t cmd_sz = sizeof(*cmd) +
7117 sizeof(cmd->ErrorDescriptor);
7118 dma_addr_t paddr64;
2b08b3e9
DB		 7119 __le32 paddr32;
7120 u32 tag;
edd16368
SC		 7121 void __iomem *vaddr;
7122 int i, err;
7123
7124 vaddr = pci_ioremap_bar(pdev, 0);
7125 if (vaddr == NULL)
7126 return -ENOMEM;
7127
7128 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
7129 * CCISS commands, so they must be allocated from the lower 4GiB of
7130 * memory.
7131 */
7132 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
7133 if (err) {
7134 iounmap(vaddr);
1eaec8f3 7135 return err;
edd16368
SC		 7136 }
7137
7138 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
7139 if (cmd == NULL) {
7140 iounmap(vaddr);
7141 return -ENOMEM;
7142 }
7143
7144 /* This must fit, because of the 32-bit consistent DMA mask. Also,
7145 * although there's no guarantee, we assume that the address is at
7146 * least 4-byte aligned (most likely, it's page-aligned).
7147 */
2b08b3e9 7148 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 7149
7150 cmd->CommandHeader.ReplyQueue = 0;
7151 cmd->CommandHeader.SGList = 0;
50a0decf 7152 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 7153 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 7154 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
7155
7156 cmd->Request.CDBLen = 16;
a505b86f
SC		 7157 cmd->Request.type_attr_dir =
7158 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 7159 cmd->Request.Timeout = 0; /* Don't time out */
7160 cmd->Request.CDB[0] = opcode;
7161 cmd->Request.CDB[1] = type;
7162 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 7163 cmd->ErrorDescriptor.Addr =
2b08b3e9 7164 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 7165 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 7166
2b08b3e9 7167 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 7168
7169 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
7170 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 7171 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 7172 break;
7173 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
7174 }
7175
7176 iounmap(vaddr);
7177
7178 /* we leak the DMA buffer here ... no choice since the controller could
7179 * still complete the command.
7180 */
7181 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
7182 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
7183 opcode, type);
7184 return -ETIMEDOUT;
7185 }
7186
7187 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
7188
7189 if (tag & HPSA_ERROR_BIT) {
7190 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
7191 opcode, type);
7192 return -EIO;
7193 }
7194
7195 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
7196 opcode, type);
7197 return 0;
7198}
7199
edd16368
SC		 7200#define hpsa_noop(p) hpsa_message(p, 3, 0)
7201
1df8552a 7202static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 7203 void __iomem *vaddr, u32 use_doorbell)
1df8552a 7204{
1df8552a
SC		 7205
7206 if (use_doorbell) {
7207 /* For everything after the P600, the PCI power state method
7208 * of resetting the controller doesn't work, so we have this
7209 * other way using the doorbell register.
7210 */
7211 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 7212 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 7213
00701a96 7214 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 7215 * doorbell reset and before any attempt to talk to the board
7216 * at all to ensure that this actually works and doesn't fall
7217 * over in some weird corner cases.
7218 */
00701a96 7219 msleep(10000);
1df8552a
SC		 7220 } else { /* Try to do it the PCI power state way */
7221
7222 /* Quoting from the Open CISS Specification: "The Power
7223 * Management Control/Status Register (CSR) controls the power
7224 * state of the device. The normal operating state is D0,
7225 * CSR=00h. The software off state is D3, CSR=03h. To reset
7226 * the controller, place the interface device in D3 then to D0,
7227 * this causes a secondary PCI reset which will reset the
7228 * controller." */
2662cab8
DB		 7229
7230 int rc = 0;
7231
1df8552a 7232 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 7233
1df8552a 7234 /* enter the D3hot power management state */
2662cab8
DB		 7235 rc = pci_set_power_state(pdev, PCI_D3hot);
7236 if (rc)
7237 return rc;
1df8552a
SC		 7238
7239 msleep(500);
7240
7241 /* enter the D0 power management state */
2662cab8
DB		 7242 rc = pci_set_power_state(pdev, PCI_D0);
7243 if (rc)
7244 return rc;
c4853efe
MM		 7245
7246 /*
7247 * The P600 requires a small delay when changing states.
7248 * Otherwise we may think the board did not reset and we bail.
7249 * This for kdump only and is particular to the P600.
7250 */
7251 msleep(500);
1df8552a
SC		 7252 }
7253 return 0;
7254}
7255
6f039790 7256static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 7257{
7258 memset(driver_version, 0, len);
f79cfec6 7259 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 7260}
7261
6f039790 7262static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 7263{
7264 char *driver_version;
7265 int i, size = sizeof(cfgtable->driver_version);
7266
7267 driver_version = kmalloc(size, GFP_KERNEL);
7268 if (!driver_version)
7269 return -ENOMEM;
7270
7271 init_driver_version(driver_version, size);
7272 for (i = 0; i < size; i++)
7273 writeb(driver_version[i], &cfgtable->driver_version[i]);
7274 kfree(driver_version);
7275 return 0;
7276}
7277
6f039790
GKH		 7278static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
7279 unsigned char *driver_ver)
580ada3c
SC		 7280{
7281 int i;
7282
7283 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
7284 driver_ver[i] = readb(&cfgtable->driver_version[i]);
7285}
7286
6f039790 7287static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 7288{
7289
7290 char *driver_ver, *old_driver_ver;
7291 int rc, size = sizeof(cfgtable->driver_version);
7292
7293 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
7294 if (!old_driver_ver)
7295 return -ENOMEM;
7296 driver_ver = old_driver_ver + size;
7297
7298 /* After a reset, the 32 bytes of "driver version" in the cfgtable
7299 * should have been changed, otherwise we know the reset failed.
7300 */
7301 init_driver_version(old_driver_ver, size);
7302 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
7303 rc = !memcmp(driver_ver, old_driver_ver, size);
7304 kfree(old_driver_ver);
7305 return rc;
7306}
edd16368 7307/* This does a hard reset of the controller using PCI power management
1df8552a 7308 * states or the using the doorbell register.
edd16368 7309 */
6b6c1cd7 7310static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 7311{
1df8552a
SC		 7312 u64 cfg_offset;
7313 u32 cfg_base_addr;
7314 u64 cfg_base_addr_index;
7315 void __iomem *vaddr;
7316 unsigned long paddr;
580ada3c 7317 u32 misc_fw_support;
270d05de 7318 int rc;
1df8552a 7319 struct CfgTable __iomem *cfgtable;
cf0b08d0 7320 u32 use_doorbell;
270d05de 7321 u16 command_register;
edd16368 7322
1df8552a
SC		 7323 /* For controllers as old as the P600, this is very nearly
7324 * the same thing as
edd16368
SC		 7325 *
7326 * pci_save_state(pci_dev);
7327 * pci_set_power_state(pci_dev, PCI_D3hot);
7328 * pci_set_power_state(pci_dev, PCI_D0);
7329 * pci_restore_state(pci_dev);
7330 *
1df8552a
SC		 7331 * For controllers newer than the P600, the pci power state
7332 * method of resetting doesn't work so we have another way
7333 * using the doorbell register.
edd16368 7334 */
18867659 7335
60f923b9
RE		 7336 if (!ctlr_is_resettable(board_id)) {
7337 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 7338 return -ENODEV;
7339 }
46380786
SC		 7340
7341 /* if controller is soft- but not hard resettable... */
7342 if (!ctlr_is_hard_resettable(board_id))
7343 return -ENOTSUPP; /* try soft reset later. */
18867659 7344
270d05de
SC		 7345 /* Save the PCI command register */
7346 pci_read_config_word(pdev, 4, &command_register);
270d05de 7347 pci_save_state(pdev);
edd16368 7348
1df8552a
SC		 7349 /* find the first memory BAR, so we can find the cfg table */
7350 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
7351 if (rc)
7352 return rc;
7353 vaddr = remap_pci_mem(paddr, 0x250);
7354 if (!vaddr)
7355 return -ENOMEM;
edd16368 7356
1df8552a
SC		 7357 /* find cfgtable in order to check if reset via doorbell is supported */
7358 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
7359 &cfg_base_addr_index, &cfg_offset);
7360 if (rc)
7361 goto unmap_vaddr;
7362 cfgtable = remap_pci_mem(pci_resource_start(pdev,
7363 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
7364 if (!cfgtable) {
7365 rc = -ENOMEM;
7366 goto unmap_vaddr;
7367 }
580ada3c
SC		 7368 rc = write_driver_ver_to_cfgtable(cfgtable);
7369 if (rc)
03741d95 7370 goto unmap_cfgtable;
edd16368 7371
cf0b08d0
SC		 7372 /* If reset via doorbell register is supported, use that.
7373 * There are two such methods. Favor the newest method.
7374 */
1df8552a 7375 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 7376 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
7377 if (use_doorbell) {
7378 use_doorbell = DOORBELL_CTLR_RESET2;
7379 } else {
7380 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
7381 if (use_doorbell) {
050f7147
SC		 7382 dev_warn(&pdev->dev,
7383 "Soft reset not supported. Firmware update is required.\n");
64670ac8 7384 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 7385 goto unmap_cfgtable;
7386 }
7387 }
edd16368 7388
1df8552a
SC		 7389 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
7390 if (rc)
7391 goto unmap_cfgtable;
edd16368 7392
270d05de 7393 pci_restore_state(pdev);
270d05de 7394 pci_write_config_word(pdev, 4, command_register);
edd16368 7395
1df8552a
SC		 7396 /* Some devices (notably the HP Smart Array 5i Controller)
7397 need a little pause here */
7398 msleep(HPSA_POST_RESET_PAUSE_MSECS);
7399
fe5389c8
SC		 7400 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
7401 if (rc) {
7402 dev_warn(&pdev->dev,
050f7147 7403 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 7404 goto unmap_cfgtable;
7405 }
fe5389c8 7406
580ada3c
SC		 7407 rc = controller_reset_failed(vaddr);
7408 if (rc < 0)
7409 goto unmap_cfgtable;
7410 if (rc) {
64670ac8
SC		 7411 dev_warn(&pdev->dev, "Unable to successfully reset "
7412 "controller. Will try soft reset.\n");
7413 rc = -ENOTSUPP;
580ada3c 7414 } else {
64670ac8 7415 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 7416 }
7417
7418unmap_cfgtable:
7419 iounmap(cfgtable);
7420
7421unmap_vaddr:
7422 iounmap(vaddr);
7423 return rc;
edd16368
SC		 7424}
7425
7426/*
7427 * We cannot read the structure directly, for portability we must use
7428 * the io functions.
7429 * This is for debug only.
7430 */
42a91641 7431static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 7432{
58f8665c 7433#ifdef HPSA_DEBUG
edd16368
SC		 7434 int i;
7435 char temp_name[17];
7436
7437 dev_info(dev, "Controller Configuration information\n");
7438 dev_info(dev, "------------------------------------\n");
7439 for (i = 0; i < 4; i++)
7440 temp_name[i] = readb(&(tb->Signature[i]));
7441 temp_name[4] = '\0';
7442 dev_info(dev, " Signature = %s\n", temp_name);
7443 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
7444 dev_info(dev, " Transport methods supported = 0x%x\n",
7445 readl(&(tb->TransportSupport)));
7446 dev_info(dev, " Transport methods active = 0x%x\n",
7447 readl(&(tb->TransportActive)));
7448 dev_info(dev, " Requested transport Method = 0x%x\n",
7449 readl(&(tb->HostWrite.TransportRequest)));
7450 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
7451 readl(&(tb->HostWrite.CoalIntDelay)));
7452 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
7453 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 7454 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 7455 readl(&(tb->CmdsOutMax)));
7456 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
7457 for (i = 0; i < 16; i++)
7458 temp_name[i] = readb(&(tb->ServerName[i]));
7459 temp_name[16] = '\0';
7460 dev_info(dev, " Server Name = %s\n", temp_name);
7461 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
7462 readl(&(tb->HeartBeat)));
edd16368 7463#endif /* HPSA_DEBUG */
58f8665c 7464}
edd16368
SC		 7465
7466static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
7467{
7468 int i, offset, mem_type, bar_type;
7469
7470 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
7471 return 0;
7472 offset = 0;
7473 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
7474 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
7475 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
7476 offset += 4;
7477 else {
7478 mem_type = pci_resource_flags(pdev, i) &
7479 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
7480 switch (mem_type) {
7481 case PCI_BASE_ADDRESS_MEM_TYPE_32:
7482 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
7483 offset += 4; /* 32 bit */
7484 break;
7485 case PCI_BASE_ADDRESS_MEM_TYPE_64:
7486 offset += 8;
7487 break;
7488 default: /* reserved in PCI 2.2 */
7489 dev_warn(&pdev->dev,
7490 "base address is invalid\n");
7491 return -1;
7492 break;
7493 }
7494 }
7495 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
7496 return i + 1;
7497 }
7498 return -1;
7499}
7500
cc64c817
RE		 7501static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
7502{
7503 if (h->msix_vector) {
7504 if (h->pdev->msix_enabled)
7505 pci_disable_msix(h->pdev);
105a3dbc 7506 h->msix_vector = 0;
cc64c817
RE		 7507 } else if (h->msi_vector) {
7508 if (h->pdev->msi_enabled)
7509 pci_disable_msi(h->pdev);
105a3dbc 7510 h->msi_vector = 0;
cc64c817
RE		 7511 }
7512}
7513
edd16368 7514/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 7515 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 7516 */
6f039790 7517static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 7518{
7519#ifdef CONFIG_PCI_MSI
254f796b
MG		 7520 int err, i;
7521 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
7522
7523 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
7524 hpsa_msix_entries[i].vector = 0;
7525 hpsa_msix_entries[i].entry = i;
7526 }
edd16368
SC		 7527
7528 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 7529 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
7530 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 7531 goto default_int_mode;
55c06c71 7532 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 7533 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 7534 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 7535 if (h->msix_vector > num_online_cpus())
7536 h->msix_vector = num_online_cpus();
18fce3c4
AG		 7537 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
7538 1, h->msix_vector);
7539 if (err < 0) {
7540 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
7541 h->msix_vector = 0;
7542 goto single_msi_mode;
7543 } else if (err < h->msix_vector) {
55c06c71 7544 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 7545 "available\n", err);
edd16368 7546 }
18fce3c4
AG		 7547 h->msix_vector = err;
7548 for (i = 0; i < h->msix_vector; i++)
7549 h->intr[i] = hpsa_msix_entries[i].vector;
7550 return;
edd16368 7551 }
18fce3c4 7552single_msi_mode:
55c06c71 7553 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 7554 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 7555 if (!pci_enable_msi(h->pdev))
edd16368
SC		 7556 h->msi_vector = 1;
7557 else
55c06c71 7558 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 7559 }
7560default_int_mode:
7561#endif /* CONFIG_PCI_MSI */
7562 /* if we get here we're going to use the default interrupt mode */
a9a3a273 7563 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 7564}
7565
6f039790 7566static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 7567{
7568 int i;
7569 u32 subsystem_vendor_id, subsystem_device_id;
7570
7571 subsystem_vendor_id = pdev->subsystem_vendor;
7572 subsystem_device_id = pdev->subsystem_device;
7573 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
7574 subsystem_vendor_id;
7575
7576 for (i = 0; i < ARRAY_SIZE(products); i++)
7577 if (*board_id == products[i].board_id)
7578 return i;
7579
6798cc0a
SC		 7580 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
7581 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
7582 !hpsa_allow_any) {
e5c880d1
SC		 7583 dev_warn(&pdev->dev, "unrecognized board ID: "
7584 "0x%08x, ignoring.\n", *board_id);
7585 return -ENODEV;
7586 }
7587 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
7588}
7589
6f039790
GKH		 7590static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
7591 unsigned long *memory_bar)
3a7774ce
SC		 7592{
7593 int i;
7594
7595 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 7596 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 7597 /* addressing mode bits already removed */
12d2cd47
SC		 7598 *memory_bar = pci_resource_start(pdev, i);
7599 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 7600 *memory_bar);
7601 return 0;
7602 }
12d2cd47 7603 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 7604 return -ENODEV;
7605}
7606
6f039790
GKH		 7607static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7608 int wait_for_ready)
2c4c8c8b 7609{
fe5389c8 7610 int i, iterations;
2c4c8c8b 7611 u32 scratchpad;
fe5389c8
SC		 7612 if (wait_for_ready)
7613 iterations = HPSA_BOARD_READY_ITERATIONS;
7614 else
7615 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 7616
fe5389c8
SC		 7617 for (i = 0; i < iterations; i++) {
7618 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7619 if (wait_for_ready) {
7620 if (scratchpad == HPSA_FIRMWARE_READY)
7621 return 0;
7622 } else {
7623 if (scratchpad != HPSA_FIRMWARE_READY)
7624 return 0;
7625 }
2c4c8c8b
SC		 7626 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7627 }
fe5389c8 7628 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 7629 return -ENODEV;
7630}
7631
6f039790
GKH		 7632static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7633 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7634 u64 *cfg_offset)
a51fd47f
SC		 7635{
7636 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7637 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7638 *cfg_base_addr &= (u32) 0x0000ffff;
7639 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7640 if (*cfg_base_addr_index == -1) {
7641 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7642 return -ENODEV;
7643 }
7644 return 0;
7645}
7646
195f2c65
RE		 7647static void hpsa_free_cfgtables(struct ctlr_info *h)
7648{
105a3dbc 7649 if (h->transtable) {
195f2c65 7650 iounmap(h->transtable);
105a3dbc
RE		 7651 h->transtable = NULL;
7652 }
7653 if (h->cfgtable) {
195f2c65 7654 iounmap(h->cfgtable);
105a3dbc
RE		 7655 h->cfgtable = NULL;
7656 }
195f2c65
RE		 7657}
7658
7659/* Find and map CISS config table and transfer table
7660+ * several items must be unmapped (freed) later
7661+ * */
6f039790 7662static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 7663{
01a02ffc
SC		 7664 u64 cfg_offset;
7665 u32 cfg_base_addr;
7666 u64 cfg_base_addr_index;
303932fd 7667 u32 trans_offset;
a51fd47f 7668 int rc;
77c4495c 7669
a51fd47f
SC		 7670 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7671 &cfg_base_addr_index, &cfg_offset);
7672 if (rc)
7673 return rc;
77c4495c 7674 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 7675 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 7676 if (!h->cfgtable) {
7677 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 7678 return -ENOMEM;
cd3c81c4 7679 }
580ada3c
SC		 7680 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7681 if (rc)
7682 return rc;
77c4495c 7683 /* Find performant mode table. */
a51fd47f 7684 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 7685 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7686 cfg_base_addr_index)+cfg_offset+trans_offset,
7687 sizeof(*h->transtable));
195f2c65
RE		 7688 if (!h->transtable) {
7689 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7690 hpsa_free_cfgtables(h);
77c4495c 7691 return -ENOMEM;
195f2c65 7692 }
77c4495c
SC		 7693 return 0;
7694}
7695
6f039790 7696static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 7697{
41ce4c35
SC		 7698#define MIN_MAX_COMMANDS 16
7699 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7700
7701 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 7702
7703 /* Limit commands in memory limited kdump scenario. */
7704 if (reset_devices && h->max_commands > 32)
7705 h->max_commands = 32;
7706
41ce4c35
SC		 7707 if (h->max_commands < MIN_MAX_COMMANDS) {
7708 dev_warn(&h->pdev->dev,
7709 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7710 h->max_commands,
7711 MIN_MAX_COMMANDS);
7712 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 7713 }
7714}
7715
c7ee65b3
WS		 7716/* If the controller reports that the total max sg entries is greater than 512,
7717 * then we know that chained SG blocks work. (Original smart arrays did not
7718 * support chained SG blocks and would return zero for max sg entries.)
7719 */
7720static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7721{
7722 return h->maxsgentries > 512;
7723}
7724
b93d7536
SC		 7725/* Interrogate the hardware for some limits:
7726 * max commands, max SG elements without chaining, and with chaining,
7727 * SG chain block size, etc.
7728 */
6f039790 7729static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 7730{
cba3d38b 7731 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 7732 h->nr_cmds = h->max_commands;
b93d7536 7733 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 7734 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 7735 if (hpsa_supports_chained_sg_blocks(h)) {
7736 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 7737 h->max_cmd_sg_entries = 32;
1a63ea6f 7738 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 7739 h->maxsgentries--; /* save one for chain pointer */
7740 } else {
c7ee65b3
WS		 7741 /*
7742 * Original smart arrays supported at most 31 s/g entries
7743 * embedded inline in the command (trying to use more
7744 * would lock up the controller)
7745 */
7746 h->max_cmd_sg_entries = 31;
1a63ea6f 7747 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 7748 h->chainsize = 0;
b93d7536 7749 }
75167d2c
SC		 7750
7751 /* Find out what task management functions are supported and cache */
7752 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 7753 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7754 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7755 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7756 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
8be986cc
SC		 7757 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7758 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
b93d7536
SC		 7759}
7760
76c46e49
SC		 7761static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7762{
0fc9fd40 7763 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 7764 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 7765 return false;
7766 }
7767 return true;
7768}
7769
97a5e98c 7770static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 7771{
97a5e98c 7772 u32 driver_support;
f7c39101 7773
97a5e98c 7774 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 7775 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7776#ifdef CONFIG_X86
97a5e98c 7777 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 7778#endif
28e13446
SC		 7779 driver_support |= ENABLE_UNIT_ATTN;
7780 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 7781}
7782
3d0eab67
SC		 7783/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7784 * in a prefetch beyond physical memory.
7785 */
7786static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7787{
7788 u32 dma_prefetch;
7789
7790 if (h->board_id != 0x3225103C)
7791 return;
7792 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7793 dma_prefetch |= 0x8000;
7794 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7795}
7796
c706a795 7797static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 7798{
7799 int i;
7800 u32 doorbell_value;
7801 unsigned long flags;
7802 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 7803 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 7804 spin_lock_irqsave(&h->lock, flags);
7805 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7806 spin_unlock_irqrestore(&h->lock, flags);
7807 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 7808 goto done;
76438d08 7809 /* delay and try again */
007e7aa9 7810 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 7811 }
c706a795
RE		 7812 return -ENODEV;
7813done:
7814 return 0;
76438d08
SC		 7815}
7816
c706a795 7817static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 7818{
7819 int i;
6eaf46fd
SC		 7820 u32 doorbell_value;
7821 unsigned long flags;
eb6b2ae9
SC		 7822
7823 /* under certain very rare conditions, this can take awhile.
7824 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7825 * as we enter this code.)
7826 */
007e7aa9 7827 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 7828 if (h->remove_in_progress)
7829 goto done;
6eaf46fd
SC		 7830 spin_lock_irqsave(&h->lock, flags);
7831 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7832 spin_unlock_irqrestore(&h->lock, flags);
382be668 7833 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 7834 goto done;
eb6b2ae9 7835 /* delay and try again */
007e7aa9 7836 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 7837 }
c706a795
RE		 7838 return -ENODEV;
7839done:
7840 return 0;
3f4336f3
SC		 7841}
7842
c706a795 7843/* return -ENODEV or other reason on error, 0 on success */
6f039790 7844static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 7845{
7846 u32 trans_support;
7847
7848 trans_support = readl(&(h->cfgtable->TransportSupport));
7849 if (!(trans_support & SIMPLE_MODE))
7850 return -ENOTSUPP;
7851
7852 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 7853
3f4336f3
SC		 7854 /* Update the field, and then ring the doorbell */
7855 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 7856 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 7857 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7858 if (hpsa_wait_for_mode_change_ack(h))
7859 goto error;
eb6b2ae9 7860 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 7861 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7862 goto error;
960a30e7 7863 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 7864 return 0;
283b4a9b 7865error:
050f7147 7866 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 7867 return -ENODEV;
eb6b2ae9
SC		 7868}
7869
195f2c65
RE		 7870/* free items allocated or mapped by hpsa_pci_init */
7871static void hpsa_free_pci_init(struct ctlr_info *h)
7872{
7873 hpsa_free_cfgtables(h); /* pci_init 4 */
7874 iounmap(h->vaddr); /* pci_init 3 */
105a3dbc 7875 h->vaddr = NULL;
195f2c65 7876 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
943a7021
RE		 7877 /*
7878 * call pci_disable_device before pci_release_regions per
7879 * Documentation/PCI/pci.txt
7880 */
195f2c65 7881 pci_disable_device(h->pdev); /* pci_init 1 */
943a7021 7882 pci_release_regions(h->pdev); /* pci_init 2 */
195f2c65
RE		 7883}
7884
7885/* several items must be freed later */
6f039790 7886static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 7887{
eb6b2ae9 7888 int prod_index, err;
edd16368 7889
e5c880d1
SC		 7890 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
7891 if (prod_index < 0)
60f923b9 7892 return prod_index;
e5c880d1
SC		 7893 h->product_name = products[prod_index].product_name;
7894 h->access = *(products[prod_index].access);
edd16368 7895
9b5c48c2
SC		 7896 h->needs_abort_tags_swizzled =
7897 ctlr_needs_abort_tags_swizzled(h->board_id);
7898
e5a44df8
MG		 7899 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7900 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7901
55c06c71 7902 err = pci_enable_device(h->pdev);
edd16368 7903 if (err) {
195f2c65 7904 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
943a7021 7905 pci_disable_device(h->pdev);
edd16368
SC		 7906 return err;
7907 }
7908
f79cfec6 7909 err = pci_request_regions(h->pdev, HPSA);
edd16368 7910 if (err) {
55c06c71 7911 dev_err(&h->pdev->dev,
195f2c65 7912 "failed to obtain PCI resources\n");
943a7021
RE		 7913 pci_disable_device(h->pdev);
7914 return err;
edd16368 7915 }
4fa604e1
RE		 7916
7917 pci_set_master(h->pdev);
7918
6b3f4c52 7919 hpsa_interrupt_mode(h);
12d2cd47 7920 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 7921 if (err)
195f2c65 7922 goto clean2; /* intmode+region, pci */
edd16368 7923 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 7924 if (!h->vaddr) {
195f2c65 7925 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 7926 err = -ENOMEM;
195f2c65 7927 goto clean2; /* intmode+region, pci */
204892e9 7928 }
fe5389c8 7929 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 7930 if (err)
195f2c65 7931 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 7932 err = hpsa_find_cfgtables(h);
7933 if (err)
195f2c65 7934 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 7935 hpsa_find_board_params(h);
edd16368 7936
76c46e49 7937 if (!hpsa_CISS_signature_present(h)) {
edd16368 7938 err = -ENODEV;
195f2c65 7939 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 7940 }
97a5e98c 7941 hpsa_set_driver_support_bits(h);
3d0eab67 7942 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 7943 err = hpsa_enter_simple_mode(h);
7944 if (err)
195f2c65 7945 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 7946 return 0;
7947
195f2c65
RE		 7948clean4: /* cfgtables, vaddr, intmode+region, pci */
7949 hpsa_free_cfgtables(h);
7950clean3: /* vaddr, intmode+region, pci */
7951 iounmap(h->vaddr);
105a3dbc 7952 h->vaddr = NULL;
195f2c65
RE		 7953clean2: /* intmode+region, pci */
7954 hpsa_disable_interrupt_mode(h);
943a7021
RE		 7955 /*
7956 * call pci_disable_device before pci_release_regions per
7957 * Documentation/PCI/pci.txt
7958 */
195f2c65 7959 pci_disable_device(h->pdev);
943a7021 7960 pci_release_regions(h->pdev);
edd16368
SC		 7961 return err;
7962}
7963
6f039790 7964static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 7965{
7966 int rc;
7967
7968#define HBA_INQUIRY_BYTE_COUNT 64
7969 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7970 if (!h->hba_inquiry_data)
7971 return;
7972 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7973 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7974 if (rc != 0) {
7975 kfree(h->hba_inquiry_data);
7976 h->hba_inquiry_data = NULL;
7977 }
7978}
7979
6b6c1cd7 7980static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 7981{
1df8552a 7982 int rc, i;
3b747298 7983 void __iomem *vaddr;
4c2a8c40
SC		 7984
7985 if (!reset_devices)
7986 return 0;
7987
132aa220
TH		 7988 /* kdump kernel is loading, we don't know in which state is
7989 * the pci interface. The dev->enable_cnt is equal zero
7990 * so we call enable+disable, wait a while and switch it on.
7991 */
7992 rc = pci_enable_device(pdev);
7993 if (rc) {
7994 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7995 return -ENODEV;
7996 }
7997 pci_disable_device(pdev);
7998 msleep(260); /* a randomly chosen number */
7999 rc = pci_enable_device(pdev);
8000 if (rc) {
8001 dev_warn(&pdev->dev, "failed to enable device.\n");
8002 return -ENODEV;
8003 }
4fa604e1 8004
859c75ab 8005 pci_set_master(pdev);
4fa604e1 8006
3b747298
TH		 8007 vaddr = pci_ioremap_bar(pdev, 0);
8008 if (vaddr == NULL) {
8009 rc = -ENOMEM;
8010 goto out_disable;
8011 }
8012 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8013 iounmap(vaddr);
8014
1df8552a 8015 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 8016 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 8017
1df8552a
SC		 8018 /* -ENOTSUPP here means we cannot reset the controller
8019 * but it's already (and still) up and running in
18867659
SC		 8020 * "performant mode". Or, it might be 640x, which can't reset
8021 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 8022 */
adf1b3a3 8023 if (rc)
132aa220 8024 goto out_disable;
4c2a8c40
SC		 8025
8026 /* Now try to get the controller to respond to a no-op */
1ba66c9c 8027 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 8028 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
8029 if (hpsa_noop(pdev) == 0)
8030 break;
8031 else
8032 dev_warn(&pdev->dev, "no-op failed%s\n",
8033 (i < 11 ? "; re-trying" : ""));
8034 }
132aa220
TH		 8035
8036out_disable:
8037
8038 pci_disable_device(pdev);
8039 return rc;
4c2a8c40
SC		 8040}
8041
1fb7c98a
RE		 8042static void hpsa_free_cmd_pool(struct ctlr_info *h)
8043{
8044 kfree(h->cmd_pool_bits);
105a3dbc
RE		 8045 h->cmd_pool_bits = NULL;
8046 if (h->cmd_pool) {
1fb7c98a
RE		 8047 pci_free_consistent(h->pdev,
8048 h->nr_cmds * sizeof(struct CommandList),
8049 h->cmd_pool,
8050 h->cmd_pool_dhandle);
105a3dbc
RE		 8051 h->cmd_pool = NULL;
8052 h->cmd_pool_dhandle = 0;
8053 }
8054 if (h->errinfo_pool) {
1fb7c98a
RE		 8055 pci_free_consistent(h->pdev,
8056 h->nr_cmds * sizeof(struct ErrorInfo),
8057 h->errinfo_pool,
8058 h->errinfo_pool_dhandle);
105a3dbc
RE		 8059 h->errinfo_pool = NULL;
8060 h->errinfo_pool_dhandle = 0;
8061 }
1fb7c98a
RE		 8062}
8063
d37ffbe4 8064static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 8065{
8066 h->cmd_pool_bits = kzalloc(
8067 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
8068 sizeof(unsigned long), GFP_KERNEL);
8069 h->cmd_pool = pci_alloc_consistent(h->pdev,
8070 h->nr_cmds * sizeof(*h->cmd_pool),
8071 &(h->cmd_pool_dhandle));
8072 h->errinfo_pool = pci_alloc_consistent(h->pdev,
8073 h->nr_cmds * sizeof(*h->errinfo_pool),
8074 &(h->errinfo_pool_dhandle));
8075 if ((h->cmd_pool_bits == NULL)
8076 || (h->cmd_pool == NULL)
8077 || (h->errinfo_pool == NULL)) {
8078 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 8079 goto clean_up;
2e9d1b36 8080 }
360c73bd 8081 hpsa_preinitialize_commands(h);
2e9d1b36 8082 return 0;
2c143342
RE		 8083clean_up:
8084 hpsa_free_cmd_pool(h);
8085 return -ENOMEM;
2e9d1b36
SC		 8086}
8087
41b3cf08
SC		 8088static void hpsa_irq_affinity_hints(struct ctlr_info *h)
8089{
ec429952 8090 int i, cpu;
41b3cf08
SC		 8091
8092 cpu = cpumask_first(cpu_online_mask);
8093 for (i = 0; i < h->msix_vector; i++) {
ec429952 8094 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 8095 cpu = cpumask_next(cpu, cpu_online_mask);
8096 }
8097}
8098
ec501a18
RE		 8099/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
8100static void hpsa_free_irqs(struct ctlr_info *h)
8101{
8102 int i;
8103
8104 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
8105 /* Single reply queue, only one irq to free */
8106 i = h->intr_mode;
8107 irq_set_affinity_hint(h->intr[i], NULL);
8108 free_irq(h->intr[i], &h->q[i]);
105a3dbc 8109 h->q[i] = 0;
ec501a18
RE		 8110 return;
8111 }
8112
8113 for (i = 0; i < h->msix_vector; i++) {
8114 irq_set_affinity_hint(h->intr[i], NULL);
8115 free_irq(h->intr[i], &h->q[i]);
105a3dbc 8116 h->q[i] = 0;
ec501a18 8117 }
a4e17fc1
RE		 8118 for (; i < MAX_REPLY_QUEUES; i++)
8119 h->q[i] = 0;
ec501a18
RE		 8120}
8121
9ee61794
RE		 8122/* returns 0 on success; cleans up and returns -Enn on error */
8123static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 8124 irqreturn_t (*msixhandler)(int, void *),
8125 irqreturn_t (*intxhandler)(int, void *))
8126{
254f796b 8127 int rc, i;
0ae01a32 8128
254f796b
MG		 8129 /*
8130 * initialize h->q[x] = x so that interrupt handlers know which
8131 * queue to process.
8132 */
8133 for (i = 0; i < MAX_REPLY_QUEUES; i++)
8134 h->q[i] = (u8) i;
8135
eee0f03a 8136 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 8137 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 8138 for (i = 0; i < h->msix_vector; i++) {
8b47004a 8139 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
254f796b 8140 rc = request_irq(h->intr[i], msixhandler,
8b47004a 8141 0, h->intrname[i],
254f796b 8142 &h->q[i]);
a4e17fc1
RE		 8143 if (rc) {
8144 int j;
8145
8146 dev_err(&h->pdev->dev,
8147 "failed to get irq %d for %s\n",
8148 h->intr[i], h->devname);
8149 for (j = 0; j < i; j++) {
8150 free_irq(h->intr[j], &h->q[j]);
8151 h->q[j] = 0;
8152 }
8153 for (; j < MAX_REPLY_QUEUES; j++)
8154 h->q[j] = 0;
8155 return rc;
8156 }
8157 }
41b3cf08 8158 hpsa_irq_affinity_hints(h);
254f796b
MG		 8159 } else {
8160 /* Use single reply pool */
eee0f03a 8161 if (h->msix_vector > 0 || h->msi_vector) {
8b47004a
RE		 8162 if (h->msix_vector)
8163 sprintf(h->intrname[h->intr_mode],
8164 "%s-msix", h->devname);
8165 else
8166 sprintf(h->intrname[h->intr_mode],
8167 "%s-msi", h->devname);
254f796b 8168 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 8169 msixhandler, 0,
8170 h->intrname[h->intr_mode],
254f796b
MG		 8171 &h->q[h->intr_mode]);
8172 } else {
8b47004a
RE		 8173 sprintf(h->intrname[h->intr_mode],
8174 "%s-intx", h->devname);
254f796b 8175 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 8176 intxhandler, IRQF_SHARED,
8177 h->intrname[h->intr_mode],
254f796b
MG		 8178 &h->q[h->intr_mode]);
8179 }
105a3dbc 8180 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
254f796b 8181 }
0ae01a32 8182 if (rc) {
195f2c65 8183 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 8184 h->intr[h->intr_mode], h->devname);
195f2c65 8185 hpsa_free_irqs(h);
0ae01a32
SC		 8186 return -ENODEV;
8187 }
8188 return 0;
8189}
8190
6f039790 8191static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8 8192{
39c53f55 8193 int rc;
bf43caf3 8194 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
64670ac8
SC		 8195
8196 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
39c53f55
RE		 8197 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
8198 if (rc) {
64670ac8 8199 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
39c53f55 8200 return rc;
64670ac8
SC		 8201 }
8202
8203 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
39c53f55
RE		 8204 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
8205 if (rc) {
64670ac8
SC		 8206 dev_warn(&h->pdev->dev, "Board failed to become ready "
8207 "after soft reset.\n");
39c53f55 8208 return rc;
64670ac8
SC		 8209 }
8210
8211 return 0;
8212}
8213
072b0518
SC		 8214static void hpsa_free_reply_queues(struct ctlr_info *h)
8215{
8216 int i;
8217
8218 for (i = 0; i < h->nreply_queues; i++) {
8219 if (!h->reply_queue[i].head)
8220 continue;
1fb7c98a
RE		 8221 pci_free_consistent(h->pdev,
8222 h->reply_queue_size,
8223 h->reply_queue[i].head,
8224 h->reply_queue[i].busaddr);
072b0518
SC		 8225 h->reply_queue[i].head = NULL;
8226 h->reply_queue[i].busaddr = 0;
8227 }
105a3dbc 8228 h->reply_queue_size = 0;
072b0518
SC		 8229}
8230
0097f0f4
SC		 8231static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
8232{
105a3dbc
RE		 8233 hpsa_free_performant_mode(h); /* init_one 7 */
8234 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8235 hpsa_free_cmd_pool(h); /* init_one 5 */
8236 hpsa_free_irqs(h); /* init_one 4 */
2946e82b
RE		 8237 scsi_host_put(h->scsi_host); /* init_one 3 */
8238 h->scsi_host = NULL; /* init_one 3 */
8239 hpsa_free_pci_init(h); /* init_one 2_5 */
9ecd953a
RE		 8240 free_percpu(h->lockup_detected); /* init_one 2 */
8241 h->lockup_detected = NULL; /* init_one 2 */
8242 if (h->resubmit_wq) {
8243 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
8244 h->resubmit_wq = NULL;
8245 }
8246 if (h->rescan_ctlr_wq) {
8247 destroy_workqueue(h->rescan_ctlr_wq);
8248 h->rescan_ctlr_wq = NULL;
8249 }
105a3dbc 8250 kfree(h); /* init_one 1 */
64670ac8
SC		 8251}
8252
a0c12413 8253/* Called when controller lockup detected. */
f2405db8 8254static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 8255{
281a7fd0
WS		 8256 int i, refcount;
8257 struct CommandList *c;
25163bd5 8258 int failcount = 0;
a0c12413 8259
080ef1cc 8260 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 8261 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8262 c = h->cmd_pool + i;
281a7fd0
WS		 8263 refcount = atomic_inc_return(&c->refcount);
8264 if (refcount > 1) {
25163bd5 8265 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 8266 finish_cmd(c);
433b5f4d 8267 atomic_dec(&h->commands_outstanding);
25163bd5 8268 failcount++;
281a7fd0
WS		 8269 }
8270 cmd_free(h, c);
a0c12413 8271 }
25163bd5
WS		 8272 dev_warn(&h->pdev->dev,
8273 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 8274}
8275
094963da
SC		 8276static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
8277{
c8ed0010 8278 int cpu;
094963da 8279
c8ed0010 8280 for_each_online_cpu(cpu) {
094963da
SC		 8281 u32 *lockup_detected;
8282 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
8283 *lockup_detected = value;
094963da
SC		 8284 }
8285 wmb(); /* be sure the per-cpu variables are out to memory */
8286}
8287
a0c12413
SC		 8288static void controller_lockup_detected(struct ctlr_info *h)
8289{
8290 unsigned long flags;
094963da 8291 u32 lockup_detected;
a0c12413 8292
a0c12413
SC		 8293 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8294 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 8295 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
8296 if (!lockup_detected) {
8297 /* no heartbeat, but controller gave us a zero. */
8298 dev_warn(&h->pdev->dev,
25163bd5
WS		 8299 "lockup detected after %d but scratchpad register is zero\n",
8300 h->heartbeat_sample_interval / HZ);
094963da
SC		 8301 lockup_detected = 0xffffffff;
8302 }
8303 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 8304 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 8305 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
8306 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 8307 pci_disable_device(h->pdev);
f2405db8 8308 fail_all_outstanding_cmds(h);
a0c12413
SC		 8309}
8310
25163bd5 8311static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 8312{
8313 u64 now;
8314 u32 heartbeat;
8315 unsigned long flags;
8316
a0c12413
SC		 8317 now = get_jiffies_64();
8318 /* If we've received an interrupt recently, we're ok. */
8319 if (time_after64(h->last_intr_timestamp +
e85c5974 8320 (h->heartbeat_sample_interval), now))
25163bd5 8321 return false;
a0c12413
SC		 8322
8323 /*
8324 * If we've already checked the heartbeat recently, we're ok.
8325 * This could happen if someone sends us a signal. We
8326 * otherwise don't care about signals in this thread.
8327 */
8328 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 8329 (h->heartbeat_sample_interval), now))
25163bd5 8330 return false;
a0c12413
SC		 8331
8332 /* If heartbeat has not changed since we last looked, we're not ok. */
8333 spin_lock_irqsave(&h->lock, flags);
8334 heartbeat = readl(&h->cfgtable->HeartBeat);
8335 spin_unlock_irqrestore(&h->lock, flags);
8336 if (h->last_heartbeat == heartbeat) {
8337 controller_lockup_detected(h);
25163bd5 8338 return true;
a0c12413
SC		 8339 }
8340
8341 /* We're ok. */
8342 h->last_heartbeat = heartbeat;
8343 h->last_heartbeat_timestamp = now;
25163bd5 8344 return false;
a0c12413
SC		 8345}
8346
9846590e 8347static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 8348{
8349 int i;
8350 char *event_type;
8351
e4aa3e6a
SC		 8352 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
8353 return;
8354
76438d08 8355 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 8356 if ((h->transMethod & (CFGTBL_Trans_io_accel1
8357 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 8358 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
8359 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
8360
8361 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
8362 event_type = "state change";
8363 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
8364 event_type = "configuration change";
8365 /* Stop sending new RAID offload reqs via the IO accelerator */
8366 scsi_block_requests(h->scsi_host);
5323ed74 8367 for (i = 0; i < h->ndevices; i++) {
76438d08 8368 h->dev[i]->offload_enabled = 0;
5323ed74
DB		 8369 h->dev[i]->offload_to_be_enabled = 0;
8370 }
23100dd9 8371 hpsa_drain_accel_commands(h);
76438d08
SC		 8372 /* Set 'accelerator path config change' bit */
8373 dev_warn(&h->pdev->dev,
8374 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
8375 h->events, event_type);
8376 writel(h->events, &(h->cfgtable->clear_event_notify));
8377 /* Set the "clear event notify field update" bit 6 */
8378 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
8379 /* Wait until ctlr clears 'clear event notify field', bit 6 */
8380 hpsa_wait_for_clear_event_notify_ack(h);
8381 scsi_unblock_requests(h->scsi_host);
8382 } else {
8383 /* Acknowledge controller notification events. */
8384 writel(h->events, &(h->cfgtable->clear_event_notify));
8385 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
8386 hpsa_wait_for_clear_event_notify_ack(h);
8387#if 0
8388 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
8389 hpsa_wait_for_mode_change_ack(h);
8390#endif
8391 }
9846590e 8392 return;
76438d08
SC		 8393}
8394
8395/* Check a register on the controller to see if there are configuration
8396 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 8397 * we should rescan the controller for devices.
8398 * Also check flag for driver-initiated rescan.
76438d08 8399 */
9846590e 8400static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 8401{
853633e8
DB		 8402 if (h->drv_req_rescan) {
8403 h->drv_req_rescan = 0;
8404 return 1;
8405 }
8406
76438d08 8407 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 8408 return 0;
76438d08
SC		 8409
8410 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 8411 return h->events & RESCAN_REQUIRED_EVENT_BITS;
8412}
76438d08 8413
9846590e
SC		 8414/*
8415 * Check if any of the offline devices have become ready
8416 */
8417static int hpsa_offline_devices_ready(struct ctlr_info *h)
8418{
8419 unsigned long flags;
8420 struct offline_device_entry *d;
8421 struct list_head *this, *tmp;
8422
8423 spin_lock_irqsave(&h->offline_device_lock, flags);
8424 list_for_each_safe(this, tmp, &h->offline_device_list) {
8425 d = list_entry(this, struct offline_device_entry,
8426 offline_list);
8427 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 8428 if (!hpsa_volume_offline(h, d->scsi3addr)) {
8429 spin_lock_irqsave(&h->offline_device_lock, flags);
8430 list_del(&d->offline_list);
8431 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 8432 return 1;
d1fea47c 8433 }
9846590e
SC		 8434 spin_lock_irqsave(&h->offline_device_lock, flags);
8435 }
8436 spin_unlock_irqrestore(&h->offline_device_lock, flags);
8437 return 0;
76438d08
SC		 8438}
8439
34592254
ST		 8440static int hpsa_luns_changed(struct ctlr_info *h)
8441{
8442 int rc = 1; /* assume there are changes */
8443 struct ReportLUNdata *logdev = NULL;
8444
8445 /* if we can't find out if lun data has changed,
8446 * assume that it has.
8447 */
8448
8449 if (!h->lastlogicals)
8450 goto out;
8451
8452 logdev = kzalloc(sizeof(*logdev), GFP_KERNEL);
8453 if (!logdev) {
8454 dev_warn(&h->pdev->dev,
8455 "Out of memory, can't track lun changes.\n");
8456 goto out;
8457 }
8458 if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) {
8459 dev_warn(&h->pdev->dev,
8460 "report luns failed, can't track lun changes.\n");
8461 goto out;
8462 }
8463 if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) {
8464 dev_info(&h->pdev->dev,
8465 "Lun changes detected.\n");
8466 memcpy(h->lastlogicals, logdev, sizeof(*logdev));
8467 goto out;
8468 } else
8469 rc = 0; /* no changes detected. */
8470out:
8471 kfree(logdev);
8472 return rc;
8473}
8474
6636e7f4 8475static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 8476{
8477 unsigned long flags;
8a98db73 8478 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 8479 struct ctlr_info, rescan_ctlr_work);
8480
8481
8482 if (h->remove_in_progress)
8a98db73 8483 return;
9846590e
SC		 8484
8485 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
8486 scsi_host_get(h->scsi_host);
9846590e
SC		 8487 hpsa_ack_ctlr_events(h);
8488 hpsa_scan_start(h->scsi_host);
8489 scsi_host_put(h->scsi_host);
34592254 8490 } else if (h->discovery_polling) {
c2adae44 8491 hpsa_disable_rld_caching(h);
34592254
ST		 8492 if (hpsa_luns_changed(h)) {
8493 struct Scsi_Host *sh = NULL;
8494
8495 dev_info(&h->pdev->dev,
8496 "driver discovery polling rescan.\n");
8497 sh = scsi_host_get(h->scsi_host);
8498 if (sh != NULL) {
8499 hpsa_scan_start(sh);
8500 scsi_host_put(sh);
8501 }
8502 }
9846590e 8503 }
8a98db73 8504 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 8505 if (!h->remove_in_progress)
8506 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8507 h->heartbeat_sample_interval);
8508 spin_unlock_irqrestore(&h->lock, flags);
8509}
8510
8511static void hpsa_monitor_ctlr_worker(struct work_struct *work)
8512{
8513 unsigned long flags;
8514 struct ctlr_info *h = container_of(to_delayed_work(work),
8515 struct ctlr_info, monitor_ctlr_work);
8516
8517 detect_controller_lockup(h);
8518 if (lockup_detected(h))
a0c12413 8519 return;
6636e7f4
DB		 8520
8521 spin_lock_irqsave(&h->lock, flags);
8522 if (!h->remove_in_progress)
8523 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 8524 h->heartbeat_sample_interval);
8525 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 8526}
8527
6636e7f4
DB		 8528static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
8529 char *name)
8530{
8531 struct workqueue_struct *wq = NULL;
6636e7f4 8532
397ea9cb 8533 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 8534 if (!wq)
8535 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
8536
8537 return wq;
8538}
8539
6f039790 8540static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 8541{
4c2a8c40 8542 int dac, rc;
edd16368 8543 struct ctlr_info *h;
64670ac8
SC		 8544 int try_soft_reset = 0;
8545 unsigned long flags;
6b6c1cd7 8546 u32 board_id;
edd16368
SC		 8547
8548 if (number_of_controllers == 0)
8549 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 8550
6b6c1cd7
TH		 8551 rc = hpsa_lookup_board_id(pdev, &board_id);
8552 if (rc < 0) {
8553 dev_warn(&pdev->dev, "Board ID not found\n");
8554 return rc;
8555 }
8556
8557 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 8558 if (rc) {
8559 if (rc != -ENOTSUPP)
8560 return rc;
8561 /* If the reset fails in a particular way (it has no way to do
8562 * a proper hard reset, so returns -ENOTSUPP) we can try to do
8563 * a soft reset once we get the controller configured up to the
8564 * point that it can accept a command.
8565 */
8566 try_soft_reset = 1;
8567 rc = 0;
8568 }
8569
8570reinit_after_soft_reset:
edd16368 8571
303932fd
DB		 8572 /* Command structures must be aligned on a 32-byte boundary because
8573 * the 5 lower bits of the address are used by the hardware. and by
8574 * the driver. See comments in hpsa.h for more info.
8575 */
303932fd 8576 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368 8577 h = kzalloc(sizeof(*h), GFP_KERNEL);
105a3dbc
RE		 8578 if (!h) {
8579 dev_err(&pdev->dev, "Failed to allocate controller head\n");
ecd9aad4 8580 return -ENOMEM;
105a3dbc 8581 }
edd16368 8582
55c06c71 8583 h->pdev = pdev;
105a3dbc 8584
a9a3a273 8585 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 8586 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 8587 spin_lock_init(&h->lock);
9846590e 8588 spin_lock_init(&h->offline_device_lock);
6eaf46fd 8589 spin_lock_init(&h->scan_lock);
34f0c627 8590 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 8591 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da
SC		 8592
8593 /* Allocate and clear per-cpu variable lockup_detected */
8594 h->lockup_detected = alloc_percpu(u32);
2a5ac326 8595 if (!h->lockup_detected) {
105a3dbc 8596 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
2a5ac326 8597 rc = -ENOMEM;
2efa5929 8598 goto clean1; /* aer/h */
2a5ac326 8599 }
094963da
SC		 8600 set_lockup_detected_for_all_cpus(h, 0);
8601
55c06c71 8602 rc = hpsa_pci_init(h);
105a3dbc 8603 if (rc)
2946e82b
RE		 8604 goto clean2; /* lu, aer/h */
8605
8606 /* relies on h-> settings made by hpsa_pci_init, including
8607 * interrupt_mode h->intr */
8608 rc = hpsa_scsi_host_alloc(h);
8609 if (rc)
8610 goto clean2_5; /* pci, lu, aer/h */
edd16368 8611
2946e82b 8612 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
edd16368
SC		 8613 h->ctlr = number_of_controllers;
8614 number_of_controllers++;
edd16368
SC		 8615
8616 /* configure PCI DMA stuff */
ecd9aad4
SC		 8617 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
8618 if (rc == 0) {
edd16368 8619 dac = 1;
ecd9aad4
SC		 8620 } else {
8621 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8622 if (rc == 0) {
8623 dac = 0;
8624 } else {
8625 dev_err(&pdev->dev, "no suitable DMA available\n");
2946e82b 8626 goto clean3; /* shost, pci, lu, aer/h */
ecd9aad4 8627 }
edd16368
SC		 8628 }
8629
8630 /* make sure the board interrupts are off */
8631 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 8632
105a3dbc
RE		 8633 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
8634 if (rc)
2946e82b 8635 goto clean3; /* shost, pci, lu, aer/h */
d37ffbe4 8636 rc = hpsa_alloc_cmd_pool(h);
8947fd10 8637 if (rc)
2946e82b 8638 goto clean4; /* irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8639 rc = hpsa_alloc_sg_chain_blocks(h);
8640 if (rc)
2946e82b 8641 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
a08a8471 8642 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 8643 init_waitqueue_head(&h->abort_cmd_wait_queue);
d604f533
WS		 8644 init_waitqueue_head(&h->event_sync_wait_queue);
8645 mutex_init(&h->reset_mutex);
a08a8471 8646 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 8647
8648 pci_set_drvdata(pdev, h);
9a41338e 8649 h->ndevices = 0;
2946e82b 8650
9a41338e 8651 spin_lock_init(&h->devlock);
105a3dbc
RE		 8652 rc = hpsa_put_ctlr_into_performant_mode(h);
8653 if (rc)
2946e82b
RE		 8654 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8655
2efa5929
RE		 8656 /* create the resubmit workqueue */
8657 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8658 if (!h->rescan_ctlr_wq) {
8659 rc = -ENOMEM;
8660 goto clean7;
8661 }
8662
8663 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8664 if (!h->resubmit_wq) {
8665 rc = -ENOMEM;
8666 goto clean7; /* aer/h */
8667 }
64670ac8 8668
105a3dbc
RE		 8669 /*
8670 * At this point, the controller is ready to take commands.
64670ac8
SC		 8671 * Now, if reset_devices and the hard reset didn't work, try
8672 * the soft reset and see if that works.
8673 */
8674 if (try_soft_reset) {
8675
8676 /* This is kind of gross. We may or may not get a completion
8677 * from the soft reset command, and if we do, then the value
8678 * from the fifo may or may not be valid. So, we wait 10 secs
8679 * after the reset throwing away any completions we get during
8680 * that time. Unregister the interrupt handler and register
8681 * fake ones to scoop up any residual completions.
8682 */
8683 spin_lock_irqsave(&h->lock, flags);
8684 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8685 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 8686 hpsa_free_irqs(h);
9ee61794 8687 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 8688 hpsa_intx_discard_completions);
8689 if (rc) {
9ee61794
RE		 8690 dev_warn(&h->pdev->dev,
8691 "Failed to request_irq after soft reset.\n");
d498757c 8692 /*
b2ef480c
RE		 8693 * cannot goto clean7 or free_irqs will be called
8694 * again. Instead, do its work
8695 */
8696 hpsa_free_performant_mode(h); /* clean7 */
8697 hpsa_free_sg_chain_blocks(h); /* clean6 */
8698 hpsa_free_cmd_pool(h); /* clean5 */
8699 /*
8700 * skip hpsa_free_irqs(h) clean4 since that
8701 * was just called before request_irqs failed
d498757c
RE		 8702 */
8703 goto clean3;
64670ac8
SC		 8704 }
8705
8706 rc = hpsa_kdump_soft_reset(h);
8707 if (rc)
8708 /* Neither hard nor soft reset worked, we're hosed. */
7ef7323f 8709 goto clean7;
64670ac8
SC		 8710
8711 dev_info(&h->pdev->dev, "Board READY.\n");
8712 dev_info(&h->pdev->dev,
8713 "Waiting for stale completions to drain.\n");
8714 h->access.set_intr_mask(h, HPSA_INTR_ON);
8715 msleep(10000);
8716 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8717
8718 rc = controller_reset_failed(h->cfgtable);
8719 if (rc)
8720 dev_info(&h->pdev->dev,
8721 "Soft reset appears to have failed.\n");
8722
8723 /* since the controller's reset, we have to go back and re-init
8724 * everything. Easiest to just forget what we've done and do it
8725 * all over again.
8726 */
8727 hpsa_undo_allocations_after_kdump_soft_reset(h);
8728 try_soft_reset = 0;
8729 if (rc)
b2ef480c 8730 /* don't goto clean, we already unallocated */
64670ac8
SC		 8731 return -ENODEV;
8732
8733 goto reinit_after_soft_reset;
8734 }
edd16368 8735
105a3dbc
RE		 8736 /* Enable Accelerated IO path at driver layer */
8737 h->acciopath_status = 1;
34592254
ST		 8738 /* Disable discovery polling.*/
8739 h->discovery_polling = 0;
da0697bd 8740
e863d68e 8741
edd16368
SC		 8742 /* Turn the interrupts on so we can service requests */
8743 h->access.set_intr_mask(h, HPSA_INTR_ON);
8744
339b2b14 8745 hpsa_hba_inquiry(h);
8a98db73 8746
34592254
ST		 8747 h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL);
8748 if (!h->lastlogicals)
8749 dev_info(&h->pdev->dev,
8750 "Can't track change to report lun data\n");
8751
cf477237
DB		 8752 /* hook into SCSI subsystem */
8753 rc = hpsa_scsi_add_host(h);
8754 if (rc)
8755 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
8756
8a98db73
SC		 8757 /* Monitor the controller for firmware lockups */
8758 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8759 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8760 schedule_delayed_work(&h->monitor_ctlr_work,
8761 h->heartbeat_sample_interval);
6636e7f4
DB		 8762 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8763 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8764 h->heartbeat_sample_interval);
88bf6d62 8765 return 0;
edd16368 8766
2946e82b 8767clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8768 hpsa_free_performant_mode(h);
8769 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8770clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
33a2ffce 8771 hpsa_free_sg_chain_blocks(h);
2946e82b 8772clean5: /* cmd, irq, shost, pci, lu, aer/h */
2e9d1b36 8773 hpsa_free_cmd_pool(h);
2946e82b 8774clean4: /* irq, shost, pci, lu, aer/h */
ec501a18 8775 hpsa_free_irqs(h);
2946e82b
RE		 8776clean3: /* shost, pci, lu, aer/h */
8777 scsi_host_put(h->scsi_host);
8778 h->scsi_host = NULL;
8779clean2_5: /* pci, lu, aer/h */
195f2c65 8780 hpsa_free_pci_init(h);
2946e82b 8781clean2: /* lu, aer/h */
105a3dbc
RE		 8782 if (h->lockup_detected) {
8783 free_percpu(h->lockup_detected);
8784 h->lockup_detected = NULL;
8785 }
8786clean1: /* wq/aer/h */
8787 if (h->resubmit_wq) {
080ef1cc 8788 destroy_workqueue(h->resubmit_wq);
105a3dbc
RE		 8789 h->resubmit_wq = NULL;
8790 }
8791 if (h->rescan_ctlr_wq) {
6636e7f4 8792 destroy_workqueue(h->rescan_ctlr_wq);
105a3dbc
RE		 8793 h->rescan_ctlr_wq = NULL;
8794 }
edd16368 8795 kfree(h);
ecd9aad4 8796 return rc;
edd16368
SC		 8797}
8798
8799static void hpsa_flush_cache(struct ctlr_info *h)
8800{
8801 char *flush_buf;
8802 struct CommandList *c;
25163bd5 8803 int rc;
702890e3 8804
094963da 8805 if (unlikely(lockup_detected(h)))
702890e3 8806 return;
edd16368
SC		 8807 flush_buf = kzalloc(4, GFP_KERNEL);
8808 if (!flush_buf)
8809 return;
8810
45fcb86e 8811 c = cmd_alloc(h);
bf43caf3 8812
a2dac136
SC		 8813 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8814 RAID_CTLR_LUNID, TYPE_CMD)) {
8815 goto out;
8816 }
25163bd5 8817 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 8818 PCI_DMA_TODEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 8819 if (rc)
8820 goto out;
edd16368 8821 if (c->err_info->CommandStatus != 0)
a2dac136 8822out:
edd16368
SC		 8823 dev_warn(&h->pdev->dev,
8824 "error flushing cache on controller\n");
45fcb86e 8825 cmd_free(h, c);
edd16368
SC		 8826 kfree(flush_buf);
8827}
8828
c2adae44
ST		 8829/* Make controller gather fresh report lun data each time we
8830 * send down a report luns request
8831 */
8832static void hpsa_disable_rld_caching(struct ctlr_info *h)
8833{
8834 u32 *options;
8835 struct CommandList *c;
8836 int rc;
8837
8838 /* Don't bother trying to set diag options if locked up */
8839 if (unlikely(h->lockup_detected))
8840 return;
8841
8842 options = kzalloc(sizeof(*options), GFP_KERNEL);
8843 if (!options) {
8844 dev_err(&h->pdev->dev,
8845 "Error: failed to disable rld caching, during alloc.\n");
8846 return;
8847 }
8848
8849 c = cmd_alloc(h);
8850
8851 /* first, get the current diag options settings */
8852 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
8853 RAID_CTLR_LUNID, TYPE_CMD))
8854 goto errout;
8855
8856 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 8857 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
c2adae44
ST		 8858 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8859 goto errout;
8860
8861 /* Now, set the bit for disabling the RLD caching */
8862 *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING;
8863
8864 if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0,
8865 RAID_CTLR_LUNID, TYPE_CMD))
8866 goto errout;
8867
8868 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 8869 PCI_DMA_TODEVICE, DEFAULT_TIMEOUT);
c2adae44
ST		 8870 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8871 goto errout;
8872
8873 /* Now verify that it got set: */
8874 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
8875 RAID_CTLR_LUNID, TYPE_CMD))
8876 goto errout;
8877
8878 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 8879 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
c2adae44
ST		 8880 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8881 goto errout;
8882
d8a080c3 8883 if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING)
c2adae44
ST		 8884 goto out;
8885
8886errout:
8887 dev_err(&h->pdev->dev,
8888 "Error: failed to disable report lun data caching.\n");
8889out:
8890 cmd_free(h, c);
8891 kfree(options);
8892}
8893
edd16368
SC		 8894static void hpsa_shutdown(struct pci_dev *pdev)
8895{
8896 struct ctlr_info *h;
8897
8898 h = pci_get_drvdata(pdev);
8899 /* Turn board interrupts off and send the flush cache command
8900 * sendcmd will turn off interrupt, and send the flush...
8901 * To write all data in the battery backed cache to disks
8902 */
8903 hpsa_flush_cache(h);
8904 h->access.set_intr_mask(h, HPSA_INTR_OFF);
105a3dbc 8905 hpsa_free_irqs(h); /* init_one 4 */
cc64c817 8906 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 8907}
8908
6f039790 8909static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 8910{
8911 int i;
8912
105a3dbc 8913 for (i = 0; i < h->ndevices; i++) {
55e14e76 8914 kfree(h->dev[i]);
105a3dbc
RE		 8915 h->dev[i] = NULL;
8916 }
55e14e76
SC		 8917}
8918
6f039790 8919static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 8920{
8921 struct ctlr_info *h;
8a98db73 8922 unsigned long flags;
edd16368
SC		 8923
8924 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 8925 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 8926 return;
8927 }
8928 h = pci_get_drvdata(pdev);
8a98db73
SC		 8929
8930 /* Get rid of any controller monitoring work items */
8931 spin_lock_irqsave(&h->lock, flags);
8932 h->remove_in_progress = 1;
8a98db73 8933 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 8934 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8935 cancel_delayed_work_sync(&h->rescan_ctlr_work);
8936 destroy_workqueue(h->rescan_ctlr_wq);
8937 destroy_workqueue(h->resubmit_wq);
cc64c817 8938
2d041306
DB		 8939 /*
8940 * Call before disabling interrupts.
8941 * scsi_remove_host can trigger I/O operations especially
8942 * when multipath is enabled. There can be SYNCHRONIZE CACHE
8943 * operations which cannot complete and will hang the system.
8944 */
8945 if (h->scsi_host)
8946 scsi_remove_host(h->scsi_host); /* init_one 8 */
105a3dbc 8947 /* includes hpsa_free_irqs - init_one 4 */
195f2c65 8948 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 8949 hpsa_shutdown(pdev);
cc64c817 8950
105a3dbc
RE		 8951 hpsa_free_device_info(h); /* scan */
8952
2946e82b
RE		 8953 kfree(h->hba_inquiry_data); /* init_one 10 */
8954 h->hba_inquiry_data = NULL; /* init_one 10 */
2946e82b 8955 hpsa_free_ioaccel2_sg_chain_blocks(h);
105a3dbc
RE		 8956 hpsa_free_performant_mode(h); /* init_one 7 */
8957 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8958 hpsa_free_cmd_pool(h); /* init_one 5 */
34592254 8959 kfree(h->lastlogicals);
105a3dbc
RE		 8960
8961 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
195f2c65 8962
2946e82b
RE		 8963 scsi_host_put(h->scsi_host); /* init_one 3 */
8964 h->scsi_host = NULL; /* init_one 3 */
8965
195f2c65 8966 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
2946e82b 8967 hpsa_free_pci_init(h); /* init_one 2.5 */
195f2c65 8968
105a3dbc
RE		 8969 free_percpu(h->lockup_detected); /* init_one 2 */
8970 h->lockup_detected = NULL; /* init_one 2 */
8971 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
d04e62b9
KB		 8972
8973 hpsa_delete_sas_host(h);
8974
105a3dbc 8975 kfree(h); /* init_one 1 */
edd16368
SC		 8976}
8977
8978static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8979 __attribute__((unused)) pm_message_t state)
8980{
8981 return -ENOSYS;
8982}
8983
8984static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8985{
8986 return -ENOSYS;
8987}
8988
8989static struct pci_driver hpsa_pci_driver = {
f79cfec6 8990 .name = HPSA,
edd16368 8991 .probe = hpsa_init_one,
6f039790 8992 .remove = hpsa_remove_one,
edd16368
SC		 8993 .id_table = hpsa_pci_device_id, /* id_table */
8994 .shutdown = hpsa_shutdown,
8995 .suspend = hpsa_suspend,
8996 .resume = hpsa_resume,
8997};
8998
303932fd
DB		 8999/* Fill in bucket_map[], given nsgs (the max number of
9000 * scatter gather elements supported) and bucket[],
9001 * which is an array of 8 integers. The bucket[] array
9002 * contains 8 different DMA transfer sizes (in 16
9003 * byte increments) which the controller uses to fetch
9004 * commands. This function fills in bucket_map[], which
9005 * maps a given number of scatter gather elements to one of
9006 * the 8 DMA transfer sizes. The point of it is to allow the
9007 * controller to only do as much DMA as needed to fetch the
9008 * command, with the DMA transfer size encoded in the lower
9009 * bits of the command address.
9010 */
9011static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 9012 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 9013{
9014 int i, j, b, size;
9015
303932fd
DB		 9016 /* Note, bucket_map must have nsgs+1 entries. */
9017 for (i = 0; i <= nsgs; i++) {
9018 /* Compute size of a command with i SG entries */
e1f7de0c 9019 size = i + min_blocks;
303932fd
DB		 9020 b = num_buckets; /* Assume the biggest bucket */
9021 /* Find the bucket that is just big enough */
e1f7de0c 9022 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 9023 if (bucket[j] >= size) {
9024 b = j;
9025 break;
9026 }
9027 }
9028 /* for a command with i SG entries, use bucket b. */
9029 bucket_map[i] = b;
9030 }
9031}
9032
105a3dbc
RE		 9033/*
9034 * return -ENODEV on err, 0 on success (or no action)
9035 * allocates numerous items that must be freed later
9036 */
c706a795 9037static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 9038{
6c311b57
SC		 9039 int i;
9040 unsigned long register_value;
e1f7de0c
MG		 9041 unsigned long transMethod = CFGTBL_Trans_Performant |
9042 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 9043 CFGTBL_Trans_enable_directed_msix |
9044 (trans_support & (CFGTBL_Trans_io_accel1 |
9045 CFGTBL_Trans_io_accel2));
e1f7de0c 9046 struct access_method access = SA5_performant_access;
def342bd
SC		 9047
9048 /* This is a bit complicated. There are 8 registers on
9049 * the controller which we write to to tell it 8 different
9050 * sizes of commands which there may be. It's a way of
9051 * reducing the DMA done to fetch each command. Encoded into
9052 * each command's tag are 3 bits which communicate to the controller
9053 * which of the eight sizes that command fits within. The size of
9054 * each command depends on how many scatter gather entries there are.
9055 * Each SG entry requires 16 bytes. The eight registers are programmed
9056 * with the number of 16-byte blocks a command of that size requires.
9057 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 9058 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 9059 * blocks. Note, this only extends to the SG entries contained
9060 * within the command block, and does not extend to chained blocks
9061 * of SG elements. bft[] contains the eight values we write to
9062 * the registers. They are not evenly distributed, but have more
9063 * sizes for small commands, and fewer sizes for larger commands.
9064 */
d66ae08b 9065 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 9066#define MIN_IOACCEL2_BFT_ENTRY 5
9067#define HPSA_IOACCEL2_HEADER_SZ 4
9068 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
9069 13, 14, 15, 16, 17, 18, 19,
9070 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
9071 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
9072 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
9073 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
9074 16 * MIN_IOACCEL2_BFT_ENTRY);
9075 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 9076 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 9077 /* 5 = 1 s/g entry or 4k
9078 * 6 = 2 s/g entry or 8k
9079 * 8 = 4 s/g entry or 16k
9080 * 10 = 6 s/g entry or 24k
9081 */
303932fd 9082
b3a52e79
SC		 9083 /* If the controller supports either ioaccel method then
9084 * we can also use the RAID stack submit path that does not
9085 * perform the superfluous readl() after each command submission.
9086 */
9087 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
9088 access = SA5_performant_access_no_read;
9089
303932fd 9090 /* Controller spec: zero out this buffer. */
072b0518
SC		 9091 for (i = 0; i < h->nreply_queues; i++)
9092 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 9093
d66ae08b
SC		 9094 bft[7] = SG_ENTRIES_IN_CMD + 4;
9095 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 9096 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 9097 for (i = 0; i < 8; i++)
9098 writel(bft[i], &h->transtable->BlockFetch[i]);
9099
9100 /* size of controller ring buffer */
9101 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 9102 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 9103 writel(0, &h->transtable->RepQCtrAddrLow32);
9104 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 9105
9106 for (i = 0; i < h->nreply_queues; i++) {
9107 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 9108 writel(h->reply_queue[i].busaddr,
254f796b
MG		 9109 &h->transtable->RepQAddr[i].lower);
9110 }
9111
b9af4937 9112 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 9113 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
9114 /*
9115 * enable outbound interrupt coalescing in accelerator mode;
9116 */
9117 if (trans_support & CFGTBL_Trans_io_accel1) {
9118 access = SA5_ioaccel_mode1_access;
9119 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
9120 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 9121 } else {
9122 if (trans_support & CFGTBL_Trans_io_accel2) {
9123 access = SA5_ioaccel_mode2_access;
9124 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
9125 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
9126 }
e1f7de0c 9127 }
303932fd 9128 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 9129 if (hpsa_wait_for_mode_change_ack(h)) {
9130 dev_err(&h->pdev->dev,
9131 "performant mode problem - doorbell timeout\n");
9132 return -ENODEV;
9133 }
303932fd
DB		 9134 register_value = readl(&(h->cfgtable->TransportActive));
9135 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 9136 dev_err(&h->pdev->dev,
9137 "performant mode problem - transport not active\n");
c706a795 9138 return -ENODEV;
303932fd 9139 }
960a30e7 9140 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 9141 h->access = access;
9142 h->transMethod = transMethod;
9143
b9af4937
SC		 9144 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
9145 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 9146 return 0;
e1f7de0c 9147
b9af4937
SC		 9148 if (trans_support & CFGTBL_Trans_io_accel1) {
9149 /* Set up I/O accelerator mode */
9150 for (i = 0; i < h->nreply_queues; i++) {
9151 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
9152 h->reply_queue[i].current_entry =
9153 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
9154 }
9155 bft[7] = h->ioaccel_maxsg + 8;
9156 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
9157 h->ioaccel1_blockFetchTable);
e1f7de0c 9158
b9af4937 9159 /* initialize all reply queue entries to unused */
072b0518
SC		 9160 for (i = 0; i < h->nreply_queues; i++)
9161 memset(h->reply_queue[i].head,
9162 (u8) IOACCEL_MODE1_REPLY_UNUSED,
9163 h->reply_queue_size);
e1f7de0c 9164
b9af4937
SC		 9165 /* set all the constant fields in the accelerator command
9166 * frames once at init time to save CPU cycles later.
9167 */
9168 for (i = 0; i < h->nr_cmds; i++) {
9169 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
9170
9171 cp->function = IOACCEL1_FUNCTION_SCSIIO;
9172 cp->err_info = (u32) (h->errinfo_pool_dhandle +
9173 (i * sizeof(struct ErrorInfo)));
9174 cp->err_info_len = sizeof(struct ErrorInfo);
9175 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 9176 cp->host_context_flags =
9177 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 9178 cp->timeout_sec = 0;
9179 cp->ReplyQueue = 0;
50a0decf 9180 cp->tag =
f2405db8 9181 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 9182 cp->host_addr =
9183 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 9184 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 9185 }
9186 } else if (trans_support & CFGTBL_Trans_io_accel2) {
9187 u64 cfg_offset, cfg_base_addr_index;
9188 u32 bft2_offset, cfg_base_addr;
9189 int rc;
9190
9191 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
9192 &cfg_base_addr_index, &cfg_offset);
9193 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
9194 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
9195 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
9196 4, h->ioaccel2_blockFetchTable);
9197 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
9198 BUILD_BUG_ON(offsetof(struct CfgTable,
9199 io_accel_request_size_offset) != 0xb8);
9200 h->ioaccel2_bft2_regs =
9201 remap_pci_mem(pci_resource_start(h->pdev,
9202 cfg_base_addr_index) +
9203 cfg_offset + bft2_offset,
9204 ARRAY_SIZE(bft2) *
9205 sizeof(*h->ioaccel2_bft2_regs));
9206 for (i = 0; i < ARRAY_SIZE(bft2); i++)
9207 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 9208 }
b9af4937 9209 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 9210 if (hpsa_wait_for_mode_change_ack(h)) {
9211 dev_err(&h->pdev->dev,
9212 "performant mode problem - enabling ioaccel mode\n");
9213 return -ENODEV;
9214 }
9215 return 0;
e1f7de0c
MG		 9216}
9217
1fb7c98a
RE		 9218/* Free ioaccel1 mode command blocks and block fetch table */
9219static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
9220{
105a3dbc 9221 if (h->ioaccel_cmd_pool) {
1fb7c98a
RE		 9222 pci_free_consistent(h->pdev,
9223 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
9224 h->ioaccel_cmd_pool,
9225 h->ioaccel_cmd_pool_dhandle);
105a3dbc
RE		 9226 h->ioaccel_cmd_pool = NULL;
9227 h->ioaccel_cmd_pool_dhandle = 0;
9228 }
1fb7c98a 9229 kfree(h->ioaccel1_blockFetchTable);
105a3dbc 9230 h->ioaccel1_blockFetchTable = NULL;
1fb7c98a
RE		 9231}
9232
d37ffbe4
RE		 9233/* Allocate ioaccel1 mode command blocks and block fetch table */
9234static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 9235{
283b4a9b
SC		 9236 h->ioaccel_maxsg =
9237 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
9238 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
9239 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
9240
e1f7de0c
MG		 9241 /* Command structures must be aligned on a 128-byte boundary
9242 * because the 7 lower bits of the address are used by the
9243 * hardware.
9244 */
e1f7de0c
MG		 9245 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
9246 IOACCEL1_COMMANDLIST_ALIGNMENT);
9247 h->ioaccel_cmd_pool =
9248 pci_alloc_consistent(h->pdev,
9249 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
9250 &(h->ioaccel_cmd_pool_dhandle));
9251
9252 h->ioaccel1_blockFetchTable =
283b4a9b 9253 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 9254 sizeof(u32)), GFP_KERNEL);
9255
9256 if ((h->ioaccel_cmd_pool == NULL) ||
9257 (h->ioaccel1_blockFetchTable == NULL))
9258 goto clean_up;
9259
9260 memset(h->ioaccel_cmd_pool, 0,
9261 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
9262 return 0;
9263
9264clean_up:
1fb7c98a 9265 hpsa_free_ioaccel1_cmd_and_bft(h);
2dd02d74 9266 return -ENOMEM;
6c311b57
SC		 9267}
9268
1fb7c98a
RE		 9269/* Free ioaccel2 mode command blocks and block fetch table */
9270static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
9271{
d9a729f3
WS		 9272 hpsa_free_ioaccel2_sg_chain_blocks(h);
9273
105a3dbc 9274 if (h->ioaccel2_cmd_pool) {
1fb7c98a
RE		 9275 pci_free_consistent(h->pdev,
9276 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
9277 h->ioaccel2_cmd_pool,
9278 h->ioaccel2_cmd_pool_dhandle);
105a3dbc
RE		 9279 h->ioaccel2_cmd_pool = NULL;
9280 h->ioaccel2_cmd_pool_dhandle = 0;
9281 }
1fb7c98a 9282 kfree(h->ioaccel2_blockFetchTable);
105a3dbc 9283 h->ioaccel2_blockFetchTable = NULL;
1fb7c98a
RE		 9284}
9285
d37ffbe4
RE		 9286/* Allocate ioaccel2 mode command blocks and block fetch table */
9287static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 9288{
d9a729f3
WS		 9289 int rc;
9290
aca9012a
SC		 9291 /* Allocate ioaccel2 mode command blocks and block fetch table */
9292
9293 h->ioaccel_maxsg =
9294 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
9295 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
9296 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
9297
aca9012a
SC		 9298 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
9299 IOACCEL2_COMMANDLIST_ALIGNMENT);
9300 h->ioaccel2_cmd_pool =
9301 pci_alloc_consistent(h->pdev,
9302 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
9303 &(h->ioaccel2_cmd_pool_dhandle));
9304
9305 h->ioaccel2_blockFetchTable =
9306 kmalloc(((h->ioaccel_maxsg + 1) *
9307 sizeof(u32)), GFP_KERNEL);
9308
9309 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 9310 (h->ioaccel2_blockFetchTable == NULL)) {
9311 rc = -ENOMEM;
9312 goto clean_up;
9313 }
9314
9315 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
9316 if (rc)
aca9012a
SC		 9317 goto clean_up;
9318
9319 memset(h->ioaccel2_cmd_pool, 0,
9320 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
9321 return 0;
9322
9323clean_up:
1fb7c98a 9324 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 9325 return rc;
aca9012a
SC		 9326}
9327
105a3dbc
RE		 9328/* Free items allocated by hpsa_put_ctlr_into_performant_mode */
9329static void hpsa_free_performant_mode(struct ctlr_info *h)
9330{
9331 kfree(h->blockFetchTable);
9332 h->blockFetchTable = NULL;
9333 hpsa_free_reply_queues(h);
9334 hpsa_free_ioaccel1_cmd_and_bft(h);
9335 hpsa_free_ioaccel2_cmd_and_bft(h);
9336}
9337
9338/* return -ENODEV on error, 0 on success (or no action)
9339 * allocates numerous items that must be freed later
9340 */
9341static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 9342{
9343 u32 trans_support;
e1f7de0c
MG		 9344 unsigned long transMethod = CFGTBL_Trans_Performant |
9345 CFGTBL_Trans_use_short_tags;
105a3dbc 9346 int i, rc;
6c311b57 9347
02ec19c8 9348 if (hpsa_simple_mode)
105a3dbc 9349 return 0;
02ec19c8 9350
67c99a72 9351 trans_support = readl(&(h->cfgtable->TransportSupport));
9352 if (!(trans_support & PERFORMANT_MODE))
105a3dbc 9353 return 0;
67c99a72 9354
e1f7de0c
MG		 9355 /* Check for I/O accelerator mode support */
9356 if (trans_support & CFGTBL_Trans_io_accel1) {
9357 transMethod |= CFGTBL_Trans_io_accel1 |
9358 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 9359 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
9360 if (rc)
9361 return rc;
9362 } else if (trans_support & CFGTBL_Trans_io_accel2) {
9363 transMethod |= CFGTBL_Trans_io_accel2 |
aca9012a 9364 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 9365 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
9366 if (rc)
9367 return rc;
e1f7de0c
MG		 9368 }
9369
eee0f03a 9370 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 9371 hpsa_get_max_perf_mode_cmds(h);
6c311b57 9372 /* Performant mode ring buffer and supporting data structures */
072b0518 9373 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 9374
254f796b 9375 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 9376 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
9377 h->reply_queue_size,
9378 &(h->reply_queue[i].busaddr));
105a3dbc
RE		 9379 if (!h->reply_queue[i].head) {
9380 rc = -ENOMEM;
9381 goto clean1; /* rq, ioaccel */
9382 }
254f796b
MG		 9383 h->reply_queue[i].size = h->max_commands;
9384 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
9385 h->reply_queue[i].current_entry = 0;
9386 }
9387
6c311b57 9388 /* Need a block fetch table for performant mode */
d66ae08b 9389 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 9390 sizeof(u32)), GFP_KERNEL);
105a3dbc
RE		 9391 if (!h->blockFetchTable) {
9392 rc = -ENOMEM;
9393 goto clean1; /* rq, ioaccel */
9394 }
6c311b57 9395
105a3dbc
RE		 9396 rc = hpsa_enter_performant_mode(h, trans_support);
9397 if (rc)
9398 goto clean2; /* bft, rq, ioaccel */
9399 return 0;
303932fd 9400
105a3dbc 9401clean2: /* bft, rq, ioaccel */
303932fd 9402 kfree(h->blockFetchTable);
105a3dbc
RE		 9403 h->blockFetchTable = NULL;
9404clean1: /* rq, ioaccel */
9405 hpsa_free_reply_queues(h);
9406 hpsa_free_ioaccel1_cmd_and_bft(h);
9407 hpsa_free_ioaccel2_cmd_and_bft(h);
9408 return rc;
303932fd
DB		 9409}
9410
23100dd9 9411static int is_accelerated_cmd(struct CommandList *c)
76438d08 9412{
23100dd9
SC		 9413 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
9414}
9415
9416static void hpsa_drain_accel_commands(struct ctlr_info *h)
9417{
9418 struct CommandList *c = NULL;
f2405db8 9419 int i, accel_cmds_out;
281a7fd0 9420 int refcount;
76438d08 9421
f2405db8 9422 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 9423 accel_cmds_out = 0;
f2405db8 9424 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 9425 c = h->cmd_pool + i;
281a7fd0
WS		 9426 refcount = atomic_inc_return(&c->refcount);
9427 if (refcount > 1) /* Command is allocated */
9428 accel_cmds_out += is_accelerated_cmd(c);
9429 cmd_free(h, c);
f2405db8 9430 }
23100dd9 9431 if (accel_cmds_out <= 0)
281a7fd0 9432 break;
76438d08
SC		 9433 msleep(100);
9434 } while (1);
9435}
9436
d04e62b9
KB		 9437static struct hpsa_sas_phy *hpsa_alloc_sas_phy(
9438 struct hpsa_sas_port *hpsa_sas_port)
9439{
9440 struct hpsa_sas_phy *hpsa_sas_phy;
9441 struct sas_phy *phy;
9442
9443 hpsa_sas_phy = kzalloc(sizeof(*hpsa_sas_phy), GFP_KERNEL);
9444 if (!hpsa_sas_phy)
9445 return NULL;
9446
9447 phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev,
9448 hpsa_sas_port->next_phy_index);
9449 if (!phy) {
9450 kfree(hpsa_sas_phy);
9451 return NULL;
9452 }
9453
9454 hpsa_sas_port->next_phy_index++;
9455 hpsa_sas_phy->phy = phy;
9456 hpsa_sas_phy->parent_port = hpsa_sas_port;
9457
9458 return hpsa_sas_phy;
9459}
9460
9461static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy)
9462{
9463 struct sas_phy *phy = hpsa_sas_phy->phy;
9464
9465 sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy);
9466 sas_phy_free(phy);
9467 if (hpsa_sas_phy->added_to_port)
9468 list_del(&hpsa_sas_phy->phy_list_entry);
9469 kfree(hpsa_sas_phy);
9470}
9471
9472static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy)
9473{
9474 int rc;
9475 struct hpsa_sas_port *hpsa_sas_port;
9476 struct sas_phy *phy;
9477 struct sas_identify *identify;
9478
9479 hpsa_sas_port = hpsa_sas_phy->parent_port;
9480 phy = hpsa_sas_phy->phy;
9481
9482 identify = &phy->identify;
9483 memset(identify, 0, sizeof(*identify));
9484 identify->sas_address = hpsa_sas_port->sas_address;
9485 identify->device_type = SAS_END_DEVICE;
9486 identify->initiator_port_protocols = SAS_PROTOCOL_STP;
9487 identify->target_port_protocols = SAS_PROTOCOL_STP;
9488 phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
9489 phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
9490 phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN;
9491 phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN;
9492 phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN;
9493
9494 rc = sas_phy_add(hpsa_sas_phy->phy);
9495 if (rc)
9496 return rc;
9497
9498 sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy);
9499 list_add_tail(&hpsa_sas_phy->phy_list_entry,
9500 &hpsa_sas_port->phy_list_head);
9501 hpsa_sas_phy->added_to_port = true;
9502
9503 return 0;
9504}
9505
9506static int
9507 hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port,
9508 struct sas_rphy *rphy)
9509{
9510 struct sas_identify *identify;
9511
9512 identify = &rphy->identify;
9513 identify->sas_address = hpsa_sas_port->sas_address;
9514 identify->initiator_port_protocols = SAS_PROTOCOL_STP;
9515 identify->target_port_protocols = SAS_PROTOCOL_STP;
9516
9517 return sas_rphy_add(rphy);
9518}
9519
9520static struct hpsa_sas_port
9521 *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node,
9522 u64 sas_address)
9523{
9524 int rc;
9525 struct hpsa_sas_port *hpsa_sas_port;
9526 struct sas_port *port;
9527
9528 hpsa_sas_port = kzalloc(sizeof(*hpsa_sas_port), GFP_KERNEL);
9529 if (!hpsa_sas_port)
9530 return NULL;
9531
9532 INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head);
9533 hpsa_sas_port->parent_node = hpsa_sas_node;
9534
9535 port = sas_port_alloc_num(hpsa_sas_node->parent_dev);
9536 if (!port)
9537 goto free_hpsa_port;
9538
9539 rc = sas_port_add(port);
9540 if (rc)
9541 goto free_sas_port;
9542
9543 hpsa_sas_port->port = port;
9544 hpsa_sas_port->sas_address = sas_address;
9545 list_add_tail(&hpsa_sas_port->port_list_entry,
9546 &hpsa_sas_node->port_list_head);
9547
9548 return hpsa_sas_port;
9549
9550free_sas_port:
9551 sas_port_free(port);
9552free_hpsa_port:
9553 kfree(hpsa_sas_port);
9554
9555 return NULL;
9556}
9557
9558static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port)
9559{
9560 struct hpsa_sas_phy *hpsa_sas_phy;
9561 struct hpsa_sas_phy *next;
9562
9563 list_for_each_entry_safe(hpsa_sas_phy, next,
9564 &hpsa_sas_port->phy_list_head, phy_list_entry)
9565 hpsa_free_sas_phy(hpsa_sas_phy);
9566
9567 sas_port_delete(hpsa_sas_port->port);
9568 list_del(&hpsa_sas_port->port_list_entry);
9569 kfree(hpsa_sas_port);
9570}
9571
9572static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev)
9573{
9574 struct hpsa_sas_node *hpsa_sas_node;
9575
9576 hpsa_sas_node = kzalloc(sizeof(*hpsa_sas_node), GFP_KERNEL);
9577 if (hpsa_sas_node) {
9578 hpsa_sas_node->parent_dev = parent_dev;
9579 INIT_LIST_HEAD(&hpsa_sas_node->port_list_head);
9580 }
9581
9582 return hpsa_sas_node;
9583}
9584
9585static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node)
9586{
9587 struct hpsa_sas_port *hpsa_sas_port;
9588 struct hpsa_sas_port *next;
9589
9590 if (!hpsa_sas_node)
9591 return;
9592
9593 list_for_each_entry_safe(hpsa_sas_port, next,
9594 &hpsa_sas_node->port_list_head, port_list_entry)
9595 hpsa_free_sas_port(hpsa_sas_port);
9596
9597 kfree(hpsa_sas_node);
9598}
9599
9600static struct hpsa_scsi_dev_t
9601 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
9602 struct sas_rphy *rphy)
9603{
9604 int i;
9605 struct hpsa_scsi_dev_t *device;
9606
9607 for (i = 0; i < h->ndevices; i++) {
9608 device = h->dev[i];
9609 if (!device->sas_port)
9610 continue;
9611 if (device->sas_port->rphy == rphy)
9612 return device;
9613 }
9614
9615 return NULL;
9616}
9617
9618static int hpsa_add_sas_host(struct ctlr_info *h)
9619{
9620 int rc;
9621 struct device *parent_dev;
9622 struct hpsa_sas_node *hpsa_sas_node;
9623 struct hpsa_sas_port *hpsa_sas_port;
9624 struct hpsa_sas_phy *hpsa_sas_phy;
9625
9626 parent_dev = &h->scsi_host->shost_gendev;
9627
9628 hpsa_sas_node = hpsa_alloc_sas_node(parent_dev);
9629 if (!hpsa_sas_node)
9630 return -ENOMEM;
9631
9632 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address);
9633 if (!hpsa_sas_port) {
9634 rc = -ENODEV;
9635 goto free_sas_node;
9636 }
9637
9638 hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port);
9639 if (!hpsa_sas_phy) {
9640 rc = -ENODEV;
9641 goto free_sas_port;
9642 }
9643
9644 rc = hpsa_sas_port_add_phy(hpsa_sas_phy);
9645 if (rc)
9646 goto free_sas_phy;
9647
9648 h->sas_host = hpsa_sas_node;
9649
9650 return 0;
9651
9652free_sas_phy:
9653 hpsa_free_sas_phy(hpsa_sas_phy);
9654free_sas_port:
9655 hpsa_free_sas_port(hpsa_sas_port);
9656free_sas_node:
9657 hpsa_free_sas_node(hpsa_sas_node);
9658
9659 return rc;
9660}
9661
9662static void hpsa_delete_sas_host(struct ctlr_info *h)
9663{
9664 hpsa_free_sas_node(h->sas_host);
9665}
9666
9667static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
9668 struct hpsa_scsi_dev_t *device)
9669{
9670 int rc;
9671 struct hpsa_sas_port *hpsa_sas_port;
9672 struct sas_rphy *rphy;
9673
9674 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address);
9675 if (!hpsa_sas_port)
9676 return -ENOMEM;
9677
9678 rphy = sas_end_device_alloc(hpsa_sas_port->port);
9679 if (!rphy) {
9680 rc = -ENODEV;
9681 goto free_sas_port;
9682 }
9683
9684 hpsa_sas_port->rphy = rphy;
9685 device->sas_port = hpsa_sas_port;
9686
9687 rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy);
9688 if (rc)
9689 goto free_sas_port;
9690
9691 return 0;
9692
9693free_sas_port:
9694 hpsa_free_sas_port(hpsa_sas_port);
9695 device->sas_port = NULL;
9696
9697 return rc;
9698}
9699
9700static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device)
9701{
9702 if (device->sas_port) {
9703 hpsa_free_sas_port(device->sas_port);
9704 device->sas_port = NULL;
9705 }
9706}
9707
9708static int
9709hpsa_sas_get_linkerrors(struct sas_phy *phy)
9710{
9711 return 0;
9712}
9713
9714static int
9715hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier)
9716{
aa105695 9717 *identifier = 0;
d04e62b9
KB		 9718 return 0;
9719}
9720
9721static int
9722hpsa_sas_get_bay_identifier(struct sas_rphy *rphy)
9723{
9724 return -ENXIO;
9725}
9726
9727static int
9728hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset)
9729{
9730 return 0;
9731}
9732
9733static int
9734hpsa_sas_phy_enable(struct sas_phy *phy, int enable)
9735{
9736 return 0;
9737}
9738
9739static int
9740hpsa_sas_phy_setup(struct sas_phy *phy)
9741{
9742 return 0;
9743}
9744
9745static void
9746hpsa_sas_phy_release(struct sas_phy *phy)
9747{
9748}
9749
9750static int
9751hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates)
9752{
9753 return -EINVAL;
9754}
9755
9756/* SMP = Serial Management Protocol */
9757static int
9758hpsa_sas_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy,
9759struct request *req)
9760{
9761 return -EINVAL;
9762}
9763
9764static struct sas_function_template hpsa_sas_transport_functions = {
9765 .get_linkerrors = hpsa_sas_get_linkerrors,
9766 .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier,
9767 .get_bay_identifier = hpsa_sas_get_bay_identifier,
9768 .phy_reset = hpsa_sas_phy_reset,
9769 .phy_enable = hpsa_sas_phy_enable,
9770 .phy_setup = hpsa_sas_phy_setup,
9771 .phy_release = hpsa_sas_phy_release,
9772 .set_phy_speed = hpsa_sas_phy_speed,
9773 .smp_handler = hpsa_sas_smp_handler,
9774};
9775
edd16368
SC		 9776/*
9777 * This is it. Register the PCI driver information for the cards we control
9778 * the OS will call our registered routines when it finds one of our cards.
9779 */
9780static int __init hpsa_init(void)
9781{
d04e62b9
KB		 9782 int rc;
9783
9784 hpsa_sas_transport_template =
9785 sas_attach_transport(&hpsa_sas_transport_functions);
9786 if (!hpsa_sas_transport_template)
9787 return -ENODEV;
9788
9789 rc = pci_register_driver(&hpsa_pci_driver);
9790
9791 if (rc)
9792 sas_release_transport(hpsa_sas_transport_template);
9793
9794 return rc;
edd16368
SC		 9795}
9796
9797static void __exit hpsa_cleanup(void)
9798{
9799 pci_unregister_driver(&hpsa_pci_driver);
d04e62b9 9800 sas_release_transport(hpsa_sas_transport_template);
edd16368
SC		 9801}
9802
e1f7de0c
MG		 9803static void __attribute__((unused)) verify_offsets(void)
9804{
dd0e19f3
ST		 9805#define VERIFY_OFFSET(member, offset) \
9806 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
9807
9808 VERIFY_OFFSET(structure_size, 0);
9809 VERIFY_OFFSET(volume_blk_size, 4);
9810 VERIFY_OFFSET(volume_blk_cnt, 8);
9811 VERIFY_OFFSET(phys_blk_shift, 16);
9812 VERIFY_OFFSET(parity_rotation_shift, 17);
9813 VERIFY_OFFSET(strip_size, 18);
9814 VERIFY_OFFSET(disk_starting_blk, 20);
9815 VERIFY_OFFSET(disk_blk_cnt, 28);
9816 VERIFY_OFFSET(data_disks_per_row, 36);
9817 VERIFY_OFFSET(metadata_disks_per_row, 38);
9818 VERIFY_OFFSET(row_cnt, 40);
9819 VERIFY_OFFSET(layout_map_count, 42);
9820 VERIFY_OFFSET(flags, 44);
9821 VERIFY_OFFSET(dekindex, 46);
9822 /* VERIFY_OFFSET(reserved, 48 */
9823 VERIFY_OFFSET(data, 64);
9824
9825#undef VERIFY_OFFSET
9826
b66cc250
MM		 9827#define VERIFY_OFFSET(member, offset) \
9828 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
9829
9830 VERIFY_OFFSET(IU_type, 0);
9831 VERIFY_OFFSET(direction, 1);
9832 VERIFY_OFFSET(reply_queue, 2);
9833 /* VERIFY_OFFSET(reserved1, 3); */
9834 VERIFY_OFFSET(scsi_nexus, 4);
9835 VERIFY_OFFSET(Tag, 8);
9836 VERIFY_OFFSET(cdb, 16);
9837 VERIFY_OFFSET(cciss_lun, 32);
9838 VERIFY_OFFSET(data_len, 40);
9839 VERIFY_OFFSET(cmd_priority_task_attr, 44);
9840 VERIFY_OFFSET(sg_count, 45);
9841 /* VERIFY_OFFSET(reserved3 */
9842 VERIFY_OFFSET(err_ptr, 48);
9843 VERIFY_OFFSET(err_len, 56);
9844 /* VERIFY_OFFSET(reserved4 */
9845 VERIFY_OFFSET(sg, 64);
9846
9847#undef VERIFY_OFFSET
9848
e1f7de0c
MG		 9849#define VERIFY_OFFSET(member, offset) \
9850 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
9851
9852 VERIFY_OFFSET(dev_handle, 0x00);
9853 VERIFY_OFFSET(reserved1, 0x02);
9854 VERIFY_OFFSET(function, 0x03);
9855 VERIFY_OFFSET(reserved2, 0x04);
9856 VERIFY_OFFSET(err_info, 0x0C);
9857 VERIFY_OFFSET(reserved3, 0x10);
9858 VERIFY_OFFSET(err_info_len, 0x12);
9859 VERIFY_OFFSET(reserved4, 0x13);
9860 VERIFY_OFFSET(sgl_offset, 0x14);
9861 VERIFY_OFFSET(reserved5, 0x15);
9862 VERIFY_OFFSET(transfer_len, 0x1C);
9863 VERIFY_OFFSET(reserved6, 0x20);
9864 VERIFY_OFFSET(io_flags, 0x24);
9865 VERIFY_OFFSET(reserved7, 0x26);
9866 VERIFY_OFFSET(LUN, 0x34);
9867 VERIFY_OFFSET(control, 0x3C);
9868 VERIFY_OFFSET(CDB, 0x40);
9869 VERIFY_OFFSET(reserved8, 0x50);
9870 VERIFY_OFFSET(host_context_flags, 0x60);
9871 VERIFY_OFFSET(timeout_sec, 0x62);
9872 VERIFY_OFFSET(ReplyQueue, 0x64);
9873 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 9874 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 9875 VERIFY_OFFSET(host_addr, 0x70);
9876 VERIFY_OFFSET(CISS_LUN, 0x78);
9877 VERIFY_OFFSET(SG, 0x78 + 8);
9878#undef VERIFY_OFFSET
9879}
9880
edd16368
SC		 9881module_init(hpsa_init);
9882module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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