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hpsa: correct lun data caching bitmap definition
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
1358f6dc
DB		 3 * Copyright 2014-2015 PMC-Sierra, Inc.
4 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
edd16368
SC		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
1358f6dc 15 * Questions/Comments/Bugfixes to storagedev@pmcs.com
edd16368
SC		 16 *
17 */
18
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/types.h>
22#include <linux/pci.h>
e5a44df8 23#include <linux/pci-aspm.h>
edd16368
SC		 24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/fs.h>
28#include <linux/timer.h>
edd16368
SC		 29#include <linux/init.h>
30#include <linux/spinlock.h>
edd16368
SC		 31#include <linux/compat.h>
32#include <linux/blktrace_api.h>
33#include <linux/uaccess.h>
34#include <linux/io.h>
35#include <linux/dma-mapping.h>
36#include <linux/completion.h>
37#include <linux/moduleparam.h>
38#include <scsi/scsi.h>
39#include <scsi/scsi_cmnd.h>
40#include <scsi/scsi_device.h>
41#include <scsi/scsi_host.h>
667e23d4 42#include <scsi/scsi_tcq.h>
9437ac43 43#include <scsi/scsi_eh.h>
d04e62b9 44#include <scsi/scsi_transport_sas.h>
73153fe5 45#include <scsi/scsi_dbg.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
a0c12413 50#include <linux/jiffies.h>
42a91641 51#include <linux/percpu-defs.h>
094963da 52#include <linux/percpu.h>
2b08b3e9 53#include <asm/unaligned.h>
283b4a9b 54#include <asm/div64.h>
edd16368
SC		 55#include "hpsa_cmd.h"
56#include "hpsa.h"
57
ec2c3aa9
DB		 58/*
59 * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.'
60 * with an optional trailing '-' followed by a byte value (0-255).
61 */
62#define HPSA_DRIVER_VERSION "3.4.14-0"
edd16368 63#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 64#define HPSA "hpsa"
edd16368 65
007e7aa9
RE		 66/* How long to wait for CISS doorbell communication */
67#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
68#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
69#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
70#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 71#define MAX_IOCTL_CONFIG_WAIT 1000
72
73/*define how many times we will try a command because of bus resets */
74#define MAX_CMD_RETRIES 3
75
76/* Embedded module documentation macros - see modules.h */
77MODULE_AUTHOR("Hewlett-Packard Company");
78MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
79 HPSA_DRIVER_VERSION);
80MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
81MODULE_VERSION(HPSA_DRIVER_VERSION);
82MODULE_LICENSE("GPL");
83
84static int hpsa_allow_any;
85module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
86MODULE_PARM_DESC(hpsa_allow_any,
87 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 88static int hpsa_simple_mode;
89module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
90MODULE_PARM_DESC(hpsa_simple_mode,
91 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 92
93/* define the PCI info for the cards we can control */
94static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
131 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
132 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
133 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
134 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
fdfa4b6d 135 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
cbb47dcb
DB		 136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
137 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
138 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
139 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
140 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
8e616a5e
SC		 141 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
142 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
143 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
144 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
145 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 146 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 147 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 148 {0,}
149};
150
151MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
152
153/* board_id = Subsystem Device ID & Vendor ID
154 * product = Marketing Name for the board
155 * access = Address of the struct of function pointers
156 */
157static struct board_type products[] = {
edd16368
SC		 158 {0x3241103C, "Smart Array P212", &SA5_access},
159 {0x3243103C, "Smart Array P410", &SA5_access},
160 {0x3245103C, "Smart Array P410i", &SA5_access},
161 {0x3247103C, "Smart Array P411", &SA5_access},
162 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 163 {0x324A103C, "Smart Array P712m", &SA5_access},
164 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 165 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 166 {0x3350103C, "Smart Array P222", &SA5_access},
167 {0x3351103C, "Smart Array P420", &SA5_access},
168 {0x3352103C, "Smart Array P421", &SA5_access},
169 {0x3353103C, "Smart Array P822", &SA5_access},
170 {0x3354103C, "Smart Array P420i", &SA5_access},
171 {0x3355103C, "Smart Array P220i", &SA5_access},
172 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 173 {0x1921103C, "Smart Array P830i", &SA5_access},
174 {0x1922103C, "Smart Array P430", &SA5_access},
175 {0x1923103C, "Smart Array P431", &SA5_access},
176 {0x1924103C, "Smart Array P830", &SA5_access},
177 {0x1926103C, "Smart Array P731m", &SA5_access},
178 {0x1928103C, "Smart Array P230i", &SA5_access},
179 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 180 {0x21BD103C, "Smart Array P244br", &SA5_access},
181 {0x21BE103C, "Smart Array P741m", &SA5_access},
182 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
183 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 184 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 185 {0x21C2103C, "Smart Array P440", &SA5_access},
186 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 187 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 188 {0x21C5103C, "Smart Array P841", &SA5_access},
189 {0x21C6103C, "Smart HBA H244br", &SA5_access},
190 {0x21C7103C, "Smart HBA H240", &SA5_access},
191 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 192 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 193 {0x21CA103C, "Smart Array P246br", &SA5_access},
194 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 195 {0x21CC103C, "Smart Array", &SA5_access},
196 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 197 {0x21CE103C, "Smart HBA", &SA5_access},
fdfa4b6d 198 {0x05809005, "SmartHBA-SA", &SA5_access},
cbb47dcb
DB		 199 {0x05819005, "SmartHBA-SA 8i", &SA5_access},
200 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
201 {0x05839005, "SmartHBA-SA 8e", &SA5_access},
202 {0x05849005, "SmartHBA-SA 16i", &SA5_access},
203 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
8e616a5e
SC		 204 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
205 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
206 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
207 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
208 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 209 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
210};
211
d04e62b9
KB		 212static struct scsi_transport_template *hpsa_sas_transport_template;
213static int hpsa_add_sas_host(struct ctlr_info *h);
214static void hpsa_delete_sas_host(struct ctlr_info *h);
215static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
216 struct hpsa_scsi_dev_t *device);
217static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device);
218static struct hpsa_scsi_dev_t
219 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
220 struct sas_rphy *rphy);
221
a58e7e53
WS		 222#define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
223static const struct scsi_cmnd hpsa_cmd_busy;
224#define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
225static const struct scsi_cmnd hpsa_cmd_idle;
edd16368
SC		 226static int number_of_controllers;
227
10f66018
SC		 228static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
229static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 230static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 231
232#ifdef CONFIG_COMPAT
42a91641
DB		 233static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
234 void __user *arg);
edd16368
SC		 235#endif
236
237static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 238static struct CommandList *cmd_alloc(struct ctlr_info *h);
73153fe5
WS		 239static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
240static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
241 struct scsi_cmnd *scmd);
a2dac136 242static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 243 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 244 int cmd_type);
2c143342 245static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 246#define VPD_PAGE (1 << 8)
b48d9804 247#define HPSA_SIMPLE_ERROR_BITS 0x03
edd16368 248
f281233d 249static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 250static void hpsa_scan_start(struct Scsi_Host *);
251static int hpsa_scan_finished(struct Scsi_Host *sh,
252 unsigned long elapsed_time);
7c0a0229 253static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 254
255static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 256static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 257static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 258static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 259static void hpsa_slave_destroy(struct scsi_device *sdev);
260
8aa60681 261static void hpsa_update_scsi_devices(struct ctlr_info *h);
edd16368
SC		 262static int check_for_unit_attention(struct ctlr_info *h,
263 struct CommandList *c);
264static void check_ioctl_unit_attention(struct ctlr_info *h,
265 struct CommandList *c);
303932fd
DB		 266/* performant mode helper functions */
267static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 268 int nsgs, int min_blocks, u32 *bucket_map);
105a3dbc
RE		 269static void hpsa_free_performant_mode(struct ctlr_info *h);
270static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 271static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 272static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
273 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
274 u64 *cfg_offset);
275static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
276 unsigned long *memory_bar);
277static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
278static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
279 int wait_for_ready);
75167d2c 280static inline void finish_cmd(struct CommandList *c);
c706a795 281static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 282#define BOARD_NOT_READY 0
283#define BOARD_READY 1
23100dd9 284static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 285static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 286static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
287 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 288 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 289static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 290static u32 lockup_detected(struct ctlr_info *h);
291static int detect_controller_lockup(struct ctlr_info *h);
c2adae44 292static void hpsa_disable_rld_caching(struct ctlr_info *h);
d04e62b9
KB		 293static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
294 struct ReportExtendedLUNdata *buf, int bufsize);
34592254 295static int hpsa_luns_changed(struct ctlr_info *h);
edd16368 296
edd16368
SC		 297static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
298{
299 unsigned long *priv = shost_priv(sdev->host);
300 return (struct ctlr_info *) *priv;
301}
302
a23513e8
SC		 303static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
304{
305 unsigned long *priv = shost_priv(sh);
306 return (struct ctlr_info *) *priv;
307}
308
a58e7e53
WS		 309static inline bool hpsa_is_cmd_idle(struct CommandList *c)
310{
311 return c->scsi_cmd == SCSI_CMD_IDLE;
312}
313
d604f533
WS		 314static inline bool hpsa_is_pending_event(struct CommandList *c)
315{
316 return c->abort_pending || c->reset_pending;
317}
318
9437ac43
SC		 319/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
320static void decode_sense_data(const u8 *sense_data, int sense_data_len,
321 u8 *sense_key, u8 *asc, u8 *ascq)
322{
323 struct scsi_sense_hdr sshdr;
324 bool rc;
325
326 *sense_key = -1;
327 *asc = -1;
328 *ascq = -1;
329
330 if (sense_data_len < 1)
331 return;
332
333 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
334 if (rc) {
335 *sense_key = sshdr.sense_key;
336 *asc = sshdr.asc;
337 *ascq = sshdr.ascq;
338 }
339}
340
edd16368
SC		 341static int check_for_unit_attention(struct ctlr_info *h,
342 struct CommandList *c)
343{
9437ac43
SC		 344 u8 sense_key, asc, ascq;
345 int sense_len;
346
347 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
348 sense_len = sizeof(c->err_info->SenseInfo);
349 else
350 sense_len = c->err_info->SenseLen;
351
352 decode_sense_data(c->err_info->SenseInfo, sense_len,
353 &sense_key, &asc, &ascq);
81c27557 354 if (sense_key != UNIT_ATTENTION || asc == 0xff)
edd16368
SC		 355 return 0;
356
9437ac43 357 switch (asc) {
edd16368 358 case STATE_CHANGED:
9437ac43 359 dev_warn(&h->pdev->dev,
2946e82b
RE		 360 "%s: a state change detected, command retried\n",
361 h->devname);
edd16368
SC		 362 break;
363 case LUN_FAILED:
7f73695a 364 dev_warn(&h->pdev->dev,
2946e82b 365 "%s: LUN failure detected\n", h->devname);
edd16368
SC		 366 break;
367 case REPORT_LUNS_CHANGED:
7f73695a 368 dev_warn(&h->pdev->dev,
2946e82b 369 "%s: report LUN data changed\n", h->devname);
edd16368 370 /*
4f4eb9f1
ST		 371 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
372 * target (array) devices.
edd16368
SC		 373 */
374 break;
375 case POWER_OR_RESET:
2946e82b
RE		 376 dev_warn(&h->pdev->dev,
377 "%s: a power on or device reset detected\n",
378 h->devname);
edd16368
SC		 379 break;
380 case UNIT_ATTENTION_CLEARED:
2946e82b
RE		 381 dev_warn(&h->pdev->dev,
382 "%s: unit attention cleared by another initiator\n",
383 h->devname);
edd16368
SC		 384 break;
385 default:
2946e82b
RE		 386 dev_warn(&h->pdev->dev,
387 "%s: unknown unit attention detected\n",
388 h->devname);
edd16368
SC		 389 break;
390 }
391 return 1;
392}
393
852af20a
MB		 394static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
395{
396 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
397 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
398 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
399 return 0;
400 dev_warn(&h->pdev->dev, HPSA "device busy");
401 return 1;
402}
403
e985c58f
SC		 404static u32 lockup_detected(struct ctlr_info *h);
405static ssize_t host_show_lockup_detected(struct device *dev,
406 struct device_attribute *attr, char *buf)
407{
408 int ld;
409 struct ctlr_info *h;
410 struct Scsi_Host *shost = class_to_shost(dev);
411
412 h = shost_to_hba(shost);
413 ld = lockup_detected(h);
414
415 return sprintf(buf, "ld=%d\n", ld);
416}
417
da0697bd
ST		 418static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
419 struct device_attribute *attr,
420 const char *buf, size_t count)
421{
422 int status, len;
423 struct ctlr_info *h;
424 struct Scsi_Host *shost = class_to_shost(dev);
425 char tmpbuf[10];
426
427 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
428 return -EACCES;
429 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
430 strncpy(tmpbuf, buf, len);
431 tmpbuf[len] = '\0';
432 if (sscanf(tmpbuf, "%d", &status) != 1)
433 return -EINVAL;
434 h = shost_to_hba(shost);
435 h->acciopath_status = !!status;
436 dev_warn(&h->pdev->dev,
437 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
438 h->acciopath_status ? "enabled" : "disabled");
439 return count;
440}
441
2ba8bfc8
SC		 442static ssize_t host_store_raid_offload_debug(struct device *dev,
443 struct device_attribute *attr,
444 const char *buf, size_t count)
445{
446 int debug_level, len;
447 struct ctlr_info *h;
448 struct Scsi_Host *shost = class_to_shost(dev);
449 char tmpbuf[10];
450
451 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
452 return -EACCES;
453 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
454 strncpy(tmpbuf, buf, len);
455 tmpbuf[len] = '\0';
456 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
457 return -EINVAL;
458 if (debug_level < 0)
459 debug_level = 0;
460 h = shost_to_hba(shost);
461 h->raid_offload_debug = debug_level;
462 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
463 h->raid_offload_debug);
464 return count;
465}
466
edd16368
SC		 467static ssize_t host_store_rescan(struct device *dev,
468 struct device_attribute *attr,
469 const char *buf, size_t count)
470{
471 struct ctlr_info *h;
472 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 473 h = shost_to_hba(shost);
31468401 474 hpsa_scan_start(h->scsi_host);
edd16368
SC		 475 return count;
476}
477
d28ce020
SC		 478static ssize_t host_show_firmware_revision(struct device *dev,
479 struct device_attribute *attr, char *buf)
480{
481 struct ctlr_info *h;
482 struct Scsi_Host *shost = class_to_shost(dev);
483 unsigned char *fwrev;
484
485 h = shost_to_hba(shost);
486 if (!h->hba_inquiry_data)
487 return 0;
488 fwrev = &h->hba_inquiry_data[32];
489 return snprintf(buf, 20, "%c%c%c%c\n",
490 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
491}
492
94a13649
SC		 493static ssize_t host_show_commands_outstanding(struct device *dev,
494 struct device_attribute *attr, char *buf)
495{
496 struct Scsi_Host *shost = class_to_shost(dev);
497 struct ctlr_info *h = shost_to_hba(shost);
498
0cbf768e
SC		 499 return snprintf(buf, 20, "%d\n",
500 atomic_read(&h->commands_outstanding));
94a13649
SC		 501}
502
745a7a25
SC		 503static ssize_t host_show_transport_mode(struct device *dev,
504 struct device_attribute *attr, char *buf)
505{
506 struct ctlr_info *h;
507 struct Scsi_Host *shost = class_to_shost(dev);
508
509 h = shost_to_hba(shost);
510 return snprintf(buf, 20, "%s\n",
960a30e7 511 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 512 "performant" : "simple");
513}
514
da0697bd
ST		 515static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
516 struct device_attribute *attr, char *buf)
517{
518 struct ctlr_info *h;
519 struct Scsi_Host *shost = class_to_shost(dev);
520
521 h = shost_to_hba(shost);
522 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
523 (h->acciopath_status == 1) ? "enabled" : "disabled");
524}
525
46380786 526/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 527static u32 unresettable_controller[] = {
528 0x324a103C, /* Smart Array P712m */
9b5c48c2 529 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 530 0x3223103C, /* Smart Array P800 */
531 0x3234103C, /* Smart Array P400 */
532 0x3235103C, /* Smart Array P400i */
533 0x3211103C, /* Smart Array E200i */
534 0x3212103C, /* Smart Array E200 */
535 0x3213103C, /* Smart Array E200i */
536 0x3214103C, /* Smart Array E200i */
537 0x3215103C, /* Smart Array E200i */
538 0x3237103C, /* Smart Array E500 */
539 0x323D103C, /* Smart Array P700m */
7af0abbc 540 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 541 0x409C0E11, /* Smart Array 6400 */
542 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 543 0x40700E11, /* Smart Array 5300 */
544 0x40820E11, /* Smart Array 532 */
545 0x40830E11, /* Smart Array 5312 */
546 0x409A0E11, /* Smart Array 641 */
547 0x409B0E11, /* Smart Array 642 */
548 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 549};
550
46380786
SC		 551/* List of controllers which cannot even be soft reset */
552static u32 soft_unresettable_controller[] = {
7af0abbc 553 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 554 0x40700E11, /* Smart Array 5300 */
555 0x40820E11, /* Smart Array 532 */
556 0x40830E11, /* Smart Array 5312 */
557 0x409A0E11, /* Smart Array 641 */
558 0x409B0E11, /* Smart Array 642 */
559 0x40910E11, /* Smart Array 6i */
46380786
SC		 560 /* Exclude 640x boards. These are two pci devices in one slot
561 * which share a battery backed cache module. One controls the
562 * cache, the other accesses the cache through the one that controls
563 * it. If we reset the one controlling the cache, the other will
564 * likely not be happy. Just forbid resetting this conjoined mess.
565 * The 640x isn't really supported by hpsa anyway.
566 */
567 0x409C0E11, /* Smart Array 6400 */
568 0x409D0E11, /* Smart Array 6400 EM */
569};
570
9b5c48c2
SC		 571static u32 needs_abort_tags_swizzled[] = {
572 0x323D103C, /* Smart Array P700m */
573 0x324a103C, /* Smart Array P712m */
574 0x324b103C, /* SmartArray P711m */
575};
576
577static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 578{
579 int i;
580
9b5c48c2
SC		 581 for (i = 0; i < nelems; i++)
582 if (a[i] == board_id)
583 return 1;
584 return 0;
46380786
SC		 585}
586
9b5c48c2 587static int ctlr_is_hard_resettable(u32 board_id)
46380786 588{
9b5c48c2
SC		 589 return !board_id_in_array(unresettable_controller,
590 ARRAY_SIZE(unresettable_controller), board_id);
591}
46380786 592
9b5c48c2
SC		 593static int ctlr_is_soft_resettable(u32 board_id)
594{
595 return !board_id_in_array(soft_unresettable_controller,
596 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 597}
598
46380786
SC		 599static int ctlr_is_resettable(u32 board_id)
600{
601 return ctlr_is_hard_resettable(board_id) ||
602 ctlr_is_soft_resettable(board_id);
603}
604
9b5c48c2
SC		 605static int ctlr_needs_abort_tags_swizzled(u32 board_id)
606{
607 return board_id_in_array(needs_abort_tags_swizzled,
608 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
609}
610
941b1cda
SC		 611static ssize_t host_show_resettable(struct device *dev,
612 struct device_attribute *attr, char *buf)
613{
614 struct ctlr_info *h;
615 struct Scsi_Host *shost = class_to_shost(dev);
616
617 h = shost_to_hba(shost);
46380786 618 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 619}
620
edd16368
SC		 621static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
622{
623 return (scsi3addr[3] & 0xC0) == 0x40;
624}
625
f2ef0ce7 626static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
7c59a0d4 627 "1(+0)ADM", "UNKNOWN", "PHYS DRV"
edd16368 628};
6b80b18f
ST		 629#define HPSA_RAID_0 0
630#define HPSA_RAID_4 1
631#define HPSA_RAID_1 2 /* also used for RAID 10 */
632#define HPSA_RAID_5 3 /* also used for RAID 50 */
633#define HPSA_RAID_51 4
634#define HPSA_RAID_6 5 /* also used for RAID 60 */
635#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
7c59a0d4
DB		 636#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2)
637#define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1)
edd16368 638
f3f01730
KB		 639static inline bool is_logical_device(struct hpsa_scsi_dev_t *device)
640{
641 return !device->physical_device;
642}
edd16368
SC		 643
644static ssize_t raid_level_show(struct device *dev,
645 struct device_attribute *attr, char *buf)
646{
647 ssize_t l = 0;
82a72c0a 648 unsigned char rlevel;
edd16368
SC		 649 struct ctlr_info *h;
650 struct scsi_device *sdev;
651 struct hpsa_scsi_dev_t *hdev;
652 unsigned long flags;
653
654 sdev = to_scsi_device(dev);
655 h = sdev_to_hba(sdev);
656 spin_lock_irqsave(&h->lock, flags);
657 hdev = sdev->hostdata;
658 if (!hdev) {
659 spin_unlock_irqrestore(&h->lock, flags);
660 return -ENODEV;
661 }
662
663 /* Is this even a logical drive? */
f3f01730 664 if (!is_logical_device(hdev)) {
edd16368
SC		 665 spin_unlock_irqrestore(&h->lock, flags);
666 l = snprintf(buf, PAGE_SIZE, "N/A\n");
667 return l;
668 }
669
670 rlevel = hdev->raid_level;
671 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 672 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 673 rlevel = RAID_UNKNOWN;
674 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
675 return l;
676}
677
678static ssize_t lunid_show(struct device *dev,
679 struct device_attribute *attr, char *buf)
680{
681 struct ctlr_info *h;
682 struct scsi_device *sdev;
683 struct hpsa_scsi_dev_t *hdev;
684 unsigned long flags;
685 unsigned char lunid[8];
686
687 sdev = to_scsi_device(dev);
688 h = sdev_to_hba(sdev);
689 spin_lock_irqsave(&h->lock, flags);
690 hdev = sdev->hostdata;
691 if (!hdev) {
692 spin_unlock_irqrestore(&h->lock, flags);
693 return -ENODEV;
694 }
695 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
696 spin_unlock_irqrestore(&h->lock, flags);
697 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
698 lunid[0], lunid[1], lunid[2], lunid[3],
699 lunid[4], lunid[5], lunid[6], lunid[7]);
700}
701
702static ssize_t unique_id_show(struct device *dev,
703 struct device_attribute *attr, char *buf)
704{
705 struct ctlr_info *h;
706 struct scsi_device *sdev;
707 struct hpsa_scsi_dev_t *hdev;
708 unsigned long flags;
709 unsigned char sn[16];
710
711 sdev = to_scsi_device(dev);
712 h = sdev_to_hba(sdev);
713 spin_lock_irqsave(&h->lock, flags);
714 hdev = sdev->hostdata;
715 if (!hdev) {
716 spin_unlock_irqrestore(&h->lock, flags);
717 return -ENODEV;
718 }
719 memcpy(sn, hdev->device_id, sizeof(sn));
720 spin_unlock_irqrestore(&h->lock, flags);
721 return snprintf(buf, 16 * 2 + 2,
722 "%02X%02X%02X%02X%02X%02X%02X%02X"
723 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
724 sn[0], sn[1], sn[2], sn[3],
725 sn[4], sn[5], sn[6], sn[7],
726 sn[8], sn[9], sn[10], sn[11],
727 sn[12], sn[13], sn[14], sn[15]);
728}
729
c1988684
ST		 730static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
731 struct device_attribute *attr, char *buf)
732{
733 struct ctlr_info *h;
734 struct scsi_device *sdev;
735 struct hpsa_scsi_dev_t *hdev;
736 unsigned long flags;
737 int offload_enabled;
738
739 sdev = to_scsi_device(dev);
740 h = sdev_to_hba(sdev);
741 spin_lock_irqsave(&h->lock, flags);
742 hdev = sdev->hostdata;
743 if (!hdev) {
744 spin_unlock_irqrestore(&h->lock, flags);
745 return -ENODEV;
746 }
747 offload_enabled = hdev->offload_enabled;
748 spin_unlock_irqrestore(&h->lock, flags);
749 return snprintf(buf, 20, "%d\n", offload_enabled);
750}
751
8270b862 752#define MAX_PATHS 8
8270b862
JH		 753static ssize_t path_info_show(struct device *dev,
754 struct device_attribute *attr, char *buf)
755{
756 struct ctlr_info *h;
757 struct scsi_device *sdev;
758 struct hpsa_scsi_dev_t *hdev;
759 unsigned long flags;
760 int i;
761 int output_len = 0;
762 u8 box;
763 u8 bay;
764 u8 path_map_index = 0;
765 char *active;
766 unsigned char phys_connector[2];
8270b862 767
8270b862
JH		 768 sdev = to_scsi_device(dev);
769 h = sdev_to_hba(sdev);
770 spin_lock_irqsave(&h->devlock, flags);
771 hdev = sdev->hostdata;
772 if (!hdev) {
773 spin_unlock_irqrestore(&h->devlock, flags);
774 return -ENODEV;
775 }
776
777 bay = hdev->bay;
778 for (i = 0; i < MAX_PATHS; i++) {
779 path_map_index = 1<<i;
780 if (i == hdev->active_path_index)
781 active = "Active";
782 else if (hdev->path_map & path_map_index)
783 active = "Inactive";
784 else
785 continue;
786
1faf072c
RV		 787 output_len += scnprintf(buf + output_len,
788 PAGE_SIZE - output_len,
789 "[%d:%d:%d:%d] %20.20s ",
8270b862
JH		 790 h->scsi_host->host_no,
791 hdev->bus, hdev->target, hdev->lun,
792 scsi_device_type(hdev->devtype));
793
cca8f13b 794 if (hdev->devtype == TYPE_RAID || is_logical_device(hdev)) {
2708f295 795 output_len += scnprintf(buf + output_len,
1faf072c
RV		 796 PAGE_SIZE - output_len,
797 "%s\n", active);
8270b862
JH		 798 continue;
799 }
800
801 box = hdev->box[i];
802 memcpy(&phys_connector, &hdev->phys_connector[i],
803 sizeof(phys_connector));
804 if (phys_connector[0] < '0')
805 phys_connector[0] = '0';
806 if (phys_connector[1] < '0')
807 phys_connector[1] = '0';
cca8f13b 808 output_len += scnprintf(buf + output_len,
1faf072c 809 PAGE_SIZE - output_len,
8270b862
JH		 810 "PORT: %.2s ",
811 phys_connector);
af15ed36
DB		 812 if ((hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) &&
813 hdev->expose_device) {
8270b862 814 if (box == 0 || box == 0xFF) {
2708f295 815 output_len += scnprintf(buf + output_len,
1faf072c 816 PAGE_SIZE - output_len,
8270b862
JH		 817 "BAY: %hhu %s\n",
818 bay, active);
819 } else {
2708f295 820 output_len += scnprintf(buf + output_len,
1faf072c 821 PAGE_SIZE - output_len,
8270b862
JH		 822 "BOX: %hhu BAY: %hhu %s\n",
823 box, bay, active);
824 }
825 } else if (box != 0 && box != 0xFF) {
2708f295 826 output_len += scnprintf(buf + output_len,
1faf072c 827 PAGE_SIZE - output_len, "BOX: %hhu %s\n",
8270b862
JH		 828 box, active);
829 } else
2708f295 830 output_len += scnprintf(buf + output_len,
1faf072c 831 PAGE_SIZE - output_len, "%s\n", active);
8270b862
JH		 832 }
833
834 spin_unlock_irqrestore(&h->devlock, flags);
1faf072c 835 return output_len;
8270b862
JH		 836}
837
3f5eac3a
SC		 838static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
839static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
840static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
841static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 842static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
843 host_show_hp_ssd_smart_path_enabled, NULL);
8270b862 844static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
da0697bd
ST		 845static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
846 host_show_hp_ssd_smart_path_status,
847 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 848static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
849 host_store_raid_offload_debug);
3f5eac3a
SC		 850static DEVICE_ATTR(firmware_revision, S_IRUGO,
851 host_show_firmware_revision, NULL);
852static DEVICE_ATTR(commands_outstanding, S_IRUGO,
853 host_show_commands_outstanding, NULL);
854static DEVICE_ATTR(transport_mode, S_IRUGO,
855 host_show_transport_mode, NULL);
941b1cda
SC		 856static DEVICE_ATTR(resettable, S_IRUGO,
857 host_show_resettable, NULL);
e985c58f
SC		 858static DEVICE_ATTR(lockup_detected, S_IRUGO,
859 host_show_lockup_detected, NULL);
3f5eac3a
SC		 860
861static struct device_attribute *hpsa_sdev_attrs[] = {
862 &dev_attr_raid_level,
863 &dev_attr_lunid,
864 &dev_attr_unique_id,
c1988684 865 &dev_attr_hp_ssd_smart_path_enabled,
8270b862 866 &dev_attr_path_info,
3f5eac3a
SC		 867 NULL,
868};
869
870static struct device_attribute *hpsa_shost_attrs[] = {
871 &dev_attr_rescan,
872 &dev_attr_firmware_revision,
873 &dev_attr_commands_outstanding,
874 &dev_attr_transport_mode,
941b1cda 875 &dev_attr_resettable,
da0697bd 876 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 877 &dev_attr_raid_offload_debug,
fb53c439 878 &dev_attr_lockup_detected,
3f5eac3a
SC		 879 NULL,
880};
881
41ce4c35
SC		 882#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
883 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
884
3f5eac3a
SC		 885static struct scsi_host_template hpsa_driver_template = {
886 .module = THIS_MODULE,
f79cfec6
SC		 887 .name = HPSA,
888 .proc_name = HPSA,
3f5eac3a
SC		 889 .queuecommand = hpsa_scsi_queue_command,
890 .scan_start = hpsa_scan_start,
891 .scan_finished = hpsa_scan_finished,
7c0a0229 892 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 893 .this_id = -1,
894 .use_clustering = ENABLE_CLUSTERING,
75167d2c 895 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 896 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
897 .ioctl = hpsa_ioctl,
898 .slave_alloc = hpsa_slave_alloc,
41ce4c35 899 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 900 .slave_destroy = hpsa_slave_destroy,
901#ifdef CONFIG_COMPAT
902 .compat_ioctl = hpsa_compat_ioctl,
903#endif
904 .sdev_attrs = hpsa_sdev_attrs,
905 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 906 .max_sectors = 8192,
54b2b50c 907 .no_write_same = 1,
3f5eac3a
SC		 908};
909
254f796b 910static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 911{
912 u32 a;
072b0518 913 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 914
e1f7de0c
MG		 915 if (h->transMethod & CFGTBL_Trans_io_accel1)
916 return h->access.command_completed(h, q);
917
3f5eac3a 918 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 919 return h->access.command_completed(h, q);
3f5eac3a 920
254f796b
MG		 921 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
922 a = rq->head[rq->current_entry];
923 rq->current_entry++;
0cbf768e 924 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 925 } else {
926 a = FIFO_EMPTY;
927 }
928 /* Check for wraparound */
254f796b
MG		 929 if (rq->current_entry == h->max_commands) {
930 rq->current_entry = 0;
931 rq->wraparound ^= 1;
3f5eac3a
SC		 932 }
933 return a;
934}
935
c349775e
ST		 936/*
937 * There are some special bits in the bus address of the
938 * command that we have to set for the controller to know
939 * how to process the command:
940 *
941 * Normal performant mode:
942 * bit 0: 1 means performant mode, 0 means simple mode.
943 * bits 1-3 = block fetch table entry
944 * bits 4-6 = command type (== 0)
945 *
946 * ioaccel1 mode:
947 * bit 0 = "performant mode" bit.
948 * bits 1-3 = block fetch table entry
949 * bits 4-6 = command type (== 110)
950 * (command type is needed because ioaccel1 mode
951 * commands are submitted through the same register as normal
952 * mode commands, so this is how the controller knows whether
953 * the command is normal mode or ioaccel1 mode.)
954 *
955 * ioaccel2 mode:
956 * bit 0 = "performant mode" bit.
957 * bits 1-4 = block fetch table entry (note extra bit)
958 * bits 4-6 = not needed, because ioaccel2 mode has
959 * a separate special register for submitting commands.
960 */
961
25163bd5
WS		 962/*
963 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 964 * set bit 0 for pull model, bits 3-1 for block fetch
965 * register number
966 */
25163bd5
WS		 967#define DEFAULT_REPLY_QUEUE (-1)
968static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
969 int reply_queue)
3f5eac3a 970{
254f796b 971 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 972 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 973 if (unlikely(!h->msix_vector))
974 return;
975 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 976 c->Header.ReplyQueue =
804a5cb5 977 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 978 else
979 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 980 }
3f5eac3a
SC		 981}
982
c349775e 983static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 984 struct CommandList *c,
985 int reply_queue)
c349775e
ST		 986{
987 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
988
25163bd5
WS		 989 /*
990 * Tell the controller to post the reply to the queue for this
c349775e
ST		 991 * processor. This seems to give the best I/O throughput.
992 */
25163bd5
WS		 993 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
994 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
995 else
996 cp->ReplyQueue = reply_queue % h->nreply_queues;
997 /*
998 * Set the bits in the address sent down to include:
c349775e
ST		 999 * - performant mode bit (bit 0)
1000 * - pull count (bits 1-3)
1001 * - command type (bits 4-6)
1002 */
1003 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
1004 IOACCEL1_BUSADDR_CMDTYPE;
1005}
1006
8be986cc
SC		 1007static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
1008 struct CommandList *c,
1009 int reply_queue)
1010{
1011 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
1012 &h->ioaccel2_cmd_pool[c->cmdindex];
1013
1014 /* Tell the controller to post the reply to the queue for this
1015 * processor. This seems to give the best I/O throughput.
1016 */
1017 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1018 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1019 else
1020 cp->reply_queue = reply_queue % h->nreply_queues;
1021 /* Set the bits in the address sent down to include:
1022 * - performant mode bit not used in ioaccel mode 2
1023 * - pull count (bits 0-3)
1024 * - command type isn't needed for ioaccel2
1025 */
1026 c->busaddr |= h->ioaccel2_blockFetchTable[0];
1027}
1028
c349775e 1029static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1030 struct CommandList *c,
1031 int reply_queue)
c349775e
ST		 1032{
1033 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
1034
25163bd5
WS		 1035 /*
1036 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1037 * processor. This seems to give the best I/O throughput.
1038 */
25163bd5
WS		 1039 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1040 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1041 else
1042 cp->reply_queue = reply_queue % h->nreply_queues;
1043 /*
1044 * Set the bits in the address sent down to include:
c349775e
ST		 1045 * - performant mode bit not used in ioaccel mode 2
1046 * - pull count (bits 0-3)
1047 * - command type isn't needed for ioaccel2
1048 */
1049 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
1050}
1051
e85c5974
SC		 1052static int is_firmware_flash_cmd(u8 *cdb)
1053{
1054 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
1055}
1056
1057/*
1058 * During firmware flash, the heartbeat register may not update as frequently
1059 * as it should. So we dial down lockup detection during firmware flash. and
1060 * dial it back up when firmware flash completes.
1061 */
1062#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
1063#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
1064static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
1065 struct CommandList *c)
1066{
1067 if (!is_firmware_flash_cmd(c->Request.CDB))
1068 return;
1069 atomic_inc(&h->firmware_flash_in_progress);
1070 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
1071}
1072
1073static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
1074 struct CommandList *c)
1075{
1076 if (is_firmware_flash_cmd(c->Request.CDB) &&
1077 atomic_dec_and_test(&h->firmware_flash_in_progress))
1078 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
1079}
1080
25163bd5
WS		 1081static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
1082 struct CommandList *c, int reply_queue)
3f5eac3a 1083{
c05e8866
SC		 1084 dial_down_lockup_detection_during_fw_flash(h, c);
1085 atomic_inc(&h->commands_outstanding);
c349775e
ST		 1086 switch (c->cmd_type) {
1087 case CMD_IOACCEL1:
25163bd5 1088 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 1089 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 1090 break;
1091 case CMD_IOACCEL2:
25163bd5 1092 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 1093 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e 1094 break;
8be986cc
SC		 1095 case IOACCEL2_TMF:
1096 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
1097 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1098 break;
c349775e 1099 default:
25163bd5 1100 set_performant_mode(h, c, reply_queue);
c05e8866 1101 h->access.submit_command(h, c);
c349775e 1102 }
3f5eac3a
SC		 1103}
1104
a58e7e53 1105static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
25163bd5 1106{
d604f533 1107 if (unlikely(hpsa_is_pending_event(c)))
a58e7e53
WS		 1108 return finish_cmd(c);
1109
25163bd5
WS		 1110 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
1111}
1112
3f5eac3a
SC		 1113static inline int is_hba_lunid(unsigned char scsi3addr[])
1114{
1115 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
1116}
1117
1118static inline int is_scsi_rev_5(struct ctlr_info *h)
1119{
1120 if (!h->hba_inquiry_data)
1121 return 0;
1122 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1123 return 1;
1124 return 0;
1125}
1126
edd16368
SC		 1127static int hpsa_find_target_lun(struct ctlr_info *h,
1128 unsigned char scsi3addr[], int bus, int *target, int *lun)
1129{
1130 /* finds an unused bus, target, lun for a new physical device
1131 * assumes h->devlock is held
1132 */
1133 int i, found = 0;
cfe5badc 1134 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 1135
263d9401 1136 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 1137
1138 for (i = 0; i < h->ndevices; i++) {
1139 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 1140 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 1141 }
1142
263d9401
AM		 1143 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1144 if (i < HPSA_MAX_DEVICES) {
1145 /* *bus = 1; */
1146 *target = i;
1147 *lun = 0;
1148 found = 1;
edd16368
SC		 1149 }
1150 return !found;
1151}
1152
1d33d85d 1153static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
0d96ef5f
WS		 1154 struct hpsa_scsi_dev_t *dev, char *description)
1155{
7c59a0d4
DB		 1156#define LABEL_SIZE 25
1157 char label[LABEL_SIZE];
1158
9975ec9d
DB		 1159 if (h == NULL || h->pdev == NULL || h->scsi_host == NULL)
1160 return;
1161
7c59a0d4
DB		 1162 switch (dev->devtype) {
1163 case TYPE_RAID:
1164 snprintf(label, LABEL_SIZE, "controller");
1165 break;
1166 case TYPE_ENCLOSURE:
1167 snprintf(label, LABEL_SIZE, "enclosure");
1168 break;
1169 case TYPE_DISK:
af15ed36 1170 case TYPE_ZBC:
7c59a0d4
DB		 1171 if (dev->external)
1172 snprintf(label, LABEL_SIZE, "external");
1173 else if (!is_logical_dev_addr_mode(dev->scsi3addr))
1174 snprintf(label, LABEL_SIZE, "%s",
1175 raid_label[PHYSICAL_DRIVE]);
1176 else
1177 snprintf(label, LABEL_SIZE, "RAID-%s",
1178 dev->raid_level > RAID_UNKNOWN ? "?" :
1179 raid_label[dev->raid_level]);
1180 break;
1181 case TYPE_ROM:
1182 snprintf(label, LABEL_SIZE, "rom");
1183 break;
1184 case TYPE_TAPE:
1185 snprintf(label, LABEL_SIZE, "tape");
1186 break;
1187 case TYPE_MEDIUM_CHANGER:
1188 snprintf(label, LABEL_SIZE, "changer");
1189 break;
1190 default:
1191 snprintf(label, LABEL_SIZE, "UNKNOWN");
1192 break;
1193 }
1194
0d96ef5f 1195 dev_printk(level, &h->pdev->dev,
7c59a0d4 1196 "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n",
0d96ef5f
WS		 1197 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1198 description,
1199 scsi_device_type(dev->devtype),
1200 dev->vendor,
1201 dev->model,
7c59a0d4 1202 label,
0d96ef5f
WS		 1203 dev->offload_config ? '+' : '-',
1204 dev->offload_enabled ? '+' : '-',
2a168208 1205 dev->expose_device);
0d96ef5f
WS		 1206}
1207
edd16368 1208/* Add an entry into h->dev[] array. */
8aa60681 1209static int hpsa_scsi_add_entry(struct ctlr_info *h,
edd16368
SC		 1210 struct hpsa_scsi_dev_t *device,
1211 struct hpsa_scsi_dev_t *added[], int *nadded)
1212{
1213 /* assumes h->devlock is held */
1214 int n = h->ndevices;
1215 int i;
1216 unsigned char addr1[8], addr2[8];
1217 struct hpsa_scsi_dev_t *sd;
1218
cfe5badc 1219 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1220 dev_err(&h->pdev->dev, "too many devices, some will be "
1221 "inaccessible.\n");
1222 return -1;
1223 }
1224
1225 /* physical devices do not have lun or target assigned until now. */
1226 if (device->lun != -1)
1227 /* Logical device, lun is already assigned. */
1228 goto lun_assigned;
1229
1230 /* If this device a non-zero lun of a multi-lun device
1231 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1232 * unit no, zero otherwise.
edd16368
SC		 1233 */
1234 if (device->scsi3addr[4] == 0) {
1235 /* This is not a non-zero lun of a multi-lun device */
1236 if (hpsa_find_target_lun(h, device->scsi3addr,
1237 device->bus, &device->target, &device->lun) != 0)
1238 return -1;
1239 goto lun_assigned;
1240 }
1241
1242 /* This is a non-zero lun of a multi-lun device.
1243 * Search through our list and find the device which
9a4178b7 1244 * has the same 8 byte LUN address, excepting byte 4 and 5.
edd16368
SC		 1245 * Assign the same bus and target for this new LUN.
1246 * Use the logical unit number from the firmware.
1247 */
1248 memcpy(addr1, device->scsi3addr, 8);
1249 addr1[4] = 0;
9a4178b7 1250 addr1[5] = 0;
edd16368
SC		 1251 for (i = 0; i < n; i++) {
1252 sd = h->dev[i];
1253 memcpy(addr2, sd->scsi3addr, 8);
1254 addr2[4] = 0;
9a4178b7 1255 addr2[5] = 0;
1256 /* differ only in byte 4 and 5? */
edd16368
SC		 1257 if (memcmp(addr1, addr2, 8) == 0) {
1258 device->bus = sd->bus;
1259 device->target = sd->target;
1260 device->lun = device->scsi3addr[4];
1261 break;
1262 }
1263 }
1264 if (device->lun == -1) {
1265 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1266 " suspect firmware bug or unsupported hardware "
1267 "configuration.\n");
1268 return -1;
1269 }
1270
1271lun_assigned:
1272
1273 h->dev[n] = device;
1274 h->ndevices++;
1275 added[*nadded] = device;
1276 (*nadded)++;
0d96ef5f 1277 hpsa_show_dev_msg(KERN_INFO, h, device,
2a168208 1278 device->expose_device ? "added" : "masked");
a473d86c
RE		 1279 device->offload_to_be_enabled = device->offload_enabled;
1280 device->offload_enabled = 0;
edd16368
SC		 1281 return 0;
1282}
1283
bd9244f7 1284/* Update an entry in h->dev[] array. */
8aa60681 1285static void hpsa_scsi_update_entry(struct ctlr_info *h,
bd9244f7
ST		 1286 int entry, struct hpsa_scsi_dev_t *new_entry)
1287{
a473d86c 1288 int offload_enabled;
bd9244f7
ST		 1289 /* assumes h->devlock is held */
1290 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1291
1292 /* Raid level changed. */
1293 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1294
03383736
DB		 1295 /* Raid offload parameters changed. Careful about the ordering. */
1296 if (new_entry->offload_config && new_entry->offload_enabled) {
1297 /*
1298 * if drive is newly offload_enabled, we want to copy the
1299 * raid map data first. If previously offload_enabled and
1300 * offload_config were set, raid map data had better be
1301 * the same as it was before. if raid map data is changed
1302 * then it had better be the case that
1303 * h->dev[entry]->offload_enabled is currently 0.
1304 */
1305 h->dev[entry]->raid_map = new_entry->raid_map;
1306 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1307 }
a3144e0b
JH		 1308 if (new_entry->hba_ioaccel_enabled) {
1309 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1310 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1311 }
1312 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1313 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1314 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1315 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1316
41ce4c35
SC		 1317 /*
1318 * We can turn off ioaccel offload now, but need to delay turning
1319 * it on until we can update h->dev[entry]->phys_disk[], but we
1320 * can't do that until all the devices are updated.
1321 */
1322 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1323 if (!new_entry->offload_enabled)
1324 h->dev[entry]->offload_enabled = 0;
1325
a473d86c
RE		 1326 offload_enabled = h->dev[entry]->offload_enabled;
1327 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1328 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1329 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1330}
1331
2a8ccf31 1332/* Replace an entry from h->dev[] array. */
8aa60681 1333static void hpsa_scsi_replace_entry(struct ctlr_info *h,
2a8ccf31
SC		 1334 int entry, struct hpsa_scsi_dev_t *new_entry,
1335 struct hpsa_scsi_dev_t *added[], int *nadded,
1336 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1337{
1338 /* assumes h->devlock is held */
cfe5badc 1339 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1340 removed[*nremoved] = h->dev[entry];
1341 (*nremoved)++;
01350d05
SC		 1342
1343 /*
1344 * New physical devices won't have target/lun assigned yet
1345 * so we need to preserve the values in the slot we are replacing.
1346 */
1347 if (new_entry->target == -1) {
1348 new_entry->target = h->dev[entry]->target;
1349 new_entry->lun = h->dev[entry]->lun;
1350 }
1351
2a8ccf31
SC		 1352 h->dev[entry] = new_entry;
1353 added[*nadded] = new_entry;
1354 (*nadded)++;
0d96ef5f 1355 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1356 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1357 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1358}
1359
edd16368 1360/* Remove an entry from h->dev[] array. */
8aa60681 1361static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
edd16368
SC		 1362 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1363{
1364 /* assumes h->devlock is held */
1365 int i;
1366 struct hpsa_scsi_dev_t *sd;
1367
cfe5badc 1368 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1369
1370 sd = h->dev[entry];
1371 removed[*nremoved] = h->dev[entry];
1372 (*nremoved)++;
1373
1374 for (i = entry; i < h->ndevices-1; i++)
1375 h->dev[i] = h->dev[i+1];
1376 h->ndevices--;
0d96ef5f 1377 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1378}
1379
1380#define SCSI3ADDR_EQ(a, b) ( \
1381 (a)[7] == (b)[7] && \
1382 (a)[6] == (b)[6] && \
1383 (a)[5] == (b)[5] && \
1384 (a)[4] == (b)[4] && \
1385 (a)[3] == (b)[3] && \
1386 (a)[2] == (b)[2] && \
1387 (a)[1] == (b)[1] && \
1388 (a)[0] == (b)[0])
1389
1390static void fixup_botched_add(struct ctlr_info *h,
1391 struct hpsa_scsi_dev_t *added)
1392{
1393 /* called when scsi_add_device fails in order to re-adjust
1394 * h->dev[] to match the mid layer's view.
1395 */
1396 unsigned long flags;
1397 int i, j;
1398
1399 spin_lock_irqsave(&h->lock, flags);
1400 for (i = 0; i < h->ndevices; i++) {
1401 if (h->dev[i] == added) {
1402 for (j = i; j < h->ndevices-1; j++)
1403 h->dev[j] = h->dev[j+1];
1404 h->ndevices--;
1405 break;
1406 }
1407 }
1408 spin_unlock_irqrestore(&h->lock, flags);
1409 kfree(added);
1410}
1411
1412static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1413 struct hpsa_scsi_dev_t *dev2)
1414{
edd16368
SC		 1415 /* we compare everything except lun and target as these
1416 * are not yet assigned. Compare parts likely
1417 * to differ first
1418 */
1419 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1420 sizeof(dev1->scsi3addr)) != 0)
1421 return 0;
1422 if (memcmp(dev1->device_id, dev2->device_id,
1423 sizeof(dev1->device_id)) != 0)
1424 return 0;
1425 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1426 return 0;
1427 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1428 return 0;
edd16368
SC		 1429 if (dev1->devtype != dev2->devtype)
1430 return 0;
edd16368
SC		 1431 if (dev1->bus != dev2->bus)
1432 return 0;
1433 return 1;
1434}
1435
bd9244f7
ST		 1436static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1437 struct hpsa_scsi_dev_t *dev2)
1438{
1439 /* Device attributes that can change, but don't mean
1440 * that the device is a different device, nor that the OS
1441 * needs to be told anything about the change.
1442 */
1443 if (dev1->raid_level != dev2->raid_level)
1444 return 1;
250fb125
SC		 1445 if (dev1->offload_config != dev2->offload_config)
1446 return 1;
1447 if (dev1->offload_enabled != dev2->offload_enabled)
1448 return 1;
93849508
DB		 1449 if (!is_logical_dev_addr_mode(dev1->scsi3addr))
1450 if (dev1->queue_depth != dev2->queue_depth)
1451 return 1;
bd9244f7
ST		 1452 return 0;
1453}
1454
edd16368
SC		 1455/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1456 * and return needle location in *index. If scsi3addr matches, but not
1457 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1458 * location in *index.
1459 * In the case of a minor device attribute change, such as RAID level, just
1460 * return DEVICE_UPDATED, along with the updated device's location in index.
1461 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1462 */
1463static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1464 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1465 int *index)
1466{
1467 int i;
1468#define DEVICE_NOT_FOUND 0
1469#define DEVICE_CHANGED 1
1470#define DEVICE_SAME 2
bd9244f7 1471#define DEVICE_UPDATED 3
1d33d85d
DB		 1472 if (needle == NULL)
1473 return DEVICE_NOT_FOUND;
1474
edd16368 1475 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1476 if (haystack[i] == NULL) /* previously removed. */
1477 continue;
edd16368
SC		 1478 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1479 *index = i;
bd9244f7
ST		 1480 if (device_is_the_same(needle, haystack[i])) {
1481 if (device_updated(needle, haystack[i]))
1482 return DEVICE_UPDATED;
edd16368 1483 return DEVICE_SAME;
bd9244f7 1484 } else {
9846590e
SC		 1485 /* Keep offline devices offline */
1486 if (needle->volume_offline)
1487 return DEVICE_NOT_FOUND;
edd16368 1488 return DEVICE_CHANGED;
bd9244f7 1489 }
edd16368
SC		 1490 }
1491 }
1492 *index = -1;
1493 return DEVICE_NOT_FOUND;
1494}
1495
9846590e
SC		 1496static void hpsa_monitor_offline_device(struct ctlr_info *h,
1497 unsigned char scsi3addr[])
1498{
1499 struct offline_device_entry *device;
1500 unsigned long flags;
1501
1502 /* Check to see if device is already on the list */
1503 spin_lock_irqsave(&h->offline_device_lock, flags);
1504 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1505 if (memcmp(device->scsi3addr, scsi3addr,
1506 sizeof(device->scsi3addr)) == 0) {
1507 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1508 return;
1509 }
1510 }
1511 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1512
1513 /* Device is not on the list, add it. */
1514 device = kmalloc(sizeof(*device), GFP_KERNEL);
1515 if (!device) {
1516 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1517 return;
1518 }
1519 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1520 spin_lock_irqsave(&h->offline_device_lock, flags);
1521 list_add_tail(&device->offline_list, &h->offline_device_list);
1522 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1523}
1524
1525/* Print a message explaining various offline volume states */
1526static void hpsa_show_volume_status(struct ctlr_info *h,
1527 struct hpsa_scsi_dev_t *sd)
1528{
1529 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1530 dev_info(&h->pdev->dev,
1531 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1532 h->scsi_host->host_no,
1533 sd->bus, sd->target, sd->lun);
1534 switch (sd->volume_offline) {
1535 case HPSA_LV_OK:
1536 break;
1537 case HPSA_LV_UNDERGOING_ERASE:
1538 dev_info(&h->pdev->dev,
1539 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1540 h->scsi_host->host_no,
1541 sd->bus, sd->target, sd->lun);
1542 break;
5ca01204
SB		 1543 case HPSA_LV_NOT_AVAILABLE:
1544 dev_info(&h->pdev->dev,
1545 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
1546 h->scsi_host->host_no,
1547 sd->bus, sd->target, sd->lun);
1548 break;
9846590e
SC		 1549 case HPSA_LV_UNDERGOING_RPI:
1550 dev_info(&h->pdev->dev,
5ca01204 1551 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
9846590e
SC		 1552 h->scsi_host->host_no,
1553 sd->bus, sd->target, sd->lun);
1554 break;
1555 case HPSA_LV_PENDING_RPI:
1556 dev_info(&h->pdev->dev,
5ca01204
SB		 1557 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1558 h->scsi_host->host_no,
1559 sd->bus, sd->target, sd->lun);
9846590e
SC		 1560 break;
1561 case HPSA_LV_ENCRYPTED_NO_KEY:
1562 dev_info(&h->pdev->dev,
1563 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1564 h->scsi_host->host_no,
1565 sd->bus, sd->target, sd->lun);
1566 break;
1567 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1568 dev_info(&h->pdev->dev,
1569 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1570 h->scsi_host->host_no,
1571 sd->bus, sd->target, sd->lun);
1572 break;
1573 case HPSA_LV_UNDERGOING_ENCRYPTION:
1574 dev_info(&h->pdev->dev,
1575 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1576 h->scsi_host->host_no,
1577 sd->bus, sd->target, sd->lun);
1578 break;
1579 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1580 dev_info(&h->pdev->dev,
1581 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1582 h->scsi_host->host_no,
1583 sd->bus, sd->target, sd->lun);
1584 break;
1585 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1586 dev_info(&h->pdev->dev,
1587 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1588 h->scsi_host->host_no,
1589 sd->bus, sd->target, sd->lun);
1590 break;
1591 case HPSA_LV_PENDING_ENCRYPTION:
1592 dev_info(&h->pdev->dev,
1593 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1594 h->scsi_host->host_no,
1595 sd->bus, sd->target, sd->lun);
1596 break;
1597 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1598 dev_info(&h->pdev->dev,
1599 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1600 h->scsi_host->host_no,
1601 sd->bus, sd->target, sd->lun);
1602 break;
1603 }
1604}
1605
03383736
DB		 1606/*
1607 * Figure the list of physical drive pointers for a logical drive with
1608 * raid offload configured.
1609 */
1610static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1611 struct hpsa_scsi_dev_t *dev[], int ndevices,
1612 struct hpsa_scsi_dev_t *logical_drive)
1613{
1614 struct raid_map_data *map = &logical_drive->raid_map;
1615 struct raid_map_disk_data *dd = &map->data[0];
1616 int i, j;
1617 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1618 le16_to_cpu(map->metadata_disks_per_row);
1619 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1620 le16_to_cpu(map->layout_map_count) *
1621 total_disks_per_row;
1622 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1623 total_disks_per_row;
1624 int qdepth;
1625
1626 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1627 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1628
d604f533
WS		 1629 logical_drive->nphysical_disks = nraid_map_entries;
1630
03383736
DB		 1631 qdepth = 0;
1632 for (i = 0; i < nraid_map_entries; i++) {
1633 logical_drive->phys_disk[i] = NULL;
1634 if (!logical_drive->offload_config)
1635 continue;
1636 for (j = 0; j < ndevices; j++) {
1d33d85d
DB		 1637 if (dev[j] == NULL)
1638 continue;
03383736
DB		 1639 if (dev[j]->devtype != TYPE_DISK)
1640 continue;
af15ed36
DB		 1641 if (dev[j]->devtype != TYPE_ZBC)
1642 continue;
f3f01730 1643 if (is_logical_device(dev[j]))
03383736
DB		 1644 continue;
1645 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1646 continue;
1647
1648 logical_drive->phys_disk[i] = dev[j];
1649 if (i < nphys_disk)
1650 qdepth = min(h->nr_cmds, qdepth +
1651 logical_drive->phys_disk[i]->queue_depth);
1652 break;
1653 }
1654
1655 /*
1656 * This can happen if a physical drive is removed and
1657 * the logical drive is degraded. In that case, the RAID
1658 * map data will refer to a physical disk which isn't actually
1659 * present. And in that case offload_enabled should already
1660 * be 0, but we'll turn it off here just in case
1661 */
1662 if (!logical_drive->phys_disk[i]) {
1663 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1664 logical_drive->offload_to_be_enabled = 0;
1665 logical_drive->queue_depth = 8;
03383736
DB		 1666 }
1667 }
1668 if (nraid_map_entries)
1669 /*
1670 * This is correct for reads, too high for full stripe writes,
1671 * way too high for partial stripe writes
1672 */
1673 logical_drive->queue_depth = qdepth;
1674 else
1675 logical_drive->queue_depth = h->nr_cmds;
1676}
1677
1678static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1679 struct hpsa_scsi_dev_t *dev[], int ndevices)
1680{
1681 int i;
1682
1683 for (i = 0; i < ndevices; i++) {
1d33d85d
DB		 1684 if (dev[i] == NULL)
1685 continue;
03383736
DB		 1686 if (dev[i]->devtype != TYPE_DISK)
1687 continue;
af15ed36
DB		 1688 if (dev[i]->devtype != TYPE_ZBC)
1689 continue;
f3f01730 1690 if (!is_logical_device(dev[i]))
03383736 1691 continue;
41ce4c35
SC		 1692
1693 /*
1694 * If offload is currently enabled, the RAID map and
1695 * phys_disk[] assignment *better* not be changing
1696 * and since it isn't changing, we do not need to
1697 * update it.
1698 */
1699 if (dev[i]->offload_enabled)
1700 continue;
1701
03383736
DB		 1702 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1703 }
1704}
1705
096ccff4
KB		 1706static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
1707{
1708 int rc = 0;
1709
1710 if (!h->scsi_host)
1711 return 1;
1712
d04e62b9
KB		 1713 if (is_logical_device(device)) /* RAID */
1714 rc = scsi_add_device(h->scsi_host, device->bus,
096ccff4 1715 device->target, device->lun);
d04e62b9
KB		 1716 else /* HBA */
1717 rc = hpsa_add_sas_device(h->sas_host, device);
1718
096ccff4
KB		 1719 return rc;
1720}
1721
1722static void hpsa_remove_device(struct ctlr_info *h,
1723 struct hpsa_scsi_dev_t *device)
1724{
1725 struct scsi_device *sdev = NULL;
1726
1727 if (!h->scsi_host)
1728 return;
1729
d04e62b9
KB		 1730 if (is_logical_device(device)) { /* RAID */
1731 sdev = scsi_device_lookup(h->scsi_host, device->bus,
096ccff4 1732 device->target, device->lun);
d04e62b9
KB		 1733 if (sdev) {
1734 scsi_remove_device(sdev);
1735 scsi_device_put(sdev);
1736 } else {
1737 /*
1738 * We don't expect to get here. Future commands
1739 * to this device will get a selection timeout as
1740 * if the device were gone.
1741 */
1742 hpsa_show_dev_msg(KERN_WARNING, h, device,
096ccff4 1743 "didn't find device for removal.");
d04e62b9
KB		 1744 }
1745 } else /* HBA */
1746 hpsa_remove_sas_device(device);
096ccff4
KB		 1747}
1748
8aa60681 1749static void adjust_hpsa_scsi_table(struct ctlr_info *h,
edd16368
SC		 1750 struct hpsa_scsi_dev_t *sd[], int nsds)
1751{
1752 /* sd contains scsi3 addresses and devtypes, and inquiry
1753 * data. This function takes what's in sd to be the current
1754 * reality and updates h->dev[] to reflect that reality.
1755 */
1756 int i, entry, device_change, changes = 0;
1757 struct hpsa_scsi_dev_t *csd;
1758 unsigned long flags;
1759 struct hpsa_scsi_dev_t **added, **removed;
1760 int nadded, nremoved;
edd16368 1761
da03ded0
DB		 1762 /*
1763 * A reset can cause a device status to change
1764 * re-schedule the scan to see what happened.
1765 */
1766 if (h->reset_in_progress) {
1767 h->drv_req_rescan = 1;
1768 return;
1769 }
edd16368 1770
cfe5badc
ST		 1771 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1772 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1773
1774 if (!added || !removed) {
1775 dev_warn(&h->pdev->dev, "out of memory in "
1776 "adjust_hpsa_scsi_table\n");
1777 goto free_and_out;
1778 }
1779
1780 spin_lock_irqsave(&h->devlock, flags);
1781
1782 /* find any devices in h->dev[] that are not in
1783 * sd[] and remove them from h->dev[], and for any
1784 * devices which have changed, remove the old device
1785 * info and add the new device info.
bd9244f7
ST		 1786 * If minor device attributes change, just update
1787 * the existing device structure.
edd16368
SC		 1788 */
1789 i = 0;
1790 nremoved = 0;
1791 nadded = 0;
1792 while (i < h->ndevices) {
1793 csd = h->dev[i];
1794 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1795 if (device_change == DEVICE_NOT_FOUND) {
1796 changes++;
8aa60681 1797 hpsa_scsi_remove_entry(h, i, removed, &nremoved);
edd16368
SC		 1798 continue; /* remove ^^^, hence i not incremented */
1799 } else if (device_change == DEVICE_CHANGED) {
1800 changes++;
8aa60681 1801 hpsa_scsi_replace_entry(h, i, sd[entry],
2a8ccf31 1802 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1803 /* Set it to NULL to prevent it from being freed
1804 * at the bottom of hpsa_update_scsi_devices()
1805 */
1806 sd[entry] = NULL;
bd9244f7 1807 } else if (device_change == DEVICE_UPDATED) {
8aa60681 1808 hpsa_scsi_update_entry(h, i, sd[entry]);
edd16368
SC		 1809 }
1810 i++;
1811 }
1812
1813 /* Now, make sure every device listed in sd[] is also
1814 * listed in h->dev[], adding them if they aren't found
1815 */
1816
1817 for (i = 0; i < nsds; i++) {
1818 if (!sd[i]) /* if already added above. */
1819 continue;
9846590e
SC		 1820
1821 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1822 * as the SCSI mid-layer does not handle such devices well.
1823 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1824 * at 160Hz, and prevents the system from coming up.
1825 */
1826 if (sd[i]->volume_offline) {
1827 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1828 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1829 continue;
1830 }
1831
edd16368
SC		 1832 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1833 h->ndevices, &entry);
1834 if (device_change == DEVICE_NOT_FOUND) {
1835 changes++;
8aa60681 1836 if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
edd16368
SC		 1837 break;
1838 sd[i] = NULL; /* prevent from being freed later. */
1839 } else if (device_change == DEVICE_CHANGED) {
1840 /* should never happen... */
1841 changes++;
1842 dev_warn(&h->pdev->dev,
1843 "device unexpectedly changed.\n");
1844 /* but if it does happen, we just ignore that device */
1845 }
1846 }
41ce4c35
SC		 1847 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1848
1849 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1850 * any logical drives that need it enabled.
1851 */
1d33d85d
DB		 1852 for (i = 0; i < h->ndevices; i++) {
1853 if (h->dev[i] == NULL)
1854 continue;
41ce4c35 1855 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1d33d85d 1856 }
41ce4c35 1857
edd16368
SC		 1858 spin_unlock_irqrestore(&h->devlock, flags);
1859
9846590e
SC		 1860 /* Monitor devices which are in one of several NOT READY states to be
1861 * brought online later. This must be done without holding h->devlock,
1862 * so don't touch h->dev[]
1863 */
1864 for (i = 0; i < nsds; i++) {
1865 if (!sd[i]) /* if already added above. */
1866 continue;
1867 if (sd[i]->volume_offline)
1868 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1869 }
1870
edd16368
SC		 1871 /* Don't notify scsi mid layer of any changes the first time through
1872 * (or if there are no changes) scsi_scan_host will do it later the
1873 * first time through.
1874 */
8aa60681 1875 if (!changes)
edd16368
SC		 1876 goto free_and_out;
1877
edd16368
SC		 1878 /* Notify scsi mid layer of any removed devices */
1879 for (i = 0; i < nremoved; i++) {
1d33d85d
DB		 1880 if (removed[i] == NULL)
1881 continue;
096ccff4
KB		 1882 if (removed[i]->expose_device)
1883 hpsa_remove_device(h, removed[i]);
edd16368
SC		 1884 kfree(removed[i]);
1885 removed[i] = NULL;
1886 }
1887
1888 /* Notify scsi mid layer of any added devices */
1889 for (i = 0; i < nadded; i++) {
096ccff4
KB		 1890 int rc = 0;
1891
1d33d85d
DB		 1892 if (added[i] == NULL)
1893 continue;
2a168208 1894 if (!(added[i]->expose_device))
41ce4c35 1895 continue;
096ccff4
KB		 1896 rc = hpsa_add_device(h, added[i]);
1897 if (!rc)
edd16368 1898 continue;
096ccff4
KB		 1899 dev_warn(&h->pdev->dev,
1900 "addition failed %d, device not added.", rc);
edd16368
SC		 1901 /* now we have to remove it from h->dev,
1902 * since it didn't get added to scsi mid layer
1903 */
1904 fixup_botched_add(h, added[i]);
853633e8 1905 h->drv_req_rescan = 1;
edd16368
SC		 1906 }
1907
1908free_and_out:
1909 kfree(added);
1910 kfree(removed);
edd16368
SC		 1911}
1912
1913/*
9e03aa2f 1914 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1915 * Assume's h->devlock is held.
1916 */
1917static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1918 int bus, int target, int lun)
1919{
1920 int i;
1921 struct hpsa_scsi_dev_t *sd;
1922
1923 for (i = 0; i < h->ndevices; i++) {
1924 sd = h->dev[i];
1925 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1926 return sd;
1927 }
1928 return NULL;
1929}
1930
edd16368
SC		 1931static int hpsa_slave_alloc(struct scsi_device *sdev)
1932{
1933 struct hpsa_scsi_dev_t *sd;
1934 unsigned long flags;
1935 struct ctlr_info *h;
1936
1937 h = sdev_to_hba(sdev);
1938 spin_lock_irqsave(&h->devlock, flags);
d04e62b9
KB		 1939 if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) {
1940 struct scsi_target *starget;
1941 struct sas_rphy *rphy;
1942
1943 starget = scsi_target(sdev);
1944 rphy = target_to_rphy(starget);
1945 sd = hpsa_find_device_by_sas_rphy(h, rphy);
1946 if (sd) {
1947 sd->target = sdev_id(sdev);
1948 sd->lun = sdev->lun;
1949 }
1950 } else
1951 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1952 sdev_id(sdev), sdev->lun);
1953
1954 if (sd && sd->expose_device) {
03383736 1955 atomic_set(&sd->ioaccel_cmds_out, 0);
d04e62b9 1956 sdev->hostdata = sd;
41ce4c35
SC		 1957 } else
1958 sdev->hostdata = NULL;
edd16368
SC		 1959 spin_unlock_irqrestore(&h->devlock, flags);
1960 return 0;
1961}
1962
41ce4c35
SC		 1963/* configure scsi device based on internal per-device structure */
1964static int hpsa_slave_configure(struct scsi_device *sdev)
1965{
1966 struct hpsa_scsi_dev_t *sd;
1967 int queue_depth;
1968
1969 sd = sdev->hostdata;
2a168208 1970 sdev->no_uld_attach = !sd || !sd->expose_device;
41ce4c35
SC		 1971
1972 if (sd)
1973 queue_depth = sd->queue_depth != 0 ?
1974 sd->queue_depth : sdev->host->can_queue;
1975 else
1976 queue_depth = sdev->host->can_queue;
1977
1978 scsi_change_queue_depth(sdev, queue_depth);
1979
1980 return 0;
1981}
1982
edd16368
SC		 1983static void hpsa_slave_destroy(struct scsi_device *sdev)
1984{
bcc44255 1985 /* nothing to do. */
edd16368
SC		 1986}
1987
d9a729f3
WS		 1988static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1989{
1990 int i;
1991
1992 if (!h->ioaccel2_cmd_sg_list)
1993 return;
1994 for (i = 0; i < h->nr_cmds; i++) {
1995 kfree(h->ioaccel2_cmd_sg_list[i]);
1996 h->ioaccel2_cmd_sg_list[i] = NULL;
1997 }
1998 kfree(h->ioaccel2_cmd_sg_list);
1999 h->ioaccel2_cmd_sg_list = NULL;
2000}
2001
2002static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
2003{
2004 int i;
2005
2006 if (h->chainsize <= 0)
2007 return 0;
2008
2009 h->ioaccel2_cmd_sg_list =
2010 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
2011 GFP_KERNEL);
2012 if (!h->ioaccel2_cmd_sg_list)
2013 return -ENOMEM;
2014 for (i = 0; i < h->nr_cmds; i++) {
2015 h->ioaccel2_cmd_sg_list[i] =
2016 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
2017 h->maxsgentries, GFP_KERNEL);
2018 if (!h->ioaccel2_cmd_sg_list[i])
2019 goto clean;
2020 }
2021 return 0;
2022
2023clean:
2024 hpsa_free_ioaccel2_sg_chain_blocks(h);
2025 return -ENOMEM;
2026}
2027
33a2ffce
SC		 2028static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
2029{
2030 int i;
2031
2032 if (!h->cmd_sg_list)
2033 return;
2034 for (i = 0; i < h->nr_cmds; i++) {
2035 kfree(h->cmd_sg_list[i]);
2036 h->cmd_sg_list[i] = NULL;
2037 }
2038 kfree(h->cmd_sg_list);
2039 h->cmd_sg_list = NULL;
2040}
2041
105a3dbc 2042static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
33a2ffce
SC		 2043{
2044 int i;
2045
2046 if (h->chainsize <= 0)
2047 return 0;
2048
2049 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
2050 GFP_KERNEL);
3d4e6af8
RE		 2051 if (!h->cmd_sg_list) {
2052 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 2053 return -ENOMEM;
3d4e6af8 2054 }
33a2ffce
SC		 2055 for (i = 0; i < h->nr_cmds; i++) {
2056 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
2057 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 2058 if (!h->cmd_sg_list[i]) {
2059 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 2060 goto clean;
3d4e6af8 2061 }
33a2ffce
SC		 2062 }
2063 return 0;
2064
2065clean:
2066 hpsa_free_sg_chain_blocks(h);
2067 return -ENOMEM;
2068}
2069
d9a729f3
WS		 2070static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
2071 struct io_accel2_cmd *cp, struct CommandList *c)
2072{
2073 struct ioaccel2_sg_element *chain_block;
2074 u64 temp64;
2075 u32 chain_size;
2076
2077 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
a736e9b6 2078 chain_size = le32_to_cpu(cp->sg[0].length);
d9a729f3
WS		 2079 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
2080 PCI_DMA_TODEVICE);
2081 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2082 /* prevent subsequent unmapping */
2083 cp->sg->address = 0;
2084 return -1;
2085 }
2086 cp->sg->address = cpu_to_le64(temp64);
2087 return 0;
2088}
2089
2090static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
2091 struct io_accel2_cmd *cp)
2092{
2093 struct ioaccel2_sg_element *chain_sg;
2094 u64 temp64;
2095 u32 chain_size;
2096
2097 chain_sg = cp->sg;
2098 temp64 = le64_to_cpu(chain_sg->address);
a736e9b6 2099 chain_size = le32_to_cpu(cp->sg[0].length);
d9a729f3
WS		 2100 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
2101}
2102
e2bea6df 2103static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 2104 struct CommandList *c)
2105{
2106 struct SGDescriptor *chain_sg, *chain_block;
2107 u64 temp64;
50a0decf 2108 u32 chain_len;
33a2ffce
SC		 2109
2110 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
2111 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 2112 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
2113 chain_len = sizeof(*chain_sg) *
2b08b3e9 2114 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 2115 chain_sg->Len = cpu_to_le32(chain_len);
2116 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 2117 PCI_DMA_TODEVICE);
e2bea6df
SC		 2118 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2119 /* prevent subsequent unmapping */
50a0decf 2120 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 2121 return -1;
2122 }
50a0decf 2123 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 2124 return 0;
33a2ffce
SC		 2125}
2126
2127static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
2128 struct CommandList *c)
2129{
2130 struct SGDescriptor *chain_sg;
33a2ffce 2131
50a0decf 2132 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 2133 return;
2134
2135 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 2136 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
2137 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 2138}
2139
a09c1441
ST		 2140
2141/* Decode the various types of errors on ioaccel2 path.
2142 * Return 1 for any error that should generate a RAID path retry.
2143 * Return 0 for errors that don't require a RAID path retry.
2144 */
2145static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 2146 struct CommandList *c,
2147 struct scsi_cmnd *cmd,
2148 struct io_accel2_cmd *c2)
2149{
2150 int data_len;
a09c1441 2151 int retry = 0;
c40820d5 2152 u32 ioaccel2_resid = 0;
c349775e
ST		 2153
2154 switch (c2->error_data.serv_response) {
2155 case IOACCEL2_SERV_RESPONSE_COMPLETE:
2156 switch (c2->error_data.status) {
2157 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
2158 break;
2159 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
ee6b1889 2160 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 2161 if (c2->error_data.data_present !=
ee6b1889
SC		 2162 IOACCEL2_SENSE_DATA_PRESENT) {
2163 memset(cmd->sense_buffer, 0,
2164 SCSI_SENSE_BUFFERSIZE);
c349775e 2165 break;
ee6b1889 2166 }
c349775e
ST		 2167 /* copy the sense data */
2168 data_len = c2->error_data.sense_data_len;
2169 if (data_len > SCSI_SENSE_BUFFERSIZE)
2170 data_len = SCSI_SENSE_BUFFERSIZE;
2171 if (data_len > sizeof(c2->error_data.sense_data_buff))
2172 data_len =
2173 sizeof(c2->error_data.sense_data_buff);
2174 memcpy(cmd->sense_buffer,
2175 c2->error_data.sense_data_buff, data_len);
a09c1441 2176 retry = 1;
c349775e
ST		 2177 break;
2178 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
a09c1441 2179 retry = 1;
c349775e
ST		 2180 break;
2181 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
a09c1441 2182 retry = 1;
c349775e
ST		 2183 break;
2184 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 2185 retry = 1;
c349775e
ST		 2186 break;
2187 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
a09c1441 2188 retry = 1;
c349775e
ST		 2189 break;
2190 default:
a09c1441 2191 retry = 1;
c349775e
ST		 2192 break;
2193 }
2194 break;
2195 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 2196 switch (c2->error_data.status) {
2197 case IOACCEL2_STATUS_SR_IO_ERROR:
2198 case IOACCEL2_STATUS_SR_IO_ABORTED:
2199 case IOACCEL2_STATUS_SR_OVERRUN:
2200 retry = 1;
2201 break;
2202 case IOACCEL2_STATUS_SR_UNDERRUN:
2203 cmd->result = (DID_OK << 16); /* host byte */
2204 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2205 ioaccel2_resid = get_unaligned_le32(
2206 &c2->error_data.resid_cnt[0]);
2207 scsi_set_resid(cmd, ioaccel2_resid);
2208 break;
2209 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
2210 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
2211 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
2212 /* We will get an event from ctlr to trigger rescan */
2213 retry = 1;
2214 break;
2215 default:
2216 retry = 1;
c40820d5 2217 }
c349775e
ST		 2218 break;
2219 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
2220 break;
2221 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
2222 break;
2223 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
a09c1441 2224 retry = 1;
c349775e
ST		 2225 break;
2226 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
c349775e
ST		 2227 break;
2228 default:
a09c1441 2229 retry = 1;
c349775e
ST		 2230 break;
2231 }
a09c1441
ST		 2232
2233 return retry; /* retry on raid path? */
c349775e
ST		 2234}
2235
a58e7e53
WS		 2236static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2237 struct CommandList *c)
2238{
d604f533
WS		 2239 bool do_wake = false;
2240
a58e7e53
WS		 2241 /*
2242 * Prevent the following race in the abort handler:
2243 *
2244 * 1. LLD is requested to abort a SCSI command
2245 * 2. The SCSI command completes
2246 * 3. The struct CommandList associated with step 2 is made available
2247 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2248 * 5. Abort handler follows scsi_cmnd->host_scribble and
2249 * finds struct CommandList and tries to aborts it
2250 * Now we have aborted the wrong command.
2251 *
d604f533
WS		 2252 * Reset c->scsi_cmd here so that the abort or reset handler will know
2253 * this command has completed. Then, check to see if the handler is
a58e7e53
WS		 2254 * waiting for this command, and, if so, wake it.
2255 */
2256 c->scsi_cmd = SCSI_CMD_IDLE;
d604f533 2257 mb(); /* Declare command idle before checking for pending events. */
a58e7e53 2258 if (c->abort_pending) {
d604f533 2259 do_wake = true;
a58e7e53 2260 c->abort_pending = false;
a58e7e53 2261 }
d604f533
WS		 2262 if (c->reset_pending) {
2263 unsigned long flags;
2264 struct hpsa_scsi_dev_t *dev;
2265
2266 /*
2267 * There appears to be a reset pending; lock the lock and
2268 * reconfirm. If so, then decrement the count of outstanding
2269 * commands and wake the reset command if this is the last one.
2270 */
2271 spin_lock_irqsave(&h->lock, flags);
2272 dev = c->reset_pending; /* Re-fetch under the lock. */
2273 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2274 do_wake = true;
2275 c->reset_pending = NULL;
2276 spin_unlock_irqrestore(&h->lock, flags);
2277 }
2278
2279 if (do_wake)
2280 wake_up_all(&h->event_sync_wait_queue);
a58e7e53
WS		 2281}
2282
73153fe5
WS		 2283static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2284 struct CommandList *c)
2285{
2286 hpsa_cmd_resolve_events(h, c);
2287 cmd_tagged_free(h, c);
2288}
2289
8a0ff92c
WS		 2290static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2291 struct CommandList *c, struct scsi_cmnd *cmd)
2292{
73153fe5 2293 hpsa_cmd_resolve_and_free(h, c);
8a0ff92c
WS		 2294 cmd->scsi_done(cmd);
2295}
2296
2297static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2298{
2299 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2300 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2301}
2302
a58e7e53
WS		 2303static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2304{
2305 cmd->result = DID_ABORT << 16;
2306}
2307
2308static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2309 struct scsi_cmnd *cmd)
2310{
2311 hpsa_set_scsi_cmd_aborted(cmd);
2312 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2313 c->Request.CDB, c->err_info->ScsiStatus);
73153fe5 2314 hpsa_cmd_resolve_and_free(h, c);
a58e7e53
WS		 2315}
2316
c349775e
ST		 2317static void process_ioaccel2_completion(struct ctlr_info *h,
2318 struct CommandList *c, struct scsi_cmnd *cmd,
2319 struct hpsa_scsi_dev_t *dev)
2320{
2321 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2322
2323 /* check for good status */
2324 if (likely(c2->error_data.serv_response == 0 &&
8a0ff92c
WS		 2325 c2->error_data.status == 0))
2326 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e 2327
8a0ff92c
WS		 2328 /*
2329 * Any RAID offload error results in retry which will use
c349775e
ST		 2330 * the normal I/O path so the controller can handle whatever's
2331 * wrong.
2332 */
f3f01730 2333 if (is_logical_device(dev) &&
c349775e
ST		 2334 c2->error_data.serv_response ==
2335 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 2336 if (c2->error_data.status ==
2337 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
2338 dev->offload_enabled = 0;
8a0ff92c
WS		 2339
2340 return hpsa_retry_cmd(h, c);
a09c1441 2341 }
080ef1cc
DB		 2342
2343 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
8a0ff92c 2344 return hpsa_retry_cmd(h, c);
080ef1cc 2345
8a0ff92c 2346 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e
ST		 2347}
2348
9437ac43
SC		 2349/* Returns 0 on success, < 0 otherwise. */
2350static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2351 struct CommandList *cp)
2352{
2353 u8 tmf_status = cp->err_info->ScsiStatus;
2354
2355 switch (tmf_status) {
2356 case CISS_TMF_COMPLETE:
2357 /*
2358 * CISS_TMF_COMPLETE never happens, instead,
2359 * ei->CommandStatus == 0 for this case.
2360 */
2361 case CISS_TMF_SUCCESS:
2362 return 0;
2363 case CISS_TMF_INVALID_FRAME:
2364 case CISS_TMF_NOT_SUPPORTED:
2365 case CISS_TMF_FAILED:
2366 case CISS_TMF_WRONG_LUN:
2367 case CISS_TMF_OVERLAPPED_TAG:
2368 break;
2369 default:
2370 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2371 tmf_status);
2372 break;
2373 }
2374 return -tmf_status;
2375}
2376
1fb011fb 2377static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2378{
2379 struct scsi_cmnd *cmd;
2380 struct ctlr_info *h;
2381 struct ErrorInfo *ei;
283b4a9b 2382 struct hpsa_scsi_dev_t *dev;
d9a729f3 2383 struct io_accel2_cmd *c2;
edd16368 2384
9437ac43
SC		 2385 u8 sense_key;
2386 u8 asc; /* additional sense code */
2387 u8 ascq; /* additional sense code qualifier */
db111e18 2388 unsigned long sense_data_size;
edd16368
SC		 2389
2390 ei = cp->err_info;
7fa3030c 2391 cmd = cp->scsi_cmd;
edd16368 2392 h = cp->h;
283b4a9b 2393 dev = cmd->device->hostdata;
d9a729f3 2394 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2395
2396 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2397 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2398 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2399 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2400
d9a729f3
WS		 2401 if ((cp->cmd_type == CMD_IOACCEL2) &&
2402 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2403 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2404
edd16368
SC		 2405 cmd->result = (DID_OK << 16); /* host byte */
2406 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2407
03383736
DB		 2408 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2409 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2410
25163bd5
WS		 2411 /*
2412 * We check for lockup status here as it may be set for
2413 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2414 * fail_all_oustanding_cmds()
2415 */
2416 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2417 /* DID_NO_CONNECT will prevent a retry */
2418 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 2419 return hpsa_cmd_free_and_done(h, cp, cmd);
25163bd5
WS		 2420 }
2421
d604f533
WS		 2422 if ((unlikely(hpsa_is_pending_event(cp)))) {
2423 if (cp->reset_pending)
2424 return hpsa_cmd_resolve_and_free(h, cp);
2425 if (cp->abort_pending)
2426 return hpsa_cmd_abort_and_free(h, cp, cmd);
2427 }
2428
c349775e
ST		 2429 if (cp->cmd_type == CMD_IOACCEL2)
2430 return process_ioaccel2_completion(h, cp, cmd, dev);
2431
6aa4c361 2432 scsi_set_resid(cmd, ei->ResidualCnt);
8a0ff92c
WS		 2433 if (ei->CommandStatus == 0)
2434 return hpsa_cmd_free_and_done(h, cp, cmd);
6aa4c361 2435
e1f7de0c
MG		 2436 /* For I/O accelerator commands, copy over some fields to the normal
2437 * CISS header used below for error handling.
2438 */
2439 if (cp->cmd_type == CMD_IOACCEL1) {
2440 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2441 cp->Header.SGList = scsi_sg_count(cmd);
2442 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2443 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2444 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2445 cp->Header.tag = c->tag;
e1f7de0c
MG		 2446 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2447 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2448
2449 /* Any RAID offload error results in retry which will use
2450 * the normal I/O path so the controller can handle whatever's
2451 * wrong.
2452 */
f3f01730 2453 if (is_logical_device(dev)) {
283b4a9b
SC		 2454 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2455 dev->offload_enabled = 0;
d604f533 2456 return hpsa_retry_cmd(h, cp);
283b4a9b 2457 }
e1f7de0c
MG		 2458 }
2459
edd16368
SC		 2460 /* an error has occurred */
2461 switch (ei->CommandStatus) {
2462
2463 case CMD_TARGET_STATUS:
9437ac43
SC		 2464 cmd->result |= ei->ScsiStatus;
2465 /* copy the sense data */
2466 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2467 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2468 else
2469 sense_data_size = sizeof(ei->SenseInfo);
2470 if (ei->SenseLen < sense_data_size)
2471 sense_data_size = ei->SenseLen;
2472 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2473 if (ei->ScsiStatus)
2474 decode_sense_data(ei->SenseInfo, sense_data_size,
2475 &sense_key, &asc, &ascq);
edd16368 2476 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2477 if (sense_key == ABORTED_COMMAND) {
2e311fba 2478 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2479 break;
2480 }
edd16368
SC		 2481 break;
2482 }
edd16368
SC		 2483 /* Problem was not a check condition
2484 * Pass it up to the upper layers...
2485 */
2486 if (ei->ScsiStatus) {
2487 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2488 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2489 "Returning result: 0x%x\n",
2490 cp, ei->ScsiStatus,
2491 sense_key, asc, ascq,
2492 cmd->result);
2493 } else { /* scsi status is zero??? How??? */
2494 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2495 "Returning no connection.\n", cp),
2496
2497 /* Ordinarily, this case should never happen,
2498 * but there is a bug in some released firmware
2499 * revisions that allows it to happen if, for
2500 * example, a 4100 backplane loses power and
2501 * the tape drive is in it. We assume that
2502 * it's a fatal error of some kind because we
2503 * can't show that it wasn't. We will make it
2504 * look like selection timeout since that is
2505 * the most common reason for this to occur,
2506 * and it's severe enough.
2507 */
2508
2509 cmd->result = DID_NO_CONNECT << 16;
2510 }
2511 break;
2512
2513 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2514 break;
2515 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2516 dev_warn(&h->pdev->dev,
2517 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2518 break;
2519 case CMD_INVALID: {
2520 /* print_bytes(cp, sizeof(*cp), 1, 0);
2521 print_cmd(cp); */
2522 /* We get CMD_INVALID if you address a non-existent device
2523 * instead of a selection timeout (no response). You will
2524 * see this if you yank out a drive, then try to access it.
2525 * This is kind of a shame because it means that any other
2526 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2527 * missing target. */
2528 cmd->result = DID_NO_CONNECT << 16;
2529 }
2530 break;
2531 case CMD_PROTOCOL_ERR:
256d0eaa 2532 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2533 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2534 cp->Request.CDB);
edd16368
SC		 2535 break;
2536 case CMD_HARDWARE_ERR:
2537 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2538 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2539 cp->Request.CDB);
edd16368
SC		 2540 break;
2541 case CMD_CONNECTION_LOST:
2542 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2543 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2544 cp->Request.CDB);
edd16368
SC		 2545 break;
2546 case CMD_ABORTED:
a58e7e53
WS		 2547 /* Return now to avoid calling scsi_done(). */
2548 return hpsa_cmd_abort_and_free(h, cp, cmd);
edd16368
SC		 2549 case CMD_ABORT_FAILED:
2550 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2551 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2552 cp->Request.CDB);
edd16368
SC		 2553 break;
2554 case CMD_UNSOLICITED_ABORT:
f6e76055 2555 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2556 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2557 cp->Request.CDB);
edd16368
SC		 2558 break;
2559 case CMD_TIMEOUT:
2560 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2561 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2562 cp->Request.CDB);
edd16368 2563 break;
1d5e2ed0
SC		 2564 case CMD_UNABORTABLE:
2565 cmd->result = DID_ERROR << 16;
2566 dev_warn(&h->pdev->dev, "Command unabortable\n");
2567 break;
9437ac43
SC		 2568 case CMD_TMF_STATUS:
2569 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2570 cmd->result = DID_ERROR << 16;
2571 break;
283b4a9b
SC		 2572 case CMD_IOACCEL_DISABLED:
2573 /* This only handles the direct pass-through case since RAID
2574 * offload is handled above. Just attempt a retry.
2575 */
2576 cmd->result = DID_SOFT_ERROR << 16;
2577 dev_warn(&h->pdev->dev,
2578 "cp %p had HP SSD Smart Path error\n", cp);
2579 break;
edd16368
SC		 2580 default:
2581 cmd->result = DID_ERROR << 16;
2582 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2583 cp, ei->CommandStatus);
2584 }
8a0ff92c
WS		 2585
2586 return hpsa_cmd_free_and_done(h, cp, cmd);
edd16368
SC		 2587}
2588
edd16368
SC		 2589static void hpsa_pci_unmap(struct pci_dev *pdev,
2590 struct CommandList *c, int sg_used, int data_direction)
2591{
2592 int i;
edd16368 2593
50a0decf
SC		 2594 for (i = 0; i < sg_used; i++)
2595 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2596 le32_to_cpu(c->SG[i].Len),
2597 data_direction);
edd16368
SC		 2598}
2599
a2dac136 2600static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2601 struct CommandList *cp,
2602 unsigned char *buf,
2603 size_t buflen,
2604 int data_direction)
2605{
01a02ffc 2606 u64 addr64;
edd16368
SC		 2607
2608 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2609 cp->Header.SGList = 0;
50a0decf 2610 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2611 return 0;
edd16368
SC		 2612 }
2613
50a0decf 2614 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2615 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2616 /* Prevent subsequent unmap of something never mapped */
eceaae18 2617 cp->Header.SGList = 0;
50a0decf 2618 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2619 return -1;
eceaae18 2620 }
50a0decf
SC		 2621 cp->SG[0].Addr = cpu_to_le64(addr64);
2622 cp->SG[0].Len = cpu_to_le32(buflen);
2623 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2624 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2625 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2626 return 0;
edd16368
SC		 2627}
2628
25163bd5
WS		 2629#define NO_TIMEOUT ((unsigned long) -1)
2630#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2631static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2632 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2633{
2634 DECLARE_COMPLETION_ONSTACK(wait);
2635
2636 c->waiting = &wait;
25163bd5
WS		 2637 __enqueue_cmd_and_start_io(h, c, reply_queue);
2638 if (timeout_msecs == NO_TIMEOUT) {
2639 /* TODO: get rid of this no-timeout thing */
2640 wait_for_completion_io(&wait);
2641 return IO_OK;
2642 }
2643 if (!wait_for_completion_io_timeout(&wait,
2644 msecs_to_jiffies(timeout_msecs))) {
2645 dev_warn(&h->pdev->dev, "Command timed out.\n");
2646 return -ETIMEDOUT;
2647 }
2648 return IO_OK;
2649}
2650
2651static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2652 int reply_queue, unsigned long timeout_msecs)
2653{
2654 if (unlikely(lockup_detected(h))) {
2655 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2656 return IO_OK;
2657 }
2658 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2659}
2660
094963da
SC		 2661static u32 lockup_detected(struct ctlr_info *h)
2662{
2663 int cpu;
2664 u32 rc, *lockup_detected;
2665
2666 cpu = get_cpu();
2667 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2668 rc = *lockup_detected;
2669 put_cpu();
2670 return rc;
2671}
2672
9c2fc160 2673#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2674static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2675 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2676{
9c2fc160 2677 int backoff_time = 10, retry_count = 0;
25163bd5 2678 int rc;
edd16368
SC		 2679
2680 do {
7630abd0 2681 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2682 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2683 timeout_msecs);
2684 if (rc)
2685 break;
edd16368 2686 retry_count++;
9c2fc160
SC		 2687 if (retry_count > 3) {
2688 msleep(backoff_time);
2689 if (backoff_time < 1000)
2690 backoff_time *= 2;
2691 }
852af20a 2692 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2693 check_for_busy(h, c)) &&
2694 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2695 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2696 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2697 rc = -EIO;
2698 return rc;
edd16368
SC		 2699}
2700
d1e8beac
SC		 2701static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2702 struct CommandList *c)
edd16368 2703{
d1e8beac
SC		 2704 const u8 *cdb = c->Request.CDB;
2705 const u8 *lun = c->Header.LUN.LunAddrBytes;
2706
2707 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2708 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2709 txt, lun[0], lun[1], lun[2], lun[3],
2710 lun[4], lun[5], lun[6], lun[7],
2711 cdb[0], cdb[1], cdb[2], cdb[3],
2712 cdb[4], cdb[5], cdb[6], cdb[7],
2713 cdb[8], cdb[9], cdb[10], cdb[11],
2714 cdb[12], cdb[13], cdb[14], cdb[15]);
2715}
2716
2717static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2718 struct CommandList *cp)
2719{
2720 const struct ErrorInfo *ei = cp->err_info;
edd16368 2721 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2722 u8 sense_key, asc, ascq;
2723 int sense_len;
edd16368 2724
edd16368
SC		 2725 switch (ei->CommandStatus) {
2726 case CMD_TARGET_STATUS:
9437ac43
SC		 2727 if (ei->SenseLen > sizeof(ei->SenseInfo))
2728 sense_len = sizeof(ei->SenseInfo);
2729 else
2730 sense_len = ei->SenseLen;
2731 decode_sense_data(ei->SenseInfo, sense_len,
2732 &sense_key, &asc, &ascq);
d1e8beac
SC		 2733 hpsa_print_cmd(h, "SCSI status", cp);
2734 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2735 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2736 sense_key, asc, ascq);
d1e8beac 2737 else
9437ac43 2738 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2739 if (ei->ScsiStatus == 0)
2740 dev_warn(d, "SCSI status is abnormally zero. "
2741 "(probably indicates selection timeout "
2742 "reported incorrectly due to a known "
2743 "firmware bug, circa July, 2001.)\n");
2744 break;
2745 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2746 break;
2747 case CMD_DATA_OVERRUN:
d1e8beac 2748 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2749 break;
2750 case CMD_INVALID: {
2751 /* controller unfortunately reports SCSI passthru's
2752 * to non-existent targets as invalid commands.
2753 */
d1e8beac
SC		 2754 hpsa_print_cmd(h, "invalid command", cp);
2755 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2756 }
2757 break;
2758 case CMD_PROTOCOL_ERR:
d1e8beac 2759 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2760 break;
2761 case CMD_HARDWARE_ERR:
d1e8beac 2762 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2763 break;
2764 case CMD_CONNECTION_LOST:
d1e8beac 2765 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2766 break;
2767 case CMD_ABORTED:
d1e8beac 2768 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2769 break;
2770 case CMD_ABORT_FAILED:
d1e8beac 2771 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2772 break;
2773 case CMD_UNSOLICITED_ABORT:
d1e8beac 2774 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2775 break;
2776 case CMD_TIMEOUT:
d1e8beac 2777 hpsa_print_cmd(h, "timed out", cp);
edd16368 2778 break;
1d5e2ed0 2779 case CMD_UNABORTABLE:
d1e8beac 2780 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2781 break;
25163bd5
WS		 2782 case CMD_CTLR_LOCKUP:
2783 hpsa_print_cmd(h, "controller lockup detected", cp);
2784 break;
edd16368 2785 default:
d1e8beac
SC		 2786 hpsa_print_cmd(h, "unknown status", cp);
2787 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2788 ei->CommandStatus);
2789 }
2790}
2791
2792static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2793 u16 page, unsigned char *buf,
edd16368
SC		 2794 unsigned char bufsize)
2795{
2796 int rc = IO_OK;
2797 struct CommandList *c;
2798 struct ErrorInfo *ei;
2799
45fcb86e 2800 c = cmd_alloc(h);
edd16368 2801
a2dac136
SC		 2802 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2803 page, scsi3addr, TYPE_CMD)) {
2804 rc = -1;
2805 goto out;
2806 }
25163bd5
WS		 2807 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2808 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2809 if (rc)
2810 goto out;
edd16368
SC		 2811 ei = c->err_info;
2812 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2813 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2814 rc = -1;
2815 }
a2dac136 2816out:
45fcb86e 2817 cmd_free(h, c);
edd16368
SC		 2818 return rc;
2819}
2820
bf711ac6 2821static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2822 u8 reset_type, int reply_queue)
edd16368
SC		 2823{
2824 int rc = IO_OK;
2825 struct CommandList *c;
2826 struct ErrorInfo *ei;
2827
45fcb86e 2828 c = cmd_alloc(h);
edd16368 2829
edd16368 2830
a2dac136 2831 /* fill_cmd can't fail here, no data buffer to map. */
0b9b7b6e 2832 (void) fill_cmd(c, reset_type, h, NULL, 0, 0,
bf711ac6 2833 scsi3addr, TYPE_MSG);
25163bd5
WS		 2834 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2835 if (rc) {
2836 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2837 goto out;
2838 }
edd16368
SC		 2839 /* no unmap needed here because no data xfer. */
2840
2841 ei = c->err_info;
2842 if (ei->CommandStatus != 0) {
d1e8beac 2843 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2844 rc = -1;
2845 }
25163bd5 2846out:
45fcb86e 2847 cmd_free(h, c);
edd16368
SC		 2848 return rc;
2849}
2850
d604f533
WS		 2851static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2852 struct hpsa_scsi_dev_t *dev,
2853 unsigned char *scsi3addr)
2854{
2855 int i;
2856 bool match = false;
2857 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2858 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2859
2860 if (hpsa_is_cmd_idle(c))
2861 return false;
2862
2863 switch (c->cmd_type) {
2864 case CMD_SCSI:
2865 case CMD_IOCTL_PEND:
2866 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2867 sizeof(c->Header.LUN.LunAddrBytes));
2868 break;
2869
2870 case CMD_IOACCEL1:
2871 case CMD_IOACCEL2:
2872 if (c->phys_disk == dev) {
2873 /* HBA mode match */
2874 match = true;
2875 } else {
2876 /* Possible RAID mode -- check each phys dev. */
2877 /* FIXME: Do we need to take out a lock here? If
2878 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2879 * instead. */
2880 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2881 /* FIXME: an alternate test might be
2882 *
2883 * match = dev->phys_disk[i]->ioaccel_handle
2884 * == c2->scsi_nexus; */
2885 match = dev->phys_disk[i] == c->phys_disk;
2886 }
2887 }
2888 break;
2889
2890 case IOACCEL2_TMF:
2891 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2892 match = dev->phys_disk[i]->ioaccel_handle ==
2893 le32_to_cpu(ac->it_nexus);
2894 }
2895 break;
2896
2897 case 0: /* The command is in the middle of being initialized. */
2898 match = false;
2899 break;
2900
2901 default:
2902 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
2903 c->cmd_type);
2904 BUG();
2905 }
2906
2907 return match;
2908}
2909
2910static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
2911 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
2912{
2913 int i;
2914 int rc = 0;
2915
2916 /* We can really only handle one reset at a time */
2917 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
2918 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
2919 return -EINTR;
2920 }
2921
2922 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
2923
2924 for (i = 0; i < h->nr_cmds; i++) {
2925 struct CommandList *c = h->cmd_pool + i;
2926 int refcount = atomic_inc_return(&c->refcount);
2927
2928 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
2929 unsigned long flags;
2930
2931 /*
2932 * Mark the target command as having a reset pending,
2933 * then lock a lock so that the command cannot complete
2934 * while we're considering it. If the command is not
2935 * idle then count it; otherwise revoke the event.
2936 */
2937 c->reset_pending = dev;
2938 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
2939 if (!hpsa_is_cmd_idle(c))
2940 atomic_inc(&dev->reset_cmds_out);
2941 else
2942 c->reset_pending = NULL;
2943 spin_unlock_irqrestore(&h->lock, flags);
2944 }
2945
2946 cmd_free(h, c);
2947 }
2948
2949 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
2950 if (!rc)
2951 wait_event(h->event_sync_wait_queue,
2952 atomic_read(&dev->reset_cmds_out) == 0 ||
2953 lockup_detected(h));
2954
2955 if (unlikely(lockup_detected(h))) {
77678d3a
DB		 2956 dev_warn(&h->pdev->dev,
2957 "Controller lockup detected during reset wait\n");
2958 rc = -ENODEV;
2959 }
d604f533
WS		 2960
2961 if (unlikely(rc))
2962 atomic_set(&dev->reset_cmds_out, 0);
2963
2964 mutex_unlock(&h->reset_mutex);
2965 return rc;
2966}
2967
edd16368
SC		 2968static void hpsa_get_raid_level(struct ctlr_info *h,
2969 unsigned char *scsi3addr, unsigned char *raid_level)
2970{
2971 int rc;
2972 unsigned char *buf;
2973
2974 *raid_level = RAID_UNKNOWN;
2975 buf = kzalloc(64, GFP_KERNEL);
2976 if (!buf)
2977 return;
b7bb24eb 2978 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2979 if (rc == 0)
2980 *raid_level = buf[8];
2981 if (*raid_level > RAID_UNKNOWN)
2982 *raid_level = RAID_UNKNOWN;
2983 kfree(buf);
2984 return;
2985}
2986
283b4a9b
SC		 2987#define HPSA_MAP_DEBUG
2988#ifdef HPSA_MAP_DEBUG
2989static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2990 struct raid_map_data *map_buff)
2991{
2992 struct raid_map_disk_data *dd = &map_buff->data[0];
2993 int map, row, col;
2994 u16 map_cnt, row_cnt, disks_per_row;
2995
2996 if (rc != 0)
2997 return;
2998
2ba8bfc8
SC		 2999 /* Show details only if debugging has been activated. */
3000 if (h->raid_offload_debug < 2)
3001 return;
3002
283b4a9b
SC		 3003 dev_info(&h->pdev->dev, "structure_size = %u\n",
3004 le32_to_cpu(map_buff->structure_size));
3005 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
3006 le32_to_cpu(map_buff->volume_blk_size));
3007 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
3008 le64_to_cpu(map_buff->volume_blk_cnt));
3009 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
3010 map_buff->phys_blk_shift);
3011 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
3012 map_buff->parity_rotation_shift);
3013 dev_info(&h->pdev->dev, "strip_size = %u\n",
3014 le16_to_cpu(map_buff->strip_size));
3015 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
3016 le64_to_cpu(map_buff->disk_starting_blk));
3017 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
3018 le64_to_cpu(map_buff->disk_blk_cnt));
3019 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
3020 le16_to_cpu(map_buff->data_disks_per_row));
3021 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
3022 le16_to_cpu(map_buff->metadata_disks_per_row));
3023 dev_info(&h->pdev->dev, "row_cnt = %u\n",
3024 le16_to_cpu(map_buff->row_cnt));
3025 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
3026 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 3027 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 3028 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 3029 dev_info(&h->pdev->dev, "encrypytion = %s\n",
3030 le16_to_cpu(map_buff->flags) &
3031 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 3032 dev_info(&h->pdev->dev, "dekindex = %u\n",
3033 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 3034 map_cnt = le16_to_cpu(map_buff->layout_map_count);
3035 for (map = 0; map < map_cnt; map++) {
3036 dev_info(&h->pdev->dev, "Map%u:\n", map);
3037 row_cnt = le16_to_cpu(map_buff->row_cnt);
3038 for (row = 0; row < row_cnt; row++) {
3039 dev_info(&h->pdev->dev, " Row%u:\n", row);
3040 disks_per_row =
3041 le16_to_cpu(map_buff->data_disks_per_row);
3042 for (col = 0; col < disks_per_row; col++, dd++)
3043 dev_info(&h->pdev->dev,
3044 " D%02u: h=0x%04x xor=%u,%u\n",
3045 col, dd->ioaccel_handle,
3046 dd->xor_mult[0], dd->xor_mult[1]);
3047 disks_per_row =
3048 le16_to_cpu(map_buff->metadata_disks_per_row);
3049 for (col = 0; col < disks_per_row; col++, dd++)
3050 dev_info(&h->pdev->dev,
3051 " M%02u: h=0x%04x xor=%u,%u\n",
3052 col, dd->ioaccel_handle,
3053 dd->xor_mult[0], dd->xor_mult[1]);
3054 }
3055 }
3056}
3057#else
3058static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
3059 __attribute__((unused)) int rc,
3060 __attribute__((unused)) struct raid_map_data *map_buff)
3061{
3062}
3063#endif
3064
3065static int hpsa_get_raid_map(struct ctlr_info *h,
3066 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3067{
3068 int rc = 0;
3069 struct CommandList *c;
3070 struct ErrorInfo *ei;
3071
45fcb86e 3072 c = cmd_alloc(h);
bf43caf3 3073
283b4a9b
SC		 3074 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
3075 sizeof(this_device->raid_map), 0,
3076 scsi3addr, TYPE_CMD)) {
2dd02d74
RE		 3077 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
3078 cmd_free(h, c);
3079 return -1;
283b4a9b 3080 }
25163bd5
WS		 3081 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3082 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3083 if (rc)
3084 goto out;
283b4a9b
SC		 3085 ei = c->err_info;
3086 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3087 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 3088 rc = -1;
3089 goto out;
283b4a9b 3090 }
45fcb86e 3091 cmd_free(h, c);
283b4a9b
SC		 3092
3093 /* @todo in the future, dynamically allocate RAID map memory */
3094 if (le32_to_cpu(this_device->raid_map.structure_size) >
3095 sizeof(this_device->raid_map)) {
3096 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
3097 rc = -1;
3098 }
3099 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
3100 return rc;
25163bd5
WS		 3101out:
3102 cmd_free(h, c);
3103 return rc;
283b4a9b
SC		 3104}
3105
d04e62b9
KB		 3106static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h,
3107 unsigned char scsi3addr[], u16 bmic_device_index,
3108 struct bmic_sense_subsystem_info *buf, size_t bufsize)
3109{
3110 int rc = IO_OK;
3111 struct CommandList *c;
3112 struct ErrorInfo *ei;
3113
3114 c = cmd_alloc(h);
3115
3116 rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize,
3117 0, RAID_CTLR_LUNID, TYPE_CMD);
3118 if (rc)
3119 goto out;
3120
3121 c->Request.CDB[2] = bmic_device_index & 0xff;
3122 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3123
3124 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3125 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3126 if (rc)
3127 goto out;
3128 ei = c->err_info;
3129 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3130 hpsa_scsi_interpret_error(h, c);
3131 rc = -1;
3132 }
3133out:
3134 cmd_free(h, c);
3135 return rc;
3136}
3137
66749d0d
ST		 3138static int hpsa_bmic_id_controller(struct ctlr_info *h,
3139 struct bmic_identify_controller *buf, size_t bufsize)
3140{
3141 int rc = IO_OK;
3142 struct CommandList *c;
3143 struct ErrorInfo *ei;
3144
3145 c = cmd_alloc(h);
3146
3147 rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize,
3148 0, RAID_CTLR_LUNID, TYPE_CMD);
3149 if (rc)
3150 goto out;
3151
3152 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3153 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3154 if (rc)
3155 goto out;
3156 ei = c->err_info;
3157 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3158 hpsa_scsi_interpret_error(h, c);
3159 rc = -1;
3160 }
3161out:
3162 cmd_free(h, c);
3163 return rc;
3164}
3165
03383736
DB		 3166static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
3167 unsigned char scsi3addr[], u16 bmic_device_index,
3168 struct bmic_identify_physical_device *buf, size_t bufsize)
3169{
3170 int rc = IO_OK;
3171 struct CommandList *c;
3172 struct ErrorInfo *ei;
3173
3174 c = cmd_alloc(h);
3175 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
3176 0, RAID_CTLR_LUNID, TYPE_CMD);
3177 if (rc)
3178 goto out;
3179
3180 c->Request.CDB[2] = bmic_device_index & 0xff;
3181 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3182
25163bd5
WS		 3183 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
3184 NO_TIMEOUT);
03383736
DB		 3185 ei = c->err_info;
3186 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3187 hpsa_scsi_interpret_error(h, c);
3188 rc = -1;
3189 }
3190out:
3191 cmd_free(h, c);
d04e62b9 3192
03383736
DB		 3193 return rc;
3194}
3195
cca8f13b
DB		 3196/*
3197 * get enclosure information
3198 * struct ReportExtendedLUNdata *rlep - Used for BMIC drive number
3199 * struct hpsa_scsi_dev_t *encl_dev - device entry for enclosure
3200 * Uses id_physical_device to determine the box_index.
3201 */
3202static void hpsa_get_enclosure_info(struct ctlr_info *h,
3203 unsigned char *scsi3addr,
3204 struct ReportExtendedLUNdata *rlep, int rle_index,
3205 struct hpsa_scsi_dev_t *encl_dev)
3206{
3207 int rc = -1;
3208 struct CommandList *c = NULL;
3209 struct ErrorInfo *ei = NULL;
3210 struct bmic_sense_storage_box_params *bssbp = NULL;
3211 struct bmic_identify_physical_device *id_phys = NULL;
3212 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
3213 u16 bmic_device_index = 0;
3214
3215 bmic_device_index = GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]);
3216
17a9e54a
DB		 3217 if (bmic_device_index == 0xFF00 || MASKED_DEVICE(&rle->lunid[0])) {
3218 rc = IO_OK;
cca8f13b 3219 goto out;
17a9e54a 3220 }
cca8f13b
DB		 3221
3222 bssbp = kzalloc(sizeof(*bssbp), GFP_KERNEL);
3223 if (!bssbp)
3224 goto out;
3225
3226 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
3227 if (!id_phys)
3228 goto out;
3229
3230 rc = hpsa_bmic_id_physical_device(h, scsi3addr, bmic_device_index,
3231 id_phys, sizeof(*id_phys));
3232 if (rc) {
3233 dev_warn(&h->pdev->dev, "%s: id_phys failed %d bdi[0x%x]\n",
3234 __func__, encl_dev->external, bmic_device_index);
3235 goto out;
3236 }
3237
3238 c = cmd_alloc(h);
3239
3240 rc = fill_cmd(c, BMIC_SENSE_STORAGE_BOX_PARAMS, h, bssbp,
3241 sizeof(*bssbp), 0, RAID_CTLR_LUNID, TYPE_CMD);
3242
3243 if (rc)
3244 goto out;
3245
3246 if (id_phys->phys_connector[1] == 'E')
3247 c->Request.CDB[5] = id_phys->box_index;
3248 else
3249 c->Request.CDB[5] = 0;
3250
3251 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
3252 NO_TIMEOUT);
3253 if (rc)
3254 goto out;
3255
3256 ei = c->err_info;
3257 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3258 rc = -1;
3259 goto out;
3260 }
3261
3262 encl_dev->box[id_phys->active_path_number] = bssbp->phys_box_on_port;
3263 memcpy(&encl_dev->phys_connector[id_phys->active_path_number],
3264 bssbp->phys_connector, sizeof(bssbp->phys_connector));
3265
3266 rc = IO_OK;
3267out:
3268 kfree(bssbp);
3269 kfree(id_phys);
3270
3271 if (c)
3272 cmd_free(h, c);
3273
3274 if (rc != IO_OK)
3275 hpsa_show_dev_msg(KERN_INFO, h, encl_dev,
3276 "Error, could not get enclosure information\n");
3277}
3278
d04e62b9
KB		 3279static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h,
3280 unsigned char *scsi3addr)
3281{
3282 struct ReportExtendedLUNdata *physdev;
3283 u32 nphysicals;
3284 u64 sa = 0;
3285 int i;
3286
3287 physdev = kzalloc(sizeof(*physdev), GFP_KERNEL);
3288 if (!physdev)
3289 return 0;
3290
3291 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
3292 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3293 kfree(physdev);
3294 return 0;
3295 }
3296 nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24;
3297
3298 for (i = 0; i < nphysicals; i++)
3299 if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) {
3300 sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]);
3301 break;
3302 }
3303
3304 kfree(physdev);
3305
3306 return sa;
3307}
3308
3309static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr,
3310 struct hpsa_scsi_dev_t *dev)
3311{
3312 int rc;
3313 u64 sa = 0;
3314
3315 if (is_hba_lunid(scsi3addr)) {
3316 struct bmic_sense_subsystem_info *ssi;
3317
3318 ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
3319 if (ssi == NULL) {
3320 dev_warn(&h->pdev->dev,
3321 "%s: out of memory\n", __func__);
3322 return;
3323 }
3324
3325 rc = hpsa_bmic_sense_subsystem_information(h,
3326 scsi3addr, 0, ssi, sizeof(*ssi));
3327 if (rc == 0) {
3328 sa = get_unaligned_be64(ssi->primary_world_wide_id);
3329 h->sas_address = sa;
3330 }
3331
3332 kfree(ssi);
3333 } else
3334 sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr);
3335
3336 dev->sas_address = sa;
3337}
3338
3339/* Get a device id from inquiry page 0x83 */
1b70150a
SC		 3340static int hpsa_vpd_page_supported(struct ctlr_info *h,
3341 unsigned char scsi3addr[], u8 page)
3342{
3343 int rc;
3344 int i;
3345 int pages;
3346 unsigned char *buf, bufsize;
3347
3348 buf = kzalloc(256, GFP_KERNEL);
3349 if (!buf)
3350 return 0;
3351
3352 /* Get the size of the page list first */
3353 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3354 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3355 buf, HPSA_VPD_HEADER_SZ);
3356 if (rc != 0)
3357 goto exit_unsupported;
3358 pages = buf[3];
3359 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3360 bufsize = pages + HPSA_VPD_HEADER_SZ;
3361 else
3362 bufsize = 255;
3363
3364 /* Get the whole VPD page list */
3365 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3366 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3367 buf, bufsize);
3368 if (rc != 0)
3369 goto exit_unsupported;
3370
3371 pages = buf[3];
3372 for (i = 1; i <= pages; i++)
3373 if (buf[3 + i] == page)
3374 goto exit_supported;
3375exit_unsupported:
3376 kfree(buf);
3377 return 0;
3378exit_supported:
3379 kfree(buf);
3380 return 1;
3381}
3382
283b4a9b
SC		 3383static void hpsa_get_ioaccel_status(struct ctlr_info *h,
3384 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3385{
3386 int rc;
3387 unsigned char *buf;
3388 u8 ioaccel_status;
3389
3390 this_device->offload_config = 0;
3391 this_device->offload_enabled = 0;
41ce4c35 3392 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 3393
3394 buf = kzalloc(64, GFP_KERNEL);
3395 if (!buf)
3396 return;
1b70150a
SC		 3397 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
3398 goto out;
283b4a9b 3399 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 3400 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 3401 if (rc != 0)
3402 goto out;
3403
3404#define IOACCEL_STATUS_BYTE 4
3405#define OFFLOAD_CONFIGURED_BIT 0x01
3406#define OFFLOAD_ENABLED_BIT 0x02
3407 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
3408 this_device->offload_config =
3409 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3410 if (this_device->offload_config) {
3411 this_device->offload_enabled =
3412 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3413 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3414 this_device->offload_enabled = 0;
3415 }
41ce4c35 3416 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 3417out:
3418 kfree(buf);
3419 return;
3420}
3421
edd16368
SC		 3422/* Get the device id from inquiry page 0x83 */
3423static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
75d23d89 3424 unsigned char *device_id, int index, int buflen)
edd16368
SC		 3425{
3426 int rc;
3427 unsigned char *buf;
3428
3429 if (buflen > 16)
3430 buflen = 16;
3431 buf = kzalloc(64, GFP_KERNEL);
3432 if (!buf)
a84d794d 3433 return -ENOMEM;
b7bb24eb 3434 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368 3435 if (rc == 0)
75d23d89
DB		 3436 memcpy(device_id, &buf[index], buflen);
3437
edd16368 3438 kfree(buf);
75d23d89 3439
edd16368
SC		 3440 return rc != 0;
3441}
3442
3443static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 3444 void *buf, int bufsize,
edd16368
SC		 3445 int extended_response)
3446{
3447 int rc = IO_OK;
3448 struct CommandList *c;
3449 unsigned char scsi3addr[8];
3450 struct ErrorInfo *ei;
3451
45fcb86e 3452 c = cmd_alloc(h);
bf43caf3 3453
e89c0ae7
SC		 3454 /* address the controller */
3455 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 3456 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3457 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3458 rc = -1;
3459 goto out;
3460 }
edd16368
SC		 3461 if (extended_response)
3462 c->Request.CDB[1] = extended_response;
25163bd5
WS		 3463 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3464 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3465 if (rc)
3466 goto out;
edd16368
SC		 3467 ei = c->err_info;
3468 if (ei->CommandStatus != 0 &&
3469 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3470 hpsa_scsi_interpret_error(h, c);
edd16368 3471 rc = -1;
283b4a9b 3472 } else {
03383736
DB		 3473 struct ReportLUNdata *rld = buf;
3474
3475 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 3476 dev_err(&h->pdev->dev,
3477 "report luns requested format %u, got %u\n",
3478 extended_response,
03383736 3479 rld->extended_response_flag);
283b4a9b
SC		 3480 rc = -1;
3481 }
edd16368 3482 }
a2dac136 3483out:
45fcb86e 3484 cmd_free(h, c);
edd16368
SC		 3485 return rc;
3486}
3487
3488static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 3489 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 3490{
03383736
DB		 3491 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3492 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 3493}
3494
3495static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3496 struct ReportLUNdata *buf, int bufsize)
3497{
3498 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3499}
3500
3501static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3502 int bus, int target, int lun)
3503{
3504 device->bus = bus;
3505 device->target = target;
3506 device->lun = lun;
3507}
3508
9846590e
SC		 3509/* Use VPD inquiry to get details of volume status */
3510static int hpsa_get_volume_status(struct ctlr_info *h,
3511 unsigned char scsi3addr[])
3512{
3513 int rc;
3514 int status;
3515 int size;
3516 unsigned char *buf;
3517
3518 buf = kzalloc(64, GFP_KERNEL);
3519 if (!buf)
3520 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3521
3522 /* Does controller have VPD for logical volume status? */
24a4b078 3523 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 3524 goto exit_failed;
9846590e
SC		 3525
3526 /* Get the size of the VPD return buffer */
3527 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3528 buf, HPSA_VPD_HEADER_SZ);
24a4b078 3529 if (rc != 0)
9846590e 3530 goto exit_failed;
9846590e
SC		 3531 size = buf[3];
3532
3533 /* Now get the whole VPD buffer */
3534 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3535 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 3536 if (rc != 0)
9846590e 3537 goto exit_failed;
9846590e
SC		 3538 status = buf[4]; /* status byte */
3539
3540 kfree(buf);
3541 return status;
3542exit_failed:
3543 kfree(buf);
3544 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3545}
3546
3547/* Determine offline status of a volume.
3548 * Return either:
3549 * 0 (not offline)
67955ba3 3550 * 0xff (offline for unknown reasons)
9846590e
SC		 3551 * # (integer code indicating one of several NOT READY states
3552 * describing why a volume is to be kept offline)
3553 */
67955ba3 3554static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 3555 unsigned char scsi3addr[])
3556{
3557 struct CommandList *c;
9437ac43
SC		 3558 unsigned char *sense;
3559 u8 sense_key, asc, ascq;
3560 int sense_len;
25163bd5 3561 int rc, ldstat = 0;
9846590e
SC		 3562 u16 cmd_status;
3563 u8 scsi_status;
3564#define ASC_LUN_NOT_READY 0x04
3565#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3566#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3567
3568 c = cmd_alloc(h);
bf43caf3 3569
9846590e 3570 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
25163bd5
WS		 3571 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3572 if (rc) {
3573 cmd_free(h, c);
3574 return 0;
3575 }
9846590e 3576 sense = c->err_info->SenseInfo;
9437ac43
SC		 3577 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3578 sense_len = sizeof(c->err_info->SenseInfo);
3579 else
3580 sense_len = c->err_info->SenseLen;
3581 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 3582 cmd_status = c->err_info->CommandStatus;
3583 scsi_status = c->err_info->ScsiStatus;
3584 cmd_free(h, c);
3585 /* Is the volume 'not ready'? */
3586 if (cmd_status != CMD_TARGET_STATUS ||
3587 scsi_status != SAM_STAT_CHECK_CONDITION ||
3588 sense_key != NOT_READY ||
3589 asc != ASC_LUN_NOT_READY) {
3590 return 0;
3591 }
3592
3593 /* Determine the reason for not ready state */
3594 ldstat = hpsa_get_volume_status(h, scsi3addr);
3595
3596 /* Keep volume offline in certain cases: */
3597 switch (ldstat) {
3598 case HPSA_LV_UNDERGOING_ERASE:
5ca01204 3599 case HPSA_LV_NOT_AVAILABLE:
9846590e
SC		 3600 case HPSA_LV_UNDERGOING_RPI:
3601 case HPSA_LV_PENDING_RPI:
3602 case HPSA_LV_ENCRYPTED_NO_KEY:
3603 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3604 case HPSA_LV_UNDERGOING_ENCRYPTION:
3605 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3606 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3607 return ldstat;
3608 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3609 /* If VPD status page isn't available,
3610 * use ASC/ASCQ to determine state
3611 */
3612 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3613 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3614 return ldstat;
3615 break;
3616 default:
3617 break;
3618 }
3619 return 0;
3620}
3621
9b5c48c2
SC		 3622/*
3623 * Find out if a logical device supports aborts by simply trying one.
3624 * Smart Array may claim not to support aborts on logical drives, but
3625 * if a MSA2000 * is connected, the drives on that will be presented
3626 * by the Smart Array as logical drives, and aborts may be sent to
3627 * those devices successfully. So the simplest way to find out is
3628 * to simply try an abort and see how the device responds.
3629 */
3630static int hpsa_device_supports_aborts(struct ctlr_info *h,
3631 unsigned char *scsi3addr)
3632{
3633 struct CommandList *c;
3634 struct ErrorInfo *ei;
3635 int rc = 0;
3636
3637 u64 tag = (u64) -1; /* bogus tag */
3638
3639 /* Assume that physical devices support aborts */
3640 if (!is_logical_dev_addr_mode(scsi3addr))
3641 return 1;
3642
3643 c = cmd_alloc(h);
bf43caf3 3644
9b5c48c2
SC		 3645 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
3646 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3647 /* no unmap needed here because no data xfer. */
3648 ei = c->err_info;
3649 switch (ei->CommandStatus) {
3650 case CMD_INVALID:
3651 rc = 0;
3652 break;
3653 case CMD_UNABORTABLE:
3654 case CMD_ABORT_FAILED:
3655 rc = 1;
3656 break;
9437ac43
SC		 3657 case CMD_TMF_STATUS:
3658 rc = hpsa_evaluate_tmf_status(h, c);
3659 break;
9b5c48c2
SC		 3660 default:
3661 rc = 0;
3662 break;
3663 }
3664 cmd_free(h, c);
3665 return rc;
3666}
3667
75d23d89
DB		 3668static void sanitize_inquiry_string(unsigned char *s, int len)
3669{
3670 bool terminated = false;
3671
3672 for (; len > 0; (--len, ++s)) {
3673 if (*s == 0)
3674 terminated = true;
3675 if (terminated || *s < 0x20 || *s > 0x7e)
3676 *s = ' ';
3677 }
3678}
3679
edd16368 3680static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3681 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3682 unsigned char *is_OBDR_device)
edd16368 3683{
0b0e1d6c
SC		 3684
3685#define OBDR_SIG_OFFSET 43
3686#define OBDR_TAPE_SIG "$DR-10"
3687#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3688#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3689
ea6d3bc3 3690 unsigned char *inq_buff;
0b0e1d6c 3691 unsigned char *obdr_sig;
683fc444 3692 int rc = 0;
edd16368 3693
ea6d3bc3 3694 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
683fc444
DB		 3695 if (!inq_buff) {
3696 rc = -ENOMEM;
edd16368 3697 goto bail_out;
683fc444 3698 }
edd16368 3699
edd16368
SC		 3700 /* Do an inquiry to the device to see what it is. */
3701 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3702 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3703 /* Inquiry failed (msg printed already) */
3704 dev_err(&h->pdev->dev,
3705 "hpsa_update_device_info: inquiry failed\n");
683fc444 3706 rc = -EIO;
edd16368
SC		 3707 goto bail_out;
3708 }
3709
75d23d89
DB		 3710 sanitize_inquiry_string(&inq_buff[8], 8);
3711 sanitize_inquiry_string(&inq_buff[16], 16);
3712
edd16368
SC		 3713 this_device->devtype = (inq_buff[0] & 0x1f);
3714 memcpy(this_device->scsi3addr, scsi3addr, 8);
3715 memcpy(this_device->vendor, &inq_buff[8],
3716 sizeof(this_device->vendor));
3717 memcpy(this_device->model, &inq_buff[16],
3718 sizeof(this_device->model));
edd16368
SC		 3719 memset(this_device->device_id, 0,
3720 sizeof(this_device->device_id));
75d23d89 3721 hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8,
edd16368
SC		 3722 sizeof(this_device->device_id));
3723
af15ed36
DB		 3724 if ((this_device->devtype == TYPE_DISK ||
3725 this_device->devtype == TYPE_ZBC) &&
283b4a9b 3726 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3727 int volume_offline;
3728
edd16368 3729 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3730 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3731 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3732 volume_offline = hpsa_volume_offline(h, scsi3addr);
3733 if (volume_offline < 0 || volume_offline > 0xff)
3734 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3735 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3736 } else {
edd16368 3737 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3738 this_device->offload_config = 0;
3739 this_device->offload_enabled = 0;
41ce4c35 3740 this_device->offload_to_be_enabled = 0;
a3144e0b 3741 this_device->hba_ioaccel_enabled = 0;
9846590e 3742 this_device->volume_offline = 0;
03383736 3743 this_device->queue_depth = h->nr_cmds;
283b4a9b 3744 }
edd16368 3745
0b0e1d6c
SC		 3746 if (is_OBDR_device) {
3747 /* See if this is a One-Button-Disaster-Recovery device
3748 * by looking for "$DR-10" at offset 43 in inquiry data.
3749 */
3750 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3751 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3752 strncmp(obdr_sig, OBDR_TAPE_SIG,
3753 OBDR_SIG_LEN) == 0);
3754 }
edd16368
SC		 3755 kfree(inq_buff);
3756 return 0;
3757
3758bail_out:
3759 kfree(inq_buff);
683fc444 3760 return rc;
edd16368
SC		 3761}
3762
9b5c48c2
SC		 3763static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3764 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3765{
3766 unsigned long flags;
3767 int rc, entry;
3768 /*
3769 * See if this device supports aborts. If we already know
3770 * the device, we already know if it supports aborts, otherwise
3771 * we have to find out if it supports aborts by trying one.
3772 */
3773 spin_lock_irqsave(&h->devlock, flags);
3774 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3775 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3776 entry >= 0 && entry < h->ndevices) {
3777 dev->supports_aborts = h->dev[entry]->supports_aborts;
3778 spin_unlock_irqrestore(&h->devlock, flags);
3779 } else {
3780 spin_unlock_irqrestore(&h->devlock, flags);
3781 dev->supports_aborts =
3782 hpsa_device_supports_aborts(h, scsi3addr);
3783 if (dev->supports_aborts < 0)
3784 dev->supports_aborts = 0;
3785 }
3786}
3787
c795505a
KB		 3788/*
3789 * Helper function to assign bus, target, lun mapping of devices.
edd16368
SC		 3790 * Logical drive target and lun are assigned at this time, but
3791 * physical device lun and target assignment are deferred (assigned
3792 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
c795505a 3793*/
edd16368 3794static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3795 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3796{
c795505a 3797 u32 lunid = get_unaligned_le32(lunaddrbytes);
1f310bde
SC		 3798
3799 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3800 /* physical device, target and lun filled in later */
edd16368 3801 if (is_hba_lunid(lunaddrbytes))
c795505a
KB		 3802 hpsa_set_bus_target_lun(device,
3803 HPSA_HBA_BUS, 0, lunid & 0x3fff);
edd16368 3804 else
1f310bde 3805 /* defer target, lun assignment for physical devices */
c795505a
KB		 3806 hpsa_set_bus_target_lun(device,
3807 HPSA_PHYSICAL_DEVICE_BUS, -1, -1);
1f310bde
SC		 3808 return;
3809 }
3810 /* It's a logical device */
66749d0d 3811 if (device->external) {
1f310bde 3812 hpsa_set_bus_target_lun(device,
c795505a
KB		 3813 HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff,
3814 lunid & 0x00ff);
1f310bde 3815 return;
edd16368 3816 }
c795505a
KB		 3817 hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS,
3818 0, lunid & 0x3fff);
edd16368
SC		 3819}
3820
edd16368 3821
54b6e9e9
ST		 3822/*
3823 * Get address of physical disk used for an ioaccel2 mode command:
3824 * 1. Extract ioaccel2 handle from the command.
3825 * 2. Find a matching ioaccel2 handle from list of physical disks.
3826 * 3. Return:
3827 * 1 and set scsi3addr to address of matching physical
3828 * 0 if no matching physical disk was found.
3829 */
3830static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3831 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3832{
41ce4c35
SC		 3833 struct io_accel2_cmd *c2 =
3834 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3835 unsigned long flags;
54b6e9e9 3836 int i;
54b6e9e9 3837
41ce4c35
SC		 3838 spin_lock_irqsave(&h->devlock, flags);
3839 for (i = 0; i < h->ndevices; i++)
3840 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3841 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3842 sizeof(h->dev[i]->scsi3addr));
3843 spin_unlock_irqrestore(&h->devlock, flags);
3844 return 1;
3845 }
3846 spin_unlock_irqrestore(&h->devlock, flags);
3847 return 0;
54b6e9e9 3848}
41ce4c35 3849
66749d0d
ST		 3850static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position,
3851 int i, int nphysicals, int nlocal_logicals)
3852{
3853 /* In report logicals, local logicals are listed first,
3854 * then any externals.
3855 */
3856 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3857
3858 if (i == raid_ctlr_position)
3859 return 0;
3860
3861 if (i < logicals_start)
3862 return 0;
3863
3864 /* i is in logicals range, but still within local logicals */
3865 if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals)
3866 return 0;
3867
3868 return 1; /* it's an external lun */
3869}
3870
edd16368
SC		 3871/*
3872 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3873 * logdev. The number of luns in physdev and logdev are returned in
3874 * *nphysicals and *nlogicals, respectively.
3875 * Returns 0 on success, -1 otherwise.
3876 */
3877static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3878 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3879 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3880{
03383736 3881 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3882 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3883 return -1;
3884 }
03383736 3885 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3886 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3887 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3888 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3889 *nphysicals = HPSA_MAX_PHYS_LUN;
3890 }
03383736 3891 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3892 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3893 return -1;
3894 }
6df1e954 3895 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3896 /* Reject Logicals in excess of our max capability. */
3897 if (*nlogicals > HPSA_MAX_LUN) {
3898 dev_warn(&h->pdev->dev,
3899 "maximum logical LUNs (%d) exceeded. "
3900 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3901 *nlogicals - HPSA_MAX_LUN);
3902 *nlogicals = HPSA_MAX_LUN;
3903 }
3904 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3905 dev_warn(&h->pdev->dev,
3906 "maximum logical + physical LUNs (%d) exceeded. "
3907 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3908 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3909 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3910 }
3911 return 0;
3912}
3913
42a91641
DB		 3914static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3915 int i, int nphysicals, int nlogicals,
a93aa1fe 3916 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3917 struct ReportLUNdata *logdev_list)
3918{
3919 /* Helper function, figure out where the LUN ID info is coming from
3920 * given index i, lists of physical and logical devices, where in
3921 * the list the raid controller is supposed to appear (first or last)
3922 */
3923
3924 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3925 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3926
3927 if (i == raid_ctlr_position)
3928 return RAID_CTLR_LUNID;
3929
3930 if (i < logicals_start)
d5b5d964
SC		 3931 return &physdev_list->LUN[i -
3932 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3933
3934 if (i < last_device)
3935 return &logdev_list->LUN[i - nphysicals -
3936 (raid_ctlr_position == 0)][0];
3937 BUG();
3938 return NULL;
3939}
3940
03383736
DB		 3941/* get physical drive ioaccel handle and queue depth */
3942static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3943 struct hpsa_scsi_dev_t *dev,
f2039b03 3944 struct ReportExtendedLUNdata *rlep, int rle_index,
03383736
DB		 3945 struct bmic_identify_physical_device *id_phys)
3946{
3947 int rc;
f2039b03 3948 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
03383736
DB		 3949
3950 dev->ioaccel_handle = rle->ioaccel_handle;
f2039b03 3951 if ((rle->device_flags & 0x08) && dev->ioaccel_handle)
a3144e0b 3952 dev->hba_ioaccel_enabled = 1;
03383736 3953 memset(id_phys, 0, sizeof(*id_phys));
f2039b03
DB		 3954 rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0],
3955 GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys,
03383736
DB		 3956 sizeof(*id_phys));
3957 if (!rc)
3958 /* Reserve space for FW operations */
3959#define DRIVE_CMDS_RESERVED_FOR_FW 2
3960#define DRIVE_QUEUE_DEPTH 7
3961 dev->queue_depth =
3962 le16_to_cpu(id_phys->current_queue_depth_limit) -
3963 DRIVE_CMDS_RESERVED_FOR_FW;
3964 else
3965 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
03383736
DB		 3966}
3967
8270b862 3968static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
f2039b03 3969 struct ReportExtendedLUNdata *rlep, int rle_index,
8270b862
JH		 3970 struct bmic_identify_physical_device *id_phys)
3971{
f2039b03
DB		 3972 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
3973
3974 if ((rle->device_flags & 0x08) && this_device->ioaccel_handle)
8270b862
JH		 3975 this_device->hba_ioaccel_enabled = 1;
3976
3977 memcpy(&this_device->active_path_index,
3978 &id_phys->active_path_number,
3979 sizeof(this_device->active_path_index));
3980 memcpy(&this_device->path_map,
3981 &id_phys->redundant_path_present_map,
3982 sizeof(this_device->path_map));
3983 memcpy(&this_device->box,
3984 &id_phys->alternate_paths_phys_box_on_port,
3985 sizeof(this_device->box));
3986 memcpy(&this_device->phys_connector,
3987 &id_phys->alternate_paths_phys_connector,
3988 sizeof(this_device->phys_connector));
3989 memcpy(&this_device->bay,
3990 &id_phys->phys_bay_in_box,
3991 sizeof(this_device->bay));
3992}
3993
66749d0d
ST		 3994/* get number of local logical disks. */
3995static int hpsa_set_local_logical_count(struct ctlr_info *h,
3996 struct bmic_identify_controller *id_ctlr,
3997 u32 *nlocals)
3998{
3999 int rc;
4000
4001 if (!id_ctlr) {
4002 dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n",
4003 __func__);
4004 return -ENOMEM;
4005 }
4006 memset(id_ctlr, 0, sizeof(*id_ctlr));
4007 rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr));
4008 if (!rc)
4009 if (id_ctlr->configured_logical_drive_count < 256)
4010 *nlocals = id_ctlr->configured_logical_drive_count;
4011 else
4012 *nlocals = le16_to_cpu(
4013 id_ctlr->extended_logical_unit_count);
4014 else
4015 *nlocals = -1;
4016 return rc;
4017}
4018
4019
8aa60681 4020static void hpsa_update_scsi_devices(struct ctlr_info *h)
edd16368
SC		 4021{
4022 /* the idea here is we could get notified
4023 * that some devices have changed, so we do a report
4024 * physical luns and report logical luns cmd, and adjust
4025 * our list of devices accordingly.
4026 *
4027 * The scsi3addr's of devices won't change so long as the
4028 * adapter is not reset. That means we can rescan and
4029 * tell which devices we already know about, vs. new
4030 * devices, vs. disappearing devices.
4031 */
a93aa1fe 4032 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 4033 struct ReportLUNdata *logdev_list = NULL;
03383736 4034 struct bmic_identify_physical_device *id_phys = NULL;
66749d0d 4035 struct bmic_identify_controller *id_ctlr = NULL;
01a02ffc
SC		 4036 u32 nphysicals = 0;
4037 u32 nlogicals = 0;
66749d0d 4038 u32 nlocal_logicals = 0;
01a02ffc 4039 u32 ndev_allocated = 0;
edd16368
SC		 4040 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
4041 int ncurrent = 0;
4f4eb9f1 4042 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 4043 int raid_ctlr_position;
04fa2f44 4044 bool physical_device;
aca4a520 4045 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 4046
cfe5badc 4047 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 4048 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
4049 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 4050 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 4051 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
66749d0d 4052 id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL);
edd16368 4053
03383736 4054 if (!currentsd || !physdev_list || !logdev_list ||
66749d0d 4055 !tmpdevice || !id_phys || !id_ctlr) {
edd16368
SC		 4056 dev_err(&h->pdev->dev, "out of memory\n");
4057 goto out;
4058 }
4059 memset(lunzerobits, 0, sizeof(lunzerobits));
4060
853633e8
DB		 4061 h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */
4062
03383736 4063 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
853633e8
DB		 4064 logdev_list, &nlogicals)) {
4065 h->drv_req_rescan = 1;
edd16368 4066 goto out;
853633e8 4067 }
edd16368 4068
66749d0d
ST		 4069 /* Set number of local logicals (non PTRAID) */
4070 if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) {
4071 dev_warn(&h->pdev->dev,
4072 "%s: Can't determine number of local logical devices.\n",
4073 __func__);
4074 }
edd16368 4075
aca4a520
ST		 4076 /* We might see up to the maximum number of logical and physical disks
4077 * plus external target devices, and a device for the local RAID
4078 * controller.
edd16368 4079 */
aca4a520 4080 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 4081
4082 /* Allocate the per device structures */
4083 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 4084 if (i >= HPSA_MAX_DEVICES) {
4085 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
4086 " %d devices ignored.\n", HPSA_MAX_DEVICES,
4087 ndevs_to_allocate - HPSA_MAX_DEVICES);
4088 break;
4089 }
4090
edd16368
SC		 4091 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
4092 if (!currentsd[i]) {
4093 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
4094 __FILE__, __LINE__);
853633e8 4095 h->drv_req_rescan = 1;
edd16368
SC		 4096 goto out;
4097 }
4098 ndev_allocated++;
4099 }
4100
8645291b 4101 if (is_scsi_rev_5(h))
339b2b14
SC		 4102 raid_ctlr_position = 0;
4103 else
4104 raid_ctlr_position = nphysicals + nlogicals;
4105
edd16368 4106 /* adjust our table of devices */
4f4eb9f1 4107 n_ext_target_devs = 0;
edd16368 4108 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 4109 u8 *lunaddrbytes, is_OBDR = 0;
683fc444 4110 int rc = 0;
f2039b03 4111 int phys_dev_index = i - (raid_ctlr_position == 0);
edd16368 4112
04fa2f44 4113 physical_device = i < nphysicals + (raid_ctlr_position == 0);
edd16368
SC		 4114
4115 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 4116 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
4117 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 4118
4119 /* skip masked non-disk devices */
04fa2f44 4120 if (MASKED_DEVICE(lunaddrbytes) && physical_device &&
cca8f13b
DB		 4121 (physdev_list->LUN[phys_dev_index].device_type != 0x06) &&
4122 (physdev_list->LUN[phys_dev_index].device_flags & 0x01))
04fa2f44 4123 continue;
edd16368
SC		 4124
4125 /* Get device type, vendor, model, device id */
683fc444
DB		 4126 rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
4127 &is_OBDR);
4128 if (rc == -ENOMEM) {
4129 dev_warn(&h->pdev->dev,
4130 "Out of memory, rescan deferred.\n");
853633e8 4131 h->drv_req_rescan = 1;
683fc444 4132 goto out;
853633e8 4133 }
683fc444
DB		 4134 if (rc) {
4135 dev_warn(&h->pdev->dev,
4136 "Inquiry failed, skipping device.\n");
4137 continue;
4138 }
4139
66749d0d
ST		 4140 /* Determine if this is a lun from an external target array */
4141 tmpdevice->external =
4142 figure_external_status(h, raid_ctlr_position, i,
4143 nphysicals, nlocal_logicals);
4144
1f310bde 4145 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 4146 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 4147 this_device = currentsd[ncurrent];
4148
34592254
ST		 4149 /* Turn on discovery_polling if there are ext target devices.
4150 * Event-based change notification is unreliable for those.
edd16368 4151 */
34592254
ST		 4152 if (!h->discovery_polling) {
4153 if (tmpdevice->external) {
4154 h->discovery_polling = 1;
4155 dev_info(&h->pdev->dev,
4156 "External target, activate discovery polling.\n");
4157 }
edd16368
SC		 4158 }
4159
34592254 4160
edd16368 4161 *this_device = *tmpdevice;
04fa2f44 4162 this_device->physical_device = physical_device;
edd16368 4163
04fa2f44
KB		 4164 /*
4165 * Expose all devices except for physical devices that
4166 * are masked.
4167 */
4168 if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device)
2a168208
KB		 4169 this_device->expose_device = 0;
4170 else
4171 this_device->expose_device = 1;
41ce4c35 4172
d04e62b9
KB		 4173
4174 /*
4175 * Get the SAS address for physical devices that are exposed.
4176 */
4177 if (this_device->physical_device && this_device->expose_device)
4178 hpsa_get_sas_address(h, lunaddrbytes, this_device);
41ce4c35 4179
edd16368 4180 switch (this_device->devtype) {
0b0e1d6c 4181 case TYPE_ROM:
edd16368
SC		 4182 /* We don't *really* support actual CD-ROM devices,
4183 * just "One Button Disaster Recovery" tape drive
4184 * which temporarily pretends to be a CD-ROM drive.
4185 * So we check that the device is really an OBDR tape
4186 * device by checking for "$DR-10" in bytes 43-48 of
4187 * the inquiry data.
4188 */
0b0e1d6c
SC		 4189 if (is_OBDR)
4190 ncurrent++;
edd16368
SC		 4191 break;
4192 case TYPE_DISK:
af15ed36 4193 case TYPE_ZBC:
04fa2f44 4194 if (this_device->physical_device) {
b9092b79
KB		 4195 /* The disk is in HBA mode. */
4196 /* Never use RAID mapper in HBA mode. */
ecf418d1 4197 this_device->offload_enabled = 0;
b9092b79 4198 hpsa_get_ioaccel_drive_info(h, this_device,
f2039b03
DB		 4199 physdev_list, phys_dev_index, id_phys);
4200 hpsa_get_path_info(this_device,
4201 physdev_list, phys_dev_index, id_phys);
b9092b79 4202 }
ecf418d1 4203 ncurrent++;
edd16368
SC		 4204 break;
4205 case TYPE_TAPE:
4206 case TYPE_MEDIUM_CHANGER:
cca8f13b
DB		 4207 ncurrent++;
4208 break;
41ce4c35 4209 case TYPE_ENCLOSURE:
17a9e54a
DB		 4210 if (!this_device->external)
4211 hpsa_get_enclosure_info(h, lunaddrbytes,
cca8f13b
DB		 4212 physdev_list, phys_dev_index,
4213 this_device);
b9092b79 4214 ncurrent++;
41ce4c35 4215 break;
edd16368
SC		 4216 case TYPE_RAID:
4217 /* Only present the Smartarray HBA as a RAID controller.
4218 * If it's a RAID controller other than the HBA itself
4219 * (an external RAID controller, MSA500 or similar)
4220 * don't present it.
4221 */
4222 if (!is_hba_lunid(lunaddrbytes))
4223 break;
4224 ncurrent++;
4225 break;
4226 default:
4227 break;
4228 }
cfe5badc 4229 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 4230 break;
4231 }
d04e62b9
KB		 4232
4233 if (h->sas_host == NULL) {
4234 int rc = 0;
4235
4236 rc = hpsa_add_sas_host(h);
4237 if (rc) {
4238 dev_warn(&h->pdev->dev,
4239 "Could not add sas host %d\n", rc);
4240 goto out;
4241 }
4242 }
4243
8aa60681 4244 adjust_hpsa_scsi_table(h, currentsd, ncurrent);
edd16368
SC		 4245out:
4246 kfree(tmpdevice);
4247 for (i = 0; i < ndev_allocated; i++)
4248 kfree(currentsd[i]);
4249 kfree(currentsd);
edd16368
SC		 4250 kfree(physdev_list);
4251 kfree(logdev_list);
66749d0d 4252 kfree(id_ctlr);
03383736 4253 kfree(id_phys);
edd16368
SC		 4254}
4255
ec5cbf04
WS		 4256static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
4257 struct scatterlist *sg)
4258{
4259 u64 addr64 = (u64) sg_dma_address(sg);
4260 unsigned int len = sg_dma_len(sg);
4261
4262 desc->Addr = cpu_to_le64(addr64);
4263 desc->Len = cpu_to_le32(len);
4264 desc->Ext = 0;
4265}
4266
c7ee65b3
WS		 4267/*
4268 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 4269 * dma mapping and fills in the scatter gather entries of the
4270 * hpsa command, cp.
4271 */
33a2ffce 4272static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 4273 struct CommandList *cp,
4274 struct scsi_cmnd *cmd)
4275{
edd16368 4276 struct scatterlist *sg;
b3a7ba7c 4277 int use_sg, i, sg_limit, chained, last_sg;
33a2ffce 4278 struct SGDescriptor *curr_sg;
edd16368 4279
33a2ffce 4280 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 4281
4282 use_sg = scsi_dma_map(cmd);
4283 if (use_sg < 0)
4284 return use_sg;
4285
4286 if (!use_sg)
4287 goto sglist_finished;
4288
b3a7ba7c
WS		 4289 /*
4290 * If the number of entries is greater than the max for a single list,
4291 * then we have a chained list; we will set up all but one entry in the
4292 * first list (the last entry is saved for link information);
4293 * otherwise, we don't have a chained list and we'll set up at each of
4294 * the entries in the one list.
4295 */
33a2ffce 4296 curr_sg = cp->SG;
b3a7ba7c
WS		 4297 chained = use_sg > h->max_cmd_sg_entries;
4298 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
4299 last_sg = scsi_sg_count(cmd) - 1;
4300 scsi_for_each_sg(cmd, sg, sg_limit, i) {
ec5cbf04 4301 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 4302 curr_sg++;
4303 }
ec5cbf04 4304
b3a7ba7c
WS		 4305 if (chained) {
4306 /*
4307 * Continue with the chained list. Set curr_sg to the chained
4308 * list. Modify the limit to the total count less the entries
4309 * we've already set up. Resume the scan at the list entry
4310 * where the previous loop left off.
4311 */
4312 curr_sg = h->cmd_sg_list[cp->cmdindex];
4313 sg_limit = use_sg - sg_limit;
4314 for_each_sg(sg, sg, sg_limit, i) {
4315 hpsa_set_sg_descriptor(curr_sg, sg);
4316 curr_sg++;
4317 }
4318 }
4319
ec5cbf04 4320 /* Back the pointer up to the last entry and mark it as "last". */
b3a7ba7c 4321 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 4322
4323 if (use_sg + chained > h->maxSG)
4324 h->maxSG = use_sg + chained;
4325
4326 if (chained) {
4327 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 4328 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 4329 if (hpsa_map_sg_chain_block(h, cp)) {
4330 scsi_dma_unmap(cmd);
4331 return -1;
4332 }
33a2ffce 4333 return 0;
edd16368
SC		 4334 }
4335
4336sglist_finished:
4337
01a02ffc 4338 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 4339 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 4340 return 0;
4341}
4342
283b4a9b
SC		 4343#define IO_ACCEL_INELIGIBLE (1)
4344static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
4345{
4346 int is_write = 0;
4347 u32 block;
4348 u32 block_cnt;
4349
4350 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
4351 switch (cdb[0]) {
4352 case WRITE_6:
4353 case WRITE_12:
4354 is_write = 1;
4355 case READ_6:
4356 case READ_12:
4357 if (*cdb_len == 6) {
c8a6c9a6 4358 block = get_unaligned_be16(&cdb[2]);
283b4a9b 4359 block_cnt = cdb[4];
c8a6c9a6
DB		 4360 if (block_cnt == 0)
4361 block_cnt = 256;
283b4a9b
SC		 4362 } else {
4363 BUG_ON(*cdb_len != 12);
c8a6c9a6
DB		 4364 block = get_unaligned_be32(&cdb[2]);
4365 block_cnt = get_unaligned_be32(&cdb[6]);
283b4a9b
SC		 4366 }
4367 if (block_cnt > 0xffff)
4368 return IO_ACCEL_INELIGIBLE;
4369
4370 cdb[0] = is_write ? WRITE_10 : READ_10;
4371 cdb[1] = 0;
4372 cdb[2] = (u8) (block >> 24);
4373 cdb[3] = (u8) (block >> 16);
4374 cdb[4] = (u8) (block >> 8);
4375 cdb[5] = (u8) (block);
4376 cdb[6] = 0;
4377 cdb[7] = (u8) (block_cnt >> 8);
4378 cdb[8] = (u8) (block_cnt);
4379 cdb[9] = 0;
4380 *cdb_len = 10;
4381 break;
4382 }
4383 return 0;
4384}
4385
c349775e 4386static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 4387 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4388 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 4389{
4390 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 4391 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
4392 unsigned int len;
4393 unsigned int total_len = 0;
4394 struct scatterlist *sg;
4395 u64 addr64;
4396 int use_sg, i;
4397 struct SGDescriptor *curr_sg;
4398 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
4399
283b4a9b 4400 /* TODO: implement chaining support */
03383736
DB		 4401 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
4402 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4403 return IO_ACCEL_INELIGIBLE;
03383736 4404 }
283b4a9b 4405
e1f7de0c
MG		 4406 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
4407
03383736
DB		 4408 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4409 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4410 return IO_ACCEL_INELIGIBLE;
03383736 4411 }
283b4a9b 4412
e1f7de0c
MG		 4413 c->cmd_type = CMD_IOACCEL1;
4414
4415 /* Adjust the DMA address to point to the accelerated command buffer */
4416 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
4417 (c->cmdindex * sizeof(*cp));
4418 BUG_ON(c->busaddr & 0x0000007F);
4419
4420 use_sg = scsi_dma_map(cmd);
03383736
DB		 4421 if (use_sg < 0) {
4422 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 4423 return use_sg;
03383736 4424 }
e1f7de0c
MG		 4425
4426 if (use_sg) {
4427 curr_sg = cp->SG;
4428 scsi_for_each_sg(cmd, sg, use_sg, i) {
4429 addr64 = (u64) sg_dma_address(sg);
4430 len = sg_dma_len(sg);
4431 total_len += len;
50a0decf
SC		 4432 curr_sg->Addr = cpu_to_le64(addr64);
4433 curr_sg->Len = cpu_to_le32(len);
4434 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 4435 curr_sg++;
4436 }
50a0decf 4437 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 4438
4439 switch (cmd->sc_data_direction) {
4440 case DMA_TO_DEVICE:
4441 control |= IOACCEL1_CONTROL_DATA_OUT;
4442 break;
4443 case DMA_FROM_DEVICE:
4444 control |= IOACCEL1_CONTROL_DATA_IN;
4445 break;
4446 case DMA_NONE:
4447 control |= IOACCEL1_CONTROL_NODATAXFER;
4448 break;
4449 default:
4450 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4451 cmd->sc_data_direction);
4452 BUG();
4453 break;
4454 }
4455 } else {
4456 control |= IOACCEL1_CONTROL_NODATAXFER;
4457 }
4458
c349775e 4459 c->Header.SGList = use_sg;
e1f7de0c 4460 /* Fill out the command structure to submit */
2b08b3e9
DB		 4461 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4462 cp->transfer_len = cpu_to_le32(total_len);
4463 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4464 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4465 cp->control = cpu_to_le32(control);
283b4a9b
SC		 4466 memcpy(cp->CDB, cdb, cdb_len);
4467 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 4468 /* Tag was already set at init time. */
283b4a9b 4469 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 4470 return 0;
4471}
edd16368 4472
283b4a9b
SC		 4473/*
4474 * Queue a command directly to a device behind the controller using the
4475 * I/O accelerator path.
4476 */
4477static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4478 struct CommandList *c)
4479{
4480 struct scsi_cmnd *cmd = c->scsi_cmd;
4481 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4482
03383736
DB		 4483 c->phys_disk = dev;
4484
283b4a9b 4485 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 4486 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 4487}
4488
dd0e19f3
ST		 4489/*
4490 * Set encryption parameters for the ioaccel2 request
4491 */
4492static void set_encrypt_ioaccel2(struct ctlr_info *h,
4493 struct CommandList *c, struct io_accel2_cmd *cp)
4494{
4495 struct scsi_cmnd *cmd = c->scsi_cmd;
4496 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4497 struct raid_map_data *map = &dev->raid_map;
4498 u64 first_block;
4499
dd0e19f3 4500 /* Are we doing encryption on this device */
2b08b3e9 4501 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 4502 return;
4503 /* Set the data encryption key index. */
4504 cp->dekindex = map->dekindex;
4505
4506 /* Set the encryption enable flag, encoded into direction field. */
4507 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4508
4509 /* Set encryption tweak values based on logical block address
4510 * If block size is 512, tweak value is LBA.
4511 * For other block sizes, tweak is (LBA * block size)/ 512)
4512 */
4513 switch (cmd->cmnd[0]) {
4514 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
4515 case WRITE_6:
4516 case READ_6:
2b08b3e9 4517 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 4518 break;
4519 case WRITE_10:
4520 case READ_10:
dd0e19f3
ST		 4521 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4522 case WRITE_12:
4523 case READ_12:
2b08b3e9 4524 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 4525 break;
4526 case WRITE_16:
4527 case READ_16:
2b08b3e9 4528 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 4529 break;
4530 default:
4531 dev_err(&h->pdev->dev,
2b08b3e9
DB		 4532 "ERROR: %s: size (0x%x) not supported for encryption\n",
4533 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 4534 BUG();
4535 break;
4536 }
2b08b3e9
DB		 4537
4538 if (le32_to_cpu(map->volume_blk_size) != 512)
4539 first_block = first_block *
4540 le32_to_cpu(map->volume_blk_size)/512;
4541
4542 cp->tweak_lower = cpu_to_le32(first_block);
4543 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 4544}
4545
c349775e
ST		 4546static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4547 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4548 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 4549{
4550 struct scsi_cmnd *cmd = c->scsi_cmd;
4551 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4552 struct ioaccel2_sg_element *curr_sg;
4553 int use_sg, i;
4554 struct scatterlist *sg;
4555 u64 addr64;
4556 u32 len;
4557 u32 total_len = 0;
4558
d9a729f3 4559 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 4560
03383736
DB		 4561 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4562 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4563 return IO_ACCEL_INELIGIBLE;
03383736
DB		 4564 }
4565
c349775e
ST		 4566 c->cmd_type = CMD_IOACCEL2;
4567 /* Adjust the DMA address to point to the accelerated command buffer */
4568 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4569 (c->cmdindex * sizeof(*cp));
4570 BUG_ON(c->busaddr & 0x0000007F);
4571
4572 memset(cp, 0, sizeof(*cp));
4573 cp->IU_type = IOACCEL2_IU_TYPE;
4574
4575 use_sg = scsi_dma_map(cmd);
03383736
DB		 4576 if (use_sg < 0) {
4577 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4578 return use_sg;
03383736 4579 }
c349775e
ST		 4580
4581 if (use_sg) {
c349775e 4582 curr_sg = cp->sg;
d9a729f3
WS		 4583 if (use_sg > h->ioaccel_maxsg) {
4584 addr64 = le64_to_cpu(
4585 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4586 curr_sg->address = cpu_to_le64(addr64);
4587 curr_sg->length = 0;
4588 curr_sg->reserved[0] = 0;
4589 curr_sg->reserved[1] = 0;
4590 curr_sg->reserved[2] = 0;
4591 curr_sg->chain_indicator = 0x80;
4592
4593 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4594 }
c349775e
ST		 4595 scsi_for_each_sg(cmd, sg, use_sg, i) {
4596 addr64 = (u64) sg_dma_address(sg);
4597 len = sg_dma_len(sg);
4598 total_len += len;
4599 curr_sg->address = cpu_to_le64(addr64);
4600 curr_sg->length = cpu_to_le32(len);
4601 curr_sg->reserved[0] = 0;
4602 curr_sg->reserved[1] = 0;
4603 curr_sg->reserved[2] = 0;
4604 curr_sg->chain_indicator = 0;
4605 curr_sg++;
4606 }
4607
4608 switch (cmd->sc_data_direction) {
4609 case DMA_TO_DEVICE:
dd0e19f3
ST		 4610 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4611 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 4612 break;
4613 case DMA_FROM_DEVICE:
dd0e19f3
ST		 4614 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4615 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 4616 break;
4617 case DMA_NONE:
dd0e19f3
ST		 4618 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4619 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 4620 break;
4621 default:
4622 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4623 cmd->sc_data_direction);
4624 BUG();
4625 break;
4626 }
4627 } else {
dd0e19f3
ST		 4628 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4629 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 4630 }
dd0e19f3
ST		 4631
4632 /* Set encryption parameters, if necessary */
4633 set_encrypt_ioaccel2(h, c, cp);
4634
2b08b3e9 4635 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 4636 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 4637 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 4638
c349775e
ST		 4639 cp->data_len = cpu_to_le32(total_len);
4640 cp->err_ptr = cpu_to_le64(c->busaddr +
4641 offsetof(struct io_accel2_cmd, error_data));
50a0decf 4642 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 4643
d9a729f3
WS		 4644 /* fill in sg elements */
4645 if (use_sg > h->ioaccel_maxsg) {
4646 cp->sg_count = 1;
a736e9b6 4647 cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0]));
d9a729f3
WS		 4648 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4649 atomic_dec(&phys_disk->ioaccel_cmds_out);
4650 scsi_dma_unmap(cmd);
4651 return -1;
4652 }
4653 } else
4654 cp->sg_count = (u8) use_sg;
4655
c349775e
ST		 4656 enqueue_cmd_and_start_io(h, c);
4657 return 0;
4658}
4659
4660/*
4661 * Queue a command to the correct I/O accelerator path.
4662 */
4663static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4664 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4665 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 4666{
03383736
DB		 4667 /* Try to honor the device's queue depth */
4668 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4669 phys_disk->queue_depth) {
4670 atomic_dec(&phys_disk->ioaccel_cmds_out);
4671 return IO_ACCEL_INELIGIBLE;
4672 }
c349775e
ST		 4673 if (h->transMethod & CFGTBL_Trans_io_accel1)
4674 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4675 cdb, cdb_len, scsi3addr,
4676 phys_disk);
c349775e
ST		 4677 else
4678 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4679 cdb, cdb_len, scsi3addr,
4680 phys_disk);
c349775e
ST		 4681}
4682
6b80b18f
ST		 4683static void raid_map_helper(struct raid_map_data *map,
4684 int offload_to_mirror, u32 *map_index, u32 *current_group)
4685{
4686 if (offload_to_mirror == 0) {
4687 /* use physical disk in the first mirrored group. */
2b08b3e9 4688 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4689 return;
4690 }
4691 do {
4692 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4693 *current_group = *map_index /
4694 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4695 if (offload_to_mirror == *current_group)
4696 continue;
2b08b3e9 4697 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4698 /* select map index from next group */
2b08b3e9 4699 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4700 (*current_group)++;
4701 } else {
4702 /* select map index from first group */
2b08b3e9 4703 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4704 *current_group = 0;
4705 }
4706 } while (offload_to_mirror != *current_group);
4707}
4708
283b4a9b
SC		 4709/*
4710 * Attempt to perform offload RAID mapping for a logical volume I/O.
4711 */
4712static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4713 struct CommandList *c)
4714{
4715 struct scsi_cmnd *cmd = c->scsi_cmd;
4716 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4717 struct raid_map_data *map = &dev->raid_map;
4718 struct raid_map_disk_data *dd = &map->data[0];
4719 int is_write = 0;
4720 u32 map_index;
4721 u64 first_block, last_block;
4722 u32 block_cnt;
4723 u32 blocks_per_row;
4724 u64 first_row, last_row;
4725 u32 first_row_offset, last_row_offset;
4726 u32 first_column, last_column;
6b80b18f
ST		 4727 u64 r0_first_row, r0_last_row;
4728 u32 r5or6_blocks_per_row;
4729 u64 r5or6_first_row, r5or6_last_row;
4730 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4731 u32 r5or6_first_column, r5or6_last_column;
4732 u32 total_disks_per_row;
4733 u32 stripesize;
4734 u32 first_group, last_group, current_group;
283b4a9b
SC		 4735 u32 map_row;
4736 u32 disk_handle;
4737 u64 disk_block;
4738 u32 disk_block_cnt;
4739 u8 cdb[16];
4740 u8 cdb_len;
2b08b3e9 4741 u16 strip_size;
283b4a9b
SC		 4742#if BITS_PER_LONG == 32
4743 u64 tmpdiv;
4744#endif
6b80b18f 4745 int offload_to_mirror;
283b4a9b 4746
283b4a9b
SC		 4747 /* check for valid opcode, get LBA and block count */
4748 switch (cmd->cmnd[0]) {
4749 case WRITE_6:
4750 is_write = 1;
4751 case READ_6:
c8a6c9a6 4752 first_block = get_unaligned_be16(&cmd->cmnd[2]);
283b4a9b 4753 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4754 if (block_cnt == 0)
4755 block_cnt = 256;
283b4a9b
SC		 4756 break;
4757 case WRITE_10:
4758 is_write = 1;
4759 case READ_10:
4760 first_block =
4761 (((u64) cmd->cmnd[2]) << 24) |
4762 (((u64) cmd->cmnd[3]) << 16) |
4763 (((u64) cmd->cmnd[4]) << 8) |
4764 cmd->cmnd[5];
4765 block_cnt =
4766 (((u32) cmd->cmnd[7]) << 8) |
4767 cmd->cmnd[8];
4768 break;
4769 case WRITE_12:
4770 is_write = 1;
4771 case READ_12:
4772 first_block =
4773 (((u64) cmd->cmnd[2]) << 24) |
4774 (((u64) cmd->cmnd[3]) << 16) |
4775 (((u64) cmd->cmnd[4]) << 8) |
4776 cmd->cmnd[5];
4777 block_cnt =
4778 (((u32) cmd->cmnd[6]) << 24) |
4779 (((u32) cmd->cmnd[7]) << 16) |
4780 (((u32) cmd->cmnd[8]) << 8) |
4781 cmd->cmnd[9];
4782 break;
4783 case WRITE_16:
4784 is_write = 1;
4785 case READ_16:
4786 first_block =
4787 (((u64) cmd->cmnd[2]) << 56) |
4788 (((u64) cmd->cmnd[3]) << 48) |
4789 (((u64) cmd->cmnd[4]) << 40) |
4790 (((u64) cmd->cmnd[5]) << 32) |
4791 (((u64) cmd->cmnd[6]) << 24) |
4792 (((u64) cmd->cmnd[7]) << 16) |
4793 (((u64) cmd->cmnd[8]) << 8) |
4794 cmd->cmnd[9];
4795 block_cnt =
4796 (((u32) cmd->cmnd[10]) << 24) |
4797 (((u32) cmd->cmnd[11]) << 16) |
4798 (((u32) cmd->cmnd[12]) << 8) |
4799 cmd->cmnd[13];
4800 break;
4801 default:
4802 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4803 }
283b4a9b
SC		 4804 last_block = first_block + block_cnt - 1;
4805
4806 /* check for write to non-RAID-0 */
4807 if (is_write && dev->raid_level != 0)
4808 return IO_ACCEL_INELIGIBLE;
4809
4810 /* check for invalid block or wraparound */
2b08b3e9
DB		 4811 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4812 last_block < first_block)
283b4a9b
SC		 4813 return IO_ACCEL_INELIGIBLE;
4814
4815 /* calculate stripe information for the request */
2b08b3e9
DB		 4816 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4817 le16_to_cpu(map->strip_size);
4818 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4819#if BITS_PER_LONG == 32
4820 tmpdiv = first_block;
4821 (void) do_div(tmpdiv, blocks_per_row);
4822 first_row = tmpdiv;
4823 tmpdiv = last_block;
4824 (void) do_div(tmpdiv, blocks_per_row);
4825 last_row = tmpdiv;
4826 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4827 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4828 tmpdiv = first_row_offset;
2b08b3e9 4829 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4830 first_column = tmpdiv;
4831 tmpdiv = last_row_offset;
2b08b3e9 4832 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4833 last_column = tmpdiv;
4834#else
4835 first_row = first_block / blocks_per_row;
4836 last_row = last_block / blocks_per_row;
4837 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4838 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4839 first_column = first_row_offset / strip_size;
4840 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4841#endif
4842
4843 /* if this isn't a single row/column then give to the controller */
4844 if ((first_row != last_row) || (first_column != last_column))
4845 return IO_ACCEL_INELIGIBLE;
4846
4847 /* proceeding with driver mapping */
2b08b3e9
DB		 4848 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4849 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4850 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4851 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4852 map_index = (map_row * total_disks_per_row) + first_column;
4853
4854 switch (dev->raid_level) {
4855 case HPSA_RAID_0:
4856 break; /* nothing special to do */
4857 case HPSA_RAID_1:
4858 /* Handles load balance across RAID 1 members.
4859 * (2-drive R1 and R10 with even # of drives.)
4860 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4861 */
2b08b3e9 4862 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4863 if (dev->offload_to_mirror)
2b08b3e9 4864 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4865 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4866 break;
4867 case HPSA_RAID_ADM:
4868 /* Handles N-way mirrors (R1-ADM)
4869 * and R10 with # of drives divisible by 3.)
4870 */
2b08b3e9 4871 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4872
4873 offload_to_mirror = dev->offload_to_mirror;
4874 raid_map_helper(map, offload_to_mirror,
4875 &map_index, &current_group);
4876 /* set mirror group to use next time */
4877 offload_to_mirror =
2b08b3e9
DB		 4878 (offload_to_mirror >=
4879 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4880 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4881 dev->offload_to_mirror = offload_to_mirror;
4882 /* Avoid direct use of dev->offload_to_mirror within this
4883 * function since multiple threads might simultaneously
4884 * increment it beyond the range of dev->layout_map_count -1.
4885 */
4886 break;
4887 case HPSA_RAID_5:
4888 case HPSA_RAID_6:
2b08b3e9 4889 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4890 break;
4891
4892 /* Verify first and last block are in same RAID group */
4893 r5or6_blocks_per_row =
2b08b3e9
DB		 4894 le16_to_cpu(map->strip_size) *
4895 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4896 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4897 stripesize = r5or6_blocks_per_row *
4898 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4899#if BITS_PER_LONG == 32
4900 tmpdiv = first_block;
4901 first_group = do_div(tmpdiv, stripesize);
4902 tmpdiv = first_group;
4903 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4904 first_group = tmpdiv;
4905 tmpdiv = last_block;
4906 last_group = do_div(tmpdiv, stripesize);
4907 tmpdiv = last_group;
4908 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4909 last_group = tmpdiv;
4910#else
4911 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4912 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4913#endif
000ff7c2 4914 if (first_group != last_group)
6b80b18f
ST		 4915 return IO_ACCEL_INELIGIBLE;
4916
4917 /* Verify request is in a single row of RAID 5/6 */
4918#if BITS_PER_LONG == 32
4919 tmpdiv = first_block;
4920 (void) do_div(tmpdiv, stripesize);
4921 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4922 tmpdiv = last_block;
4923 (void) do_div(tmpdiv, stripesize);
4924 r5or6_last_row = r0_last_row = tmpdiv;
4925#else
4926 first_row = r5or6_first_row = r0_first_row =
4927 first_block / stripesize;
4928 r5or6_last_row = r0_last_row = last_block / stripesize;
4929#endif
4930 if (r5or6_first_row != r5or6_last_row)
4931 return IO_ACCEL_INELIGIBLE;
4932
4933
4934 /* Verify request is in a single column */
4935#if BITS_PER_LONG == 32
4936 tmpdiv = first_block;
4937 first_row_offset = do_div(tmpdiv, stripesize);
4938 tmpdiv = first_row_offset;
4939 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4940 r5or6_first_row_offset = first_row_offset;
4941 tmpdiv = last_block;
4942 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4943 tmpdiv = r5or6_last_row_offset;
4944 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4945 tmpdiv = r5or6_first_row_offset;
4946 (void) do_div(tmpdiv, map->strip_size);
4947 first_column = r5or6_first_column = tmpdiv;
4948 tmpdiv = r5or6_last_row_offset;
4949 (void) do_div(tmpdiv, map->strip_size);
4950 r5or6_last_column = tmpdiv;
4951#else
4952 first_row_offset = r5or6_first_row_offset =
4953 (u32)((first_block % stripesize) %
4954 r5or6_blocks_per_row);
4955
4956 r5or6_last_row_offset =
4957 (u32)((last_block % stripesize) %
4958 r5or6_blocks_per_row);
4959
4960 first_column = r5or6_first_column =
2b08b3e9 4961 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4962 r5or6_last_column =
2b08b3e9 4963 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4964#endif
4965 if (r5or6_first_column != r5or6_last_column)
4966 return IO_ACCEL_INELIGIBLE;
4967
4968 /* Request is eligible */
4969 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4970 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4971
4972 map_index = (first_group *
2b08b3e9 4973 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4974 (map_row * total_disks_per_row) + first_column;
4975 break;
4976 default:
4977 return IO_ACCEL_INELIGIBLE;
283b4a9b 4978 }
6b80b18f 4979
07543e0c
SC		 4980 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4981 return IO_ACCEL_INELIGIBLE;
4982
03383736
DB		 4983 c->phys_disk = dev->phys_disk[map_index];
4984
283b4a9b 4985 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 4986 disk_block = le64_to_cpu(map->disk_starting_blk) +
4987 first_row * le16_to_cpu(map->strip_size) +
4988 (first_row_offset - first_column *
4989 le16_to_cpu(map->strip_size));
283b4a9b
SC		 4990 disk_block_cnt = block_cnt;
4991
4992 /* handle differing logical/physical block sizes */
4993 if (map->phys_blk_shift) {
4994 disk_block <<= map->phys_blk_shift;
4995 disk_block_cnt <<= map->phys_blk_shift;
4996 }
4997 BUG_ON(disk_block_cnt > 0xffff);
4998
4999 /* build the new CDB for the physical disk I/O */
5000 if (disk_block > 0xffffffff) {
5001 cdb[0] = is_write ? WRITE_16 : READ_16;
5002 cdb[1] = 0;
5003 cdb[2] = (u8) (disk_block >> 56);
5004 cdb[3] = (u8) (disk_block >> 48);
5005 cdb[4] = (u8) (disk_block >> 40);
5006 cdb[5] = (u8) (disk_block >> 32);
5007 cdb[6] = (u8) (disk_block >> 24);
5008 cdb[7] = (u8) (disk_block >> 16);
5009 cdb[8] = (u8) (disk_block >> 8);
5010 cdb[9] = (u8) (disk_block);
5011 cdb[10] = (u8) (disk_block_cnt >> 24);
5012 cdb[11] = (u8) (disk_block_cnt >> 16);
5013 cdb[12] = (u8) (disk_block_cnt >> 8);
5014 cdb[13] = (u8) (disk_block_cnt);
5015 cdb[14] = 0;
5016 cdb[15] = 0;
5017 cdb_len = 16;
5018 } else {
5019 cdb[0] = is_write ? WRITE_10 : READ_10;
5020 cdb[1] = 0;
5021 cdb[2] = (u8) (disk_block >> 24);
5022 cdb[3] = (u8) (disk_block >> 16);
5023 cdb[4] = (u8) (disk_block >> 8);
5024 cdb[5] = (u8) (disk_block);
5025 cdb[6] = 0;
5026 cdb[7] = (u8) (disk_block_cnt >> 8);
5027 cdb[8] = (u8) (disk_block_cnt);
5028 cdb[9] = 0;
5029 cdb_len = 10;
5030 }
5031 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 5032 dev->scsi3addr,
5033 dev->phys_disk[map_index]);
283b4a9b
SC		 5034}
5035
25163bd5
WS		 5036/*
5037 * Submit commands down the "normal" RAID stack path
5038 * All callers to hpsa_ciss_submit must check lockup_detected
5039 * beforehand, before (opt.) and after calling cmd_alloc
5040 */
574f05d3
SC		 5041static int hpsa_ciss_submit(struct ctlr_info *h,
5042 struct CommandList *c, struct scsi_cmnd *cmd,
5043 unsigned char scsi3addr[])
edd16368 5044{
edd16368 5045 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 5046 c->cmd_type = CMD_SCSI;
5047 c->scsi_cmd = cmd;
5048 c->Header.ReplyQueue = 0; /* unused in simple mode */
5049 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 5050 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 5051
5052 /* Fill in the request block... */
5053
5054 c->Request.Timeout = 0;
edd16368
SC		 5055 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
5056 c->Request.CDBLen = cmd->cmd_len;
5057 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 5058 switch (cmd->sc_data_direction) {
5059 case DMA_TO_DEVICE:
a505b86f
SC		 5060 c->Request.type_attr_dir =
5061 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5062 break;
5063 case DMA_FROM_DEVICE:
a505b86f
SC		 5064 c->Request.type_attr_dir =
5065 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5066 break;
5067 case DMA_NONE:
a505b86f
SC		 5068 c->Request.type_attr_dir =
5069 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5070 break;
5071 case DMA_BIDIRECTIONAL:
5072 /* This can happen if a buggy application does a scsi passthru
5073 * and sets both inlen and outlen to non-zero. ( see
5074 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
5075 */
5076
a505b86f
SC		 5077 c->Request.type_attr_dir =
5078 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 5079 /* This is technically wrong, and hpsa controllers should
5080 * reject it with CMD_INVALID, which is the most correct
5081 * response, but non-fibre backends appear to let it
5082 * slide by, and give the same results as if this field
5083 * were set correctly. Either way is acceptable for
5084 * our purposes here.
5085 */
5086
5087 break;
5088
5089 default:
5090 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
5091 cmd->sc_data_direction);
5092 BUG();
5093 break;
5094 }
5095
33a2ffce 5096 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
73153fe5 5097 hpsa_cmd_resolve_and_free(h, c);
edd16368
SC		 5098 return SCSI_MLQUEUE_HOST_BUSY;
5099 }
5100 enqueue_cmd_and_start_io(h, c);
5101 /* the cmd'll come back via intr handler in complete_scsi_command() */
5102 return 0;
5103}
5104
360c73bd
SC		 5105static void hpsa_cmd_init(struct ctlr_info *h, int index,
5106 struct CommandList *c)
5107{
5108 dma_addr_t cmd_dma_handle, err_dma_handle;
5109
5110 /* Zero out all of commandlist except the last field, refcount */
5111 memset(c, 0, offsetof(struct CommandList, refcount));
5112 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
5113 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
5114 c->err_info = h->errinfo_pool + index;
5115 memset(c->err_info, 0, sizeof(*c->err_info));
5116 err_dma_handle = h->errinfo_pool_dhandle
5117 + index * sizeof(*c->err_info);
5118 c->cmdindex = index;
5119 c->busaddr = (u32) cmd_dma_handle;
5120 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
5121 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
5122 c->h = h;
a58e7e53 5123 c->scsi_cmd = SCSI_CMD_IDLE;
360c73bd
SC		 5124}
5125
5126static void hpsa_preinitialize_commands(struct ctlr_info *h)
5127{
5128 int i;
5129
5130 for (i = 0; i < h->nr_cmds; i++) {
5131 struct CommandList *c = h->cmd_pool + i;
5132
5133 hpsa_cmd_init(h, i, c);
5134 atomic_set(&c->refcount, 0);
5135 }
5136}
5137
5138static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
5139 struct CommandList *c)
5140{
5141 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
5142
73153fe5
WS		 5143 BUG_ON(c->cmdindex != index);
5144
360c73bd
SC		 5145 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
5146 memset(c->err_info, 0, sizeof(*c->err_info));
5147 c->busaddr = (u32) cmd_dma_handle;
5148}
5149
592a0ad5
WS		 5150static int hpsa_ioaccel_submit(struct ctlr_info *h,
5151 struct CommandList *c, struct scsi_cmnd *cmd,
5152 unsigned char *scsi3addr)
5153{
5154 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
5155 int rc = IO_ACCEL_INELIGIBLE;
5156
5157 cmd->host_scribble = (unsigned char *) c;
5158
5159 if (dev->offload_enabled) {
5160 hpsa_cmd_init(h, c->cmdindex, c);
5161 c->cmd_type = CMD_SCSI;
5162 c->scsi_cmd = cmd;
5163 rc = hpsa_scsi_ioaccel_raid_map(h, c);
5164 if (rc < 0) /* scsi_dma_map failed. */
5165 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 5166 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 5167 hpsa_cmd_init(h, c->cmdindex, c);
5168 c->cmd_type = CMD_SCSI;
5169 c->scsi_cmd = cmd;
5170 rc = hpsa_scsi_ioaccel_direct_map(h, c);
5171 if (rc < 0) /* scsi_dma_map failed. */
5172 rc = SCSI_MLQUEUE_HOST_BUSY;
5173 }
5174 return rc;
5175}
5176
080ef1cc
DB		 5177static void hpsa_command_resubmit_worker(struct work_struct *work)
5178{
5179 struct scsi_cmnd *cmd;
5180 struct hpsa_scsi_dev_t *dev;
8a0ff92c 5181 struct CommandList *c = container_of(work, struct CommandList, work);
080ef1cc
DB		 5182
5183 cmd = c->scsi_cmd;
5184 dev = cmd->device->hostdata;
5185 if (!dev) {
5186 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 5187 return hpsa_cmd_free_and_done(c->h, c, cmd);
080ef1cc 5188 }
d604f533
WS		 5189 if (c->reset_pending)
5190 return hpsa_cmd_resolve_and_free(c->h, c);
a58e7e53
WS		 5191 if (c->abort_pending)
5192 return hpsa_cmd_abort_and_free(c->h, c, cmd);
592a0ad5
WS		 5193 if (c->cmd_type == CMD_IOACCEL2) {
5194 struct ctlr_info *h = c->h;
5195 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5196 int rc;
5197
5198 if (c2->error_data.serv_response ==
5199 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
5200 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
5201 if (rc == 0)
5202 return;
5203 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
5204 /*
5205 * If we get here, it means dma mapping failed.
5206 * Try again via scsi mid layer, which will
5207 * then get SCSI_MLQUEUE_HOST_BUSY.
5208 */
5209 cmd->result = DID_IMM_RETRY << 16;
8a0ff92c 5210 return hpsa_cmd_free_and_done(h, c, cmd);
592a0ad5
WS		 5211 }
5212 /* else, fall thru and resubmit down CISS path */
5213 }
5214 }
360c73bd 5215 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 5216 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
5217 /*
5218 * If we get here, it means dma mapping failed. Try
5219 * again via scsi mid layer, which will then get
5220 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 5221 *
5222 * hpsa_ciss_submit will have already freed c
5223 * if it encountered a dma mapping failure.
080ef1cc
DB		 5224 */
5225 cmd->result = DID_IMM_RETRY << 16;
5226 cmd->scsi_done(cmd);
5227 }
5228}
5229
574f05d3
SC		 5230/* Running in struct Scsi_Host->host_lock less mode */
5231static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
5232{
5233 struct ctlr_info *h;
5234 struct hpsa_scsi_dev_t *dev;
5235 unsigned char scsi3addr[8];
5236 struct CommandList *c;
5237 int rc = 0;
5238
5239 /* Get the ptr to our adapter structure out of cmd->host. */
5240 h = sdev_to_hba(cmd->device);
73153fe5
WS		 5241
5242 BUG_ON(cmd->request->tag < 0);
5243
574f05d3
SC		 5244 dev = cmd->device->hostdata;
5245 if (!dev) {
5246 cmd->result = DID_NO_CONNECT << 16;
5247 cmd->scsi_done(cmd);
5248 return 0;
5249 }
574f05d3 5250
73153fe5 5251 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
bf43caf3 5252
407863cb 5253 if (unlikely(lockup_detected(h))) {
25163bd5 5254 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 5255 cmd->scsi_done(cmd);
5256 return 0;
5257 }
73153fe5 5258 c = cmd_tagged_alloc(h, cmd);
574f05d3 5259
407863cb
SC		 5260 /*
5261 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 5262 * Retries always go down the normal I/O path.
5263 */
5264 if (likely(cmd->retries == 0 &&
5265 cmd->request->cmd_type == REQ_TYPE_FS &&
5266 h->acciopath_status)) {
592a0ad5
WS		 5267 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
5268 if (rc == 0)
5269 return 0;
5270 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
73153fe5 5271 hpsa_cmd_resolve_and_free(h, c);
592a0ad5 5272 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 5273 }
5274 }
5275 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
5276}
5277
8ebc9248 5278static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 5279{
5280 unsigned long flags;
5281
8ebc9248
WS		 5282 spin_lock_irqsave(&h->scan_lock, flags);
5283 h->scan_finished = 1;
5284 wake_up_all(&h->scan_wait_queue);
5285 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 5286}
5287
a08a8471
SC		 5288static void hpsa_scan_start(struct Scsi_Host *sh)
5289{
5290 struct ctlr_info *h = shost_to_hba(sh);
5291 unsigned long flags;
5292
8ebc9248
WS		 5293 /*
5294 * Don't let rescans be initiated on a controller known to be locked
5295 * up. If the controller locks up *during* a rescan, that thread is
5296 * probably hosed, but at least we can prevent new rescan threads from
5297 * piling up on a locked up controller.
5298 */
5299 if (unlikely(lockup_detected(h)))
5300 return hpsa_scan_complete(h);
5f389360 5301
a08a8471
SC		 5302 /* wait until any scan already in progress is finished. */
5303 while (1) {
5304 spin_lock_irqsave(&h->scan_lock, flags);
5305 if (h->scan_finished)
5306 break;
5307 spin_unlock_irqrestore(&h->scan_lock, flags);
5308 wait_event(h->scan_wait_queue, h->scan_finished);
5309 /* Note: We don't need to worry about a race between this
5310 * thread and driver unload because the midlayer will
5311 * have incremented the reference count, so unload won't
5312 * happen if we're in here.
5313 */
5314 }
5315 h->scan_finished = 0; /* mark scan as in progress */
5316 spin_unlock_irqrestore(&h->scan_lock, flags);
5317
8ebc9248
WS		 5318 if (unlikely(lockup_detected(h)))
5319 return hpsa_scan_complete(h);
5f389360 5320
8aa60681 5321 hpsa_update_scsi_devices(h);
a08a8471 5322
8ebc9248 5323 hpsa_scan_complete(h);
a08a8471
SC		 5324}
5325
7c0a0229
DB		 5326static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
5327{
03383736
DB		 5328 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
5329
5330 if (!logical_drive)
5331 return -ENODEV;
7c0a0229
DB		 5332
5333 if (qdepth < 1)
5334 qdepth = 1;
03383736
DB		 5335 else if (qdepth > logical_drive->queue_depth)
5336 qdepth = logical_drive->queue_depth;
5337
5338 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 5339}
5340
a08a8471
SC		 5341static int hpsa_scan_finished(struct Scsi_Host *sh,
5342 unsigned long elapsed_time)
5343{
5344 struct ctlr_info *h = shost_to_hba(sh);
5345 unsigned long flags;
5346 int finished;
5347
5348 spin_lock_irqsave(&h->scan_lock, flags);
5349 finished = h->scan_finished;
5350 spin_unlock_irqrestore(&h->scan_lock, flags);
5351 return finished;
5352}
5353
2946e82b 5354static int hpsa_scsi_host_alloc(struct ctlr_info *h)
edd16368 5355{
b705690d 5356 struct Scsi_Host *sh;
edd16368 5357
b705690d 5358 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2946e82b
RE		 5359 if (sh == NULL) {
5360 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
5361 return -ENOMEM;
5362 }
b705690d
SC		 5363
5364 sh->io_port = 0;
5365 sh->n_io_port = 0;
5366 sh->this_id = -1;
5367 sh->max_channel = 3;
5368 sh->max_cmd_len = MAX_COMMAND_SIZE;
5369 sh->max_lun = HPSA_MAX_LUN;
5370 sh->max_id = HPSA_MAX_LUN;
41ce4c35 5371 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 5372 sh->cmd_per_lun = sh->can_queue;
b705690d 5373 sh->sg_tablesize = h->maxsgentries;
d04e62b9 5374 sh->transportt = hpsa_sas_transport_template;
b705690d
SC		 5375 sh->hostdata[0] = (unsigned long) h;
5376 sh->irq = h->intr[h->intr_mode];
5377 sh->unique_id = sh->irq;
64d513ac 5378
2946e82b 5379 h->scsi_host = sh;
b705690d 5380 return 0;
2946e82b 5381}
b705690d 5382
2946e82b
RE		 5383static int hpsa_scsi_add_host(struct ctlr_info *h)
5384{
5385 int rv;
5386
5387 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
5388 if (rv) {
5389 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
5390 return rv;
5391 }
5392 scsi_scan_host(h->scsi_host);
5393 return 0;
edd16368
SC		 5394}
5395
73153fe5
WS		 5396/*
5397 * The block layer has already gone to the trouble of picking out a unique,
5398 * small-integer tag for this request. We use an offset from that value as
5399 * an index to select our command block. (The offset allows us to reserve the
5400 * low-numbered entries for our own uses.)
5401 */
5402static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
5403{
5404 int idx = scmd->request->tag;
5405
5406 if (idx < 0)
5407 return idx;
5408
5409 /* Offset to leave space for internal cmds. */
5410 return idx += HPSA_NRESERVED_CMDS;
5411}
5412
b69324ff
WS		 5413/*
5414 * Send a TEST_UNIT_READY command to the specified LUN using the specified
5415 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5416 */
5417static int hpsa_send_test_unit_ready(struct ctlr_info *h,
5418 struct CommandList *c, unsigned char lunaddr[],
5419 int reply_queue)
5420{
5421 int rc;
5422
5423 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
5424 (void) fill_cmd(c, TEST_UNIT_READY, h,
5425 NULL, 0, 0, lunaddr, TYPE_CMD);
5426 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5427 if (rc)
5428 return rc;
5429 /* no unmap needed here because no data xfer. */
5430
5431 /* Check if the unit is already ready. */
5432 if (c->err_info->CommandStatus == CMD_SUCCESS)
5433 return 0;
5434
5435 /*
5436 * The first command sent after reset will receive "unit attention" to
5437 * indicate that the LUN has been reset...this is actually what we're
5438 * looking for (but, success is good too).
5439 */
5440 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5441 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5442 (c->err_info->SenseInfo[2] == NO_SENSE ||
5443 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5444 return 0;
5445
5446 return 1;
5447}
5448
5449/*
5450 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5451 * returns zero when the unit is ready, and non-zero when giving up.
5452 */
5453static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5454 struct CommandList *c,
5455 unsigned char lunaddr[], int reply_queue)
edd16368 5456{
8919358e 5457 int rc;
edd16368
SC		 5458 int count = 0;
5459 int waittime = 1; /* seconds */
edd16368
SC		 5460
5461 /* Send test unit ready until device ready, or give up. */
b69324ff 5462 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
edd16368 5463
b69324ff
WS		 5464 /*
5465 * Wait for a bit. do this first, because if we send
edd16368
SC		 5466 * the TUR right away, the reset will just abort it.
5467 */
5468 msleep(1000 * waittime);
b69324ff
WS		 5469
5470 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5471 if (!rc)
5472 break;
edd16368
SC		 5473
5474 /* Increase wait time with each try, up to a point. */
5475 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
b69324ff 5476 waittime *= 2;
edd16368 5477
b69324ff
WS		 5478 dev_warn(&h->pdev->dev,
5479 "waiting %d secs for device to become ready.\n",
5480 waittime);
5481 }
edd16368 5482
b69324ff
WS		 5483 return rc;
5484}
edd16368 5485
b69324ff
WS		 5486static int wait_for_device_to_become_ready(struct ctlr_info *h,
5487 unsigned char lunaddr[],
5488 int reply_queue)
5489{
5490 int first_queue;
5491 int last_queue;
5492 int rq;
5493 int rc = 0;
5494 struct CommandList *c;
5495
5496 c = cmd_alloc(h);
5497
5498 /*
5499 * If no specific reply queue was requested, then send the TUR
5500 * repeatedly, requesting a reply on each reply queue; otherwise execute
5501 * the loop exactly once using only the specified queue.
5502 */
5503 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5504 first_queue = 0;
5505 last_queue = h->nreply_queues - 1;
5506 } else {
5507 first_queue = reply_queue;
5508 last_queue = reply_queue;
5509 }
5510
5511 for (rq = first_queue; rq <= last_queue; rq++) {
5512 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5513 if (rc)
edd16368 5514 break;
edd16368
SC		 5515 }
5516
5517 if (rc)
5518 dev_warn(&h->pdev->dev, "giving up on device.\n");
5519 else
5520 dev_warn(&h->pdev->dev, "device is ready.\n");
5521
45fcb86e 5522 cmd_free(h, c);
edd16368
SC		 5523 return rc;
5524}
5525
5526/* Need at least one of these error handlers to keep ../scsi/hosts.c from
5527 * complaining. Doing a host- or bus-reset can't do anything good here.
5528 */
5529static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5530{
5531 int rc;
5532 struct ctlr_info *h;
5533 struct hpsa_scsi_dev_t *dev;
0b9b7b6e 5534 u8 reset_type;
2dc127bb 5535 char msg[48];
edd16368
SC		 5536
5537 /* find the controller to which the command to be aborted was sent */
5538 h = sdev_to_hba(scsicmd->device);
5539 if (h == NULL) /* paranoia */
5540 return FAILED;
e345893b
DB		 5541
5542 if (lockup_detected(h))
5543 return FAILED;
5544
edd16368
SC		 5545 dev = scsicmd->device->hostdata;
5546 if (!dev) {
d604f533 5547 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
edd16368
SC		 5548 return FAILED;
5549 }
25163bd5
WS		 5550
5551 /* if controller locked up, we can guarantee command won't complete */
5552 if (lockup_detected(h)) {
2dc127bb
DC		 5553 snprintf(msg, sizeof(msg),
5554 "cmd %d RESET FAILED, lockup detected",
5555 hpsa_get_cmd_index(scsicmd));
73153fe5 5556 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5557 return FAILED;
5558 }
5559
5560 /* this reset request might be the result of a lockup; check */
5561 if (detect_controller_lockup(h)) {
2dc127bb
DC		 5562 snprintf(msg, sizeof(msg),
5563 "cmd %d RESET FAILED, new lockup detected",
5564 hpsa_get_cmd_index(scsicmd));
73153fe5 5565 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5566 return FAILED;
5567 }
5568
d604f533
WS		 5569 /* Do not attempt on controller */
5570 if (is_hba_lunid(dev->scsi3addr))
5571 return SUCCESS;
5572
0b9b7b6e
ST		 5573 if (is_logical_dev_addr_mode(dev->scsi3addr))
5574 reset_type = HPSA_DEVICE_RESET_MSG;
5575 else
5576 reset_type = HPSA_PHYS_TARGET_RESET;
5577
5578 sprintf(msg, "resetting %s",
5579 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ");
5580 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5 5581
da03ded0 5582 h->reset_in_progress = 1;
25163bd5 5583
edd16368 5584 /* send a reset to the SCSI LUN which the command was sent to */
0b9b7b6e 5585 rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type,
d604f533 5586 DEFAULT_REPLY_QUEUE);
0b9b7b6e
ST		 5587 sprintf(msg, "reset %s %s",
5588 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ",
5589 rc == 0 ? "completed successfully" : "failed");
d604f533 5590 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
da03ded0 5591 h->reset_in_progress = 0;
d604f533 5592 return rc == 0 ? SUCCESS : FAILED;
edd16368
SC		 5593}
5594
6cba3f19
SC		 5595static void swizzle_abort_tag(u8 *tag)
5596{
5597 u8 original_tag[8];
5598
5599 memcpy(original_tag, tag, 8);
5600 tag[0] = original_tag[3];
5601 tag[1] = original_tag[2];
5602 tag[2] = original_tag[1];
5603 tag[3] = original_tag[0];
5604 tag[4] = original_tag[7];
5605 tag[5] = original_tag[6];
5606 tag[6] = original_tag[5];
5607 tag[7] = original_tag[4];
5608}
5609
17eb87d2 5610static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 5611 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 5612{
2b08b3e9 5613 u64 tag;
17eb87d2
ST		 5614 if (c->cmd_type == CMD_IOACCEL1) {
5615 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5616 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 5617 tag = le64_to_cpu(cm1->tag);
5618 *tagupper = cpu_to_le32(tag >> 32);
5619 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 5620 return;
5621 }
5622 if (c->cmd_type == CMD_IOACCEL2) {
5623 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5624 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 5625 /* upper tag not used in ioaccel2 mode */
5626 memset(tagupper, 0, sizeof(*tagupper));
5627 *taglower = cm2->Tag;
54b6e9e9 5628 return;
17eb87d2 5629 }
2b08b3e9
DB		 5630 tag = le64_to_cpu(c->Header.tag);
5631 *tagupper = cpu_to_le32(tag >> 32);
5632 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 5633}
5634
75167d2c 5635static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 5636 struct CommandList *abort, int reply_queue)
75167d2c
SC		 5637{
5638 int rc = IO_OK;
5639 struct CommandList *c;
5640 struct ErrorInfo *ei;
2b08b3e9 5641 __le32 tagupper, taglower;
75167d2c 5642
45fcb86e 5643 c = cmd_alloc(h);
75167d2c 5644
a2dac136 5645 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 5646 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 5647 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 5648 if (h->needs_abort_tags_swizzled)
6cba3f19 5649 swizzle_abort_tag(&c->Request.CDB[4]);
25163bd5 5650 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
17eb87d2 5651 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5652 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 5653 __func__, tagupper, taglower);
75167d2c
SC		 5654 /* no unmap needed here because no data xfer. */
5655
5656 ei = c->err_info;
5657 switch (ei->CommandStatus) {
5658 case CMD_SUCCESS:
5659 break;
9437ac43
SC		 5660 case CMD_TMF_STATUS:
5661 rc = hpsa_evaluate_tmf_status(h, c);
5662 break;
75167d2c
SC		 5663 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5664 rc = -1;
5665 break;
5666 default:
5667 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 5668 __func__, tagupper, taglower);
d1e8beac 5669 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 5670 rc = -1;
5671 break;
5672 }
45fcb86e 5673 cmd_free(h, c);
dd0e19f3
ST		 5674 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5675 __func__, tagupper, taglower);
75167d2c
SC		 5676 return rc;
5677}
5678
8be986cc
SC		 5679static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5680 struct CommandList *command_to_abort, int reply_queue)
5681{
5682 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5683 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5684 struct io_accel2_cmd *c2a =
5685 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
a58e7e53 5686 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
8be986cc
SC		 5687 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5688
5689 /*
5690 * We're overlaying struct hpsa_tmf_struct on top of something which
5691 * was allocated as a struct io_accel2_cmd, so we better be sure it
5692 * actually fits, and doesn't overrun the error info space.
5693 */
5694 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5695 sizeof(struct io_accel2_cmd));
5696 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5697 offsetof(struct hpsa_tmf_struct, error_len) +
5698 sizeof(ac->error_len));
5699
5700 c->cmd_type = IOACCEL2_TMF;
a58e7e53
WS		 5701 c->scsi_cmd = SCSI_CMD_BUSY;
5702
8be986cc
SC		 5703 /* Adjust the DMA address to point to the accelerated command buffer */
5704 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5705 (c->cmdindex * sizeof(struct io_accel2_cmd));
5706 BUG_ON(c->busaddr & 0x0000007F);
5707
5708 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5709 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5710 ac->reply_queue = reply_queue;
5711 ac->tmf = IOACCEL2_TMF_ABORT;
5712 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5713 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5714 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5715 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5716 ac->error_ptr = cpu_to_le64(c->busaddr +
5717 offsetof(struct io_accel2_cmd, error_data));
5718 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5719}
5720
54b6e9e9
ST		 5721/* ioaccel2 path firmware cannot handle abort task requests.
5722 * Change abort requests to physical target reset, and send to the
5723 * address of the physical disk used for the ioaccel 2 command.
5724 * Return 0 on success (IO_OK)
5725 * -1 on failure
5726 */
5727
5728static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 5729 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 5730{
5731 int rc = IO_OK;
5732 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5733 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5734 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5735 unsigned char *psa = &phys_scsi3addr[0];
5736
5737 /* Get a pointer to the hpsa logical device. */
7fa3030c 5738 scmd = abort->scsi_cmd;
54b6e9e9
ST		 5739 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5740 if (dev == NULL) {
5741 dev_warn(&h->pdev->dev,
5742 "Cannot abort: no device pointer for command.\n");
5743 return -1; /* not abortable */
5744 }
5745
2ba8bfc8
SC		 5746 if (h->raid_offload_debug > 0)
5747 dev_info(&h->pdev->dev,
0d96ef5f 5748 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 5749 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 5750 "Reset as abort",
2ba8bfc8
SC		 5751 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5752 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5753
54b6e9e9
ST		 5754 if (!dev->offload_enabled) {
5755 dev_warn(&h->pdev->dev,
5756 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5757 return -1; /* not abortable */
5758 }
5759
5760 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5761 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5762 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5763 return -1; /* not abortable */
5764 }
5765
5766 /* send the reset */
2ba8bfc8
SC		 5767 if (h->raid_offload_debug > 0)
5768 dev_info(&h->pdev->dev,
5769 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5770 psa[0], psa[1], psa[2], psa[3],
5771 psa[4], psa[5], psa[6], psa[7]);
d604f533 5772 rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 5773 if (rc != 0) {
5774 dev_warn(&h->pdev->dev,
5775 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5776 psa[0], psa[1], psa[2], psa[3],
5777 psa[4], psa[5], psa[6], psa[7]);
5778 return rc; /* failed to reset */
5779 }
5780
5781 /* wait for device to recover */
b69324ff 5782 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
54b6e9e9
ST		 5783 dev_warn(&h->pdev->dev,
5784 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5785 psa[0], psa[1], psa[2], psa[3],
5786 psa[4], psa[5], psa[6], psa[7]);
5787 return -1; /* failed to recover */
5788 }
5789
5790 /* device recovered */
5791 dev_info(&h->pdev->dev,
5792 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5793 psa[0], psa[1], psa[2], psa[3],
5794 psa[4], psa[5], psa[6], psa[7]);
5795
5796 return rc; /* success */
5797}
5798
8be986cc
SC		 5799static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
5800 struct CommandList *abort, int reply_queue)
5801{
5802 int rc = IO_OK;
5803 struct CommandList *c;
5804 __le32 taglower, tagupper;
5805 struct hpsa_scsi_dev_t *dev;
5806 struct io_accel2_cmd *c2;
5807
5808 dev = abort->scsi_cmd->device->hostdata;
5809 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
5810 return -1;
5811
5812 c = cmd_alloc(h);
5813 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
5814 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5815 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5816 hpsa_get_tag(h, abort, &taglower, &tagupper);
5817 dev_dbg(&h->pdev->dev,
5818 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
5819 __func__, tagupper, taglower);
5820 /* no unmap needed here because no data xfer. */
5821
5822 dev_dbg(&h->pdev->dev,
5823 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
5824 __func__, tagupper, taglower, c2->error_data.serv_response);
5825 switch (c2->error_data.serv_response) {
5826 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
5827 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
5828 rc = 0;
5829 break;
5830 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
5831 case IOACCEL2_SERV_RESPONSE_FAILURE:
5832 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
5833 rc = -1;
5834 break;
5835 default:
5836 dev_warn(&h->pdev->dev,
5837 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
5838 __func__, tagupper, taglower,
5839 c2->error_data.serv_response);
5840 rc = -1;
5841 }
5842 cmd_free(h, c);
5843 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
5844 tagupper, taglower);
5845 return rc;
5846}
5847
6cba3f19 5848static int hpsa_send_abort_both_ways(struct ctlr_info *h,
25163bd5 5849 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
6cba3f19 5850{
8be986cc
SC		 5851 /*
5852 * ioccelerator mode 2 commands should be aborted via the
54b6e9e9 5853 * accelerated path, since RAID path is unaware of these commands,
8be986cc
SC		 5854 * but not all underlying firmware can handle abort TMF.
5855 * Change abort to physical device reset when abort TMF is unsupported.
54b6e9e9 5856 */
8be986cc
SC		 5857 if (abort->cmd_type == CMD_IOACCEL2) {
5858 if (HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)
5859 return hpsa_send_abort_ioaccel2(h, abort,
5860 reply_queue);
5861 else
5862 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
25163bd5 5863 abort, reply_queue);
8be986cc 5864 }
9b5c48c2 5865 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
25163bd5 5866}
54b6e9e9 5867
25163bd5
WS		 5868/* Find out which reply queue a command was meant to return on */
5869static int hpsa_extract_reply_queue(struct ctlr_info *h,
5870 struct CommandList *c)
5871{
5872 if (c->cmd_type == CMD_IOACCEL2)
5873 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5874 return c->Header.ReplyQueue;
6cba3f19
SC		 5875}
5876
9b5c48c2
SC		 5877/*
5878 * Limit concurrency of abort commands to prevent
5879 * over-subscription of commands
5880 */
5881static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5882{
5883#define ABORT_CMD_WAIT_MSECS 5000
5884 return !wait_event_timeout(h->abort_cmd_wait_queue,
5885 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5886 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5887}
5888
75167d2c
SC		 5889/* Send an abort for the specified command.
5890 * If the device and controller support it,
5891 * send a task abort request.
5892 */
5893static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5894{
5895
a58e7e53 5896 int rc;
75167d2c
SC		 5897 struct ctlr_info *h;
5898 struct hpsa_scsi_dev_t *dev;
5899 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 5900 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
5901 char msg[256]; /* For debug messaging. */
5902 int ml = 0;
2b08b3e9 5903 __le32 tagupper, taglower;
25163bd5
WS		 5904 int refcount, reply_queue;
5905
5906 if (sc == NULL)
5907 return FAILED;
75167d2c 5908
9b5c48c2
SC		 5909 if (sc->device == NULL)
5910 return FAILED;
5911
75167d2c
SC		 5912 /* Find the controller of the command to be aborted */
5913 h = sdev_to_hba(sc->device);
9b5c48c2 5914 if (h == NULL)
75167d2c
SC		 5915 return FAILED;
5916
25163bd5
WS		 5917 /* Find the device of the command to be aborted */
5918 dev = sc->device->hostdata;
5919 if (!dev) {
5920 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
5921 msg);
e345893b 5922 return FAILED;
25163bd5
WS		 5923 }
5924
5925 /* If controller locked up, we can guarantee command won't complete */
5926 if (lockup_detected(h)) {
5927 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5928 "ABORT FAILED, lockup detected");
5929 return FAILED;
5930 }
5931
5932 /* This is a good time to check if controller lockup has occurred */
5933 if (detect_controller_lockup(h)) {
5934 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5935 "ABORT FAILED, new lockup detected");
5936 return FAILED;
5937 }
e345893b 5938
75167d2c
SC		 5939 /* Check that controller supports some kind of task abort */
5940 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5941 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5942 return FAILED;
5943
5944 memset(msg, 0, sizeof(msg));
4b761557 5945 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
75167d2c 5946 h->scsi_host->host_no, sc->device->channel,
0d96ef5f 5947 sc->device->id, sc->device->lun,
4b761557 5948 "Aborting command", sc);
75167d2c 5949
75167d2c
SC		 5950 /* Get SCSI command to be aborted */
5951 abort = (struct CommandList *) sc->host_scribble;
5952 if (abort == NULL) {
281a7fd0
WS		 5953 /* This can happen if the command already completed. */
5954 return SUCCESS;
5955 }
5956 refcount = atomic_inc_return(&abort->refcount);
5957 if (refcount == 1) { /* Command is done already. */
5958 cmd_free(h, abort);
5959 return SUCCESS;
75167d2c 5960 }
9b5c48c2
SC		 5961
5962 /* Don't bother trying the abort if we know it won't work. */
5963 if (abort->cmd_type != CMD_IOACCEL2 &&
5964 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5965 cmd_free(h, abort);
5966 return FAILED;
5967 }
5968
a58e7e53
WS		 5969 /*
5970 * Check that we're aborting the right command.
5971 * It's possible the CommandList already completed and got re-used.
5972 */
5973 if (abort->scsi_cmd != sc) {
5974 cmd_free(h, abort);
5975 return SUCCESS;
5976 }
5977
5978 abort->abort_pending = true;
17eb87d2 5979 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5980 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 5981 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 5982 as = abort->scsi_cmd;
75167d2c 5983 if (as != NULL)
4b761557
RE		 5984 ml += sprintf(msg+ml,
5985 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
5986 as->cmd_len, as->cmnd[0], as->cmnd[1],
5987 as->serial_number);
5988 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
0d96ef5f 5989 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
4b761557 5990
75167d2c
SC		 5991 /*
5992 * Command is in flight, or possibly already completed
5993 * by the firmware (but not to the scsi mid layer) but we can't
5994 * distinguish which. Send the abort down.
5995 */
9b5c48c2
SC		 5996 if (wait_for_available_abort_cmd(h)) {
5997 dev_warn(&h->pdev->dev,
4b761557
RE		 5998 "%s FAILED, timeout waiting for an abort command to become available.\n",
5999 msg);
9b5c48c2
SC		 6000 cmd_free(h, abort);
6001 return FAILED;
6002 }
25163bd5 6003 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
9b5c48c2
SC		 6004 atomic_inc(&h->abort_cmds_available);
6005 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 6006 if (rc != 0) {
4b761557 6007 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
0d96ef5f 6008 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4b761557 6009 "FAILED to abort command");
281a7fd0 6010 cmd_free(h, abort);
75167d2c
SC		 6011 return FAILED;
6012 }
4b761557 6013 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
d604f533 6014 wait_event(h->event_sync_wait_queue,
a58e7e53 6015 abort->scsi_cmd != sc || lockup_detected(h));
281a7fd0 6016 cmd_free(h, abort);
a58e7e53 6017 return !lockup_detected(h) ? SUCCESS : FAILED;
75167d2c
SC		 6018}
6019
73153fe5
WS		 6020/*
6021 * For operations with an associated SCSI command, a command block is allocated
6022 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
6023 * block request tag as an index into a table of entries. cmd_tagged_free() is
6024 * the complement, although cmd_free() may be called instead.
6025 */
6026static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
6027 struct scsi_cmnd *scmd)
6028{
6029 int idx = hpsa_get_cmd_index(scmd);
6030 struct CommandList *c = h->cmd_pool + idx;
6031
6032 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
6033 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
6034 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
6035 /* The index value comes from the block layer, so if it's out of
6036 * bounds, it's probably not our bug.
6037 */
6038 BUG();
6039 }
6040
6041 atomic_inc(&c->refcount);
6042 if (unlikely(!hpsa_is_cmd_idle(c))) {
6043 /*
6044 * We expect that the SCSI layer will hand us a unique tag
6045 * value. Thus, there should never be a collision here between
6046 * two requests...because if the selected command isn't idle
6047 * then someone is going to be very disappointed.
6048 */
6049 dev_err(&h->pdev->dev,
6050 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
6051 idx);
6052 if (c->scsi_cmd != NULL)
6053 scsi_print_command(c->scsi_cmd);
6054 scsi_print_command(scmd);
6055 }
6056
6057 hpsa_cmd_partial_init(h, idx, c);
6058 return c;
6059}
6060
6061static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
6062{
6063 /*
6064 * Release our reference to the block. We don't need to do anything
6065 * else to free it, because it is accessed by index. (There's no point
6066 * in checking the result of the decrement, since we cannot guarantee
6067 * that there isn't a concurrent abort which is also accessing it.)
6068 */
6069 (void)atomic_dec(&c->refcount);
6070}
6071
edd16368
SC		 6072/*
6073 * For operations that cannot sleep, a command block is allocated at init,
6074 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
6075 * which ones are free or in use. Lock must be held when calling this.
6076 * cmd_free() is the complement.
bf43caf3
RE		 6077 * This function never gives up and returns NULL. If it hangs,
6078 * another thread must call cmd_free() to free some tags.
edd16368 6079 */
281a7fd0 6080
edd16368
SC		 6081static struct CommandList *cmd_alloc(struct ctlr_info *h)
6082{
6083 struct CommandList *c;
360c73bd 6084 int refcount, i;
73153fe5 6085 int offset = 0;
4c413128 6086
33811026
RE		 6087 /*
6088 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 6089 * multiple threads could get in here, and one thread could
6090 * be scanning through the list of bits looking for a free
6091 * one, but the free ones are always behind him, and other
6092 * threads sneak in behind him and eat them before he can
6093 * get to them, so that while there is always a free one, a
6094 * very unlucky thread might be starved anyway, never able to
6095 * beat the other threads. In reality, this happens so
6096 * infrequently as to be indistinguishable from never.
73153fe5
WS		 6097 *
6098 * Note that we start allocating commands before the SCSI host structure
6099 * is initialized. Since the search starts at bit zero, this
6100 * all works, since we have at least one command structure available;
6101 * however, it means that the structures with the low indexes have to be
6102 * reserved for driver-initiated requests, while requests from the block
6103 * layer will use the higher indexes.
4c413128 6104 */
edd16368 6105
281a7fd0 6106 for (;;) {
73153fe5
WS		 6107 i = find_next_zero_bit(h->cmd_pool_bits,
6108 HPSA_NRESERVED_CMDS,
6109 offset);
6110 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
281a7fd0
WS		 6111 offset = 0;
6112 continue;
6113 }
6114 c = h->cmd_pool + i;
6115 refcount = atomic_inc_return(&c->refcount);
6116 if (unlikely(refcount > 1)) {
6117 cmd_free(h, c); /* already in use */
73153fe5 6118 offset = (i + 1) % HPSA_NRESERVED_CMDS;
281a7fd0
WS		 6119 continue;
6120 }
6121 set_bit(i & (BITS_PER_LONG - 1),
6122 h->cmd_pool_bits + (i / BITS_PER_LONG));
6123 break; /* it's ours now. */
6124 }
360c73bd 6125 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 6126 return c;
6127}
6128
73153fe5
WS		 6129/*
6130 * This is the complementary operation to cmd_alloc(). Note, however, in some
6131 * corner cases it may also be used to free blocks allocated by
6132 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
6133 * the clear-bit is harmless.
6134 */
edd16368
SC		 6135static void cmd_free(struct ctlr_info *h, struct CommandList *c)
6136{
281a7fd0
WS		 6137 if (atomic_dec_and_test(&c->refcount)) {
6138 int i;
edd16368 6139
281a7fd0
WS		 6140 i = c - h->cmd_pool;
6141 clear_bit(i & (BITS_PER_LONG - 1),
6142 h->cmd_pool_bits + (i / BITS_PER_LONG));
6143 }
edd16368
SC		 6144}
6145
edd16368
SC		 6146#ifdef CONFIG_COMPAT
6147
42a91641
DB		 6148static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
6149 void __user *arg)
edd16368
SC		 6150{
6151 IOCTL32_Command_struct __user *arg32 =
6152 (IOCTL32_Command_struct __user *) arg;
6153 IOCTL_Command_struct arg64;
6154 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
6155 int err;
6156 u32 cp;
6157
938abd84 6158 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 6159 err = 0;
6160 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
6161 sizeof(arg64.LUN_info));
6162 err |= copy_from_user(&arg64.Request, &arg32->Request,
6163 sizeof(arg64.Request));
6164 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
6165 sizeof(arg64.error_info));
6166 err |= get_user(arg64.buf_size, &arg32->buf_size);
6167 err |= get_user(cp, &arg32->buf);
6168 arg64.buf = compat_ptr(cp);
6169 err |= copy_to_user(p, &arg64, sizeof(arg64));
6170
6171 if (err)
6172 return -EFAULT;
6173
42a91641 6174 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 6175 if (err)
6176 return err;
6177 err |= copy_in_user(&arg32->error_info, &p->error_info,
6178 sizeof(arg32->error_info));
6179 if (err)
6180 return -EFAULT;
6181 return err;
6182}
6183
6184static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 6185 int cmd, void __user *arg)
edd16368
SC		 6186{
6187 BIG_IOCTL32_Command_struct __user *arg32 =
6188 (BIG_IOCTL32_Command_struct __user *) arg;
6189 BIG_IOCTL_Command_struct arg64;
6190 BIG_IOCTL_Command_struct __user *p =
6191 compat_alloc_user_space(sizeof(arg64));
6192 int err;
6193 u32 cp;
6194
938abd84 6195 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 6196 err = 0;
6197 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
6198 sizeof(arg64.LUN_info));
6199 err |= copy_from_user(&arg64.Request, &arg32->Request,
6200 sizeof(arg64.Request));
6201 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
6202 sizeof(arg64.error_info));
6203 err |= get_user(arg64.buf_size, &arg32->buf_size);
6204 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
6205 err |= get_user(cp, &arg32->buf);
6206 arg64.buf = compat_ptr(cp);
6207 err |= copy_to_user(p, &arg64, sizeof(arg64));
6208
6209 if (err)
6210 return -EFAULT;
6211
42a91641 6212 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 6213 if (err)
6214 return err;
6215 err |= copy_in_user(&arg32->error_info, &p->error_info,
6216 sizeof(arg32->error_info));
6217 if (err)
6218 return -EFAULT;
6219 return err;
6220}
71fe75a7 6221
42a91641 6222static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 6223{
6224 switch (cmd) {
6225 case CCISS_GETPCIINFO:
6226 case CCISS_GETINTINFO:
6227 case CCISS_SETINTINFO:
6228 case CCISS_GETNODENAME:
6229 case CCISS_SETNODENAME:
6230 case CCISS_GETHEARTBEAT:
6231 case CCISS_GETBUSTYPES:
6232 case CCISS_GETFIRMVER:
6233 case CCISS_GETDRIVVER:
6234 case CCISS_REVALIDVOLS:
6235 case CCISS_DEREGDISK:
6236 case CCISS_REGNEWDISK:
6237 case CCISS_REGNEWD:
6238 case CCISS_RESCANDISK:
6239 case CCISS_GETLUNINFO:
6240 return hpsa_ioctl(dev, cmd, arg);
6241
6242 case CCISS_PASSTHRU32:
6243 return hpsa_ioctl32_passthru(dev, cmd, arg);
6244 case CCISS_BIG_PASSTHRU32:
6245 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
6246
6247 default:
6248 return -ENOIOCTLCMD;
6249 }
6250}
edd16368
SC		 6251#endif
6252
6253static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
6254{
6255 struct hpsa_pci_info pciinfo;
6256
6257 if (!argp)
6258 return -EINVAL;
6259 pciinfo.domain = pci_domain_nr(h->pdev->bus);
6260 pciinfo.bus = h->pdev->bus->number;
6261 pciinfo.dev_fn = h->pdev->devfn;
6262 pciinfo.board_id = h->board_id;
6263 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
6264 return -EFAULT;
6265 return 0;
6266}
6267
6268static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
6269{
6270 DriverVer_type DriverVer;
6271 unsigned char vmaj, vmin, vsubmin;
6272 int rc;
6273
6274 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
6275 &vmaj, &vmin, &vsubmin);
6276 if (rc != 3) {
6277 dev_info(&h->pdev->dev, "driver version string '%s' "
6278 "unrecognized.", HPSA_DRIVER_VERSION);
6279 vmaj = 0;
6280 vmin = 0;
6281 vsubmin = 0;
6282 }
6283 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
6284 if (!argp)
6285 return -EINVAL;
6286 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
6287 return -EFAULT;
6288 return 0;
6289}
6290
6291static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6292{
6293 IOCTL_Command_struct iocommand;
6294 struct CommandList *c;
6295 char *buff = NULL;
50a0decf 6296 u64 temp64;
c1f63c8f 6297 int rc = 0;
edd16368
SC		 6298
6299 if (!argp)
6300 return -EINVAL;
6301 if (!capable(CAP_SYS_RAWIO))
6302 return -EPERM;
6303 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
6304 return -EFAULT;
6305 if ((iocommand.buf_size < 1) &&
6306 (iocommand.Request.Type.Direction != XFER_NONE)) {
6307 return -EINVAL;
6308 }
6309 if (iocommand.buf_size > 0) {
6310 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
6311 if (buff == NULL)
2dd02d74 6312 return -ENOMEM;
9233fb10 6313 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 6314 /* Copy the data into the buffer we created */
6315 if (copy_from_user(buff, iocommand.buf,
6316 iocommand.buf_size)) {
c1f63c8f
SC		 6317 rc = -EFAULT;
6318 goto out_kfree;
b03a7771
SC		 6319 }
6320 } else {
6321 memset(buff, 0, iocommand.buf_size);
edd16368 6322 }
b03a7771 6323 }
45fcb86e 6324 c = cmd_alloc(h);
bf43caf3 6325
edd16368
SC		 6326 /* Fill in the command type */
6327 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6328 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6329 /* Fill in Command Header */
6330 c->Header.ReplyQueue = 0; /* unused in simple mode */
6331 if (iocommand.buf_size > 0) { /* buffer to fill */
6332 c->Header.SGList = 1;
50a0decf 6333 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6334 } else { /* no buffers to fill */
6335 c->Header.SGList = 0;
50a0decf 6336 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 6337 }
6338 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6339
6340 /* Fill in Request block */
6341 memcpy(&c->Request, &iocommand.Request,
6342 sizeof(c->Request));
6343
6344 /* Fill in the scatter gather information */
6345 if (iocommand.buf_size > 0) {
50a0decf 6346 temp64 = pci_map_single(h->pdev, buff,
edd16368 6347 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6348 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
6349 c->SG[0].Addr = cpu_to_le64(0);
6350 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 6351 rc = -ENOMEM;
6352 goto out;
6353 }
50a0decf
SC		 6354 c->SG[0].Addr = cpu_to_le64(temp64);
6355 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
6356 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 6357 }
25163bd5 6358 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
c2dd32e0
SC		 6359 if (iocommand.buf_size > 0)
6360 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 6361 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6362 if (rc) {
6363 rc = -EIO;
6364 goto out;
6365 }
edd16368
SC		 6366
6367 /* Copy the error information out */
6368 memcpy(&iocommand.error_info, c->err_info,
6369 sizeof(iocommand.error_info));
6370 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 6371 rc = -EFAULT;
6372 goto out;
edd16368 6373 }
9233fb10 6374 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 6375 iocommand.buf_size > 0) {
edd16368
SC		 6376 /* Copy the data out of the buffer we created */
6377 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 6378 rc = -EFAULT;
6379 goto out;
edd16368
SC		 6380 }
6381 }
c1f63c8f 6382out:
45fcb86e 6383 cmd_free(h, c);
c1f63c8f
SC		 6384out_kfree:
6385 kfree(buff);
6386 return rc;
edd16368
SC		 6387}
6388
6389static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6390{
6391 BIG_IOCTL_Command_struct *ioc;
6392 struct CommandList *c;
6393 unsigned char **buff = NULL;
6394 int *buff_size = NULL;
50a0decf 6395 u64 temp64;
edd16368
SC		 6396 BYTE sg_used = 0;
6397 int status = 0;
01a02ffc
SC		 6398 u32 left;
6399 u32 sz;
edd16368
SC		 6400 BYTE __user *data_ptr;
6401
6402 if (!argp)
6403 return -EINVAL;
6404 if (!capable(CAP_SYS_RAWIO))
6405 return -EPERM;
6406 ioc = (BIG_IOCTL_Command_struct *)
6407 kmalloc(sizeof(*ioc), GFP_KERNEL);
6408 if (!ioc) {
6409 status = -ENOMEM;
6410 goto cleanup1;
6411 }
6412 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
6413 status = -EFAULT;
6414 goto cleanup1;
6415 }
6416 if ((ioc->buf_size < 1) &&
6417 (ioc->Request.Type.Direction != XFER_NONE)) {
6418 status = -EINVAL;
6419 goto cleanup1;
6420 }
6421 /* Check kmalloc limits using all SGs */
6422 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
6423 status = -EINVAL;
6424 goto cleanup1;
6425 }
d66ae08b 6426 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 6427 status = -EINVAL;
6428 goto cleanup1;
6429 }
d66ae08b 6430 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 6431 if (!buff) {
6432 status = -ENOMEM;
6433 goto cleanup1;
6434 }
d66ae08b 6435 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 6436 if (!buff_size) {
6437 status = -ENOMEM;
6438 goto cleanup1;
6439 }
6440 left = ioc->buf_size;
6441 data_ptr = ioc->buf;
6442 while (left) {
6443 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6444 buff_size[sg_used] = sz;
6445 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6446 if (buff[sg_used] == NULL) {
6447 status = -ENOMEM;
6448 goto cleanup1;
6449 }
9233fb10 6450 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 6451 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 6452 status = -EFAULT;
edd16368
SC		 6453 goto cleanup1;
6454 }
6455 } else
6456 memset(buff[sg_used], 0, sz);
6457 left -= sz;
6458 data_ptr += sz;
6459 sg_used++;
6460 }
45fcb86e 6461 c = cmd_alloc(h);
bf43caf3 6462
edd16368 6463 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6464 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368 6465 c->Header.ReplyQueue = 0;
50a0decf
SC		 6466 c->Header.SGList = (u8) sg_used;
6467 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 6468 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6469 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6470 if (ioc->buf_size > 0) {
6471 int i;
6472 for (i = 0; i < sg_used; i++) {
50a0decf 6473 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 6474 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6475 if (dma_mapping_error(&h->pdev->dev,
6476 (dma_addr_t) temp64)) {
6477 c->SG[i].Addr = cpu_to_le64(0);
6478 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 6479 hpsa_pci_unmap(h->pdev, c, i,
6480 PCI_DMA_BIDIRECTIONAL);
6481 status = -ENOMEM;
e2d4a1f6 6482 goto cleanup0;
bcc48ffa 6483 }
50a0decf
SC		 6484 c->SG[i].Addr = cpu_to_le64(temp64);
6485 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6486 c->SG[i].Ext = cpu_to_le32(0);
edd16368 6487 }
50a0decf 6488 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 6489 }
25163bd5 6490 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
b03a7771
SC		 6491 if (sg_used)
6492 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 6493 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6494 if (status) {
6495 status = -EIO;
6496 goto cleanup0;
6497 }
6498
edd16368
SC		 6499 /* Copy the error information out */
6500 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6501 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 6502 status = -EFAULT;
e2d4a1f6 6503 goto cleanup0;
edd16368 6504 }
9233fb10 6505 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 6506 int i;
6507
edd16368
SC		 6508 /* Copy the data out of the buffer we created */
6509 BYTE __user *ptr = ioc->buf;
6510 for (i = 0; i < sg_used; i++) {
6511 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 6512 status = -EFAULT;
e2d4a1f6 6513 goto cleanup0;
edd16368
SC		 6514 }
6515 ptr += buff_size[i];
6516 }
6517 }
edd16368 6518 status = 0;
e2d4a1f6 6519cleanup0:
45fcb86e 6520 cmd_free(h, c);
edd16368
SC		 6521cleanup1:
6522 if (buff) {
2b08b3e9
DB		 6523 int i;
6524
edd16368
SC		 6525 for (i = 0; i < sg_used; i++)
6526 kfree(buff[i]);
6527 kfree(buff);
6528 }
6529 kfree(buff_size);
6530 kfree(ioc);
6531 return status;
6532}
6533
6534static void check_ioctl_unit_attention(struct ctlr_info *h,
6535 struct CommandList *c)
6536{
6537 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6538 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6539 (void) check_for_unit_attention(h, c);
6540}
0390f0c0 6541
edd16368
SC		 6542/*
6543 * ioctl
6544 */
42a91641 6545static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 6546{
6547 struct ctlr_info *h;
6548 void __user *argp = (void __user *)arg;
0390f0c0 6549 int rc;
edd16368
SC		 6550
6551 h = sdev_to_hba(dev);
6552
6553 switch (cmd) {
6554 case CCISS_DEREGDISK:
6555 case CCISS_REGNEWDISK:
6556 case CCISS_REGNEWD:
a08a8471 6557 hpsa_scan_start(h->scsi_host);
edd16368
SC		 6558 return 0;
6559 case CCISS_GETPCIINFO:
6560 return hpsa_getpciinfo_ioctl(h, argp);
6561 case CCISS_GETDRIVVER:
6562 return hpsa_getdrivver_ioctl(h, argp);
6563 case CCISS_PASSTHRU:
34f0c627 6564 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6565 return -EAGAIN;
6566 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 6567 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6568 return rc;
edd16368 6569 case CCISS_BIG_PASSTHRU:
34f0c627 6570 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6571 return -EAGAIN;
6572 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 6573 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6574 return rc;
edd16368
SC		 6575 default:
6576 return -ENOTTY;
6577 }
6578}
6579
bf43caf3 6580static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6f039790 6581 u8 reset_type)
64670ac8
SC		 6582{
6583 struct CommandList *c;
6584
6585 c = cmd_alloc(h);
bf43caf3 6586
a2dac136
SC		 6587 /* fill_cmd can't fail here, no data buffer to map */
6588 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 6589 RAID_CTLR_LUNID, TYPE_MSG);
6590 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6591 c->waiting = NULL;
6592 enqueue_cmd_and_start_io(h, c);
6593 /* Don't wait for completion, the reset won't complete. Don't free
6594 * the command either. This is the last command we will send before
6595 * re-initializing everything, so it doesn't matter and won't leak.
6596 */
bf43caf3 6597 return;
64670ac8
SC		 6598}
6599
a2dac136 6600static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 6601 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 6602 int cmd_type)
6603{
6604 int pci_dir = XFER_NONE;
9b5c48c2 6605 u64 tag; /* for commands to be aborted */
edd16368
SC		 6606
6607 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6608 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6609 c->Header.ReplyQueue = 0;
6610 if (buff != NULL && size > 0) {
6611 c->Header.SGList = 1;
50a0decf 6612 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6613 } else {
6614 c->Header.SGList = 0;
50a0decf 6615 c->Header.SGTotal = cpu_to_le16(0);
edd16368 6616 }
edd16368
SC		 6617 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6618
edd16368
SC		 6619 if (cmd_type == TYPE_CMD) {
6620 switch (cmd) {
6621 case HPSA_INQUIRY:
6622 /* are we trying to read a vital product page */
b7bb24eb 6623 if (page_code & VPD_PAGE) {
edd16368 6624 c->Request.CDB[1] = 0x01;
b7bb24eb 6625 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 6626 }
6627 c->Request.CDBLen = 6;
a505b86f
SC		 6628 c->Request.type_attr_dir =
6629 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6630 c->Request.Timeout = 0;
6631 c->Request.CDB[0] = HPSA_INQUIRY;
6632 c->Request.CDB[4] = size & 0xFF;
6633 break;
6634 case HPSA_REPORT_LOG:
6635 case HPSA_REPORT_PHYS:
6636 /* Talking to controller so It's a physical command
6637 mode = 00 target = 0. Nothing to write.
6638 */
6639 c->Request.CDBLen = 12;
a505b86f
SC		 6640 c->Request.type_attr_dir =
6641 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6642 c->Request.Timeout = 0;
6643 c->Request.CDB[0] = cmd;
6644 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6645 c->Request.CDB[7] = (size >> 16) & 0xFF;
6646 c->Request.CDB[8] = (size >> 8) & 0xFF;
6647 c->Request.CDB[9] = size & 0xFF;
6648 break;
c2adae44
ST		 6649 case BMIC_SENSE_DIAG_OPTIONS:
6650 c->Request.CDBLen = 16;
6651 c->Request.type_attr_dir =
6652 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6653 c->Request.Timeout = 0;
6654 /* Spec says this should be BMIC_WRITE */
6655 c->Request.CDB[0] = BMIC_READ;
6656 c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS;
6657 break;
6658 case BMIC_SET_DIAG_OPTIONS:
6659 c->Request.CDBLen = 16;
6660 c->Request.type_attr_dir =
6661 TYPE_ATTR_DIR(cmd_type,
6662 ATTR_SIMPLE, XFER_WRITE);
6663 c->Request.Timeout = 0;
6664 c->Request.CDB[0] = BMIC_WRITE;
6665 c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS;
6666 break;
edd16368
SC		 6667 case HPSA_CACHE_FLUSH:
6668 c->Request.CDBLen = 12;
a505b86f
SC		 6669 c->Request.type_attr_dir =
6670 TYPE_ATTR_DIR(cmd_type,
6671 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 6672 c->Request.Timeout = 0;
6673 c->Request.CDB[0] = BMIC_WRITE;
6674 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 6675 c->Request.CDB[7] = (size >> 8) & 0xFF;
6676 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 6677 break;
6678 case TEST_UNIT_READY:
6679 c->Request.CDBLen = 6;
a505b86f
SC		 6680 c->Request.type_attr_dir =
6681 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 6682 c->Request.Timeout = 0;
6683 break;
283b4a9b
SC		 6684 case HPSA_GET_RAID_MAP:
6685 c->Request.CDBLen = 12;
a505b86f
SC		 6686 c->Request.type_attr_dir =
6687 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 6688 c->Request.Timeout = 0;
6689 c->Request.CDB[0] = HPSA_CISS_READ;
6690 c->Request.CDB[1] = cmd;
6691 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6692 c->Request.CDB[7] = (size >> 16) & 0xFF;
6693 c->Request.CDB[8] = (size >> 8) & 0xFF;
6694 c->Request.CDB[9] = size & 0xFF;
6695 break;
316b221a
SC		 6696 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6697 c->Request.CDBLen = 10;
a505b86f
SC		 6698 c->Request.type_attr_dir =
6699 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 6700 c->Request.Timeout = 0;
6701 c->Request.CDB[0] = BMIC_READ;
6702 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6703 c->Request.CDB[7] = (size >> 16) & 0xFF;
6704 c->Request.CDB[8] = (size >> 8) & 0xFF;
6705 break;
03383736
DB		 6706 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6707 c->Request.CDBLen = 10;
6708 c->Request.type_attr_dir =
6709 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6710 c->Request.Timeout = 0;
6711 c->Request.CDB[0] = BMIC_READ;
6712 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6713 c->Request.CDB[7] = (size >> 16) & 0xFF;
6714 c->Request.CDB[8] = (size >> 8) & 0XFF;
6715 break;
d04e62b9
KB		 6716 case BMIC_SENSE_SUBSYSTEM_INFORMATION:
6717 c->Request.CDBLen = 10;
6718 c->Request.type_attr_dir =
6719 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6720 c->Request.Timeout = 0;
6721 c->Request.CDB[0] = BMIC_READ;
6722 c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION;
6723 c->Request.CDB[7] = (size >> 16) & 0xFF;
6724 c->Request.CDB[8] = (size >> 8) & 0XFF;
6725 break;
cca8f13b
DB		 6726 case BMIC_SENSE_STORAGE_BOX_PARAMS:
6727 c->Request.CDBLen = 10;
6728 c->Request.type_attr_dir =
6729 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6730 c->Request.Timeout = 0;
6731 c->Request.CDB[0] = BMIC_READ;
6732 c->Request.CDB[6] = BMIC_SENSE_STORAGE_BOX_PARAMS;
6733 c->Request.CDB[7] = (size >> 16) & 0xFF;
6734 c->Request.CDB[8] = (size >> 8) & 0XFF;
6735 break;
66749d0d
ST		 6736 case BMIC_IDENTIFY_CONTROLLER:
6737 c->Request.CDBLen = 10;
6738 c->Request.type_attr_dir =
6739 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6740 c->Request.Timeout = 0;
6741 c->Request.CDB[0] = BMIC_READ;
6742 c->Request.CDB[1] = 0;
6743 c->Request.CDB[2] = 0;
6744 c->Request.CDB[3] = 0;
6745 c->Request.CDB[4] = 0;
6746 c->Request.CDB[5] = 0;
6747 c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER;
6748 c->Request.CDB[7] = (size >> 16) & 0xFF;
6749 c->Request.CDB[8] = (size >> 8) & 0XFF;
6750 c->Request.CDB[9] = 0;
6751 break;
edd16368
SC		 6752 default:
6753 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6754 BUG();
a2dac136 6755 return -1;
edd16368
SC		 6756 }
6757 } else if (cmd_type == TYPE_MSG) {
6758 switch (cmd) {
6759
0b9b7b6e
ST		 6760 case HPSA_PHYS_TARGET_RESET:
6761 c->Request.CDBLen = 16;
6762 c->Request.type_attr_dir =
6763 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
6764 c->Request.Timeout = 0; /* Don't time out */
6765 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6766 c->Request.CDB[0] = HPSA_RESET;
6767 c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE;
6768 /* Physical target reset needs no control bytes 4-7*/
6769 c->Request.CDB[4] = 0x00;
6770 c->Request.CDB[5] = 0x00;
6771 c->Request.CDB[6] = 0x00;
6772 c->Request.CDB[7] = 0x00;
6773 break;
edd16368
SC		 6774 case HPSA_DEVICE_RESET_MSG:
6775 c->Request.CDBLen = 16;
a505b86f
SC		 6776 c->Request.type_attr_dir =
6777 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 6778 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 6779 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6780 c->Request.CDB[0] = cmd;
21e89afd 6781 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 6782 /* If bytes 4-7 are zero, it means reset the */
6783 /* LunID device */
6784 c->Request.CDB[4] = 0x00;
6785 c->Request.CDB[5] = 0x00;
6786 c->Request.CDB[6] = 0x00;
6787 c->Request.CDB[7] = 0x00;
75167d2c
SC		 6788 break;
6789 case HPSA_ABORT_MSG:
9b5c48c2 6790 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 6791 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 6792 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
6793 tag, c->Header.tag);
75167d2c 6794 c->Request.CDBLen = 16;
a505b86f
SC		 6795 c->Request.type_attr_dir =
6796 TYPE_ATTR_DIR(cmd_type,
6797 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 6798 c->Request.Timeout = 0; /* Don't time out */
6799 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
6800 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
6801 c->Request.CDB[2] = 0x00; /* reserved */
6802 c->Request.CDB[3] = 0x00; /* reserved */
6803 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 6804 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 6805 c->Request.CDB[12] = 0x00; /* reserved */
6806 c->Request.CDB[13] = 0x00; /* reserved */
6807 c->Request.CDB[14] = 0x00; /* reserved */
6808 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 6809 break;
edd16368
SC		 6810 default:
6811 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6812 cmd);
6813 BUG();
6814 }
6815 } else {
6816 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6817 BUG();
6818 }
6819
a505b86f 6820 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 6821 case XFER_READ:
6822 pci_dir = PCI_DMA_FROMDEVICE;
6823 break;
6824 case XFER_WRITE:
6825 pci_dir = PCI_DMA_TODEVICE;
6826 break;
6827 case XFER_NONE:
6828 pci_dir = PCI_DMA_NONE;
6829 break;
6830 default:
6831 pci_dir = PCI_DMA_BIDIRECTIONAL;
6832 }
a2dac136
SC		 6833 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
6834 return -1;
6835 return 0;
edd16368
SC		 6836}
6837
6838/*
6839 * Map (physical) PCI mem into (virtual) kernel space
6840 */
6841static void __iomem *remap_pci_mem(ulong base, ulong size)
6842{
6843 ulong page_base = ((ulong) base) & PAGE_MASK;
6844 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 6845 void __iomem *page_remapped = ioremap_nocache(page_base,
6846 page_offs + size);
edd16368
SC		 6847
6848 return page_remapped ? (page_remapped + page_offs) : NULL;
6849}
6850
254f796b 6851static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 6852{
254f796b 6853 return h->access.command_completed(h, q);
edd16368
SC		 6854}
6855
900c5440 6856static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 6857{
6858 return h->access.intr_pending(h);
6859}
6860
6861static inline long interrupt_not_for_us(struct ctlr_info *h)
6862{
10f66018
SC		 6863 return (h->access.intr_pending(h) == 0) ||
6864 (h->interrupts_enabled == 0);
edd16368
SC		 6865}
6866
01a02ffc
SC		 6867static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6868 u32 raw_tag)
edd16368
SC		 6869{
6870 if (unlikely(tag_index >= h->nr_cmds)) {
6871 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6872 return 1;
6873 }
6874 return 0;
6875}
6876
5a3d16f5 6877static inline void finish_cmd(struct CommandList *c)
edd16368 6878{
e85c5974 6879 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 6880 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6881 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 6882 complete_scsi_command(c);
8be986cc 6883 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
edd16368 6884 complete(c->waiting);
a104c99f
SC		 6885}
6886
303932fd 6887/* process completion of an indexed ("direct lookup") command */
1d94f94d 6888static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 6889 u32 raw_tag)
6890{
6891 u32 tag_index;
6892 struct CommandList *c;
6893
f2405db8 6894 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 6895 if (!bad_tag(h, tag_index, raw_tag)) {
6896 c = h->cmd_pool + tag_index;
6897 finish_cmd(c);
6898 }
303932fd
DB		 6899}
6900
64670ac8
SC		 6901/* Some controllers, like p400, will give us one interrupt
6902 * after a soft reset, even if we turned interrupts off.
6903 * Only need to check for this in the hpsa_xxx_discard_completions
6904 * functions.
6905 */
6906static int ignore_bogus_interrupt(struct ctlr_info *h)
6907{
6908 if (likely(!reset_devices))
6909 return 0;
6910
6911 if (likely(h->interrupts_enabled))
6912 return 0;
6913
6914 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
6915 "(known firmware bug.) Ignoring.\n");
6916
6917 return 1;
6918}
6919
254f796b
MG		 6920/*
6921 * Convert &h->q[x] (passed to interrupt handlers) back to h.
6922 * Relies on (h-q[x] == x) being true for x such that
6923 * 0 <= x < MAX_REPLY_QUEUES.
6924 */
6925static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 6926{
254f796b
MG		 6927 return container_of((queue - *queue), struct ctlr_info, q[0]);
6928}
6929
6930static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6931{
6932 struct ctlr_info *h = queue_to_hba(queue);
6933 u8 q = *(u8 *) queue;
64670ac8
SC		 6934 u32 raw_tag;
6935
6936 if (ignore_bogus_interrupt(h))
6937 return IRQ_NONE;
6938
6939 if (interrupt_not_for_us(h))
6940 return IRQ_NONE;
a0c12413 6941 h->last_intr_timestamp = get_jiffies_64();
64670ac8 6942 while (interrupt_pending(h)) {
254f796b 6943 raw_tag = get_next_completion(h, q);
64670ac8 6944 while (raw_tag != FIFO_EMPTY)
254f796b 6945 raw_tag = next_command(h, q);
64670ac8 6946 }
64670ac8
SC		 6947 return IRQ_HANDLED;
6948}
6949
254f796b 6950static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 6951{
254f796b 6952 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 6953 u32 raw_tag;
254f796b 6954 u8 q = *(u8 *) queue;
64670ac8
SC		 6955
6956 if (ignore_bogus_interrupt(h))
6957 return IRQ_NONE;
6958
a0c12413 6959 h->last_intr_timestamp = get_jiffies_64();
254f796b 6960 raw_tag = get_next_completion(h, q);
64670ac8 6961 while (raw_tag != FIFO_EMPTY)
254f796b 6962 raw_tag = next_command(h, q);
64670ac8
SC		 6963 return IRQ_HANDLED;
6964}
6965
254f796b 6966static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 6967{
254f796b 6968 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 6969 u32 raw_tag;
254f796b 6970 u8 q = *(u8 *) queue;
edd16368
SC		 6971
6972 if (interrupt_not_for_us(h))
6973 return IRQ_NONE;
a0c12413 6974 h->last_intr_timestamp = get_jiffies_64();
10f66018 6975 while (interrupt_pending(h)) {
254f796b 6976 raw_tag = get_next_completion(h, q);
10f66018 6977 while (raw_tag != FIFO_EMPTY) {
f2405db8 6978 process_indexed_cmd(h, raw_tag);
254f796b 6979 raw_tag = next_command(h, q);
10f66018
SC		 6980 }
6981 }
10f66018
SC		 6982 return IRQ_HANDLED;
6983}
6984
254f796b 6985static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 6986{
254f796b 6987 struct ctlr_info *h = queue_to_hba(queue);
10f66018 6988 u32 raw_tag;
254f796b 6989 u8 q = *(u8 *) queue;
10f66018 6990
a0c12413 6991 h->last_intr_timestamp = get_jiffies_64();
254f796b 6992 raw_tag = get_next_completion(h, q);
303932fd 6993 while (raw_tag != FIFO_EMPTY) {
f2405db8 6994 process_indexed_cmd(h, raw_tag);
254f796b 6995 raw_tag = next_command(h, q);
edd16368 6996 }
edd16368
SC		 6997 return IRQ_HANDLED;
6998}
6999
a9a3a273
SC		 7000/* Send a message CDB to the firmware. Careful, this only works
7001 * in simple mode, not performant mode due to the tag lookup.
7002 * We only ever use this immediately after a controller reset.
7003 */
6f039790
GKH		 7004static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
7005 unsigned char type)
edd16368
SC		 7006{
7007 struct Command {
7008 struct CommandListHeader CommandHeader;
7009 struct RequestBlock Request;
7010 struct ErrDescriptor ErrorDescriptor;
7011 };
7012 struct Command *cmd;
7013 static const size_t cmd_sz = sizeof(*cmd) +
7014 sizeof(cmd->ErrorDescriptor);
7015 dma_addr_t paddr64;
2b08b3e9
DB		 7016 __le32 paddr32;
7017 u32 tag;
edd16368
SC		 7018 void __iomem *vaddr;
7019 int i, err;
7020
7021 vaddr = pci_ioremap_bar(pdev, 0);
7022 if (vaddr == NULL)
7023 return -ENOMEM;
7024
7025 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
7026 * CCISS commands, so they must be allocated from the lower 4GiB of
7027 * memory.
7028 */
7029 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
7030 if (err) {
7031 iounmap(vaddr);
1eaec8f3 7032 return err;
edd16368
SC		 7033 }
7034
7035 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
7036 if (cmd == NULL) {
7037 iounmap(vaddr);
7038 return -ENOMEM;
7039 }
7040
7041 /* This must fit, because of the 32-bit consistent DMA mask. Also,
7042 * although there's no guarantee, we assume that the address is at
7043 * least 4-byte aligned (most likely, it's page-aligned).
7044 */
2b08b3e9 7045 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 7046
7047 cmd->CommandHeader.ReplyQueue = 0;
7048 cmd->CommandHeader.SGList = 0;
50a0decf 7049 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 7050 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 7051 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
7052
7053 cmd->Request.CDBLen = 16;
a505b86f
SC		 7054 cmd->Request.type_attr_dir =
7055 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 7056 cmd->Request.Timeout = 0; /* Don't time out */
7057 cmd->Request.CDB[0] = opcode;
7058 cmd->Request.CDB[1] = type;
7059 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 7060 cmd->ErrorDescriptor.Addr =
2b08b3e9 7061 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 7062 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 7063
2b08b3e9 7064 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 7065
7066 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
7067 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 7068 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 7069 break;
7070 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
7071 }
7072
7073 iounmap(vaddr);
7074
7075 /* we leak the DMA buffer here ... no choice since the controller could
7076 * still complete the command.
7077 */
7078 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
7079 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
7080 opcode, type);
7081 return -ETIMEDOUT;
7082 }
7083
7084 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
7085
7086 if (tag & HPSA_ERROR_BIT) {
7087 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
7088 opcode, type);
7089 return -EIO;
7090 }
7091
7092 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
7093 opcode, type);
7094 return 0;
7095}
7096
edd16368
SC		 7097#define hpsa_noop(p) hpsa_message(p, 3, 0)
7098
1df8552a 7099static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 7100 void __iomem *vaddr, u32 use_doorbell)
1df8552a 7101{
1df8552a
SC		 7102
7103 if (use_doorbell) {
7104 /* For everything after the P600, the PCI power state method
7105 * of resetting the controller doesn't work, so we have this
7106 * other way using the doorbell register.
7107 */
7108 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 7109 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 7110
00701a96 7111 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 7112 * doorbell reset and before any attempt to talk to the board
7113 * at all to ensure that this actually works and doesn't fall
7114 * over in some weird corner cases.
7115 */
00701a96 7116 msleep(10000);
1df8552a
SC		 7117 } else { /* Try to do it the PCI power state way */
7118
7119 /* Quoting from the Open CISS Specification: "The Power
7120 * Management Control/Status Register (CSR) controls the power
7121 * state of the device. The normal operating state is D0,
7122 * CSR=00h. The software off state is D3, CSR=03h. To reset
7123 * the controller, place the interface device in D3 then to D0,
7124 * this causes a secondary PCI reset which will reset the
7125 * controller." */
2662cab8
DB		 7126
7127 int rc = 0;
7128
1df8552a 7129 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 7130
1df8552a 7131 /* enter the D3hot power management state */
2662cab8
DB		 7132 rc = pci_set_power_state(pdev, PCI_D3hot);
7133 if (rc)
7134 return rc;
1df8552a
SC		 7135
7136 msleep(500);
7137
7138 /* enter the D0 power management state */
2662cab8
DB		 7139 rc = pci_set_power_state(pdev, PCI_D0);
7140 if (rc)
7141 return rc;
c4853efe
MM		 7142
7143 /*
7144 * The P600 requires a small delay when changing states.
7145 * Otherwise we may think the board did not reset and we bail.
7146 * This for kdump only and is particular to the P600.
7147 */
7148 msleep(500);
1df8552a
SC		 7149 }
7150 return 0;
7151}
7152
6f039790 7153static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 7154{
7155 memset(driver_version, 0, len);
f79cfec6 7156 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 7157}
7158
6f039790 7159static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 7160{
7161 char *driver_version;
7162 int i, size = sizeof(cfgtable->driver_version);
7163
7164 driver_version = kmalloc(size, GFP_KERNEL);
7165 if (!driver_version)
7166 return -ENOMEM;
7167
7168 init_driver_version(driver_version, size);
7169 for (i = 0; i < size; i++)
7170 writeb(driver_version[i], &cfgtable->driver_version[i]);
7171 kfree(driver_version);
7172 return 0;
7173}
7174
6f039790
GKH		 7175static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
7176 unsigned char *driver_ver)
580ada3c
SC		 7177{
7178 int i;
7179
7180 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
7181 driver_ver[i] = readb(&cfgtable->driver_version[i]);
7182}
7183
6f039790 7184static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 7185{
7186
7187 char *driver_ver, *old_driver_ver;
7188 int rc, size = sizeof(cfgtable->driver_version);
7189
7190 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
7191 if (!old_driver_ver)
7192 return -ENOMEM;
7193 driver_ver = old_driver_ver + size;
7194
7195 /* After a reset, the 32 bytes of "driver version" in the cfgtable
7196 * should have been changed, otherwise we know the reset failed.
7197 */
7198 init_driver_version(old_driver_ver, size);
7199 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
7200 rc = !memcmp(driver_ver, old_driver_ver, size);
7201 kfree(old_driver_ver);
7202 return rc;
7203}
edd16368 7204/* This does a hard reset of the controller using PCI power management
1df8552a 7205 * states or the using the doorbell register.
edd16368 7206 */
6b6c1cd7 7207static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 7208{
1df8552a
SC		 7209 u64 cfg_offset;
7210 u32 cfg_base_addr;
7211 u64 cfg_base_addr_index;
7212 void __iomem *vaddr;
7213 unsigned long paddr;
580ada3c 7214 u32 misc_fw_support;
270d05de 7215 int rc;
1df8552a 7216 struct CfgTable __iomem *cfgtable;
cf0b08d0 7217 u32 use_doorbell;
270d05de 7218 u16 command_register;
edd16368 7219
1df8552a
SC		 7220 /* For controllers as old as the P600, this is very nearly
7221 * the same thing as
edd16368
SC		 7222 *
7223 * pci_save_state(pci_dev);
7224 * pci_set_power_state(pci_dev, PCI_D3hot);
7225 * pci_set_power_state(pci_dev, PCI_D0);
7226 * pci_restore_state(pci_dev);
7227 *
1df8552a
SC		 7228 * For controllers newer than the P600, the pci power state
7229 * method of resetting doesn't work so we have another way
7230 * using the doorbell register.
edd16368 7231 */
18867659 7232
60f923b9
RE		 7233 if (!ctlr_is_resettable(board_id)) {
7234 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 7235 return -ENODEV;
7236 }
46380786
SC		 7237
7238 /* if controller is soft- but not hard resettable... */
7239 if (!ctlr_is_hard_resettable(board_id))
7240 return -ENOTSUPP; /* try soft reset later. */
18867659 7241
270d05de
SC		 7242 /* Save the PCI command register */
7243 pci_read_config_word(pdev, 4, &command_register);
270d05de 7244 pci_save_state(pdev);
edd16368 7245
1df8552a
SC		 7246 /* find the first memory BAR, so we can find the cfg table */
7247 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
7248 if (rc)
7249 return rc;
7250 vaddr = remap_pci_mem(paddr, 0x250);
7251 if (!vaddr)
7252 return -ENOMEM;
edd16368 7253
1df8552a
SC		 7254 /* find cfgtable in order to check if reset via doorbell is supported */
7255 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
7256 &cfg_base_addr_index, &cfg_offset);
7257 if (rc)
7258 goto unmap_vaddr;
7259 cfgtable = remap_pci_mem(pci_resource_start(pdev,
7260 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
7261 if (!cfgtable) {
7262 rc = -ENOMEM;
7263 goto unmap_vaddr;
7264 }
580ada3c
SC		 7265 rc = write_driver_ver_to_cfgtable(cfgtable);
7266 if (rc)
03741d95 7267 goto unmap_cfgtable;
edd16368 7268
cf0b08d0
SC		 7269 /* If reset via doorbell register is supported, use that.
7270 * There are two such methods. Favor the newest method.
7271 */
1df8552a 7272 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 7273 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
7274 if (use_doorbell) {
7275 use_doorbell = DOORBELL_CTLR_RESET2;
7276 } else {
7277 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
7278 if (use_doorbell) {
050f7147
SC		 7279 dev_warn(&pdev->dev,
7280 "Soft reset not supported. Firmware update is required.\n");
64670ac8 7281 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 7282 goto unmap_cfgtable;
7283 }
7284 }
edd16368 7285
1df8552a
SC		 7286 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
7287 if (rc)
7288 goto unmap_cfgtable;
edd16368 7289
270d05de 7290 pci_restore_state(pdev);
270d05de 7291 pci_write_config_word(pdev, 4, command_register);
edd16368 7292
1df8552a
SC		 7293 /* Some devices (notably the HP Smart Array 5i Controller)
7294 need a little pause here */
7295 msleep(HPSA_POST_RESET_PAUSE_MSECS);
7296
fe5389c8
SC		 7297 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
7298 if (rc) {
7299 dev_warn(&pdev->dev,
050f7147 7300 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 7301 goto unmap_cfgtable;
7302 }
fe5389c8 7303
580ada3c
SC		 7304 rc = controller_reset_failed(vaddr);
7305 if (rc < 0)
7306 goto unmap_cfgtable;
7307 if (rc) {
64670ac8
SC		 7308 dev_warn(&pdev->dev, "Unable to successfully reset "
7309 "controller. Will try soft reset.\n");
7310 rc = -ENOTSUPP;
580ada3c 7311 } else {
64670ac8 7312 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 7313 }
7314
7315unmap_cfgtable:
7316 iounmap(cfgtable);
7317
7318unmap_vaddr:
7319 iounmap(vaddr);
7320 return rc;
edd16368
SC		 7321}
7322
7323/*
7324 * We cannot read the structure directly, for portability we must use
7325 * the io functions.
7326 * This is for debug only.
7327 */
42a91641 7328static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 7329{
58f8665c 7330#ifdef HPSA_DEBUG
edd16368
SC		 7331 int i;
7332 char temp_name[17];
7333
7334 dev_info(dev, "Controller Configuration information\n");
7335 dev_info(dev, "------------------------------------\n");
7336 for (i = 0; i < 4; i++)
7337 temp_name[i] = readb(&(tb->Signature[i]));
7338 temp_name[4] = '\0';
7339 dev_info(dev, " Signature = %s\n", temp_name);
7340 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
7341 dev_info(dev, " Transport methods supported = 0x%x\n",
7342 readl(&(tb->TransportSupport)));
7343 dev_info(dev, " Transport methods active = 0x%x\n",
7344 readl(&(tb->TransportActive)));
7345 dev_info(dev, " Requested transport Method = 0x%x\n",
7346 readl(&(tb->HostWrite.TransportRequest)));
7347 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
7348 readl(&(tb->HostWrite.CoalIntDelay)));
7349 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
7350 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 7351 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 7352 readl(&(tb->CmdsOutMax)));
7353 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
7354 for (i = 0; i < 16; i++)
7355 temp_name[i] = readb(&(tb->ServerName[i]));
7356 temp_name[16] = '\0';
7357 dev_info(dev, " Server Name = %s\n", temp_name);
7358 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
7359 readl(&(tb->HeartBeat)));
edd16368 7360#endif /* HPSA_DEBUG */
58f8665c 7361}
edd16368
SC		 7362
7363static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
7364{
7365 int i, offset, mem_type, bar_type;
7366
7367 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
7368 return 0;
7369 offset = 0;
7370 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
7371 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
7372 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
7373 offset += 4;
7374 else {
7375 mem_type = pci_resource_flags(pdev, i) &
7376 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
7377 switch (mem_type) {
7378 case PCI_BASE_ADDRESS_MEM_TYPE_32:
7379 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
7380 offset += 4; /* 32 bit */
7381 break;
7382 case PCI_BASE_ADDRESS_MEM_TYPE_64:
7383 offset += 8;
7384 break;
7385 default: /* reserved in PCI 2.2 */
7386 dev_warn(&pdev->dev,
7387 "base address is invalid\n");
7388 return -1;
7389 break;
7390 }
7391 }
7392 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
7393 return i + 1;
7394 }
7395 return -1;
7396}
7397
cc64c817
RE		 7398static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
7399{
7400 if (h->msix_vector) {
7401 if (h->pdev->msix_enabled)
7402 pci_disable_msix(h->pdev);
105a3dbc 7403 h->msix_vector = 0;
cc64c817
RE		 7404 } else if (h->msi_vector) {
7405 if (h->pdev->msi_enabled)
7406 pci_disable_msi(h->pdev);
105a3dbc 7407 h->msi_vector = 0;
cc64c817
RE		 7408 }
7409}
7410
edd16368 7411/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 7412 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 7413 */
6f039790 7414static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 7415{
7416#ifdef CONFIG_PCI_MSI
254f796b
MG		 7417 int err, i;
7418 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
7419
7420 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
7421 hpsa_msix_entries[i].vector = 0;
7422 hpsa_msix_entries[i].entry = i;
7423 }
edd16368
SC		 7424
7425 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 7426 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
7427 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 7428 goto default_int_mode;
55c06c71 7429 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 7430 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 7431 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 7432 if (h->msix_vector > num_online_cpus())
7433 h->msix_vector = num_online_cpus();
18fce3c4
AG		 7434 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
7435 1, h->msix_vector);
7436 if (err < 0) {
7437 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
7438 h->msix_vector = 0;
7439 goto single_msi_mode;
7440 } else if (err < h->msix_vector) {
55c06c71 7441 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 7442 "available\n", err);
edd16368 7443 }
18fce3c4
AG		 7444 h->msix_vector = err;
7445 for (i = 0; i < h->msix_vector; i++)
7446 h->intr[i] = hpsa_msix_entries[i].vector;
7447 return;
edd16368 7448 }
18fce3c4 7449single_msi_mode:
55c06c71 7450 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 7451 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 7452 if (!pci_enable_msi(h->pdev))
edd16368
SC		 7453 h->msi_vector = 1;
7454 else
55c06c71 7455 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 7456 }
7457default_int_mode:
7458#endif /* CONFIG_PCI_MSI */
7459 /* if we get here we're going to use the default interrupt mode */
a9a3a273 7460 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 7461}
7462
6f039790 7463static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 7464{
7465 int i;
7466 u32 subsystem_vendor_id, subsystem_device_id;
7467
7468 subsystem_vendor_id = pdev->subsystem_vendor;
7469 subsystem_device_id = pdev->subsystem_device;
7470 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
7471 subsystem_vendor_id;
7472
7473 for (i = 0; i < ARRAY_SIZE(products); i++)
7474 if (*board_id == products[i].board_id)
7475 return i;
7476
6798cc0a
SC		 7477 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
7478 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
7479 !hpsa_allow_any) {
e5c880d1
SC		 7480 dev_warn(&pdev->dev, "unrecognized board ID: "
7481 "0x%08x, ignoring.\n", *board_id);
7482 return -ENODEV;
7483 }
7484 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
7485}
7486
6f039790
GKH		 7487static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
7488 unsigned long *memory_bar)
3a7774ce
SC		 7489{
7490 int i;
7491
7492 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 7493 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 7494 /* addressing mode bits already removed */
12d2cd47
SC		 7495 *memory_bar = pci_resource_start(pdev, i);
7496 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 7497 *memory_bar);
7498 return 0;
7499 }
12d2cd47 7500 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 7501 return -ENODEV;
7502}
7503
6f039790
GKH		 7504static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7505 int wait_for_ready)
2c4c8c8b 7506{
fe5389c8 7507 int i, iterations;
2c4c8c8b 7508 u32 scratchpad;
fe5389c8
SC		 7509 if (wait_for_ready)
7510 iterations = HPSA_BOARD_READY_ITERATIONS;
7511 else
7512 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 7513
fe5389c8
SC		 7514 for (i = 0; i < iterations; i++) {
7515 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7516 if (wait_for_ready) {
7517 if (scratchpad == HPSA_FIRMWARE_READY)
7518 return 0;
7519 } else {
7520 if (scratchpad != HPSA_FIRMWARE_READY)
7521 return 0;
7522 }
2c4c8c8b
SC		 7523 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7524 }
fe5389c8 7525 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 7526 return -ENODEV;
7527}
7528
6f039790
GKH		 7529static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7530 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7531 u64 *cfg_offset)
a51fd47f
SC		 7532{
7533 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7534 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7535 *cfg_base_addr &= (u32) 0x0000ffff;
7536 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7537 if (*cfg_base_addr_index == -1) {
7538 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7539 return -ENODEV;
7540 }
7541 return 0;
7542}
7543
195f2c65
RE		 7544static void hpsa_free_cfgtables(struct ctlr_info *h)
7545{
105a3dbc 7546 if (h->transtable) {
195f2c65 7547 iounmap(h->transtable);
105a3dbc
RE		 7548 h->transtable = NULL;
7549 }
7550 if (h->cfgtable) {
195f2c65 7551 iounmap(h->cfgtable);
105a3dbc
RE		 7552 h->cfgtable = NULL;
7553 }
195f2c65
RE		 7554}
7555
7556/* Find and map CISS config table and transfer table
7557+ * several items must be unmapped (freed) later
7558+ * */
6f039790 7559static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 7560{
01a02ffc
SC		 7561 u64 cfg_offset;
7562 u32 cfg_base_addr;
7563 u64 cfg_base_addr_index;
303932fd 7564 u32 trans_offset;
a51fd47f 7565 int rc;
77c4495c 7566
a51fd47f
SC		 7567 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7568 &cfg_base_addr_index, &cfg_offset);
7569 if (rc)
7570 return rc;
77c4495c 7571 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 7572 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 7573 if (!h->cfgtable) {
7574 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 7575 return -ENOMEM;
cd3c81c4 7576 }
580ada3c
SC		 7577 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7578 if (rc)
7579 return rc;
77c4495c 7580 /* Find performant mode table. */
a51fd47f 7581 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 7582 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7583 cfg_base_addr_index)+cfg_offset+trans_offset,
7584 sizeof(*h->transtable));
195f2c65
RE		 7585 if (!h->transtable) {
7586 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7587 hpsa_free_cfgtables(h);
77c4495c 7588 return -ENOMEM;
195f2c65 7589 }
77c4495c
SC		 7590 return 0;
7591}
7592
6f039790 7593static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 7594{
41ce4c35
SC		 7595#define MIN_MAX_COMMANDS 16
7596 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7597
7598 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 7599
7600 /* Limit commands in memory limited kdump scenario. */
7601 if (reset_devices && h->max_commands > 32)
7602 h->max_commands = 32;
7603
41ce4c35
SC		 7604 if (h->max_commands < MIN_MAX_COMMANDS) {
7605 dev_warn(&h->pdev->dev,
7606 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7607 h->max_commands,
7608 MIN_MAX_COMMANDS);
7609 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 7610 }
7611}
7612
c7ee65b3
WS		 7613/* If the controller reports that the total max sg entries is greater than 512,
7614 * then we know that chained SG blocks work. (Original smart arrays did not
7615 * support chained SG blocks and would return zero for max sg entries.)
7616 */
7617static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7618{
7619 return h->maxsgentries > 512;
7620}
7621
b93d7536
SC		 7622/* Interrogate the hardware for some limits:
7623 * max commands, max SG elements without chaining, and with chaining,
7624 * SG chain block size, etc.
7625 */
6f039790 7626static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 7627{
cba3d38b 7628 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 7629 h->nr_cmds = h->max_commands;
b93d7536 7630 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 7631 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 7632 if (hpsa_supports_chained_sg_blocks(h)) {
7633 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 7634 h->max_cmd_sg_entries = 32;
1a63ea6f 7635 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 7636 h->maxsgentries--; /* save one for chain pointer */
7637 } else {
c7ee65b3
WS		 7638 /*
7639 * Original smart arrays supported at most 31 s/g entries
7640 * embedded inline in the command (trying to use more
7641 * would lock up the controller)
7642 */
7643 h->max_cmd_sg_entries = 31;
1a63ea6f 7644 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 7645 h->chainsize = 0;
b93d7536 7646 }
75167d2c
SC		 7647
7648 /* Find out what task management functions are supported and cache */
7649 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 7650 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7651 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7652 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7653 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
8be986cc
SC		 7654 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7655 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
b93d7536
SC		 7656}
7657
76c46e49
SC		 7658static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7659{
0fc9fd40 7660 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 7661 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 7662 return false;
7663 }
7664 return true;
7665}
7666
97a5e98c 7667static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 7668{
97a5e98c 7669 u32 driver_support;
f7c39101 7670
97a5e98c 7671 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 7672 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7673#ifdef CONFIG_X86
97a5e98c 7674 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 7675#endif
28e13446
SC		 7676 driver_support |= ENABLE_UNIT_ATTN;
7677 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 7678}
7679
3d0eab67
SC		 7680/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7681 * in a prefetch beyond physical memory.
7682 */
7683static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7684{
7685 u32 dma_prefetch;
7686
7687 if (h->board_id != 0x3225103C)
7688 return;
7689 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7690 dma_prefetch |= 0x8000;
7691 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7692}
7693
c706a795 7694static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 7695{
7696 int i;
7697 u32 doorbell_value;
7698 unsigned long flags;
7699 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 7700 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 7701 spin_lock_irqsave(&h->lock, flags);
7702 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7703 spin_unlock_irqrestore(&h->lock, flags);
7704 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 7705 goto done;
76438d08 7706 /* delay and try again */
007e7aa9 7707 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 7708 }
c706a795
RE		 7709 return -ENODEV;
7710done:
7711 return 0;
76438d08
SC		 7712}
7713
c706a795 7714static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 7715{
7716 int i;
6eaf46fd
SC		 7717 u32 doorbell_value;
7718 unsigned long flags;
eb6b2ae9
SC		 7719
7720 /* under certain very rare conditions, this can take awhile.
7721 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7722 * as we enter this code.)
7723 */
007e7aa9 7724 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 7725 if (h->remove_in_progress)
7726 goto done;
6eaf46fd
SC		 7727 spin_lock_irqsave(&h->lock, flags);
7728 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7729 spin_unlock_irqrestore(&h->lock, flags);
382be668 7730 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 7731 goto done;
eb6b2ae9 7732 /* delay and try again */
007e7aa9 7733 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 7734 }
c706a795
RE		 7735 return -ENODEV;
7736done:
7737 return 0;
3f4336f3
SC		 7738}
7739
c706a795 7740/* return -ENODEV or other reason on error, 0 on success */
6f039790 7741static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 7742{
7743 u32 trans_support;
7744
7745 trans_support = readl(&(h->cfgtable->TransportSupport));
7746 if (!(trans_support & SIMPLE_MODE))
7747 return -ENOTSUPP;
7748
7749 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 7750
3f4336f3
SC		 7751 /* Update the field, and then ring the doorbell */
7752 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 7753 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 7754 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7755 if (hpsa_wait_for_mode_change_ack(h))
7756 goto error;
eb6b2ae9 7757 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 7758 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7759 goto error;
960a30e7 7760 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 7761 return 0;
283b4a9b 7762error:
050f7147 7763 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 7764 return -ENODEV;
eb6b2ae9
SC		 7765}
7766
195f2c65
RE		 7767/* free items allocated or mapped by hpsa_pci_init */
7768static void hpsa_free_pci_init(struct ctlr_info *h)
7769{
7770 hpsa_free_cfgtables(h); /* pci_init 4 */
7771 iounmap(h->vaddr); /* pci_init 3 */
105a3dbc 7772 h->vaddr = NULL;
195f2c65 7773 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
943a7021
RE		 7774 /*
7775 * call pci_disable_device before pci_release_regions per
7776 * Documentation/PCI/pci.txt
7777 */
195f2c65 7778 pci_disable_device(h->pdev); /* pci_init 1 */
943a7021 7779 pci_release_regions(h->pdev); /* pci_init 2 */
195f2c65
RE		 7780}
7781
7782/* several items must be freed later */
6f039790 7783static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 7784{
eb6b2ae9 7785 int prod_index, err;
edd16368 7786
e5c880d1
SC		 7787 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
7788 if (prod_index < 0)
60f923b9 7789 return prod_index;
e5c880d1
SC		 7790 h->product_name = products[prod_index].product_name;
7791 h->access = *(products[prod_index].access);
edd16368 7792
9b5c48c2
SC		 7793 h->needs_abort_tags_swizzled =
7794 ctlr_needs_abort_tags_swizzled(h->board_id);
7795
e5a44df8
MG		 7796 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7797 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7798
55c06c71 7799 err = pci_enable_device(h->pdev);
edd16368 7800 if (err) {
195f2c65 7801 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
943a7021 7802 pci_disable_device(h->pdev);
edd16368
SC		 7803 return err;
7804 }
7805
f79cfec6 7806 err = pci_request_regions(h->pdev, HPSA);
edd16368 7807 if (err) {
55c06c71 7808 dev_err(&h->pdev->dev,
195f2c65 7809 "failed to obtain PCI resources\n");
943a7021
RE		 7810 pci_disable_device(h->pdev);
7811 return err;
edd16368 7812 }
4fa604e1
RE		 7813
7814 pci_set_master(h->pdev);
7815
6b3f4c52 7816 hpsa_interrupt_mode(h);
12d2cd47 7817 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 7818 if (err)
195f2c65 7819 goto clean2; /* intmode+region, pci */
edd16368 7820 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 7821 if (!h->vaddr) {
195f2c65 7822 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 7823 err = -ENOMEM;
195f2c65 7824 goto clean2; /* intmode+region, pci */
204892e9 7825 }
fe5389c8 7826 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 7827 if (err)
195f2c65 7828 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 7829 err = hpsa_find_cfgtables(h);
7830 if (err)
195f2c65 7831 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 7832 hpsa_find_board_params(h);
edd16368 7833
76c46e49 7834 if (!hpsa_CISS_signature_present(h)) {
edd16368 7835 err = -ENODEV;
195f2c65 7836 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 7837 }
97a5e98c 7838 hpsa_set_driver_support_bits(h);
3d0eab67 7839 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 7840 err = hpsa_enter_simple_mode(h);
7841 if (err)
195f2c65 7842 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 7843 return 0;
7844
195f2c65
RE		 7845clean4: /* cfgtables, vaddr, intmode+region, pci */
7846 hpsa_free_cfgtables(h);
7847clean3: /* vaddr, intmode+region, pci */
7848 iounmap(h->vaddr);
105a3dbc 7849 h->vaddr = NULL;
195f2c65
RE		 7850clean2: /* intmode+region, pci */
7851 hpsa_disable_interrupt_mode(h);
943a7021
RE		 7852 /*
7853 * call pci_disable_device before pci_release_regions per
7854 * Documentation/PCI/pci.txt
7855 */
195f2c65 7856 pci_disable_device(h->pdev);
943a7021 7857 pci_release_regions(h->pdev);
edd16368
SC		 7858 return err;
7859}
7860
6f039790 7861static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 7862{
7863 int rc;
7864
7865#define HBA_INQUIRY_BYTE_COUNT 64
7866 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7867 if (!h->hba_inquiry_data)
7868 return;
7869 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7870 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7871 if (rc != 0) {
7872 kfree(h->hba_inquiry_data);
7873 h->hba_inquiry_data = NULL;
7874 }
7875}
7876
6b6c1cd7 7877static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 7878{
1df8552a 7879 int rc, i;
3b747298 7880 void __iomem *vaddr;
4c2a8c40
SC		 7881
7882 if (!reset_devices)
7883 return 0;
7884
132aa220
TH		 7885 /* kdump kernel is loading, we don't know in which state is
7886 * the pci interface. The dev->enable_cnt is equal zero
7887 * so we call enable+disable, wait a while and switch it on.
7888 */
7889 rc = pci_enable_device(pdev);
7890 if (rc) {
7891 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7892 return -ENODEV;
7893 }
7894 pci_disable_device(pdev);
7895 msleep(260); /* a randomly chosen number */
7896 rc = pci_enable_device(pdev);
7897 if (rc) {
7898 dev_warn(&pdev->dev, "failed to enable device.\n");
7899 return -ENODEV;
7900 }
4fa604e1 7901
859c75ab 7902 pci_set_master(pdev);
4fa604e1 7903
3b747298
TH		 7904 vaddr = pci_ioremap_bar(pdev, 0);
7905 if (vaddr == NULL) {
7906 rc = -ENOMEM;
7907 goto out_disable;
7908 }
7909 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
7910 iounmap(vaddr);
7911
1df8552a 7912 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 7913 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 7914
1df8552a
SC		 7915 /* -ENOTSUPP here means we cannot reset the controller
7916 * but it's already (and still) up and running in
18867659
SC		 7917 * "performant mode". Or, it might be 640x, which can't reset
7918 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 7919 */
adf1b3a3 7920 if (rc)
132aa220 7921 goto out_disable;
4c2a8c40
SC		 7922
7923 /* Now try to get the controller to respond to a no-op */
1ba66c9c 7924 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 7925 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
7926 if (hpsa_noop(pdev) == 0)
7927 break;
7928 else
7929 dev_warn(&pdev->dev, "no-op failed%s\n",
7930 (i < 11 ? "; re-trying" : ""));
7931 }
132aa220
TH		 7932
7933out_disable:
7934
7935 pci_disable_device(pdev);
7936 return rc;
4c2a8c40
SC		 7937}
7938
1fb7c98a
RE		 7939static void hpsa_free_cmd_pool(struct ctlr_info *h)
7940{
7941 kfree(h->cmd_pool_bits);
105a3dbc
RE		 7942 h->cmd_pool_bits = NULL;
7943 if (h->cmd_pool) {
1fb7c98a
RE		 7944 pci_free_consistent(h->pdev,
7945 h->nr_cmds * sizeof(struct CommandList),
7946 h->cmd_pool,
7947 h->cmd_pool_dhandle);
105a3dbc
RE		 7948 h->cmd_pool = NULL;
7949 h->cmd_pool_dhandle = 0;
7950 }
7951 if (h->errinfo_pool) {
1fb7c98a
RE		 7952 pci_free_consistent(h->pdev,
7953 h->nr_cmds * sizeof(struct ErrorInfo),
7954 h->errinfo_pool,
7955 h->errinfo_pool_dhandle);
105a3dbc
RE		 7956 h->errinfo_pool = NULL;
7957 h->errinfo_pool_dhandle = 0;
7958 }
1fb7c98a
RE		 7959}
7960
d37ffbe4 7961static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 7962{
7963 h->cmd_pool_bits = kzalloc(
7964 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
7965 sizeof(unsigned long), GFP_KERNEL);
7966 h->cmd_pool = pci_alloc_consistent(h->pdev,
7967 h->nr_cmds * sizeof(*h->cmd_pool),
7968 &(h->cmd_pool_dhandle));
7969 h->errinfo_pool = pci_alloc_consistent(h->pdev,
7970 h->nr_cmds * sizeof(*h->errinfo_pool),
7971 &(h->errinfo_pool_dhandle));
7972 if ((h->cmd_pool_bits == NULL)
7973 || (h->cmd_pool == NULL)
7974 || (h->errinfo_pool == NULL)) {
7975 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 7976 goto clean_up;
2e9d1b36 7977 }
360c73bd 7978 hpsa_preinitialize_commands(h);
2e9d1b36 7979 return 0;
2c143342
RE		 7980clean_up:
7981 hpsa_free_cmd_pool(h);
7982 return -ENOMEM;
2e9d1b36
SC		 7983}
7984
41b3cf08
SC		 7985static void hpsa_irq_affinity_hints(struct ctlr_info *h)
7986{
ec429952 7987 int i, cpu;
41b3cf08
SC		 7988
7989 cpu = cpumask_first(cpu_online_mask);
7990 for (i = 0; i < h->msix_vector; i++) {
ec429952 7991 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 7992 cpu = cpumask_next(cpu, cpu_online_mask);
7993 }
7994}
7995
ec501a18
RE		 7996/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
7997static void hpsa_free_irqs(struct ctlr_info *h)
7998{
7999 int i;
8000
8001 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
8002 /* Single reply queue, only one irq to free */
8003 i = h->intr_mode;
8004 irq_set_affinity_hint(h->intr[i], NULL);
8005 free_irq(h->intr[i], &h->q[i]);
105a3dbc 8006 h->q[i] = 0;
ec501a18
RE		 8007 return;
8008 }
8009
8010 for (i = 0; i < h->msix_vector; i++) {
8011 irq_set_affinity_hint(h->intr[i], NULL);
8012 free_irq(h->intr[i], &h->q[i]);
105a3dbc 8013 h->q[i] = 0;
ec501a18 8014 }
a4e17fc1
RE		 8015 for (; i < MAX_REPLY_QUEUES; i++)
8016 h->q[i] = 0;
ec501a18
RE		 8017}
8018
9ee61794
RE		 8019/* returns 0 on success; cleans up and returns -Enn on error */
8020static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 8021 irqreturn_t (*msixhandler)(int, void *),
8022 irqreturn_t (*intxhandler)(int, void *))
8023{
254f796b 8024 int rc, i;
0ae01a32 8025
254f796b
MG		 8026 /*
8027 * initialize h->q[x] = x so that interrupt handlers know which
8028 * queue to process.
8029 */
8030 for (i = 0; i < MAX_REPLY_QUEUES; i++)
8031 h->q[i] = (u8) i;
8032
eee0f03a 8033 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 8034 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 8035 for (i = 0; i < h->msix_vector; i++) {
8b47004a 8036 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
254f796b 8037 rc = request_irq(h->intr[i], msixhandler,
8b47004a 8038 0, h->intrname[i],
254f796b 8039 &h->q[i]);
a4e17fc1
RE		 8040 if (rc) {
8041 int j;
8042
8043 dev_err(&h->pdev->dev,
8044 "failed to get irq %d for %s\n",
8045 h->intr[i], h->devname);
8046 for (j = 0; j < i; j++) {
8047 free_irq(h->intr[j], &h->q[j]);
8048 h->q[j] = 0;
8049 }
8050 for (; j < MAX_REPLY_QUEUES; j++)
8051 h->q[j] = 0;
8052 return rc;
8053 }
8054 }
41b3cf08 8055 hpsa_irq_affinity_hints(h);
254f796b
MG		 8056 } else {
8057 /* Use single reply pool */
eee0f03a 8058 if (h->msix_vector > 0 || h->msi_vector) {
8b47004a
RE		 8059 if (h->msix_vector)
8060 sprintf(h->intrname[h->intr_mode],
8061 "%s-msix", h->devname);
8062 else
8063 sprintf(h->intrname[h->intr_mode],
8064 "%s-msi", h->devname);
254f796b 8065 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 8066 msixhandler, 0,
8067 h->intrname[h->intr_mode],
254f796b
MG		 8068 &h->q[h->intr_mode]);
8069 } else {
8b47004a
RE		 8070 sprintf(h->intrname[h->intr_mode],
8071 "%s-intx", h->devname);
254f796b 8072 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 8073 intxhandler, IRQF_SHARED,
8074 h->intrname[h->intr_mode],
254f796b
MG		 8075 &h->q[h->intr_mode]);
8076 }
105a3dbc 8077 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
254f796b 8078 }
0ae01a32 8079 if (rc) {
195f2c65 8080 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 8081 h->intr[h->intr_mode], h->devname);
195f2c65 8082 hpsa_free_irqs(h);
0ae01a32
SC		 8083 return -ENODEV;
8084 }
8085 return 0;
8086}
8087
6f039790 8088static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8 8089{
39c53f55 8090 int rc;
bf43caf3 8091 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
64670ac8
SC		 8092
8093 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
39c53f55
RE		 8094 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
8095 if (rc) {
64670ac8 8096 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
39c53f55 8097 return rc;
64670ac8
SC		 8098 }
8099
8100 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
39c53f55
RE		 8101 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
8102 if (rc) {
64670ac8
SC		 8103 dev_warn(&h->pdev->dev, "Board failed to become ready "
8104 "after soft reset.\n");
39c53f55 8105 return rc;
64670ac8
SC		 8106 }
8107
8108 return 0;
8109}
8110
072b0518
SC		 8111static void hpsa_free_reply_queues(struct ctlr_info *h)
8112{
8113 int i;
8114
8115 for (i = 0; i < h->nreply_queues; i++) {
8116 if (!h->reply_queue[i].head)
8117 continue;
1fb7c98a
RE		 8118 pci_free_consistent(h->pdev,
8119 h->reply_queue_size,
8120 h->reply_queue[i].head,
8121 h->reply_queue[i].busaddr);
072b0518
SC		 8122 h->reply_queue[i].head = NULL;
8123 h->reply_queue[i].busaddr = 0;
8124 }
105a3dbc 8125 h->reply_queue_size = 0;
072b0518
SC		 8126}
8127
0097f0f4
SC		 8128static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
8129{
105a3dbc
RE		 8130 hpsa_free_performant_mode(h); /* init_one 7 */
8131 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8132 hpsa_free_cmd_pool(h); /* init_one 5 */
8133 hpsa_free_irqs(h); /* init_one 4 */
2946e82b
RE		 8134 scsi_host_put(h->scsi_host); /* init_one 3 */
8135 h->scsi_host = NULL; /* init_one 3 */
8136 hpsa_free_pci_init(h); /* init_one 2_5 */
9ecd953a
RE		 8137 free_percpu(h->lockup_detected); /* init_one 2 */
8138 h->lockup_detected = NULL; /* init_one 2 */
8139 if (h->resubmit_wq) {
8140 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
8141 h->resubmit_wq = NULL;
8142 }
8143 if (h->rescan_ctlr_wq) {
8144 destroy_workqueue(h->rescan_ctlr_wq);
8145 h->rescan_ctlr_wq = NULL;
8146 }
105a3dbc 8147 kfree(h); /* init_one 1 */
64670ac8
SC		 8148}
8149
a0c12413 8150/* Called when controller lockup detected. */
f2405db8 8151static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 8152{
281a7fd0
WS		 8153 int i, refcount;
8154 struct CommandList *c;
25163bd5 8155 int failcount = 0;
a0c12413 8156
080ef1cc 8157 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 8158 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8159 c = h->cmd_pool + i;
281a7fd0
WS		 8160 refcount = atomic_inc_return(&c->refcount);
8161 if (refcount > 1) {
25163bd5 8162 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 8163 finish_cmd(c);
433b5f4d 8164 atomic_dec(&h->commands_outstanding);
25163bd5 8165 failcount++;
281a7fd0
WS		 8166 }
8167 cmd_free(h, c);
a0c12413 8168 }
25163bd5
WS		 8169 dev_warn(&h->pdev->dev,
8170 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 8171}
8172
094963da
SC		 8173static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
8174{
c8ed0010 8175 int cpu;
094963da 8176
c8ed0010 8177 for_each_online_cpu(cpu) {
094963da
SC		 8178 u32 *lockup_detected;
8179 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
8180 *lockup_detected = value;
094963da
SC		 8181 }
8182 wmb(); /* be sure the per-cpu variables are out to memory */
8183}
8184
a0c12413
SC		 8185static void controller_lockup_detected(struct ctlr_info *h)
8186{
8187 unsigned long flags;
094963da 8188 u32 lockup_detected;
a0c12413 8189
a0c12413
SC		 8190 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8191 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 8192 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
8193 if (!lockup_detected) {
8194 /* no heartbeat, but controller gave us a zero. */
8195 dev_warn(&h->pdev->dev,
25163bd5
WS		 8196 "lockup detected after %d but scratchpad register is zero\n",
8197 h->heartbeat_sample_interval / HZ);
094963da
SC		 8198 lockup_detected = 0xffffffff;
8199 }
8200 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 8201 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 8202 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
8203 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 8204 pci_disable_device(h->pdev);
f2405db8 8205 fail_all_outstanding_cmds(h);
a0c12413
SC		 8206}
8207
25163bd5 8208static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 8209{
8210 u64 now;
8211 u32 heartbeat;
8212 unsigned long flags;
8213
a0c12413
SC		 8214 now = get_jiffies_64();
8215 /* If we've received an interrupt recently, we're ok. */
8216 if (time_after64(h->last_intr_timestamp +
e85c5974 8217 (h->heartbeat_sample_interval), now))
25163bd5 8218 return false;
a0c12413
SC		 8219
8220 /*
8221 * If we've already checked the heartbeat recently, we're ok.
8222 * This could happen if someone sends us a signal. We
8223 * otherwise don't care about signals in this thread.
8224 */
8225 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 8226 (h->heartbeat_sample_interval), now))
25163bd5 8227 return false;
a0c12413
SC		 8228
8229 /* If heartbeat has not changed since we last looked, we're not ok. */
8230 spin_lock_irqsave(&h->lock, flags);
8231 heartbeat = readl(&h->cfgtable->HeartBeat);
8232 spin_unlock_irqrestore(&h->lock, flags);
8233 if (h->last_heartbeat == heartbeat) {
8234 controller_lockup_detected(h);
25163bd5 8235 return true;
a0c12413
SC		 8236 }
8237
8238 /* We're ok. */
8239 h->last_heartbeat = heartbeat;
8240 h->last_heartbeat_timestamp = now;
25163bd5 8241 return false;
a0c12413
SC		 8242}
8243
9846590e 8244static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 8245{
8246 int i;
8247 char *event_type;
8248
e4aa3e6a
SC		 8249 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
8250 return;
8251
76438d08 8252 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 8253 if ((h->transMethod & (CFGTBL_Trans_io_accel1
8254 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 8255 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
8256 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
8257
8258 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
8259 event_type = "state change";
8260 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
8261 event_type = "configuration change";
8262 /* Stop sending new RAID offload reqs via the IO accelerator */
8263 scsi_block_requests(h->scsi_host);
8264 for (i = 0; i < h->ndevices; i++)
8265 h->dev[i]->offload_enabled = 0;
23100dd9 8266 hpsa_drain_accel_commands(h);
76438d08
SC		 8267 /* Set 'accelerator path config change' bit */
8268 dev_warn(&h->pdev->dev,
8269 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
8270 h->events, event_type);
8271 writel(h->events, &(h->cfgtable->clear_event_notify));
8272 /* Set the "clear event notify field update" bit 6 */
8273 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
8274 /* Wait until ctlr clears 'clear event notify field', bit 6 */
8275 hpsa_wait_for_clear_event_notify_ack(h);
8276 scsi_unblock_requests(h->scsi_host);
8277 } else {
8278 /* Acknowledge controller notification events. */
8279 writel(h->events, &(h->cfgtable->clear_event_notify));
8280 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
8281 hpsa_wait_for_clear_event_notify_ack(h);
8282#if 0
8283 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
8284 hpsa_wait_for_mode_change_ack(h);
8285#endif
8286 }
9846590e 8287 return;
76438d08
SC		 8288}
8289
8290/* Check a register on the controller to see if there are configuration
8291 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 8292 * we should rescan the controller for devices.
8293 * Also check flag for driver-initiated rescan.
76438d08 8294 */
9846590e 8295static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 8296{
853633e8
DB		 8297 if (h->drv_req_rescan) {
8298 h->drv_req_rescan = 0;
8299 return 1;
8300 }
8301
76438d08 8302 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 8303 return 0;
76438d08
SC		 8304
8305 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 8306 return h->events & RESCAN_REQUIRED_EVENT_BITS;
8307}
76438d08 8308
9846590e
SC		 8309/*
8310 * Check if any of the offline devices have become ready
8311 */
8312static int hpsa_offline_devices_ready(struct ctlr_info *h)
8313{
8314 unsigned long flags;
8315 struct offline_device_entry *d;
8316 struct list_head *this, *tmp;
8317
8318 spin_lock_irqsave(&h->offline_device_lock, flags);
8319 list_for_each_safe(this, tmp, &h->offline_device_list) {
8320 d = list_entry(this, struct offline_device_entry,
8321 offline_list);
8322 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 8323 if (!hpsa_volume_offline(h, d->scsi3addr)) {
8324 spin_lock_irqsave(&h->offline_device_lock, flags);
8325 list_del(&d->offline_list);
8326 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 8327 return 1;
d1fea47c 8328 }
9846590e
SC		 8329 spin_lock_irqsave(&h->offline_device_lock, flags);
8330 }
8331 spin_unlock_irqrestore(&h->offline_device_lock, flags);
8332 return 0;
76438d08
SC		 8333}
8334
34592254
ST		 8335static int hpsa_luns_changed(struct ctlr_info *h)
8336{
8337 int rc = 1; /* assume there are changes */
8338 struct ReportLUNdata *logdev = NULL;
8339
8340 /* if we can't find out if lun data has changed,
8341 * assume that it has.
8342 */
8343
8344 if (!h->lastlogicals)
8345 goto out;
8346
8347 logdev = kzalloc(sizeof(*logdev), GFP_KERNEL);
8348 if (!logdev) {
8349 dev_warn(&h->pdev->dev,
8350 "Out of memory, can't track lun changes.\n");
8351 goto out;
8352 }
8353 if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) {
8354 dev_warn(&h->pdev->dev,
8355 "report luns failed, can't track lun changes.\n");
8356 goto out;
8357 }
8358 if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) {
8359 dev_info(&h->pdev->dev,
8360 "Lun changes detected.\n");
8361 memcpy(h->lastlogicals, logdev, sizeof(*logdev));
8362 goto out;
8363 } else
8364 rc = 0; /* no changes detected. */
8365out:
8366 kfree(logdev);
8367 return rc;
8368}
8369
6636e7f4 8370static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 8371{
8372 unsigned long flags;
8a98db73 8373 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 8374 struct ctlr_info, rescan_ctlr_work);
8375
8376
8377 if (h->remove_in_progress)
8a98db73 8378 return;
9846590e
SC		 8379
8380 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
8381 scsi_host_get(h->scsi_host);
9846590e
SC		 8382 hpsa_ack_ctlr_events(h);
8383 hpsa_scan_start(h->scsi_host);
8384 scsi_host_put(h->scsi_host);
34592254 8385 } else if (h->discovery_polling) {
c2adae44 8386 hpsa_disable_rld_caching(h);
34592254
ST		 8387 if (hpsa_luns_changed(h)) {
8388 struct Scsi_Host *sh = NULL;
8389
8390 dev_info(&h->pdev->dev,
8391 "driver discovery polling rescan.\n");
8392 sh = scsi_host_get(h->scsi_host);
8393 if (sh != NULL) {
8394 hpsa_scan_start(sh);
8395 scsi_host_put(sh);
8396 }
8397 }
9846590e 8398 }
8a98db73 8399 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 8400 if (!h->remove_in_progress)
8401 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8402 h->heartbeat_sample_interval);
8403 spin_unlock_irqrestore(&h->lock, flags);
8404}
8405
8406static void hpsa_monitor_ctlr_worker(struct work_struct *work)
8407{
8408 unsigned long flags;
8409 struct ctlr_info *h = container_of(to_delayed_work(work),
8410 struct ctlr_info, monitor_ctlr_work);
8411
8412 detect_controller_lockup(h);
8413 if (lockup_detected(h))
a0c12413 8414 return;
6636e7f4
DB		 8415
8416 spin_lock_irqsave(&h->lock, flags);
8417 if (!h->remove_in_progress)
8418 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 8419 h->heartbeat_sample_interval);
8420 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 8421}
8422
6636e7f4
DB		 8423static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
8424 char *name)
8425{
8426 struct workqueue_struct *wq = NULL;
6636e7f4 8427
397ea9cb 8428 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 8429 if (!wq)
8430 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
8431
8432 return wq;
8433}
8434
6f039790 8435static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 8436{
4c2a8c40 8437 int dac, rc;
edd16368 8438 struct ctlr_info *h;
64670ac8
SC		 8439 int try_soft_reset = 0;
8440 unsigned long flags;
6b6c1cd7 8441 u32 board_id;
edd16368
SC		 8442
8443 if (number_of_controllers == 0)
8444 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 8445
6b6c1cd7
TH		 8446 rc = hpsa_lookup_board_id(pdev, &board_id);
8447 if (rc < 0) {
8448 dev_warn(&pdev->dev, "Board ID not found\n");
8449 return rc;
8450 }
8451
8452 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 8453 if (rc) {
8454 if (rc != -ENOTSUPP)
8455 return rc;
8456 /* If the reset fails in a particular way (it has no way to do
8457 * a proper hard reset, so returns -ENOTSUPP) we can try to do
8458 * a soft reset once we get the controller configured up to the
8459 * point that it can accept a command.
8460 */
8461 try_soft_reset = 1;
8462 rc = 0;
8463 }
8464
8465reinit_after_soft_reset:
edd16368 8466
303932fd
DB		 8467 /* Command structures must be aligned on a 32-byte boundary because
8468 * the 5 lower bits of the address are used by the hardware. and by
8469 * the driver. See comments in hpsa.h for more info.
8470 */
303932fd 8471 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368 8472 h = kzalloc(sizeof(*h), GFP_KERNEL);
105a3dbc
RE		 8473 if (!h) {
8474 dev_err(&pdev->dev, "Failed to allocate controller head\n");
ecd9aad4 8475 return -ENOMEM;
105a3dbc 8476 }
edd16368 8477
55c06c71 8478 h->pdev = pdev;
105a3dbc 8479
a9a3a273 8480 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 8481 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 8482 spin_lock_init(&h->lock);
9846590e 8483 spin_lock_init(&h->offline_device_lock);
6eaf46fd 8484 spin_lock_init(&h->scan_lock);
34f0c627 8485 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 8486 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da
SC		 8487
8488 /* Allocate and clear per-cpu variable lockup_detected */
8489 h->lockup_detected = alloc_percpu(u32);
2a5ac326 8490 if (!h->lockup_detected) {
105a3dbc 8491 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
2a5ac326 8492 rc = -ENOMEM;
2efa5929 8493 goto clean1; /* aer/h */
2a5ac326 8494 }
094963da
SC		 8495 set_lockup_detected_for_all_cpus(h, 0);
8496
55c06c71 8497 rc = hpsa_pci_init(h);
105a3dbc 8498 if (rc)
2946e82b
RE		 8499 goto clean2; /* lu, aer/h */
8500
8501 /* relies on h-> settings made by hpsa_pci_init, including
8502 * interrupt_mode h->intr */
8503 rc = hpsa_scsi_host_alloc(h);
8504 if (rc)
8505 goto clean2_5; /* pci, lu, aer/h */
edd16368 8506
2946e82b 8507 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
edd16368
SC		 8508 h->ctlr = number_of_controllers;
8509 number_of_controllers++;
edd16368
SC		 8510
8511 /* configure PCI DMA stuff */
ecd9aad4
SC		 8512 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
8513 if (rc == 0) {
edd16368 8514 dac = 1;
ecd9aad4
SC		 8515 } else {
8516 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8517 if (rc == 0) {
8518 dac = 0;
8519 } else {
8520 dev_err(&pdev->dev, "no suitable DMA available\n");
2946e82b 8521 goto clean3; /* shost, pci, lu, aer/h */
ecd9aad4 8522 }
edd16368
SC		 8523 }
8524
8525 /* make sure the board interrupts are off */
8526 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 8527
105a3dbc
RE		 8528 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
8529 if (rc)
2946e82b 8530 goto clean3; /* shost, pci, lu, aer/h */
d37ffbe4 8531 rc = hpsa_alloc_cmd_pool(h);
8947fd10 8532 if (rc)
2946e82b 8533 goto clean4; /* irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8534 rc = hpsa_alloc_sg_chain_blocks(h);
8535 if (rc)
2946e82b 8536 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
a08a8471 8537 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 8538 init_waitqueue_head(&h->abort_cmd_wait_queue);
d604f533
WS		 8539 init_waitqueue_head(&h->event_sync_wait_queue);
8540 mutex_init(&h->reset_mutex);
a08a8471 8541 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 8542
8543 pci_set_drvdata(pdev, h);
9a41338e 8544 h->ndevices = 0;
2946e82b 8545
9a41338e 8546 spin_lock_init(&h->devlock);
105a3dbc
RE		 8547 rc = hpsa_put_ctlr_into_performant_mode(h);
8548 if (rc)
2946e82b
RE		 8549 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8550
8551 /* hook into SCSI subsystem */
8552 rc = hpsa_scsi_add_host(h);
8553 if (rc)
8554 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
2efa5929
RE		 8555
8556 /* create the resubmit workqueue */
8557 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8558 if (!h->rescan_ctlr_wq) {
8559 rc = -ENOMEM;
8560 goto clean7;
8561 }
8562
8563 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8564 if (!h->resubmit_wq) {
8565 rc = -ENOMEM;
8566 goto clean7; /* aer/h */
8567 }
64670ac8 8568
105a3dbc
RE		 8569 /*
8570 * At this point, the controller is ready to take commands.
64670ac8
SC		 8571 * Now, if reset_devices and the hard reset didn't work, try
8572 * the soft reset and see if that works.
8573 */
8574 if (try_soft_reset) {
8575
8576 /* This is kind of gross. We may or may not get a completion
8577 * from the soft reset command, and if we do, then the value
8578 * from the fifo may or may not be valid. So, we wait 10 secs
8579 * after the reset throwing away any completions we get during
8580 * that time. Unregister the interrupt handler and register
8581 * fake ones to scoop up any residual completions.
8582 */
8583 spin_lock_irqsave(&h->lock, flags);
8584 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8585 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 8586 hpsa_free_irqs(h);
9ee61794 8587 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 8588 hpsa_intx_discard_completions);
8589 if (rc) {
9ee61794
RE		 8590 dev_warn(&h->pdev->dev,
8591 "Failed to request_irq after soft reset.\n");
d498757c 8592 /*
b2ef480c
RE		 8593 * cannot goto clean7 or free_irqs will be called
8594 * again. Instead, do its work
8595 */
8596 hpsa_free_performant_mode(h); /* clean7 */
8597 hpsa_free_sg_chain_blocks(h); /* clean6 */
8598 hpsa_free_cmd_pool(h); /* clean5 */
8599 /*
8600 * skip hpsa_free_irqs(h) clean4 since that
8601 * was just called before request_irqs failed
d498757c
RE		 8602 */
8603 goto clean3;
64670ac8
SC		 8604 }
8605
8606 rc = hpsa_kdump_soft_reset(h);
8607 if (rc)
8608 /* Neither hard nor soft reset worked, we're hosed. */
7ef7323f 8609 goto clean7;
64670ac8
SC		 8610
8611 dev_info(&h->pdev->dev, "Board READY.\n");
8612 dev_info(&h->pdev->dev,
8613 "Waiting for stale completions to drain.\n");
8614 h->access.set_intr_mask(h, HPSA_INTR_ON);
8615 msleep(10000);
8616 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8617
8618 rc = controller_reset_failed(h->cfgtable);
8619 if (rc)
8620 dev_info(&h->pdev->dev,
8621 "Soft reset appears to have failed.\n");
8622
8623 /* since the controller's reset, we have to go back and re-init
8624 * everything. Easiest to just forget what we've done and do it
8625 * all over again.
8626 */
8627 hpsa_undo_allocations_after_kdump_soft_reset(h);
8628 try_soft_reset = 0;
8629 if (rc)
b2ef480c 8630 /* don't goto clean, we already unallocated */
64670ac8
SC		 8631 return -ENODEV;
8632
8633 goto reinit_after_soft_reset;
8634 }
edd16368 8635
105a3dbc
RE		 8636 /* Enable Accelerated IO path at driver layer */
8637 h->acciopath_status = 1;
34592254
ST		 8638 /* Disable discovery polling.*/
8639 h->discovery_polling = 0;
da0697bd 8640
e863d68e 8641
edd16368
SC		 8642 /* Turn the interrupts on so we can service requests */
8643 h->access.set_intr_mask(h, HPSA_INTR_ON);
8644
339b2b14 8645 hpsa_hba_inquiry(h);
8a98db73 8646
34592254
ST		 8647 h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL);
8648 if (!h->lastlogicals)
8649 dev_info(&h->pdev->dev,
8650 "Can't track change to report lun data\n");
8651
8a98db73
SC		 8652 /* Monitor the controller for firmware lockups */
8653 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8654 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8655 schedule_delayed_work(&h->monitor_ctlr_work,
8656 h->heartbeat_sample_interval);
6636e7f4
DB		 8657 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8658 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8659 h->heartbeat_sample_interval);
88bf6d62 8660 return 0;
edd16368 8661
2946e82b 8662clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8663 hpsa_free_performant_mode(h);
8664 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8665clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
33a2ffce 8666 hpsa_free_sg_chain_blocks(h);
2946e82b 8667clean5: /* cmd, irq, shost, pci, lu, aer/h */
2e9d1b36 8668 hpsa_free_cmd_pool(h);
2946e82b 8669clean4: /* irq, shost, pci, lu, aer/h */
ec501a18 8670 hpsa_free_irqs(h);
2946e82b
RE		 8671clean3: /* shost, pci, lu, aer/h */
8672 scsi_host_put(h->scsi_host);
8673 h->scsi_host = NULL;
8674clean2_5: /* pci, lu, aer/h */
195f2c65 8675 hpsa_free_pci_init(h);
2946e82b 8676clean2: /* lu, aer/h */
105a3dbc
RE		 8677 if (h->lockup_detected) {
8678 free_percpu(h->lockup_detected);
8679 h->lockup_detected = NULL;
8680 }
8681clean1: /* wq/aer/h */
8682 if (h->resubmit_wq) {
080ef1cc 8683 destroy_workqueue(h->resubmit_wq);
105a3dbc
RE		 8684 h->resubmit_wq = NULL;
8685 }
8686 if (h->rescan_ctlr_wq) {
6636e7f4 8687 destroy_workqueue(h->rescan_ctlr_wq);
105a3dbc
RE		 8688 h->rescan_ctlr_wq = NULL;
8689 }
edd16368 8690 kfree(h);
ecd9aad4 8691 return rc;
edd16368
SC		 8692}
8693
8694static void hpsa_flush_cache(struct ctlr_info *h)
8695{
8696 char *flush_buf;
8697 struct CommandList *c;
25163bd5 8698 int rc;
702890e3 8699
094963da 8700 if (unlikely(lockup_detected(h)))
702890e3 8701 return;
edd16368
SC		 8702 flush_buf = kzalloc(4, GFP_KERNEL);
8703 if (!flush_buf)
8704 return;
8705
45fcb86e 8706 c = cmd_alloc(h);
bf43caf3 8707
a2dac136
SC		 8708 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8709 RAID_CTLR_LUNID, TYPE_CMD)) {
8710 goto out;
8711 }
25163bd5
WS		 8712 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8713 PCI_DMA_TODEVICE, NO_TIMEOUT);
8714 if (rc)
8715 goto out;
edd16368 8716 if (c->err_info->CommandStatus != 0)
a2dac136 8717out:
edd16368
SC		 8718 dev_warn(&h->pdev->dev,
8719 "error flushing cache on controller\n");
45fcb86e 8720 cmd_free(h, c);
edd16368
SC		 8721 kfree(flush_buf);
8722}
8723
c2adae44
ST		 8724/* Make controller gather fresh report lun data each time we
8725 * send down a report luns request
8726 */
8727static void hpsa_disable_rld_caching(struct ctlr_info *h)
8728{
8729 u32 *options;
8730 struct CommandList *c;
8731 int rc;
8732
8733 /* Don't bother trying to set diag options if locked up */
8734 if (unlikely(h->lockup_detected))
8735 return;
8736
8737 options = kzalloc(sizeof(*options), GFP_KERNEL);
8738 if (!options) {
8739 dev_err(&h->pdev->dev,
8740 "Error: failed to disable rld caching, during alloc.\n");
8741 return;
8742 }
8743
8744 c = cmd_alloc(h);
8745
8746 /* first, get the current diag options settings */
8747 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
8748 RAID_CTLR_LUNID, TYPE_CMD))
8749 goto errout;
8750
8751 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8752 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
8753 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8754 goto errout;
8755
8756 /* Now, set the bit for disabling the RLD caching */
8757 *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING;
8758
8759 if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0,
8760 RAID_CTLR_LUNID, TYPE_CMD))
8761 goto errout;
8762
8763 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8764 PCI_DMA_TODEVICE, NO_TIMEOUT);
8765 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8766 goto errout;
8767
8768 /* Now verify that it got set: */
8769 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
8770 RAID_CTLR_LUNID, TYPE_CMD))
8771 goto errout;
8772
8773 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8774 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
8775 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8776 goto errout;
8777
d8a080c3 8778 if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING)
c2adae44
ST		 8779 goto out;
8780
8781errout:
8782 dev_err(&h->pdev->dev,
8783 "Error: failed to disable report lun data caching.\n");
8784out:
8785 cmd_free(h, c);
8786 kfree(options);
8787}
8788
edd16368
SC		 8789static void hpsa_shutdown(struct pci_dev *pdev)
8790{
8791 struct ctlr_info *h;
8792
8793 h = pci_get_drvdata(pdev);
8794 /* Turn board interrupts off and send the flush cache command
8795 * sendcmd will turn off interrupt, and send the flush...
8796 * To write all data in the battery backed cache to disks
8797 */
8798 hpsa_flush_cache(h);
8799 h->access.set_intr_mask(h, HPSA_INTR_OFF);
105a3dbc 8800 hpsa_free_irqs(h); /* init_one 4 */
cc64c817 8801 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 8802}
8803
6f039790 8804static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 8805{
8806 int i;
8807
105a3dbc 8808 for (i = 0; i < h->ndevices; i++) {
55e14e76 8809 kfree(h->dev[i]);
105a3dbc
RE		 8810 h->dev[i] = NULL;
8811 }
55e14e76
SC		 8812}
8813
6f039790 8814static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 8815{
8816 struct ctlr_info *h;
8a98db73 8817 unsigned long flags;
edd16368
SC		 8818
8819 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 8820 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 8821 return;
8822 }
8823 h = pci_get_drvdata(pdev);
8a98db73
SC		 8824
8825 /* Get rid of any controller monitoring work items */
8826 spin_lock_irqsave(&h->lock, flags);
8827 h->remove_in_progress = 1;
8a98db73 8828 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 8829 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8830 cancel_delayed_work_sync(&h->rescan_ctlr_work);
8831 destroy_workqueue(h->rescan_ctlr_wq);
8832 destroy_workqueue(h->resubmit_wq);
cc64c817 8833
2d041306
DB		 8834 /*
8835 * Call before disabling interrupts.
8836 * scsi_remove_host can trigger I/O operations especially
8837 * when multipath is enabled. There can be SYNCHRONIZE CACHE
8838 * operations which cannot complete and will hang the system.
8839 */
8840 if (h->scsi_host)
8841 scsi_remove_host(h->scsi_host); /* init_one 8 */
105a3dbc 8842 /* includes hpsa_free_irqs - init_one 4 */
195f2c65 8843 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 8844 hpsa_shutdown(pdev);
cc64c817 8845
105a3dbc
RE		 8846 hpsa_free_device_info(h); /* scan */
8847
2946e82b
RE		 8848 kfree(h->hba_inquiry_data); /* init_one 10 */
8849 h->hba_inquiry_data = NULL; /* init_one 10 */
2946e82b 8850 hpsa_free_ioaccel2_sg_chain_blocks(h);
105a3dbc
RE		 8851 hpsa_free_performant_mode(h); /* init_one 7 */
8852 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8853 hpsa_free_cmd_pool(h); /* init_one 5 */
34592254 8854 kfree(h->lastlogicals);
105a3dbc
RE		 8855
8856 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
195f2c65 8857
2946e82b
RE		 8858 scsi_host_put(h->scsi_host); /* init_one 3 */
8859 h->scsi_host = NULL; /* init_one 3 */
8860
195f2c65 8861 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
2946e82b 8862 hpsa_free_pci_init(h); /* init_one 2.5 */
195f2c65 8863
105a3dbc
RE		 8864 free_percpu(h->lockup_detected); /* init_one 2 */
8865 h->lockup_detected = NULL; /* init_one 2 */
8866 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
d04e62b9
KB		 8867
8868 hpsa_delete_sas_host(h);
8869
105a3dbc 8870 kfree(h); /* init_one 1 */
edd16368
SC		 8871}
8872
8873static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8874 __attribute__((unused)) pm_message_t state)
8875{
8876 return -ENOSYS;
8877}
8878
8879static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8880{
8881 return -ENOSYS;
8882}
8883
8884static struct pci_driver hpsa_pci_driver = {
f79cfec6 8885 .name = HPSA,
edd16368 8886 .probe = hpsa_init_one,
6f039790 8887 .remove = hpsa_remove_one,
edd16368
SC		 8888 .id_table = hpsa_pci_device_id, /* id_table */
8889 .shutdown = hpsa_shutdown,
8890 .suspend = hpsa_suspend,
8891 .resume = hpsa_resume,
8892};
8893
303932fd
DB		 8894/* Fill in bucket_map[], given nsgs (the max number of
8895 * scatter gather elements supported) and bucket[],
8896 * which is an array of 8 integers. The bucket[] array
8897 * contains 8 different DMA transfer sizes (in 16
8898 * byte increments) which the controller uses to fetch
8899 * commands. This function fills in bucket_map[], which
8900 * maps a given number of scatter gather elements to one of
8901 * the 8 DMA transfer sizes. The point of it is to allow the
8902 * controller to only do as much DMA as needed to fetch the
8903 * command, with the DMA transfer size encoded in the lower
8904 * bits of the command address.
8905 */
8906static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 8907 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 8908{
8909 int i, j, b, size;
8910
303932fd
DB		 8911 /* Note, bucket_map must have nsgs+1 entries. */
8912 for (i = 0; i <= nsgs; i++) {
8913 /* Compute size of a command with i SG entries */
e1f7de0c 8914 size = i + min_blocks;
303932fd
DB		 8915 b = num_buckets; /* Assume the biggest bucket */
8916 /* Find the bucket that is just big enough */
e1f7de0c 8917 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 8918 if (bucket[j] >= size) {
8919 b = j;
8920 break;
8921 }
8922 }
8923 /* for a command with i SG entries, use bucket b. */
8924 bucket_map[i] = b;
8925 }
8926}
8927
105a3dbc
RE		 8928/*
8929 * return -ENODEV on err, 0 on success (or no action)
8930 * allocates numerous items that must be freed later
8931 */
c706a795 8932static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 8933{
6c311b57
SC		 8934 int i;
8935 unsigned long register_value;
e1f7de0c
MG		 8936 unsigned long transMethod = CFGTBL_Trans_Performant |
8937 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 8938 CFGTBL_Trans_enable_directed_msix |
8939 (trans_support & (CFGTBL_Trans_io_accel1 |
8940 CFGTBL_Trans_io_accel2));
e1f7de0c 8941 struct access_method access = SA5_performant_access;
def342bd
SC		 8942
8943 /* This is a bit complicated. There are 8 registers on
8944 * the controller which we write to to tell it 8 different
8945 * sizes of commands which there may be. It's a way of
8946 * reducing the DMA done to fetch each command. Encoded into
8947 * each command's tag are 3 bits which communicate to the controller
8948 * which of the eight sizes that command fits within. The size of
8949 * each command depends on how many scatter gather entries there are.
8950 * Each SG entry requires 16 bytes. The eight registers are programmed
8951 * with the number of 16-byte blocks a command of that size requires.
8952 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 8953 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 8954 * blocks. Note, this only extends to the SG entries contained
8955 * within the command block, and does not extend to chained blocks
8956 * of SG elements. bft[] contains the eight values we write to
8957 * the registers. They are not evenly distributed, but have more
8958 * sizes for small commands, and fewer sizes for larger commands.
8959 */
d66ae08b 8960 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 8961#define MIN_IOACCEL2_BFT_ENTRY 5
8962#define HPSA_IOACCEL2_HEADER_SZ 4
8963 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
8964 13, 14, 15, 16, 17, 18, 19,
8965 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
8966 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
8967 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
8968 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
8969 16 * MIN_IOACCEL2_BFT_ENTRY);
8970 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 8971 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 8972 /* 5 = 1 s/g entry or 4k
8973 * 6 = 2 s/g entry or 8k
8974 * 8 = 4 s/g entry or 16k
8975 * 10 = 6 s/g entry or 24k
8976 */
303932fd 8977
b3a52e79
SC		 8978 /* If the controller supports either ioaccel method then
8979 * we can also use the RAID stack submit path that does not
8980 * perform the superfluous readl() after each command submission.
8981 */
8982 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
8983 access = SA5_performant_access_no_read;
8984
303932fd 8985 /* Controller spec: zero out this buffer. */
072b0518
SC		 8986 for (i = 0; i < h->nreply_queues; i++)
8987 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 8988
d66ae08b
SC		 8989 bft[7] = SG_ENTRIES_IN_CMD + 4;
8990 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 8991 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 8992 for (i = 0; i < 8; i++)
8993 writel(bft[i], &h->transtable->BlockFetch[i]);
8994
8995 /* size of controller ring buffer */
8996 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 8997 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 8998 writel(0, &h->transtable->RepQCtrAddrLow32);
8999 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 9000
9001 for (i = 0; i < h->nreply_queues; i++) {
9002 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 9003 writel(h->reply_queue[i].busaddr,
254f796b
MG		 9004 &h->transtable->RepQAddr[i].lower);
9005 }
9006
b9af4937 9007 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 9008 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
9009 /*
9010 * enable outbound interrupt coalescing in accelerator mode;
9011 */
9012 if (trans_support & CFGTBL_Trans_io_accel1) {
9013 access = SA5_ioaccel_mode1_access;
9014 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
9015 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 9016 } else {
9017 if (trans_support & CFGTBL_Trans_io_accel2) {
9018 access = SA5_ioaccel_mode2_access;
9019 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
9020 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
9021 }
e1f7de0c 9022 }
303932fd 9023 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 9024 if (hpsa_wait_for_mode_change_ack(h)) {
9025 dev_err(&h->pdev->dev,
9026 "performant mode problem - doorbell timeout\n");
9027 return -ENODEV;
9028 }
303932fd
DB		 9029 register_value = readl(&(h->cfgtable->TransportActive));
9030 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 9031 dev_err(&h->pdev->dev,
9032 "performant mode problem - transport not active\n");
c706a795 9033 return -ENODEV;
303932fd 9034 }
960a30e7 9035 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 9036 h->access = access;
9037 h->transMethod = transMethod;
9038
b9af4937
SC		 9039 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
9040 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 9041 return 0;
e1f7de0c 9042
b9af4937
SC		 9043 if (trans_support & CFGTBL_Trans_io_accel1) {
9044 /* Set up I/O accelerator mode */
9045 for (i = 0; i < h->nreply_queues; i++) {
9046 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
9047 h->reply_queue[i].current_entry =
9048 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
9049 }
9050 bft[7] = h->ioaccel_maxsg + 8;
9051 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
9052 h->ioaccel1_blockFetchTable);
e1f7de0c 9053
b9af4937 9054 /* initialize all reply queue entries to unused */
072b0518
SC		 9055 for (i = 0; i < h->nreply_queues; i++)
9056 memset(h->reply_queue[i].head,
9057 (u8) IOACCEL_MODE1_REPLY_UNUSED,
9058 h->reply_queue_size);
e1f7de0c 9059
b9af4937
SC		 9060 /* set all the constant fields in the accelerator command
9061 * frames once at init time to save CPU cycles later.
9062 */
9063 for (i = 0; i < h->nr_cmds; i++) {
9064 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
9065
9066 cp->function = IOACCEL1_FUNCTION_SCSIIO;
9067 cp->err_info = (u32) (h->errinfo_pool_dhandle +
9068 (i * sizeof(struct ErrorInfo)));
9069 cp->err_info_len = sizeof(struct ErrorInfo);
9070 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 9071 cp->host_context_flags =
9072 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 9073 cp->timeout_sec = 0;
9074 cp->ReplyQueue = 0;
50a0decf 9075 cp->tag =
f2405db8 9076 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 9077 cp->host_addr =
9078 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 9079 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 9080 }
9081 } else if (trans_support & CFGTBL_Trans_io_accel2) {
9082 u64 cfg_offset, cfg_base_addr_index;
9083 u32 bft2_offset, cfg_base_addr;
9084 int rc;
9085
9086 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
9087 &cfg_base_addr_index, &cfg_offset);
9088 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
9089 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
9090 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
9091 4, h->ioaccel2_blockFetchTable);
9092 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
9093 BUILD_BUG_ON(offsetof(struct CfgTable,
9094 io_accel_request_size_offset) != 0xb8);
9095 h->ioaccel2_bft2_regs =
9096 remap_pci_mem(pci_resource_start(h->pdev,
9097 cfg_base_addr_index) +
9098 cfg_offset + bft2_offset,
9099 ARRAY_SIZE(bft2) *
9100 sizeof(*h->ioaccel2_bft2_regs));
9101 for (i = 0; i < ARRAY_SIZE(bft2); i++)
9102 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 9103 }
b9af4937 9104 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 9105 if (hpsa_wait_for_mode_change_ack(h)) {
9106 dev_err(&h->pdev->dev,
9107 "performant mode problem - enabling ioaccel mode\n");
9108 return -ENODEV;
9109 }
9110 return 0;
e1f7de0c
MG		 9111}
9112
1fb7c98a
RE		 9113/* Free ioaccel1 mode command blocks and block fetch table */
9114static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
9115{
105a3dbc 9116 if (h->ioaccel_cmd_pool) {
1fb7c98a
RE		 9117 pci_free_consistent(h->pdev,
9118 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
9119 h->ioaccel_cmd_pool,
9120 h->ioaccel_cmd_pool_dhandle);
105a3dbc
RE		 9121 h->ioaccel_cmd_pool = NULL;
9122 h->ioaccel_cmd_pool_dhandle = 0;
9123 }
1fb7c98a 9124 kfree(h->ioaccel1_blockFetchTable);
105a3dbc 9125 h->ioaccel1_blockFetchTable = NULL;
1fb7c98a
RE		 9126}
9127
d37ffbe4
RE		 9128/* Allocate ioaccel1 mode command blocks and block fetch table */
9129static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 9130{
283b4a9b
SC		 9131 h->ioaccel_maxsg =
9132 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
9133 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
9134 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
9135
e1f7de0c
MG		 9136 /* Command structures must be aligned on a 128-byte boundary
9137 * because the 7 lower bits of the address are used by the
9138 * hardware.
9139 */
e1f7de0c
MG		 9140 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
9141 IOACCEL1_COMMANDLIST_ALIGNMENT);
9142 h->ioaccel_cmd_pool =
9143 pci_alloc_consistent(h->pdev,
9144 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
9145 &(h->ioaccel_cmd_pool_dhandle));
9146
9147 h->ioaccel1_blockFetchTable =
283b4a9b 9148 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 9149 sizeof(u32)), GFP_KERNEL);
9150
9151 if ((h->ioaccel_cmd_pool == NULL) ||
9152 (h->ioaccel1_blockFetchTable == NULL))
9153 goto clean_up;
9154
9155 memset(h->ioaccel_cmd_pool, 0,
9156 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
9157 return 0;
9158
9159clean_up:
1fb7c98a 9160 hpsa_free_ioaccel1_cmd_and_bft(h);
2dd02d74 9161 return -ENOMEM;
6c311b57
SC		 9162}
9163
1fb7c98a
RE		 9164/* Free ioaccel2 mode command blocks and block fetch table */
9165static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
9166{
d9a729f3
WS		 9167 hpsa_free_ioaccel2_sg_chain_blocks(h);
9168
105a3dbc 9169 if (h->ioaccel2_cmd_pool) {
1fb7c98a
RE		 9170 pci_free_consistent(h->pdev,
9171 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
9172 h->ioaccel2_cmd_pool,
9173 h->ioaccel2_cmd_pool_dhandle);
105a3dbc
RE		 9174 h->ioaccel2_cmd_pool = NULL;
9175 h->ioaccel2_cmd_pool_dhandle = 0;
9176 }
1fb7c98a 9177 kfree(h->ioaccel2_blockFetchTable);
105a3dbc 9178 h->ioaccel2_blockFetchTable = NULL;
1fb7c98a
RE		 9179}
9180
d37ffbe4
RE		 9181/* Allocate ioaccel2 mode command blocks and block fetch table */
9182static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 9183{
d9a729f3
WS		 9184 int rc;
9185
aca9012a
SC		 9186 /* Allocate ioaccel2 mode command blocks and block fetch table */
9187
9188 h->ioaccel_maxsg =
9189 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
9190 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
9191 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
9192
aca9012a
SC		 9193 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
9194 IOACCEL2_COMMANDLIST_ALIGNMENT);
9195 h->ioaccel2_cmd_pool =
9196 pci_alloc_consistent(h->pdev,
9197 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
9198 &(h->ioaccel2_cmd_pool_dhandle));
9199
9200 h->ioaccel2_blockFetchTable =
9201 kmalloc(((h->ioaccel_maxsg + 1) *
9202 sizeof(u32)), GFP_KERNEL);
9203
9204 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 9205 (h->ioaccel2_blockFetchTable == NULL)) {
9206 rc = -ENOMEM;
9207 goto clean_up;
9208 }
9209
9210 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
9211 if (rc)
aca9012a
SC		 9212 goto clean_up;
9213
9214 memset(h->ioaccel2_cmd_pool, 0,
9215 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
9216 return 0;
9217
9218clean_up:
1fb7c98a 9219 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 9220 return rc;
aca9012a
SC		 9221}
9222
105a3dbc
RE		 9223/* Free items allocated by hpsa_put_ctlr_into_performant_mode */
9224static void hpsa_free_performant_mode(struct ctlr_info *h)
9225{
9226 kfree(h->blockFetchTable);
9227 h->blockFetchTable = NULL;
9228 hpsa_free_reply_queues(h);
9229 hpsa_free_ioaccel1_cmd_and_bft(h);
9230 hpsa_free_ioaccel2_cmd_and_bft(h);
9231}
9232
9233/* return -ENODEV on error, 0 on success (or no action)
9234 * allocates numerous items that must be freed later
9235 */
9236static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 9237{
9238 u32 trans_support;
e1f7de0c
MG		 9239 unsigned long transMethod = CFGTBL_Trans_Performant |
9240 CFGTBL_Trans_use_short_tags;
105a3dbc 9241 int i, rc;
6c311b57 9242
02ec19c8 9243 if (hpsa_simple_mode)
105a3dbc 9244 return 0;
02ec19c8 9245
67c99a72 9246 trans_support = readl(&(h->cfgtable->TransportSupport));
9247 if (!(trans_support & PERFORMANT_MODE))
105a3dbc 9248 return 0;
67c99a72 9249
e1f7de0c
MG		 9250 /* Check for I/O accelerator mode support */
9251 if (trans_support & CFGTBL_Trans_io_accel1) {
9252 transMethod |= CFGTBL_Trans_io_accel1 |
9253 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 9254 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
9255 if (rc)
9256 return rc;
9257 } else if (trans_support & CFGTBL_Trans_io_accel2) {
9258 transMethod |= CFGTBL_Trans_io_accel2 |
aca9012a 9259 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 9260 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
9261 if (rc)
9262 return rc;
e1f7de0c
MG		 9263 }
9264
eee0f03a 9265 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 9266 hpsa_get_max_perf_mode_cmds(h);
6c311b57 9267 /* Performant mode ring buffer and supporting data structures */
072b0518 9268 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 9269
254f796b 9270 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 9271 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
9272 h->reply_queue_size,
9273 &(h->reply_queue[i].busaddr));
105a3dbc
RE		 9274 if (!h->reply_queue[i].head) {
9275 rc = -ENOMEM;
9276 goto clean1; /* rq, ioaccel */
9277 }
254f796b
MG		 9278 h->reply_queue[i].size = h->max_commands;
9279 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
9280 h->reply_queue[i].current_entry = 0;
9281 }
9282
6c311b57 9283 /* Need a block fetch table for performant mode */
d66ae08b 9284 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 9285 sizeof(u32)), GFP_KERNEL);
105a3dbc
RE		 9286 if (!h->blockFetchTable) {
9287 rc = -ENOMEM;
9288 goto clean1; /* rq, ioaccel */
9289 }
6c311b57 9290
105a3dbc
RE		 9291 rc = hpsa_enter_performant_mode(h, trans_support);
9292 if (rc)
9293 goto clean2; /* bft, rq, ioaccel */
9294 return 0;
303932fd 9295
105a3dbc 9296clean2: /* bft, rq, ioaccel */
303932fd 9297 kfree(h->blockFetchTable);
105a3dbc
RE		 9298 h->blockFetchTable = NULL;
9299clean1: /* rq, ioaccel */
9300 hpsa_free_reply_queues(h);
9301 hpsa_free_ioaccel1_cmd_and_bft(h);
9302 hpsa_free_ioaccel2_cmd_and_bft(h);
9303 return rc;
303932fd
DB		 9304}
9305
23100dd9 9306static int is_accelerated_cmd(struct CommandList *c)
76438d08 9307{
23100dd9
SC		 9308 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
9309}
9310
9311static void hpsa_drain_accel_commands(struct ctlr_info *h)
9312{
9313 struct CommandList *c = NULL;
f2405db8 9314 int i, accel_cmds_out;
281a7fd0 9315 int refcount;
76438d08 9316
f2405db8 9317 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 9318 accel_cmds_out = 0;
f2405db8 9319 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 9320 c = h->cmd_pool + i;
281a7fd0
WS		 9321 refcount = atomic_inc_return(&c->refcount);
9322 if (refcount > 1) /* Command is allocated */
9323 accel_cmds_out += is_accelerated_cmd(c);
9324 cmd_free(h, c);
f2405db8 9325 }
23100dd9 9326 if (accel_cmds_out <= 0)
281a7fd0 9327 break;
76438d08
SC		 9328 msleep(100);
9329 } while (1);
9330}
9331
d04e62b9
KB		 9332static struct hpsa_sas_phy *hpsa_alloc_sas_phy(
9333 struct hpsa_sas_port *hpsa_sas_port)
9334{
9335 struct hpsa_sas_phy *hpsa_sas_phy;
9336 struct sas_phy *phy;
9337
9338 hpsa_sas_phy = kzalloc(sizeof(*hpsa_sas_phy), GFP_KERNEL);
9339 if (!hpsa_sas_phy)
9340 return NULL;
9341
9342 phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev,
9343 hpsa_sas_port->next_phy_index);
9344 if (!phy) {
9345 kfree(hpsa_sas_phy);
9346 return NULL;
9347 }
9348
9349 hpsa_sas_port->next_phy_index++;
9350 hpsa_sas_phy->phy = phy;
9351 hpsa_sas_phy->parent_port = hpsa_sas_port;
9352
9353 return hpsa_sas_phy;
9354}
9355
9356static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy)
9357{
9358 struct sas_phy *phy = hpsa_sas_phy->phy;
9359
9360 sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy);
9361 sas_phy_free(phy);
9362 if (hpsa_sas_phy->added_to_port)
9363 list_del(&hpsa_sas_phy->phy_list_entry);
9364 kfree(hpsa_sas_phy);
9365}
9366
9367static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy)
9368{
9369 int rc;
9370 struct hpsa_sas_port *hpsa_sas_port;
9371 struct sas_phy *phy;
9372 struct sas_identify *identify;
9373
9374 hpsa_sas_port = hpsa_sas_phy->parent_port;
9375 phy = hpsa_sas_phy->phy;
9376
9377 identify = &phy->identify;
9378 memset(identify, 0, sizeof(*identify));
9379 identify->sas_address = hpsa_sas_port->sas_address;
9380 identify->device_type = SAS_END_DEVICE;
9381 identify->initiator_port_protocols = SAS_PROTOCOL_STP;
9382 identify->target_port_protocols = SAS_PROTOCOL_STP;
9383 phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
9384 phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
9385 phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN;
9386 phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN;
9387 phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN;
9388
9389 rc = sas_phy_add(hpsa_sas_phy->phy);
9390 if (rc)
9391 return rc;
9392
9393 sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy);
9394 list_add_tail(&hpsa_sas_phy->phy_list_entry,
9395 &hpsa_sas_port->phy_list_head);
9396 hpsa_sas_phy->added_to_port = true;
9397
9398 return 0;
9399}
9400
9401static int
9402 hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port,
9403 struct sas_rphy *rphy)
9404{
9405 struct sas_identify *identify;
9406
9407 identify = &rphy->identify;
9408 identify->sas_address = hpsa_sas_port->sas_address;
9409 identify->initiator_port_protocols = SAS_PROTOCOL_STP;
9410 identify->target_port_protocols = SAS_PROTOCOL_STP;
9411
9412 return sas_rphy_add(rphy);
9413}
9414
9415static struct hpsa_sas_port
9416 *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node,
9417 u64 sas_address)
9418{
9419 int rc;
9420 struct hpsa_sas_port *hpsa_sas_port;
9421 struct sas_port *port;
9422
9423 hpsa_sas_port = kzalloc(sizeof(*hpsa_sas_port), GFP_KERNEL);
9424 if (!hpsa_sas_port)
9425 return NULL;
9426
9427 INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head);
9428 hpsa_sas_port->parent_node = hpsa_sas_node;
9429
9430 port = sas_port_alloc_num(hpsa_sas_node->parent_dev);
9431 if (!port)
9432 goto free_hpsa_port;
9433
9434 rc = sas_port_add(port);
9435 if (rc)
9436 goto free_sas_port;
9437
9438 hpsa_sas_port->port = port;
9439 hpsa_sas_port->sas_address = sas_address;
9440 list_add_tail(&hpsa_sas_port->port_list_entry,
9441 &hpsa_sas_node->port_list_head);
9442
9443 return hpsa_sas_port;
9444
9445free_sas_port:
9446 sas_port_free(port);
9447free_hpsa_port:
9448 kfree(hpsa_sas_port);
9449
9450 return NULL;
9451}
9452
9453static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port)
9454{
9455 struct hpsa_sas_phy *hpsa_sas_phy;
9456 struct hpsa_sas_phy *next;
9457
9458 list_for_each_entry_safe(hpsa_sas_phy, next,
9459 &hpsa_sas_port->phy_list_head, phy_list_entry)
9460 hpsa_free_sas_phy(hpsa_sas_phy);
9461
9462 sas_port_delete(hpsa_sas_port->port);
9463 list_del(&hpsa_sas_port->port_list_entry);
9464 kfree(hpsa_sas_port);
9465}
9466
9467static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev)
9468{
9469 struct hpsa_sas_node *hpsa_sas_node;
9470
9471 hpsa_sas_node = kzalloc(sizeof(*hpsa_sas_node), GFP_KERNEL);
9472 if (hpsa_sas_node) {
9473 hpsa_sas_node->parent_dev = parent_dev;
9474 INIT_LIST_HEAD(&hpsa_sas_node->port_list_head);
9475 }
9476
9477 return hpsa_sas_node;
9478}
9479
9480static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node)
9481{
9482 struct hpsa_sas_port *hpsa_sas_port;
9483 struct hpsa_sas_port *next;
9484
9485 if (!hpsa_sas_node)
9486 return;
9487
9488 list_for_each_entry_safe(hpsa_sas_port, next,
9489 &hpsa_sas_node->port_list_head, port_list_entry)
9490 hpsa_free_sas_port(hpsa_sas_port);
9491
9492 kfree(hpsa_sas_node);
9493}
9494
9495static struct hpsa_scsi_dev_t
9496 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
9497 struct sas_rphy *rphy)
9498{
9499 int i;
9500 struct hpsa_scsi_dev_t *device;
9501
9502 for (i = 0; i < h->ndevices; i++) {
9503 device = h->dev[i];
9504 if (!device->sas_port)
9505 continue;
9506 if (device->sas_port->rphy == rphy)
9507 return device;
9508 }
9509
9510 return NULL;
9511}
9512
9513static int hpsa_add_sas_host(struct ctlr_info *h)
9514{
9515 int rc;
9516 struct device *parent_dev;
9517 struct hpsa_sas_node *hpsa_sas_node;
9518 struct hpsa_sas_port *hpsa_sas_port;
9519 struct hpsa_sas_phy *hpsa_sas_phy;
9520
9521 parent_dev = &h->scsi_host->shost_gendev;
9522
9523 hpsa_sas_node = hpsa_alloc_sas_node(parent_dev);
9524 if (!hpsa_sas_node)
9525 return -ENOMEM;
9526
9527 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address);
9528 if (!hpsa_sas_port) {
9529 rc = -ENODEV;
9530 goto free_sas_node;
9531 }
9532
9533 hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port);
9534 if (!hpsa_sas_phy) {
9535 rc = -ENODEV;
9536 goto free_sas_port;
9537 }
9538
9539 rc = hpsa_sas_port_add_phy(hpsa_sas_phy);
9540 if (rc)
9541 goto free_sas_phy;
9542
9543 h->sas_host = hpsa_sas_node;
9544
9545 return 0;
9546
9547free_sas_phy:
9548 hpsa_free_sas_phy(hpsa_sas_phy);
9549free_sas_port:
9550 hpsa_free_sas_port(hpsa_sas_port);
9551free_sas_node:
9552 hpsa_free_sas_node(hpsa_sas_node);
9553
9554 return rc;
9555}
9556
9557static void hpsa_delete_sas_host(struct ctlr_info *h)
9558{
9559 hpsa_free_sas_node(h->sas_host);
9560}
9561
9562static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
9563 struct hpsa_scsi_dev_t *device)
9564{
9565 int rc;
9566 struct hpsa_sas_port *hpsa_sas_port;
9567 struct sas_rphy *rphy;
9568
9569 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address);
9570 if (!hpsa_sas_port)
9571 return -ENOMEM;
9572
9573 rphy = sas_end_device_alloc(hpsa_sas_port->port);
9574 if (!rphy) {
9575 rc = -ENODEV;
9576 goto free_sas_port;
9577 }
9578
9579 hpsa_sas_port->rphy = rphy;
9580 device->sas_port = hpsa_sas_port;
9581
9582 rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy);
9583 if (rc)
9584 goto free_sas_port;
9585
9586 return 0;
9587
9588free_sas_port:
9589 hpsa_free_sas_port(hpsa_sas_port);
9590 device->sas_port = NULL;
9591
9592 return rc;
9593}
9594
9595static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device)
9596{
9597 if (device->sas_port) {
9598 hpsa_free_sas_port(device->sas_port);
9599 device->sas_port = NULL;
9600 }
9601}
9602
9603static int
9604hpsa_sas_get_linkerrors(struct sas_phy *phy)
9605{
9606 return 0;
9607}
9608
9609static int
9610hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier)
9611{
9612 return 0;
9613}
9614
9615static int
9616hpsa_sas_get_bay_identifier(struct sas_rphy *rphy)
9617{
9618 return -ENXIO;
9619}
9620
9621static int
9622hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset)
9623{
9624 return 0;
9625}
9626
9627static int
9628hpsa_sas_phy_enable(struct sas_phy *phy, int enable)
9629{
9630 return 0;
9631}
9632
9633static int
9634hpsa_sas_phy_setup(struct sas_phy *phy)
9635{
9636 return 0;
9637}
9638
9639static void
9640hpsa_sas_phy_release(struct sas_phy *phy)
9641{
9642}
9643
9644static int
9645hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates)
9646{
9647 return -EINVAL;
9648}
9649
9650/* SMP = Serial Management Protocol */
9651static int
9652hpsa_sas_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy,
9653struct request *req)
9654{
9655 return -EINVAL;
9656}
9657
9658static struct sas_function_template hpsa_sas_transport_functions = {
9659 .get_linkerrors = hpsa_sas_get_linkerrors,
9660 .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier,
9661 .get_bay_identifier = hpsa_sas_get_bay_identifier,
9662 .phy_reset = hpsa_sas_phy_reset,
9663 .phy_enable = hpsa_sas_phy_enable,
9664 .phy_setup = hpsa_sas_phy_setup,
9665 .phy_release = hpsa_sas_phy_release,
9666 .set_phy_speed = hpsa_sas_phy_speed,
9667 .smp_handler = hpsa_sas_smp_handler,
9668};
9669
edd16368
SC		 9670/*
9671 * This is it. Register the PCI driver information for the cards we control
9672 * the OS will call our registered routines when it finds one of our cards.
9673 */
9674static int __init hpsa_init(void)
9675{
d04e62b9
KB		 9676 int rc;
9677
9678 hpsa_sas_transport_template =
9679 sas_attach_transport(&hpsa_sas_transport_functions);
9680 if (!hpsa_sas_transport_template)
9681 return -ENODEV;
9682
9683 rc = pci_register_driver(&hpsa_pci_driver);
9684
9685 if (rc)
9686 sas_release_transport(hpsa_sas_transport_template);
9687
9688 return rc;
edd16368
SC		 9689}
9690
9691static void __exit hpsa_cleanup(void)
9692{
9693 pci_unregister_driver(&hpsa_pci_driver);
d04e62b9 9694 sas_release_transport(hpsa_sas_transport_template);
edd16368
SC		 9695}
9696
e1f7de0c
MG		 9697static void __attribute__((unused)) verify_offsets(void)
9698{
dd0e19f3
ST		 9699#define VERIFY_OFFSET(member, offset) \
9700 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
9701
9702 VERIFY_OFFSET(structure_size, 0);
9703 VERIFY_OFFSET(volume_blk_size, 4);
9704 VERIFY_OFFSET(volume_blk_cnt, 8);
9705 VERIFY_OFFSET(phys_blk_shift, 16);
9706 VERIFY_OFFSET(parity_rotation_shift, 17);
9707 VERIFY_OFFSET(strip_size, 18);
9708 VERIFY_OFFSET(disk_starting_blk, 20);
9709 VERIFY_OFFSET(disk_blk_cnt, 28);
9710 VERIFY_OFFSET(data_disks_per_row, 36);
9711 VERIFY_OFFSET(metadata_disks_per_row, 38);
9712 VERIFY_OFFSET(row_cnt, 40);
9713 VERIFY_OFFSET(layout_map_count, 42);
9714 VERIFY_OFFSET(flags, 44);
9715 VERIFY_OFFSET(dekindex, 46);
9716 /* VERIFY_OFFSET(reserved, 48 */
9717 VERIFY_OFFSET(data, 64);
9718
9719#undef VERIFY_OFFSET
9720
b66cc250
MM		 9721#define VERIFY_OFFSET(member, offset) \
9722 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
9723
9724 VERIFY_OFFSET(IU_type, 0);
9725 VERIFY_OFFSET(direction, 1);
9726 VERIFY_OFFSET(reply_queue, 2);
9727 /* VERIFY_OFFSET(reserved1, 3); */
9728 VERIFY_OFFSET(scsi_nexus, 4);
9729 VERIFY_OFFSET(Tag, 8);
9730 VERIFY_OFFSET(cdb, 16);
9731 VERIFY_OFFSET(cciss_lun, 32);
9732 VERIFY_OFFSET(data_len, 40);
9733 VERIFY_OFFSET(cmd_priority_task_attr, 44);
9734 VERIFY_OFFSET(sg_count, 45);
9735 /* VERIFY_OFFSET(reserved3 */
9736 VERIFY_OFFSET(err_ptr, 48);
9737 VERIFY_OFFSET(err_len, 56);
9738 /* VERIFY_OFFSET(reserved4 */
9739 VERIFY_OFFSET(sg, 64);
9740
9741#undef VERIFY_OFFSET
9742
e1f7de0c
MG		 9743#define VERIFY_OFFSET(member, offset) \
9744 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
9745
9746 VERIFY_OFFSET(dev_handle, 0x00);
9747 VERIFY_OFFSET(reserved1, 0x02);
9748 VERIFY_OFFSET(function, 0x03);
9749 VERIFY_OFFSET(reserved2, 0x04);
9750 VERIFY_OFFSET(err_info, 0x0C);
9751 VERIFY_OFFSET(reserved3, 0x10);
9752 VERIFY_OFFSET(err_info_len, 0x12);
9753 VERIFY_OFFSET(reserved4, 0x13);
9754 VERIFY_OFFSET(sgl_offset, 0x14);
9755 VERIFY_OFFSET(reserved5, 0x15);
9756 VERIFY_OFFSET(transfer_len, 0x1C);
9757 VERIFY_OFFSET(reserved6, 0x20);
9758 VERIFY_OFFSET(io_flags, 0x24);
9759 VERIFY_OFFSET(reserved7, 0x26);
9760 VERIFY_OFFSET(LUN, 0x34);
9761 VERIFY_OFFSET(control, 0x3C);
9762 VERIFY_OFFSET(CDB, 0x40);
9763 VERIFY_OFFSET(reserved8, 0x50);
9764 VERIFY_OFFSET(host_context_flags, 0x60);
9765 VERIFY_OFFSET(timeout_sec, 0x62);
9766 VERIFY_OFFSET(ReplyQueue, 0x64);
9767 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 9768 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 9769 VERIFY_OFFSET(host_addr, 0x70);
9770 VERIFY_OFFSET(CISS_LUN, 0x78);
9771 VERIFY_OFFSET(SG, 0x78 + 8);
9772#undef VERIFY_OFFSET
9773}
9774
edd16368
SC		 9775module_init(hpsa_init);
9776module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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