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[SCSI] hpsa: allow user to disable accelerated i/o path
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
edd16368 50#include <linux/kthread.h>
a0c12413 51#include <linux/jiffies.h>
283b4a9b 52#include <asm/div64.h>
edd16368
SC		 53#include "hpsa_cmd.h"
54#include "hpsa.h"
55
56/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
e481cce8 57#define HPSA_DRIVER_VERSION "3.4.0-1"
edd16368 58#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 59#define HPSA "hpsa"
edd16368
SC		 60
61/* How long to wait (in milliseconds) for board to go into simple mode */
62#define MAX_CONFIG_WAIT 30000
63#define MAX_IOCTL_CONFIG_WAIT 1000
64
65/*define how many times we will try a command because of bus resets */
66#define MAX_CMD_RETRIES 3
67
68/* Embedded module documentation macros - see modules.h */
69MODULE_AUTHOR("Hewlett-Packard Company");
70MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
71 HPSA_DRIVER_VERSION);
72MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
73MODULE_VERSION(HPSA_DRIVER_VERSION);
74MODULE_LICENSE("GPL");
75
76static int hpsa_allow_any;
77module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(hpsa_allow_any,
79 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 80static int hpsa_simple_mode;
81module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_simple_mode,
83 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 84
85/* define the PCI info for the cards we can control */
86static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
7c03b870 122 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 123 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 124 {0,}
125};
126
127MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
128
129/* board_id = Subsystem Device ID & Vendor ID
130 * product = Marketing Name for the board
131 * access = Address of the struct of function pointers
132 */
133static struct board_type products[] = {
edd16368
SC		 134 {0x3241103C, "Smart Array P212", &SA5_access},
135 {0x3243103C, "Smart Array P410", &SA5_access},
136 {0x3245103C, "Smart Array P410i", &SA5_access},
137 {0x3247103C, "Smart Array P411", &SA5_access},
138 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 139 {0x324A103C, "Smart Array P712m", &SA5_access},
140 {0x324B103C, "Smart Array P711m", &SA5_access},
fe0c9610
MM		 141 {0x3350103C, "Smart Array P222", &SA5_access},
142 {0x3351103C, "Smart Array P420", &SA5_access},
143 {0x3352103C, "Smart Array P421", &SA5_access},
144 {0x3353103C, "Smart Array P822", &SA5_access},
145 {0x3354103C, "Smart Array P420i", &SA5_access},
146 {0x3355103C, "Smart Array P220i", &SA5_access},
147 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 148 {0x1921103C, "Smart Array P830i", &SA5_access},
149 {0x1922103C, "Smart Array P430", &SA5_access},
150 {0x1923103C, "Smart Array P431", &SA5_access},
151 {0x1924103C, "Smart Array P830", &SA5_access},
152 {0x1926103C, "Smart Array P731m", &SA5_access},
153 {0x1928103C, "Smart Array P230i", &SA5_access},
154 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 155 {0x21BD103C, "Smart Array", &SA5_access},
156 {0x21BE103C, "Smart Array", &SA5_access},
157 {0x21BF103C, "Smart Array", &SA5_access},
158 {0x21C0103C, "Smart Array", &SA5_access},
159 {0x21C1103C, "Smart Array", &SA5_access},
160 {0x21C2103C, "Smart Array", &SA5_access},
161 {0x21C3103C, "Smart Array", &SA5_access},
162 {0x21C4103C, "Smart Array", &SA5_access},
163 {0x21C5103C, "Smart Array", &SA5_access},
164 {0x21C7103C, "Smart Array", &SA5_access},
165 {0x21C8103C, "Smart Array", &SA5_access},
166 {0x21C9103C, "Smart Array", &SA5_access},
edd16368
SC		 167 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
168};
169
170static int number_of_controllers;
171
10f66018
SC		 172static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
173static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
edd16368
SC		 174static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
175static void start_io(struct ctlr_info *h);
176
177#ifdef CONFIG_COMPAT
178static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
179#endif
180
181static void cmd_free(struct ctlr_info *h, struct CommandList *c);
182static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
183static struct CommandList *cmd_alloc(struct ctlr_info *h);
184static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
a2dac136 185static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
01a02ffc 186 void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
edd16368
SC		 187 int cmd_type);
188
f281233d 189static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 190static void hpsa_scan_start(struct Scsi_Host *);
191static int hpsa_scan_finished(struct Scsi_Host *sh,
192 unsigned long elapsed_time);
667e23d4
SC		 193static int hpsa_change_queue_depth(struct scsi_device *sdev,
194 int qdepth, int reason);
edd16368
SC		 195
196static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 197static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 198static int hpsa_slave_alloc(struct scsi_device *sdev);
199static void hpsa_slave_destroy(struct scsi_device *sdev);
200
edd16368 201static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 202static int check_for_unit_attention(struct ctlr_info *h,
203 struct CommandList *c);
204static void check_ioctl_unit_attention(struct ctlr_info *h,
205 struct CommandList *c);
303932fd
DB		 206/* performant mode helper functions */
207static void calc_bucket_map(int *bucket, int num_buckets,
e1f7de0c 208 int nsgs, int min_blocks, int *bucket_map);
6f039790 209static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 210static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 211static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
212 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
213 u64 *cfg_offset);
214static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
215 unsigned long *memory_bar);
216static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
217static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
218 int wait_for_ready);
75167d2c 219static inline void finish_cmd(struct CommandList *c);
283b4a9b 220static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 221#define BOARD_NOT_READY 0
222#define BOARD_READY 1
76438d08
SC		 223static void hpsa_drain_commands(struct ctlr_info *h);
224static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 225static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
226 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
227 u8 *scsi3addr);
edd16368 228
edd16368
SC		 229static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
230{
231 unsigned long *priv = shost_priv(sdev->host);
232 return (struct ctlr_info *) *priv;
233}
234
a23513e8
SC		 235static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
236{
237 unsigned long *priv = shost_priv(sh);
238 return (struct ctlr_info *) *priv;
239}
240
edd16368
SC		 241static int check_for_unit_attention(struct ctlr_info *h,
242 struct CommandList *c)
243{
244 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
245 return 0;
246
247 switch (c->err_info->SenseInfo[12]) {
248 case STATE_CHANGED:
f79cfec6 249 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 250 "detected, command retried\n", h->ctlr);
251 break;
252 case LUN_FAILED:
f79cfec6 253 dev_warn(&h->pdev->dev, HPSA "%d: LUN failure "
edd16368
SC		 254 "detected, action required\n", h->ctlr);
255 break;
256 case REPORT_LUNS_CHANGED:
f79cfec6 257 dev_warn(&h->pdev->dev, HPSA "%d: report LUN data "
31468401 258 "changed, action required\n", h->ctlr);
edd16368 259 /*
4f4eb9f1
ST		 260 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
261 * target (array) devices.
edd16368
SC		 262 */
263 break;
264 case POWER_OR_RESET:
f79cfec6 265 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 266 "or device reset detected\n", h->ctlr);
267 break;
268 case UNIT_ATTENTION_CLEARED:
f79cfec6 269 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 270 "cleared by another initiator\n", h->ctlr);
271 break;
272 default:
f79cfec6 273 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 274 "unit attention detected\n", h->ctlr);
275 break;
276 }
277 return 1;
278}
279
852af20a
MB		 280static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
281{
282 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
283 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
284 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
285 return 0;
286 dev_warn(&h->pdev->dev, HPSA "device busy");
287 return 1;
288}
289
da0697bd
ST		 290static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
291 struct device_attribute *attr,
292 const char *buf, size_t count)
293{
294 int status, len;
295 struct ctlr_info *h;
296 struct Scsi_Host *shost = class_to_shost(dev);
297 char tmpbuf[10];
298
299 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
300 return -EACCES;
301 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
302 strncpy(tmpbuf, buf, len);
303 tmpbuf[len] = '\0';
304 if (sscanf(tmpbuf, "%d", &status) != 1)
305 return -EINVAL;
306 h = shost_to_hba(shost);
307 h->acciopath_status = !!status;
308 dev_warn(&h->pdev->dev,
309 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
310 h->acciopath_status ? "enabled" : "disabled");
311 return count;
312}
313
edd16368
SC		 314static ssize_t host_store_rescan(struct device *dev,
315 struct device_attribute *attr,
316 const char *buf, size_t count)
317{
318 struct ctlr_info *h;
319 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 320 h = shost_to_hba(shost);
31468401 321 hpsa_scan_start(h->scsi_host);
edd16368
SC		 322 return count;
323}
324
d28ce020
SC		 325static ssize_t host_show_firmware_revision(struct device *dev,
326 struct device_attribute *attr, char *buf)
327{
328 struct ctlr_info *h;
329 struct Scsi_Host *shost = class_to_shost(dev);
330 unsigned char *fwrev;
331
332 h = shost_to_hba(shost);
333 if (!h->hba_inquiry_data)
334 return 0;
335 fwrev = &h->hba_inquiry_data[32];
336 return snprintf(buf, 20, "%c%c%c%c\n",
337 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
338}
339
94a13649
SC		 340static ssize_t host_show_commands_outstanding(struct device *dev,
341 struct device_attribute *attr, char *buf)
342{
343 struct Scsi_Host *shost = class_to_shost(dev);
344 struct ctlr_info *h = shost_to_hba(shost);
345
346 return snprintf(buf, 20, "%d\n", h->commands_outstanding);
347}
348
745a7a25
SC		 349static ssize_t host_show_transport_mode(struct device *dev,
350 struct device_attribute *attr, char *buf)
351{
352 struct ctlr_info *h;
353 struct Scsi_Host *shost = class_to_shost(dev);
354
355 h = shost_to_hba(shost);
356 return snprintf(buf, 20, "%s\n",
960a30e7 357 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 358 "performant" : "simple");
359}
360
da0697bd
ST		 361static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
362 struct device_attribute *attr, char *buf)
363{
364 struct ctlr_info *h;
365 struct Scsi_Host *shost = class_to_shost(dev);
366
367 h = shost_to_hba(shost);
368 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
369 (h->acciopath_status == 1) ? "enabled" : "disabled");
370}
371
46380786 372/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 373static u32 unresettable_controller[] = {
374 0x324a103C, /* Smart Array P712m */
375 0x324b103C, /* SmartArray P711m */
376 0x3223103C, /* Smart Array P800 */
377 0x3234103C, /* Smart Array P400 */
378 0x3235103C, /* Smart Array P400i */
379 0x3211103C, /* Smart Array E200i */
380 0x3212103C, /* Smart Array E200 */
381 0x3213103C, /* Smart Array E200i */
382 0x3214103C, /* Smart Array E200i */
383 0x3215103C, /* Smart Array E200i */
384 0x3237103C, /* Smart Array E500 */
385 0x323D103C, /* Smart Array P700m */
7af0abbc 386 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 387 0x409C0E11, /* Smart Array 6400 */
388 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 389 0x40700E11, /* Smart Array 5300 */
390 0x40820E11, /* Smart Array 532 */
391 0x40830E11, /* Smart Array 5312 */
392 0x409A0E11, /* Smart Array 641 */
393 0x409B0E11, /* Smart Array 642 */
394 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 395};
396
46380786
SC		 397/* List of controllers which cannot even be soft reset */
398static u32 soft_unresettable_controller[] = {
7af0abbc 399 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 400 0x40700E11, /* Smart Array 5300 */
401 0x40820E11, /* Smart Array 532 */
402 0x40830E11, /* Smart Array 5312 */
403 0x409A0E11, /* Smart Array 641 */
404 0x409B0E11, /* Smart Array 642 */
405 0x40910E11, /* Smart Array 6i */
46380786
SC		 406 /* Exclude 640x boards. These are two pci devices in one slot
407 * which share a battery backed cache module. One controls the
408 * cache, the other accesses the cache through the one that controls
409 * it. If we reset the one controlling the cache, the other will
410 * likely not be happy. Just forbid resetting this conjoined mess.
411 * The 640x isn't really supported by hpsa anyway.
412 */
413 0x409C0E11, /* Smart Array 6400 */
414 0x409D0E11, /* Smart Array 6400 EM */
415};
416
417static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 418{
419 int i;
420
421 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 422 if (unresettable_controller[i] == board_id)
423 return 0;
424 return 1;
425}
426
427static int ctlr_is_soft_resettable(u32 board_id)
428{
429 int i;
430
431 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
432 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 433 return 0;
434 return 1;
435}
436
46380786
SC		 437static int ctlr_is_resettable(u32 board_id)
438{
439 return ctlr_is_hard_resettable(board_id) ||
440 ctlr_is_soft_resettable(board_id);
441}
442
941b1cda
SC		 443static ssize_t host_show_resettable(struct device *dev,
444 struct device_attribute *attr, char *buf)
445{
446 struct ctlr_info *h;
447 struct Scsi_Host *shost = class_to_shost(dev);
448
449 h = shost_to_hba(shost);
46380786 450 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 451}
452
edd16368
SC		 453static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
454{
455 return (scsi3addr[3] & 0xC0) == 0x40;
456}
457
458static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
d82357ea 459 "1(ADM)", "UNKNOWN"
edd16368 460};
6b80b18f
ST		 461#define HPSA_RAID_0 0
462#define HPSA_RAID_4 1
463#define HPSA_RAID_1 2 /* also used for RAID 10 */
464#define HPSA_RAID_5 3 /* also used for RAID 50 */
465#define HPSA_RAID_51 4
466#define HPSA_RAID_6 5 /* also used for RAID 60 */
467#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 468#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
469
470static ssize_t raid_level_show(struct device *dev,
471 struct device_attribute *attr, char *buf)
472{
473 ssize_t l = 0;
82a72c0a 474 unsigned char rlevel;
edd16368
SC		 475 struct ctlr_info *h;
476 struct scsi_device *sdev;
477 struct hpsa_scsi_dev_t *hdev;
478 unsigned long flags;
479
480 sdev = to_scsi_device(dev);
481 h = sdev_to_hba(sdev);
482 spin_lock_irqsave(&h->lock, flags);
483 hdev = sdev->hostdata;
484 if (!hdev) {
485 spin_unlock_irqrestore(&h->lock, flags);
486 return -ENODEV;
487 }
488
489 /* Is this even a logical drive? */
490 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
491 spin_unlock_irqrestore(&h->lock, flags);
492 l = snprintf(buf, PAGE_SIZE, "N/A\n");
493 return l;
494 }
495
496 rlevel = hdev->raid_level;
497 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 498 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 499 rlevel = RAID_UNKNOWN;
500 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
501 return l;
502}
503
504static ssize_t lunid_show(struct device *dev,
505 struct device_attribute *attr, char *buf)
506{
507 struct ctlr_info *h;
508 struct scsi_device *sdev;
509 struct hpsa_scsi_dev_t *hdev;
510 unsigned long flags;
511 unsigned char lunid[8];
512
513 sdev = to_scsi_device(dev);
514 h = sdev_to_hba(sdev);
515 spin_lock_irqsave(&h->lock, flags);
516 hdev = sdev->hostdata;
517 if (!hdev) {
518 spin_unlock_irqrestore(&h->lock, flags);
519 return -ENODEV;
520 }
521 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
522 spin_unlock_irqrestore(&h->lock, flags);
523 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
524 lunid[0], lunid[1], lunid[2], lunid[3],
525 lunid[4], lunid[5], lunid[6], lunid[7]);
526}
527
528static ssize_t unique_id_show(struct device *dev,
529 struct device_attribute *attr, char *buf)
530{
531 struct ctlr_info *h;
532 struct scsi_device *sdev;
533 struct hpsa_scsi_dev_t *hdev;
534 unsigned long flags;
535 unsigned char sn[16];
536
537 sdev = to_scsi_device(dev);
538 h = sdev_to_hba(sdev);
539 spin_lock_irqsave(&h->lock, flags);
540 hdev = sdev->hostdata;
541 if (!hdev) {
542 spin_unlock_irqrestore(&h->lock, flags);
543 return -ENODEV;
544 }
545 memcpy(sn, hdev->device_id, sizeof(sn));
546 spin_unlock_irqrestore(&h->lock, flags);
547 return snprintf(buf, 16 * 2 + 2,
548 "%02X%02X%02X%02X%02X%02X%02X%02X"
549 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
550 sn[0], sn[1], sn[2], sn[3],
551 sn[4], sn[5], sn[6], sn[7],
552 sn[8], sn[9], sn[10], sn[11],
553 sn[12], sn[13], sn[14], sn[15]);
554}
555
c1988684
ST		 556static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
557 struct device_attribute *attr, char *buf)
558{
559 struct ctlr_info *h;
560 struct scsi_device *sdev;
561 struct hpsa_scsi_dev_t *hdev;
562 unsigned long flags;
563 int offload_enabled;
564
565 sdev = to_scsi_device(dev);
566 h = sdev_to_hba(sdev);
567 spin_lock_irqsave(&h->lock, flags);
568 hdev = sdev->hostdata;
569 if (!hdev) {
570 spin_unlock_irqrestore(&h->lock, flags);
571 return -ENODEV;
572 }
573 offload_enabled = hdev->offload_enabled;
574 spin_unlock_irqrestore(&h->lock, flags);
575 return snprintf(buf, 20, "%d\n", offload_enabled);
576}
577
3f5eac3a
SC		 578static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
579static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
580static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
581static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 582static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
583 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 584static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
585 host_show_hp_ssd_smart_path_status,
586 host_store_hp_ssd_smart_path_status);
3f5eac3a
SC		 587static DEVICE_ATTR(firmware_revision, S_IRUGO,
588 host_show_firmware_revision, NULL);
589static DEVICE_ATTR(commands_outstanding, S_IRUGO,
590 host_show_commands_outstanding, NULL);
591static DEVICE_ATTR(transport_mode, S_IRUGO,
592 host_show_transport_mode, NULL);
941b1cda
SC		 593static DEVICE_ATTR(resettable, S_IRUGO,
594 host_show_resettable, NULL);
3f5eac3a
SC		 595
596static struct device_attribute *hpsa_sdev_attrs[] = {
597 &dev_attr_raid_level,
598 &dev_attr_lunid,
599 &dev_attr_unique_id,
c1988684 600 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 601 NULL,
602};
603
604static struct device_attribute *hpsa_shost_attrs[] = {
605 &dev_attr_rescan,
606 &dev_attr_firmware_revision,
607 &dev_attr_commands_outstanding,
608 &dev_attr_transport_mode,
941b1cda 609 &dev_attr_resettable,
da0697bd 610 &dev_attr_hp_ssd_smart_path_status,
3f5eac3a
SC		 611 NULL,
612};
613
614static struct scsi_host_template hpsa_driver_template = {
615 .module = THIS_MODULE,
f79cfec6
SC		 616 .name = HPSA,
617 .proc_name = HPSA,
3f5eac3a
SC		 618 .queuecommand = hpsa_scsi_queue_command,
619 .scan_start = hpsa_scan_start,
620 .scan_finished = hpsa_scan_finished,
621 .change_queue_depth = hpsa_change_queue_depth,
622 .this_id = -1,
623 .use_clustering = ENABLE_CLUSTERING,
75167d2c 624 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 625 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
626 .ioctl = hpsa_ioctl,
627 .slave_alloc = hpsa_slave_alloc,
628 .slave_destroy = hpsa_slave_destroy,
629#ifdef CONFIG_COMPAT
630 .compat_ioctl = hpsa_compat_ioctl,
631#endif
632 .sdev_attrs = hpsa_sdev_attrs,
633 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 634 .max_sectors = 8192,
54b2b50c 635 .no_write_same = 1,
3f5eac3a
SC		 636};
637
638
639/* Enqueuing and dequeuing functions for cmdlists. */
640static inline void addQ(struct list_head *list, struct CommandList *c)
641{
642 list_add_tail(&c->list, list);
643}
644
254f796b 645static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 646{
647 u32 a;
254f796b 648 struct reply_pool *rq = &h->reply_queue[q];
e16a33ad 649 unsigned long flags;
3f5eac3a 650
e1f7de0c
MG		 651 if (h->transMethod & CFGTBL_Trans_io_accel1)
652 return h->access.command_completed(h, q);
653
3f5eac3a 654 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 655 return h->access.command_completed(h, q);
3f5eac3a 656
254f796b
MG		 657 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
658 a = rq->head[rq->current_entry];
659 rq->current_entry++;
e16a33ad 660 spin_lock_irqsave(&h->lock, flags);
3f5eac3a 661 h->commands_outstanding--;
e16a33ad 662 spin_unlock_irqrestore(&h->lock, flags);
3f5eac3a
SC		 663 } else {
664 a = FIFO_EMPTY;
665 }
666 /* Check for wraparound */
254f796b
MG		 667 if (rq->current_entry == h->max_commands) {
668 rq->current_entry = 0;
669 rq->wraparound ^= 1;
3f5eac3a
SC		 670 }
671 return a;
672}
673
c349775e
ST		 674/*
675 * There are some special bits in the bus address of the
676 * command that we have to set for the controller to know
677 * how to process the command:
678 *
679 * Normal performant mode:
680 * bit 0: 1 means performant mode, 0 means simple mode.
681 * bits 1-3 = block fetch table entry
682 * bits 4-6 = command type (== 0)
683 *
684 * ioaccel1 mode:
685 * bit 0 = "performant mode" bit.
686 * bits 1-3 = block fetch table entry
687 * bits 4-6 = command type (== 110)
688 * (command type is needed because ioaccel1 mode
689 * commands are submitted through the same register as normal
690 * mode commands, so this is how the controller knows whether
691 * the command is normal mode or ioaccel1 mode.)
692 *
693 * ioaccel2 mode:
694 * bit 0 = "performant mode" bit.
695 * bits 1-4 = block fetch table entry (note extra bit)
696 * bits 4-6 = not needed, because ioaccel2 mode has
697 * a separate special register for submitting commands.
698 */
699
3f5eac3a
SC		 700/* set_performant_mode: Modify the tag for cciss performant
701 * set bit 0 for pull model, bits 3-1 for block fetch
702 * register number
703 */
704static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
705{
254f796b 706 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 707 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 708 if (likely(h->msix_vector > 0))
254f796b 709 c->Header.ReplyQueue =
804a5cb5 710 raw_smp_processor_id() % h->nreply_queues;
254f796b 711 }
3f5eac3a
SC		 712}
713
c349775e
ST		 714static void set_ioaccel1_performant_mode(struct ctlr_info *h,
715 struct CommandList *c)
716{
717 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
718
719 /* Tell the controller to post the reply to the queue for this
720 * processor. This seems to give the best I/O throughput.
721 */
722 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
723 /* Set the bits in the address sent down to include:
724 * - performant mode bit (bit 0)
725 * - pull count (bits 1-3)
726 * - command type (bits 4-6)
727 */
728 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
729 IOACCEL1_BUSADDR_CMDTYPE;
730}
731
732static void set_ioaccel2_performant_mode(struct ctlr_info *h,
733 struct CommandList *c)
734{
735 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
736
737 /* Tell the controller to post the reply to the queue for this
738 * processor. This seems to give the best I/O throughput.
739 */
740 cp->reply_queue = smp_processor_id() % h->nreply_queues;
741 /* Set the bits in the address sent down to include:
742 * - performant mode bit not used in ioaccel mode 2
743 * - pull count (bits 0-3)
744 * - command type isn't needed for ioaccel2
745 */
746 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
747}
748
e85c5974
SC		 749static int is_firmware_flash_cmd(u8 *cdb)
750{
751 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
752}
753
754/*
755 * During firmware flash, the heartbeat register may not update as frequently
756 * as it should. So we dial down lockup detection during firmware flash. and
757 * dial it back up when firmware flash completes.
758 */
759#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
760#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
761static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
762 struct CommandList *c)
763{
764 if (!is_firmware_flash_cmd(c->Request.CDB))
765 return;
766 atomic_inc(&h->firmware_flash_in_progress);
767 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
768}
769
770static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
771 struct CommandList *c)
772{
773 if (is_firmware_flash_cmd(c->Request.CDB) &&
774 atomic_dec_and_test(&h->firmware_flash_in_progress))
775 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
776}
777
3f5eac3a
SC		 778static void enqueue_cmd_and_start_io(struct ctlr_info *h,
779 struct CommandList *c)
780{
781 unsigned long flags;
782
c349775e
ST		 783 switch (c->cmd_type) {
784 case CMD_IOACCEL1:
785 set_ioaccel1_performant_mode(h, c);
786 break;
787 case CMD_IOACCEL2:
788 set_ioaccel2_performant_mode(h, c);
789 break;
790 default:
791 set_performant_mode(h, c);
792 }
e85c5974 793 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 794 spin_lock_irqsave(&h->lock, flags);
795 addQ(&h->reqQ, c);
796 h->Qdepth++;
3f5eac3a 797 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 798 start_io(h);
3f5eac3a
SC		 799}
800
801static inline void removeQ(struct CommandList *c)
802{
803 if (WARN_ON(list_empty(&c->list)))
804 return;
805 list_del_init(&c->list);
806}
807
808static inline int is_hba_lunid(unsigned char scsi3addr[])
809{
810 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
811}
812
813static inline int is_scsi_rev_5(struct ctlr_info *h)
814{
815 if (!h->hba_inquiry_data)
816 return 0;
817 if ((h->hba_inquiry_data[2] & 0x07) == 5)
818 return 1;
819 return 0;
820}
821
edd16368
SC		 822static int hpsa_find_target_lun(struct ctlr_info *h,
823 unsigned char scsi3addr[], int bus, int *target, int *lun)
824{
825 /* finds an unused bus, target, lun for a new physical device
826 * assumes h->devlock is held
827 */
828 int i, found = 0;
cfe5badc 829 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 830
263d9401 831 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 832
833 for (i = 0; i < h->ndevices; i++) {
834 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 835 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 836 }
837
263d9401
AM		 838 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
839 if (i < HPSA_MAX_DEVICES) {
840 /* *bus = 1; */
841 *target = i;
842 *lun = 0;
843 found = 1;
edd16368
SC		 844 }
845 return !found;
846}
847
848/* Add an entry into h->dev[] array. */
849static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
850 struct hpsa_scsi_dev_t *device,
851 struct hpsa_scsi_dev_t *added[], int *nadded)
852{
853 /* assumes h->devlock is held */
854 int n = h->ndevices;
855 int i;
856 unsigned char addr1[8], addr2[8];
857 struct hpsa_scsi_dev_t *sd;
858
cfe5badc 859 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 860 dev_err(&h->pdev->dev, "too many devices, some will be "
861 "inaccessible.\n");
862 return -1;
863 }
864
865 /* physical devices do not have lun or target assigned until now. */
866 if (device->lun != -1)
867 /* Logical device, lun is already assigned. */
868 goto lun_assigned;
869
870 /* If this device a non-zero lun of a multi-lun device
871 * byte 4 of the 8-byte LUN addr will contain the logical
872 * unit no, zero otherise.
873 */
874 if (device->scsi3addr[4] == 0) {
875 /* This is not a non-zero lun of a multi-lun device */
876 if (hpsa_find_target_lun(h, device->scsi3addr,
877 device->bus, &device->target, &device->lun) != 0)
878 return -1;
879 goto lun_assigned;
880 }
881
882 /* This is a non-zero lun of a multi-lun device.
883 * Search through our list and find the device which
884 * has the same 8 byte LUN address, excepting byte 4.
885 * Assign the same bus and target for this new LUN.
886 * Use the logical unit number from the firmware.
887 */
888 memcpy(addr1, device->scsi3addr, 8);
889 addr1[4] = 0;
890 for (i = 0; i < n; i++) {
891 sd = h->dev[i];
892 memcpy(addr2, sd->scsi3addr, 8);
893 addr2[4] = 0;
894 /* differ only in byte 4? */
895 if (memcmp(addr1, addr2, 8) == 0) {
896 device->bus = sd->bus;
897 device->target = sd->target;
898 device->lun = device->scsi3addr[4];
899 break;
900 }
901 }
902 if (device->lun == -1) {
903 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
904 " suspect firmware bug or unsupported hardware "
905 "configuration.\n");
906 return -1;
907 }
908
909lun_assigned:
910
911 h->dev[n] = device;
912 h->ndevices++;
913 added[*nadded] = device;
914 (*nadded)++;
915
916 /* initially, (before registering with scsi layer) we don't
917 * know our hostno and we don't want to print anything first
918 * time anyway (the scsi layer's inquiries will show that info)
919 */
920 /* if (hostno != -1) */
921 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
922 scsi_device_type(device->devtype), hostno,
923 device->bus, device->target, device->lun);
924 return 0;
925}
926
bd9244f7
ST		 927/* Update an entry in h->dev[] array. */
928static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
929 int entry, struct hpsa_scsi_dev_t *new_entry)
930{
931 /* assumes h->devlock is held */
932 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
933
934 /* Raid level changed. */
935 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 936
937 /* Raid offload parameters changed. */
938 h->dev[entry]->offload_config = new_entry->offload_config;
939 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
9fb0de2d
SC		 940 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
941 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
942 h->dev[entry]->raid_map = new_entry->raid_map;
250fb125 943
bd9244f7
ST		 944 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
945 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
946 new_entry->target, new_entry->lun);
947}
948
2a8ccf31
SC		 949/* Replace an entry from h->dev[] array. */
950static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
951 int entry, struct hpsa_scsi_dev_t *new_entry,
952 struct hpsa_scsi_dev_t *added[], int *nadded,
953 struct hpsa_scsi_dev_t *removed[], int *nremoved)
954{
955 /* assumes h->devlock is held */
cfe5badc 956 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 957 removed[*nremoved] = h->dev[entry];
958 (*nremoved)++;
01350d05
SC		 959
960 /*
961 * New physical devices won't have target/lun assigned yet
962 * so we need to preserve the values in the slot we are replacing.
963 */
964 if (new_entry->target == -1) {
965 new_entry->target = h->dev[entry]->target;
966 new_entry->lun = h->dev[entry]->lun;
967 }
968
2a8ccf31
SC		 969 h->dev[entry] = new_entry;
970 added[*nadded] = new_entry;
971 (*nadded)++;
972 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
973 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
974 new_entry->target, new_entry->lun);
975}
976
edd16368
SC		 977/* Remove an entry from h->dev[] array. */
978static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
979 struct hpsa_scsi_dev_t *removed[], int *nremoved)
980{
981 /* assumes h->devlock is held */
982 int i;
983 struct hpsa_scsi_dev_t *sd;
984
cfe5badc 985 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 986
987 sd = h->dev[entry];
988 removed[*nremoved] = h->dev[entry];
989 (*nremoved)++;
990
991 for (i = entry; i < h->ndevices-1; i++)
992 h->dev[i] = h->dev[i+1];
993 h->ndevices--;
994 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
995 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
996 sd->lun);
997}
998
999#define SCSI3ADDR_EQ(a, b) ( \
1000 (a)[7] == (b)[7] && \
1001 (a)[6] == (b)[6] && \
1002 (a)[5] == (b)[5] && \
1003 (a)[4] == (b)[4] && \
1004 (a)[3] == (b)[3] && \
1005 (a)[2] == (b)[2] && \
1006 (a)[1] == (b)[1] && \
1007 (a)[0] == (b)[0])
1008
1009static void fixup_botched_add(struct ctlr_info *h,
1010 struct hpsa_scsi_dev_t *added)
1011{
1012 /* called when scsi_add_device fails in order to re-adjust
1013 * h->dev[] to match the mid layer's view.
1014 */
1015 unsigned long flags;
1016 int i, j;
1017
1018 spin_lock_irqsave(&h->lock, flags);
1019 for (i = 0; i < h->ndevices; i++) {
1020 if (h->dev[i] == added) {
1021 for (j = i; j < h->ndevices-1; j++)
1022 h->dev[j] = h->dev[j+1];
1023 h->ndevices--;
1024 break;
1025 }
1026 }
1027 spin_unlock_irqrestore(&h->lock, flags);
1028 kfree(added);
1029}
1030
1031static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1032 struct hpsa_scsi_dev_t *dev2)
1033{
edd16368
SC		 1034 /* we compare everything except lun and target as these
1035 * are not yet assigned. Compare parts likely
1036 * to differ first
1037 */
1038 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1039 sizeof(dev1->scsi3addr)) != 0)
1040 return 0;
1041 if (memcmp(dev1->device_id, dev2->device_id,
1042 sizeof(dev1->device_id)) != 0)
1043 return 0;
1044 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1045 return 0;
1046 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1047 return 0;
edd16368
SC		 1048 if (dev1->devtype != dev2->devtype)
1049 return 0;
edd16368
SC		 1050 if (dev1->bus != dev2->bus)
1051 return 0;
1052 return 1;
1053}
1054
bd9244f7
ST		 1055static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1056 struct hpsa_scsi_dev_t *dev2)
1057{
1058 /* Device attributes that can change, but don't mean
1059 * that the device is a different device, nor that the OS
1060 * needs to be told anything about the change.
1061 */
1062 if (dev1->raid_level != dev2->raid_level)
1063 return 1;
250fb125
SC		 1064 if (dev1->offload_config != dev2->offload_config)
1065 return 1;
1066 if (dev1->offload_enabled != dev2->offload_enabled)
1067 return 1;
bd9244f7
ST		 1068 return 0;
1069}
1070
edd16368
SC		 1071/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1072 * and return needle location in *index. If scsi3addr matches, but not
1073 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1074 * location in *index.
1075 * In the case of a minor device attribute change, such as RAID level, just
1076 * return DEVICE_UPDATED, along with the updated device's location in index.
1077 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1078 */
1079static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1080 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1081 int *index)
1082{
1083 int i;
1084#define DEVICE_NOT_FOUND 0
1085#define DEVICE_CHANGED 1
1086#define DEVICE_SAME 2
bd9244f7 1087#define DEVICE_UPDATED 3
edd16368 1088 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1089 if (haystack[i] == NULL) /* previously removed. */
1090 continue;
edd16368
SC		 1091 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1092 *index = i;
bd9244f7
ST		 1093 if (device_is_the_same(needle, haystack[i])) {
1094 if (device_updated(needle, haystack[i]))
1095 return DEVICE_UPDATED;
edd16368 1096 return DEVICE_SAME;
bd9244f7 1097 } else {
edd16368 1098 return DEVICE_CHANGED;
bd9244f7 1099 }
edd16368
SC		 1100 }
1101 }
1102 *index = -1;
1103 return DEVICE_NOT_FOUND;
1104}
1105
4967bd3e 1106static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1107 struct hpsa_scsi_dev_t *sd[], int nsds)
1108{
1109 /* sd contains scsi3 addresses and devtypes, and inquiry
1110 * data. This function takes what's in sd to be the current
1111 * reality and updates h->dev[] to reflect that reality.
1112 */
1113 int i, entry, device_change, changes = 0;
1114 struct hpsa_scsi_dev_t *csd;
1115 unsigned long flags;
1116 struct hpsa_scsi_dev_t **added, **removed;
1117 int nadded, nremoved;
1118 struct Scsi_Host *sh = NULL;
1119
cfe5badc
ST		 1120 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1121 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1122
1123 if (!added || !removed) {
1124 dev_warn(&h->pdev->dev, "out of memory in "
1125 "adjust_hpsa_scsi_table\n");
1126 goto free_and_out;
1127 }
1128
1129 spin_lock_irqsave(&h->devlock, flags);
1130
1131 /* find any devices in h->dev[] that are not in
1132 * sd[] and remove them from h->dev[], and for any
1133 * devices which have changed, remove the old device
1134 * info and add the new device info.
bd9244f7
ST		 1135 * If minor device attributes change, just update
1136 * the existing device structure.
edd16368
SC		 1137 */
1138 i = 0;
1139 nremoved = 0;
1140 nadded = 0;
1141 while (i < h->ndevices) {
1142 csd = h->dev[i];
1143 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1144 if (device_change == DEVICE_NOT_FOUND) {
1145 changes++;
1146 hpsa_scsi_remove_entry(h, hostno, i,
1147 removed, &nremoved);
1148 continue; /* remove ^^^, hence i not incremented */
1149 } else if (device_change == DEVICE_CHANGED) {
1150 changes++;
2a8ccf31
SC		 1151 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1152 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1153 /* Set it to NULL to prevent it from being freed
1154 * at the bottom of hpsa_update_scsi_devices()
1155 */
1156 sd[entry] = NULL;
bd9244f7
ST		 1157 } else if (device_change == DEVICE_UPDATED) {
1158 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1159 }
1160 i++;
1161 }
1162
1163 /* Now, make sure every device listed in sd[] is also
1164 * listed in h->dev[], adding them if they aren't found
1165 */
1166
1167 for (i = 0; i < nsds; i++) {
1168 if (!sd[i]) /* if already added above. */
1169 continue;
1170 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1171 h->ndevices, &entry);
1172 if (device_change == DEVICE_NOT_FOUND) {
1173 changes++;
1174 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1175 added, &nadded) != 0)
1176 break;
1177 sd[i] = NULL; /* prevent from being freed later. */
1178 } else if (device_change == DEVICE_CHANGED) {
1179 /* should never happen... */
1180 changes++;
1181 dev_warn(&h->pdev->dev,
1182 "device unexpectedly changed.\n");
1183 /* but if it does happen, we just ignore that device */
1184 }
1185 }
1186 spin_unlock_irqrestore(&h->devlock, flags);
1187
1188 /* Don't notify scsi mid layer of any changes the first time through
1189 * (or if there are no changes) scsi_scan_host will do it later the
1190 * first time through.
1191 */
1192 if (hostno == -1 || !changes)
1193 goto free_and_out;
1194
1195 sh = h->scsi_host;
1196 /* Notify scsi mid layer of any removed devices */
1197 for (i = 0; i < nremoved; i++) {
1198 struct scsi_device *sdev =
1199 scsi_device_lookup(sh, removed[i]->bus,
1200 removed[i]->target, removed[i]->lun);
1201 if (sdev != NULL) {
1202 scsi_remove_device(sdev);
1203 scsi_device_put(sdev);
1204 } else {
1205 /* We don't expect to get here.
1206 * future cmds to this device will get selection
1207 * timeout as if the device was gone.
1208 */
1209 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1210 " for removal.", hostno, removed[i]->bus,
1211 removed[i]->target, removed[i]->lun);
1212 }
1213 kfree(removed[i]);
1214 removed[i] = NULL;
1215 }
1216
1217 /* Notify scsi mid layer of any added devices */
1218 for (i = 0; i < nadded; i++) {
1219 if (scsi_add_device(sh, added[i]->bus,
1220 added[i]->target, added[i]->lun) == 0)
1221 continue;
1222 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1223 "device not added.\n", hostno, added[i]->bus,
1224 added[i]->target, added[i]->lun);
1225 /* now we have to remove it from h->dev,
1226 * since it didn't get added to scsi mid layer
1227 */
1228 fixup_botched_add(h, added[i]);
1229 }
1230
1231free_and_out:
1232 kfree(added);
1233 kfree(removed);
edd16368
SC		 1234}
1235
1236/*
9e03aa2f 1237 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1238 * Assume's h->devlock is held.
1239 */
1240static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1241 int bus, int target, int lun)
1242{
1243 int i;
1244 struct hpsa_scsi_dev_t *sd;
1245
1246 for (i = 0; i < h->ndevices; i++) {
1247 sd = h->dev[i];
1248 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1249 return sd;
1250 }
1251 return NULL;
1252}
1253
1254/* link sdev->hostdata to our per-device structure. */
1255static int hpsa_slave_alloc(struct scsi_device *sdev)
1256{
1257 struct hpsa_scsi_dev_t *sd;
1258 unsigned long flags;
1259 struct ctlr_info *h;
1260
1261 h = sdev_to_hba(sdev);
1262 spin_lock_irqsave(&h->devlock, flags);
1263 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1264 sdev_id(sdev), sdev->lun);
1265 if (sd != NULL)
1266 sdev->hostdata = sd;
1267 spin_unlock_irqrestore(&h->devlock, flags);
1268 return 0;
1269}
1270
1271static void hpsa_slave_destroy(struct scsi_device *sdev)
1272{
bcc44255 1273 /* nothing to do. */
edd16368
SC		 1274}
1275
33a2ffce
SC		 1276static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1277{
1278 int i;
1279
1280 if (!h->cmd_sg_list)
1281 return;
1282 for (i = 0; i < h->nr_cmds; i++) {
1283 kfree(h->cmd_sg_list[i]);
1284 h->cmd_sg_list[i] = NULL;
1285 }
1286 kfree(h->cmd_sg_list);
1287 h->cmd_sg_list = NULL;
1288}
1289
1290static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1291{
1292 int i;
1293
1294 if (h->chainsize <= 0)
1295 return 0;
1296
1297 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1298 GFP_KERNEL);
1299 if (!h->cmd_sg_list)
1300 return -ENOMEM;
1301 for (i = 0; i < h->nr_cmds; i++) {
1302 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1303 h->chainsize, GFP_KERNEL);
1304 if (!h->cmd_sg_list[i])
1305 goto clean;
1306 }
1307 return 0;
1308
1309clean:
1310 hpsa_free_sg_chain_blocks(h);
1311 return -ENOMEM;
1312}
1313
e2bea6df 1314static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1315 struct CommandList *c)
1316{
1317 struct SGDescriptor *chain_sg, *chain_block;
1318 u64 temp64;
1319
1320 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1321 chain_block = h->cmd_sg_list[c->cmdindex];
1322 chain_sg->Ext = HPSA_SG_CHAIN;
1323 chain_sg->Len = sizeof(*chain_sg) *
1324 (c->Header.SGTotal - h->max_cmd_sg_entries);
1325 temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
1326 PCI_DMA_TODEVICE);
e2bea6df
SC		 1327 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1328 /* prevent subsequent unmapping */
1329 chain_sg->Addr.lower = 0;
1330 chain_sg->Addr.upper = 0;
1331 return -1;
1332 }
33a2ffce
SC		 1333 chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
1334 chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
e2bea6df 1335 return 0;
33a2ffce
SC		 1336}
1337
1338static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1339 struct CommandList *c)
1340{
1341 struct SGDescriptor *chain_sg;
1342 union u64bit temp64;
1343
1344 if (c->Header.SGTotal <= h->max_cmd_sg_entries)
1345 return;
1346
1347 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1348 temp64.val32.lower = chain_sg->Addr.lower;
1349 temp64.val32.upper = chain_sg->Addr.upper;
1350 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
1351}
1352
c349775e
ST		 1353static void handle_ioaccel_mode2_error(struct ctlr_info *h,
1354 struct CommandList *c,
1355 struct scsi_cmnd *cmd,
1356 struct io_accel2_cmd *c2)
1357{
1358 int data_len;
1359
1360 switch (c2->error_data.serv_response) {
1361 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1362 switch (c2->error_data.status) {
1363 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1364 break;
1365 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1366 dev_warn(&h->pdev->dev,
1367 "%s: task complete with check condition.\n",
1368 "HP SSD Smart Path");
1369 if (c2->error_data.data_present !=
1370 IOACCEL2_SENSE_DATA_PRESENT)
1371 break;
1372 /* copy the sense data */
1373 data_len = c2->error_data.sense_data_len;
1374 if (data_len > SCSI_SENSE_BUFFERSIZE)
1375 data_len = SCSI_SENSE_BUFFERSIZE;
1376 if (data_len > sizeof(c2->error_data.sense_data_buff))
1377 data_len =
1378 sizeof(c2->error_data.sense_data_buff);
1379 memcpy(cmd->sense_buffer,
1380 c2->error_data.sense_data_buff, data_len);
1381 cmd->result |= SAM_STAT_CHECK_CONDITION;
1382 break;
1383 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1384 dev_warn(&h->pdev->dev,
1385 "%s: task complete with BUSY status.\n",
1386 "HP SSD Smart Path");
1387 break;
1388 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1389 dev_warn(&h->pdev->dev,
1390 "%s: task complete with reservation conflict.\n",
1391 "HP SSD Smart Path");
1392 break;
1393 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1394 /* Make scsi midlayer do unlimited retries */
1395 cmd->result = DID_IMM_RETRY << 16;
1396 break;
1397 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1398 dev_warn(&h->pdev->dev,
1399 "%s: task complete with aborted status.\n",
1400 "HP SSD Smart Path");
1401 break;
1402 default:
1403 dev_warn(&h->pdev->dev,
1404 "%s: task complete with unrecognized status: 0x%02x\n",
1405 "HP SSD Smart Path", c2->error_data.status);
1406 break;
1407 }
1408 break;
1409 case IOACCEL2_SERV_RESPONSE_FAILURE:
1410 /* don't expect to get here. */
1411 dev_warn(&h->pdev->dev,
1412 "unexpected delivery or target failure, status = 0x%02x\n",
1413 c2->error_data.status);
1414 break;
1415 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1416 break;
1417 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1418 break;
1419 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1420 dev_warn(&h->pdev->dev, "task management function rejected.\n");
1421 break;
1422 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1423 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1424 break;
1425 default:
1426 dev_warn(&h->pdev->dev,
1427 "%s: Unrecognized server response: 0x%02x\n",
1428 "HP SSD Smart Path", c2->error_data.serv_response);
1429 break;
1430 }
1431}
1432
1433static void process_ioaccel2_completion(struct ctlr_info *h,
1434 struct CommandList *c, struct scsi_cmnd *cmd,
1435 struct hpsa_scsi_dev_t *dev)
1436{
1437 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
1438
1439 /* check for good status */
1440 if (likely(c2->error_data.serv_response == 0 &&
1441 c2->error_data.status == 0)) {
1442 cmd_free(h, c);
1443 cmd->scsi_done(cmd);
1444 return;
1445 }
1446
1447 /* Any RAID offload error results in retry which will use
1448 * the normal I/O path so the controller can handle whatever's
1449 * wrong.
1450 */
1451 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1452 c2->error_data.serv_response ==
1453 IOACCEL2_SERV_RESPONSE_FAILURE) {
1454 if (c2->error_data.status !=
1455 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1456 dev_warn(&h->pdev->dev,
1457 "%s: Error 0x%02x, Retrying on standard path.\n",
1458 "HP SSD Smart Path", c2->error_data.status);
1459 dev->offload_enabled = 0;
1460 cmd->result = DID_SOFT_ERROR << 16;
1461 cmd_free(h, c);
1462 cmd->scsi_done(cmd);
1463 return;
1464 }
1465 handle_ioaccel_mode2_error(h, c, cmd, c2);
1466 cmd_free(h, c);
1467 cmd->scsi_done(cmd);
1468}
1469
1fb011fb 1470static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1471{
1472 struct scsi_cmnd *cmd;
1473 struct ctlr_info *h;
1474 struct ErrorInfo *ei;
283b4a9b 1475 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1476
1477 unsigned char sense_key;
1478 unsigned char asc; /* additional sense code */
1479 unsigned char ascq; /* additional sense code qualifier */
db111e18 1480 unsigned long sense_data_size;
edd16368
SC		 1481
1482 ei = cp->err_info;
1483 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1484 h = cp->h;
283b4a9b 1485 dev = cmd->device->hostdata;
edd16368
SC		 1486
1487 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c
MG		 1488 if ((cp->cmd_type == CMD_SCSI) &&
1489 (cp->Header.SGTotal > h->max_cmd_sg_entries))
33a2ffce 1490 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1491
1492 cmd->result = (DID_OK << 16); /* host byte */
1493 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1494
1495 if (cp->cmd_type == CMD_IOACCEL2)
1496 return process_ioaccel2_completion(h, cp, cmd, dev);
1497
5512672f 1498 cmd->result |= ei->ScsiStatus;
edd16368
SC		 1499
1500 /* copy the sense data whether we need to or not. */
db111e18
SC		 1501 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1502 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1503 else
1504 sense_data_size = sizeof(ei->SenseInfo);
1505 if (ei->SenseLen < sense_data_size)
1506 sense_data_size = ei->SenseLen;
1507
1508 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368
SC		 1509 scsi_set_resid(cmd, ei->ResidualCnt);
1510
1511 if (ei->CommandStatus == 0) {
edd16368 1512 cmd_free(h, cp);
2cc5bfaf 1513 cmd->scsi_done(cmd);
edd16368
SC		 1514 return;
1515 }
1516
e1f7de0c
MG		 1517 /* For I/O accelerator commands, copy over some fields to the normal
1518 * CISS header used below for error handling.
1519 */
1520 if (cp->cmd_type == CMD_IOACCEL1) {
1521 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
1522 cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd);
1523 cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK;
1524 cp->Header.Tag.lower = c->Tag.lower;
1525 cp->Header.Tag.upper = c->Tag.upper;
1526 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1527 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1528
1529 /* Any RAID offload error results in retry which will use
1530 * the normal I/O path so the controller can handle whatever's
1531 * wrong.
1532 */
1533 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1534 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1535 dev->offload_enabled = 0;
1536 cmd->result = DID_SOFT_ERROR << 16;
1537 cmd_free(h, cp);
1538 cmd->scsi_done(cmd);
1539 return;
1540 }
e1f7de0c
MG		 1541 }
1542
edd16368
SC		 1543 /* an error has occurred */
1544 switch (ei->CommandStatus) {
1545
1546 case CMD_TARGET_STATUS:
1547 if (ei->ScsiStatus) {
1548 /* Get sense key */
1549 sense_key = 0xf & ei->SenseInfo[2];
1550 /* Get additional sense code */
1551 asc = ei->SenseInfo[12];
1552 /* Get addition sense code qualifier */
1553 ascq = ei->SenseInfo[13];
1554 }
1555
1556 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
3ce438df 1557 if (check_for_unit_attention(h, cp))
edd16368 1558 break;
edd16368
SC		 1559 if (sense_key == ILLEGAL_REQUEST) {
1560 /*
1561 * SCSI REPORT_LUNS is commonly unsupported on
1562 * Smart Array. Suppress noisy complaint.
1563 */
1564 if (cp->Request.CDB[0] == REPORT_LUNS)
1565 break;
1566
1567 /* If ASC/ASCQ indicate Logical Unit
1568 * Not Supported condition,
1569 */
1570 if ((asc == 0x25) && (ascq == 0x0)) {
1571 dev_warn(&h->pdev->dev, "cp %p "
1572 "has check condition\n", cp);
1573 break;
1574 }
1575 }
1576
1577 if (sense_key == NOT_READY) {
1578 /* If Sense is Not Ready, Logical Unit
1579 * Not ready, Manual Intervention
1580 * required
1581 */
1582 if ((asc == 0x04) && (ascq == 0x03)) {
edd16368
SC		 1583 dev_warn(&h->pdev->dev, "cp %p "
1584 "has check condition: unit "
1585 "not ready, manual "
1586 "intervention required\n", cp);
1587 break;
1588 }
1589 }
1d3b3609
MG		 1590 if (sense_key == ABORTED_COMMAND) {
1591 /* Aborted command is retryable */
1592 dev_warn(&h->pdev->dev, "cp %p "
1593 "has check condition: aborted command: "
1594 "ASC: 0x%x, ASCQ: 0x%x\n",
1595 cp, asc, ascq);
2e311fba 1596 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1597 break;
1598 }
edd16368 1599 /* Must be some other type of check condition */
21b8e4ef 1600 dev_dbg(&h->pdev->dev, "cp %p has check condition: "
edd16368
SC		 1601 "unknown type: "
1602 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1603 "Returning result: 0x%x, "
1604 "cmd=[%02x %02x %02x %02x %02x "
807be732 1605 "%02x %02x %02x %02x %02x %02x "
edd16368
SC		 1606 "%02x %02x %02x %02x %02x]\n",
1607 cp, sense_key, asc, ascq,
1608 cmd->result,
1609 cmd->cmnd[0], cmd->cmnd[1],
1610 cmd->cmnd[2], cmd->cmnd[3],
1611 cmd->cmnd[4], cmd->cmnd[5],
1612 cmd->cmnd[6], cmd->cmnd[7],
807be732
MM		 1613 cmd->cmnd[8], cmd->cmnd[9],
1614 cmd->cmnd[10], cmd->cmnd[11],
1615 cmd->cmnd[12], cmd->cmnd[13],
1616 cmd->cmnd[14], cmd->cmnd[15]);
edd16368
SC		 1617 break;
1618 }
1619
1620
1621 /* Problem was not a check condition
1622 * Pass it up to the upper layers...
1623 */
1624 if (ei->ScsiStatus) {
1625 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1626 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1627 "Returning result: 0x%x\n",
1628 cp, ei->ScsiStatus,
1629 sense_key, asc, ascq,
1630 cmd->result);
1631 } else { /* scsi status is zero??? How??? */
1632 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1633 "Returning no connection.\n", cp),
1634
1635 /* Ordinarily, this case should never happen,
1636 * but there is a bug in some released firmware
1637 * revisions that allows it to happen if, for
1638 * example, a 4100 backplane loses power and
1639 * the tape drive is in it. We assume that
1640 * it's a fatal error of some kind because we
1641 * can't show that it wasn't. We will make it
1642 * look like selection timeout since that is
1643 * the most common reason for this to occur,
1644 * and it's severe enough.
1645 */
1646
1647 cmd->result = DID_NO_CONNECT << 16;
1648 }
1649 break;
1650
1651 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1652 break;
1653 case CMD_DATA_OVERRUN:
1654 dev_warn(&h->pdev->dev, "cp %p has"
1655 " completed with data overrun "
1656 "reported\n", cp);
1657 break;
1658 case CMD_INVALID: {
1659 /* print_bytes(cp, sizeof(*cp), 1, 0);
1660 print_cmd(cp); */
1661 /* We get CMD_INVALID if you address a non-existent device
1662 * instead of a selection timeout (no response). You will
1663 * see this if you yank out a drive, then try to access it.
1664 * This is kind of a shame because it means that any other
1665 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1666 * missing target. */
1667 cmd->result = DID_NO_CONNECT << 16;
1668 }
1669 break;
1670 case CMD_PROTOCOL_ERR:
256d0eaa 1671 cmd->result = DID_ERROR << 16;
edd16368 1672 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1673 "protocol error\n", cp);
edd16368
SC		 1674 break;
1675 case CMD_HARDWARE_ERR:
1676 cmd->result = DID_ERROR << 16;
1677 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1678 break;
1679 case CMD_CONNECTION_LOST:
1680 cmd->result = DID_ERROR << 16;
1681 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1682 break;
1683 case CMD_ABORTED:
1684 cmd->result = DID_ABORT << 16;
1685 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1686 cp, ei->ScsiStatus);
1687 break;
1688 case CMD_ABORT_FAILED:
1689 cmd->result = DID_ERROR << 16;
1690 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1691 break;
1692 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1693 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1694 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1695 "abort\n", cp);
1696 break;
1697 case CMD_TIMEOUT:
1698 cmd->result = DID_TIME_OUT << 16;
1699 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1700 break;
1d5e2ed0
SC		 1701 case CMD_UNABORTABLE:
1702 cmd->result = DID_ERROR << 16;
1703 dev_warn(&h->pdev->dev, "Command unabortable\n");
1704 break;
283b4a9b
SC		 1705 case CMD_IOACCEL_DISABLED:
1706 /* This only handles the direct pass-through case since RAID
1707 * offload is handled above. Just attempt a retry.
1708 */
1709 cmd->result = DID_SOFT_ERROR << 16;
1710 dev_warn(&h->pdev->dev,
1711 "cp %p had HP SSD Smart Path error\n", cp);
1712 break;
edd16368
SC		 1713 default:
1714 cmd->result = DID_ERROR << 16;
1715 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1716 cp, ei->CommandStatus);
1717 }
edd16368 1718 cmd_free(h, cp);
2cc5bfaf 1719 cmd->scsi_done(cmd);
edd16368
SC		 1720}
1721
edd16368
SC		 1722static void hpsa_pci_unmap(struct pci_dev *pdev,
1723 struct CommandList *c, int sg_used, int data_direction)
1724{
1725 int i;
1726 union u64bit addr64;
1727
1728 for (i = 0; i < sg_used; i++) {
1729 addr64.val32.lower = c->SG[i].Addr.lower;
1730 addr64.val32.upper = c->SG[i].Addr.upper;
1731 pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
1732 data_direction);
1733 }
1734}
1735
a2dac136 1736static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1737 struct CommandList *cp,
1738 unsigned char *buf,
1739 size_t buflen,
1740 int data_direction)
1741{
01a02ffc 1742 u64 addr64;
edd16368
SC		 1743
1744 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1745 cp->Header.SGList = 0;
1746 cp->Header.SGTotal = 0;
a2dac136 1747 return 0;
edd16368
SC		 1748 }
1749
01a02ffc 1750 addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1751 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1752 /* Prevent subsequent unmap of something never mapped */
eceaae18
SK		 1753 cp->Header.SGList = 0;
1754 cp->Header.SGTotal = 0;
a2dac136 1755 return -1;
eceaae18 1756 }
edd16368 1757 cp->SG[0].Addr.lower =
01a02ffc 1758 (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
edd16368 1759 cp->SG[0].Addr.upper =
01a02ffc 1760 (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
edd16368 1761 cp->SG[0].Len = buflen;
e1d9cbfa 1762 cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */
01a02ffc
SC		 1763 cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
1764 cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
a2dac136 1765 return 0;
edd16368
SC		 1766}
1767
1768static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1769 struct CommandList *c)
1770{
1771 DECLARE_COMPLETION_ONSTACK(wait);
1772
1773 c->waiting = &wait;
1774 enqueue_cmd_and_start_io(h, c);
1775 wait_for_completion(&wait);
1776}
1777
a0c12413
SC		 1778static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1779 struct CommandList *c)
1780{
1781 unsigned long flags;
1782
1783 /* If controller lockup detected, fake a hardware error. */
1784 spin_lock_irqsave(&h->lock, flags);
1785 if (unlikely(h->lockup_detected)) {
1786 spin_unlock_irqrestore(&h->lock, flags);
1787 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
1788 } else {
1789 spin_unlock_irqrestore(&h->lock, flags);
1790 hpsa_scsi_do_simple_cmd_core(h, c);
1791 }
1792}
1793
9c2fc160 1794#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 1795static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
1796 struct CommandList *c, int data_direction)
1797{
9c2fc160 1798 int backoff_time = 10, retry_count = 0;
edd16368
SC		 1799
1800 do {
7630abd0 1801 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 1802 hpsa_scsi_do_simple_cmd_core(h, c);
1803 retry_count++;
9c2fc160
SC		 1804 if (retry_count > 3) {
1805 msleep(backoff_time);
1806 if (backoff_time < 1000)
1807 backoff_time *= 2;
1808 }
852af20a 1809 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 1810 check_for_busy(h, c)) &&
1811 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 1812 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
1813}
1814
1815static void hpsa_scsi_interpret_error(struct CommandList *cp)
1816{
1817 struct ErrorInfo *ei;
1818 struct device *d = &cp->h->pdev->dev;
1819
1820 ei = cp->err_info;
1821 switch (ei->CommandStatus) {
1822 case CMD_TARGET_STATUS:
1823 dev_warn(d, "cmd %p has completed with errors\n", cp);
1824 dev_warn(d, "cmd %p has SCSI Status = %x\n", cp,
1825 ei->ScsiStatus);
1826 if (ei->ScsiStatus == 0)
1827 dev_warn(d, "SCSI status is abnormally zero. "
1828 "(probably indicates selection timeout "
1829 "reported incorrectly due to a known "
1830 "firmware bug, circa July, 2001.)\n");
1831 break;
1832 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1833 dev_info(d, "UNDERRUN\n");
1834 break;
1835 case CMD_DATA_OVERRUN:
1836 dev_warn(d, "cp %p has completed with data overrun\n", cp);
1837 break;
1838 case CMD_INVALID: {
1839 /* controller unfortunately reports SCSI passthru's
1840 * to non-existent targets as invalid commands.
1841 */
1842 dev_warn(d, "cp %p is reported invalid (probably means "
1843 "target device no longer present)\n", cp);
1844 /* print_bytes((unsigned char *) cp, sizeof(*cp), 1, 0);
1845 print_cmd(cp); */
1846 }
1847 break;
1848 case CMD_PROTOCOL_ERR:
1849 dev_warn(d, "cp %p has protocol error \n", cp);
1850 break;
1851 case CMD_HARDWARE_ERR:
1852 /* cmd->result = DID_ERROR << 16; */
1853 dev_warn(d, "cp %p had hardware error\n", cp);
1854 break;
1855 case CMD_CONNECTION_LOST:
1856 dev_warn(d, "cp %p had connection lost\n", cp);
1857 break;
1858 case CMD_ABORTED:
1859 dev_warn(d, "cp %p was aborted\n", cp);
1860 break;
1861 case CMD_ABORT_FAILED:
1862 dev_warn(d, "cp %p reports abort failed\n", cp);
1863 break;
1864 case CMD_UNSOLICITED_ABORT:
1865 dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp);
1866 break;
1867 case CMD_TIMEOUT:
1868 dev_warn(d, "cp %p timed out\n", cp);
1869 break;
1d5e2ed0
SC		 1870 case CMD_UNABORTABLE:
1871 dev_warn(d, "Command unabortable\n");
1872 break;
edd16368
SC		 1873 default:
1874 dev_warn(d, "cp %p returned unknown status %x\n", cp,
1875 ei->CommandStatus);
1876 }
1877}
1878
1879static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
1880 unsigned char page, unsigned char *buf,
1881 unsigned char bufsize)
1882{
1883 int rc = IO_OK;
1884 struct CommandList *c;
1885 struct ErrorInfo *ei;
1886
1887 c = cmd_special_alloc(h);
1888
1889 if (c == NULL) { /* trouble... */
1890 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
ecd9aad4 1891 return -ENOMEM;
edd16368
SC		 1892 }
1893
a2dac136
SC		 1894 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
1895 page, scsi3addr, TYPE_CMD)) {
1896 rc = -1;
1897 goto out;
1898 }
edd16368
SC		 1899 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
1900 ei = c->err_info;
1901 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
1902 hpsa_scsi_interpret_error(c);
1903 rc = -1;
1904 }
a2dac136 1905out:
edd16368
SC		 1906 cmd_special_free(h, c);
1907 return rc;
1908}
1909
bf711ac6
ST		 1910static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
1911 u8 reset_type)
edd16368
SC		 1912{
1913 int rc = IO_OK;
1914 struct CommandList *c;
1915 struct ErrorInfo *ei;
1916
1917 c = cmd_special_alloc(h);
1918
1919 if (c == NULL) { /* trouble... */
1920 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
e9ea04a6 1921 return -ENOMEM;
edd16368
SC		 1922 }
1923
a2dac136 1924 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 1925 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
1926 scsi3addr, TYPE_MSG);
1927 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 1928 hpsa_scsi_do_simple_cmd_core(h, c);
1929 /* no unmap needed here because no data xfer. */
1930
1931 ei = c->err_info;
1932 if (ei->CommandStatus != 0) {
1933 hpsa_scsi_interpret_error(c);
1934 rc = -1;
1935 }
1936 cmd_special_free(h, c);
1937 return rc;
1938}
1939
1940static void hpsa_get_raid_level(struct ctlr_info *h,
1941 unsigned char *scsi3addr, unsigned char *raid_level)
1942{
1943 int rc;
1944 unsigned char *buf;
1945
1946 *raid_level = RAID_UNKNOWN;
1947 buf = kzalloc(64, GFP_KERNEL);
1948 if (!buf)
1949 return;
1950 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0xC1, buf, 64);
1951 if (rc == 0)
1952 *raid_level = buf[8];
1953 if (*raid_level > RAID_UNKNOWN)
1954 *raid_level = RAID_UNKNOWN;
1955 kfree(buf);
1956 return;
1957}
1958
283b4a9b
SC		 1959#define HPSA_MAP_DEBUG
1960#ifdef HPSA_MAP_DEBUG
1961static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
1962 struct raid_map_data *map_buff)
1963{
1964 struct raid_map_disk_data *dd = &map_buff->data[0];
1965 int map, row, col;
1966 u16 map_cnt, row_cnt, disks_per_row;
1967
1968 if (rc != 0)
1969 return;
1970
1971 dev_info(&h->pdev->dev, "structure_size = %u\n",
1972 le32_to_cpu(map_buff->structure_size));
1973 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
1974 le32_to_cpu(map_buff->volume_blk_size));
1975 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
1976 le64_to_cpu(map_buff->volume_blk_cnt));
1977 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
1978 map_buff->phys_blk_shift);
1979 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
1980 map_buff->parity_rotation_shift);
1981 dev_info(&h->pdev->dev, "strip_size = %u\n",
1982 le16_to_cpu(map_buff->strip_size));
1983 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
1984 le64_to_cpu(map_buff->disk_starting_blk));
1985 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
1986 le64_to_cpu(map_buff->disk_blk_cnt));
1987 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
1988 le16_to_cpu(map_buff->data_disks_per_row));
1989 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
1990 le16_to_cpu(map_buff->metadata_disks_per_row));
1991 dev_info(&h->pdev->dev, "row_cnt = %u\n",
1992 le16_to_cpu(map_buff->row_cnt));
1993 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
1994 le16_to_cpu(map_buff->layout_map_count));
1995
1996 map_cnt = le16_to_cpu(map_buff->layout_map_count);
1997 for (map = 0; map < map_cnt; map++) {
1998 dev_info(&h->pdev->dev, "Map%u:\n", map);
1999 row_cnt = le16_to_cpu(map_buff->row_cnt);
2000 for (row = 0; row < row_cnt; row++) {
2001 dev_info(&h->pdev->dev, " Row%u:\n", row);
2002 disks_per_row =
2003 le16_to_cpu(map_buff->data_disks_per_row);
2004 for (col = 0; col < disks_per_row; col++, dd++)
2005 dev_info(&h->pdev->dev,
2006 " D%02u: h=0x%04x xor=%u,%u\n",
2007 col, dd->ioaccel_handle,
2008 dd->xor_mult[0], dd->xor_mult[1]);
2009 disks_per_row =
2010 le16_to_cpu(map_buff->metadata_disks_per_row);
2011 for (col = 0; col < disks_per_row; col++, dd++)
2012 dev_info(&h->pdev->dev,
2013 " M%02u: h=0x%04x xor=%u,%u\n",
2014 col, dd->ioaccel_handle,
2015 dd->xor_mult[0], dd->xor_mult[1]);
2016 }
2017 }
2018}
2019#else
2020static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2021 __attribute__((unused)) int rc,
2022 __attribute__((unused)) struct raid_map_data *map_buff)
2023{
2024}
2025#endif
2026
2027static int hpsa_get_raid_map(struct ctlr_info *h,
2028 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2029{
2030 int rc = 0;
2031 struct CommandList *c;
2032 struct ErrorInfo *ei;
2033
2034 c = cmd_special_alloc(h);
2035 if (c == NULL) {
2036 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2037 return -ENOMEM;
2038 }
2039 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2040 sizeof(this_device->raid_map), 0,
2041 scsi3addr, TYPE_CMD)) {
2042 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
2043 cmd_special_free(h, c);
2044 return -ENOMEM;
2045 }
2046 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2047 ei = c->err_info;
2048 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2049 hpsa_scsi_interpret_error(c);
2050 cmd_special_free(h, c);
2051 return -1;
2052 }
2053 cmd_special_free(h, c);
2054
2055 /* @todo in the future, dynamically allocate RAID map memory */
2056 if (le32_to_cpu(this_device->raid_map.structure_size) >
2057 sizeof(this_device->raid_map)) {
2058 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2059 rc = -1;
2060 }
2061 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2062 return rc;
2063}
2064
2065static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2066 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2067{
2068 int rc;
2069 unsigned char *buf;
2070 u8 ioaccel_status;
2071
2072 this_device->offload_config = 0;
2073 this_device->offload_enabled = 0;
2074
2075 buf = kzalloc(64, GFP_KERNEL);
2076 if (!buf)
2077 return;
2078 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2079 HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
2080 if (rc != 0)
2081 goto out;
2082
2083#define IOACCEL_STATUS_BYTE 4
2084#define OFFLOAD_CONFIGURED_BIT 0x01
2085#define OFFLOAD_ENABLED_BIT 0x02
2086 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2087 this_device->offload_config =
2088 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2089 if (this_device->offload_config) {
2090 this_device->offload_enabled =
2091 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2092 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2093 this_device->offload_enabled = 0;
2094 }
2095out:
2096 kfree(buf);
2097 return;
2098}
2099
edd16368
SC		 2100/* Get the device id from inquiry page 0x83 */
2101static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2102 unsigned char *device_id, int buflen)
2103{
2104 int rc;
2105 unsigned char *buf;
2106
2107 if (buflen > 16)
2108 buflen = 16;
2109 buf = kzalloc(64, GFP_KERNEL);
2110 if (!buf)
2111 return -1;
2112 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0x83, buf, 64);
2113 if (rc == 0)
2114 memcpy(device_id, &buf[8], buflen);
2115 kfree(buf);
2116 return rc != 0;
2117}
2118
2119static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2120 struct ReportLUNdata *buf, int bufsize,
2121 int extended_response)
2122{
2123 int rc = IO_OK;
2124 struct CommandList *c;
2125 unsigned char scsi3addr[8];
2126 struct ErrorInfo *ei;
2127
2128 c = cmd_special_alloc(h);
2129 if (c == NULL) { /* trouble... */
2130 dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2131 return -1;
2132 }
e89c0ae7
SC		 2133 /* address the controller */
2134 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2135 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2136 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2137 rc = -1;
2138 goto out;
2139 }
edd16368
SC		 2140 if (extended_response)
2141 c->Request.CDB[1] = extended_response;
2142 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2143 ei = c->err_info;
2144 if (ei->CommandStatus != 0 &&
2145 ei->CommandStatus != CMD_DATA_UNDERRUN) {
2146 hpsa_scsi_interpret_error(c);
2147 rc = -1;
283b4a9b
SC		 2148 } else {
2149 if (buf->extended_response_flag != extended_response) {
2150 dev_err(&h->pdev->dev,
2151 "report luns requested format %u, got %u\n",
2152 extended_response,
2153 buf->extended_response_flag);
2154 rc = -1;
2155 }
edd16368 2156 }
a2dac136 2157out:
edd16368
SC		 2158 cmd_special_free(h, c);
2159 return rc;
2160}
2161
2162static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2163 struct ReportLUNdata *buf,
2164 int bufsize, int extended_response)
2165{
2166 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2167}
2168
2169static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2170 struct ReportLUNdata *buf, int bufsize)
2171{
2172 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2173}
2174
2175static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2176 int bus, int target, int lun)
2177{
2178 device->bus = bus;
2179 device->target = target;
2180 device->lun = lun;
2181}
2182
2183static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2184 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2185 unsigned char *is_OBDR_device)
edd16368 2186{
0b0e1d6c
SC		 2187
2188#define OBDR_SIG_OFFSET 43
2189#define OBDR_TAPE_SIG "$DR-10"
2190#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2191#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2192
ea6d3bc3 2193 unsigned char *inq_buff;
0b0e1d6c 2194 unsigned char *obdr_sig;
edd16368 2195
ea6d3bc3 2196 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2197 if (!inq_buff)
2198 goto bail_out;
2199
edd16368
SC		 2200 /* Do an inquiry to the device to see what it is. */
2201 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2202 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2203 /* Inquiry failed (msg printed already) */
2204 dev_err(&h->pdev->dev,
2205 "hpsa_update_device_info: inquiry failed\n");
2206 goto bail_out;
2207 }
2208
edd16368
SC		 2209 this_device->devtype = (inq_buff[0] & 0x1f);
2210 memcpy(this_device->scsi3addr, scsi3addr, 8);
2211 memcpy(this_device->vendor, &inq_buff[8],
2212 sizeof(this_device->vendor));
2213 memcpy(this_device->model, &inq_buff[16],
2214 sizeof(this_device->model));
edd16368
SC		 2215 memset(this_device->device_id, 0,
2216 sizeof(this_device->device_id));
2217 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2218 sizeof(this_device->device_id));
2219
2220 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2221 is_logical_dev_addr_mode(scsi3addr)) {
edd16368 2222 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2223 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2224 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
2225 } else {
edd16368 2226 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2227 this_device->offload_config = 0;
2228 this_device->offload_enabled = 0;
2229 }
edd16368 2230
0b0e1d6c
SC		 2231 if (is_OBDR_device) {
2232 /* See if this is a One-Button-Disaster-Recovery device
2233 * by looking for "$DR-10" at offset 43 in inquiry data.
2234 */
2235 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2236 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2237 strncmp(obdr_sig, OBDR_TAPE_SIG,
2238 OBDR_SIG_LEN) == 0);
2239 }
2240
edd16368
SC		 2241 kfree(inq_buff);
2242 return 0;
2243
2244bail_out:
2245 kfree(inq_buff);
2246 return 1;
2247}
2248
4f4eb9f1 2249static unsigned char *ext_target_model[] = {
edd16368
SC		 2250 "MSA2012",
2251 "MSA2024",
2252 "MSA2312",
2253 "MSA2324",
fda38518 2254 "P2000 G3 SAS",
e06c8e5c 2255 "MSA 2040 SAS",
edd16368
SC		 2256 NULL,
2257};
2258
4f4eb9f1 2259static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2260{
2261 int i;
2262
4f4eb9f1
ST		 2263 for (i = 0; ext_target_model[i]; i++)
2264 if (strncmp(device->model, ext_target_model[i],
2265 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2266 return 1;
2267 return 0;
2268}
2269
2270/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2271 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2272 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2273 * Logical drive target and lun are assigned at this time, but
2274 * physical device lun and target assignment are deferred (assigned
2275 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2276 */
2277static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2278 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2279{
1f310bde
SC		 2280 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2281
2282 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2283 /* physical device, target and lun filled in later */
edd16368 2284 if (is_hba_lunid(lunaddrbytes))
1f310bde 2285 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2286 else
1f310bde
SC		 2287 /* defer target, lun assignment for physical devices */
2288 hpsa_set_bus_target_lun(device, 2, -1, -1);
2289 return;
2290 }
2291 /* It's a logical device */
4f4eb9f1
ST		 2292 if (is_ext_target(h, device)) {
2293 /* external target way, put logicals on bus 1
1f310bde
SC		 2294 * and match target/lun numbers box
2295 * reports, other smart array, bus 0, target 0, match lunid
2296 */
2297 hpsa_set_bus_target_lun(device,
2298 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2299 return;
edd16368 2300 }
1f310bde 2301 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2302}
2303
2304/*
2305 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2306 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2307 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2308 * it for some reason. *tmpdevice is the target we're adding,
2309 * this_device is a pointer into the current element of currentsd[]
2310 * that we're building up in update_scsi_devices(), below.
2311 * lunzerobits is a bitmap that tracks which targets already have a
2312 * lun 0 assigned.
2313 * Returns 1 if an enclosure was added, 0 if not.
2314 */
4f4eb9f1 2315static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2316 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2317 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2318 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2319{
2320 unsigned char scsi3addr[8];
2321
1f310bde 2322 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2323 return 0; /* There is already a lun 0 on this target. */
2324
2325 if (!is_logical_dev_addr_mode(lunaddrbytes))
2326 return 0; /* It's the logical targets that may lack lun 0. */
2327
4f4eb9f1
ST		 2328 if (!is_ext_target(h, tmpdevice))
2329 return 0; /* Only external target devices have this problem. */
edd16368 2330
1f310bde 2331 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2332 return 0;
2333
c4f8a299 2334 memset(scsi3addr, 0, 8);
1f310bde 2335 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2336 if (is_hba_lunid(scsi3addr))
2337 return 0; /* Don't add the RAID controller here. */
2338
339b2b14
SC		 2339 if (is_scsi_rev_5(h))
2340 return 0; /* p1210m doesn't need to do this. */
2341
4f4eb9f1 2342 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2343 dev_warn(&h->pdev->dev, "Maximum number of external "
2344 "target devices exceeded. Check your hardware "
edd16368
SC		 2345 "configuration.");
2346 return 0;
2347 }
2348
0b0e1d6c 2349 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2350 return 0;
4f4eb9f1 2351 (*n_ext_target_devs)++;
1f310bde
SC		 2352 hpsa_set_bus_target_lun(this_device,
2353 tmpdevice->bus, tmpdevice->target, 0);
2354 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2355 return 1;
2356}
2357
54b6e9e9
ST		 2358/*
2359 * Get address of physical disk used for an ioaccel2 mode command:
2360 * 1. Extract ioaccel2 handle from the command.
2361 * 2. Find a matching ioaccel2 handle from list of physical disks.
2362 * 3. Return:
2363 * 1 and set scsi3addr to address of matching physical
2364 * 0 if no matching physical disk was found.
2365 */
2366static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2367 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2368{
2369 struct ReportExtendedLUNdata *physicals = NULL;
2370 int responsesize = 24; /* size of physical extended response */
2371 int extended = 2; /* flag forces reporting 'other dev info'. */
2372 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2373 u32 nphysicals = 0; /* number of reported physical devs */
2374 int found = 0; /* found match (1) or not (0) */
2375 u32 find; /* handle we need to match */
2376 int i;
2377 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2378 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2379 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2380 u32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2381 u32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2382
2383 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2384 return 0; /* no match */
2385
2386 /* point to the ioaccel2 device handle */
2387 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2388 if (c2a == NULL)
2389 return 0; /* no match */
2390
2391 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2392 if (scmd == NULL)
2393 return 0; /* no match */
2394
2395 d = scmd->device->hostdata;
2396 if (d == NULL)
2397 return 0; /* no match */
2398
2399 it_nexus = cpu_to_le32((u32) d->ioaccel_handle);
2400 scsi_nexus = cpu_to_le32((u32) c2a->scsi_nexus);
2401 find = c2a->scsi_nexus;
2402
2403 /* Get the list of physical devices */
2404 physicals = kzalloc(reportsize, GFP_KERNEL);
2405 if (hpsa_scsi_do_report_phys_luns(h, (struct ReportLUNdata *) physicals,
2406 reportsize, extended)) {
2407 dev_err(&h->pdev->dev,
2408 "Can't lookup %s device handle: report physical LUNs failed.\n",
2409 "HP SSD Smart Path");
2410 kfree(physicals);
2411 return 0;
2412 }
2413 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2414 responsesize;
2415
2416
2417 /* find ioaccel2 handle in list of physicals: */
2418 for (i = 0; i < nphysicals; i++) {
2419 /* handle is in bytes 28-31 of each lun */
2420 if (memcmp(&((struct ReportExtendedLUNdata *)
2421 physicals)->LUN[i][20], &find, 4) != 0) {
2422 continue; /* didn't match */
2423 }
2424 found = 1;
2425 memcpy(scsi3addr, &((struct ReportExtendedLUNdata *)
2426 physicals)->LUN[i][0], 8);
2427 break; /* found it */
2428 }
2429
2430 kfree(physicals);
2431 if (found)
2432 return 1;
2433 else
2434 return 0;
2435
2436}
edd16368
SC		 2437/*
2438 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2439 * logdev. The number of luns in physdev and logdev are returned in
2440 * *nphysicals and *nlogicals, respectively.
2441 * Returns 0 on success, -1 otherwise.
2442 */
2443static int hpsa_gather_lun_info(struct ctlr_info *h,
2444 int reportlunsize,
283b4a9b 2445 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2446 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2447{
283b4a9b
SC		 2448 int physical_entry_size = 8;
2449
2450 *physical_mode = 0;
2451
2452 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2453 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2454 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2455 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2456 physical_entry_size = 24;
2457 }
a93aa1fe 2458 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize,
283b4a9b 2459 *physical_mode)) {
edd16368
SC		 2460 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2461 return -1;
2462 }
283b4a9b
SC		 2463 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2464 physical_entry_size;
edd16368
SC		 2465 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2466 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2467 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2468 *nphysicals - HPSA_MAX_PHYS_LUN);
2469 *nphysicals = HPSA_MAX_PHYS_LUN;
2470 }
2471 if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
2472 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2473 return -1;
2474 }
6df1e954 2475 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2476 /* Reject Logicals in excess of our max capability. */
2477 if (*nlogicals > HPSA_MAX_LUN) {
2478 dev_warn(&h->pdev->dev,
2479 "maximum logical LUNs (%d) exceeded. "
2480 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2481 *nlogicals - HPSA_MAX_LUN);
2482 *nlogicals = HPSA_MAX_LUN;
2483 }
2484 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2485 dev_warn(&h->pdev->dev,
2486 "maximum logical + physical LUNs (%d) exceeded. "
2487 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2488 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2489 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2490 }
2491 return 0;
2492}
2493
339b2b14 2494u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
a93aa1fe
MG		 2495 int nphysicals, int nlogicals,
2496 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2497 struct ReportLUNdata *logdev_list)
2498{
2499 /* Helper function, figure out where the LUN ID info is coming from
2500 * given index i, lists of physical and logical devices, where in
2501 * the list the raid controller is supposed to appear (first or last)
2502 */
2503
2504 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2505 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2506
2507 if (i == raid_ctlr_position)
2508 return RAID_CTLR_LUNID;
2509
2510 if (i < logicals_start)
2511 return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
2512
2513 if (i < last_device)
2514 return &logdev_list->LUN[i - nphysicals -
2515 (raid_ctlr_position == 0)][0];
2516 BUG();
2517 return NULL;
2518}
2519
edd16368
SC		 2520static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2521{
2522 /* the idea here is we could get notified
2523 * that some devices have changed, so we do a report
2524 * physical luns and report logical luns cmd, and adjust
2525 * our list of devices accordingly.
2526 *
2527 * The scsi3addr's of devices won't change so long as the
2528 * adapter is not reset. That means we can rescan and
2529 * tell which devices we already know about, vs. new
2530 * devices, vs. disappearing devices.
2531 */
a93aa1fe 2532 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 2533 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 2534 u32 nphysicals = 0;
2535 u32 nlogicals = 0;
283b4a9b 2536 int physical_mode = 0;
01a02ffc 2537 u32 ndev_allocated = 0;
edd16368
SC		 2538 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
2539 int ncurrent = 0;
283b4a9b 2540 int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 24;
4f4eb9f1 2541 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 2542 int raid_ctlr_position;
aca4a520 2543 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 2544
cfe5badc 2545 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 2546 physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
2547 logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
edd16368
SC		 2548 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
2549
0b0e1d6c 2550 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 2551 dev_err(&h->pdev->dev, "out of memory\n");
2552 goto out;
2553 }
2554 memset(lunzerobits, 0, sizeof(lunzerobits));
2555
a93aa1fe
MG		 2556 if (hpsa_gather_lun_info(h, reportlunsize,
2557 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 2558 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 2559 goto out;
2560
aca4a520
ST		 2561 /* We might see up to the maximum number of logical and physical disks
2562 * plus external target devices, and a device for the local RAID
2563 * controller.
edd16368 2564 */
aca4a520 2565 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 2566
2567 /* Allocate the per device structures */
2568 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 2569 if (i >= HPSA_MAX_DEVICES) {
2570 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
2571 " %d devices ignored.\n", HPSA_MAX_DEVICES,
2572 ndevs_to_allocate - HPSA_MAX_DEVICES);
2573 break;
2574 }
2575
edd16368
SC		 2576 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
2577 if (!currentsd[i]) {
2578 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
2579 __FILE__, __LINE__);
2580 goto out;
2581 }
2582 ndev_allocated++;
2583 }
2584
339b2b14
SC		 2585 if (unlikely(is_scsi_rev_5(h)))
2586 raid_ctlr_position = 0;
2587 else
2588 raid_ctlr_position = nphysicals + nlogicals;
2589
edd16368 2590 /* adjust our table of devices */
4f4eb9f1 2591 n_ext_target_devs = 0;
edd16368 2592 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 2593 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 2594
2595 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 2596 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
2597 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 2598 /* skip masked physical devices. */
339b2b14
SC		 2599 if (lunaddrbytes[3] & 0xC0 &&
2600 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 2601 continue;
2602
2603 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 2604 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
2605 &is_OBDR))
edd16368 2606 continue; /* skip it if we can't talk to it. */
1f310bde 2607 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 2608 this_device = currentsd[ncurrent];
2609
2610 /*
4f4eb9f1 2611 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 2612 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
2613 * is nonetheless an enclosure device there. We have to
2614 * present that otherwise linux won't find anything if
2615 * there is no lun 0.
2616 */
4f4eb9f1 2617 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 2618 lunaddrbytes, lunzerobits,
4f4eb9f1 2619 &n_ext_target_devs)) {
edd16368
SC		 2620 ncurrent++;
2621 this_device = currentsd[ncurrent];
2622 }
2623
2624 *this_device = *tmpdevice;
edd16368
SC		 2625
2626 switch (this_device->devtype) {
0b0e1d6c 2627 case TYPE_ROM:
edd16368
SC		 2628 /* We don't *really* support actual CD-ROM devices,
2629 * just "One Button Disaster Recovery" tape drive
2630 * which temporarily pretends to be a CD-ROM drive.
2631 * So we check that the device is really an OBDR tape
2632 * device by checking for "$DR-10" in bytes 43-48 of
2633 * the inquiry data.
2634 */
0b0e1d6c
SC		 2635 if (is_OBDR)
2636 ncurrent++;
edd16368
SC		 2637 break;
2638 case TYPE_DISK:
283b4a9b
SC		 2639 if (i >= nphysicals) {
2640 ncurrent++;
edd16368 2641 break;
283b4a9b
SC		 2642 }
2643 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
2644 memcpy(&this_device->ioaccel_handle,
2645 &lunaddrbytes[20],
2646 sizeof(this_device->ioaccel_handle));
2647 ncurrent++;
2648 }
edd16368
SC		 2649 break;
2650 case TYPE_TAPE:
2651 case TYPE_MEDIUM_CHANGER:
2652 ncurrent++;
2653 break;
2654 case TYPE_RAID:
2655 /* Only present the Smartarray HBA as a RAID controller.
2656 * If it's a RAID controller other than the HBA itself
2657 * (an external RAID controller, MSA500 or similar)
2658 * don't present it.
2659 */
2660 if (!is_hba_lunid(lunaddrbytes))
2661 break;
2662 ncurrent++;
2663 break;
2664 default:
2665 break;
2666 }
cfe5badc 2667 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 2668 break;
2669 }
2670 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
2671out:
2672 kfree(tmpdevice);
2673 for (i = 0; i < ndev_allocated; i++)
2674 kfree(currentsd[i]);
2675 kfree(currentsd);
edd16368
SC		 2676 kfree(physdev_list);
2677 kfree(logdev_list);
edd16368
SC		 2678}
2679
2680/* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
2681 * dma mapping and fills in the scatter gather entries of the
2682 * hpsa command, cp.
2683 */
33a2ffce 2684static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 2685 struct CommandList *cp,
2686 struct scsi_cmnd *cmd)
2687{
2688 unsigned int len;
2689 struct scatterlist *sg;
01a02ffc 2690 u64 addr64;
33a2ffce
SC		 2691 int use_sg, i, sg_index, chained;
2692 struct SGDescriptor *curr_sg;
edd16368 2693
33a2ffce 2694 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 2695
2696 use_sg = scsi_dma_map(cmd);
2697 if (use_sg < 0)
2698 return use_sg;
2699
2700 if (!use_sg)
2701 goto sglist_finished;
2702
33a2ffce
SC		 2703 curr_sg = cp->SG;
2704 chained = 0;
2705 sg_index = 0;
edd16368 2706 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 2707 if (i == h->max_cmd_sg_entries - 1 &&
2708 use_sg > h->max_cmd_sg_entries) {
2709 chained = 1;
2710 curr_sg = h->cmd_sg_list[cp->cmdindex];
2711 sg_index = 0;
2712 }
01a02ffc 2713 addr64 = (u64) sg_dma_address(sg);
edd16368 2714 len = sg_dma_len(sg);
33a2ffce
SC		 2715 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2716 curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2717 curr_sg->Len = len;
e1d9cbfa 2718 curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST;
33a2ffce
SC		 2719 curr_sg++;
2720 }
2721
2722 if (use_sg + chained > h->maxSG)
2723 h->maxSG = use_sg + chained;
2724
2725 if (chained) {
2726 cp->Header.SGList = h->max_cmd_sg_entries;
2727 cp->Header.SGTotal = (u16) (use_sg + 1);
e2bea6df
SC		 2728 if (hpsa_map_sg_chain_block(h, cp)) {
2729 scsi_dma_unmap(cmd);
2730 return -1;
2731 }
33a2ffce 2732 return 0;
edd16368
SC		 2733 }
2734
2735sglist_finished:
2736
01a02ffc
SC		 2737 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
2738 cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
edd16368
SC		 2739 return 0;
2740}
2741
283b4a9b
SC		 2742#define IO_ACCEL_INELIGIBLE (1)
2743static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
2744{
2745 int is_write = 0;
2746 u32 block;
2747 u32 block_cnt;
2748
2749 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
2750 switch (cdb[0]) {
2751 case WRITE_6:
2752 case WRITE_12:
2753 is_write = 1;
2754 case READ_6:
2755 case READ_12:
2756 if (*cdb_len == 6) {
2757 block = (((u32) cdb[2]) << 8) | cdb[3];
2758 block_cnt = cdb[4];
2759 } else {
2760 BUG_ON(*cdb_len != 12);
2761 block = (((u32) cdb[2]) << 24) |
2762 (((u32) cdb[3]) << 16) |
2763 (((u32) cdb[4]) << 8) |
2764 cdb[5];
2765 block_cnt =
2766 (((u32) cdb[6]) << 24) |
2767 (((u32) cdb[7]) << 16) |
2768 (((u32) cdb[8]) << 8) |
2769 cdb[9];
2770 }
2771 if (block_cnt > 0xffff)
2772 return IO_ACCEL_INELIGIBLE;
2773
2774 cdb[0] = is_write ? WRITE_10 : READ_10;
2775 cdb[1] = 0;
2776 cdb[2] = (u8) (block >> 24);
2777 cdb[3] = (u8) (block >> 16);
2778 cdb[4] = (u8) (block >> 8);
2779 cdb[5] = (u8) (block);
2780 cdb[6] = 0;
2781 cdb[7] = (u8) (block_cnt >> 8);
2782 cdb[8] = (u8) (block_cnt);
2783 cdb[9] = 0;
2784 *cdb_len = 10;
2785 break;
2786 }
2787 return 0;
2788}
2789
c349775e 2790static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 2791 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2792 u8 *scsi3addr)
e1f7de0c
MG		 2793{
2794 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 2795 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
2796 unsigned int len;
2797 unsigned int total_len = 0;
2798 struct scatterlist *sg;
2799 u64 addr64;
2800 int use_sg, i;
2801 struct SGDescriptor *curr_sg;
2802 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
2803
283b4a9b
SC		 2804 /* TODO: implement chaining support */
2805 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
2806 return IO_ACCEL_INELIGIBLE;
2807
e1f7de0c
MG		 2808 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
2809
283b4a9b
SC		 2810 if (fixup_ioaccel_cdb(cdb, &cdb_len))
2811 return IO_ACCEL_INELIGIBLE;
2812
e1f7de0c
MG		 2813 c->cmd_type = CMD_IOACCEL1;
2814
2815 /* Adjust the DMA address to point to the accelerated command buffer */
2816 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
2817 (c->cmdindex * sizeof(*cp));
2818 BUG_ON(c->busaddr & 0x0000007F);
2819
2820 use_sg = scsi_dma_map(cmd);
2821 if (use_sg < 0)
2822 return use_sg;
2823
2824 if (use_sg) {
2825 curr_sg = cp->SG;
2826 scsi_for_each_sg(cmd, sg, use_sg, i) {
2827 addr64 = (u64) sg_dma_address(sg);
2828 len = sg_dma_len(sg);
2829 total_len += len;
2830 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2831 curr_sg->Addr.upper =
2832 (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2833 curr_sg->Len = len;
2834
2835 if (i == (scsi_sg_count(cmd) - 1))
2836 curr_sg->Ext = HPSA_SG_LAST;
2837 else
2838 curr_sg->Ext = 0; /* we are not chaining */
2839 curr_sg++;
2840 }
2841
2842 switch (cmd->sc_data_direction) {
2843 case DMA_TO_DEVICE:
2844 control |= IOACCEL1_CONTROL_DATA_OUT;
2845 break;
2846 case DMA_FROM_DEVICE:
2847 control |= IOACCEL1_CONTROL_DATA_IN;
2848 break;
2849 case DMA_NONE:
2850 control |= IOACCEL1_CONTROL_NODATAXFER;
2851 break;
2852 default:
2853 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
2854 cmd->sc_data_direction);
2855 BUG();
2856 break;
2857 }
2858 } else {
2859 control |= IOACCEL1_CONTROL_NODATAXFER;
2860 }
2861
c349775e 2862 c->Header.SGList = use_sg;
e1f7de0c 2863 /* Fill out the command structure to submit */
283b4a9b 2864 cp->dev_handle = ioaccel_handle & 0xFFFF;
e1f7de0c
MG		 2865 cp->transfer_len = total_len;
2866 cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ |
283b4a9b 2867 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK);
e1f7de0c 2868 cp->control = control;
283b4a9b
SC		 2869 memcpy(cp->CDB, cdb, cdb_len);
2870 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 2871 /* Tag was already set at init time. */
283b4a9b 2872 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 2873 return 0;
2874}
edd16368 2875
283b4a9b
SC		 2876/*
2877 * Queue a command directly to a device behind the controller using the
2878 * I/O accelerator path.
2879 */
2880static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
2881 struct CommandList *c)
2882{
2883 struct scsi_cmnd *cmd = c->scsi_cmd;
2884 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
2885
2886 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
2887 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
2888}
2889
c349775e
ST		 2890static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
2891 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2892 u8 *scsi3addr)
2893{
2894 struct scsi_cmnd *cmd = c->scsi_cmd;
2895 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
2896 struct ioaccel2_sg_element *curr_sg;
2897 int use_sg, i;
2898 struct scatterlist *sg;
2899 u64 addr64;
2900 u32 len;
2901 u32 total_len = 0;
2902
2903 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
2904 return IO_ACCEL_INELIGIBLE;
2905
2906 if (fixup_ioaccel_cdb(cdb, &cdb_len))
2907 return IO_ACCEL_INELIGIBLE;
2908 c->cmd_type = CMD_IOACCEL2;
2909 /* Adjust the DMA address to point to the accelerated command buffer */
2910 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
2911 (c->cmdindex * sizeof(*cp));
2912 BUG_ON(c->busaddr & 0x0000007F);
2913
2914 memset(cp, 0, sizeof(*cp));
2915 cp->IU_type = IOACCEL2_IU_TYPE;
2916
2917 use_sg = scsi_dma_map(cmd);
2918 if (use_sg < 0)
2919 return use_sg;
2920
2921 if (use_sg) {
2922 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
2923 curr_sg = cp->sg;
2924 scsi_for_each_sg(cmd, sg, use_sg, i) {
2925 addr64 = (u64) sg_dma_address(sg);
2926 len = sg_dma_len(sg);
2927 total_len += len;
2928 curr_sg->address = cpu_to_le64(addr64);
2929 curr_sg->length = cpu_to_le32(len);
2930 curr_sg->reserved[0] = 0;
2931 curr_sg->reserved[1] = 0;
2932 curr_sg->reserved[2] = 0;
2933 curr_sg->chain_indicator = 0;
2934 curr_sg++;
2935 }
2936
2937 switch (cmd->sc_data_direction) {
2938 case DMA_TO_DEVICE:
2939 cp->direction = IOACCEL2_DIR_DATA_OUT;
2940 break;
2941 case DMA_FROM_DEVICE:
2942 cp->direction = IOACCEL2_DIR_DATA_IN;
2943 break;
2944 case DMA_NONE:
2945 cp->direction = IOACCEL2_DIR_NO_DATA;
2946 break;
2947 default:
2948 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
2949 cmd->sc_data_direction);
2950 BUG();
2951 break;
2952 }
2953 } else {
2954 cp->direction = IOACCEL2_DIR_NO_DATA;
2955 }
2956 cp->scsi_nexus = ioaccel_handle;
2957 cp->Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT) |
2958 DIRECT_LOOKUP_BIT;
2959 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
2960 memset(cp->cciss_lun, 0, sizeof(cp->cciss_lun));
2961 cp->cmd_priority_task_attr = 0;
2962
2963 /* fill in sg elements */
2964 cp->sg_count = (u8) use_sg;
2965
2966 cp->data_len = cpu_to_le32(total_len);
2967 cp->err_ptr = cpu_to_le64(c->busaddr +
2968 offsetof(struct io_accel2_cmd, error_data));
2969 cp->err_len = cpu_to_le32((u32) sizeof(cp->error_data));
2970
2971 enqueue_cmd_and_start_io(h, c);
2972 return 0;
2973}
2974
2975/*
2976 * Queue a command to the correct I/O accelerator path.
2977 */
2978static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
2979 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2980 u8 *scsi3addr)
2981{
2982 if (h->transMethod & CFGTBL_Trans_io_accel1)
2983 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
2984 cdb, cdb_len, scsi3addr);
2985 else
2986 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
2987 cdb, cdb_len, scsi3addr);
2988}
2989
6b80b18f
ST		 2990static void raid_map_helper(struct raid_map_data *map,
2991 int offload_to_mirror, u32 *map_index, u32 *current_group)
2992{
2993 if (offload_to_mirror == 0) {
2994 /* use physical disk in the first mirrored group. */
2995 *map_index %= map->data_disks_per_row;
2996 return;
2997 }
2998 do {
2999 /* determine mirror group that *map_index indicates */
3000 *current_group = *map_index / map->data_disks_per_row;
3001 if (offload_to_mirror == *current_group)
3002 continue;
3003 if (*current_group < (map->layout_map_count - 1)) {
3004 /* select map index from next group */
3005 *map_index += map->data_disks_per_row;
3006 (*current_group)++;
3007 } else {
3008 /* select map index from first group */
3009 *map_index %= map->data_disks_per_row;
3010 *current_group = 0;
3011 }
3012 } while (offload_to_mirror != *current_group);
3013}
3014
283b4a9b
SC		 3015/*
3016 * Attempt to perform offload RAID mapping for a logical volume I/O.
3017 */
3018static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3019 struct CommandList *c)
3020{
3021 struct scsi_cmnd *cmd = c->scsi_cmd;
3022 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3023 struct raid_map_data *map = &dev->raid_map;
3024 struct raid_map_disk_data *dd = &map->data[0];
3025 int is_write = 0;
3026 u32 map_index;
3027 u64 first_block, last_block;
3028 u32 block_cnt;
3029 u32 blocks_per_row;
3030 u64 first_row, last_row;
3031 u32 first_row_offset, last_row_offset;
3032 u32 first_column, last_column;
6b80b18f
ST		 3033 u64 r0_first_row, r0_last_row;
3034 u32 r5or6_blocks_per_row;
3035 u64 r5or6_first_row, r5or6_last_row;
3036 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3037 u32 r5or6_first_column, r5or6_last_column;
3038 u32 total_disks_per_row;
3039 u32 stripesize;
3040 u32 first_group, last_group, current_group;
283b4a9b
SC		 3041 u32 map_row;
3042 u32 disk_handle;
3043 u64 disk_block;
3044 u32 disk_block_cnt;
3045 u8 cdb[16];
3046 u8 cdb_len;
3047#if BITS_PER_LONG == 32
3048 u64 tmpdiv;
3049#endif
6b80b18f 3050 int offload_to_mirror;
283b4a9b
SC		 3051
3052 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3053
3054 /* check for valid opcode, get LBA and block count */
3055 switch (cmd->cmnd[0]) {
3056 case WRITE_6:
3057 is_write = 1;
3058 case READ_6:
3059 first_block =
3060 (((u64) cmd->cmnd[2]) << 8) |
3061 cmd->cmnd[3];
3062 block_cnt = cmd->cmnd[4];
3063 break;
3064 case WRITE_10:
3065 is_write = 1;
3066 case READ_10:
3067 first_block =
3068 (((u64) cmd->cmnd[2]) << 24) |
3069 (((u64) cmd->cmnd[3]) << 16) |
3070 (((u64) cmd->cmnd[4]) << 8) |
3071 cmd->cmnd[5];
3072 block_cnt =
3073 (((u32) cmd->cmnd[7]) << 8) |
3074 cmd->cmnd[8];
3075 break;
3076 case WRITE_12:
3077 is_write = 1;
3078 case READ_12:
3079 first_block =
3080 (((u64) cmd->cmnd[2]) << 24) |
3081 (((u64) cmd->cmnd[3]) << 16) |
3082 (((u64) cmd->cmnd[4]) << 8) |
3083 cmd->cmnd[5];
3084 block_cnt =
3085 (((u32) cmd->cmnd[6]) << 24) |
3086 (((u32) cmd->cmnd[7]) << 16) |
3087 (((u32) cmd->cmnd[8]) << 8) |
3088 cmd->cmnd[9];
3089 break;
3090 case WRITE_16:
3091 is_write = 1;
3092 case READ_16:
3093 first_block =
3094 (((u64) cmd->cmnd[2]) << 56) |
3095 (((u64) cmd->cmnd[3]) << 48) |
3096 (((u64) cmd->cmnd[4]) << 40) |
3097 (((u64) cmd->cmnd[5]) << 32) |
3098 (((u64) cmd->cmnd[6]) << 24) |
3099 (((u64) cmd->cmnd[7]) << 16) |
3100 (((u64) cmd->cmnd[8]) << 8) |
3101 cmd->cmnd[9];
3102 block_cnt =
3103 (((u32) cmd->cmnd[10]) << 24) |
3104 (((u32) cmd->cmnd[11]) << 16) |
3105 (((u32) cmd->cmnd[12]) << 8) |
3106 cmd->cmnd[13];
3107 break;
3108 default:
3109 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3110 }
3111 BUG_ON(block_cnt == 0);
3112 last_block = first_block + block_cnt - 1;
3113
3114 /* check for write to non-RAID-0 */
3115 if (is_write && dev->raid_level != 0)
3116 return IO_ACCEL_INELIGIBLE;
3117
3118 /* check for invalid block or wraparound */
3119 if (last_block >= map->volume_blk_cnt || last_block < first_block)
3120 return IO_ACCEL_INELIGIBLE;
3121
3122 /* calculate stripe information for the request */
3123 blocks_per_row = map->data_disks_per_row * map->strip_size;
3124#if BITS_PER_LONG == 32
3125 tmpdiv = first_block;
3126 (void) do_div(tmpdiv, blocks_per_row);
3127 first_row = tmpdiv;
3128 tmpdiv = last_block;
3129 (void) do_div(tmpdiv, blocks_per_row);
3130 last_row = tmpdiv;
3131 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3132 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3133 tmpdiv = first_row_offset;
3134 (void) do_div(tmpdiv, map->strip_size);
3135 first_column = tmpdiv;
3136 tmpdiv = last_row_offset;
3137 (void) do_div(tmpdiv, map->strip_size);
3138 last_column = tmpdiv;
3139#else
3140 first_row = first_block / blocks_per_row;
3141 last_row = last_block / blocks_per_row;
3142 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3143 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3144 first_column = first_row_offset / map->strip_size;
3145 last_column = last_row_offset / map->strip_size;
3146#endif
3147
3148 /* if this isn't a single row/column then give to the controller */
3149 if ((first_row != last_row) || (first_column != last_column))
3150 return IO_ACCEL_INELIGIBLE;
3151
3152 /* proceeding with driver mapping */
6b80b18f
ST		 3153 total_disks_per_row = map->data_disks_per_row +
3154 map->metadata_disks_per_row;
283b4a9b
SC		 3155 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3156 map->row_cnt;
6b80b18f
ST		 3157 map_index = (map_row * total_disks_per_row) + first_column;
3158
3159 switch (dev->raid_level) {
3160 case HPSA_RAID_0:
3161 break; /* nothing special to do */
3162 case HPSA_RAID_1:
3163 /* Handles load balance across RAID 1 members.
3164 * (2-drive R1 and R10 with even # of drives.)
3165 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 3166 */
6b80b18f 3167 BUG_ON(map->layout_map_count != 2);
283b4a9b
SC		 3168 if (dev->offload_to_mirror)
3169 map_index += map->data_disks_per_row;
3170 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 3171 break;
3172 case HPSA_RAID_ADM:
3173 /* Handles N-way mirrors (R1-ADM)
3174 * and R10 with # of drives divisible by 3.)
3175 */
3176 BUG_ON(map->layout_map_count != 3);
3177
3178 offload_to_mirror = dev->offload_to_mirror;
3179 raid_map_helper(map, offload_to_mirror,
3180 &map_index, &current_group);
3181 /* set mirror group to use next time */
3182 offload_to_mirror =
3183 (offload_to_mirror >= map->layout_map_count - 1)
3184 ? 0 : offload_to_mirror + 1;
3185 /* FIXME: remove after debug/dev */
3186 BUG_ON(offload_to_mirror >= map->layout_map_count);
3187 dev_warn(&h->pdev->dev,
3188 "DEBUG: Using physical disk map index %d from mirror group %d\n",
3189 map_index, offload_to_mirror);
3190 dev->offload_to_mirror = offload_to_mirror;
3191 /* Avoid direct use of dev->offload_to_mirror within this
3192 * function since multiple threads might simultaneously
3193 * increment it beyond the range of dev->layout_map_count -1.
3194 */
3195 break;
3196 case HPSA_RAID_5:
3197 case HPSA_RAID_6:
3198 if (map->layout_map_count <= 1)
3199 break;
3200
3201 /* Verify first and last block are in same RAID group */
3202 r5or6_blocks_per_row =
3203 map->strip_size * map->data_disks_per_row;
3204 BUG_ON(r5or6_blocks_per_row == 0);
3205 stripesize = r5or6_blocks_per_row * map->layout_map_count;
3206#if BITS_PER_LONG == 32
3207 tmpdiv = first_block;
3208 first_group = do_div(tmpdiv, stripesize);
3209 tmpdiv = first_group;
3210 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3211 first_group = tmpdiv;
3212 tmpdiv = last_block;
3213 last_group = do_div(tmpdiv, stripesize);
3214 tmpdiv = last_group;
3215 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3216 last_group = tmpdiv;
3217#else
3218 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
3219 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
3220 if (first_group != last_group)
3221#endif
3222 return IO_ACCEL_INELIGIBLE;
3223
3224 /* Verify request is in a single row of RAID 5/6 */
3225#if BITS_PER_LONG == 32
3226 tmpdiv = first_block;
3227 (void) do_div(tmpdiv, stripesize);
3228 first_row = r5or6_first_row = r0_first_row = tmpdiv;
3229 tmpdiv = last_block;
3230 (void) do_div(tmpdiv, stripesize);
3231 r5or6_last_row = r0_last_row = tmpdiv;
3232#else
3233 first_row = r5or6_first_row = r0_first_row =
3234 first_block / stripesize;
3235 r5or6_last_row = r0_last_row = last_block / stripesize;
3236#endif
3237 if (r5or6_first_row != r5or6_last_row)
3238 return IO_ACCEL_INELIGIBLE;
3239
3240
3241 /* Verify request is in a single column */
3242#if BITS_PER_LONG == 32
3243 tmpdiv = first_block;
3244 first_row_offset = do_div(tmpdiv, stripesize);
3245 tmpdiv = first_row_offset;
3246 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
3247 r5or6_first_row_offset = first_row_offset;
3248 tmpdiv = last_block;
3249 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
3250 tmpdiv = r5or6_last_row_offset;
3251 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
3252 tmpdiv = r5or6_first_row_offset;
3253 (void) do_div(tmpdiv, map->strip_size);
3254 first_column = r5or6_first_column = tmpdiv;
3255 tmpdiv = r5or6_last_row_offset;
3256 (void) do_div(tmpdiv, map->strip_size);
3257 r5or6_last_column = tmpdiv;
3258#else
3259 first_row_offset = r5or6_first_row_offset =
3260 (u32)((first_block % stripesize) %
3261 r5or6_blocks_per_row);
3262
3263 r5or6_last_row_offset =
3264 (u32)((last_block % stripesize) %
3265 r5or6_blocks_per_row);
3266
3267 first_column = r5or6_first_column =
3268 r5or6_first_row_offset / map->strip_size;
3269 r5or6_last_column =
3270 r5or6_last_row_offset / map->strip_size;
3271#endif
3272 if (r5or6_first_column != r5or6_last_column)
3273 return IO_ACCEL_INELIGIBLE;
3274
3275 /* Request is eligible */
3276 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3277 map->row_cnt;
3278
3279 map_index = (first_group *
3280 (map->row_cnt * total_disks_per_row)) +
3281 (map_row * total_disks_per_row) + first_column;
3282 break;
3283 default:
3284 return IO_ACCEL_INELIGIBLE;
283b4a9b 3285 }
6b80b18f 3286
283b4a9b
SC		 3287 disk_handle = dd[map_index].ioaccel_handle;
3288 disk_block = map->disk_starting_blk + (first_row * map->strip_size) +
3289 (first_row_offset - (first_column * map->strip_size));
3290 disk_block_cnt = block_cnt;
3291
3292 /* handle differing logical/physical block sizes */
3293 if (map->phys_blk_shift) {
3294 disk_block <<= map->phys_blk_shift;
3295 disk_block_cnt <<= map->phys_blk_shift;
3296 }
3297 BUG_ON(disk_block_cnt > 0xffff);
3298
3299 /* build the new CDB for the physical disk I/O */
3300 if (disk_block > 0xffffffff) {
3301 cdb[0] = is_write ? WRITE_16 : READ_16;
3302 cdb[1] = 0;
3303 cdb[2] = (u8) (disk_block >> 56);
3304 cdb[3] = (u8) (disk_block >> 48);
3305 cdb[4] = (u8) (disk_block >> 40);
3306 cdb[5] = (u8) (disk_block >> 32);
3307 cdb[6] = (u8) (disk_block >> 24);
3308 cdb[7] = (u8) (disk_block >> 16);
3309 cdb[8] = (u8) (disk_block >> 8);
3310 cdb[9] = (u8) (disk_block);
3311 cdb[10] = (u8) (disk_block_cnt >> 24);
3312 cdb[11] = (u8) (disk_block_cnt >> 16);
3313 cdb[12] = (u8) (disk_block_cnt >> 8);
3314 cdb[13] = (u8) (disk_block_cnt);
3315 cdb[14] = 0;
3316 cdb[15] = 0;
3317 cdb_len = 16;
3318 } else {
3319 cdb[0] = is_write ? WRITE_10 : READ_10;
3320 cdb[1] = 0;
3321 cdb[2] = (u8) (disk_block >> 24);
3322 cdb[3] = (u8) (disk_block >> 16);
3323 cdb[4] = (u8) (disk_block >> 8);
3324 cdb[5] = (u8) (disk_block);
3325 cdb[6] = 0;
3326 cdb[7] = (u8) (disk_block_cnt >> 8);
3327 cdb[8] = (u8) (disk_block_cnt);
3328 cdb[9] = 0;
3329 cdb_len = 10;
3330 }
3331 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3332 dev->scsi3addr);
3333}
3334
f281233d 3335static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
edd16368
SC		 3336 void (*done)(struct scsi_cmnd *))
3337{
3338 struct ctlr_info *h;
3339 struct hpsa_scsi_dev_t *dev;
3340 unsigned char scsi3addr[8];
3341 struct CommandList *c;
3342 unsigned long flags;
283b4a9b 3343 int rc = 0;
edd16368
SC		 3344
3345 /* Get the ptr to our adapter structure out of cmd->host. */
3346 h = sdev_to_hba(cmd->device);
3347 dev = cmd->device->hostdata;
3348 if (!dev) {
3349 cmd->result = DID_NO_CONNECT << 16;
3350 done(cmd);
3351 return 0;
3352 }
3353 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3354
edd16368 3355 spin_lock_irqsave(&h->lock, flags);
a0c12413
SC		 3356 if (unlikely(h->lockup_detected)) {
3357 spin_unlock_irqrestore(&h->lock, flags);
3358 cmd->result = DID_ERROR << 16;
3359 done(cmd);
3360 return 0;
3361 }
edd16368 3362 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 3363 c = cmd_alloc(h);
edd16368
SC		 3364 if (c == NULL) { /* trouble... */
3365 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
3366 return SCSI_MLQUEUE_HOST_BUSY;
3367 }
3368
3369 /* Fill in the command list header */
3370
3371 cmd->scsi_done = done; /* save this for use by completion code */
3372
3373 /* save c in case we have to abort it */
3374 cmd->host_scribble = (unsigned char *) c;
3375
3376 c->cmd_type = CMD_SCSI;
3377 c->scsi_cmd = cmd;
e1f7de0c 3378
283b4a9b
SC		 3379 /* Call alternate submit routine for I/O accelerated commands.
3380 * Retries always go down the normal I/O path.
3381 */
3382 if (likely(cmd->retries == 0 &&
da0697bd
ST		 3383 cmd->request->cmd_type == REQ_TYPE_FS &&
3384 h->acciopath_status)) {
283b4a9b
SC		 3385 if (dev->offload_enabled) {
3386 rc = hpsa_scsi_ioaccel_raid_map(h, c);
3387 if (rc == 0)
3388 return 0; /* Sent on ioaccel path */
3389 if (rc < 0) { /* scsi_dma_map failed. */
3390 cmd_free(h, c);
3391 return SCSI_MLQUEUE_HOST_BUSY;
3392 }
3393 } else if (dev->ioaccel_handle) {
3394 rc = hpsa_scsi_ioaccel_direct_map(h, c);
3395 if (rc == 0)
3396 return 0; /* Sent on direct map path */
3397 if (rc < 0) { /* scsi_dma_map failed. */
3398 cmd_free(h, c);
3399 return SCSI_MLQUEUE_HOST_BUSY;
3400 }
3401 }
3402 }
e1f7de0c 3403
edd16368
SC		 3404 c->Header.ReplyQueue = 0; /* unused in simple mode */
3405 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
303932fd
DB		 3406 c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
3407 c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
edd16368
SC		 3408
3409 /* Fill in the request block... */
3410
3411 c->Request.Timeout = 0;
3412 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
3413 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
3414 c->Request.CDBLen = cmd->cmd_len;
3415 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
3416 c->Request.Type.Type = TYPE_CMD;
3417 c->Request.Type.Attribute = ATTR_SIMPLE;
3418 switch (cmd->sc_data_direction) {
3419 case DMA_TO_DEVICE:
3420 c->Request.Type.Direction = XFER_WRITE;
3421 break;
3422 case DMA_FROM_DEVICE:
3423 c->Request.Type.Direction = XFER_READ;
3424 break;
3425 case DMA_NONE:
3426 c->Request.Type.Direction = XFER_NONE;
3427 break;
3428 case DMA_BIDIRECTIONAL:
3429 /* This can happen if a buggy application does a scsi passthru
3430 * and sets both inlen and outlen to non-zero. ( see
3431 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
3432 */
3433
3434 c->Request.Type.Direction = XFER_RSVD;
3435 /* This is technically wrong, and hpsa controllers should
3436 * reject it with CMD_INVALID, which is the most correct
3437 * response, but non-fibre backends appear to let it
3438 * slide by, and give the same results as if this field
3439 * were set correctly. Either way is acceptable for
3440 * our purposes here.
3441 */
3442
3443 break;
3444
3445 default:
3446 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3447 cmd->sc_data_direction);
3448 BUG();
3449 break;
3450 }
3451
33a2ffce 3452 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 3453 cmd_free(h, c);
3454 return SCSI_MLQUEUE_HOST_BUSY;
3455 }
3456 enqueue_cmd_and_start_io(h, c);
3457 /* the cmd'll come back via intr handler in complete_scsi_command() */
3458 return 0;
3459}
3460
f281233d
JG		 3461static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
3462
5f389360
SC		 3463static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
3464{
3465 unsigned long flags;
3466
3467 /*
3468 * Don't let rescans be initiated on a controller known
3469 * to be locked up. If the controller locks up *during*
3470 * a rescan, that thread is probably hosed, but at least
3471 * we can prevent new rescan threads from piling up on a
3472 * locked up controller.
3473 */
3474 spin_lock_irqsave(&h->lock, flags);
3475 if (unlikely(h->lockup_detected)) {
3476 spin_unlock_irqrestore(&h->lock, flags);
3477 spin_lock_irqsave(&h->scan_lock, flags);
3478 h->scan_finished = 1;
3479 wake_up_all(&h->scan_wait_queue);
3480 spin_unlock_irqrestore(&h->scan_lock, flags);
3481 return 1;
3482 }
3483 spin_unlock_irqrestore(&h->lock, flags);
3484 return 0;
3485}
3486
a08a8471
SC		 3487static void hpsa_scan_start(struct Scsi_Host *sh)
3488{
3489 struct ctlr_info *h = shost_to_hba(sh);
3490 unsigned long flags;
3491
5f389360
SC		 3492 if (do_not_scan_if_controller_locked_up(h))
3493 return;
3494
a08a8471
SC		 3495 /* wait until any scan already in progress is finished. */
3496 while (1) {
3497 spin_lock_irqsave(&h->scan_lock, flags);
3498 if (h->scan_finished)
3499 break;
3500 spin_unlock_irqrestore(&h->scan_lock, flags);
3501 wait_event(h->scan_wait_queue, h->scan_finished);
3502 /* Note: We don't need to worry about a race between this
3503 * thread and driver unload because the midlayer will
3504 * have incremented the reference count, so unload won't
3505 * happen if we're in here.
3506 */
3507 }
3508 h->scan_finished = 0; /* mark scan as in progress */
3509 spin_unlock_irqrestore(&h->scan_lock, flags);
3510
5f389360
SC		 3511 if (do_not_scan_if_controller_locked_up(h))
3512 return;
3513
a08a8471
SC		 3514 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
3515
3516 spin_lock_irqsave(&h->scan_lock, flags);
3517 h->scan_finished = 1; /* mark scan as finished. */
3518 wake_up_all(&h->scan_wait_queue);
3519 spin_unlock_irqrestore(&h->scan_lock, flags);
3520}
3521
3522static int hpsa_scan_finished(struct Scsi_Host *sh,
3523 unsigned long elapsed_time)
3524{
3525 struct ctlr_info *h = shost_to_hba(sh);
3526 unsigned long flags;
3527 int finished;
3528
3529 spin_lock_irqsave(&h->scan_lock, flags);
3530 finished = h->scan_finished;
3531 spin_unlock_irqrestore(&h->scan_lock, flags);
3532 return finished;
3533}
3534
667e23d4
SC		 3535static int hpsa_change_queue_depth(struct scsi_device *sdev,
3536 int qdepth, int reason)
3537{
3538 struct ctlr_info *h = sdev_to_hba(sdev);
3539
3540 if (reason != SCSI_QDEPTH_DEFAULT)
3541 return -ENOTSUPP;
3542
3543 if (qdepth < 1)
3544 qdepth = 1;
3545 else
3546 if (qdepth > h->nr_cmds)
3547 qdepth = h->nr_cmds;
3548 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
3549 return sdev->queue_depth;
3550}
3551
edd16368
SC		 3552static void hpsa_unregister_scsi(struct ctlr_info *h)
3553{
3554 /* we are being forcibly unloaded, and may not refuse. */
3555 scsi_remove_host(h->scsi_host);
3556 scsi_host_put(h->scsi_host);
3557 h->scsi_host = NULL;
3558}
3559
3560static int hpsa_register_scsi(struct ctlr_info *h)
3561{
b705690d
SC		 3562 struct Scsi_Host *sh;
3563 int error;
edd16368 3564
b705690d
SC		 3565 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
3566 if (sh == NULL)
3567 goto fail;
3568
3569 sh->io_port = 0;
3570 sh->n_io_port = 0;
3571 sh->this_id = -1;
3572 sh->max_channel = 3;
3573 sh->max_cmd_len = MAX_COMMAND_SIZE;
3574 sh->max_lun = HPSA_MAX_LUN;
3575 sh->max_id = HPSA_MAX_LUN;
3576 sh->can_queue = h->nr_cmds;
3577 sh->cmd_per_lun = h->nr_cmds;
3578 sh->sg_tablesize = h->maxsgentries;
3579 h->scsi_host = sh;
3580 sh->hostdata[0] = (unsigned long) h;
3581 sh->irq = h->intr[h->intr_mode];
3582 sh->unique_id = sh->irq;
3583 error = scsi_add_host(sh, &h->pdev->dev);
3584 if (error)
3585 goto fail_host_put;
3586 scsi_scan_host(sh);
3587 return 0;
3588
3589 fail_host_put:
3590 dev_err(&h->pdev->dev, "%s: scsi_add_host"
3591 " failed for controller %d\n", __func__, h->ctlr);
3592 scsi_host_put(sh);
3593 return error;
3594 fail:
3595 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
3596 " failed for controller %d\n", __func__, h->ctlr);
3597 return -ENOMEM;
edd16368
SC		 3598}
3599
3600static int wait_for_device_to_become_ready(struct ctlr_info *h,
3601 unsigned char lunaddr[])
3602{
3603 int rc = 0;
3604 int count = 0;
3605 int waittime = 1; /* seconds */
3606 struct CommandList *c;
3607
3608 c = cmd_special_alloc(h);
3609 if (!c) {
3610 dev_warn(&h->pdev->dev, "out of memory in "
3611 "wait_for_device_to_become_ready.\n");
3612 return IO_ERROR;
3613 }
3614
3615 /* Send test unit ready until device ready, or give up. */
3616 while (count < HPSA_TUR_RETRY_LIMIT) {
3617
3618 /* Wait for a bit. do this first, because if we send
3619 * the TUR right away, the reset will just abort it.
3620 */
3621 msleep(1000 * waittime);
3622 count++;
3623
3624 /* Increase wait time with each try, up to a point. */
3625 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
3626 waittime = waittime * 2;
3627
a2dac136
SC		 3628 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
3629 (void) fill_cmd(c, TEST_UNIT_READY, h,
3630 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 3631 hpsa_scsi_do_simple_cmd_core(h, c);
3632 /* no unmap needed here because no data xfer. */
3633
3634 if (c->err_info->CommandStatus == CMD_SUCCESS)
3635 break;
3636
3637 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
3638 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
3639 (c->err_info->SenseInfo[2] == NO_SENSE ||
3640 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
3641 break;
3642
3643 dev_warn(&h->pdev->dev, "waiting %d secs "
3644 "for device to become ready.\n", waittime);
3645 rc = 1; /* device not ready. */
3646 }
3647
3648 if (rc)
3649 dev_warn(&h->pdev->dev, "giving up on device.\n");
3650 else
3651 dev_warn(&h->pdev->dev, "device is ready.\n");
3652
3653 cmd_special_free(h, c);
3654 return rc;
3655}
3656
3657/* Need at least one of these error handlers to keep ../scsi/hosts.c from
3658 * complaining. Doing a host- or bus-reset can't do anything good here.
3659 */
3660static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
3661{
3662 int rc;
3663 struct ctlr_info *h;
3664 struct hpsa_scsi_dev_t *dev;
3665
3666 /* find the controller to which the command to be aborted was sent */
3667 h = sdev_to_hba(scsicmd->device);
3668 if (h == NULL) /* paranoia */
3669 return FAILED;
edd16368
SC		 3670 dev = scsicmd->device->hostdata;
3671 if (!dev) {
3672 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
3673 "device lookup failed.\n");
3674 return FAILED;
3675 }
d416b0c7
SC		 3676 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
3677 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 3678 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 3679 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 3680 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
3681 return SUCCESS;
3682
3683 dev_warn(&h->pdev->dev, "resetting device failed.\n");
3684 return FAILED;
3685}
3686
6cba3f19
SC		 3687static void swizzle_abort_tag(u8 *tag)
3688{
3689 u8 original_tag[8];
3690
3691 memcpy(original_tag, tag, 8);
3692 tag[0] = original_tag[3];
3693 tag[1] = original_tag[2];
3694 tag[2] = original_tag[1];
3695 tag[3] = original_tag[0];
3696 tag[4] = original_tag[7];
3697 tag[5] = original_tag[6];
3698 tag[6] = original_tag[5];
3699 tag[7] = original_tag[4];
3700}
3701
17eb87d2
ST		 3702static void hpsa_get_tag(struct ctlr_info *h,
3703 struct CommandList *c, u32 *taglower, u32 *tagupper)
3704{
3705 if (c->cmd_type == CMD_IOACCEL1) {
3706 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
3707 &h->ioaccel_cmd_pool[c->cmdindex];
3708 *tagupper = cm1->Tag.upper;
3709 *taglower = cm1->Tag.lower;
54b6e9e9
ST		 3710 return;
3711 }
3712 if (c->cmd_type == CMD_IOACCEL2) {
3713 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
3714 &h->ioaccel2_cmd_pool[c->cmdindex];
3715 *tagupper = cm2->Tag.upper;
3716 *taglower = cm2->Tag.lower;
3717 return;
17eb87d2 3718 }
54b6e9e9
ST		 3719 *tagupper = c->Header.Tag.upper;
3720 *taglower = c->Header.Tag.lower;
17eb87d2
ST		 3721}
3722
54b6e9e9 3723
75167d2c 3724static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 3725 struct CommandList *abort, int swizzle)
75167d2c
SC		 3726{
3727 int rc = IO_OK;
3728 struct CommandList *c;
3729 struct ErrorInfo *ei;
17eb87d2 3730 u32 tagupper, taglower;
75167d2c
SC		 3731
3732 c = cmd_special_alloc(h);
3733 if (c == NULL) { /* trouble... */
3734 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
3735 return -ENOMEM;
3736 }
3737
a2dac136
SC		 3738 /* fill_cmd can't fail here, no buffer to map */
3739 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
3740 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 3741 if (swizzle)
3742 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 3743 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 3744 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 3745 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 3746 __func__, tagupper, taglower);
75167d2c
SC		 3747 /* no unmap needed here because no data xfer. */
3748
3749 ei = c->err_info;
3750 switch (ei->CommandStatus) {
3751 case CMD_SUCCESS:
3752 break;
3753 case CMD_UNABORTABLE: /* Very common, don't make noise. */
3754 rc = -1;
3755 break;
3756 default:
3757 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 3758 __func__, tagupper, taglower);
75167d2c
SC		 3759 hpsa_scsi_interpret_error(c);
3760 rc = -1;
3761 break;
3762 }
3763 cmd_special_free(h, c);
3764 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
3765 abort->Header.Tag.upper, abort->Header.Tag.lower);
3766 return rc;
3767}
3768
3769/*
3770 * hpsa_find_cmd_in_queue
3771 *
3772 * Used to determine whether a command (find) is still present
3773 * in queue_head. Optionally excludes the last element of queue_head.
3774 *
3775 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
3776 * not yet been submitted, and so can be aborted by the driver without
3777 * sending an abort to the hardware.
3778 *
3779 * Returns pointer to command if found in queue, NULL otherwise.
3780 */
3781static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
3782 struct scsi_cmnd *find, struct list_head *queue_head)
3783{
3784 unsigned long flags;
3785 struct CommandList *c = NULL; /* ptr into cmpQ */
3786
3787 if (!find)
3788 return 0;
3789 spin_lock_irqsave(&h->lock, flags);
3790 list_for_each_entry(c, queue_head, list) {
3791 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
3792 continue;
3793 if (c->scsi_cmd == find) {
3794 spin_unlock_irqrestore(&h->lock, flags);
3795 return c;
3796 }
3797 }
3798 spin_unlock_irqrestore(&h->lock, flags);
3799 return NULL;
3800}
3801
6cba3f19
SC		 3802static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
3803 u8 *tag, struct list_head *queue_head)
3804{
3805 unsigned long flags;
3806 struct CommandList *c;
3807
3808 spin_lock_irqsave(&h->lock, flags);
3809 list_for_each_entry(c, queue_head, list) {
3810 if (memcmp(&c->Header.Tag, tag, 8) != 0)
3811 continue;
3812 spin_unlock_irqrestore(&h->lock, flags);
3813 return c;
3814 }
3815 spin_unlock_irqrestore(&h->lock, flags);
3816 return NULL;
3817}
3818
54b6e9e9
ST		 3819/* ioaccel2 path firmware cannot handle abort task requests.
3820 * Change abort requests to physical target reset, and send to the
3821 * address of the physical disk used for the ioaccel 2 command.
3822 * Return 0 on success (IO_OK)
3823 * -1 on failure
3824 */
3825
3826static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
3827 unsigned char *scsi3addr, struct CommandList *abort)
3828{
3829 int rc = IO_OK;
3830 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
3831 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
3832 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
3833 unsigned char *psa = &phys_scsi3addr[0];
3834
3835 /* Get a pointer to the hpsa logical device. */
3836 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
3837 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
3838 if (dev == NULL) {
3839 dev_warn(&h->pdev->dev,
3840 "Cannot abort: no device pointer for command.\n");
3841 return -1; /* not abortable */
3842 }
3843
3844 if (!dev->offload_enabled) {
3845 dev_warn(&h->pdev->dev,
3846 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
3847 return -1; /* not abortable */
3848 }
3849
3850 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
3851 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
3852 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
3853 return -1; /* not abortable */
3854 }
3855
3856 /* send the reset */
3857 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
3858 if (rc != 0) {
3859 dev_warn(&h->pdev->dev,
3860 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
3861 psa[0], psa[1], psa[2], psa[3],
3862 psa[4], psa[5], psa[6], psa[7]);
3863 return rc; /* failed to reset */
3864 }
3865
3866 /* wait for device to recover */
3867 if (wait_for_device_to_become_ready(h, psa) != 0) {
3868 dev_warn(&h->pdev->dev,
3869 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
3870 psa[0], psa[1], psa[2], psa[3],
3871 psa[4], psa[5], psa[6], psa[7]);
3872 return -1; /* failed to recover */
3873 }
3874
3875 /* device recovered */
3876 dev_info(&h->pdev->dev,
3877 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
3878 psa[0], psa[1], psa[2], psa[3],
3879 psa[4], psa[5], psa[6], psa[7]);
3880
3881 return rc; /* success */
3882}
3883
6cba3f19
SC		 3884/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
3885 * tell which kind we're dealing with, so we send the abort both ways. There
3886 * shouldn't be any collisions between swizzled and unswizzled tags due to the
3887 * way we construct our tags but we check anyway in case the assumptions which
3888 * make this true someday become false.
3889 */
3890static int hpsa_send_abort_both_ways(struct ctlr_info *h,
3891 unsigned char *scsi3addr, struct CommandList *abort)
3892{
3893 u8 swizzled_tag[8];
3894 struct CommandList *c;
3895 int rc = 0, rc2 = 0;
3896
54b6e9e9
ST		 3897 /* ioccelerator mode 2 commands should be aborted via the
3898 * accelerated path, since RAID path is unaware of these commands,
3899 * but underlying firmware can't handle abort TMF.
3900 * Change abort to physical device reset.
3901 */
3902 if (abort->cmd_type == CMD_IOACCEL2)
3903 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
3904
6cba3f19
SC		 3905 /* we do not expect to find the swizzled tag in our queue, but
3906 * check anyway just to be sure the assumptions which make this
3907 * the case haven't become wrong.
3908 */
3909 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
3910 swizzle_abort_tag(swizzled_tag);
3911 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
3912 if (c != NULL) {
3913 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
3914 return hpsa_send_abort(h, scsi3addr, abort, 0);
3915 }
3916 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
3917
3918 /* if the command is still in our queue, we can't conclude that it was
3919 * aborted (it might have just completed normally) but in any case
3920 * we don't need to try to abort it another way.
3921 */
3922 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
3923 if (c)
3924 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
3925 return rc && rc2;
3926}
3927
75167d2c
SC		 3928/* Send an abort for the specified command.
3929 * If the device and controller support it,
3930 * send a task abort request.
3931 */
3932static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
3933{
3934
3935 int i, rc;
3936 struct ctlr_info *h;
3937 struct hpsa_scsi_dev_t *dev;
3938 struct CommandList *abort; /* pointer to command to be aborted */
3939 struct CommandList *found;
3940 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
3941 char msg[256]; /* For debug messaging. */
3942 int ml = 0;
17eb87d2 3943 u32 tagupper, taglower;
75167d2c
SC		 3944
3945 /* Find the controller of the command to be aborted */
3946 h = sdev_to_hba(sc->device);
3947 if (WARN(h == NULL,
3948 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
3949 return FAILED;
3950
3951 /* Check that controller supports some kind of task abort */
3952 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
3953 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
3954 return FAILED;
3955
3956 memset(msg, 0, sizeof(msg));
3957 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ",
3958 h->scsi_host->host_no, sc->device->channel,
3959 sc->device->id, sc->device->lun);
3960
3961 /* Find the device of the command to be aborted */
3962 dev = sc->device->hostdata;
3963 if (!dev) {
3964 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
3965 msg);
3966 return FAILED;
3967 }
3968
3969 /* Get SCSI command to be aborted */
3970 abort = (struct CommandList *) sc->host_scribble;
3971 if (abort == NULL) {
3972 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
3973 msg);
3974 return FAILED;
3975 }
17eb87d2
ST		 3976 hpsa_get_tag(h, abort, &taglower, &tagupper);
3977 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 3978 as = (struct scsi_cmnd *) abort->scsi_cmd;
3979 if (as != NULL)
3980 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
3981 as->cmnd[0], as->serial_number);
3982 dev_dbg(&h->pdev->dev, "%s\n", msg);
3983 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
3984 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
3985
3986 /* Search reqQ to See if command is queued but not submitted,
3987 * if so, complete the command with aborted status and remove
3988 * it from the reqQ.
3989 */
3990 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
3991 if (found) {
3992 found->err_info->CommandStatus = CMD_ABORTED;
3993 finish_cmd(found);
3994 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
3995 msg);
3996 return SUCCESS;
3997 }
3998
3999 /* not in reqQ, if also not in cmpQ, must have already completed */
4000 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4001 if (!found) {
d6ebd0f7 4002 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 4003 msg);
4004 return SUCCESS;
4005 }
4006
4007 /*
4008 * Command is in flight, or possibly already completed
4009 * by the firmware (but not to the scsi mid layer) but we can't
4010 * distinguish which. Send the abort down.
4011 */
6cba3f19 4012 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 4013 if (rc != 0) {
4014 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
4015 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
4016 h->scsi_host->host_no,
4017 dev->bus, dev->target, dev->lun);
4018 return FAILED;
4019 }
4020 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
4021
4022 /* If the abort(s) above completed and actually aborted the
4023 * command, then the command to be aborted should already be
4024 * completed. If not, wait around a bit more to see if they
4025 * manage to complete normally.
4026 */
4027#define ABORT_COMPLETE_WAIT_SECS 30
4028 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
4029 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4030 if (!found)
4031 return SUCCESS;
4032 msleep(100);
4033 }
4034 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
4035 msg, ABORT_COMPLETE_WAIT_SECS);
4036 return FAILED;
4037}
4038
4039
edd16368
SC		 4040/*
4041 * For operations that cannot sleep, a command block is allocated at init,
4042 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4043 * which ones are free or in use. Lock must be held when calling this.
4044 * cmd_free() is the complement.
4045 */
4046static struct CommandList *cmd_alloc(struct ctlr_info *h)
4047{
4048 struct CommandList *c;
4049 int i;
4050 union u64bit temp64;
4051 dma_addr_t cmd_dma_handle, err_dma_handle;
e16a33ad 4052 unsigned long flags;
edd16368 4053
e16a33ad 4054 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4055 do {
4056 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
e16a33ad
MG		 4057 if (i == h->nr_cmds) {
4058 spin_unlock_irqrestore(&h->lock, flags);
edd16368 4059 return NULL;
e16a33ad 4060 }
edd16368
SC		 4061 } while (test_and_set_bit
4062 (i & (BITS_PER_LONG - 1),
4063 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
e16a33ad
MG		 4064 spin_unlock_irqrestore(&h->lock, flags);
4065
edd16368
SC		 4066 c = h->cmd_pool + i;
4067 memset(c, 0, sizeof(*c));
4068 cmd_dma_handle = h->cmd_pool_dhandle
4069 + i * sizeof(*c);
4070 c->err_info = h->errinfo_pool + i;
4071 memset(c->err_info, 0, sizeof(*c->err_info));
4072 err_dma_handle = h->errinfo_pool_dhandle
4073 + i * sizeof(*c->err_info);
edd16368
SC		 4074
4075 c->cmdindex = i;
4076
9e0fc764 4077 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4078 c->busaddr = (u32) cmd_dma_handle;
4079 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4080 c->ErrDesc.Addr.lower = temp64.val32.lower;
4081 c->ErrDesc.Addr.upper = temp64.val32.upper;
4082 c->ErrDesc.Len = sizeof(*c->err_info);
4083
4084 c->h = h;
4085 return c;
4086}
4087
4088/* For operations that can wait for kmalloc to possibly sleep,
4089 * this routine can be called. Lock need not be held to call
4090 * cmd_special_alloc. cmd_special_free() is the complement.
4091 */
4092static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
4093{
4094 struct CommandList *c;
4095 union u64bit temp64;
4096 dma_addr_t cmd_dma_handle, err_dma_handle;
4097
4098 c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
4099 if (c == NULL)
4100 return NULL;
4101 memset(c, 0, sizeof(*c));
4102
e1f7de0c 4103 c->cmd_type = CMD_SCSI;
edd16368
SC		 4104 c->cmdindex = -1;
4105
4106 c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
4107 &err_dma_handle);
4108
4109 if (c->err_info == NULL) {
4110 pci_free_consistent(h->pdev,
4111 sizeof(*c), c, cmd_dma_handle);
4112 return NULL;
4113 }
4114 memset(c->err_info, 0, sizeof(*c->err_info));
4115
9e0fc764 4116 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4117 c->busaddr = (u32) cmd_dma_handle;
4118 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4119 c->ErrDesc.Addr.lower = temp64.val32.lower;
4120 c->ErrDesc.Addr.upper = temp64.val32.upper;
4121 c->ErrDesc.Len = sizeof(*c->err_info);
4122
4123 c->h = h;
4124 return c;
4125}
4126
4127static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4128{
4129 int i;
e16a33ad 4130 unsigned long flags;
edd16368
SC		 4131
4132 i = c - h->cmd_pool;
e16a33ad 4133 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4134 clear_bit(i & (BITS_PER_LONG - 1),
4135 h->cmd_pool_bits + (i / BITS_PER_LONG));
e16a33ad 4136 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4137}
4138
4139static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
4140{
4141 union u64bit temp64;
4142
4143 temp64.val32.lower = c->ErrDesc.Addr.lower;
4144 temp64.val32.upper = c->ErrDesc.Addr.upper;
4145 pci_free_consistent(h->pdev, sizeof(*c->err_info),
4146 c->err_info, (dma_addr_t) temp64.val);
4147 pci_free_consistent(h->pdev, sizeof(*c),
d896f3f3 4148 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
edd16368
SC		 4149}
4150
4151#ifdef CONFIG_COMPAT
4152
edd16368
SC		 4153static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
4154{
4155 IOCTL32_Command_struct __user *arg32 =
4156 (IOCTL32_Command_struct __user *) arg;
4157 IOCTL_Command_struct arg64;
4158 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
4159 int err;
4160 u32 cp;
4161
938abd84 4162 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4163 err = 0;
4164 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4165 sizeof(arg64.LUN_info));
4166 err |= copy_from_user(&arg64.Request, &arg32->Request,
4167 sizeof(arg64.Request));
4168 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4169 sizeof(arg64.error_info));
4170 err |= get_user(arg64.buf_size, &arg32->buf_size);
4171 err |= get_user(cp, &arg32->buf);
4172 arg64.buf = compat_ptr(cp);
4173 err |= copy_to_user(p, &arg64, sizeof(arg64));
4174
4175 if (err)
4176 return -EFAULT;
4177
e39eeaed 4178 err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
edd16368
SC		 4179 if (err)
4180 return err;
4181 err |= copy_in_user(&arg32->error_info, &p->error_info,
4182 sizeof(arg32->error_info));
4183 if (err)
4184 return -EFAULT;
4185 return err;
4186}
4187
4188static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
4189 int cmd, void *arg)
4190{
4191 BIG_IOCTL32_Command_struct __user *arg32 =
4192 (BIG_IOCTL32_Command_struct __user *) arg;
4193 BIG_IOCTL_Command_struct arg64;
4194 BIG_IOCTL_Command_struct __user *p =
4195 compat_alloc_user_space(sizeof(arg64));
4196 int err;
4197 u32 cp;
4198
938abd84 4199 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4200 err = 0;
4201 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4202 sizeof(arg64.LUN_info));
4203 err |= copy_from_user(&arg64.Request, &arg32->Request,
4204 sizeof(arg64.Request));
4205 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4206 sizeof(arg64.error_info));
4207 err |= get_user(arg64.buf_size, &arg32->buf_size);
4208 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4209 err |= get_user(cp, &arg32->buf);
4210 arg64.buf = compat_ptr(cp);
4211 err |= copy_to_user(p, &arg64, sizeof(arg64));
4212
4213 if (err)
4214 return -EFAULT;
4215
e39eeaed 4216 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
edd16368
SC		 4217 if (err)
4218 return err;
4219 err |= copy_in_user(&arg32->error_info, &p->error_info,
4220 sizeof(arg32->error_info));
4221 if (err)
4222 return -EFAULT;
4223 return err;
4224}
71fe75a7
SC		 4225
4226static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
4227{
4228 switch (cmd) {
4229 case CCISS_GETPCIINFO:
4230 case CCISS_GETINTINFO:
4231 case CCISS_SETINTINFO:
4232 case CCISS_GETNODENAME:
4233 case CCISS_SETNODENAME:
4234 case CCISS_GETHEARTBEAT:
4235 case CCISS_GETBUSTYPES:
4236 case CCISS_GETFIRMVER:
4237 case CCISS_GETDRIVVER:
4238 case CCISS_REVALIDVOLS:
4239 case CCISS_DEREGDISK:
4240 case CCISS_REGNEWDISK:
4241 case CCISS_REGNEWD:
4242 case CCISS_RESCANDISK:
4243 case CCISS_GETLUNINFO:
4244 return hpsa_ioctl(dev, cmd, arg);
4245
4246 case CCISS_PASSTHRU32:
4247 return hpsa_ioctl32_passthru(dev, cmd, arg);
4248 case CCISS_BIG_PASSTHRU32:
4249 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4250
4251 default:
4252 return -ENOIOCTLCMD;
4253 }
4254}
edd16368
SC		 4255#endif
4256
4257static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4258{
4259 struct hpsa_pci_info pciinfo;
4260
4261 if (!argp)
4262 return -EINVAL;
4263 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4264 pciinfo.bus = h->pdev->bus->number;
4265 pciinfo.dev_fn = h->pdev->devfn;
4266 pciinfo.board_id = h->board_id;
4267 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4268 return -EFAULT;
4269 return 0;
4270}
4271
4272static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4273{
4274 DriverVer_type DriverVer;
4275 unsigned char vmaj, vmin, vsubmin;
4276 int rc;
4277
4278 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4279 &vmaj, &vmin, &vsubmin);
4280 if (rc != 3) {
4281 dev_info(&h->pdev->dev, "driver version string '%s' "
4282 "unrecognized.", HPSA_DRIVER_VERSION);
4283 vmaj = 0;
4284 vmin = 0;
4285 vsubmin = 0;
4286 }
4287 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4288 if (!argp)
4289 return -EINVAL;
4290 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4291 return -EFAULT;
4292 return 0;
4293}
4294
4295static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4296{
4297 IOCTL_Command_struct iocommand;
4298 struct CommandList *c;
4299 char *buff = NULL;
4300 union u64bit temp64;
c1f63c8f 4301 int rc = 0;
edd16368
SC		 4302
4303 if (!argp)
4304 return -EINVAL;
4305 if (!capable(CAP_SYS_RAWIO))
4306 return -EPERM;
4307 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4308 return -EFAULT;
4309 if ((iocommand.buf_size < 1) &&
4310 (iocommand.Request.Type.Direction != XFER_NONE)) {
4311 return -EINVAL;
4312 }
4313 if (iocommand.buf_size > 0) {
4314 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4315 if (buff == NULL)
4316 return -EFAULT;
b03a7771
SC		 4317 if (iocommand.Request.Type.Direction == XFER_WRITE) {
4318 /* Copy the data into the buffer we created */
4319 if (copy_from_user(buff, iocommand.buf,
4320 iocommand.buf_size)) {
c1f63c8f
SC		 4321 rc = -EFAULT;
4322 goto out_kfree;
b03a7771
SC		 4323 }
4324 } else {
4325 memset(buff, 0, iocommand.buf_size);
edd16368 4326 }
b03a7771 4327 }
edd16368
SC		 4328 c = cmd_special_alloc(h);
4329 if (c == NULL) {
c1f63c8f
SC		 4330 rc = -ENOMEM;
4331 goto out_kfree;
edd16368
SC		 4332 }
4333 /* Fill in the command type */
4334 c->cmd_type = CMD_IOCTL_PEND;
4335 /* Fill in Command Header */
4336 c->Header.ReplyQueue = 0; /* unused in simple mode */
4337 if (iocommand.buf_size > 0) { /* buffer to fill */
4338 c->Header.SGList = 1;
4339 c->Header.SGTotal = 1;
4340 } else { /* no buffers to fill */
4341 c->Header.SGList = 0;
4342 c->Header.SGTotal = 0;
4343 }
4344 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
4345 /* use the kernel address the cmd block for tag */
4346 c->Header.Tag.lower = c->busaddr;
4347
4348 /* Fill in Request block */
4349 memcpy(&c->Request, &iocommand.Request,
4350 sizeof(c->Request));
4351
4352 /* Fill in the scatter gather information */
4353 if (iocommand.buf_size > 0) {
4354 temp64.val = pci_map_single(h->pdev, buff,
4355 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4356 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4357 c->SG[0].Addr.lower = 0;
4358 c->SG[0].Addr.upper = 0;
4359 c->SG[0].Len = 0;
4360 rc = -ENOMEM;
4361 goto out;
4362 }
edd16368
SC		 4363 c->SG[0].Addr.lower = temp64.val32.lower;
4364 c->SG[0].Addr.upper = temp64.val32.upper;
4365 c->SG[0].Len = iocommand.buf_size;
e1d9cbfa 4366 c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/
edd16368 4367 }
a0c12413 4368 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 4369 if (iocommand.buf_size > 0)
4370 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4371 check_ioctl_unit_attention(h, c);
4372
4373 /* Copy the error information out */
4374 memcpy(&iocommand.error_info, c->err_info,
4375 sizeof(iocommand.error_info));
4376 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 4377 rc = -EFAULT;
4378 goto out;
edd16368 4379 }
b03a7771
SC		 4380 if (iocommand.Request.Type.Direction == XFER_READ &&
4381 iocommand.buf_size > 0) {
edd16368
SC		 4382 /* Copy the data out of the buffer we created */
4383 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 4384 rc = -EFAULT;
4385 goto out;
edd16368
SC		 4386 }
4387 }
c1f63c8f 4388out:
edd16368 4389 cmd_special_free(h, c);
c1f63c8f
SC		 4390out_kfree:
4391 kfree(buff);
4392 return rc;
edd16368
SC		 4393}
4394
4395static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4396{
4397 BIG_IOCTL_Command_struct *ioc;
4398 struct CommandList *c;
4399 unsigned char **buff = NULL;
4400 int *buff_size = NULL;
4401 union u64bit temp64;
4402 BYTE sg_used = 0;
4403 int status = 0;
4404 int i;
01a02ffc
SC		 4405 u32 left;
4406 u32 sz;
edd16368
SC		 4407 BYTE __user *data_ptr;
4408
4409 if (!argp)
4410 return -EINVAL;
4411 if (!capable(CAP_SYS_RAWIO))
4412 return -EPERM;
4413 ioc = (BIG_IOCTL_Command_struct *)
4414 kmalloc(sizeof(*ioc), GFP_KERNEL);
4415 if (!ioc) {
4416 status = -ENOMEM;
4417 goto cleanup1;
4418 }
4419 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
4420 status = -EFAULT;
4421 goto cleanup1;
4422 }
4423 if ((ioc->buf_size < 1) &&
4424 (ioc->Request.Type.Direction != XFER_NONE)) {
4425 status = -EINVAL;
4426 goto cleanup1;
4427 }
4428 /* Check kmalloc limits using all SGs */
4429 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
4430 status = -EINVAL;
4431 goto cleanup1;
4432 }
d66ae08b 4433 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 4434 status = -EINVAL;
4435 goto cleanup1;
4436 }
d66ae08b 4437 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 4438 if (!buff) {
4439 status = -ENOMEM;
4440 goto cleanup1;
4441 }
d66ae08b 4442 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 4443 if (!buff_size) {
4444 status = -ENOMEM;
4445 goto cleanup1;
4446 }
4447 left = ioc->buf_size;
4448 data_ptr = ioc->buf;
4449 while (left) {
4450 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
4451 buff_size[sg_used] = sz;
4452 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
4453 if (buff[sg_used] == NULL) {
4454 status = -ENOMEM;
4455 goto cleanup1;
4456 }
4457 if (ioc->Request.Type.Direction == XFER_WRITE) {
4458 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
4459 status = -ENOMEM;
4460 goto cleanup1;
4461 }
4462 } else
4463 memset(buff[sg_used], 0, sz);
4464 left -= sz;
4465 data_ptr += sz;
4466 sg_used++;
4467 }
4468 c = cmd_special_alloc(h);
4469 if (c == NULL) {
4470 status = -ENOMEM;
4471 goto cleanup1;
4472 }
4473 c->cmd_type = CMD_IOCTL_PEND;
4474 c->Header.ReplyQueue = 0;
b03a7771 4475 c->Header.SGList = c->Header.SGTotal = sg_used;
edd16368
SC		 4476 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
4477 c->Header.Tag.lower = c->busaddr;
4478 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
4479 if (ioc->buf_size > 0) {
4480 int i;
4481 for (i = 0; i < sg_used; i++) {
4482 temp64.val = pci_map_single(h->pdev, buff[i],
4483 buff_size[i], PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4484 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4485 c->SG[i].Addr.lower = 0;
4486 c->SG[i].Addr.upper = 0;
4487 c->SG[i].Len = 0;
4488 hpsa_pci_unmap(h->pdev, c, i,
4489 PCI_DMA_BIDIRECTIONAL);
4490 status = -ENOMEM;
e2d4a1f6 4491 goto cleanup0;
bcc48ffa 4492 }
edd16368
SC		 4493 c->SG[i].Addr.lower = temp64.val32.lower;
4494 c->SG[i].Addr.upper = temp64.val32.upper;
4495 c->SG[i].Len = buff_size[i];
e1d9cbfa 4496 c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST;
edd16368
SC		 4497 }
4498 }
a0c12413 4499 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 4500 if (sg_used)
4501 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4502 check_ioctl_unit_attention(h, c);
4503 /* Copy the error information out */
4504 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
4505 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 4506 status = -EFAULT;
e2d4a1f6 4507 goto cleanup0;
edd16368 4508 }
b03a7771 4509 if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
edd16368
SC		 4510 /* Copy the data out of the buffer we created */
4511 BYTE __user *ptr = ioc->buf;
4512 for (i = 0; i < sg_used; i++) {
4513 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 4514 status = -EFAULT;
e2d4a1f6 4515 goto cleanup0;
edd16368
SC		 4516 }
4517 ptr += buff_size[i];
4518 }
4519 }
edd16368 4520 status = 0;
e2d4a1f6
SC		 4521cleanup0:
4522 cmd_special_free(h, c);
edd16368
SC		 4523cleanup1:
4524 if (buff) {
4525 for (i = 0; i < sg_used; i++)
4526 kfree(buff[i]);
4527 kfree(buff);
4528 }
4529 kfree(buff_size);
4530 kfree(ioc);
4531 return status;
4532}
4533
4534static void check_ioctl_unit_attention(struct ctlr_info *h,
4535 struct CommandList *c)
4536{
4537 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4538 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
4539 (void) check_for_unit_attention(h, c);
4540}
0390f0c0
SC		 4541
4542static int increment_passthru_count(struct ctlr_info *h)
4543{
4544 unsigned long flags;
4545
4546 spin_lock_irqsave(&h->passthru_count_lock, flags);
4547 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
4548 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4549 return -1;
4550 }
4551 h->passthru_count++;
4552 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4553 return 0;
4554}
4555
4556static void decrement_passthru_count(struct ctlr_info *h)
4557{
4558 unsigned long flags;
4559
4560 spin_lock_irqsave(&h->passthru_count_lock, flags);
4561 if (h->passthru_count <= 0) {
4562 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4563 /* not expecting to get here. */
4564 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
4565 return;
4566 }
4567 h->passthru_count--;
4568 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4569}
4570
edd16368
SC		 4571/*
4572 * ioctl
4573 */
4574static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
4575{
4576 struct ctlr_info *h;
4577 void __user *argp = (void __user *)arg;
0390f0c0 4578 int rc;
edd16368
SC		 4579
4580 h = sdev_to_hba(dev);
4581
4582 switch (cmd) {
4583 case CCISS_DEREGDISK:
4584 case CCISS_REGNEWDISK:
4585 case CCISS_REGNEWD:
a08a8471 4586 hpsa_scan_start(h->scsi_host);
edd16368
SC		 4587 return 0;
4588 case CCISS_GETPCIINFO:
4589 return hpsa_getpciinfo_ioctl(h, argp);
4590 case CCISS_GETDRIVVER:
4591 return hpsa_getdrivver_ioctl(h, argp);
4592 case CCISS_PASSTHRU:
0390f0c0
SC		 4593 if (increment_passthru_count(h))
4594 return -EAGAIN;
4595 rc = hpsa_passthru_ioctl(h, argp);
4596 decrement_passthru_count(h);
4597 return rc;
edd16368 4598 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 4599 if (increment_passthru_count(h))
4600 return -EAGAIN;
4601 rc = hpsa_big_passthru_ioctl(h, argp);
4602 decrement_passthru_count(h);
4603 return rc;
edd16368
SC		 4604 default:
4605 return -ENOTTY;
4606 }
4607}
4608
6f039790
GKH		 4609static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
4610 u8 reset_type)
64670ac8
SC		 4611{
4612 struct CommandList *c;
4613
4614 c = cmd_alloc(h);
4615 if (!c)
4616 return -ENOMEM;
a2dac136
SC		 4617 /* fill_cmd can't fail here, no data buffer to map */
4618 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 4619 RAID_CTLR_LUNID, TYPE_MSG);
4620 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
4621 c->waiting = NULL;
4622 enqueue_cmd_and_start_io(h, c);
4623 /* Don't wait for completion, the reset won't complete. Don't free
4624 * the command either. This is the last command we will send before
4625 * re-initializing everything, so it doesn't matter and won't leak.
4626 */
4627 return 0;
4628}
4629
a2dac136 4630static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
01a02ffc 4631 void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
edd16368
SC		 4632 int cmd_type)
4633{
4634 int pci_dir = XFER_NONE;
75167d2c 4635 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 4636
4637 c->cmd_type = CMD_IOCTL_PEND;
4638 c->Header.ReplyQueue = 0;
4639 if (buff != NULL && size > 0) {
4640 c->Header.SGList = 1;
4641 c->Header.SGTotal = 1;
4642 } else {
4643 c->Header.SGList = 0;
4644 c->Header.SGTotal = 0;
4645 }
4646 c->Header.Tag.lower = c->busaddr;
4647 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
4648
4649 c->Request.Type.Type = cmd_type;
4650 if (cmd_type == TYPE_CMD) {
4651 switch (cmd) {
4652 case HPSA_INQUIRY:
4653 /* are we trying to read a vital product page */
4654 if (page_code != 0) {
4655 c->Request.CDB[1] = 0x01;
4656 c->Request.CDB[2] = page_code;
4657 }
4658 c->Request.CDBLen = 6;
4659 c->Request.Type.Attribute = ATTR_SIMPLE;
4660 c->Request.Type.Direction = XFER_READ;
4661 c->Request.Timeout = 0;
4662 c->Request.CDB[0] = HPSA_INQUIRY;
4663 c->Request.CDB[4] = size & 0xFF;
4664 break;
4665 case HPSA_REPORT_LOG:
4666 case HPSA_REPORT_PHYS:
4667 /* Talking to controller so It's a physical command
4668 mode = 00 target = 0. Nothing to write.
4669 */
4670 c->Request.CDBLen = 12;
4671 c->Request.Type.Attribute = ATTR_SIMPLE;
4672 c->Request.Type.Direction = XFER_READ;
4673 c->Request.Timeout = 0;
4674 c->Request.CDB[0] = cmd;
4675 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
4676 c->Request.CDB[7] = (size >> 16) & 0xFF;
4677 c->Request.CDB[8] = (size >> 8) & 0xFF;
4678 c->Request.CDB[9] = size & 0xFF;
4679 break;
edd16368
SC		 4680 case HPSA_CACHE_FLUSH:
4681 c->Request.CDBLen = 12;
4682 c->Request.Type.Attribute = ATTR_SIMPLE;
4683 c->Request.Type.Direction = XFER_WRITE;
4684 c->Request.Timeout = 0;
4685 c->Request.CDB[0] = BMIC_WRITE;
4686 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 4687 c->Request.CDB[7] = (size >> 8) & 0xFF;
4688 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 4689 break;
4690 case TEST_UNIT_READY:
4691 c->Request.CDBLen = 6;
4692 c->Request.Type.Attribute = ATTR_SIMPLE;
4693 c->Request.Type.Direction = XFER_NONE;
4694 c->Request.Timeout = 0;
4695 break;
283b4a9b
SC		 4696 case HPSA_GET_RAID_MAP:
4697 c->Request.CDBLen = 12;
4698 c->Request.Type.Attribute = ATTR_SIMPLE;
4699 c->Request.Type.Direction = XFER_READ;
4700 c->Request.Timeout = 0;
4701 c->Request.CDB[0] = HPSA_CISS_READ;
4702 c->Request.CDB[1] = cmd;
4703 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
4704 c->Request.CDB[7] = (size >> 16) & 0xFF;
4705 c->Request.CDB[8] = (size >> 8) & 0xFF;
4706 c->Request.CDB[9] = size & 0xFF;
4707 break;
edd16368
SC		 4708 default:
4709 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
4710 BUG();
a2dac136 4711 return -1;
edd16368
SC		 4712 }
4713 } else if (cmd_type == TYPE_MSG) {
4714 switch (cmd) {
4715
4716 case HPSA_DEVICE_RESET_MSG:
4717 c->Request.CDBLen = 16;
4718 c->Request.Type.Type = 1; /* It is a MSG not a CMD */
4719 c->Request.Type.Attribute = ATTR_SIMPLE;
4720 c->Request.Type.Direction = XFER_NONE;
4721 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 4722 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
4723 c->Request.CDB[0] = cmd;
21e89afd 4724 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 4725 /* If bytes 4-7 are zero, it means reset the */
4726 /* LunID device */
4727 c->Request.CDB[4] = 0x00;
4728 c->Request.CDB[5] = 0x00;
4729 c->Request.CDB[6] = 0x00;
4730 c->Request.CDB[7] = 0x00;
75167d2c
SC		 4731 break;
4732 case HPSA_ABORT_MSG:
4733 a = buff; /* point to command to be aborted */
4734 dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n",
4735 a->Header.Tag.upper, a->Header.Tag.lower,
4736 c->Header.Tag.upper, c->Header.Tag.lower);
4737 c->Request.CDBLen = 16;
4738 c->Request.Type.Type = TYPE_MSG;
4739 c->Request.Type.Attribute = ATTR_SIMPLE;
4740 c->Request.Type.Direction = XFER_WRITE;
4741 c->Request.Timeout = 0; /* Don't time out */
4742 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
4743 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
4744 c->Request.CDB[2] = 0x00; /* reserved */
4745 c->Request.CDB[3] = 0x00; /* reserved */
4746 /* Tag to abort goes in CDB[4]-CDB[11] */
4747 c->Request.CDB[4] = a->Header.Tag.lower & 0xFF;
4748 c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF;
4749 c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF;
4750 c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF;
4751 c->Request.CDB[8] = a->Header.Tag.upper & 0xFF;
4752 c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF;
4753 c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF;
4754 c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF;
4755 c->Request.CDB[12] = 0x00; /* reserved */
4756 c->Request.CDB[13] = 0x00; /* reserved */
4757 c->Request.CDB[14] = 0x00; /* reserved */
4758 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 4759 break;
edd16368
SC		 4760 default:
4761 dev_warn(&h->pdev->dev, "unknown message type %d\n",
4762 cmd);
4763 BUG();
4764 }
4765 } else {
4766 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
4767 BUG();
4768 }
4769
4770 switch (c->Request.Type.Direction) {
4771 case XFER_READ:
4772 pci_dir = PCI_DMA_FROMDEVICE;
4773 break;
4774 case XFER_WRITE:
4775 pci_dir = PCI_DMA_TODEVICE;
4776 break;
4777 case XFER_NONE:
4778 pci_dir = PCI_DMA_NONE;
4779 break;
4780 default:
4781 pci_dir = PCI_DMA_BIDIRECTIONAL;
4782 }
a2dac136
SC		 4783 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
4784 return -1;
4785 return 0;
edd16368
SC		 4786}
4787
4788/*
4789 * Map (physical) PCI mem into (virtual) kernel space
4790 */
4791static void __iomem *remap_pci_mem(ulong base, ulong size)
4792{
4793 ulong page_base = ((ulong) base) & PAGE_MASK;
4794 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 4795 void __iomem *page_remapped = ioremap_nocache(page_base,
4796 page_offs + size);
edd16368
SC		 4797
4798 return page_remapped ? (page_remapped + page_offs) : NULL;
4799}
4800
4801/* Takes cmds off the submission queue and sends them to the hardware,
4802 * then puts them on the queue of cmds waiting for completion.
4803 */
4804static void start_io(struct ctlr_info *h)
4805{
4806 struct CommandList *c;
e16a33ad 4807 unsigned long flags;
edd16368 4808
e16a33ad 4809 spin_lock_irqsave(&h->lock, flags);
9e0fc764
SC		 4810 while (!list_empty(&h->reqQ)) {
4811 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 4812 /* can't do anything if fifo is full */
4813 if ((h->access.fifo_full(h))) {
396883e2 4814 h->fifo_recently_full = 1;
edd16368
SC		 4815 dev_warn(&h->pdev->dev, "fifo full\n");
4816 break;
4817 }
396883e2 4818 h->fifo_recently_full = 0;
edd16368
SC		 4819
4820 /* Get the first entry from the Request Q */
4821 removeQ(c);
4822 h->Qdepth--;
4823
edd16368
SC		 4824 /* Put job onto the completed Q */
4825 addQ(&h->cmpQ, c);
e16a33ad
MG		 4826
4827 /* Must increment commands_outstanding before unlocking
4828 * and submitting to avoid race checking for fifo full
4829 * condition.
4830 */
4831 h->commands_outstanding++;
4832 if (h->commands_outstanding > h->max_outstanding)
4833 h->max_outstanding = h->commands_outstanding;
4834
4835 /* Tell the controller execute command */
4836 spin_unlock_irqrestore(&h->lock, flags);
4837 h->access.submit_command(h, c);
4838 spin_lock_irqsave(&h->lock, flags);
edd16368 4839 }
e16a33ad 4840 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4841}
4842
254f796b 4843static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 4844{
254f796b 4845 return h->access.command_completed(h, q);
edd16368
SC		 4846}
4847
900c5440 4848static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 4849{
4850 return h->access.intr_pending(h);
4851}
4852
4853static inline long interrupt_not_for_us(struct ctlr_info *h)
4854{
10f66018
SC		 4855 return (h->access.intr_pending(h) == 0) ||
4856 (h->interrupts_enabled == 0);
edd16368
SC		 4857}
4858
01a02ffc
SC		 4859static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
4860 u32 raw_tag)
edd16368
SC		 4861{
4862 if (unlikely(tag_index >= h->nr_cmds)) {
4863 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
4864 return 1;
4865 }
4866 return 0;
4867}
4868
5a3d16f5 4869static inline void finish_cmd(struct CommandList *c)
edd16368 4870{
e16a33ad 4871 unsigned long flags;
396883e2
SC		 4872 int io_may_be_stalled = 0;
4873 struct ctlr_info *h = c->h;
e16a33ad 4874
396883e2 4875 spin_lock_irqsave(&h->lock, flags);
edd16368 4876 removeQ(c);
396883e2
SC		 4877
4878 /*
4879 * Check for possibly stalled i/o.
4880 *
4881 * If a fifo_full condition is encountered, requests will back up
4882 * in h->reqQ. This queue is only emptied out by start_io which is
4883 * only called when a new i/o request comes in. If no i/o's are
4884 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
4885 * start_io from here if we detect such a danger.
4886 *
4887 * Normally, we shouldn't hit this case, but pounding on the
4888 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
4889 * commands_outstanding is low. We want to avoid calling
4890 * start_io from in here as much as possible, and esp. don't
4891 * want to get in a cycle where we call start_io every time
4892 * through here.
4893 */
4894 if (unlikely(h->fifo_recently_full) &&
4895 h->commands_outstanding < 5)
4896 io_may_be_stalled = 1;
4897
4898 spin_unlock_irqrestore(&h->lock, flags);
4899
e85c5974 4900 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 4901 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
4902 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 4903 complete_scsi_command(c);
edd16368
SC		 4904 else if (c->cmd_type == CMD_IOCTL_PEND)
4905 complete(c->waiting);
396883e2
SC		 4906 if (unlikely(io_may_be_stalled))
4907 start_io(h);
edd16368
SC		 4908}
4909
a104c99f
SC		 4910static inline u32 hpsa_tag_contains_index(u32 tag)
4911{
a104c99f
SC		 4912 return tag & DIRECT_LOOKUP_BIT;
4913}
4914
4915static inline u32 hpsa_tag_to_index(u32 tag)
4916{
a104c99f
SC		 4917 return tag >> DIRECT_LOOKUP_SHIFT;
4918}
4919
a9a3a273
SC		 4920
4921static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 4922{
a9a3a273
SC		 4923#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
4924#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 4925 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 4926 return tag & ~HPSA_SIMPLE_ERROR_BITS;
4927 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 4928}
4929
303932fd 4930/* process completion of an indexed ("direct lookup") command */
1d94f94d 4931static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 4932 u32 raw_tag)
4933{
4934 u32 tag_index;
4935 struct CommandList *c;
4936
4937 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 4938 if (!bad_tag(h, tag_index, raw_tag)) {
4939 c = h->cmd_pool + tag_index;
4940 finish_cmd(c);
4941 }
303932fd
DB		 4942}
4943
4944/* process completion of a non-indexed command */
1d94f94d 4945static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 4946 u32 raw_tag)
4947{
4948 u32 tag;
4949 struct CommandList *c = NULL;
e16a33ad 4950 unsigned long flags;
303932fd 4951
a9a3a273 4952 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 4953 spin_lock_irqsave(&h->lock, flags);
9e0fc764 4954 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 4955 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 4956 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 4957 finish_cmd(c);
1d94f94d 4958 return;
303932fd
DB		 4959 }
4960 }
e16a33ad 4961 spin_unlock_irqrestore(&h->lock, flags);
303932fd 4962 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 4963}
4964
64670ac8
SC		 4965/* Some controllers, like p400, will give us one interrupt
4966 * after a soft reset, even if we turned interrupts off.
4967 * Only need to check for this in the hpsa_xxx_discard_completions
4968 * functions.
4969 */
4970static int ignore_bogus_interrupt(struct ctlr_info *h)
4971{
4972 if (likely(!reset_devices))
4973 return 0;
4974
4975 if (likely(h->interrupts_enabled))
4976 return 0;
4977
4978 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
4979 "(known firmware bug.) Ignoring.\n");
4980
4981 return 1;
4982}
4983
254f796b
MG		 4984/*
4985 * Convert &h->q[x] (passed to interrupt handlers) back to h.
4986 * Relies on (h-q[x] == x) being true for x such that
4987 * 0 <= x < MAX_REPLY_QUEUES.
4988 */
4989static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 4990{
254f796b
MG		 4991 return container_of((queue - *queue), struct ctlr_info, q[0]);
4992}
4993
4994static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
4995{
4996 struct ctlr_info *h = queue_to_hba(queue);
4997 u8 q = *(u8 *) queue;
64670ac8
SC		 4998 u32 raw_tag;
4999
5000 if (ignore_bogus_interrupt(h))
5001 return IRQ_NONE;
5002
5003 if (interrupt_not_for_us(h))
5004 return IRQ_NONE;
a0c12413 5005 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5006 while (interrupt_pending(h)) {
254f796b 5007 raw_tag = get_next_completion(h, q);
64670ac8 5008 while (raw_tag != FIFO_EMPTY)
254f796b 5009 raw_tag = next_command(h, q);
64670ac8 5010 }
64670ac8
SC		 5011 return IRQ_HANDLED;
5012}
5013
254f796b 5014static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5015{
254f796b 5016 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5017 u32 raw_tag;
254f796b 5018 u8 q = *(u8 *) queue;
64670ac8
SC		 5019
5020 if (ignore_bogus_interrupt(h))
5021 return IRQ_NONE;
5022
a0c12413 5023 h->last_intr_timestamp = get_jiffies_64();
254f796b 5024 raw_tag = get_next_completion(h, q);
64670ac8 5025 while (raw_tag != FIFO_EMPTY)
254f796b 5026 raw_tag = next_command(h, q);
64670ac8
SC		 5027 return IRQ_HANDLED;
5028}
5029
254f796b 5030static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5031{
254f796b 5032 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5033 u32 raw_tag;
254f796b 5034 u8 q = *(u8 *) queue;
edd16368
SC		 5035
5036 if (interrupt_not_for_us(h))
5037 return IRQ_NONE;
a0c12413 5038 h->last_intr_timestamp = get_jiffies_64();
10f66018 5039 while (interrupt_pending(h)) {
254f796b 5040 raw_tag = get_next_completion(h, q);
10f66018 5041 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5042 if (likely(hpsa_tag_contains_index(raw_tag)))
5043 process_indexed_cmd(h, raw_tag);
10f66018 5044 else
1d94f94d 5045 process_nonindexed_cmd(h, raw_tag);
254f796b 5046 raw_tag = next_command(h, q);
10f66018
SC		 5047 }
5048 }
10f66018
SC		 5049 return IRQ_HANDLED;
5050}
5051
254f796b 5052static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5053{
254f796b 5054 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5055 u32 raw_tag;
254f796b 5056 u8 q = *(u8 *) queue;
10f66018 5057
a0c12413 5058 h->last_intr_timestamp = get_jiffies_64();
254f796b 5059 raw_tag = get_next_completion(h, q);
303932fd 5060 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5061 if (likely(hpsa_tag_contains_index(raw_tag)))
5062 process_indexed_cmd(h, raw_tag);
303932fd 5063 else
1d94f94d 5064 process_nonindexed_cmd(h, raw_tag);
254f796b 5065 raw_tag = next_command(h, q);
edd16368 5066 }
edd16368
SC		 5067 return IRQ_HANDLED;
5068}
5069
a9a3a273
SC		 5070/* Send a message CDB to the firmware. Careful, this only works
5071 * in simple mode, not performant mode due to the tag lookup.
5072 * We only ever use this immediately after a controller reset.
5073 */
6f039790
GKH		 5074static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5075 unsigned char type)
edd16368
SC		 5076{
5077 struct Command {
5078 struct CommandListHeader CommandHeader;
5079 struct RequestBlock Request;
5080 struct ErrDescriptor ErrorDescriptor;
5081 };
5082 struct Command *cmd;
5083 static const size_t cmd_sz = sizeof(*cmd) +
5084 sizeof(cmd->ErrorDescriptor);
5085 dma_addr_t paddr64;
5086 uint32_t paddr32, tag;
5087 void __iomem *vaddr;
5088 int i, err;
5089
5090 vaddr = pci_ioremap_bar(pdev, 0);
5091 if (vaddr == NULL)
5092 return -ENOMEM;
5093
5094 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5095 * CCISS commands, so they must be allocated from the lower 4GiB of
5096 * memory.
5097 */
5098 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5099 if (err) {
5100 iounmap(vaddr);
5101 return -ENOMEM;
5102 }
5103
5104 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5105 if (cmd == NULL) {
5106 iounmap(vaddr);
5107 return -ENOMEM;
5108 }
5109
5110 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5111 * although there's no guarantee, we assume that the address is at
5112 * least 4-byte aligned (most likely, it's page-aligned).
5113 */
5114 paddr32 = paddr64;
5115
5116 cmd->CommandHeader.ReplyQueue = 0;
5117 cmd->CommandHeader.SGList = 0;
5118 cmd->CommandHeader.SGTotal = 0;
5119 cmd->CommandHeader.Tag.lower = paddr32;
5120 cmd->CommandHeader.Tag.upper = 0;
5121 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5122
5123 cmd->Request.CDBLen = 16;
5124 cmd->Request.Type.Type = TYPE_MSG;
5125 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
5126 cmd->Request.Type.Direction = XFER_NONE;
5127 cmd->Request.Timeout = 0; /* Don't time out */
5128 cmd->Request.CDB[0] = opcode;
5129 cmd->Request.CDB[1] = type;
5130 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
5131 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
5132 cmd->ErrorDescriptor.Addr.upper = 0;
5133 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
5134
5135 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
5136
5137 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5138 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
a9a3a273 5139 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
edd16368
SC		 5140 break;
5141 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5142 }
5143
5144 iounmap(vaddr);
5145
5146 /* we leak the DMA buffer here ... no choice since the controller could
5147 * still complete the command.
5148 */
5149 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5150 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5151 opcode, type);
5152 return -ETIMEDOUT;
5153 }
5154
5155 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5156
5157 if (tag & HPSA_ERROR_BIT) {
5158 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5159 opcode, type);
5160 return -EIO;
5161 }
5162
5163 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5164 opcode, type);
5165 return 0;
5166}
5167
edd16368
SC		 5168#define hpsa_noop(p) hpsa_message(p, 3, 0)
5169
1df8552a 5170static int hpsa_controller_hard_reset(struct pci_dev *pdev,
cf0b08d0 5171 void * __iomem vaddr, u32 use_doorbell)
1df8552a
SC		 5172{
5173 u16 pmcsr;
5174 int pos;
5175
5176 if (use_doorbell) {
5177 /* For everything after the P600, the PCI power state method
5178 * of resetting the controller doesn't work, so we have this
5179 * other way using the doorbell register.
5180 */
5181 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5182 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239
SC		 5183
5184 /* PMC hardware guys tell us we need a 5 second delay after
5185 * doorbell reset and before any attempt to talk to the board
5186 * at all to ensure that this actually works and doesn't fall
5187 * over in some weird corner cases.
5188 */
5189 msleep(5000);
1df8552a
SC		 5190 } else { /* Try to do it the PCI power state way */
5191
5192 /* Quoting from the Open CISS Specification: "The Power
5193 * Management Control/Status Register (CSR) controls the power
5194 * state of the device. The normal operating state is D0,
5195 * CSR=00h. The software off state is D3, CSR=03h. To reset
5196 * the controller, place the interface device in D3 then to D0,
5197 * this causes a secondary PCI reset which will reset the
5198 * controller." */
5199
5200 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
5201 if (pos == 0) {
5202 dev_err(&pdev->dev,
5203 "hpsa_reset_controller: "
5204 "PCI PM not supported\n");
5205 return -ENODEV;
5206 }
5207 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
5208 /* enter the D3hot power management state */
5209 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
5210 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5211 pmcsr |= PCI_D3hot;
5212 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
5213
5214 msleep(500);
5215
5216 /* enter the D0 power management state */
5217 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5218 pmcsr |= PCI_D0;
5219 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
c4853efe
MM		 5220
5221 /*
5222 * The P600 requires a small delay when changing states.
5223 * Otherwise we may think the board did not reset and we bail.
5224 * This for kdump only and is particular to the P600.
5225 */
5226 msleep(500);
1df8552a
SC		 5227 }
5228 return 0;
5229}
5230
6f039790 5231static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5232{
5233 memset(driver_version, 0, len);
f79cfec6 5234 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5235}
5236
6f039790 5237static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5238{
5239 char *driver_version;
5240 int i, size = sizeof(cfgtable->driver_version);
5241
5242 driver_version = kmalloc(size, GFP_KERNEL);
5243 if (!driver_version)
5244 return -ENOMEM;
5245
5246 init_driver_version(driver_version, size);
5247 for (i = 0; i < size; i++)
5248 writeb(driver_version[i], &cfgtable->driver_version[i]);
5249 kfree(driver_version);
5250 return 0;
5251}
5252
6f039790
GKH		 5253static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5254 unsigned char *driver_ver)
580ada3c
SC		 5255{
5256 int i;
5257
5258 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5259 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5260}
5261
6f039790 5262static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5263{
5264
5265 char *driver_ver, *old_driver_ver;
5266 int rc, size = sizeof(cfgtable->driver_version);
5267
5268 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5269 if (!old_driver_ver)
5270 return -ENOMEM;
5271 driver_ver = old_driver_ver + size;
5272
5273 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5274 * should have been changed, otherwise we know the reset failed.
5275 */
5276 init_driver_version(old_driver_ver, size);
5277 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5278 rc = !memcmp(driver_ver, old_driver_ver, size);
5279 kfree(old_driver_ver);
5280 return rc;
5281}
edd16368 5282/* This does a hard reset of the controller using PCI power management
1df8552a 5283 * states or the using the doorbell register.
edd16368 5284 */
6f039790 5285static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5286{
1df8552a
SC		 5287 u64 cfg_offset;
5288 u32 cfg_base_addr;
5289 u64 cfg_base_addr_index;
5290 void __iomem *vaddr;
5291 unsigned long paddr;
580ada3c 5292 u32 misc_fw_support;
270d05de 5293 int rc;
1df8552a 5294 struct CfgTable __iomem *cfgtable;
cf0b08d0 5295 u32 use_doorbell;
18867659 5296 u32 board_id;
270d05de 5297 u16 command_register;
edd16368 5298
1df8552a
SC		 5299 /* For controllers as old as the P600, this is very nearly
5300 * the same thing as
edd16368
SC		 5301 *
5302 * pci_save_state(pci_dev);
5303 * pci_set_power_state(pci_dev, PCI_D3hot);
5304 * pci_set_power_state(pci_dev, PCI_D0);
5305 * pci_restore_state(pci_dev);
5306 *
1df8552a
SC		 5307 * For controllers newer than the P600, the pci power state
5308 * method of resetting doesn't work so we have another way
5309 * using the doorbell register.
edd16368 5310 */
18867659 5311
25c1e56a 5312 rc = hpsa_lookup_board_id(pdev, &board_id);
46380786 5313 if (rc < 0 || !ctlr_is_resettable(board_id)) {
25c1e56a
SC		 5314 dev_warn(&pdev->dev, "Not resetting device.\n");
5315 return -ENODEV;
5316 }
46380786
SC		 5317
5318 /* if controller is soft- but not hard resettable... */
5319 if (!ctlr_is_hard_resettable(board_id))
5320 return -ENOTSUPP; /* try soft reset later. */
18867659 5321
270d05de
SC		 5322 /* Save the PCI command register */
5323 pci_read_config_word(pdev, 4, &command_register);
5324 /* Turn the board off. This is so that later pci_restore_state()
5325 * won't turn the board on before the rest of config space is ready.
5326 */
5327 pci_disable_device(pdev);
5328 pci_save_state(pdev);
edd16368 5329
1df8552a
SC		 5330 /* find the first memory BAR, so we can find the cfg table */
5331 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5332 if (rc)
5333 return rc;
5334 vaddr = remap_pci_mem(paddr, 0x250);
5335 if (!vaddr)
5336 return -ENOMEM;
edd16368 5337
1df8552a
SC		 5338 /* find cfgtable in order to check if reset via doorbell is supported */
5339 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
5340 &cfg_base_addr_index, &cfg_offset);
5341 if (rc)
5342 goto unmap_vaddr;
5343 cfgtable = remap_pci_mem(pci_resource_start(pdev,
5344 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
5345 if (!cfgtable) {
5346 rc = -ENOMEM;
5347 goto unmap_vaddr;
5348 }
580ada3c
SC		 5349 rc = write_driver_ver_to_cfgtable(cfgtable);
5350 if (rc)
5351 goto unmap_vaddr;
edd16368 5352
cf0b08d0
SC		 5353 /* If reset via doorbell register is supported, use that.
5354 * There are two such methods. Favor the newest method.
5355 */
1df8552a 5356 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 5357 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
5358 if (use_doorbell) {
5359 use_doorbell = DOORBELL_CTLR_RESET2;
5360 } else {
5361 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
5362 if (use_doorbell) {
fba63097
MM		 5363 dev_warn(&pdev->dev, "Soft reset not supported. "
5364 "Firmware update is required.\n");
64670ac8 5365 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 5366 goto unmap_cfgtable;
5367 }
5368 }
edd16368 5369
1df8552a
SC		 5370 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
5371 if (rc)
5372 goto unmap_cfgtable;
edd16368 5373
270d05de
SC		 5374 pci_restore_state(pdev);
5375 rc = pci_enable_device(pdev);
5376 if (rc) {
5377 dev_warn(&pdev->dev, "failed to enable device.\n");
5378 goto unmap_cfgtable;
edd16368 5379 }
270d05de 5380 pci_write_config_word(pdev, 4, command_register);
edd16368 5381
1df8552a
SC		 5382 /* Some devices (notably the HP Smart Array 5i Controller)
5383 need a little pause here */
5384 msleep(HPSA_POST_RESET_PAUSE_MSECS);
5385
fe5389c8
SC		 5386 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
5387 if (rc) {
5388 dev_warn(&pdev->dev,
64670ac8
SC		 5389 "failed waiting for board to become ready "
5390 "after hard reset\n");
fe5389c8
SC		 5391 goto unmap_cfgtable;
5392 }
fe5389c8 5393
580ada3c
SC		 5394 rc = controller_reset_failed(vaddr);
5395 if (rc < 0)
5396 goto unmap_cfgtable;
5397 if (rc) {
64670ac8
SC		 5398 dev_warn(&pdev->dev, "Unable to successfully reset "
5399 "controller. Will try soft reset.\n");
5400 rc = -ENOTSUPP;
580ada3c 5401 } else {
64670ac8 5402 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 5403 }
5404
5405unmap_cfgtable:
5406 iounmap(cfgtable);
5407
5408unmap_vaddr:
5409 iounmap(vaddr);
5410 return rc;
edd16368
SC		 5411}
5412
5413/*
5414 * We cannot read the structure directly, for portability we must use
5415 * the io functions.
5416 * This is for debug only.
5417 */
edd16368
SC		 5418static void print_cfg_table(struct device *dev, struct CfgTable *tb)
5419{
58f8665c 5420#ifdef HPSA_DEBUG
edd16368
SC		 5421 int i;
5422 char temp_name[17];
5423
5424 dev_info(dev, "Controller Configuration information\n");
5425 dev_info(dev, "------------------------------------\n");
5426 for (i = 0; i < 4; i++)
5427 temp_name[i] = readb(&(tb->Signature[i]));
5428 temp_name[4] = '\0';
5429 dev_info(dev, " Signature = %s\n", temp_name);
5430 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
5431 dev_info(dev, " Transport methods supported = 0x%x\n",
5432 readl(&(tb->TransportSupport)));
5433 dev_info(dev, " Transport methods active = 0x%x\n",
5434 readl(&(tb->TransportActive)));
5435 dev_info(dev, " Requested transport Method = 0x%x\n",
5436 readl(&(tb->HostWrite.TransportRequest)));
5437 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
5438 readl(&(tb->HostWrite.CoalIntDelay)));
5439 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
5440 readl(&(tb->HostWrite.CoalIntCount)));
5441 dev_info(dev, " Max outstanding commands = 0x%d\n",
5442 readl(&(tb->CmdsOutMax)));
5443 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
5444 for (i = 0; i < 16; i++)
5445 temp_name[i] = readb(&(tb->ServerName[i]));
5446 temp_name[16] = '\0';
5447 dev_info(dev, " Server Name = %s\n", temp_name);
5448 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
5449 readl(&(tb->HeartBeat)));
edd16368 5450#endif /* HPSA_DEBUG */
58f8665c 5451}
edd16368
SC		 5452
5453static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
5454{
5455 int i, offset, mem_type, bar_type;
5456
5457 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
5458 return 0;
5459 offset = 0;
5460 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5461 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
5462 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
5463 offset += 4;
5464 else {
5465 mem_type = pci_resource_flags(pdev, i) &
5466 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
5467 switch (mem_type) {
5468 case PCI_BASE_ADDRESS_MEM_TYPE_32:
5469 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
5470 offset += 4; /* 32 bit */
5471 break;
5472 case PCI_BASE_ADDRESS_MEM_TYPE_64:
5473 offset += 8;
5474 break;
5475 default: /* reserved in PCI 2.2 */
5476 dev_warn(&pdev->dev,
5477 "base address is invalid\n");
5478 return -1;
5479 break;
5480 }
5481 }
5482 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
5483 return i + 1;
5484 }
5485 return -1;
5486}
5487
5488/* If MSI/MSI-X is supported by the kernel we will try to enable it on
5489 * controllers that are capable. If not, we use IO-APIC mode.
5490 */
5491
6f039790 5492static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 5493{
5494#ifdef CONFIG_PCI_MSI
254f796b
MG		 5495 int err, i;
5496 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
5497
5498 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
5499 hpsa_msix_entries[i].vector = 0;
5500 hpsa_msix_entries[i].entry = i;
5501 }
edd16368
SC		 5502
5503 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 5504 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
5505 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 5506 goto default_int_mode;
55c06c71
SC		 5507 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
5508 dev_info(&h->pdev->dev, "MSIX\n");
eee0f03a 5509 h->msix_vector = MAX_REPLY_QUEUES;
254f796b 5510 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
eee0f03a 5511 h->msix_vector);
edd16368 5512 if (err > 0) {
55c06c71 5513 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 5514 "available\n", err);
eee0f03a
HR		 5515 h->msix_vector = err;
5516 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
5517 h->msix_vector);
5518 }
5519 if (!err) {
5520 for (i = 0; i < h->msix_vector; i++)
5521 h->intr[i] = hpsa_msix_entries[i].vector;
5522 return;
edd16368 5523 } else {
55c06c71 5524 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
edd16368 5525 err);
eee0f03a 5526 h->msix_vector = 0;
edd16368
SC		 5527 goto default_int_mode;
5528 }
5529 }
55c06c71
SC		 5530 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
5531 dev_info(&h->pdev->dev, "MSI\n");
5532 if (!pci_enable_msi(h->pdev))
edd16368
SC		 5533 h->msi_vector = 1;
5534 else
55c06c71 5535 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 5536 }
5537default_int_mode:
5538#endif /* CONFIG_PCI_MSI */
5539 /* if we get here we're going to use the default interrupt mode */
a9a3a273 5540 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 5541}
5542
6f039790 5543static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 5544{
5545 int i;
5546 u32 subsystem_vendor_id, subsystem_device_id;
5547
5548 subsystem_vendor_id = pdev->subsystem_vendor;
5549 subsystem_device_id = pdev->subsystem_device;
5550 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
5551 subsystem_vendor_id;
5552
5553 for (i = 0; i < ARRAY_SIZE(products); i++)
5554 if (*board_id == products[i].board_id)
5555 return i;
5556
6798cc0a
SC		 5557 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
5558 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
5559 !hpsa_allow_any) {
e5c880d1
SC		 5560 dev_warn(&pdev->dev, "unrecognized board ID: "
5561 "0x%08x, ignoring.\n", *board_id);
5562 return -ENODEV;
5563 }
5564 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
5565}
5566
6f039790
GKH		 5567static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
5568 unsigned long *memory_bar)
3a7774ce
SC		 5569{
5570 int i;
5571
5572 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 5573 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 5574 /* addressing mode bits already removed */
12d2cd47
SC		 5575 *memory_bar = pci_resource_start(pdev, i);
5576 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 5577 *memory_bar);
5578 return 0;
5579 }
12d2cd47 5580 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 5581 return -ENODEV;
5582}
5583
6f039790
GKH		 5584static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
5585 int wait_for_ready)
2c4c8c8b 5586{
fe5389c8 5587 int i, iterations;
2c4c8c8b 5588 u32 scratchpad;
fe5389c8
SC		 5589 if (wait_for_ready)
5590 iterations = HPSA_BOARD_READY_ITERATIONS;
5591 else
5592 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 5593
fe5389c8
SC		 5594 for (i = 0; i < iterations; i++) {
5595 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
5596 if (wait_for_ready) {
5597 if (scratchpad == HPSA_FIRMWARE_READY)
5598 return 0;
5599 } else {
5600 if (scratchpad != HPSA_FIRMWARE_READY)
5601 return 0;
5602 }
2c4c8c8b
SC		 5603 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
5604 }
fe5389c8 5605 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 5606 return -ENODEV;
5607}
5608
6f039790
GKH		 5609static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
5610 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
5611 u64 *cfg_offset)
a51fd47f
SC		 5612{
5613 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
5614 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
5615 *cfg_base_addr &= (u32) 0x0000ffff;
5616 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
5617 if (*cfg_base_addr_index == -1) {
5618 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
5619 return -ENODEV;
5620 }
5621 return 0;
5622}
5623
6f039790 5624static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 5625{
01a02ffc
SC		 5626 u64 cfg_offset;
5627 u32 cfg_base_addr;
5628 u64 cfg_base_addr_index;
303932fd 5629 u32 trans_offset;
a51fd47f 5630 int rc;
77c4495c 5631
a51fd47f
SC		 5632 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
5633 &cfg_base_addr_index, &cfg_offset);
5634 if (rc)
5635 return rc;
77c4495c 5636 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 5637 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
77c4495c
SC		 5638 if (!h->cfgtable)
5639 return -ENOMEM;
580ada3c
SC		 5640 rc = write_driver_ver_to_cfgtable(h->cfgtable);
5641 if (rc)
5642 return rc;
77c4495c 5643 /* Find performant mode table. */
a51fd47f 5644 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 5645 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
5646 cfg_base_addr_index)+cfg_offset+trans_offset,
5647 sizeof(*h->transtable));
5648 if (!h->transtable)
5649 return -ENOMEM;
5650 return 0;
5651}
5652
6f039790 5653static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 5654{
5655 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 5656
5657 /* Limit commands in memory limited kdump scenario. */
5658 if (reset_devices && h->max_commands > 32)
5659 h->max_commands = 32;
5660
cba3d38b
SC		 5661 if (h->max_commands < 16) {
5662 dev_warn(&h->pdev->dev, "Controller reports "
5663 "max supported commands of %d, an obvious lie. "
5664 "Using 16. Ensure that firmware is up to date.\n",
5665 h->max_commands);
5666 h->max_commands = 16;
5667 }
5668}
5669
b93d7536
SC		 5670/* Interrogate the hardware for some limits:
5671 * max commands, max SG elements without chaining, and with chaining,
5672 * SG chain block size, etc.
5673 */
6f039790 5674static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 5675{
cba3d38b 5676 hpsa_get_max_perf_mode_cmds(h);
b93d7536
SC		 5677 h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
5678 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 5679 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
b93d7536
SC		 5680 /*
5681 * Limit in-command s/g elements to 32 save dma'able memory.
5682 * Howvever spec says if 0, use 31
5683 */
5684 h->max_cmd_sg_entries = 31;
5685 if (h->maxsgentries > 512) {
5686 h->max_cmd_sg_entries = 32;
5687 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
5688 h->maxsgentries--; /* save one for chain pointer */
5689 } else {
5690 h->maxsgentries = 31; /* default to traditional values */
5691 h->chainsize = 0;
5692 }
75167d2c
SC		 5693
5694 /* Find out what task management functions are supported and cache */
5695 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 5696 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
5697 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
5698 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5699 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 5700}
5701
76c46e49
SC		 5702static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
5703{
0fc9fd40 5704 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
76c46e49
SC		 5705 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
5706 return false;
5707 }
5708 return true;
5709}
5710
97a5e98c 5711static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 5712{
97a5e98c 5713 u32 driver_support;
f7c39101 5714
28e13446
SC		 5715#ifdef CONFIG_X86
5716 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
97a5e98c
SC		 5717 driver_support = readl(&(h->cfgtable->driver_support));
5718 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 5719#endif
28e13446
SC		 5720 driver_support |= ENABLE_UNIT_ATTN;
5721 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 5722}
5723
3d0eab67
SC		 5724/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
5725 * in a prefetch beyond physical memory.
5726 */
5727static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
5728{
5729 u32 dma_prefetch;
5730
5731 if (h->board_id != 0x3225103C)
5732 return;
5733 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
5734 dma_prefetch |= 0x8000;
5735 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
5736}
5737
76438d08
SC		 5738static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
5739{
5740 int i;
5741 u32 doorbell_value;
5742 unsigned long flags;
5743 /* wait until the clear_event_notify bit 6 is cleared by controller. */
5744 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
5745 spin_lock_irqsave(&h->lock, flags);
5746 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
5747 spin_unlock_irqrestore(&h->lock, flags);
5748 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
5749 break;
5750 /* delay and try again */
5751 msleep(20);
5752 }
5753}
5754
6f039790 5755static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 5756{
5757 int i;
6eaf46fd
SC		 5758 u32 doorbell_value;
5759 unsigned long flags;
eb6b2ae9
SC		 5760
5761 /* under certain very rare conditions, this can take awhile.
5762 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
5763 * as we enter this code.)
5764 */
5765 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 5766 spin_lock_irqsave(&h->lock, flags);
5767 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
5768 spin_unlock_irqrestore(&h->lock, flags);
382be668 5769 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 5770 break;
5771 /* delay and try again */
60d3f5b0 5772 usleep_range(10000, 20000);
eb6b2ae9 5773 }
3f4336f3
SC		 5774}
5775
6f039790 5776static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 5777{
5778 u32 trans_support;
5779
5780 trans_support = readl(&(h->cfgtable->TransportSupport));
5781 if (!(trans_support & SIMPLE_MODE))
5782 return -ENOTSUPP;
5783
5784 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 5785
3f4336f3
SC		 5786 /* Update the field, and then ring the doorbell */
5787 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 5788 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 5789 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
5790 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 5791 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 5792 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
5793 goto error;
960a30e7 5794 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 5795 return 0;
283b4a9b
SC		 5796error:
5797 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
5798 return -ENODEV;
eb6b2ae9
SC		 5799}
5800
6f039790 5801static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 5802{
eb6b2ae9 5803 int prod_index, err;
edd16368 5804
e5c880d1
SC		 5805 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
5806 if (prod_index < 0)
5807 return -ENODEV;
5808 h->product_name = products[prod_index].product_name;
5809 h->access = *(products[prod_index].access);
edd16368 5810
e5a44df8
MG		 5811 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
5812 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
5813
55c06c71 5814 err = pci_enable_device(h->pdev);
edd16368 5815 if (err) {
55c06c71 5816 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 5817 return err;
5818 }
5819
5cb460a6
SC		 5820 /* Enable bus mastering (pci_disable_device may disable this) */
5821 pci_set_master(h->pdev);
5822
f79cfec6 5823 err = pci_request_regions(h->pdev, HPSA);
edd16368 5824 if (err) {
55c06c71
SC		 5825 dev_err(&h->pdev->dev,
5826 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 5827 return err;
5828 }
6b3f4c52 5829 hpsa_interrupt_mode(h);
12d2cd47 5830 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 5831 if (err)
edd16368 5832 goto err_out_free_res;
edd16368 5833 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 5834 if (!h->vaddr) {
5835 err = -ENOMEM;
5836 goto err_out_free_res;
5837 }
fe5389c8 5838 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 5839 if (err)
edd16368 5840 goto err_out_free_res;
77c4495c
SC		 5841 err = hpsa_find_cfgtables(h);
5842 if (err)
edd16368 5843 goto err_out_free_res;
b93d7536 5844 hpsa_find_board_params(h);
edd16368 5845
76c46e49 5846 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 5847 err = -ENODEV;
5848 goto err_out_free_res;
5849 }
97a5e98c 5850 hpsa_set_driver_support_bits(h);
3d0eab67 5851 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 5852 err = hpsa_enter_simple_mode(h);
5853 if (err)
edd16368 5854 goto err_out_free_res;
edd16368
SC		 5855 return 0;
5856
5857err_out_free_res:
204892e9
SC		 5858 if (h->transtable)
5859 iounmap(h->transtable);
5860 if (h->cfgtable)
5861 iounmap(h->cfgtable);
5862 if (h->vaddr)
5863 iounmap(h->vaddr);
f0bd0b68 5864 pci_disable_device(h->pdev);
55c06c71 5865 pci_release_regions(h->pdev);
edd16368
SC		 5866 return err;
5867}
5868
6f039790 5869static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 5870{
5871 int rc;
5872
5873#define HBA_INQUIRY_BYTE_COUNT 64
5874 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
5875 if (!h->hba_inquiry_data)
5876 return;
5877 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
5878 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
5879 if (rc != 0) {
5880 kfree(h->hba_inquiry_data);
5881 h->hba_inquiry_data = NULL;
5882 }
5883}
5884
6f039790 5885static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 5886{
1df8552a 5887 int rc, i;
4c2a8c40
SC		 5888
5889 if (!reset_devices)
5890 return 0;
5891
1df8552a
SC		 5892 /* Reset the controller with a PCI power-cycle or via doorbell */
5893 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 5894
1df8552a
SC		 5895 /* -ENOTSUPP here means we cannot reset the controller
5896 * but it's already (and still) up and running in
18867659
SC		 5897 * "performant mode". Or, it might be 640x, which can't reset
5898 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a
SC		 5899 */
5900 if (rc == -ENOTSUPP)
64670ac8 5901 return rc; /* just try to do the kdump anyhow. */
1df8552a
SC		 5902 if (rc)
5903 return -ENODEV;
4c2a8c40
SC		 5904
5905 /* Now try to get the controller to respond to a no-op */
2b870cb3 5906 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 5907 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
5908 if (hpsa_noop(pdev) == 0)
5909 break;
5910 else
5911 dev_warn(&pdev->dev, "no-op failed%s\n",
5912 (i < 11 ? "; re-trying" : ""));
5913 }
5914 return 0;
5915}
5916
6f039790 5917static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 5918{
5919 h->cmd_pool_bits = kzalloc(
5920 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
5921 sizeof(unsigned long), GFP_KERNEL);
5922 h->cmd_pool = pci_alloc_consistent(h->pdev,
5923 h->nr_cmds * sizeof(*h->cmd_pool),
5924 &(h->cmd_pool_dhandle));
5925 h->errinfo_pool = pci_alloc_consistent(h->pdev,
5926 h->nr_cmds * sizeof(*h->errinfo_pool),
5927 &(h->errinfo_pool_dhandle));
5928 if ((h->cmd_pool_bits == NULL)
5929 || (h->cmd_pool == NULL)
5930 || (h->errinfo_pool == NULL)) {
5931 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
5932 return -ENOMEM;
5933 }
5934 return 0;
5935}
5936
5937static void hpsa_free_cmd_pool(struct ctlr_info *h)
5938{
5939 kfree(h->cmd_pool_bits);
5940 if (h->cmd_pool)
5941 pci_free_consistent(h->pdev,
5942 h->nr_cmds * sizeof(struct CommandList),
5943 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 5944 if (h->ioaccel2_cmd_pool)
5945 pci_free_consistent(h->pdev,
5946 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
5947 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 5948 if (h->errinfo_pool)
5949 pci_free_consistent(h->pdev,
5950 h->nr_cmds * sizeof(struct ErrorInfo),
5951 h->errinfo_pool,
5952 h->errinfo_pool_dhandle);
e1f7de0c
MG		 5953 if (h->ioaccel_cmd_pool)
5954 pci_free_consistent(h->pdev,
5955 h->nr_cmds * sizeof(struct io_accel1_cmd),
5956 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 5957}
5958
0ae01a32
SC		 5959static int hpsa_request_irq(struct ctlr_info *h,
5960 irqreturn_t (*msixhandler)(int, void *),
5961 irqreturn_t (*intxhandler)(int, void *))
5962{
254f796b 5963 int rc, i;
0ae01a32 5964
254f796b
MG		 5965 /*
5966 * initialize h->q[x] = x so that interrupt handlers know which
5967 * queue to process.
5968 */
5969 for (i = 0; i < MAX_REPLY_QUEUES; i++)
5970 h->q[i] = (u8) i;
5971
eee0f03a 5972 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 5973 /* If performant mode and MSI-X, use multiple reply queues */
eee0f03a 5974 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 5975 rc = request_irq(h->intr[i], msixhandler,
5976 0, h->devname,
5977 &h->q[i]);
5978 } else {
5979 /* Use single reply pool */
eee0f03a 5980 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 5981 rc = request_irq(h->intr[h->intr_mode],
5982 msixhandler, 0, h->devname,
5983 &h->q[h->intr_mode]);
5984 } else {
5985 rc = request_irq(h->intr[h->intr_mode],
5986 intxhandler, IRQF_SHARED, h->devname,
5987 &h->q[h->intr_mode]);
5988 }
5989 }
0ae01a32
SC		 5990 if (rc) {
5991 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
5992 h->intr[h->intr_mode], h->devname);
5993 return -ENODEV;
5994 }
5995 return 0;
5996}
5997
6f039790 5998static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 5999{
6000 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6001 HPSA_RESET_TYPE_CONTROLLER)) {
6002 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6003 return -EIO;
6004 }
6005
6006 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6007 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6008 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6009 return -1;
6010 }
6011
6012 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6013 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
6014 dev_warn(&h->pdev->dev, "Board failed to become ready "
6015 "after soft reset.\n");
6016 return -1;
6017 }
6018
6019 return 0;
6020}
6021
254f796b
MG		 6022static void free_irqs(struct ctlr_info *h)
6023{
6024 int i;
6025
6026 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6027 /* Single reply queue, only one irq to free */
6028 i = h->intr_mode;
6029 free_irq(h->intr[i], &h->q[i]);
6030 return;
6031 }
6032
eee0f03a 6033 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 6034 free_irq(h->intr[i], &h->q[i]);
6035}
6036
0097f0f4 6037static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 6038{
254f796b 6039 free_irqs(h);
64670ac8 6040#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6041 if (h->msix_vector) {
6042 if (h->pdev->msix_enabled)
6043 pci_disable_msix(h->pdev);
6044 } else if (h->msi_vector) {
6045 if (h->pdev->msi_enabled)
6046 pci_disable_msi(h->pdev);
6047 }
64670ac8 6048#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6049}
6050
6051static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6052{
6053 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6054 hpsa_free_sg_chain_blocks(h);
6055 hpsa_free_cmd_pool(h);
e1f7de0c 6056 kfree(h->ioaccel1_blockFetchTable);
64670ac8
SC		 6057 kfree(h->blockFetchTable);
6058 pci_free_consistent(h->pdev, h->reply_pool_size,
6059 h->reply_pool, h->reply_pool_dhandle);
6060 if (h->vaddr)
6061 iounmap(h->vaddr);
6062 if (h->transtable)
6063 iounmap(h->transtable);
6064 if (h->cfgtable)
6065 iounmap(h->cfgtable);
6066 pci_release_regions(h->pdev);
6067 kfree(h);
6068}
6069
a0c12413
SC		 6070/* Called when controller lockup detected. */
6071static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
6072{
6073 struct CommandList *c = NULL;
6074
6075 assert_spin_locked(&h->lock);
6076 /* Mark all outstanding commands as failed and complete them. */
6077 while (!list_empty(list)) {
6078 c = list_entry(list->next, struct CommandList, list);
6079 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 6080 finish_cmd(c);
a0c12413
SC		 6081 }
6082}
6083
6084static void controller_lockup_detected(struct ctlr_info *h)
6085{
6086 unsigned long flags;
6087
a0c12413
SC		 6088 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6089 spin_lock_irqsave(&h->lock, flags);
6090 h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6091 spin_unlock_irqrestore(&h->lock, flags);
6092 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
6093 h->lockup_detected);
6094 pci_disable_device(h->pdev);
6095 spin_lock_irqsave(&h->lock, flags);
6096 fail_all_cmds_on_list(h, &h->cmpQ);
6097 fail_all_cmds_on_list(h, &h->reqQ);
6098 spin_unlock_irqrestore(&h->lock, flags);
6099}
6100
a0c12413
SC		 6101static void detect_controller_lockup(struct ctlr_info *h)
6102{
6103 u64 now;
6104 u32 heartbeat;
6105 unsigned long flags;
6106
a0c12413
SC		 6107 now = get_jiffies_64();
6108 /* If we've received an interrupt recently, we're ok. */
6109 if (time_after64(h->last_intr_timestamp +
e85c5974 6110 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6111 return;
6112
6113 /*
6114 * If we've already checked the heartbeat recently, we're ok.
6115 * This could happen if someone sends us a signal. We
6116 * otherwise don't care about signals in this thread.
6117 */
6118 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6119 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6120 return;
6121
6122 /* If heartbeat has not changed since we last looked, we're not ok. */
6123 spin_lock_irqsave(&h->lock, flags);
6124 heartbeat = readl(&h->cfgtable->HeartBeat);
6125 spin_unlock_irqrestore(&h->lock, flags);
6126 if (h->last_heartbeat == heartbeat) {
6127 controller_lockup_detected(h);
6128 return;
6129 }
6130
6131 /* We're ok. */
6132 h->last_heartbeat = heartbeat;
6133 h->last_heartbeat_timestamp = now;
6134}
6135
76438d08
SC		 6136static int hpsa_kickoff_rescan(struct ctlr_info *h)
6137{
6138 int i;
6139 char *event_type;
6140
6141 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6142 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6143 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6144 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6145 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6146
6147 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6148 event_type = "state change";
6149 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6150 event_type = "configuration change";
6151 /* Stop sending new RAID offload reqs via the IO accelerator */
6152 scsi_block_requests(h->scsi_host);
6153 for (i = 0; i < h->ndevices; i++)
6154 h->dev[i]->offload_enabled = 0;
6155 hpsa_drain_commands(h);
6156 /* Set 'accelerator path config change' bit */
6157 dev_warn(&h->pdev->dev,
6158 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
6159 h->events, event_type);
6160 writel(h->events, &(h->cfgtable->clear_event_notify));
6161 /* Set the "clear event notify field update" bit 6 */
6162 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6163 /* Wait until ctlr clears 'clear event notify field', bit 6 */
6164 hpsa_wait_for_clear_event_notify_ack(h);
6165 scsi_unblock_requests(h->scsi_host);
6166 } else {
6167 /* Acknowledge controller notification events. */
6168 writel(h->events, &(h->cfgtable->clear_event_notify));
6169 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6170 hpsa_wait_for_clear_event_notify_ack(h);
6171#if 0
6172 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6173 hpsa_wait_for_mode_change_ack(h);
6174#endif
6175 }
6176
6177 /* Something in the device list may have changed to trigger
6178 * the event, so do a rescan.
6179 */
6180 hpsa_scan_start(h->scsi_host);
6181 /* release reference taken on scsi host in check_controller_events */
6182 scsi_host_put(h->scsi_host);
6183 return 0;
6184}
6185
6186/* Check a register on the controller to see if there are configuration
6187 * changes (added/changed/removed logical drives, etc.) which mean that
6188 * we should rescan the controller for devices. If so, add the controller
6189 * to the list of controllers needing to be rescanned, and gets a
6190 * reference to the associated scsi_host.
6191 */
6192static void hpsa_ctlr_needs_rescan(struct ctlr_info *h)
6193{
6194 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
6195 return;
6196
6197 h->events = readl(&(h->cfgtable->event_notify));
6198 if (!h->events)
6199 return;
6200
6201 /*
6202 * Take a reference on scsi host for the duration of the scan
6203 * Release in hpsa_kickoff_rescan(). No lock needed for scan_list
6204 * as only a single thread accesses this list.
6205 */
6206 scsi_host_get(h->scsi_host);
6207 hpsa_kickoff_rescan(h);
6208}
6209
8a98db73 6210static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6211{
6212 unsigned long flags;
8a98db73
SC		 6213 struct ctlr_info *h = container_of(to_delayed_work(work),
6214 struct ctlr_info, monitor_ctlr_work);
6215 detect_controller_lockup(h);
6216 if (h->lockup_detected)
6217 return;
76438d08 6218 hpsa_ctlr_needs_rescan(h);
8a98db73
SC		 6219 spin_lock_irqsave(&h->lock, flags);
6220 if (h->remove_in_progress) {
6221 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6222 return;
6223 }
8a98db73
SC		 6224 schedule_delayed_work(&h->monitor_ctlr_work,
6225 h->heartbeat_sample_interval);
6226 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6227}
6228
6f039790 6229static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6230{
4c2a8c40 6231 int dac, rc;
edd16368 6232 struct ctlr_info *h;
64670ac8
SC		 6233 int try_soft_reset = 0;
6234 unsigned long flags;
edd16368
SC		 6235
6236 if (number_of_controllers == 0)
6237 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6238
4c2a8c40 6239 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6240 if (rc) {
6241 if (rc != -ENOTSUPP)
6242 return rc;
6243 /* If the reset fails in a particular way (it has no way to do
6244 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6245 * a soft reset once we get the controller configured up to the
6246 * point that it can accept a command.
6247 */
6248 try_soft_reset = 1;
6249 rc = 0;
6250 }
6251
6252reinit_after_soft_reset:
edd16368 6253
303932fd
DB		 6254 /* Command structures must be aligned on a 32-byte boundary because
6255 * the 5 lower bits of the address are used by the hardware. and by
6256 * the driver. See comments in hpsa.h for more info.
6257 */
283b4a9b 6258#define COMMANDLIST_ALIGNMENT 128
303932fd 6259 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6260 h = kzalloc(sizeof(*h), GFP_KERNEL);
6261 if (!h)
ecd9aad4 6262 return -ENOMEM;
edd16368 6263
55c06c71 6264 h->pdev = pdev;
a9a3a273 6265 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 6266 INIT_LIST_HEAD(&h->cmpQ);
6267 INIT_LIST_HEAD(&h->reqQ);
6eaf46fd
SC		 6268 spin_lock_init(&h->lock);
6269 spin_lock_init(&h->scan_lock);
0390f0c0 6270 spin_lock_init(&h->passthru_count_lock);
55c06c71 6271 rc = hpsa_pci_init(h);
ecd9aad4 6272 if (rc != 0)
edd16368
SC		 6273 goto clean1;
6274
f79cfec6 6275 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 6276 h->ctlr = number_of_controllers;
6277 number_of_controllers++;
edd16368
SC		 6278
6279 /* configure PCI DMA stuff */
ecd9aad4
SC		 6280 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6281 if (rc == 0) {
edd16368 6282 dac = 1;
ecd9aad4
SC		 6283 } else {
6284 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6285 if (rc == 0) {
6286 dac = 0;
6287 } else {
6288 dev_err(&pdev->dev, "no suitable DMA available\n");
6289 goto clean1;
6290 }
edd16368
SC		 6291 }
6292
6293 /* make sure the board interrupts are off */
6294 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 6295
0ae01a32 6296 if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 6297 goto clean2;
303932fd
DB		 6298 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
6299 h->devname, pdev->device,
a9a3a273 6300 h->intr[h->intr_mode], dac ? "" : " not");
2e9d1b36 6301 if (hpsa_allocate_cmd_pool(h))
edd16368 6302 goto clean4;
33a2ffce
SC		 6303 if (hpsa_allocate_sg_chain_blocks(h))
6304 goto clean4;
a08a8471
SC		 6305 init_waitqueue_head(&h->scan_wait_queue);
6306 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 6307
6308 pci_set_drvdata(pdev, h);
9a41338e
SC		 6309 h->ndevices = 0;
6310 h->scsi_host = NULL;
6311 spin_lock_init(&h->devlock);
64670ac8
SC		 6312 hpsa_put_ctlr_into_performant_mode(h);
6313
6314 /* At this point, the controller is ready to take commands.
6315 * Now, if reset_devices and the hard reset didn't work, try
6316 * the soft reset and see if that works.
6317 */
6318 if (try_soft_reset) {
6319
6320 /* This is kind of gross. We may or may not get a completion
6321 * from the soft reset command, and if we do, then the value
6322 * from the fifo may or may not be valid. So, we wait 10 secs
6323 * after the reset throwing away any completions we get during
6324 * that time. Unregister the interrupt handler and register
6325 * fake ones to scoop up any residual completions.
6326 */
6327 spin_lock_irqsave(&h->lock, flags);
6328 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6329 spin_unlock_irqrestore(&h->lock, flags);
254f796b 6330 free_irqs(h);
64670ac8
SC		 6331 rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
6332 hpsa_intx_discard_completions);
6333 if (rc) {
6334 dev_warn(&h->pdev->dev, "Failed to request_irq after "
6335 "soft reset.\n");
6336 goto clean4;
6337 }
6338
6339 rc = hpsa_kdump_soft_reset(h);
6340 if (rc)
6341 /* Neither hard nor soft reset worked, we're hosed. */
6342 goto clean4;
6343
6344 dev_info(&h->pdev->dev, "Board READY.\n");
6345 dev_info(&h->pdev->dev,
6346 "Waiting for stale completions to drain.\n");
6347 h->access.set_intr_mask(h, HPSA_INTR_ON);
6348 msleep(10000);
6349 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6350
6351 rc = controller_reset_failed(h->cfgtable);
6352 if (rc)
6353 dev_info(&h->pdev->dev,
6354 "Soft reset appears to have failed.\n");
6355
6356 /* since the controller's reset, we have to go back and re-init
6357 * everything. Easiest to just forget what we've done and do it
6358 * all over again.
6359 */
6360 hpsa_undo_allocations_after_kdump_soft_reset(h);
6361 try_soft_reset = 0;
6362 if (rc)
6363 /* don't go to clean4, we already unallocated */
6364 return -ENODEV;
6365
6366 goto reinit_after_soft_reset;
6367 }
edd16368 6368
da0697bd
ST		 6369 /* Enable Accelerated IO path at driver layer */
6370 h->acciopath_status = 1;
6371
edd16368
SC		 6372 /* Turn the interrupts on so we can service requests */
6373 h->access.set_intr_mask(h, HPSA_INTR_ON);
6374
339b2b14 6375 hpsa_hba_inquiry(h);
edd16368 6376 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 6377
6378 /* Monitor the controller for firmware lockups */
6379 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
6380 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
6381 schedule_delayed_work(&h->monitor_ctlr_work,
6382 h->heartbeat_sample_interval);
88bf6d62 6383 return 0;
edd16368
SC		 6384
6385clean4:
33a2ffce 6386 hpsa_free_sg_chain_blocks(h);
2e9d1b36 6387 hpsa_free_cmd_pool(h);
254f796b 6388 free_irqs(h);
edd16368
SC		 6389clean2:
6390clean1:
edd16368 6391 kfree(h);
ecd9aad4 6392 return rc;
edd16368
SC		 6393}
6394
6395static void hpsa_flush_cache(struct ctlr_info *h)
6396{
6397 char *flush_buf;
6398 struct CommandList *c;
702890e3
SC		 6399 unsigned long flags;
6400
6401 /* Don't bother trying to flush the cache if locked up */
6402 spin_lock_irqsave(&h->lock, flags);
6403 if (unlikely(h->lockup_detected)) {
6404 spin_unlock_irqrestore(&h->lock, flags);
6405 return;
6406 }
6407 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 6408
6409 flush_buf = kzalloc(4, GFP_KERNEL);
6410 if (!flush_buf)
6411 return;
6412
6413 c = cmd_special_alloc(h);
6414 if (!c) {
6415 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
6416 goto out_of_memory;
6417 }
a2dac136
SC		 6418 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
6419 RAID_CTLR_LUNID, TYPE_CMD)) {
6420 goto out;
6421 }
edd16368
SC		 6422 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
6423 if (c->err_info->CommandStatus != 0)
a2dac136 6424out:
edd16368
SC		 6425 dev_warn(&h->pdev->dev,
6426 "error flushing cache on controller\n");
6427 cmd_special_free(h, c);
6428out_of_memory:
6429 kfree(flush_buf);
6430}
6431
6432static void hpsa_shutdown(struct pci_dev *pdev)
6433{
6434 struct ctlr_info *h;
6435
6436 h = pci_get_drvdata(pdev);
6437 /* Turn board interrupts off and send the flush cache command
6438 * sendcmd will turn off interrupt, and send the flush...
6439 * To write all data in the battery backed cache to disks
6440 */
6441 hpsa_flush_cache(h);
6442 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 6443 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 6444}
6445
6f039790 6446static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 6447{
6448 int i;
6449
6450 for (i = 0; i < h->ndevices; i++)
6451 kfree(h->dev[i]);
6452}
6453
6f039790 6454static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 6455{
6456 struct ctlr_info *h;
8a98db73 6457 unsigned long flags;
edd16368
SC		 6458
6459 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 6460 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 6461 return;
6462 }
6463 h = pci_get_drvdata(pdev);
8a98db73
SC		 6464
6465 /* Get rid of any controller monitoring work items */
6466 spin_lock_irqsave(&h->lock, flags);
6467 h->remove_in_progress = 1;
6468 cancel_delayed_work(&h->monitor_ctlr_work);
6469 spin_unlock_irqrestore(&h->lock, flags);
6470
edd16368
SC		 6471 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
6472 hpsa_shutdown(pdev);
6473 iounmap(h->vaddr);
204892e9
SC		 6474 iounmap(h->transtable);
6475 iounmap(h->cfgtable);
55e14e76 6476 hpsa_free_device_info(h);
33a2ffce 6477 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 6478 pci_free_consistent(h->pdev,
6479 h->nr_cmds * sizeof(struct CommandList),
6480 h->cmd_pool, h->cmd_pool_dhandle);
6481 pci_free_consistent(h->pdev,
6482 h->nr_cmds * sizeof(struct ErrorInfo),
6483 h->errinfo_pool, h->errinfo_pool_dhandle);
303932fd
DB		 6484 pci_free_consistent(h->pdev, h->reply_pool_size,
6485 h->reply_pool, h->reply_pool_dhandle);
edd16368 6486 kfree(h->cmd_pool_bits);
303932fd 6487 kfree(h->blockFetchTable);
e1f7de0c 6488 kfree(h->ioaccel1_blockFetchTable);
aca9012a 6489 kfree(h->ioaccel2_blockFetchTable);
339b2b14 6490 kfree(h->hba_inquiry_data);
f0bd0b68 6491 pci_disable_device(pdev);
edd16368 6492 pci_release_regions(pdev);
edd16368
SC		 6493 kfree(h);
6494}
6495
6496static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
6497 __attribute__((unused)) pm_message_t state)
6498{
6499 return -ENOSYS;
6500}
6501
6502static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
6503{
6504 return -ENOSYS;
6505}
6506
6507static struct pci_driver hpsa_pci_driver = {
f79cfec6 6508 .name = HPSA,
edd16368 6509 .probe = hpsa_init_one,
6f039790 6510 .remove = hpsa_remove_one,
edd16368
SC		 6511 .id_table = hpsa_pci_device_id, /* id_table */
6512 .shutdown = hpsa_shutdown,
6513 .suspend = hpsa_suspend,
6514 .resume = hpsa_resume,
6515};
6516
303932fd
DB		 6517/* Fill in bucket_map[], given nsgs (the max number of
6518 * scatter gather elements supported) and bucket[],
6519 * which is an array of 8 integers. The bucket[] array
6520 * contains 8 different DMA transfer sizes (in 16
6521 * byte increments) which the controller uses to fetch
6522 * commands. This function fills in bucket_map[], which
6523 * maps a given number of scatter gather elements to one of
6524 * the 8 DMA transfer sizes. The point of it is to allow the
6525 * controller to only do as much DMA as needed to fetch the
6526 * command, with the DMA transfer size encoded in the lower
6527 * bits of the command address.
6528 */
6529static void calc_bucket_map(int bucket[], int num_buckets,
e1f7de0c 6530 int nsgs, int min_blocks, int *bucket_map)
303932fd
DB		 6531{
6532 int i, j, b, size;
6533
303932fd
DB		 6534 /* Note, bucket_map must have nsgs+1 entries. */
6535 for (i = 0; i <= nsgs; i++) {
6536 /* Compute size of a command with i SG entries */
e1f7de0c 6537 size = i + min_blocks;
303932fd
DB		 6538 b = num_buckets; /* Assume the biggest bucket */
6539 /* Find the bucket that is just big enough */
e1f7de0c 6540 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 6541 if (bucket[j] >= size) {
6542 b = j;
6543 break;
6544 }
6545 }
6546 /* for a command with i SG entries, use bucket b. */
6547 bucket_map[i] = b;
6548 }
6549}
6550
e1f7de0c 6551static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 6552{
6c311b57
SC		 6553 int i;
6554 unsigned long register_value;
e1f7de0c
MG		 6555 unsigned long transMethod = CFGTBL_Trans_Performant |
6556 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 6557 CFGTBL_Trans_enable_directed_msix |
6558 (trans_support & (CFGTBL_Trans_io_accel1 |
6559 CFGTBL_Trans_io_accel2));
e1f7de0c 6560 struct access_method access = SA5_performant_access;
def342bd
SC		 6561
6562 /* This is a bit complicated. There are 8 registers on
6563 * the controller which we write to to tell it 8 different
6564 * sizes of commands which there may be. It's a way of
6565 * reducing the DMA done to fetch each command. Encoded into
6566 * each command's tag are 3 bits which communicate to the controller
6567 * which of the eight sizes that command fits within. The size of
6568 * each command depends on how many scatter gather entries there are.
6569 * Each SG entry requires 16 bytes. The eight registers are programmed
6570 * with the number of 16-byte blocks a command of that size requires.
6571 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 6572 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 6573 * blocks. Note, this only extends to the SG entries contained
6574 * within the command block, and does not extend to chained blocks
6575 * of SG elements. bft[] contains the eight values we write to
6576 * the registers. They are not evenly distributed, but have more
6577 * sizes for small commands, and fewer sizes for larger commands.
6578 */
d66ae08b 6579 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 6580#define MIN_IOACCEL2_BFT_ENTRY 5
6581#define HPSA_IOACCEL2_HEADER_SZ 4
6582 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
6583 13, 14, 15, 16, 17, 18, 19,
6584 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
6585 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
6586 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
6587 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
6588 16 * MIN_IOACCEL2_BFT_ENTRY);
6589 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 6590 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 6591 /* 5 = 1 s/g entry or 4k
6592 * 6 = 2 s/g entry or 8k
6593 * 8 = 4 s/g entry or 16k
6594 * 10 = 6 s/g entry or 24k
6595 */
303932fd 6596
303932fd
DB		 6597 /* Controller spec: zero out this buffer. */
6598 memset(h->reply_pool, 0, h->reply_pool_size);
303932fd 6599
d66ae08b
SC		 6600 bft[7] = SG_ENTRIES_IN_CMD + 4;
6601 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 6602 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 6603 for (i = 0; i < 8; i++)
6604 writel(bft[i], &h->transtable->BlockFetch[i]);
6605
6606 /* size of controller ring buffer */
6607 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 6608 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 6609 writel(0, &h->transtable->RepQCtrAddrLow32);
6610 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 6611
6612 for (i = 0; i < h->nreply_queues; i++) {
6613 writel(0, &h->transtable->RepQAddr[i].upper);
6614 writel(h->reply_pool_dhandle +
6615 (h->max_commands * sizeof(u64) * i),
6616 &h->transtable->RepQAddr[i].lower);
6617 }
6618
b9af4937 6619 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 6620 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
6621 /*
6622 * enable outbound interrupt coalescing in accelerator mode;
6623 */
6624 if (trans_support & CFGTBL_Trans_io_accel1) {
6625 access = SA5_ioaccel_mode1_access;
6626 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
6627 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 6628 } else {
6629 if (trans_support & CFGTBL_Trans_io_accel2) {
6630 access = SA5_ioaccel_mode2_access;
6631 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
6632 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
6633 }
e1f7de0c 6634 }
303932fd 6635 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 6636 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 6637 register_value = readl(&(h->cfgtable->TransportActive));
6638 if (!(register_value & CFGTBL_Trans_Performant)) {
6639 dev_warn(&h->pdev->dev, "unable to get board into"
6640 " performant mode\n");
6641 return;
6642 }
960a30e7 6643 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 6644 h->access = access;
6645 h->transMethod = transMethod;
6646
b9af4937
SC		 6647 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
6648 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 6649 return;
6650
b9af4937
SC		 6651 if (trans_support & CFGTBL_Trans_io_accel1) {
6652 /* Set up I/O accelerator mode */
6653 for (i = 0; i < h->nreply_queues; i++) {
6654 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
6655 h->reply_queue[i].current_entry =
6656 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
6657 }
6658 bft[7] = h->ioaccel_maxsg + 8;
6659 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
6660 h->ioaccel1_blockFetchTable);
e1f7de0c 6661
b9af4937
SC		 6662 /* initialize all reply queue entries to unused */
6663 memset(h->reply_pool, (u8) IOACCEL_MODE1_REPLY_UNUSED,
6664 h->reply_pool_size);
e1f7de0c 6665
b9af4937
SC		 6666 /* set all the constant fields in the accelerator command
6667 * frames once at init time to save CPU cycles later.
6668 */
6669 for (i = 0; i < h->nr_cmds; i++) {
6670 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
6671
6672 cp->function = IOACCEL1_FUNCTION_SCSIIO;
6673 cp->err_info = (u32) (h->errinfo_pool_dhandle +
6674 (i * sizeof(struct ErrorInfo)));
6675 cp->err_info_len = sizeof(struct ErrorInfo);
6676 cp->sgl_offset = IOACCEL1_SGLOFFSET;
6677 cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT;
6678 cp->timeout_sec = 0;
6679 cp->ReplyQueue = 0;
6680 cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) |
6681 DIRECT_LOOKUP_BIT;
6682 cp->Tag.upper = 0;
6683 cp->host_addr.lower =
6684 (u32) (h->ioaccel_cmd_pool_dhandle +
6685 (i * sizeof(struct io_accel1_cmd)));
6686 cp->host_addr.upper = 0;
6687 }
6688 } else if (trans_support & CFGTBL_Trans_io_accel2) {
6689 u64 cfg_offset, cfg_base_addr_index;
6690 u32 bft2_offset, cfg_base_addr;
6691 int rc;
6692
6693 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6694 &cfg_base_addr_index, &cfg_offset);
6695 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
6696 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
6697 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
6698 4, h->ioaccel2_blockFetchTable);
6699 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
6700 BUILD_BUG_ON(offsetof(struct CfgTable,
6701 io_accel_request_size_offset) != 0xb8);
6702 h->ioaccel2_bft2_regs =
6703 remap_pci_mem(pci_resource_start(h->pdev,
6704 cfg_base_addr_index) +
6705 cfg_offset + bft2_offset,
6706 ARRAY_SIZE(bft2) *
6707 sizeof(*h->ioaccel2_bft2_regs));
6708 for (i = 0; i < ARRAY_SIZE(bft2); i++)
6709 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 6710 }
b9af4937
SC		 6711 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6712 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 6713}
6714
6715static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
6716{
283b4a9b
SC		 6717 h->ioaccel_maxsg =
6718 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
6719 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
6720 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
6721
e1f7de0c
MG		 6722 /* Command structures must be aligned on a 128-byte boundary
6723 * because the 7 lower bits of the address are used by the
6724 * hardware.
6725 */
6726#define IOACCEL1_COMMANDLIST_ALIGNMENT 128
6727 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
6728 IOACCEL1_COMMANDLIST_ALIGNMENT);
6729 h->ioaccel_cmd_pool =
6730 pci_alloc_consistent(h->pdev,
6731 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
6732 &(h->ioaccel_cmd_pool_dhandle));
6733
6734 h->ioaccel1_blockFetchTable =
283b4a9b 6735 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 6736 sizeof(u32)), GFP_KERNEL);
6737
6738 if ((h->ioaccel_cmd_pool == NULL) ||
6739 (h->ioaccel1_blockFetchTable == NULL))
6740 goto clean_up;
6741
6742 memset(h->ioaccel_cmd_pool, 0,
6743 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
6744 return 0;
6745
6746clean_up:
6747 if (h->ioaccel_cmd_pool)
6748 pci_free_consistent(h->pdev,
6749 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
6750 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
6751 kfree(h->ioaccel1_blockFetchTable);
6752 return 1;
6c311b57
SC		 6753}
6754
aca9012a
SC		 6755static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
6756{
6757 /* Allocate ioaccel2 mode command blocks and block fetch table */
6758
6759 h->ioaccel_maxsg =
6760 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
6761 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
6762 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
6763
6764#define IOACCEL2_COMMANDLIST_ALIGNMENT 128
6765 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
6766 IOACCEL2_COMMANDLIST_ALIGNMENT);
6767 h->ioaccel2_cmd_pool =
6768 pci_alloc_consistent(h->pdev,
6769 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6770 &(h->ioaccel2_cmd_pool_dhandle));
6771
6772 h->ioaccel2_blockFetchTable =
6773 kmalloc(((h->ioaccel_maxsg + 1) *
6774 sizeof(u32)), GFP_KERNEL);
6775
6776 if ((h->ioaccel2_cmd_pool == NULL) ||
6777 (h->ioaccel2_blockFetchTable == NULL))
6778 goto clean_up;
6779
6780 memset(h->ioaccel2_cmd_pool, 0,
6781 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
6782 return 0;
6783
6784clean_up:
6785 if (h->ioaccel2_cmd_pool)
6786 pci_free_consistent(h->pdev,
6787 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6788 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
6789 kfree(h->ioaccel2_blockFetchTable);
6790 return 1;
6791}
6792
6f039790 6793static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 6794{
6795 u32 trans_support;
e1f7de0c
MG		 6796 unsigned long transMethod = CFGTBL_Trans_Performant |
6797 CFGTBL_Trans_use_short_tags;
254f796b 6798 int i;
6c311b57 6799
02ec19c8
SC		 6800 if (hpsa_simple_mode)
6801 return;
6802
e1f7de0c
MG		 6803 /* Check for I/O accelerator mode support */
6804 if (trans_support & CFGTBL_Trans_io_accel1) {
6805 transMethod |= CFGTBL_Trans_io_accel1 |
6806 CFGTBL_Trans_enable_directed_msix;
6807 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
6808 goto clean_up;
aca9012a
SC		 6809 } else {
6810 if (trans_support & CFGTBL_Trans_io_accel2) {
6811 transMethod |= CFGTBL_Trans_io_accel2 |
6812 CFGTBL_Trans_enable_directed_msix;
6813 if (ioaccel2_alloc_cmds_and_bft(h))
6814 goto clean_up;
6815 }
e1f7de0c
MG		 6816 }
6817
6818 /* TODO, check that this next line h->nreply_queues is correct */
6c311b57
SC		 6819 trans_support = readl(&(h->cfgtable->TransportSupport));
6820 if (!(trans_support & PERFORMANT_MODE))
6821 return;
6822
eee0f03a 6823 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 6824 hpsa_get_max_perf_mode_cmds(h);
6c311b57 6825 /* Performant mode ring buffer and supporting data structures */
254f796b 6826 h->reply_pool_size = h->max_commands * sizeof(u64) * h->nreply_queues;
6c311b57
SC		 6827 h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
6828 &(h->reply_pool_dhandle));
6829
254f796b
MG		 6830 for (i = 0; i < h->nreply_queues; i++) {
6831 h->reply_queue[i].head = &h->reply_pool[h->max_commands * i];
6832 h->reply_queue[i].size = h->max_commands;
6833 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
6834 h->reply_queue[i].current_entry = 0;
6835 }
6836
6c311b57 6837 /* Need a block fetch table for performant mode */
d66ae08b 6838 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57
SC		 6839 sizeof(u32)), GFP_KERNEL);
6840
6841 if ((h->reply_pool == NULL)
6842 || (h->blockFetchTable == NULL))
6843 goto clean_up;
6844
e1f7de0c 6845 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 6846 return;
6847
6848clean_up:
6849 if (h->reply_pool)
6850 pci_free_consistent(h->pdev, h->reply_pool_size,
6851 h->reply_pool, h->reply_pool_dhandle);
6852 kfree(h->blockFetchTable);
6853}
6854
76438d08
SC		 6855static void hpsa_drain_commands(struct ctlr_info *h)
6856{
6857 int cmds_out;
6858 unsigned long flags;
6859
6860 do { /* wait for all outstanding commands to drain out */
6861 spin_lock_irqsave(&h->lock, flags);
6862 cmds_out = h->commands_outstanding;
6863 spin_unlock_irqrestore(&h->lock, flags);
6864 if (cmds_out <= 0)
6865 break;
6866 msleep(100);
6867 } while (1);
6868}
6869
edd16368
SC		 6870/*
6871 * This is it. Register the PCI driver information for the cards we control
6872 * the OS will call our registered routines when it finds one of our cards.
6873 */
6874static int __init hpsa_init(void)
6875{
31468401 6876 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 6877}
6878
6879static void __exit hpsa_cleanup(void)
6880{
6881 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 6882}
6883
e1f7de0c
MG		 6884static void __attribute__((unused)) verify_offsets(void)
6885{
b66cc250
MM		 6886#define VERIFY_OFFSET(member, offset) \
6887 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
6888
6889 VERIFY_OFFSET(IU_type, 0);
6890 VERIFY_OFFSET(direction, 1);
6891 VERIFY_OFFSET(reply_queue, 2);
6892 /* VERIFY_OFFSET(reserved1, 3); */
6893 VERIFY_OFFSET(scsi_nexus, 4);
6894 VERIFY_OFFSET(Tag, 8);
6895 VERIFY_OFFSET(cdb, 16);
6896 VERIFY_OFFSET(cciss_lun, 32);
6897 VERIFY_OFFSET(data_len, 40);
6898 VERIFY_OFFSET(cmd_priority_task_attr, 44);
6899 VERIFY_OFFSET(sg_count, 45);
6900 /* VERIFY_OFFSET(reserved3 */
6901 VERIFY_OFFSET(err_ptr, 48);
6902 VERIFY_OFFSET(err_len, 56);
6903 /* VERIFY_OFFSET(reserved4 */
6904 VERIFY_OFFSET(sg, 64);
6905
6906#undef VERIFY_OFFSET
6907
e1f7de0c
MG		 6908#define VERIFY_OFFSET(member, offset) \
6909 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
6910
6911 VERIFY_OFFSET(dev_handle, 0x00);
6912 VERIFY_OFFSET(reserved1, 0x02);
6913 VERIFY_OFFSET(function, 0x03);
6914 VERIFY_OFFSET(reserved2, 0x04);
6915 VERIFY_OFFSET(err_info, 0x0C);
6916 VERIFY_OFFSET(reserved3, 0x10);
6917 VERIFY_OFFSET(err_info_len, 0x12);
6918 VERIFY_OFFSET(reserved4, 0x13);
6919 VERIFY_OFFSET(sgl_offset, 0x14);
6920 VERIFY_OFFSET(reserved5, 0x15);
6921 VERIFY_OFFSET(transfer_len, 0x1C);
6922 VERIFY_OFFSET(reserved6, 0x20);
6923 VERIFY_OFFSET(io_flags, 0x24);
6924 VERIFY_OFFSET(reserved7, 0x26);
6925 VERIFY_OFFSET(LUN, 0x34);
6926 VERIFY_OFFSET(control, 0x3C);
6927 VERIFY_OFFSET(CDB, 0x40);
6928 VERIFY_OFFSET(reserved8, 0x50);
6929 VERIFY_OFFSET(host_context_flags, 0x60);
6930 VERIFY_OFFSET(timeout_sec, 0x62);
6931 VERIFY_OFFSET(ReplyQueue, 0x64);
6932 VERIFY_OFFSET(reserved9, 0x65);
6933 VERIFY_OFFSET(Tag, 0x68);
6934 VERIFY_OFFSET(host_addr, 0x70);
6935 VERIFY_OFFSET(CISS_LUN, 0x78);
6936 VERIFY_OFFSET(SG, 0x78 + 8);
6937#undef VERIFY_OFFSET
6938}
6939
edd16368
SC		 6940module_init(hpsa_init);
6941module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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