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[SCSI] hpsa: add controller base data-at-rest encryption compatibility ioaccel2
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
edd16368 50#include <linux/kthread.h>
a0c12413 51#include <linux/jiffies.h>
283b4a9b 52#include <asm/div64.h>
edd16368
SC		 53#include "hpsa_cmd.h"
54#include "hpsa.h"
55
56/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
e481cce8 57#define HPSA_DRIVER_VERSION "3.4.0-1"
edd16368 58#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 59#define HPSA "hpsa"
edd16368
SC		 60
61/* How long to wait (in milliseconds) for board to go into simple mode */
62#define MAX_CONFIG_WAIT 30000
63#define MAX_IOCTL_CONFIG_WAIT 1000
64
65/*define how many times we will try a command because of bus resets */
66#define MAX_CMD_RETRIES 3
67
68/* Embedded module documentation macros - see modules.h */
69MODULE_AUTHOR("Hewlett-Packard Company");
70MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
71 HPSA_DRIVER_VERSION);
72MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
73MODULE_VERSION(HPSA_DRIVER_VERSION);
74MODULE_LICENSE("GPL");
75
76static int hpsa_allow_any;
77module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(hpsa_allow_any,
79 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 80static int hpsa_simple_mode;
81module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_simple_mode,
83 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 84
85/* define the PCI info for the cards we can control */
86static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
7c03b870 122 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 123 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 124 {0,}
125};
126
127MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
128
129/* board_id = Subsystem Device ID & Vendor ID
130 * product = Marketing Name for the board
131 * access = Address of the struct of function pointers
132 */
133static struct board_type products[] = {
edd16368
SC		 134 {0x3241103C, "Smart Array P212", &SA5_access},
135 {0x3243103C, "Smart Array P410", &SA5_access},
136 {0x3245103C, "Smart Array P410i", &SA5_access},
137 {0x3247103C, "Smart Array P411", &SA5_access},
138 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 139 {0x324A103C, "Smart Array P712m", &SA5_access},
140 {0x324B103C, "Smart Array P711m", &SA5_access},
fe0c9610
MM		 141 {0x3350103C, "Smart Array P222", &SA5_access},
142 {0x3351103C, "Smart Array P420", &SA5_access},
143 {0x3352103C, "Smart Array P421", &SA5_access},
144 {0x3353103C, "Smart Array P822", &SA5_access},
145 {0x3354103C, "Smart Array P420i", &SA5_access},
146 {0x3355103C, "Smart Array P220i", &SA5_access},
147 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 148 {0x1921103C, "Smart Array P830i", &SA5_access},
149 {0x1922103C, "Smart Array P430", &SA5_access},
150 {0x1923103C, "Smart Array P431", &SA5_access},
151 {0x1924103C, "Smart Array P830", &SA5_access},
152 {0x1926103C, "Smart Array P731m", &SA5_access},
153 {0x1928103C, "Smart Array P230i", &SA5_access},
154 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 155 {0x21BD103C, "Smart Array", &SA5_access},
156 {0x21BE103C, "Smart Array", &SA5_access},
157 {0x21BF103C, "Smart Array", &SA5_access},
158 {0x21C0103C, "Smart Array", &SA5_access},
159 {0x21C1103C, "Smart Array", &SA5_access},
160 {0x21C2103C, "Smart Array", &SA5_access},
161 {0x21C3103C, "Smart Array", &SA5_access},
162 {0x21C4103C, "Smart Array", &SA5_access},
163 {0x21C5103C, "Smart Array", &SA5_access},
164 {0x21C7103C, "Smart Array", &SA5_access},
165 {0x21C8103C, "Smart Array", &SA5_access},
166 {0x21C9103C, "Smart Array", &SA5_access},
edd16368
SC		 167 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
168};
169
170static int number_of_controllers;
171
10f66018
SC		 172static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
173static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
edd16368
SC		 174static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
175static void start_io(struct ctlr_info *h);
176
177#ifdef CONFIG_COMPAT
178static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
179#endif
180
181static void cmd_free(struct ctlr_info *h, struct CommandList *c);
182static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
183static struct CommandList *cmd_alloc(struct ctlr_info *h);
184static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
a2dac136 185static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 186 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 187 int cmd_type);
b7bb24eb 188#define VPD_PAGE (1 << 8)
edd16368 189
f281233d 190static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 191static void hpsa_scan_start(struct Scsi_Host *);
192static int hpsa_scan_finished(struct Scsi_Host *sh,
193 unsigned long elapsed_time);
667e23d4
SC		 194static int hpsa_change_queue_depth(struct scsi_device *sdev,
195 int qdepth, int reason);
edd16368
SC		 196
197static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 198static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 199static int hpsa_slave_alloc(struct scsi_device *sdev);
200static void hpsa_slave_destroy(struct scsi_device *sdev);
201
edd16368 202static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 203static int check_for_unit_attention(struct ctlr_info *h,
204 struct CommandList *c);
205static void check_ioctl_unit_attention(struct ctlr_info *h,
206 struct CommandList *c);
303932fd
DB		 207/* performant mode helper functions */
208static void calc_bucket_map(int *bucket, int num_buckets,
e1f7de0c 209 int nsgs, int min_blocks, int *bucket_map);
6f039790 210static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 211static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 212static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
213 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
214 u64 *cfg_offset);
215static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
216 unsigned long *memory_bar);
217static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
218static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
219 int wait_for_ready);
75167d2c 220static inline void finish_cmd(struct CommandList *c);
283b4a9b 221static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 222#define BOARD_NOT_READY 0
223#define BOARD_READY 1
76438d08
SC		 224static void hpsa_drain_commands(struct ctlr_info *h);
225static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 226static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
227 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
228 u8 *scsi3addr);
edd16368 229
edd16368
SC		 230static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
231{
232 unsigned long *priv = shost_priv(sdev->host);
233 return (struct ctlr_info *) *priv;
234}
235
a23513e8
SC		 236static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
237{
238 unsigned long *priv = shost_priv(sh);
239 return (struct ctlr_info *) *priv;
240}
241
edd16368
SC		 242static int check_for_unit_attention(struct ctlr_info *h,
243 struct CommandList *c)
244{
245 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
246 return 0;
247
248 switch (c->err_info->SenseInfo[12]) {
249 case STATE_CHANGED:
f79cfec6 250 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 251 "detected, command retried\n", h->ctlr);
252 break;
253 case LUN_FAILED:
f79cfec6 254 dev_warn(&h->pdev->dev, HPSA "%d: LUN failure "
edd16368
SC		 255 "detected, action required\n", h->ctlr);
256 break;
257 case REPORT_LUNS_CHANGED:
f79cfec6 258 dev_warn(&h->pdev->dev, HPSA "%d: report LUN data "
31468401 259 "changed, action required\n", h->ctlr);
edd16368 260 /*
4f4eb9f1
ST		 261 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
262 * target (array) devices.
edd16368
SC		 263 */
264 break;
265 case POWER_OR_RESET:
f79cfec6 266 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 267 "or device reset detected\n", h->ctlr);
268 break;
269 case UNIT_ATTENTION_CLEARED:
f79cfec6 270 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 271 "cleared by another initiator\n", h->ctlr);
272 break;
273 default:
f79cfec6 274 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 275 "unit attention detected\n", h->ctlr);
276 break;
277 }
278 return 1;
279}
280
852af20a
MB		 281static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
282{
283 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
284 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
285 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
286 return 0;
287 dev_warn(&h->pdev->dev, HPSA "device busy");
288 return 1;
289}
290
da0697bd
ST		 291static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
292 struct device_attribute *attr,
293 const char *buf, size_t count)
294{
295 int status, len;
296 struct ctlr_info *h;
297 struct Scsi_Host *shost = class_to_shost(dev);
298 char tmpbuf[10];
299
300 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
301 return -EACCES;
302 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
303 strncpy(tmpbuf, buf, len);
304 tmpbuf[len] = '\0';
305 if (sscanf(tmpbuf, "%d", &status) != 1)
306 return -EINVAL;
307 h = shost_to_hba(shost);
308 h->acciopath_status = !!status;
309 dev_warn(&h->pdev->dev,
310 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
311 h->acciopath_status ? "enabled" : "disabled");
312 return count;
313}
314
edd16368
SC		 315static ssize_t host_store_rescan(struct device *dev,
316 struct device_attribute *attr,
317 const char *buf, size_t count)
318{
319 struct ctlr_info *h;
320 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 321 h = shost_to_hba(shost);
31468401 322 hpsa_scan_start(h->scsi_host);
edd16368
SC		 323 return count;
324}
325
d28ce020
SC		 326static ssize_t host_show_firmware_revision(struct device *dev,
327 struct device_attribute *attr, char *buf)
328{
329 struct ctlr_info *h;
330 struct Scsi_Host *shost = class_to_shost(dev);
331 unsigned char *fwrev;
332
333 h = shost_to_hba(shost);
334 if (!h->hba_inquiry_data)
335 return 0;
336 fwrev = &h->hba_inquiry_data[32];
337 return snprintf(buf, 20, "%c%c%c%c\n",
338 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
339}
340
94a13649
SC		 341static ssize_t host_show_commands_outstanding(struct device *dev,
342 struct device_attribute *attr, char *buf)
343{
344 struct Scsi_Host *shost = class_to_shost(dev);
345 struct ctlr_info *h = shost_to_hba(shost);
346
347 return snprintf(buf, 20, "%d\n", h->commands_outstanding);
348}
349
745a7a25
SC		 350static ssize_t host_show_transport_mode(struct device *dev,
351 struct device_attribute *attr, char *buf)
352{
353 struct ctlr_info *h;
354 struct Scsi_Host *shost = class_to_shost(dev);
355
356 h = shost_to_hba(shost);
357 return snprintf(buf, 20, "%s\n",
960a30e7 358 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 359 "performant" : "simple");
360}
361
da0697bd
ST		 362static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
363 struct device_attribute *attr, char *buf)
364{
365 struct ctlr_info *h;
366 struct Scsi_Host *shost = class_to_shost(dev);
367
368 h = shost_to_hba(shost);
369 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
370 (h->acciopath_status == 1) ? "enabled" : "disabled");
371}
372
46380786 373/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 374static u32 unresettable_controller[] = {
375 0x324a103C, /* Smart Array P712m */
376 0x324b103C, /* SmartArray P711m */
377 0x3223103C, /* Smart Array P800 */
378 0x3234103C, /* Smart Array P400 */
379 0x3235103C, /* Smart Array P400i */
380 0x3211103C, /* Smart Array E200i */
381 0x3212103C, /* Smart Array E200 */
382 0x3213103C, /* Smart Array E200i */
383 0x3214103C, /* Smart Array E200i */
384 0x3215103C, /* Smart Array E200i */
385 0x3237103C, /* Smart Array E500 */
386 0x323D103C, /* Smart Array P700m */
7af0abbc 387 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 388 0x409C0E11, /* Smart Array 6400 */
389 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 390 0x40700E11, /* Smart Array 5300 */
391 0x40820E11, /* Smart Array 532 */
392 0x40830E11, /* Smart Array 5312 */
393 0x409A0E11, /* Smart Array 641 */
394 0x409B0E11, /* Smart Array 642 */
395 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 396};
397
46380786
SC		 398/* List of controllers which cannot even be soft reset */
399static u32 soft_unresettable_controller[] = {
7af0abbc 400 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 401 0x40700E11, /* Smart Array 5300 */
402 0x40820E11, /* Smart Array 532 */
403 0x40830E11, /* Smart Array 5312 */
404 0x409A0E11, /* Smart Array 641 */
405 0x409B0E11, /* Smart Array 642 */
406 0x40910E11, /* Smart Array 6i */
46380786
SC		 407 /* Exclude 640x boards. These are two pci devices in one slot
408 * which share a battery backed cache module. One controls the
409 * cache, the other accesses the cache through the one that controls
410 * it. If we reset the one controlling the cache, the other will
411 * likely not be happy. Just forbid resetting this conjoined mess.
412 * The 640x isn't really supported by hpsa anyway.
413 */
414 0x409C0E11, /* Smart Array 6400 */
415 0x409D0E11, /* Smart Array 6400 EM */
416};
417
418static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 419{
420 int i;
421
422 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 423 if (unresettable_controller[i] == board_id)
424 return 0;
425 return 1;
426}
427
428static int ctlr_is_soft_resettable(u32 board_id)
429{
430 int i;
431
432 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
433 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 434 return 0;
435 return 1;
436}
437
46380786
SC		 438static int ctlr_is_resettable(u32 board_id)
439{
440 return ctlr_is_hard_resettable(board_id) ||
441 ctlr_is_soft_resettable(board_id);
442}
443
941b1cda
SC		 444static ssize_t host_show_resettable(struct device *dev,
445 struct device_attribute *attr, char *buf)
446{
447 struct ctlr_info *h;
448 struct Scsi_Host *shost = class_to_shost(dev);
449
450 h = shost_to_hba(shost);
46380786 451 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 452}
453
edd16368
SC		 454static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
455{
456 return (scsi3addr[3] & 0xC0) == 0x40;
457}
458
459static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
d82357ea 460 "1(ADM)", "UNKNOWN"
edd16368 461};
6b80b18f
ST		 462#define HPSA_RAID_0 0
463#define HPSA_RAID_4 1
464#define HPSA_RAID_1 2 /* also used for RAID 10 */
465#define HPSA_RAID_5 3 /* also used for RAID 50 */
466#define HPSA_RAID_51 4
467#define HPSA_RAID_6 5 /* also used for RAID 60 */
468#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 469#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
470
471static ssize_t raid_level_show(struct device *dev,
472 struct device_attribute *attr, char *buf)
473{
474 ssize_t l = 0;
82a72c0a 475 unsigned char rlevel;
edd16368
SC		 476 struct ctlr_info *h;
477 struct scsi_device *sdev;
478 struct hpsa_scsi_dev_t *hdev;
479 unsigned long flags;
480
481 sdev = to_scsi_device(dev);
482 h = sdev_to_hba(sdev);
483 spin_lock_irqsave(&h->lock, flags);
484 hdev = sdev->hostdata;
485 if (!hdev) {
486 spin_unlock_irqrestore(&h->lock, flags);
487 return -ENODEV;
488 }
489
490 /* Is this even a logical drive? */
491 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
492 spin_unlock_irqrestore(&h->lock, flags);
493 l = snprintf(buf, PAGE_SIZE, "N/A\n");
494 return l;
495 }
496
497 rlevel = hdev->raid_level;
498 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 499 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 500 rlevel = RAID_UNKNOWN;
501 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
502 return l;
503}
504
505static ssize_t lunid_show(struct device *dev,
506 struct device_attribute *attr, char *buf)
507{
508 struct ctlr_info *h;
509 struct scsi_device *sdev;
510 struct hpsa_scsi_dev_t *hdev;
511 unsigned long flags;
512 unsigned char lunid[8];
513
514 sdev = to_scsi_device(dev);
515 h = sdev_to_hba(sdev);
516 spin_lock_irqsave(&h->lock, flags);
517 hdev = sdev->hostdata;
518 if (!hdev) {
519 spin_unlock_irqrestore(&h->lock, flags);
520 return -ENODEV;
521 }
522 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
523 spin_unlock_irqrestore(&h->lock, flags);
524 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
525 lunid[0], lunid[1], lunid[2], lunid[3],
526 lunid[4], lunid[5], lunid[6], lunid[7]);
527}
528
529static ssize_t unique_id_show(struct device *dev,
530 struct device_attribute *attr, char *buf)
531{
532 struct ctlr_info *h;
533 struct scsi_device *sdev;
534 struct hpsa_scsi_dev_t *hdev;
535 unsigned long flags;
536 unsigned char sn[16];
537
538 sdev = to_scsi_device(dev);
539 h = sdev_to_hba(sdev);
540 spin_lock_irqsave(&h->lock, flags);
541 hdev = sdev->hostdata;
542 if (!hdev) {
543 spin_unlock_irqrestore(&h->lock, flags);
544 return -ENODEV;
545 }
546 memcpy(sn, hdev->device_id, sizeof(sn));
547 spin_unlock_irqrestore(&h->lock, flags);
548 return snprintf(buf, 16 * 2 + 2,
549 "%02X%02X%02X%02X%02X%02X%02X%02X"
550 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
551 sn[0], sn[1], sn[2], sn[3],
552 sn[4], sn[5], sn[6], sn[7],
553 sn[8], sn[9], sn[10], sn[11],
554 sn[12], sn[13], sn[14], sn[15]);
555}
556
c1988684
ST		 557static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
558 struct device_attribute *attr, char *buf)
559{
560 struct ctlr_info *h;
561 struct scsi_device *sdev;
562 struct hpsa_scsi_dev_t *hdev;
563 unsigned long flags;
564 int offload_enabled;
565
566 sdev = to_scsi_device(dev);
567 h = sdev_to_hba(sdev);
568 spin_lock_irqsave(&h->lock, flags);
569 hdev = sdev->hostdata;
570 if (!hdev) {
571 spin_unlock_irqrestore(&h->lock, flags);
572 return -ENODEV;
573 }
574 offload_enabled = hdev->offload_enabled;
575 spin_unlock_irqrestore(&h->lock, flags);
576 return snprintf(buf, 20, "%d\n", offload_enabled);
577}
578
3f5eac3a
SC		 579static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
580static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
581static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
582static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 583static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
584 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 585static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
586 host_show_hp_ssd_smart_path_status,
587 host_store_hp_ssd_smart_path_status);
3f5eac3a
SC		 588static DEVICE_ATTR(firmware_revision, S_IRUGO,
589 host_show_firmware_revision, NULL);
590static DEVICE_ATTR(commands_outstanding, S_IRUGO,
591 host_show_commands_outstanding, NULL);
592static DEVICE_ATTR(transport_mode, S_IRUGO,
593 host_show_transport_mode, NULL);
941b1cda
SC		 594static DEVICE_ATTR(resettable, S_IRUGO,
595 host_show_resettable, NULL);
3f5eac3a
SC		 596
597static struct device_attribute *hpsa_sdev_attrs[] = {
598 &dev_attr_raid_level,
599 &dev_attr_lunid,
600 &dev_attr_unique_id,
c1988684 601 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 602 NULL,
603};
604
605static struct device_attribute *hpsa_shost_attrs[] = {
606 &dev_attr_rescan,
607 &dev_attr_firmware_revision,
608 &dev_attr_commands_outstanding,
609 &dev_attr_transport_mode,
941b1cda 610 &dev_attr_resettable,
da0697bd 611 &dev_attr_hp_ssd_smart_path_status,
3f5eac3a
SC		 612 NULL,
613};
614
615static struct scsi_host_template hpsa_driver_template = {
616 .module = THIS_MODULE,
f79cfec6
SC		 617 .name = HPSA,
618 .proc_name = HPSA,
3f5eac3a
SC		 619 .queuecommand = hpsa_scsi_queue_command,
620 .scan_start = hpsa_scan_start,
621 .scan_finished = hpsa_scan_finished,
622 .change_queue_depth = hpsa_change_queue_depth,
623 .this_id = -1,
624 .use_clustering = ENABLE_CLUSTERING,
75167d2c 625 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 626 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
627 .ioctl = hpsa_ioctl,
628 .slave_alloc = hpsa_slave_alloc,
629 .slave_destroy = hpsa_slave_destroy,
630#ifdef CONFIG_COMPAT
631 .compat_ioctl = hpsa_compat_ioctl,
632#endif
633 .sdev_attrs = hpsa_sdev_attrs,
634 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 635 .max_sectors = 8192,
54b2b50c 636 .no_write_same = 1,
3f5eac3a
SC		 637};
638
639
640/* Enqueuing and dequeuing functions for cmdlists. */
641static inline void addQ(struct list_head *list, struct CommandList *c)
642{
643 list_add_tail(&c->list, list);
644}
645
254f796b 646static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 647{
648 u32 a;
254f796b 649 struct reply_pool *rq = &h->reply_queue[q];
e16a33ad 650 unsigned long flags;
3f5eac3a 651
e1f7de0c
MG		 652 if (h->transMethod & CFGTBL_Trans_io_accel1)
653 return h->access.command_completed(h, q);
654
3f5eac3a 655 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 656 return h->access.command_completed(h, q);
3f5eac3a 657
254f796b
MG		 658 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
659 a = rq->head[rq->current_entry];
660 rq->current_entry++;
e16a33ad 661 spin_lock_irqsave(&h->lock, flags);
3f5eac3a 662 h->commands_outstanding--;
e16a33ad 663 spin_unlock_irqrestore(&h->lock, flags);
3f5eac3a
SC		 664 } else {
665 a = FIFO_EMPTY;
666 }
667 /* Check for wraparound */
254f796b
MG		 668 if (rq->current_entry == h->max_commands) {
669 rq->current_entry = 0;
670 rq->wraparound ^= 1;
3f5eac3a
SC		 671 }
672 return a;
673}
674
c349775e
ST		 675/*
676 * There are some special bits in the bus address of the
677 * command that we have to set for the controller to know
678 * how to process the command:
679 *
680 * Normal performant mode:
681 * bit 0: 1 means performant mode, 0 means simple mode.
682 * bits 1-3 = block fetch table entry
683 * bits 4-6 = command type (== 0)
684 *
685 * ioaccel1 mode:
686 * bit 0 = "performant mode" bit.
687 * bits 1-3 = block fetch table entry
688 * bits 4-6 = command type (== 110)
689 * (command type is needed because ioaccel1 mode
690 * commands are submitted through the same register as normal
691 * mode commands, so this is how the controller knows whether
692 * the command is normal mode or ioaccel1 mode.)
693 *
694 * ioaccel2 mode:
695 * bit 0 = "performant mode" bit.
696 * bits 1-4 = block fetch table entry (note extra bit)
697 * bits 4-6 = not needed, because ioaccel2 mode has
698 * a separate special register for submitting commands.
699 */
700
3f5eac3a
SC		 701/* set_performant_mode: Modify the tag for cciss performant
702 * set bit 0 for pull model, bits 3-1 for block fetch
703 * register number
704 */
705static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
706{
254f796b 707 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 708 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 709 if (likely(h->msix_vector > 0))
254f796b 710 c->Header.ReplyQueue =
804a5cb5 711 raw_smp_processor_id() % h->nreply_queues;
254f796b 712 }
3f5eac3a
SC		 713}
714
c349775e
ST		 715static void set_ioaccel1_performant_mode(struct ctlr_info *h,
716 struct CommandList *c)
717{
718 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
719
720 /* Tell the controller to post the reply to the queue for this
721 * processor. This seems to give the best I/O throughput.
722 */
723 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
724 /* Set the bits in the address sent down to include:
725 * - performant mode bit (bit 0)
726 * - pull count (bits 1-3)
727 * - command type (bits 4-6)
728 */
729 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
730 IOACCEL1_BUSADDR_CMDTYPE;
731}
732
733static void set_ioaccel2_performant_mode(struct ctlr_info *h,
734 struct CommandList *c)
735{
736 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
737
738 /* Tell the controller to post the reply to the queue for this
739 * processor. This seems to give the best I/O throughput.
740 */
741 cp->reply_queue = smp_processor_id() % h->nreply_queues;
742 /* Set the bits in the address sent down to include:
743 * - performant mode bit not used in ioaccel mode 2
744 * - pull count (bits 0-3)
745 * - command type isn't needed for ioaccel2
746 */
747 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
748}
749
e85c5974
SC		 750static int is_firmware_flash_cmd(u8 *cdb)
751{
752 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
753}
754
755/*
756 * During firmware flash, the heartbeat register may not update as frequently
757 * as it should. So we dial down lockup detection during firmware flash. and
758 * dial it back up when firmware flash completes.
759 */
760#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
761#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
762static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
763 struct CommandList *c)
764{
765 if (!is_firmware_flash_cmd(c->Request.CDB))
766 return;
767 atomic_inc(&h->firmware_flash_in_progress);
768 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
769}
770
771static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
772 struct CommandList *c)
773{
774 if (is_firmware_flash_cmd(c->Request.CDB) &&
775 atomic_dec_and_test(&h->firmware_flash_in_progress))
776 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
777}
778
3f5eac3a
SC		 779static void enqueue_cmd_and_start_io(struct ctlr_info *h,
780 struct CommandList *c)
781{
782 unsigned long flags;
783
c349775e
ST		 784 switch (c->cmd_type) {
785 case CMD_IOACCEL1:
786 set_ioaccel1_performant_mode(h, c);
787 break;
788 case CMD_IOACCEL2:
789 set_ioaccel2_performant_mode(h, c);
790 break;
791 default:
792 set_performant_mode(h, c);
793 }
e85c5974 794 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 795 spin_lock_irqsave(&h->lock, flags);
796 addQ(&h->reqQ, c);
797 h->Qdepth++;
3f5eac3a 798 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 799 start_io(h);
3f5eac3a
SC		 800}
801
802static inline void removeQ(struct CommandList *c)
803{
804 if (WARN_ON(list_empty(&c->list)))
805 return;
806 list_del_init(&c->list);
807}
808
809static inline int is_hba_lunid(unsigned char scsi3addr[])
810{
811 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
812}
813
814static inline int is_scsi_rev_5(struct ctlr_info *h)
815{
816 if (!h->hba_inquiry_data)
817 return 0;
818 if ((h->hba_inquiry_data[2] & 0x07) == 5)
819 return 1;
820 return 0;
821}
822
edd16368
SC		 823static int hpsa_find_target_lun(struct ctlr_info *h,
824 unsigned char scsi3addr[], int bus, int *target, int *lun)
825{
826 /* finds an unused bus, target, lun for a new physical device
827 * assumes h->devlock is held
828 */
829 int i, found = 0;
cfe5badc 830 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 831
263d9401 832 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 833
834 for (i = 0; i < h->ndevices; i++) {
835 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 836 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 837 }
838
263d9401
AM		 839 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
840 if (i < HPSA_MAX_DEVICES) {
841 /* *bus = 1; */
842 *target = i;
843 *lun = 0;
844 found = 1;
edd16368
SC		 845 }
846 return !found;
847}
848
849/* Add an entry into h->dev[] array. */
850static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
851 struct hpsa_scsi_dev_t *device,
852 struct hpsa_scsi_dev_t *added[], int *nadded)
853{
854 /* assumes h->devlock is held */
855 int n = h->ndevices;
856 int i;
857 unsigned char addr1[8], addr2[8];
858 struct hpsa_scsi_dev_t *sd;
859
cfe5badc 860 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 861 dev_err(&h->pdev->dev, "too many devices, some will be "
862 "inaccessible.\n");
863 return -1;
864 }
865
866 /* physical devices do not have lun or target assigned until now. */
867 if (device->lun != -1)
868 /* Logical device, lun is already assigned. */
869 goto lun_assigned;
870
871 /* If this device a non-zero lun of a multi-lun device
872 * byte 4 of the 8-byte LUN addr will contain the logical
873 * unit no, zero otherise.
874 */
875 if (device->scsi3addr[4] == 0) {
876 /* This is not a non-zero lun of a multi-lun device */
877 if (hpsa_find_target_lun(h, device->scsi3addr,
878 device->bus, &device->target, &device->lun) != 0)
879 return -1;
880 goto lun_assigned;
881 }
882
883 /* This is a non-zero lun of a multi-lun device.
884 * Search through our list and find the device which
885 * has the same 8 byte LUN address, excepting byte 4.
886 * Assign the same bus and target for this new LUN.
887 * Use the logical unit number from the firmware.
888 */
889 memcpy(addr1, device->scsi3addr, 8);
890 addr1[4] = 0;
891 for (i = 0; i < n; i++) {
892 sd = h->dev[i];
893 memcpy(addr2, sd->scsi3addr, 8);
894 addr2[4] = 0;
895 /* differ only in byte 4? */
896 if (memcmp(addr1, addr2, 8) == 0) {
897 device->bus = sd->bus;
898 device->target = sd->target;
899 device->lun = device->scsi3addr[4];
900 break;
901 }
902 }
903 if (device->lun == -1) {
904 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
905 " suspect firmware bug or unsupported hardware "
906 "configuration.\n");
907 return -1;
908 }
909
910lun_assigned:
911
912 h->dev[n] = device;
913 h->ndevices++;
914 added[*nadded] = device;
915 (*nadded)++;
916
917 /* initially, (before registering with scsi layer) we don't
918 * know our hostno and we don't want to print anything first
919 * time anyway (the scsi layer's inquiries will show that info)
920 */
921 /* if (hostno != -1) */
922 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
923 scsi_device_type(device->devtype), hostno,
924 device->bus, device->target, device->lun);
925 return 0;
926}
927
bd9244f7
ST		 928/* Update an entry in h->dev[] array. */
929static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
930 int entry, struct hpsa_scsi_dev_t *new_entry)
931{
932 /* assumes h->devlock is held */
933 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
934
935 /* Raid level changed. */
936 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 937
938 /* Raid offload parameters changed. */
939 h->dev[entry]->offload_config = new_entry->offload_config;
940 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
9fb0de2d
SC		 941 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
942 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
943 h->dev[entry]->raid_map = new_entry->raid_map;
250fb125 944
bd9244f7
ST		 945 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
946 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
947 new_entry->target, new_entry->lun);
948}
949
2a8ccf31
SC		 950/* Replace an entry from h->dev[] array. */
951static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
952 int entry, struct hpsa_scsi_dev_t *new_entry,
953 struct hpsa_scsi_dev_t *added[], int *nadded,
954 struct hpsa_scsi_dev_t *removed[], int *nremoved)
955{
956 /* assumes h->devlock is held */
cfe5badc 957 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 958 removed[*nremoved] = h->dev[entry];
959 (*nremoved)++;
01350d05
SC		 960
961 /*
962 * New physical devices won't have target/lun assigned yet
963 * so we need to preserve the values in the slot we are replacing.
964 */
965 if (new_entry->target == -1) {
966 new_entry->target = h->dev[entry]->target;
967 new_entry->lun = h->dev[entry]->lun;
968 }
969
2a8ccf31
SC		 970 h->dev[entry] = new_entry;
971 added[*nadded] = new_entry;
972 (*nadded)++;
973 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
974 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
975 new_entry->target, new_entry->lun);
976}
977
edd16368
SC		 978/* Remove an entry from h->dev[] array. */
979static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
980 struct hpsa_scsi_dev_t *removed[], int *nremoved)
981{
982 /* assumes h->devlock is held */
983 int i;
984 struct hpsa_scsi_dev_t *sd;
985
cfe5badc 986 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 987
988 sd = h->dev[entry];
989 removed[*nremoved] = h->dev[entry];
990 (*nremoved)++;
991
992 for (i = entry; i < h->ndevices-1; i++)
993 h->dev[i] = h->dev[i+1];
994 h->ndevices--;
995 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
996 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
997 sd->lun);
998}
999
1000#define SCSI3ADDR_EQ(a, b) ( \
1001 (a)[7] == (b)[7] && \
1002 (a)[6] == (b)[6] && \
1003 (a)[5] == (b)[5] && \
1004 (a)[4] == (b)[4] && \
1005 (a)[3] == (b)[3] && \
1006 (a)[2] == (b)[2] && \
1007 (a)[1] == (b)[1] && \
1008 (a)[0] == (b)[0])
1009
1010static void fixup_botched_add(struct ctlr_info *h,
1011 struct hpsa_scsi_dev_t *added)
1012{
1013 /* called when scsi_add_device fails in order to re-adjust
1014 * h->dev[] to match the mid layer's view.
1015 */
1016 unsigned long flags;
1017 int i, j;
1018
1019 spin_lock_irqsave(&h->lock, flags);
1020 for (i = 0; i < h->ndevices; i++) {
1021 if (h->dev[i] == added) {
1022 for (j = i; j < h->ndevices-1; j++)
1023 h->dev[j] = h->dev[j+1];
1024 h->ndevices--;
1025 break;
1026 }
1027 }
1028 spin_unlock_irqrestore(&h->lock, flags);
1029 kfree(added);
1030}
1031
1032static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1033 struct hpsa_scsi_dev_t *dev2)
1034{
edd16368
SC		 1035 /* we compare everything except lun and target as these
1036 * are not yet assigned. Compare parts likely
1037 * to differ first
1038 */
1039 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1040 sizeof(dev1->scsi3addr)) != 0)
1041 return 0;
1042 if (memcmp(dev1->device_id, dev2->device_id,
1043 sizeof(dev1->device_id)) != 0)
1044 return 0;
1045 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1046 return 0;
1047 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1048 return 0;
edd16368
SC		 1049 if (dev1->devtype != dev2->devtype)
1050 return 0;
edd16368
SC		 1051 if (dev1->bus != dev2->bus)
1052 return 0;
1053 return 1;
1054}
1055
bd9244f7
ST		 1056static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1057 struct hpsa_scsi_dev_t *dev2)
1058{
1059 /* Device attributes that can change, but don't mean
1060 * that the device is a different device, nor that the OS
1061 * needs to be told anything about the change.
1062 */
1063 if (dev1->raid_level != dev2->raid_level)
1064 return 1;
250fb125
SC		 1065 if (dev1->offload_config != dev2->offload_config)
1066 return 1;
1067 if (dev1->offload_enabled != dev2->offload_enabled)
1068 return 1;
bd9244f7
ST		 1069 return 0;
1070}
1071
edd16368
SC		 1072/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1073 * and return needle location in *index. If scsi3addr matches, but not
1074 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1075 * location in *index.
1076 * In the case of a minor device attribute change, such as RAID level, just
1077 * return DEVICE_UPDATED, along with the updated device's location in index.
1078 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1079 */
1080static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1081 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1082 int *index)
1083{
1084 int i;
1085#define DEVICE_NOT_FOUND 0
1086#define DEVICE_CHANGED 1
1087#define DEVICE_SAME 2
bd9244f7 1088#define DEVICE_UPDATED 3
edd16368 1089 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1090 if (haystack[i] == NULL) /* previously removed. */
1091 continue;
edd16368
SC		 1092 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1093 *index = i;
bd9244f7
ST		 1094 if (device_is_the_same(needle, haystack[i])) {
1095 if (device_updated(needle, haystack[i]))
1096 return DEVICE_UPDATED;
edd16368 1097 return DEVICE_SAME;
bd9244f7 1098 } else {
edd16368 1099 return DEVICE_CHANGED;
bd9244f7 1100 }
edd16368
SC		 1101 }
1102 }
1103 *index = -1;
1104 return DEVICE_NOT_FOUND;
1105}
1106
4967bd3e 1107static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1108 struct hpsa_scsi_dev_t *sd[], int nsds)
1109{
1110 /* sd contains scsi3 addresses and devtypes, and inquiry
1111 * data. This function takes what's in sd to be the current
1112 * reality and updates h->dev[] to reflect that reality.
1113 */
1114 int i, entry, device_change, changes = 0;
1115 struct hpsa_scsi_dev_t *csd;
1116 unsigned long flags;
1117 struct hpsa_scsi_dev_t **added, **removed;
1118 int nadded, nremoved;
1119 struct Scsi_Host *sh = NULL;
1120
cfe5badc
ST		 1121 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1122 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1123
1124 if (!added || !removed) {
1125 dev_warn(&h->pdev->dev, "out of memory in "
1126 "adjust_hpsa_scsi_table\n");
1127 goto free_and_out;
1128 }
1129
1130 spin_lock_irqsave(&h->devlock, flags);
1131
1132 /* find any devices in h->dev[] that are not in
1133 * sd[] and remove them from h->dev[], and for any
1134 * devices which have changed, remove the old device
1135 * info and add the new device info.
bd9244f7
ST		 1136 * If minor device attributes change, just update
1137 * the existing device structure.
edd16368
SC		 1138 */
1139 i = 0;
1140 nremoved = 0;
1141 nadded = 0;
1142 while (i < h->ndevices) {
1143 csd = h->dev[i];
1144 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1145 if (device_change == DEVICE_NOT_FOUND) {
1146 changes++;
1147 hpsa_scsi_remove_entry(h, hostno, i,
1148 removed, &nremoved);
1149 continue; /* remove ^^^, hence i not incremented */
1150 } else if (device_change == DEVICE_CHANGED) {
1151 changes++;
2a8ccf31
SC		 1152 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1153 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1154 /* Set it to NULL to prevent it from being freed
1155 * at the bottom of hpsa_update_scsi_devices()
1156 */
1157 sd[entry] = NULL;
bd9244f7
ST		 1158 } else if (device_change == DEVICE_UPDATED) {
1159 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1160 }
1161 i++;
1162 }
1163
1164 /* Now, make sure every device listed in sd[] is also
1165 * listed in h->dev[], adding them if they aren't found
1166 */
1167
1168 for (i = 0; i < nsds; i++) {
1169 if (!sd[i]) /* if already added above. */
1170 continue;
1171 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1172 h->ndevices, &entry);
1173 if (device_change == DEVICE_NOT_FOUND) {
1174 changes++;
1175 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1176 added, &nadded) != 0)
1177 break;
1178 sd[i] = NULL; /* prevent from being freed later. */
1179 } else if (device_change == DEVICE_CHANGED) {
1180 /* should never happen... */
1181 changes++;
1182 dev_warn(&h->pdev->dev,
1183 "device unexpectedly changed.\n");
1184 /* but if it does happen, we just ignore that device */
1185 }
1186 }
1187 spin_unlock_irqrestore(&h->devlock, flags);
1188
1189 /* Don't notify scsi mid layer of any changes the first time through
1190 * (or if there are no changes) scsi_scan_host will do it later the
1191 * first time through.
1192 */
1193 if (hostno == -1 || !changes)
1194 goto free_and_out;
1195
1196 sh = h->scsi_host;
1197 /* Notify scsi mid layer of any removed devices */
1198 for (i = 0; i < nremoved; i++) {
1199 struct scsi_device *sdev =
1200 scsi_device_lookup(sh, removed[i]->bus,
1201 removed[i]->target, removed[i]->lun);
1202 if (sdev != NULL) {
1203 scsi_remove_device(sdev);
1204 scsi_device_put(sdev);
1205 } else {
1206 /* We don't expect to get here.
1207 * future cmds to this device will get selection
1208 * timeout as if the device was gone.
1209 */
1210 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1211 " for removal.", hostno, removed[i]->bus,
1212 removed[i]->target, removed[i]->lun);
1213 }
1214 kfree(removed[i]);
1215 removed[i] = NULL;
1216 }
1217
1218 /* Notify scsi mid layer of any added devices */
1219 for (i = 0; i < nadded; i++) {
1220 if (scsi_add_device(sh, added[i]->bus,
1221 added[i]->target, added[i]->lun) == 0)
1222 continue;
1223 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1224 "device not added.\n", hostno, added[i]->bus,
1225 added[i]->target, added[i]->lun);
1226 /* now we have to remove it from h->dev,
1227 * since it didn't get added to scsi mid layer
1228 */
1229 fixup_botched_add(h, added[i]);
1230 }
1231
1232free_and_out:
1233 kfree(added);
1234 kfree(removed);
edd16368
SC		 1235}
1236
1237/*
9e03aa2f 1238 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1239 * Assume's h->devlock is held.
1240 */
1241static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1242 int bus, int target, int lun)
1243{
1244 int i;
1245 struct hpsa_scsi_dev_t *sd;
1246
1247 for (i = 0; i < h->ndevices; i++) {
1248 sd = h->dev[i];
1249 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1250 return sd;
1251 }
1252 return NULL;
1253}
1254
1255/* link sdev->hostdata to our per-device structure. */
1256static int hpsa_slave_alloc(struct scsi_device *sdev)
1257{
1258 struct hpsa_scsi_dev_t *sd;
1259 unsigned long flags;
1260 struct ctlr_info *h;
1261
1262 h = sdev_to_hba(sdev);
1263 spin_lock_irqsave(&h->devlock, flags);
1264 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1265 sdev_id(sdev), sdev->lun);
1266 if (sd != NULL)
1267 sdev->hostdata = sd;
1268 spin_unlock_irqrestore(&h->devlock, flags);
1269 return 0;
1270}
1271
1272static void hpsa_slave_destroy(struct scsi_device *sdev)
1273{
bcc44255 1274 /* nothing to do. */
edd16368
SC		 1275}
1276
33a2ffce
SC		 1277static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1278{
1279 int i;
1280
1281 if (!h->cmd_sg_list)
1282 return;
1283 for (i = 0; i < h->nr_cmds; i++) {
1284 kfree(h->cmd_sg_list[i]);
1285 h->cmd_sg_list[i] = NULL;
1286 }
1287 kfree(h->cmd_sg_list);
1288 h->cmd_sg_list = NULL;
1289}
1290
1291static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1292{
1293 int i;
1294
1295 if (h->chainsize <= 0)
1296 return 0;
1297
1298 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1299 GFP_KERNEL);
1300 if (!h->cmd_sg_list)
1301 return -ENOMEM;
1302 for (i = 0; i < h->nr_cmds; i++) {
1303 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1304 h->chainsize, GFP_KERNEL);
1305 if (!h->cmd_sg_list[i])
1306 goto clean;
1307 }
1308 return 0;
1309
1310clean:
1311 hpsa_free_sg_chain_blocks(h);
1312 return -ENOMEM;
1313}
1314
e2bea6df 1315static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1316 struct CommandList *c)
1317{
1318 struct SGDescriptor *chain_sg, *chain_block;
1319 u64 temp64;
1320
1321 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1322 chain_block = h->cmd_sg_list[c->cmdindex];
1323 chain_sg->Ext = HPSA_SG_CHAIN;
1324 chain_sg->Len = sizeof(*chain_sg) *
1325 (c->Header.SGTotal - h->max_cmd_sg_entries);
1326 temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
1327 PCI_DMA_TODEVICE);
e2bea6df
SC		 1328 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1329 /* prevent subsequent unmapping */
1330 chain_sg->Addr.lower = 0;
1331 chain_sg->Addr.upper = 0;
1332 return -1;
1333 }
33a2ffce
SC		 1334 chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
1335 chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
e2bea6df 1336 return 0;
33a2ffce
SC		 1337}
1338
1339static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1340 struct CommandList *c)
1341{
1342 struct SGDescriptor *chain_sg;
1343 union u64bit temp64;
1344
1345 if (c->Header.SGTotal <= h->max_cmd_sg_entries)
1346 return;
1347
1348 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1349 temp64.val32.lower = chain_sg->Addr.lower;
1350 temp64.val32.upper = chain_sg->Addr.upper;
1351 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
1352}
1353
a09c1441
ST		 1354
1355/* Decode the various types of errors on ioaccel2 path.
1356 * Return 1 for any error that should generate a RAID path retry.
1357 * Return 0 for errors that don't require a RAID path retry.
1358 */
1359static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1360 struct CommandList *c,
1361 struct scsi_cmnd *cmd,
1362 struct io_accel2_cmd *c2)
1363{
1364 int data_len;
a09c1441 1365 int retry = 0;
c349775e
ST		 1366
1367 switch (c2->error_data.serv_response) {
1368 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1369 switch (c2->error_data.status) {
1370 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1371 break;
1372 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1373 dev_warn(&h->pdev->dev,
1374 "%s: task complete with check condition.\n",
1375 "HP SSD Smart Path");
1376 if (c2->error_data.data_present !=
1377 IOACCEL2_SENSE_DATA_PRESENT)
1378 break;
1379 /* copy the sense data */
1380 data_len = c2->error_data.sense_data_len;
1381 if (data_len > SCSI_SENSE_BUFFERSIZE)
1382 data_len = SCSI_SENSE_BUFFERSIZE;
1383 if (data_len > sizeof(c2->error_data.sense_data_buff))
1384 data_len =
1385 sizeof(c2->error_data.sense_data_buff);
1386 memcpy(cmd->sense_buffer,
1387 c2->error_data.sense_data_buff, data_len);
1388 cmd->result |= SAM_STAT_CHECK_CONDITION;
a09c1441 1389 retry = 1;
c349775e
ST		 1390 break;
1391 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1392 dev_warn(&h->pdev->dev,
1393 "%s: task complete with BUSY status.\n",
1394 "HP SSD Smart Path");
a09c1441 1395 retry = 1;
c349775e
ST		 1396 break;
1397 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1398 dev_warn(&h->pdev->dev,
1399 "%s: task complete with reservation conflict.\n",
1400 "HP SSD Smart Path");
a09c1441 1401 retry = 1;
c349775e
ST		 1402 break;
1403 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1404 /* Make scsi midlayer do unlimited retries */
1405 cmd->result = DID_IMM_RETRY << 16;
1406 break;
1407 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1408 dev_warn(&h->pdev->dev,
1409 "%s: task complete with aborted status.\n",
1410 "HP SSD Smart Path");
a09c1441 1411 retry = 1;
c349775e
ST		 1412 break;
1413 default:
1414 dev_warn(&h->pdev->dev,
1415 "%s: task complete with unrecognized status: 0x%02x\n",
1416 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1417 retry = 1;
c349775e
ST		 1418 break;
1419 }
1420 break;
1421 case IOACCEL2_SERV_RESPONSE_FAILURE:
1422 /* don't expect to get here. */
1423 dev_warn(&h->pdev->dev,
1424 "unexpected delivery or target failure, status = 0x%02x\n",
1425 c2->error_data.status);
a09c1441 1426 retry = 1;
c349775e
ST		 1427 break;
1428 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1429 break;
1430 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1431 break;
1432 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1433 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1434 retry = 1;
c349775e
ST		 1435 break;
1436 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1437 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1438 break;
1439 default:
1440 dev_warn(&h->pdev->dev,
1441 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1442 "HP SSD Smart Path",
1443 c2->error_data.serv_response);
1444 retry = 1;
c349775e
ST		 1445 break;
1446 }
a09c1441
ST		 1447
1448 return retry; /* retry on raid path? */
c349775e
ST		 1449}
1450
1451static void process_ioaccel2_completion(struct ctlr_info *h,
1452 struct CommandList *c, struct scsi_cmnd *cmd,
1453 struct hpsa_scsi_dev_t *dev)
1454{
1455 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
a09c1441 1456 int raid_retry = 0;
c349775e
ST		 1457
1458 /* check for good status */
1459 if (likely(c2->error_data.serv_response == 0 &&
1460 c2->error_data.status == 0)) {
1461 cmd_free(h, c);
1462 cmd->scsi_done(cmd);
1463 return;
1464 }
1465
1466 /* Any RAID offload error results in retry which will use
1467 * the normal I/O path so the controller can handle whatever's
1468 * wrong.
1469 */
1470 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1471 c2->error_data.serv_response ==
1472 IOACCEL2_SERV_RESPONSE_FAILURE) {
a09c1441
ST		 1473 if (c2->error_data.status ==
1474 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1475 dev_warn(&h->pdev->dev,
1476 "%s: Path is unavailable, retrying on standard path.\n",
1477 "HP SSD Smart Path");
1478 else
c349775e 1479 dev_warn(&h->pdev->dev,
a09c1441 1480 "%s: Error 0x%02x, retrying on standard path.\n",
c349775e 1481 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1482
c349775e 1483 dev->offload_enabled = 0;
e863d68e 1484 h->drv_req_rescan = 1; /* schedule controller for a rescan */
c349775e
ST		 1485 cmd->result = DID_SOFT_ERROR << 16;
1486 cmd_free(h, c);
1487 cmd->scsi_done(cmd);
1488 return;
1489 }
a09c1441
ST		 1490 raid_retry = handle_ioaccel_mode2_error(h, c, cmd, c2);
1491 /* If error found, disable Smart Path, schedule a rescan,
1492 * and force a retry on the standard path.
1493 */
1494 if (raid_retry) {
1495 dev_warn(&h->pdev->dev, "%s: Retrying on standard path.\n",
1496 "HP SSD Smart Path");
1497 dev->offload_enabled = 0; /* Disable Smart Path */
1498 h->drv_req_rescan = 1; /* schedule controller rescan */
1499 cmd->result = DID_SOFT_ERROR << 16;
1500 }
c349775e
ST		 1501 cmd_free(h, c);
1502 cmd->scsi_done(cmd);
1503}
1504
1fb011fb 1505static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1506{
1507 struct scsi_cmnd *cmd;
1508 struct ctlr_info *h;
1509 struct ErrorInfo *ei;
283b4a9b 1510 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1511
1512 unsigned char sense_key;
1513 unsigned char asc; /* additional sense code */
1514 unsigned char ascq; /* additional sense code qualifier */
db111e18 1515 unsigned long sense_data_size;
edd16368
SC		 1516
1517 ei = cp->err_info;
1518 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1519 h = cp->h;
283b4a9b 1520 dev = cmd->device->hostdata;
edd16368
SC		 1521
1522 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c
MG		 1523 if ((cp->cmd_type == CMD_SCSI) &&
1524 (cp->Header.SGTotal > h->max_cmd_sg_entries))
33a2ffce 1525 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1526
1527 cmd->result = (DID_OK << 16); /* host byte */
1528 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1529
1530 if (cp->cmd_type == CMD_IOACCEL2)
1531 return process_ioaccel2_completion(h, cp, cmd, dev);
1532
5512672f 1533 cmd->result |= ei->ScsiStatus;
edd16368
SC		 1534
1535 /* copy the sense data whether we need to or not. */
db111e18
SC		 1536 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1537 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1538 else
1539 sense_data_size = sizeof(ei->SenseInfo);
1540 if (ei->SenseLen < sense_data_size)
1541 sense_data_size = ei->SenseLen;
1542
1543 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368
SC		 1544 scsi_set_resid(cmd, ei->ResidualCnt);
1545
1546 if (ei->CommandStatus == 0) {
edd16368 1547 cmd_free(h, cp);
2cc5bfaf 1548 cmd->scsi_done(cmd);
edd16368
SC		 1549 return;
1550 }
1551
e1f7de0c
MG		 1552 /* For I/O accelerator commands, copy over some fields to the normal
1553 * CISS header used below for error handling.
1554 */
1555 if (cp->cmd_type == CMD_IOACCEL1) {
1556 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
1557 cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd);
1558 cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK;
1559 cp->Header.Tag.lower = c->Tag.lower;
1560 cp->Header.Tag.upper = c->Tag.upper;
1561 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1562 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1563
1564 /* Any RAID offload error results in retry which will use
1565 * the normal I/O path so the controller can handle whatever's
1566 * wrong.
1567 */
1568 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1569 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1570 dev->offload_enabled = 0;
1571 cmd->result = DID_SOFT_ERROR << 16;
1572 cmd_free(h, cp);
1573 cmd->scsi_done(cmd);
1574 return;
1575 }
e1f7de0c
MG		 1576 }
1577
edd16368
SC		 1578 /* an error has occurred */
1579 switch (ei->CommandStatus) {
1580
1581 case CMD_TARGET_STATUS:
1582 if (ei->ScsiStatus) {
1583 /* Get sense key */
1584 sense_key = 0xf & ei->SenseInfo[2];
1585 /* Get additional sense code */
1586 asc = ei->SenseInfo[12];
1587 /* Get addition sense code qualifier */
1588 ascq = ei->SenseInfo[13];
1589 }
1590
1591 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
3ce438df 1592 if (check_for_unit_attention(h, cp))
edd16368 1593 break;
edd16368
SC		 1594 if (sense_key == ILLEGAL_REQUEST) {
1595 /*
1596 * SCSI REPORT_LUNS is commonly unsupported on
1597 * Smart Array. Suppress noisy complaint.
1598 */
1599 if (cp->Request.CDB[0] == REPORT_LUNS)
1600 break;
1601
1602 /* If ASC/ASCQ indicate Logical Unit
1603 * Not Supported condition,
1604 */
1605 if ((asc == 0x25) && (ascq == 0x0)) {
1606 dev_warn(&h->pdev->dev, "cp %p "
1607 "has check condition\n", cp);
1608 break;
1609 }
1610 }
1611
1612 if (sense_key == NOT_READY) {
1613 /* If Sense is Not Ready, Logical Unit
1614 * Not ready, Manual Intervention
1615 * required
1616 */
1617 if ((asc == 0x04) && (ascq == 0x03)) {
edd16368
SC		 1618 dev_warn(&h->pdev->dev, "cp %p "
1619 "has check condition: unit "
1620 "not ready, manual "
1621 "intervention required\n", cp);
1622 break;
1623 }
1624 }
1d3b3609
MG		 1625 if (sense_key == ABORTED_COMMAND) {
1626 /* Aborted command is retryable */
1627 dev_warn(&h->pdev->dev, "cp %p "
1628 "has check condition: aborted command: "
1629 "ASC: 0x%x, ASCQ: 0x%x\n",
1630 cp, asc, ascq);
2e311fba 1631 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1632 break;
1633 }
edd16368 1634 /* Must be some other type of check condition */
21b8e4ef 1635 dev_dbg(&h->pdev->dev, "cp %p has check condition: "
edd16368
SC		 1636 "unknown type: "
1637 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1638 "Returning result: 0x%x, "
1639 "cmd=[%02x %02x %02x %02x %02x "
807be732 1640 "%02x %02x %02x %02x %02x %02x "
edd16368
SC		 1641 "%02x %02x %02x %02x %02x]\n",
1642 cp, sense_key, asc, ascq,
1643 cmd->result,
1644 cmd->cmnd[0], cmd->cmnd[1],
1645 cmd->cmnd[2], cmd->cmnd[3],
1646 cmd->cmnd[4], cmd->cmnd[5],
1647 cmd->cmnd[6], cmd->cmnd[7],
807be732
MM		 1648 cmd->cmnd[8], cmd->cmnd[9],
1649 cmd->cmnd[10], cmd->cmnd[11],
1650 cmd->cmnd[12], cmd->cmnd[13],
1651 cmd->cmnd[14], cmd->cmnd[15]);
edd16368
SC		 1652 break;
1653 }
1654
1655
1656 /* Problem was not a check condition
1657 * Pass it up to the upper layers...
1658 */
1659 if (ei->ScsiStatus) {
1660 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1661 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1662 "Returning result: 0x%x\n",
1663 cp, ei->ScsiStatus,
1664 sense_key, asc, ascq,
1665 cmd->result);
1666 } else { /* scsi status is zero??? How??? */
1667 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1668 "Returning no connection.\n", cp),
1669
1670 /* Ordinarily, this case should never happen,
1671 * but there is a bug in some released firmware
1672 * revisions that allows it to happen if, for
1673 * example, a 4100 backplane loses power and
1674 * the tape drive is in it. We assume that
1675 * it's a fatal error of some kind because we
1676 * can't show that it wasn't. We will make it
1677 * look like selection timeout since that is
1678 * the most common reason for this to occur,
1679 * and it's severe enough.
1680 */
1681
1682 cmd->result = DID_NO_CONNECT << 16;
1683 }
1684 break;
1685
1686 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1687 break;
1688 case CMD_DATA_OVERRUN:
1689 dev_warn(&h->pdev->dev, "cp %p has"
1690 " completed with data overrun "
1691 "reported\n", cp);
1692 break;
1693 case CMD_INVALID: {
1694 /* print_bytes(cp, sizeof(*cp), 1, 0);
1695 print_cmd(cp); */
1696 /* We get CMD_INVALID if you address a non-existent device
1697 * instead of a selection timeout (no response). You will
1698 * see this if you yank out a drive, then try to access it.
1699 * This is kind of a shame because it means that any other
1700 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1701 * missing target. */
1702 cmd->result = DID_NO_CONNECT << 16;
1703 }
1704 break;
1705 case CMD_PROTOCOL_ERR:
256d0eaa 1706 cmd->result = DID_ERROR << 16;
edd16368 1707 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1708 "protocol error\n", cp);
edd16368
SC		 1709 break;
1710 case CMD_HARDWARE_ERR:
1711 cmd->result = DID_ERROR << 16;
1712 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1713 break;
1714 case CMD_CONNECTION_LOST:
1715 cmd->result = DID_ERROR << 16;
1716 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1717 break;
1718 case CMD_ABORTED:
1719 cmd->result = DID_ABORT << 16;
1720 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1721 cp, ei->ScsiStatus);
1722 break;
1723 case CMD_ABORT_FAILED:
1724 cmd->result = DID_ERROR << 16;
1725 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1726 break;
1727 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1728 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1729 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1730 "abort\n", cp);
1731 break;
1732 case CMD_TIMEOUT:
1733 cmd->result = DID_TIME_OUT << 16;
1734 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1735 break;
1d5e2ed0
SC		 1736 case CMD_UNABORTABLE:
1737 cmd->result = DID_ERROR << 16;
1738 dev_warn(&h->pdev->dev, "Command unabortable\n");
1739 break;
283b4a9b
SC		 1740 case CMD_IOACCEL_DISABLED:
1741 /* This only handles the direct pass-through case since RAID
1742 * offload is handled above. Just attempt a retry.
1743 */
1744 cmd->result = DID_SOFT_ERROR << 16;
1745 dev_warn(&h->pdev->dev,
1746 "cp %p had HP SSD Smart Path error\n", cp);
1747 break;
edd16368
SC		 1748 default:
1749 cmd->result = DID_ERROR << 16;
1750 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1751 cp, ei->CommandStatus);
1752 }
edd16368 1753 cmd_free(h, cp);
2cc5bfaf 1754 cmd->scsi_done(cmd);
edd16368
SC		 1755}
1756
edd16368
SC		 1757static void hpsa_pci_unmap(struct pci_dev *pdev,
1758 struct CommandList *c, int sg_used, int data_direction)
1759{
1760 int i;
1761 union u64bit addr64;
1762
1763 for (i = 0; i < sg_used; i++) {
1764 addr64.val32.lower = c->SG[i].Addr.lower;
1765 addr64.val32.upper = c->SG[i].Addr.upper;
1766 pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
1767 data_direction);
1768 }
1769}
1770
a2dac136 1771static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1772 struct CommandList *cp,
1773 unsigned char *buf,
1774 size_t buflen,
1775 int data_direction)
1776{
01a02ffc 1777 u64 addr64;
edd16368
SC		 1778
1779 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1780 cp->Header.SGList = 0;
1781 cp->Header.SGTotal = 0;
a2dac136 1782 return 0;
edd16368
SC		 1783 }
1784
01a02ffc 1785 addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1786 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1787 /* Prevent subsequent unmap of something never mapped */
eceaae18
SK		 1788 cp->Header.SGList = 0;
1789 cp->Header.SGTotal = 0;
a2dac136 1790 return -1;
eceaae18 1791 }
edd16368 1792 cp->SG[0].Addr.lower =
01a02ffc 1793 (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
edd16368 1794 cp->SG[0].Addr.upper =
01a02ffc 1795 (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
edd16368 1796 cp->SG[0].Len = buflen;
e1d9cbfa 1797 cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */
01a02ffc
SC		 1798 cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
1799 cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
a2dac136 1800 return 0;
edd16368
SC		 1801}
1802
1803static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1804 struct CommandList *c)
1805{
1806 DECLARE_COMPLETION_ONSTACK(wait);
1807
1808 c->waiting = &wait;
1809 enqueue_cmd_and_start_io(h, c);
1810 wait_for_completion(&wait);
1811}
1812
a0c12413
SC		 1813static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1814 struct CommandList *c)
1815{
1816 unsigned long flags;
1817
1818 /* If controller lockup detected, fake a hardware error. */
1819 spin_lock_irqsave(&h->lock, flags);
1820 if (unlikely(h->lockup_detected)) {
1821 spin_unlock_irqrestore(&h->lock, flags);
1822 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
1823 } else {
1824 spin_unlock_irqrestore(&h->lock, flags);
1825 hpsa_scsi_do_simple_cmd_core(h, c);
1826 }
1827}
1828
9c2fc160 1829#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 1830static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
1831 struct CommandList *c, int data_direction)
1832{
9c2fc160 1833 int backoff_time = 10, retry_count = 0;
edd16368
SC		 1834
1835 do {
7630abd0 1836 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 1837 hpsa_scsi_do_simple_cmd_core(h, c);
1838 retry_count++;
9c2fc160
SC		 1839 if (retry_count > 3) {
1840 msleep(backoff_time);
1841 if (backoff_time < 1000)
1842 backoff_time *= 2;
1843 }
852af20a 1844 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 1845 check_for_busy(h, c)) &&
1846 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 1847 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
1848}
1849
1850static void hpsa_scsi_interpret_error(struct CommandList *cp)
1851{
1852 struct ErrorInfo *ei;
1853 struct device *d = &cp->h->pdev->dev;
1854
1855 ei = cp->err_info;
1856 switch (ei->CommandStatus) {
1857 case CMD_TARGET_STATUS:
1858 dev_warn(d, "cmd %p has completed with errors\n", cp);
1859 dev_warn(d, "cmd %p has SCSI Status = %x\n", cp,
1860 ei->ScsiStatus);
1861 if (ei->ScsiStatus == 0)
1862 dev_warn(d, "SCSI status is abnormally zero. "
1863 "(probably indicates selection timeout "
1864 "reported incorrectly due to a known "
1865 "firmware bug, circa July, 2001.)\n");
1866 break;
1867 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1868 dev_info(d, "UNDERRUN\n");
1869 break;
1870 case CMD_DATA_OVERRUN:
1871 dev_warn(d, "cp %p has completed with data overrun\n", cp);
1872 break;
1873 case CMD_INVALID: {
1874 /* controller unfortunately reports SCSI passthru's
1875 * to non-existent targets as invalid commands.
1876 */
1877 dev_warn(d, "cp %p is reported invalid (probably means "
1878 "target device no longer present)\n", cp);
1879 /* print_bytes((unsigned char *) cp, sizeof(*cp), 1, 0);
1880 print_cmd(cp); */
1881 }
1882 break;
1883 case CMD_PROTOCOL_ERR:
1884 dev_warn(d, "cp %p has protocol error \n", cp);
1885 break;
1886 case CMD_HARDWARE_ERR:
1887 /* cmd->result = DID_ERROR << 16; */
1888 dev_warn(d, "cp %p had hardware error\n", cp);
1889 break;
1890 case CMD_CONNECTION_LOST:
1891 dev_warn(d, "cp %p had connection lost\n", cp);
1892 break;
1893 case CMD_ABORTED:
1894 dev_warn(d, "cp %p was aborted\n", cp);
1895 break;
1896 case CMD_ABORT_FAILED:
1897 dev_warn(d, "cp %p reports abort failed\n", cp);
1898 break;
1899 case CMD_UNSOLICITED_ABORT:
1900 dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp);
1901 break;
1902 case CMD_TIMEOUT:
1903 dev_warn(d, "cp %p timed out\n", cp);
1904 break;
1d5e2ed0
SC		 1905 case CMD_UNABORTABLE:
1906 dev_warn(d, "Command unabortable\n");
1907 break;
edd16368
SC		 1908 default:
1909 dev_warn(d, "cp %p returned unknown status %x\n", cp,
1910 ei->CommandStatus);
1911 }
1912}
1913
1914static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 1915 u16 page, unsigned char *buf,
edd16368
SC		 1916 unsigned char bufsize)
1917{
1918 int rc = IO_OK;
1919 struct CommandList *c;
1920 struct ErrorInfo *ei;
1921
1922 c = cmd_special_alloc(h);
1923
1924 if (c == NULL) { /* trouble... */
1925 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
ecd9aad4 1926 return -ENOMEM;
edd16368
SC		 1927 }
1928
a2dac136
SC		 1929 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
1930 page, scsi3addr, TYPE_CMD)) {
1931 rc = -1;
1932 goto out;
1933 }
edd16368
SC		 1934 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
1935 ei = c->err_info;
1936 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
1937 hpsa_scsi_interpret_error(c);
1938 rc = -1;
1939 }
a2dac136 1940out:
edd16368
SC		 1941 cmd_special_free(h, c);
1942 return rc;
1943}
1944
bf711ac6
ST		 1945static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
1946 u8 reset_type)
edd16368
SC		 1947{
1948 int rc = IO_OK;
1949 struct CommandList *c;
1950 struct ErrorInfo *ei;
1951
1952 c = cmd_special_alloc(h);
1953
1954 if (c == NULL) { /* trouble... */
1955 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
e9ea04a6 1956 return -ENOMEM;
edd16368
SC		 1957 }
1958
a2dac136 1959 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 1960 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
1961 scsi3addr, TYPE_MSG);
1962 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 1963 hpsa_scsi_do_simple_cmd_core(h, c);
1964 /* no unmap needed here because no data xfer. */
1965
1966 ei = c->err_info;
1967 if (ei->CommandStatus != 0) {
1968 hpsa_scsi_interpret_error(c);
1969 rc = -1;
1970 }
1971 cmd_special_free(h, c);
1972 return rc;
1973}
1974
1975static void hpsa_get_raid_level(struct ctlr_info *h,
1976 unsigned char *scsi3addr, unsigned char *raid_level)
1977{
1978 int rc;
1979 unsigned char *buf;
1980
1981 *raid_level = RAID_UNKNOWN;
1982 buf = kzalloc(64, GFP_KERNEL);
1983 if (!buf)
1984 return;
b7bb24eb 1985 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 1986 if (rc == 0)
1987 *raid_level = buf[8];
1988 if (*raid_level > RAID_UNKNOWN)
1989 *raid_level = RAID_UNKNOWN;
1990 kfree(buf);
1991 return;
1992}
1993
283b4a9b
SC		 1994#define HPSA_MAP_DEBUG
1995#ifdef HPSA_MAP_DEBUG
1996static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
1997 struct raid_map_data *map_buff)
1998{
1999 struct raid_map_disk_data *dd = &map_buff->data[0];
2000 int map, row, col;
2001 u16 map_cnt, row_cnt, disks_per_row;
2002
2003 if (rc != 0)
2004 return;
2005
2006 dev_info(&h->pdev->dev, "structure_size = %u\n",
2007 le32_to_cpu(map_buff->structure_size));
2008 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2009 le32_to_cpu(map_buff->volume_blk_size));
2010 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2011 le64_to_cpu(map_buff->volume_blk_cnt));
2012 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2013 map_buff->phys_blk_shift);
2014 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2015 map_buff->parity_rotation_shift);
2016 dev_info(&h->pdev->dev, "strip_size = %u\n",
2017 le16_to_cpu(map_buff->strip_size));
2018 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2019 le64_to_cpu(map_buff->disk_starting_blk));
2020 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2021 le64_to_cpu(map_buff->disk_blk_cnt));
2022 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2023 le16_to_cpu(map_buff->data_disks_per_row));
2024 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2025 le16_to_cpu(map_buff->metadata_disks_per_row));
2026 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2027 le16_to_cpu(map_buff->row_cnt));
2028 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2029 le16_to_cpu(map_buff->layout_map_count));
dd0e19f3
ST		 2030 dev_info(&h->pdev->dev, "flags = %u\n",
2031 le16_to_cpu(map_buff->flags));
2032 if (map_buff->flags & RAID_MAP_FLAG_ENCRYPT_ON)
2033 dev_info(&h->pdev->dev, "encrypytion = ON\n");
2034 else
2035 dev_info(&h->pdev->dev, "encrypytion = OFF\n");
2036 dev_info(&h->pdev->dev, "dekindex = %u\n",
2037 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2038
2039 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2040 for (map = 0; map < map_cnt; map++) {
2041 dev_info(&h->pdev->dev, "Map%u:\n", map);
2042 row_cnt = le16_to_cpu(map_buff->row_cnt);
2043 for (row = 0; row < row_cnt; row++) {
2044 dev_info(&h->pdev->dev, " Row%u:\n", row);
2045 disks_per_row =
2046 le16_to_cpu(map_buff->data_disks_per_row);
2047 for (col = 0; col < disks_per_row; col++, dd++)
2048 dev_info(&h->pdev->dev,
2049 " D%02u: h=0x%04x xor=%u,%u\n",
2050 col, dd->ioaccel_handle,
2051 dd->xor_mult[0], dd->xor_mult[1]);
2052 disks_per_row =
2053 le16_to_cpu(map_buff->metadata_disks_per_row);
2054 for (col = 0; col < disks_per_row; col++, dd++)
2055 dev_info(&h->pdev->dev,
2056 " M%02u: h=0x%04x xor=%u,%u\n",
2057 col, dd->ioaccel_handle,
2058 dd->xor_mult[0], dd->xor_mult[1]);
2059 }
2060 }
2061}
2062#else
2063static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2064 __attribute__((unused)) int rc,
2065 __attribute__((unused)) struct raid_map_data *map_buff)
2066{
2067}
2068#endif
2069
2070static int hpsa_get_raid_map(struct ctlr_info *h,
2071 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2072{
2073 int rc = 0;
2074 struct CommandList *c;
2075 struct ErrorInfo *ei;
2076
2077 c = cmd_special_alloc(h);
2078 if (c == NULL) {
2079 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2080 return -ENOMEM;
2081 }
2082 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2083 sizeof(this_device->raid_map), 0,
2084 scsi3addr, TYPE_CMD)) {
2085 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
2086 cmd_special_free(h, c);
2087 return -ENOMEM;
2088 }
2089 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2090 ei = c->err_info;
2091 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2092 hpsa_scsi_interpret_error(c);
2093 cmd_special_free(h, c);
2094 return -1;
2095 }
2096 cmd_special_free(h, c);
2097
2098 /* @todo in the future, dynamically allocate RAID map memory */
2099 if (le32_to_cpu(this_device->raid_map.structure_size) >
2100 sizeof(this_device->raid_map)) {
2101 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2102 rc = -1;
2103 }
2104 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2105 return rc;
2106}
2107
1b70150a
SC		 2108static int hpsa_vpd_page_supported(struct ctlr_info *h,
2109 unsigned char scsi3addr[], u8 page)
2110{
2111 int rc;
2112 int i;
2113 int pages;
2114 unsigned char *buf, bufsize;
2115
2116 buf = kzalloc(256, GFP_KERNEL);
2117 if (!buf)
2118 return 0;
2119
2120 /* Get the size of the page list first */
2121 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2122 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2123 buf, HPSA_VPD_HEADER_SZ);
2124 if (rc != 0)
2125 goto exit_unsupported;
2126 pages = buf[3];
2127 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2128 bufsize = pages + HPSA_VPD_HEADER_SZ;
2129 else
2130 bufsize = 255;
2131
2132 /* Get the whole VPD page list */
2133 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2134 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2135 buf, bufsize);
2136 if (rc != 0)
2137 goto exit_unsupported;
2138
2139 pages = buf[3];
2140 for (i = 1; i <= pages; i++)
2141 if (buf[3 + i] == page)
2142 goto exit_supported;
2143exit_unsupported:
2144 kfree(buf);
2145 return 0;
2146exit_supported:
2147 kfree(buf);
2148 return 1;
2149}
2150
283b4a9b
SC		 2151static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2152 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2153{
2154 int rc;
2155 unsigned char *buf;
2156 u8 ioaccel_status;
2157
2158 this_device->offload_config = 0;
2159 this_device->offload_enabled = 0;
2160
2161 buf = kzalloc(64, GFP_KERNEL);
2162 if (!buf)
2163 return;
1b70150a
SC		 2164 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2165 goto out;
283b4a9b 2166 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2167 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2168 if (rc != 0)
2169 goto out;
2170
2171#define IOACCEL_STATUS_BYTE 4
2172#define OFFLOAD_CONFIGURED_BIT 0x01
2173#define OFFLOAD_ENABLED_BIT 0x02
2174 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2175 this_device->offload_config =
2176 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2177 if (this_device->offload_config) {
2178 this_device->offload_enabled =
2179 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2180 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2181 this_device->offload_enabled = 0;
2182 }
2183out:
2184 kfree(buf);
2185 return;
2186}
2187
edd16368
SC		 2188/* Get the device id from inquiry page 0x83 */
2189static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2190 unsigned char *device_id, int buflen)
2191{
2192 int rc;
2193 unsigned char *buf;
2194
2195 if (buflen > 16)
2196 buflen = 16;
2197 buf = kzalloc(64, GFP_KERNEL);
2198 if (!buf)
2199 return -1;
b7bb24eb 2200 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2201 if (rc == 0)
2202 memcpy(device_id, &buf[8], buflen);
2203 kfree(buf);
2204 return rc != 0;
2205}
2206
2207static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2208 struct ReportLUNdata *buf, int bufsize,
2209 int extended_response)
2210{
2211 int rc = IO_OK;
2212 struct CommandList *c;
2213 unsigned char scsi3addr[8];
2214 struct ErrorInfo *ei;
2215
2216 c = cmd_special_alloc(h);
2217 if (c == NULL) { /* trouble... */
2218 dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2219 return -1;
2220 }
e89c0ae7
SC		 2221 /* address the controller */
2222 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2223 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2224 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2225 rc = -1;
2226 goto out;
2227 }
edd16368
SC		 2228 if (extended_response)
2229 c->Request.CDB[1] = extended_response;
2230 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2231 ei = c->err_info;
2232 if (ei->CommandStatus != 0 &&
2233 ei->CommandStatus != CMD_DATA_UNDERRUN) {
2234 hpsa_scsi_interpret_error(c);
2235 rc = -1;
283b4a9b
SC		 2236 } else {
2237 if (buf->extended_response_flag != extended_response) {
2238 dev_err(&h->pdev->dev,
2239 "report luns requested format %u, got %u\n",
2240 extended_response,
2241 buf->extended_response_flag);
2242 rc = -1;
2243 }
edd16368 2244 }
a2dac136 2245out:
edd16368
SC		 2246 cmd_special_free(h, c);
2247 return rc;
2248}
2249
2250static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2251 struct ReportLUNdata *buf,
2252 int bufsize, int extended_response)
2253{
2254 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2255}
2256
2257static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2258 struct ReportLUNdata *buf, int bufsize)
2259{
2260 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2261}
2262
2263static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2264 int bus, int target, int lun)
2265{
2266 device->bus = bus;
2267 device->target = target;
2268 device->lun = lun;
2269}
2270
2271static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2272 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2273 unsigned char *is_OBDR_device)
edd16368 2274{
0b0e1d6c
SC		 2275
2276#define OBDR_SIG_OFFSET 43
2277#define OBDR_TAPE_SIG "$DR-10"
2278#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2279#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2280
ea6d3bc3 2281 unsigned char *inq_buff;
0b0e1d6c 2282 unsigned char *obdr_sig;
edd16368 2283
ea6d3bc3 2284 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2285 if (!inq_buff)
2286 goto bail_out;
2287
edd16368
SC		 2288 /* Do an inquiry to the device to see what it is. */
2289 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2290 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2291 /* Inquiry failed (msg printed already) */
2292 dev_err(&h->pdev->dev,
2293 "hpsa_update_device_info: inquiry failed\n");
2294 goto bail_out;
2295 }
2296
edd16368
SC		 2297 this_device->devtype = (inq_buff[0] & 0x1f);
2298 memcpy(this_device->scsi3addr, scsi3addr, 8);
2299 memcpy(this_device->vendor, &inq_buff[8],
2300 sizeof(this_device->vendor));
2301 memcpy(this_device->model, &inq_buff[16],
2302 sizeof(this_device->model));
edd16368
SC		 2303 memset(this_device->device_id, 0,
2304 sizeof(this_device->device_id));
2305 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2306 sizeof(this_device->device_id));
2307
2308 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2309 is_logical_dev_addr_mode(scsi3addr)) {
edd16368 2310 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2311 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2312 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
2313 } else {
edd16368 2314 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2315 this_device->offload_config = 0;
2316 this_device->offload_enabled = 0;
2317 }
edd16368 2318
0b0e1d6c
SC		 2319 if (is_OBDR_device) {
2320 /* See if this is a One-Button-Disaster-Recovery device
2321 * by looking for "$DR-10" at offset 43 in inquiry data.
2322 */
2323 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2324 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2325 strncmp(obdr_sig, OBDR_TAPE_SIG,
2326 OBDR_SIG_LEN) == 0);
2327 }
2328
edd16368
SC		 2329 kfree(inq_buff);
2330 return 0;
2331
2332bail_out:
2333 kfree(inq_buff);
2334 return 1;
2335}
2336
4f4eb9f1 2337static unsigned char *ext_target_model[] = {
edd16368
SC		 2338 "MSA2012",
2339 "MSA2024",
2340 "MSA2312",
2341 "MSA2324",
fda38518 2342 "P2000 G3 SAS",
e06c8e5c 2343 "MSA 2040 SAS",
edd16368
SC		 2344 NULL,
2345};
2346
4f4eb9f1 2347static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2348{
2349 int i;
2350
4f4eb9f1
ST		 2351 for (i = 0; ext_target_model[i]; i++)
2352 if (strncmp(device->model, ext_target_model[i],
2353 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2354 return 1;
2355 return 0;
2356}
2357
2358/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2359 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2360 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2361 * Logical drive target and lun are assigned at this time, but
2362 * physical device lun and target assignment are deferred (assigned
2363 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2364 */
2365static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2366 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2367{
1f310bde
SC		 2368 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2369
2370 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2371 /* physical device, target and lun filled in later */
edd16368 2372 if (is_hba_lunid(lunaddrbytes))
1f310bde 2373 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2374 else
1f310bde
SC		 2375 /* defer target, lun assignment for physical devices */
2376 hpsa_set_bus_target_lun(device, 2, -1, -1);
2377 return;
2378 }
2379 /* It's a logical device */
4f4eb9f1
ST		 2380 if (is_ext_target(h, device)) {
2381 /* external target way, put logicals on bus 1
1f310bde
SC		 2382 * and match target/lun numbers box
2383 * reports, other smart array, bus 0, target 0, match lunid
2384 */
2385 hpsa_set_bus_target_lun(device,
2386 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2387 return;
edd16368 2388 }
1f310bde 2389 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2390}
2391
2392/*
2393 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2394 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2395 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2396 * it for some reason. *tmpdevice is the target we're adding,
2397 * this_device is a pointer into the current element of currentsd[]
2398 * that we're building up in update_scsi_devices(), below.
2399 * lunzerobits is a bitmap that tracks which targets already have a
2400 * lun 0 assigned.
2401 * Returns 1 if an enclosure was added, 0 if not.
2402 */
4f4eb9f1 2403static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2404 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2405 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2406 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2407{
2408 unsigned char scsi3addr[8];
2409
1f310bde 2410 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2411 return 0; /* There is already a lun 0 on this target. */
2412
2413 if (!is_logical_dev_addr_mode(lunaddrbytes))
2414 return 0; /* It's the logical targets that may lack lun 0. */
2415
4f4eb9f1
ST		 2416 if (!is_ext_target(h, tmpdevice))
2417 return 0; /* Only external target devices have this problem. */
edd16368 2418
1f310bde 2419 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2420 return 0;
2421
c4f8a299 2422 memset(scsi3addr, 0, 8);
1f310bde 2423 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2424 if (is_hba_lunid(scsi3addr))
2425 return 0; /* Don't add the RAID controller here. */
2426
339b2b14
SC		 2427 if (is_scsi_rev_5(h))
2428 return 0; /* p1210m doesn't need to do this. */
2429
4f4eb9f1 2430 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2431 dev_warn(&h->pdev->dev, "Maximum number of external "
2432 "target devices exceeded. Check your hardware "
edd16368
SC		 2433 "configuration.");
2434 return 0;
2435 }
2436
0b0e1d6c 2437 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2438 return 0;
4f4eb9f1 2439 (*n_ext_target_devs)++;
1f310bde
SC		 2440 hpsa_set_bus_target_lun(this_device,
2441 tmpdevice->bus, tmpdevice->target, 0);
2442 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2443 return 1;
2444}
2445
54b6e9e9
ST		 2446/*
2447 * Get address of physical disk used for an ioaccel2 mode command:
2448 * 1. Extract ioaccel2 handle from the command.
2449 * 2. Find a matching ioaccel2 handle from list of physical disks.
2450 * 3. Return:
2451 * 1 and set scsi3addr to address of matching physical
2452 * 0 if no matching physical disk was found.
2453 */
2454static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2455 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2456{
2457 struct ReportExtendedLUNdata *physicals = NULL;
2458 int responsesize = 24; /* size of physical extended response */
2459 int extended = 2; /* flag forces reporting 'other dev info'. */
2460 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2461 u32 nphysicals = 0; /* number of reported physical devs */
2462 int found = 0; /* found match (1) or not (0) */
2463 u32 find; /* handle we need to match */
2464 int i;
2465 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2466 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2467 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2468 u32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2469 u32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2470
2471 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2472 return 0; /* no match */
2473
2474 /* point to the ioaccel2 device handle */
2475 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2476 if (c2a == NULL)
2477 return 0; /* no match */
2478
2479 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2480 if (scmd == NULL)
2481 return 0; /* no match */
2482
2483 d = scmd->device->hostdata;
2484 if (d == NULL)
2485 return 0; /* no match */
2486
2487 it_nexus = cpu_to_le32((u32) d->ioaccel_handle);
2488 scsi_nexus = cpu_to_le32((u32) c2a->scsi_nexus);
2489 find = c2a->scsi_nexus;
2490
2491 /* Get the list of physical devices */
2492 physicals = kzalloc(reportsize, GFP_KERNEL);
2493 if (hpsa_scsi_do_report_phys_luns(h, (struct ReportLUNdata *) physicals,
2494 reportsize, extended)) {
2495 dev_err(&h->pdev->dev,
2496 "Can't lookup %s device handle: report physical LUNs failed.\n",
2497 "HP SSD Smart Path");
2498 kfree(physicals);
2499 return 0;
2500 }
2501 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2502 responsesize;
2503
2504
2505 /* find ioaccel2 handle in list of physicals: */
2506 for (i = 0; i < nphysicals; i++) {
2507 /* handle is in bytes 28-31 of each lun */
2508 if (memcmp(&((struct ReportExtendedLUNdata *)
2509 physicals)->LUN[i][20], &find, 4) != 0) {
2510 continue; /* didn't match */
2511 }
2512 found = 1;
2513 memcpy(scsi3addr, &((struct ReportExtendedLUNdata *)
2514 physicals)->LUN[i][0], 8);
2515 break; /* found it */
2516 }
2517
2518 kfree(physicals);
2519 if (found)
2520 return 1;
2521 else
2522 return 0;
2523
2524}
edd16368
SC		 2525/*
2526 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2527 * logdev. The number of luns in physdev and logdev are returned in
2528 * *nphysicals and *nlogicals, respectively.
2529 * Returns 0 on success, -1 otherwise.
2530 */
2531static int hpsa_gather_lun_info(struct ctlr_info *h,
2532 int reportlunsize,
283b4a9b 2533 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2534 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2535{
283b4a9b
SC		 2536 int physical_entry_size = 8;
2537
2538 *physical_mode = 0;
2539
2540 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2541 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2542 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2543 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2544 physical_entry_size = 24;
2545 }
a93aa1fe 2546 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize,
283b4a9b 2547 *physical_mode)) {
edd16368
SC		 2548 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2549 return -1;
2550 }
283b4a9b
SC		 2551 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2552 physical_entry_size;
edd16368
SC		 2553 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2554 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2555 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2556 *nphysicals - HPSA_MAX_PHYS_LUN);
2557 *nphysicals = HPSA_MAX_PHYS_LUN;
2558 }
2559 if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
2560 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2561 return -1;
2562 }
6df1e954 2563 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2564 /* Reject Logicals in excess of our max capability. */
2565 if (*nlogicals > HPSA_MAX_LUN) {
2566 dev_warn(&h->pdev->dev,
2567 "maximum logical LUNs (%d) exceeded. "
2568 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2569 *nlogicals - HPSA_MAX_LUN);
2570 *nlogicals = HPSA_MAX_LUN;
2571 }
2572 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2573 dev_warn(&h->pdev->dev,
2574 "maximum logical + physical LUNs (%d) exceeded. "
2575 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2576 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2577 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2578 }
2579 return 0;
2580}
2581
339b2b14 2582u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
a93aa1fe
MG		 2583 int nphysicals, int nlogicals,
2584 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2585 struct ReportLUNdata *logdev_list)
2586{
2587 /* Helper function, figure out where the LUN ID info is coming from
2588 * given index i, lists of physical and logical devices, where in
2589 * the list the raid controller is supposed to appear (first or last)
2590 */
2591
2592 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2593 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2594
2595 if (i == raid_ctlr_position)
2596 return RAID_CTLR_LUNID;
2597
2598 if (i < logicals_start)
2599 return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
2600
2601 if (i < last_device)
2602 return &logdev_list->LUN[i - nphysicals -
2603 (raid_ctlr_position == 0)][0];
2604 BUG();
2605 return NULL;
2606}
2607
edd16368
SC		 2608static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2609{
2610 /* the idea here is we could get notified
2611 * that some devices have changed, so we do a report
2612 * physical luns and report logical luns cmd, and adjust
2613 * our list of devices accordingly.
2614 *
2615 * The scsi3addr's of devices won't change so long as the
2616 * adapter is not reset. That means we can rescan and
2617 * tell which devices we already know about, vs. new
2618 * devices, vs. disappearing devices.
2619 */
a93aa1fe 2620 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 2621 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 2622 u32 nphysicals = 0;
2623 u32 nlogicals = 0;
283b4a9b 2624 int physical_mode = 0;
01a02ffc 2625 u32 ndev_allocated = 0;
edd16368
SC		 2626 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
2627 int ncurrent = 0;
283b4a9b 2628 int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 24;
4f4eb9f1 2629 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 2630 int raid_ctlr_position;
aca4a520 2631 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 2632
cfe5badc 2633 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 2634 physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
2635 logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
edd16368
SC		 2636 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
2637
0b0e1d6c 2638 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 2639 dev_err(&h->pdev->dev, "out of memory\n");
2640 goto out;
2641 }
2642 memset(lunzerobits, 0, sizeof(lunzerobits));
2643
a93aa1fe
MG		 2644 if (hpsa_gather_lun_info(h, reportlunsize,
2645 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 2646 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 2647 goto out;
2648
aca4a520
ST		 2649 /* We might see up to the maximum number of logical and physical disks
2650 * plus external target devices, and a device for the local RAID
2651 * controller.
edd16368 2652 */
aca4a520 2653 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 2654
2655 /* Allocate the per device structures */
2656 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 2657 if (i >= HPSA_MAX_DEVICES) {
2658 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
2659 " %d devices ignored.\n", HPSA_MAX_DEVICES,
2660 ndevs_to_allocate - HPSA_MAX_DEVICES);
2661 break;
2662 }
2663
edd16368
SC		 2664 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
2665 if (!currentsd[i]) {
2666 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
2667 __FILE__, __LINE__);
2668 goto out;
2669 }
2670 ndev_allocated++;
2671 }
2672
339b2b14
SC		 2673 if (unlikely(is_scsi_rev_5(h)))
2674 raid_ctlr_position = 0;
2675 else
2676 raid_ctlr_position = nphysicals + nlogicals;
2677
edd16368 2678 /* adjust our table of devices */
4f4eb9f1 2679 n_ext_target_devs = 0;
edd16368 2680 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 2681 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 2682
2683 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 2684 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
2685 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 2686 /* skip masked physical devices. */
339b2b14
SC		 2687 if (lunaddrbytes[3] & 0xC0 &&
2688 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 2689 continue;
2690
2691 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 2692 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
2693 &is_OBDR))
edd16368 2694 continue; /* skip it if we can't talk to it. */
1f310bde 2695 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 2696 this_device = currentsd[ncurrent];
2697
2698 /*
4f4eb9f1 2699 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 2700 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
2701 * is nonetheless an enclosure device there. We have to
2702 * present that otherwise linux won't find anything if
2703 * there is no lun 0.
2704 */
4f4eb9f1 2705 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 2706 lunaddrbytes, lunzerobits,
4f4eb9f1 2707 &n_ext_target_devs)) {
edd16368
SC		 2708 ncurrent++;
2709 this_device = currentsd[ncurrent];
2710 }
2711
2712 *this_device = *tmpdevice;
edd16368
SC		 2713
2714 switch (this_device->devtype) {
0b0e1d6c 2715 case TYPE_ROM:
edd16368
SC		 2716 /* We don't *really* support actual CD-ROM devices,
2717 * just "One Button Disaster Recovery" tape drive
2718 * which temporarily pretends to be a CD-ROM drive.
2719 * So we check that the device is really an OBDR tape
2720 * device by checking for "$DR-10" in bytes 43-48 of
2721 * the inquiry data.
2722 */
0b0e1d6c
SC		 2723 if (is_OBDR)
2724 ncurrent++;
edd16368
SC		 2725 break;
2726 case TYPE_DISK:
283b4a9b
SC		 2727 if (i >= nphysicals) {
2728 ncurrent++;
edd16368 2729 break;
283b4a9b
SC		 2730 }
2731 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
2732 memcpy(&this_device->ioaccel_handle,
2733 &lunaddrbytes[20],
2734 sizeof(this_device->ioaccel_handle));
2735 ncurrent++;
2736 }
edd16368
SC		 2737 break;
2738 case TYPE_TAPE:
2739 case TYPE_MEDIUM_CHANGER:
2740 ncurrent++;
2741 break;
2742 case TYPE_RAID:
2743 /* Only present the Smartarray HBA as a RAID controller.
2744 * If it's a RAID controller other than the HBA itself
2745 * (an external RAID controller, MSA500 or similar)
2746 * don't present it.
2747 */
2748 if (!is_hba_lunid(lunaddrbytes))
2749 break;
2750 ncurrent++;
2751 break;
2752 default:
2753 break;
2754 }
cfe5badc 2755 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 2756 break;
2757 }
2758 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
2759out:
2760 kfree(tmpdevice);
2761 for (i = 0; i < ndev_allocated; i++)
2762 kfree(currentsd[i]);
2763 kfree(currentsd);
edd16368
SC		 2764 kfree(physdev_list);
2765 kfree(logdev_list);
edd16368
SC		 2766}
2767
2768/* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
2769 * dma mapping and fills in the scatter gather entries of the
2770 * hpsa command, cp.
2771 */
33a2ffce 2772static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 2773 struct CommandList *cp,
2774 struct scsi_cmnd *cmd)
2775{
2776 unsigned int len;
2777 struct scatterlist *sg;
01a02ffc 2778 u64 addr64;
33a2ffce
SC		 2779 int use_sg, i, sg_index, chained;
2780 struct SGDescriptor *curr_sg;
edd16368 2781
33a2ffce 2782 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 2783
2784 use_sg = scsi_dma_map(cmd);
2785 if (use_sg < 0)
2786 return use_sg;
2787
2788 if (!use_sg)
2789 goto sglist_finished;
2790
33a2ffce
SC		 2791 curr_sg = cp->SG;
2792 chained = 0;
2793 sg_index = 0;
edd16368 2794 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 2795 if (i == h->max_cmd_sg_entries - 1 &&
2796 use_sg > h->max_cmd_sg_entries) {
2797 chained = 1;
2798 curr_sg = h->cmd_sg_list[cp->cmdindex];
2799 sg_index = 0;
2800 }
01a02ffc 2801 addr64 = (u64) sg_dma_address(sg);
edd16368 2802 len = sg_dma_len(sg);
33a2ffce
SC		 2803 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2804 curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2805 curr_sg->Len = len;
e1d9cbfa 2806 curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST;
33a2ffce
SC		 2807 curr_sg++;
2808 }
2809
2810 if (use_sg + chained > h->maxSG)
2811 h->maxSG = use_sg + chained;
2812
2813 if (chained) {
2814 cp->Header.SGList = h->max_cmd_sg_entries;
2815 cp->Header.SGTotal = (u16) (use_sg + 1);
e2bea6df
SC		 2816 if (hpsa_map_sg_chain_block(h, cp)) {
2817 scsi_dma_unmap(cmd);
2818 return -1;
2819 }
33a2ffce 2820 return 0;
edd16368
SC		 2821 }
2822
2823sglist_finished:
2824
01a02ffc
SC		 2825 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
2826 cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
edd16368
SC		 2827 return 0;
2828}
2829
283b4a9b
SC		 2830#define IO_ACCEL_INELIGIBLE (1)
2831static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
2832{
2833 int is_write = 0;
2834 u32 block;
2835 u32 block_cnt;
2836
2837 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
2838 switch (cdb[0]) {
2839 case WRITE_6:
2840 case WRITE_12:
2841 is_write = 1;
2842 case READ_6:
2843 case READ_12:
2844 if (*cdb_len == 6) {
2845 block = (((u32) cdb[2]) << 8) | cdb[3];
2846 block_cnt = cdb[4];
2847 } else {
2848 BUG_ON(*cdb_len != 12);
2849 block = (((u32) cdb[2]) << 24) |
2850 (((u32) cdb[3]) << 16) |
2851 (((u32) cdb[4]) << 8) |
2852 cdb[5];
2853 block_cnt =
2854 (((u32) cdb[6]) << 24) |
2855 (((u32) cdb[7]) << 16) |
2856 (((u32) cdb[8]) << 8) |
2857 cdb[9];
2858 }
2859 if (block_cnt > 0xffff)
2860 return IO_ACCEL_INELIGIBLE;
2861
2862 cdb[0] = is_write ? WRITE_10 : READ_10;
2863 cdb[1] = 0;
2864 cdb[2] = (u8) (block >> 24);
2865 cdb[3] = (u8) (block >> 16);
2866 cdb[4] = (u8) (block >> 8);
2867 cdb[5] = (u8) (block);
2868 cdb[6] = 0;
2869 cdb[7] = (u8) (block_cnt >> 8);
2870 cdb[8] = (u8) (block_cnt);
2871 cdb[9] = 0;
2872 *cdb_len = 10;
2873 break;
2874 }
2875 return 0;
2876}
2877
c349775e 2878static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 2879 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2880 u8 *scsi3addr)
e1f7de0c
MG		 2881{
2882 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 2883 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
2884 unsigned int len;
2885 unsigned int total_len = 0;
2886 struct scatterlist *sg;
2887 u64 addr64;
2888 int use_sg, i;
2889 struct SGDescriptor *curr_sg;
2890 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
2891
283b4a9b
SC		 2892 /* TODO: implement chaining support */
2893 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
2894 return IO_ACCEL_INELIGIBLE;
2895
e1f7de0c
MG		 2896 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
2897
283b4a9b
SC		 2898 if (fixup_ioaccel_cdb(cdb, &cdb_len))
2899 return IO_ACCEL_INELIGIBLE;
2900
e1f7de0c
MG		 2901 c->cmd_type = CMD_IOACCEL1;
2902
2903 /* Adjust the DMA address to point to the accelerated command buffer */
2904 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
2905 (c->cmdindex * sizeof(*cp));
2906 BUG_ON(c->busaddr & 0x0000007F);
2907
2908 use_sg = scsi_dma_map(cmd);
2909 if (use_sg < 0)
2910 return use_sg;
2911
2912 if (use_sg) {
2913 curr_sg = cp->SG;
2914 scsi_for_each_sg(cmd, sg, use_sg, i) {
2915 addr64 = (u64) sg_dma_address(sg);
2916 len = sg_dma_len(sg);
2917 total_len += len;
2918 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2919 curr_sg->Addr.upper =
2920 (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2921 curr_sg->Len = len;
2922
2923 if (i == (scsi_sg_count(cmd) - 1))
2924 curr_sg->Ext = HPSA_SG_LAST;
2925 else
2926 curr_sg->Ext = 0; /* we are not chaining */
2927 curr_sg++;
2928 }
2929
2930 switch (cmd->sc_data_direction) {
2931 case DMA_TO_DEVICE:
2932 control |= IOACCEL1_CONTROL_DATA_OUT;
2933 break;
2934 case DMA_FROM_DEVICE:
2935 control |= IOACCEL1_CONTROL_DATA_IN;
2936 break;
2937 case DMA_NONE:
2938 control |= IOACCEL1_CONTROL_NODATAXFER;
2939 break;
2940 default:
2941 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
2942 cmd->sc_data_direction);
2943 BUG();
2944 break;
2945 }
2946 } else {
2947 control |= IOACCEL1_CONTROL_NODATAXFER;
2948 }
2949
c349775e 2950 c->Header.SGList = use_sg;
e1f7de0c 2951 /* Fill out the command structure to submit */
283b4a9b 2952 cp->dev_handle = ioaccel_handle & 0xFFFF;
e1f7de0c
MG		 2953 cp->transfer_len = total_len;
2954 cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ |
283b4a9b 2955 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK);
e1f7de0c 2956 cp->control = control;
283b4a9b
SC		 2957 memcpy(cp->CDB, cdb, cdb_len);
2958 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 2959 /* Tag was already set at init time. */
283b4a9b 2960 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 2961 return 0;
2962}
edd16368 2963
283b4a9b
SC		 2964/*
2965 * Queue a command directly to a device behind the controller using the
2966 * I/O accelerator path.
2967 */
2968static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
2969 struct CommandList *c)
2970{
2971 struct scsi_cmnd *cmd = c->scsi_cmd;
2972 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
2973
2974 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
2975 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
2976}
2977
dd0e19f3
ST		 2978/*
2979 * Set encryption parameters for the ioaccel2 request
2980 */
2981static void set_encrypt_ioaccel2(struct ctlr_info *h,
2982 struct CommandList *c, struct io_accel2_cmd *cp)
2983{
2984 struct scsi_cmnd *cmd = c->scsi_cmd;
2985 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
2986 struct raid_map_data *map = &dev->raid_map;
2987 u64 first_block;
2988
2989 BUG_ON(!(dev->offload_config && dev->offload_enabled));
2990
2991 /* Are we doing encryption on this device */
2992 if (!(map->flags & RAID_MAP_FLAG_ENCRYPT_ON))
2993 return;
2994 /* Set the data encryption key index. */
2995 cp->dekindex = map->dekindex;
2996
2997 /* Set the encryption enable flag, encoded into direction field. */
2998 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
2999
3000 /* Set encryption tweak values based on logical block address
3001 * If block size is 512, tweak value is LBA.
3002 * For other block sizes, tweak is (LBA * block size)/ 512)
3003 */
3004 switch (cmd->cmnd[0]) {
3005 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3006 case WRITE_6:
3007 case READ_6:
3008 if (map->volume_blk_size == 512) {
3009 cp->tweak_lower =
3010 (((u32) cmd->cmnd[2]) << 8) |
3011 cmd->cmnd[3];
3012 cp->tweak_upper = 0;
3013 } else {
3014 first_block =
3015 (((u64) cmd->cmnd[2]) << 8) |
3016 cmd->cmnd[3];
3017 first_block = (first_block * map->volume_blk_size)/512;
3018 cp->tweak_lower = (u32)first_block;
3019 cp->tweak_upper = (u32)(first_block >> 32);
3020 }
3021 break;
3022 case WRITE_10:
3023 case READ_10:
3024 if (map->volume_blk_size == 512) {
3025 cp->tweak_lower =
3026 (((u32) cmd->cmnd[2]) << 24) |
3027 (((u32) cmd->cmnd[3]) << 16) |
3028 (((u32) cmd->cmnd[4]) << 8) |
3029 cmd->cmnd[5];
3030 cp->tweak_upper = 0;
3031 } else {
3032 first_block =
3033 (((u64) cmd->cmnd[2]) << 24) |
3034 (((u64) cmd->cmnd[3]) << 16) |
3035 (((u64) cmd->cmnd[4]) << 8) |
3036 cmd->cmnd[5];
3037 first_block = (first_block * map->volume_blk_size)/512;
3038 cp->tweak_lower = (u32)first_block;
3039 cp->tweak_upper = (u32)(first_block >> 32);
3040 }
3041 break;
3042 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3043 case WRITE_12:
3044 case READ_12:
3045 if (map->volume_blk_size == 512) {
3046 cp->tweak_lower =
3047 (((u32) cmd->cmnd[2]) << 24) |
3048 (((u32) cmd->cmnd[3]) << 16) |
3049 (((u32) cmd->cmnd[4]) << 8) |
3050 cmd->cmnd[5];
3051 cp->tweak_upper = 0;
3052 } else {
3053 first_block =
3054 (((u64) cmd->cmnd[2]) << 24) |
3055 (((u64) cmd->cmnd[3]) << 16) |
3056 (((u64) cmd->cmnd[4]) << 8) |
3057 cmd->cmnd[5];
3058 first_block = (first_block * map->volume_blk_size)/512;
3059 cp->tweak_lower = (u32)first_block;
3060 cp->tweak_upper = (u32)(first_block >> 32);
3061 }
3062 break;
3063 case WRITE_16:
3064 case READ_16:
3065 if (map->volume_blk_size == 512) {
3066 cp->tweak_lower =
3067 (((u32) cmd->cmnd[6]) << 24) |
3068 (((u32) cmd->cmnd[7]) << 16) |
3069 (((u32) cmd->cmnd[8]) << 8) |
3070 cmd->cmnd[9];
3071 cp->tweak_upper =
3072 (((u32) cmd->cmnd[2]) << 24) |
3073 (((u32) cmd->cmnd[3]) << 16) |
3074 (((u32) cmd->cmnd[4]) << 8) |
3075 cmd->cmnd[5];
3076 } else {
3077 first_block =
3078 (((u64) cmd->cmnd[2]) << 56) |
3079 (((u64) cmd->cmnd[3]) << 48) |
3080 (((u64) cmd->cmnd[4]) << 40) |
3081 (((u64) cmd->cmnd[5]) << 32) |
3082 (((u64) cmd->cmnd[6]) << 24) |
3083 (((u64) cmd->cmnd[7]) << 16) |
3084 (((u64) cmd->cmnd[8]) << 8) |
3085 cmd->cmnd[9];
3086 first_block = (first_block * map->volume_blk_size)/512;
3087 cp->tweak_lower = (u32)first_block;
3088 cp->tweak_upper = (u32)(first_block >> 32);
3089 }
3090 break;
3091 default:
3092 dev_err(&h->pdev->dev,
3093 "ERROR: %s: IOACCEL request CDB size not supported for encryption\n",
3094 __func__);
3095 BUG();
3096 break;
3097 }
3098}
3099
c349775e
ST		 3100static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3101 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3102 u8 *scsi3addr)
3103{
3104 struct scsi_cmnd *cmd = c->scsi_cmd;
3105 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3106 struct ioaccel2_sg_element *curr_sg;
3107 int use_sg, i;
3108 struct scatterlist *sg;
3109 u64 addr64;
3110 u32 len;
3111 u32 total_len = 0;
3112
3113 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3114 return IO_ACCEL_INELIGIBLE;
3115
3116 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3117 return IO_ACCEL_INELIGIBLE;
3118 c->cmd_type = CMD_IOACCEL2;
3119 /* Adjust the DMA address to point to the accelerated command buffer */
3120 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3121 (c->cmdindex * sizeof(*cp));
3122 BUG_ON(c->busaddr & 0x0000007F);
3123
3124 memset(cp, 0, sizeof(*cp));
3125 cp->IU_type = IOACCEL2_IU_TYPE;
3126
3127 use_sg = scsi_dma_map(cmd);
3128 if (use_sg < 0)
3129 return use_sg;
3130
3131 if (use_sg) {
3132 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
3133 curr_sg = cp->sg;
3134 scsi_for_each_sg(cmd, sg, use_sg, i) {
3135 addr64 = (u64) sg_dma_address(sg);
3136 len = sg_dma_len(sg);
3137 total_len += len;
3138 curr_sg->address = cpu_to_le64(addr64);
3139 curr_sg->length = cpu_to_le32(len);
3140 curr_sg->reserved[0] = 0;
3141 curr_sg->reserved[1] = 0;
3142 curr_sg->reserved[2] = 0;
3143 curr_sg->chain_indicator = 0;
3144 curr_sg++;
3145 }
3146
3147 switch (cmd->sc_data_direction) {
3148 case DMA_TO_DEVICE:
dd0e19f3
ST		 3149 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3150 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3151 break;
3152 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3153 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3154 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3155 break;
3156 case DMA_NONE:
dd0e19f3
ST		 3157 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3158 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3159 break;
3160 default:
3161 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3162 cmd->sc_data_direction);
3163 BUG();
3164 break;
3165 }
3166 } else {
dd0e19f3
ST		 3167 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3168 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3169 }
dd0e19f3
ST		 3170
3171 /* Set encryption parameters, if necessary */
3172 set_encrypt_ioaccel2(h, c, cp);
3173
c349775e 3174 cp->scsi_nexus = ioaccel_handle;
dd0e19f3 3175 cp->Tag = (c->cmdindex << DIRECT_LOOKUP_SHIFT) |
c349775e
ST		 3176 DIRECT_LOOKUP_BIT;
3177 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
3178 memset(cp->cciss_lun, 0, sizeof(cp->cciss_lun));
3179 cp->cmd_priority_task_attr = 0;
3180
3181 /* fill in sg elements */
3182 cp->sg_count = (u8) use_sg;
3183
3184 cp->data_len = cpu_to_le32(total_len);
3185 cp->err_ptr = cpu_to_le64(c->busaddr +
3186 offsetof(struct io_accel2_cmd, error_data));
3187 cp->err_len = cpu_to_le32((u32) sizeof(cp->error_data));
3188
3189 enqueue_cmd_and_start_io(h, c);
3190 return 0;
3191}
3192
3193/*
3194 * Queue a command to the correct I/O accelerator path.
3195 */
3196static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3197 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3198 u8 *scsi3addr)
3199{
3200 if (h->transMethod & CFGTBL_Trans_io_accel1)
3201 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
3202 cdb, cdb_len, scsi3addr);
3203 else
3204 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
3205 cdb, cdb_len, scsi3addr);
3206}
3207
6b80b18f
ST		 3208static void raid_map_helper(struct raid_map_data *map,
3209 int offload_to_mirror, u32 *map_index, u32 *current_group)
3210{
3211 if (offload_to_mirror == 0) {
3212 /* use physical disk in the first mirrored group. */
3213 *map_index %= map->data_disks_per_row;
3214 return;
3215 }
3216 do {
3217 /* determine mirror group that *map_index indicates */
3218 *current_group = *map_index / map->data_disks_per_row;
3219 if (offload_to_mirror == *current_group)
3220 continue;
3221 if (*current_group < (map->layout_map_count - 1)) {
3222 /* select map index from next group */
3223 *map_index += map->data_disks_per_row;
3224 (*current_group)++;
3225 } else {
3226 /* select map index from first group */
3227 *map_index %= map->data_disks_per_row;
3228 *current_group = 0;
3229 }
3230 } while (offload_to_mirror != *current_group);
3231}
3232
283b4a9b
SC		 3233/*
3234 * Attempt to perform offload RAID mapping for a logical volume I/O.
3235 */
3236static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3237 struct CommandList *c)
3238{
3239 struct scsi_cmnd *cmd = c->scsi_cmd;
3240 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3241 struct raid_map_data *map = &dev->raid_map;
3242 struct raid_map_disk_data *dd = &map->data[0];
3243 int is_write = 0;
3244 u32 map_index;
3245 u64 first_block, last_block;
3246 u32 block_cnt;
3247 u32 blocks_per_row;
3248 u64 first_row, last_row;
3249 u32 first_row_offset, last_row_offset;
3250 u32 first_column, last_column;
6b80b18f
ST		 3251 u64 r0_first_row, r0_last_row;
3252 u32 r5or6_blocks_per_row;
3253 u64 r5or6_first_row, r5or6_last_row;
3254 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3255 u32 r5or6_first_column, r5or6_last_column;
3256 u32 total_disks_per_row;
3257 u32 stripesize;
3258 u32 first_group, last_group, current_group;
283b4a9b
SC		 3259 u32 map_row;
3260 u32 disk_handle;
3261 u64 disk_block;
3262 u32 disk_block_cnt;
3263 u8 cdb[16];
3264 u8 cdb_len;
3265#if BITS_PER_LONG == 32
3266 u64 tmpdiv;
3267#endif
6b80b18f 3268 int offload_to_mirror;
283b4a9b
SC		 3269
3270 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3271
3272 /* check for valid opcode, get LBA and block count */
3273 switch (cmd->cmnd[0]) {
3274 case WRITE_6:
3275 is_write = 1;
3276 case READ_6:
3277 first_block =
3278 (((u64) cmd->cmnd[2]) << 8) |
3279 cmd->cmnd[3];
3280 block_cnt = cmd->cmnd[4];
3281 break;
3282 case WRITE_10:
3283 is_write = 1;
3284 case READ_10:
3285 first_block =
3286 (((u64) cmd->cmnd[2]) << 24) |
3287 (((u64) cmd->cmnd[3]) << 16) |
3288 (((u64) cmd->cmnd[4]) << 8) |
3289 cmd->cmnd[5];
3290 block_cnt =
3291 (((u32) cmd->cmnd[7]) << 8) |
3292 cmd->cmnd[8];
3293 break;
3294 case WRITE_12:
3295 is_write = 1;
3296 case READ_12:
3297 first_block =
3298 (((u64) cmd->cmnd[2]) << 24) |
3299 (((u64) cmd->cmnd[3]) << 16) |
3300 (((u64) cmd->cmnd[4]) << 8) |
3301 cmd->cmnd[5];
3302 block_cnt =
3303 (((u32) cmd->cmnd[6]) << 24) |
3304 (((u32) cmd->cmnd[7]) << 16) |
3305 (((u32) cmd->cmnd[8]) << 8) |
3306 cmd->cmnd[9];
3307 break;
3308 case WRITE_16:
3309 is_write = 1;
3310 case READ_16:
3311 first_block =
3312 (((u64) cmd->cmnd[2]) << 56) |
3313 (((u64) cmd->cmnd[3]) << 48) |
3314 (((u64) cmd->cmnd[4]) << 40) |
3315 (((u64) cmd->cmnd[5]) << 32) |
3316 (((u64) cmd->cmnd[6]) << 24) |
3317 (((u64) cmd->cmnd[7]) << 16) |
3318 (((u64) cmd->cmnd[8]) << 8) |
3319 cmd->cmnd[9];
3320 block_cnt =
3321 (((u32) cmd->cmnd[10]) << 24) |
3322 (((u32) cmd->cmnd[11]) << 16) |
3323 (((u32) cmd->cmnd[12]) << 8) |
3324 cmd->cmnd[13];
3325 break;
3326 default:
3327 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3328 }
3329 BUG_ON(block_cnt == 0);
3330 last_block = first_block + block_cnt - 1;
3331
3332 /* check for write to non-RAID-0 */
3333 if (is_write && dev->raid_level != 0)
3334 return IO_ACCEL_INELIGIBLE;
3335
3336 /* check for invalid block or wraparound */
3337 if (last_block >= map->volume_blk_cnt || last_block < first_block)
3338 return IO_ACCEL_INELIGIBLE;
3339
3340 /* calculate stripe information for the request */
3341 blocks_per_row = map->data_disks_per_row * map->strip_size;
3342#if BITS_PER_LONG == 32
3343 tmpdiv = first_block;
3344 (void) do_div(tmpdiv, blocks_per_row);
3345 first_row = tmpdiv;
3346 tmpdiv = last_block;
3347 (void) do_div(tmpdiv, blocks_per_row);
3348 last_row = tmpdiv;
3349 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3350 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3351 tmpdiv = first_row_offset;
3352 (void) do_div(tmpdiv, map->strip_size);
3353 first_column = tmpdiv;
3354 tmpdiv = last_row_offset;
3355 (void) do_div(tmpdiv, map->strip_size);
3356 last_column = tmpdiv;
3357#else
3358 first_row = first_block / blocks_per_row;
3359 last_row = last_block / blocks_per_row;
3360 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3361 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3362 first_column = first_row_offset / map->strip_size;
3363 last_column = last_row_offset / map->strip_size;
3364#endif
3365
3366 /* if this isn't a single row/column then give to the controller */
3367 if ((first_row != last_row) || (first_column != last_column))
3368 return IO_ACCEL_INELIGIBLE;
3369
3370 /* proceeding with driver mapping */
6b80b18f
ST		 3371 total_disks_per_row = map->data_disks_per_row +
3372 map->metadata_disks_per_row;
283b4a9b
SC		 3373 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3374 map->row_cnt;
6b80b18f
ST		 3375 map_index = (map_row * total_disks_per_row) + first_column;
3376
3377 switch (dev->raid_level) {
3378 case HPSA_RAID_0:
3379 break; /* nothing special to do */
3380 case HPSA_RAID_1:
3381 /* Handles load balance across RAID 1 members.
3382 * (2-drive R1 and R10 with even # of drives.)
3383 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 3384 */
6b80b18f 3385 BUG_ON(map->layout_map_count != 2);
283b4a9b
SC		 3386 if (dev->offload_to_mirror)
3387 map_index += map->data_disks_per_row;
3388 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 3389 break;
3390 case HPSA_RAID_ADM:
3391 /* Handles N-way mirrors (R1-ADM)
3392 * and R10 with # of drives divisible by 3.)
3393 */
3394 BUG_ON(map->layout_map_count != 3);
3395
3396 offload_to_mirror = dev->offload_to_mirror;
3397 raid_map_helper(map, offload_to_mirror,
3398 &map_index, &current_group);
3399 /* set mirror group to use next time */
3400 offload_to_mirror =
3401 (offload_to_mirror >= map->layout_map_count - 1)
3402 ? 0 : offload_to_mirror + 1;
3403 /* FIXME: remove after debug/dev */
3404 BUG_ON(offload_to_mirror >= map->layout_map_count);
3405 dev_warn(&h->pdev->dev,
3406 "DEBUG: Using physical disk map index %d from mirror group %d\n",
3407 map_index, offload_to_mirror);
3408 dev->offload_to_mirror = offload_to_mirror;
3409 /* Avoid direct use of dev->offload_to_mirror within this
3410 * function since multiple threads might simultaneously
3411 * increment it beyond the range of dev->layout_map_count -1.
3412 */
3413 break;
3414 case HPSA_RAID_5:
3415 case HPSA_RAID_6:
3416 if (map->layout_map_count <= 1)
3417 break;
3418
3419 /* Verify first and last block are in same RAID group */
3420 r5or6_blocks_per_row =
3421 map->strip_size * map->data_disks_per_row;
3422 BUG_ON(r5or6_blocks_per_row == 0);
3423 stripesize = r5or6_blocks_per_row * map->layout_map_count;
3424#if BITS_PER_LONG == 32
3425 tmpdiv = first_block;
3426 first_group = do_div(tmpdiv, stripesize);
3427 tmpdiv = first_group;
3428 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3429 first_group = tmpdiv;
3430 tmpdiv = last_block;
3431 last_group = do_div(tmpdiv, stripesize);
3432 tmpdiv = last_group;
3433 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3434 last_group = tmpdiv;
3435#else
3436 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
3437 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
3438 if (first_group != last_group)
3439#endif
3440 return IO_ACCEL_INELIGIBLE;
3441
3442 /* Verify request is in a single row of RAID 5/6 */
3443#if BITS_PER_LONG == 32
3444 tmpdiv = first_block;
3445 (void) do_div(tmpdiv, stripesize);
3446 first_row = r5or6_first_row = r0_first_row = tmpdiv;
3447 tmpdiv = last_block;
3448 (void) do_div(tmpdiv, stripesize);
3449 r5or6_last_row = r0_last_row = tmpdiv;
3450#else
3451 first_row = r5or6_first_row = r0_first_row =
3452 first_block / stripesize;
3453 r5or6_last_row = r0_last_row = last_block / stripesize;
3454#endif
3455 if (r5or6_first_row != r5or6_last_row)
3456 return IO_ACCEL_INELIGIBLE;
3457
3458
3459 /* Verify request is in a single column */
3460#if BITS_PER_LONG == 32
3461 tmpdiv = first_block;
3462 first_row_offset = do_div(tmpdiv, stripesize);
3463 tmpdiv = first_row_offset;
3464 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
3465 r5or6_first_row_offset = first_row_offset;
3466 tmpdiv = last_block;
3467 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
3468 tmpdiv = r5or6_last_row_offset;
3469 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
3470 tmpdiv = r5or6_first_row_offset;
3471 (void) do_div(tmpdiv, map->strip_size);
3472 first_column = r5or6_first_column = tmpdiv;
3473 tmpdiv = r5or6_last_row_offset;
3474 (void) do_div(tmpdiv, map->strip_size);
3475 r5or6_last_column = tmpdiv;
3476#else
3477 first_row_offset = r5or6_first_row_offset =
3478 (u32)((first_block % stripesize) %
3479 r5or6_blocks_per_row);
3480
3481 r5or6_last_row_offset =
3482 (u32)((last_block % stripesize) %
3483 r5or6_blocks_per_row);
3484
3485 first_column = r5or6_first_column =
3486 r5or6_first_row_offset / map->strip_size;
3487 r5or6_last_column =
3488 r5or6_last_row_offset / map->strip_size;
3489#endif
3490 if (r5or6_first_column != r5or6_last_column)
3491 return IO_ACCEL_INELIGIBLE;
3492
3493 /* Request is eligible */
3494 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3495 map->row_cnt;
3496
3497 map_index = (first_group *
3498 (map->row_cnt * total_disks_per_row)) +
3499 (map_row * total_disks_per_row) + first_column;
3500 break;
3501 default:
3502 return IO_ACCEL_INELIGIBLE;
283b4a9b 3503 }
6b80b18f 3504
283b4a9b
SC		 3505 disk_handle = dd[map_index].ioaccel_handle;
3506 disk_block = map->disk_starting_blk + (first_row * map->strip_size) +
3507 (first_row_offset - (first_column * map->strip_size));
3508 disk_block_cnt = block_cnt;
3509
3510 /* handle differing logical/physical block sizes */
3511 if (map->phys_blk_shift) {
3512 disk_block <<= map->phys_blk_shift;
3513 disk_block_cnt <<= map->phys_blk_shift;
3514 }
3515 BUG_ON(disk_block_cnt > 0xffff);
3516
3517 /* build the new CDB for the physical disk I/O */
3518 if (disk_block > 0xffffffff) {
3519 cdb[0] = is_write ? WRITE_16 : READ_16;
3520 cdb[1] = 0;
3521 cdb[2] = (u8) (disk_block >> 56);
3522 cdb[3] = (u8) (disk_block >> 48);
3523 cdb[4] = (u8) (disk_block >> 40);
3524 cdb[5] = (u8) (disk_block >> 32);
3525 cdb[6] = (u8) (disk_block >> 24);
3526 cdb[7] = (u8) (disk_block >> 16);
3527 cdb[8] = (u8) (disk_block >> 8);
3528 cdb[9] = (u8) (disk_block);
3529 cdb[10] = (u8) (disk_block_cnt >> 24);
3530 cdb[11] = (u8) (disk_block_cnt >> 16);
3531 cdb[12] = (u8) (disk_block_cnt >> 8);
3532 cdb[13] = (u8) (disk_block_cnt);
3533 cdb[14] = 0;
3534 cdb[15] = 0;
3535 cdb_len = 16;
3536 } else {
3537 cdb[0] = is_write ? WRITE_10 : READ_10;
3538 cdb[1] = 0;
3539 cdb[2] = (u8) (disk_block >> 24);
3540 cdb[3] = (u8) (disk_block >> 16);
3541 cdb[4] = (u8) (disk_block >> 8);
3542 cdb[5] = (u8) (disk_block);
3543 cdb[6] = 0;
3544 cdb[7] = (u8) (disk_block_cnt >> 8);
3545 cdb[8] = (u8) (disk_block_cnt);
3546 cdb[9] = 0;
3547 cdb_len = 10;
3548 }
3549 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3550 dev->scsi3addr);
3551}
3552
f281233d 3553static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
edd16368
SC		 3554 void (*done)(struct scsi_cmnd *))
3555{
3556 struct ctlr_info *h;
3557 struct hpsa_scsi_dev_t *dev;
3558 unsigned char scsi3addr[8];
3559 struct CommandList *c;
3560 unsigned long flags;
283b4a9b 3561 int rc = 0;
edd16368
SC		 3562
3563 /* Get the ptr to our adapter structure out of cmd->host. */
3564 h = sdev_to_hba(cmd->device);
3565 dev = cmd->device->hostdata;
3566 if (!dev) {
3567 cmd->result = DID_NO_CONNECT << 16;
3568 done(cmd);
3569 return 0;
3570 }
3571 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3572
edd16368 3573 spin_lock_irqsave(&h->lock, flags);
a0c12413
SC		 3574 if (unlikely(h->lockup_detected)) {
3575 spin_unlock_irqrestore(&h->lock, flags);
3576 cmd->result = DID_ERROR << 16;
3577 done(cmd);
3578 return 0;
3579 }
edd16368 3580 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 3581 c = cmd_alloc(h);
edd16368
SC		 3582 if (c == NULL) { /* trouble... */
3583 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
3584 return SCSI_MLQUEUE_HOST_BUSY;
3585 }
3586
3587 /* Fill in the command list header */
3588
3589 cmd->scsi_done = done; /* save this for use by completion code */
3590
3591 /* save c in case we have to abort it */
3592 cmd->host_scribble = (unsigned char *) c;
3593
3594 c->cmd_type = CMD_SCSI;
3595 c->scsi_cmd = cmd;
e1f7de0c 3596
283b4a9b
SC		 3597 /* Call alternate submit routine for I/O accelerated commands.
3598 * Retries always go down the normal I/O path.
3599 */
3600 if (likely(cmd->retries == 0 &&
da0697bd
ST		 3601 cmd->request->cmd_type == REQ_TYPE_FS &&
3602 h->acciopath_status)) {
283b4a9b
SC		 3603 if (dev->offload_enabled) {
3604 rc = hpsa_scsi_ioaccel_raid_map(h, c);
3605 if (rc == 0)
3606 return 0; /* Sent on ioaccel path */
3607 if (rc < 0) { /* scsi_dma_map failed. */
3608 cmd_free(h, c);
3609 return SCSI_MLQUEUE_HOST_BUSY;
3610 }
3611 } else if (dev->ioaccel_handle) {
3612 rc = hpsa_scsi_ioaccel_direct_map(h, c);
3613 if (rc == 0)
3614 return 0; /* Sent on direct map path */
3615 if (rc < 0) { /* scsi_dma_map failed. */
3616 cmd_free(h, c);
3617 return SCSI_MLQUEUE_HOST_BUSY;
3618 }
3619 }
3620 }
e1f7de0c 3621
edd16368
SC		 3622 c->Header.ReplyQueue = 0; /* unused in simple mode */
3623 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
303932fd
DB		 3624 c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
3625 c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
edd16368
SC		 3626
3627 /* Fill in the request block... */
3628
3629 c->Request.Timeout = 0;
3630 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
3631 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
3632 c->Request.CDBLen = cmd->cmd_len;
3633 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
3634 c->Request.Type.Type = TYPE_CMD;
3635 c->Request.Type.Attribute = ATTR_SIMPLE;
3636 switch (cmd->sc_data_direction) {
3637 case DMA_TO_DEVICE:
3638 c->Request.Type.Direction = XFER_WRITE;
3639 break;
3640 case DMA_FROM_DEVICE:
3641 c->Request.Type.Direction = XFER_READ;
3642 break;
3643 case DMA_NONE:
3644 c->Request.Type.Direction = XFER_NONE;
3645 break;
3646 case DMA_BIDIRECTIONAL:
3647 /* This can happen if a buggy application does a scsi passthru
3648 * and sets both inlen and outlen to non-zero. ( see
3649 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
3650 */
3651
3652 c->Request.Type.Direction = XFER_RSVD;
3653 /* This is technically wrong, and hpsa controllers should
3654 * reject it with CMD_INVALID, which is the most correct
3655 * response, but non-fibre backends appear to let it
3656 * slide by, and give the same results as if this field
3657 * were set correctly. Either way is acceptable for
3658 * our purposes here.
3659 */
3660
3661 break;
3662
3663 default:
3664 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3665 cmd->sc_data_direction);
3666 BUG();
3667 break;
3668 }
3669
33a2ffce 3670 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 3671 cmd_free(h, c);
3672 return SCSI_MLQUEUE_HOST_BUSY;
3673 }
3674 enqueue_cmd_and_start_io(h, c);
3675 /* the cmd'll come back via intr handler in complete_scsi_command() */
3676 return 0;
3677}
3678
f281233d
JG		 3679static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
3680
5f389360
SC		 3681static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
3682{
3683 unsigned long flags;
3684
3685 /*
3686 * Don't let rescans be initiated on a controller known
3687 * to be locked up. If the controller locks up *during*
3688 * a rescan, that thread is probably hosed, but at least
3689 * we can prevent new rescan threads from piling up on a
3690 * locked up controller.
3691 */
3692 spin_lock_irqsave(&h->lock, flags);
3693 if (unlikely(h->lockup_detected)) {
3694 spin_unlock_irqrestore(&h->lock, flags);
3695 spin_lock_irqsave(&h->scan_lock, flags);
3696 h->scan_finished = 1;
3697 wake_up_all(&h->scan_wait_queue);
3698 spin_unlock_irqrestore(&h->scan_lock, flags);
3699 return 1;
3700 }
3701 spin_unlock_irqrestore(&h->lock, flags);
3702 return 0;
3703}
3704
a08a8471
SC		 3705static void hpsa_scan_start(struct Scsi_Host *sh)
3706{
3707 struct ctlr_info *h = shost_to_hba(sh);
3708 unsigned long flags;
3709
5f389360
SC		 3710 if (do_not_scan_if_controller_locked_up(h))
3711 return;
3712
a08a8471
SC		 3713 /* wait until any scan already in progress is finished. */
3714 while (1) {
3715 spin_lock_irqsave(&h->scan_lock, flags);
3716 if (h->scan_finished)
3717 break;
3718 spin_unlock_irqrestore(&h->scan_lock, flags);
3719 wait_event(h->scan_wait_queue, h->scan_finished);
3720 /* Note: We don't need to worry about a race between this
3721 * thread and driver unload because the midlayer will
3722 * have incremented the reference count, so unload won't
3723 * happen if we're in here.
3724 */
3725 }
3726 h->scan_finished = 0; /* mark scan as in progress */
3727 spin_unlock_irqrestore(&h->scan_lock, flags);
3728
5f389360
SC		 3729 if (do_not_scan_if_controller_locked_up(h))
3730 return;
3731
a08a8471
SC		 3732 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
3733
3734 spin_lock_irqsave(&h->scan_lock, flags);
3735 h->scan_finished = 1; /* mark scan as finished. */
3736 wake_up_all(&h->scan_wait_queue);
3737 spin_unlock_irqrestore(&h->scan_lock, flags);
3738}
3739
3740static int hpsa_scan_finished(struct Scsi_Host *sh,
3741 unsigned long elapsed_time)
3742{
3743 struct ctlr_info *h = shost_to_hba(sh);
3744 unsigned long flags;
3745 int finished;
3746
3747 spin_lock_irqsave(&h->scan_lock, flags);
3748 finished = h->scan_finished;
3749 spin_unlock_irqrestore(&h->scan_lock, flags);
3750 return finished;
3751}
3752
667e23d4
SC		 3753static int hpsa_change_queue_depth(struct scsi_device *sdev,
3754 int qdepth, int reason)
3755{
3756 struct ctlr_info *h = sdev_to_hba(sdev);
3757
3758 if (reason != SCSI_QDEPTH_DEFAULT)
3759 return -ENOTSUPP;
3760
3761 if (qdepth < 1)
3762 qdepth = 1;
3763 else
3764 if (qdepth > h->nr_cmds)
3765 qdepth = h->nr_cmds;
3766 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
3767 return sdev->queue_depth;
3768}
3769
edd16368
SC		 3770static void hpsa_unregister_scsi(struct ctlr_info *h)
3771{
3772 /* we are being forcibly unloaded, and may not refuse. */
3773 scsi_remove_host(h->scsi_host);
3774 scsi_host_put(h->scsi_host);
3775 h->scsi_host = NULL;
3776}
3777
3778static int hpsa_register_scsi(struct ctlr_info *h)
3779{
b705690d
SC		 3780 struct Scsi_Host *sh;
3781 int error;
edd16368 3782
b705690d
SC		 3783 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
3784 if (sh == NULL)
3785 goto fail;
3786
3787 sh->io_port = 0;
3788 sh->n_io_port = 0;
3789 sh->this_id = -1;
3790 sh->max_channel = 3;
3791 sh->max_cmd_len = MAX_COMMAND_SIZE;
3792 sh->max_lun = HPSA_MAX_LUN;
3793 sh->max_id = HPSA_MAX_LUN;
3794 sh->can_queue = h->nr_cmds;
3795 sh->cmd_per_lun = h->nr_cmds;
3796 sh->sg_tablesize = h->maxsgentries;
3797 h->scsi_host = sh;
3798 sh->hostdata[0] = (unsigned long) h;
3799 sh->irq = h->intr[h->intr_mode];
3800 sh->unique_id = sh->irq;
3801 error = scsi_add_host(sh, &h->pdev->dev);
3802 if (error)
3803 goto fail_host_put;
3804 scsi_scan_host(sh);
3805 return 0;
3806
3807 fail_host_put:
3808 dev_err(&h->pdev->dev, "%s: scsi_add_host"
3809 " failed for controller %d\n", __func__, h->ctlr);
3810 scsi_host_put(sh);
3811 return error;
3812 fail:
3813 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
3814 " failed for controller %d\n", __func__, h->ctlr);
3815 return -ENOMEM;
edd16368
SC		 3816}
3817
3818static int wait_for_device_to_become_ready(struct ctlr_info *h,
3819 unsigned char lunaddr[])
3820{
3821 int rc = 0;
3822 int count = 0;
3823 int waittime = 1; /* seconds */
3824 struct CommandList *c;
3825
3826 c = cmd_special_alloc(h);
3827 if (!c) {
3828 dev_warn(&h->pdev->dev, "out of memory in "
3829 "wait_for_device_to_become_ready.\n");
3830 return IO_ERROR;
3831 }
3832
3833 /* Send test unit ready until device ready, or give up. */
3834 while (count < HPSA_TUR_RETRY_LIMIT) {
3835
3836 /* Wait for a bit. do this first, because if we send
3837 * the TUR right away, the reset will just abort it.
3838 */
3839 msleep(1000 * waittime);
3840 count++;
3841
3842 /* Increase wait time with each try, up to a point. */
3843 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
3844 waittime = waittime * 2;
3845
a2dac136
SC		 3846 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
3847 (void) fill_cmd(c, TEST_UNIT_READY, h,
3848 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 3849 hpsa_scsi_do_simple_cmd_core(h, c);
3850 /* no unmap needed here because no data xfer. */
3851
3852 if (c->err_info->CommandStatus == CMD_SUCCESS)
3853 break;
3854
3855 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
3856 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
3857 (c->err_info->SenseInfo[2] == NO_SENSE ||
3858 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
3859 break;
3860
3861 dev_warn(&h->pdev->dev, "waiting %d secs "
3862 "for device to become ready.\n", waittime);
3863 rc = 1; /* device not ready. */
3864 }
3865
3866 if (rc)
3867 dev_warn(&h->pdev->dev, "giving up on device.\n");
3868 else
3869 dev_warn(&h->pdev->dev, "device is ready.\n");
3870
3871 cmd_special_free(h, c);
3872 return rc;
3873}
3874
3875/* Need at least one of these error handlers to keep ../scsi/hosts.c from
3876 * complaining. Doing a host- or bus-reset can't do anything good here.
3877 */
3878static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
3879{
3880 int rc;
3881 struct ctlr_info *h;
3882 struct hpsa_scsi_dev_t *dev;
3883
3884 /* find the controller to which the command to be aborted was sent */
3885 h = sdev_to_hba(scsicmd->device);
3886 if (h == NULL) /* paranoia */
3887 return FAILED;
edd16368
SC		 3888 dev = scsicmd->device->hostdata;
3889 if (!dev) {
3890 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
3891 "device lookup failed.\n");
3892 return FAILED;
3893 }
d416b0c7
SC		 3894 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
3895 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 3896 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 3897 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 3898 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
3899 return SUCCESS;
3900
3901 dev_warn(&h->pdev->dev, "resetting device failed.\n");
3902 return FAILED;
3903}
3904
6cba3f19
SC		 3905static void swizzle_abort_tag(u8 *tag)
3906{
3907 u8 original_tag[8];
3908
3909 memcpy(original_tag, tag, 8);
3910 tag[0] = original_tag[3];
3911 tag[1] = original_tag[2];
3912 tag[2] = original_tag[1];
3913 tag[3] = original_tag[0];
3914 tag[4] = original_tag[7];
3915 tag[5] = original_tag[6];
3916 tag[6] = original_tag[5];
3917 tag[7] = original_tag[4];
3918}
3919
17eb87d2
ST		 3920static void hpsa_get_tag(struct ctlr_info *h,
3921 struct CommandList *c, u32 *taglower, u32 *tagupper)
3922{
3923 if (c->cmd_type == CMD_IOACCEL1) {
3924 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
3925 &h->ioaccel_cmd_pool[c->cmdindex];
3926 *tagupper = cm1->Tag.upper;
3927 *taglower = cm1->Tag.lower;
54b6e9e9
ST		 3928 return;
3929 }
3930 if (c->cmd_type == CMD_IOACCEL2) {
3931 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
3932 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 3933 /* upper tag not used in ioaccel2 mode */
3934 memset(tagupper, 0, sizeof(*tagupper));
3935 *taglower = cm2->Tag;
54b6e9e9 3936 return;
17eb87d2 3937 }
54b6e9e9
ST		 3938 *tagupper = c->Header.Tag.upper;
3939 *taglower = c->Header.Tag.lower;
17eb87d2
ST		 3940}
3941
54b6e9e9 3942
75167d2c 3943static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 3944 struct CommandList *abort, int swizzle)
75167d2c
SC		 3945{
3946 int rc = IO_OK;
3947 struct CommandList *c;
3948 struct ErrorInfo *ei;
17eb87d2 3949 u32 tagupper, taglower;
75167d2c
SC		 3950
3951 c = cmd_special_alloc(h);
3952 if (c == NULL) { /* trouble... */
3953 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
3954 return -ENOMEM;
3955 }
3956
a2dac136
SC		 3957 /* fill_cmd can't fail here, no buffer to map */
3958 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
3959 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 3960 if (swizzle)
3961 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 3962 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 3963 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 3964 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 3965 __func__, tagupper, taglower);
75167d2c
SC		 3966 /* no unmap needed here because no data xfer. */
3967
3968 ei = c->err_info;
3969 switch (ei->CommandStatus) {
3970 case CMD_SUCCESS:
3971 break;
3972 case CMD_UNABORTABLE: /* Very common, don't make noise. */
3973 rc = -1;
3974 break;
3975 default:
3976 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 3977 __func__, tagupper, taglower);
75167d2c
SC		 3978 hpsa_scsi_interpret_error(c);
3979 rc = -1;
3980 break;
3981 }
3982 cmd_special_free(h, c);
dd0e19f3
ST		 3983 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
3984 __func__, tagupper, taglower);
75167d2c
SC		 3985 return rc;
3986}
3987
3988/*
3989 * hpsa_find_cmd_in_queue
3990 *
3991 * Used to determine whether a command (find) is still present
3992 * in queue_head. Optionally excludes the last element of queue_head.
3993 *
3994 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
3995 * not yet been submitted, and so can be aborted by the driver without
3996 * sending an abort to the hardware.
3997 *
3998 * Returns pointer to command if found in queue, NULL otherwise.
3999 */
4000static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
4001 struct scsi_cmnd *find, struct list_head *queue_head)
4002{
4003 unsigned long flags;
4004 struct CommandList *c = NULL; /* ptr into cmpQ */
4005
4006 if (!find)
4007 return 0;
4008 spin_lock_irqsave(&h->lock, flags);
4009 list_for_each_entry(c, queue_head, list) {
4010 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
4011 continue;
4012 if (c->scsi_cmd == find) {
4013 spin_unlock_irqrestore(&h->lock, flags);
4014 return c;
4015 }
4016 }
4017 spin_unlock_irqrestore(&h->lock, flags);
4018 return NULL;
4019}
4020
6cba3f19
SC		 4021static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
4022 u8 *tag, struct list_head *queue_head)
4023{
4024 unsigned long flags;
4025 struct CommandList *c;
4026
4027 spin_lock_irqsave(&h->lock, flags);
4028 list_for_each_entry(c, queue_head, list) {
4029 if (memcmp(&c->Header.Tag, tag, 8) != 0)
4030 continue;
4031 spin_unlock_irqrestore(&h->lock, flags);
4032 return c;
4033 }
4034 spin_unlock_irqrestore(&h->lock, flags);
4035 return NULL;
4036}
4037
54b6e9e9
ST		 4038/* ioaccel2 path firmware cannot handle abort task requests.
4039 * Change abort requests to physical target reset, and send to the
4040 * address of the physical disk used for the ioaccel 2 command.
4041 * Return 0 on success (IO_OK)
4042 * -1 on failure
4043 */
4044
4045static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
4046 unsigned char *scsi3addr, struct CommandList *abort)
4047{
4048 int rc = IO_OK;
4049 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4050 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4051 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4052 unsigned char *psa = &phys_scsi3addr[0];
4053
4054 /* Get a pointer to the hpsa logical device. */
4055 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
4056 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4057 if (dev == NULL) {
4058 dev_warn(&h->pdev->dev,
4059 "Cannot abort: no device pointer for command.\n");
4060 return -1; /* not abortable */
4061 }
4062
4063 if (!dev->offload_enabled) {
4064 dev_warn(&h->pdev->dev,
4065 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4066 return -1; /* not abortable */
4067 }
4068
4069 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4070 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4071 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4072 return -1; /* not abortable */
4073 }
4074
4075 /* send the reset */
4076 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
4077 if (rc != 0) {
4078 dev_warn(&h->pdev->dev,
4079 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4080 psa[0], psa[1], psa[2], psa[3],
4081 psa[4], psa[5], psa[6], psa[7]);
4082 return rc; /* failed to reset */
4083 }
4084
4085 /* wait for device to recover */
4086 if (wait_for_device_to_become_ready(h, psa) != 0) {
4087 dev_warn(&h->pdev->dev,
4088 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4089 psa[0], psa[1], psa[2], psa[3],
4090 psa[4], psa[5], psa[6], psa[7]);
4091 return -1; /* failed to recover */
4092 }
4093
4094 /* device recovered */
4095 dev_info(&h->pdev->dev,
4096 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4097 psa[0], psa[1], psa[2], psa[3],
4098 psa[4], psa[5], psa[6], psa[7]);
4099
4100 return rc; /* success */
4101}
4102
6cba3f19
SC		 4103/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
4104 * tell which kind we're dealing with, so we send the abort both ways. There
4105 * shouldn't be any collisions between swizzled and unswizzled tags due to the
4106 * way we construct our tags but we check anyway in case the assumptions which
4107 * make this true someday become false.
4108 */
4109static int hpsa_send_abort_both_ways(struct ctlr_info *h,
4110 unsigned char *scsi3addr, struct CommandList *abort)
4111{
4112 u8 swizzled_tag[8];
4113 struct CommandList *c;
4114 int rc = 0, rc2 = 0;
4115
54b6e9e9
ST		 4116 /* ioccelerator mode 2 commands should be aborted via the
4117 * accelerated path, since RAID path is unaware of these commands,
4118 * but underlying firmware can't handle abort TMF.
4119 * Change abort to physical device reset.
4120 */
4121 if (abort->cmd_type == CMD_IOACCEL2)
4122 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
4123
6cba3f19
SC		 4124 /* we do not expect to find the swizzled tag in our queue, but
4125 * check anyway just to be sure the assumptions which make this
4126 * the case haven't become wrong.
4127 */
4128 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
4129 swizzle_abort_tag(swizzled_tag);
4130 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
4131 if (c != NULL) {
4132 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
4133 return hpsa_send_abort(h, scsi3addr, abort, 0);
4134 }
4135 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
4136
4137 /* if the command is still in our queue, we can't conclude that it was
4138 * aborted (it might have just completed normally) but in any case
4139 * we don't need to try to abort it another way.
4140 */
4141 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
4142 if (c)
4143 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
4144 return rc && rc2;
4145}
4146
75167d2c
SC		 4147/* Send an abort for the specified command.
4148 * If the device and controller support it,
4149 * send a task abort request.
4150 */
4151static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
4152{
4153
4154 int i, rc;
4155 struct ctlr_info *h;
4156 struct hpsa_scsi_dev_t *dev;
4157 struct CommandList *abort; /* pointer to command to be aborted */
4158 struct CommandList *found;
4159 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
4160 char msg[256]; /* For debug messaging. */
4161 int ml = 0;
17eb87d2 4162 u32 tagupper, taglower;
75167d2c
SC		 4163
4164 /* Find the controller of the command to be aborted */
4165 h = sdev_to_hba(sc->device);
4166 if (WARN(h == NULL,
4167 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
4168 return FAILED;
4169
4170 /* Check that controller supports some kind of task abort */
4171 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
4172 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
4173 return FAILED;
4174
4175 memset(msg, 0, sizeof(msg));
4176 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ",
4177 h->scsi_host->host_no, sc->device->channel,
4178 sc->device->id, sc->device->lun);
4179
4180 /* Find the device of the command to be aborted */
4181 dev = sc->device->hostdata;
4182 if (!dev) {
4183 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
4184 msg);
4185 return FAILED;
4186 }
4187
4188 /* Get SCSI command to be aborted */
4189 abort = (struct CommandList *) sc->host_scribble;
4190 if (abort == NULL) {
4191 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
4192 msg);
4193 return FAILED;
4194 }
17eb87d2
ST		 4195 hpsa_get_tag(h, abort, &taglower, &tagupper);
4196 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 4197 as = (struct scsi_cmnd *) abort->scsi_cmd;
4198 if (as != NULL)
4199 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
4200 as->cmnd[0], as->serial_number);
4201 dev_dbg(&h->pdev->dev, "%s\n", msg);
4202 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
4203 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
4204
4205 /* Search reqQ to See if command is queued but not submitted,
4206 * if so, complete the command with aborted status and remove
4207 * it from the reqQ.
4208 */
4209 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
4210 if (found) {
4211 found->err_info->CommandStatus = CMD_ABORTED;
4212 finish_cmd(found);
4213 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
4214 msg);
4215 return SUCCESS;
4216 }
4217
4218 /* not in reqQ, if also not in cmpQ, must have already completed */
4219 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4220 if (!found) {
d6ebd0f7 4221 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 4222 msg);
4223 return SUCCESS;
4224 }
4225
4226 /*
4227 * Command is in flight, or possibly already completed
4228 * by the firmware (but not to the scsi mid layer) but we can't
4229 * distinguish which. Send the abort down.
4230 */
6cba3f19 4231 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 4232 if (rc != 0) {
4233 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
4234 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
4235 h->scsi_host->host_no,
4236 dev->bus, dev->target, dev->lun);
4237 return FAILED;
4238 }
4239 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
4240
4241 /* If the abort(s) above completed and actually aborted the
4242 * command, then the command to be aborted should already be
4243 * completed. If not, wait around a bit more to see if they
4244 * manage to complete normally.
4245 */
4246#define ABORT_COMPLETE_WAIT_SECS 30
4247 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
4248 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4249 if (!found)
4250 return SUCCESS;
4251 msleep(100);
4252 }
4253 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
4254 msg, ABORT_COMPLETE_WAIT_SECS);
4255 return FAILED;
4256}
4257
4258
edd16368
SC		 4259/*
4260 * For operations that cannot sleep, a command block is allocated at init,
4261 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4262 * which ones are free or in use. Lock must be held when calling this.
4263 * cmd_free() is the complement.
4264 */
4265static struct CommandList *cmd_alloc(struct ctlr_info *h)
4266{
4267 struct CommandList *c;
4268 int i;
4269 union u64bit temp64;
4270 dma_addr_t cmd_dma_handle, err_dma_handle;
e16a33ad 4271 unsigned long flags;
edd16368 4272
e16a33ad 4273 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4274 do {
4275 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
e16a33ad
MG		 4276 if (i == h->nr_cmds) {
4277 spin_unlock_irqrestore(&h->lock, flags);
edd16368 4278 return NULL;
e16a33ad 4279 }
edd16368
SC		 4280 } while (test_and_set_bit
4281 (i & (BITS_PER_LONG - 1),
4282 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
e16a33ad
MG		 4283 spin_unlock_irqrestore(&h->lock, flags);
4284
edd16368
SC		 4285 c = h->cmd_pool + i;
4286 memset(c, 0, sizeof(*c));
4287 cmd_dma_handle = h->cmd_pool_dhandle
4288 + i * sizeof(*c);
4289 c->err_info = h->errinfo_pool + i;
4290 memset(c->err_info, 0, sizeof(*c->err_info));
4291 err_dma_handle = h->errinfo_pool_dhandle
4292 + i * sizeof(*c->err_info);
edd16368
SC		 4293
4294 c->cmdindex = i;
4295
9e0fc764 4296 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4297 c->busaddr = (u32) cmd_dma_handle;
4298 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4299 c->ErrDesc.Addr.lower = temp64.val32.lower;
4300 c->ErrDesc.Addr.upper = temp64.val32.upper;
4301 c->ErrDesc.Len = sizeof(*c->err_info);
4302
4303 c->h = h;
4304 return c;
4305}
4306
4307/* For operations that can wait for kmalloc to possibly sleep,
4308 * this routine can be called. Lock need not be held to call
4309 * cmd_special_alloc. cmd_special_free() is the complement.
4310 */
4311static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
4312{
4313 struct CommandList *c;
4314 union u64bit temp64;
4315 dma_addr_t cmd_dma_handle, err_dma_handle;
4316
4317 c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
4318 if (c == NULL)
4319 return NULL;
4320 memset(c, 0, sizeof(*c));
4321
e1f7de0c 4322 c->cmd_type = CMD_SCSI;
edd16368
SC		 4323 c->cmdindex = -1;
4324
4325 c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
4326 &err_dma_handle);
4327
4328 if (c->err_info == NULL) {
4329 pci_free_consistent(h->pdev,
4330 sizeof(*c), c, cmd_dma_handle);
4331 return NULL;
4332 }
4333 memset(c->err_info, 0, sizeof(*c->err_info));
4334
9e0fc764 4335 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4336 c->busaddr = (u32) cmd_dma_handle;
4337 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4338 c->ErrDesc.Addr.lower = temp64.val32.lower;
4339 c->ErrDesc.Addr.upper = temp64.val32.upper;
4340 c->ErrDesc.Len = sizeof(*c->err_info);
4341
4342 c->h = h;
4343 return c;
4344}
4345
4346static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4347{
4348 int i;
e16a33ad 4349 unsigned long flags;
edd16368
SC		 4350
4351 i = c - h->cmd_pool;
e16a33ad 4352 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4353 clear_bit(i & (BITS_PER_LONG - 1),
4354 h->cmd_pool_bits + (i / BITS_PER_LONG));
e16a33ad 4355 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4356}
4357
4358static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
4359{
4360 union u64bit temp64;
4361
4362 temp64.val32.lower = c->ErrDesc.Addr.lower;
4363 temp64.val32.upper = c->ErrDesc.Addr.upper;
4364 pci_free_consistent(h->pdev, sizeof(*c->err_info),
4365 c->err_info, (dma_addr_t) temp64.val);
4366 pci_free_consistent(h->pdev, sizeof(*c),
d896f3f3 4367 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
edd16368
SC		 4368}
4369
4370#ifdef CONFIG_COMPAT
4371
edd16368
SC		 4372static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
4373{
4374 IOCTL32_Command_struct __user *arg32 =
4375 (IOCTL32_Command_struct __user *) arg;
4376 IOCTL_Command_struct arg64;
4377 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
4378 int err;
4379 u32 cp;
4380
938abd84 4381 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4382 err = 0;
4383 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4384 sizeof(arg64.LUN_info));
4385 err |= copy_from_user(&arg64.Request, &arg32->Request,
4386 sizeof(arg64.Request));
4387 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4388 sizeof(arg64.error_info));
4389 err |= get_user(arg64.buf_size, &arg32->buf_size);
4390 err |= get_user(cp, &arg32->buf);
4391 arg64.buf = compat_ptr(cp);
4392 err |= copy_to_user(p, &arg64, sizeof(arg64));
4393
4394 if (err)
4395 return -EFAULT;
4396
e39eeaed 4397 err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
edd16368
SC		 4398 if (err)
4399 return err;
4400 err |= copy_in_user(&arg32->error_info, &p->error_info,
4401 sizeof(arg32->error_info));
4402 if (err)
4403 return -EFAULT;
4404 return err;
4405}
4406
4407static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
4408 int cmd, void *arg)
4409{
4410 BIG_IOCTL32_Command_struct __user *arg32 =
4411 (BIG_IOCTL32_Command_struct __user *) arg;
4412 BIG_IOCTL_Command_struct arg64;
4413 BIG_IOCTL_Command_struct __user *p =
4414 compat_alloc_user_space(sizeof(arg64));
4415 int err;
4416 u32 cp;
4417
938abd84 4418 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4419 err = 0;
4420 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4421 sizeof(arg64.LUN_info));
4422 err |= copy_from_user(&arg64.Request, &arg32->Request,
4423 sizeof(arg64.Request));
4424 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4425 sizeof(arg64.error_info));
4426 err |= get_user(arg64.buf_size, &arg32->buf_size);
4427 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4428 err |= get_user(cp, &arg32->buf);
4429 arg64.buf = compat_ptr(cp);
4430 err |= copy_to_user(p, &arg64, sizeof(arg64));
4431
4432 if (err)
4433 return -EFAULT;
4434
e39eeaed 4435 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
edd16368
SC		 4436 if (err)
4437 return err;
4438 err |= copy_in_user(&arg32->error_info, &p->error_info,
4439 sizeof(arg32->error_info));
4440 if (err)
4441 return -EFAULT;
4442 return err;
4443}
71fe75a7
SC		 4444
4445static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
4446{
4447 switch (cmd) {
4448 case CCISS_GETPCIINFO:
4449 case CCISS_GETINTINFO:
4450 case CCISS_SETINTINFO:
4451 case CCISS_GETNODENAME:
4452 case CCISS_SETNODENAME:
4453 case CCISS_GETHEARTBEAT:
4454 case CCISS_GETBUSTYPES:
4455 case CCISS_GETFIRMVER:
4456 case CCISS_GETDRIVVER:
4457 case CCISS_REVALIDVOLS:
4458 case CCISS_DEREGDISK:
4459 case CCISS_REGNEWDISK:
4460 case CCISS_REGNEWD:
4461 case CCISS_RESCANDISK:
4462 case CCISS_GETLUNINFO:
4463 return hpsa_ioctl(dev, cmd, arg);
4464
4465 case CCISS_PASSTHRU32:
4466 return hpsa_ioctl32_passthru(dev, cmd, arg);
4467 case CCISS_BIG_PASSTHRU32:
4468 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4469
4470 default:
4471 return -ENOIOCTLCMD;
4472 }
4473}
edd16368
SC		 4474#endif
4475
4476static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4477{
4478 struct hpsa_pci_info pciinfo;
4479
4480 if (!argp)
4481 return -EINVAL;
4482 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4483 pciinfo.bus = h->pdev->bus->number;
4484 pciinfo.dev_fn = h->pdev->devfn;
4485 pciinfo.board_id = h->board_id;
4486 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4487 return -EFAULT;
4488 return 0;
4489}
4490
4491static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4492{
4493 DriverVer_type DriverVer;
4494 unsigned char vmaj, vmin, vsubmin;
4495 int rc;
4496
4497 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4498 &vmaj, &vmin, &vsubmin);
4499 if (rc != 3) {
4500 dev_info(&h->pdev->dev, "driver version string '%s' "
4501 "unrecognized.", HPSA_DRIVER_VERSION);
4502 vmaj = 0;
4503 vmin = 0;
4504 vsubmin = 0;
4505 }
4506 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4507 if (!argp)
4508 return -EINVAL;
4509 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4510 return -EFAULT;
4511 return 0;
4512}
4513
4514static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4515{
4516 IOCTL_Command_struct iocommand;
4517 struct CommandList *c;
4518 char *buff = NULL;
4519 union u64bit temp64;
c1f63c8f 4520 int rc = 0;
edd16368
SC		 4521
4522 if (!argp)
4523 return -EINVAL;
4524 if (!capable(CAP_SYS_RAWIO))
4525 return -EPERM;
4526 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4527 return -EFAULT;
4528 if ((iocommand.buf_size < 1) &&
4529 (iocommand.Request.Type.Direction != XFER_NONE)) {
4530 return -EINVAL;
4531 }
4532 if (iocommand.buf_size > 0) {
4533 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4534 if (buff == NULL)
4535 return -EFAULT;
b03a7771
SC		 4536 if (iocommand.Request.Type.Direction == XFER_WRITE) {
4537 /* Copy the data into the buffer we created */
4538 if (copy_from_user(buff, iocommand.buf,
4539 iocommand.buf_size)) {
c1f63c8f
SC		 4540 rc = -EFAULT;
4541 goto out_kfree;
b03a7771
SC		 4542 }
4543 } else {
4544 memset(buff, 0, iocommand.buf_size);
edd16368 4545 }
b03a7771 4546 }
edd16368
SC		 4547 c = cmd_special_alloc(h);
4548 if (c == NULL) {
c1f63c8f
SC		 4549 rc = -ENOMEM;
4550 goto out_kfree;
edd16368
SC		 4551 }
4552 /* Fill in the command type */
4553 c->cmd_type = CMD_IOCTL_PEND;
4554 /* Fill in Command Header */
4555 c->Header.ReplyQueue = 0; /* unused in simple mode */
4556 if (iocommand.buf_size > 0) { /* buffer to fill */
4557 c->Header.SGList = 1;
4558 c->Header.SGTotal = 1;
4559 } else { /* no buffers to fill */
4560 c->Header.SGList = 0;
4561 c->Header.SGTotal = 0;
4562 }
4563 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
4564 /* use the kernel address the cmd block for tag */
4565 c->Header.Tag.lower = c->busaddr;
4566
4567 /* Fill in Request block */
4568 memcpy(&c->Request, &iocommand.Request,
4569 sizeof(c->Request));
4570
4571 /* Fill in the scatter gather information */
4572 if (iocommand.buf_size > 0) {
4573 temp64.val = pci_map_single(h->pdev, buff,
4574 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4575 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4576 c->SG[0].Addr.lower = 0;
4577 c->SG[0].Addr.upper = 0;
4578 c->SG[0].Len = 0;
4579 rc = -ENOMEM;
4580 goto out;
4581 }
edd16368
SC		 4582 c->SG[0].Addr.lower = temp64.val32.lower;
4583 c->SG[0].Addr.upper = temp64.val32.upper;
4584 c->SG[0].Len = iocommand.buf_size;
e1d9cbfa 4585 c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/
edd16368 4586 }
a0c12413 4587 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 4588 if (iocommand.buf_size > 0)
4589 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4590 check_ioctl_unit_attention(h, c);
4591
4592 /* Copy the error information out */
4593 memcpy(&iocommand.error_info, c->err_info,
4594 sizeof(iocommand.error_info));
4595 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 4596 rc = -EFAULT;
4597 goto out;
edd16368 4598 }
b03a7771
SC		 4599 if (iocommand.Request.Type.Direction == XFER_READ &&
4600 iocommand.buf_size > 0) {
edd16368
SC		 4601 /* Copy the data out of the buffer we created */
4602 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 4603 rc = -EFAULT;
4604 goto out;
edd16368
SC		 4605 }
4606 }
c1f63c8f 4607out:
edd16368 4608 cmd_special_free(h, c);
c1f63c8f
SC		 4609out_kfree:
4610 kfree(buff);
4611 return rc;
edd16368
SC		 4612}
4613
4614static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4615{
4616 BIG_IOCTL_Command_struct *ioc;
4617 struct CommandList *c;
4618 unsigned char **buff = NULL;
4619 int *buff_size = NULL;
4620 union u64bit temp64;
4621 BYTE sg_used = 0;
4622 int status = 0;
4623 int i;
01a02ffc
SC		 4624 u32 left;
4625 u32 sz;
edd16368
SC		 4626 BYTE __user *data_ptr;
4627
4628 if (!argp)
4629 return -EINVAL;
4630 if (!capable(CAP_SYS_RAWIO))
4631 return -EPERM;
4632 ioc = (BIG_IOCTL_Command_struct *)
4633 kmalloc(sizeof(*ioc), GFP_KERNEL);
4634 if (!ioc) {
4635 status = -ENOMEM;
4636 goto cleanup1;
4637 }
4638 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
4639 status = -EFAULT;
4640 goto cleanup1;
4641 }
4642 if ((ioc->buf_size < 1) &&
4643 (ioc->Request.Type.Direction != XFER_NONE)) {
4644 status = -EINVAL;
4645 goto cleanup1;
4646 }
4647 /* Check kmalloc limits using all SGs */
4648 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
4649 status = -EINVAL;
4650 goto cleanup1;
4651 }
d66ae08b 4652 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 4653 status = -EINVAL;
4654 goto cleanup1;
4655 }
d66ae08b 4656 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 4657 if (!buff) {
4658 status = -ENOMEM;
4659 goto cleanup1;
4660 }
d66ae08b 4661 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 4662 if (!buff_size) {
4663 status = -ENOMEM;
4664 goto cleanup1;
4665 }
4666 left = ioc->buf_size;
4667 data_ptr = ioc->buf;
4668 while (left) {
4669 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
4670 buff_size[sg_used] = sz;
4671 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
4672 if (buff[sg_used] == NULL) {
4673 status = -ENOMEM;
4674 goto cleanup1;
4675 }
4676 if (ioc->Request.Type.Direction == XFER_WRITE) {
4677 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
4678 status = -ENOMEM;
4679 goto cleanup1;
4680 }
4681 } else
4682 memset(buff[sg_used], 0, sz);
4683 left -= sz;
4684 data_ptr += sz;
4685 sg_used++;
4686 }
4687 c = cmd_special_alloc(h);
4688 if (c == NULL) {
4689 status = -ENOMEM;
4690 goto cleanup1;
4691 }
4692 c->cmd_type = CMD_IOCTL_PEND;
4693 c->Header.ReplyQueue = 0;
b03a7771 4694 c->Header.SGList = c->Header.SGTotal = sg_used;
edd16368
SC		 4695 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
4696 c->Header.Tag.lower = c->busaddr;
4697 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
4698 if (ioc->buf_size > 0) {
4699 int i;
4700 for (i = 0; i < sg_used; i++) {
4701 temp64.val = pci_map_single(h->pdev, buff[i],
4702 buff_size[i], PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4703 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4704 c->SG[i].Addr.lower = 0;
4705 c->SG[i].Addr.upper = 0;
4706 c->SG[i].Len = 0;
4707 hpsa_pci_unmap(h->pdev, c, i,
4708 PCI_DMA_BIDIRECTIONAL);
4709 status = -ENOMEM;
e2d4a1f6 4710 goto cleanup0;
bcc48ffa 4711 }
edd16368
SC		 4712 c->SG[i].Addr.lower = temp64.val32.lower;
4713 c->SG[i].Addr.upper = temp64.val32.upper;
4714 c->SG[i].Len = buff_size[i];
e1d9cbfa 4715 c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST;
edd16368
SC		 4716 }
4717 }
a0c12413 4718 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 4719 if (sg_used)
4720 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4721 check_ioctl_unit_attention(h, c);
4722 /* Copy the error information out */
4723 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
4724 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 4725 status = -EFAULT;
e2d4a1f6 4726 goto cleanup0;
edd16368 4727 }
b03a7771 4728 if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
edd16368
SC		 4729 /* Copy the data out of the buffer we created */
4730 BYTE __user *ptr = ioc->buf;
4731 for (i = 0; i < sg_used; i++) {
4732 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 4733 status = -EFAULT;
e2d4a1f6 4734 goto cleanup0;
edd16368
SC		 4735 }
4736 ptr += buff_size[i];
4737 }
4738 }
edd16368 4739 status = 0;
e2d4a1f6
SC		 4740cleanup0:
4741 cmd_special_free(h, c);
edd16368
SC		 4742cleanup1:
4743 if (buff) {
4744 for (i = 0; i < sg_used; i++)
4745 kfree(buff[i]);
4746 kfree(buff);
4747 }
4748 kfree(buff_size);
4749 kfree(ioc);
4750 return status;
4751}
4752
4753static void check_ioctl_unit_attention(struct ctlr_info *h,
4754 struct CommandList *c)
4755{
4756 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4757 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
4758 (void) check_for_unit_attention(h, c);
4759}
0390f0c0
SC		 4760
4761static int increment_passthru_count(struct ctlr_info *h)
4762{
4763 unsigned long flags;
4764
4765 spin_lock_irqsave(&h->passthru_count_lock, flags);
4766 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
4767 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4768 return -1;
4769 }
4770 h->passthru_count++;
4771 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4772 return 0;
4773}
4774
4775static void decrement_passthru_count(struct ctlr_info *h)
4776{
4777 unsigned long flags;
4778
4779 spin_lock_irqsave(&h->passthru_count_lock, flags);
4780 if (h->passthru_count <= 0) {
4781 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4782 /* not expecting to get here. */
4783 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
4784 return;
4785 }
4786 h->passthru_count--;
4787 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4788}
4789
edd16368
SC		 4790/*
4791 * ioctl
4792 */
4793static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
4794{
4795 struct ctlr_info *h;
4796 void __user *argp = (void __user *)arg;
0390f0c0 4797 int rc;
edd16368
SC		 4798
4799 h = sdev_to_hba(dev);
4800
4801 switch (cmd) {
4802 case CCISS_DEREGDISK:
4803 case CCISS_REGNEWDISK:
4804 case CCISS_REGNEWD:
a08a8471 4805 hpsa_scan_start(h->scsi_host);
edd16368
SC		 4806 return 0;
4807 case CCISS_GETPCIINFO:
4808 return hpsa_getpciinfo_ioctl(h, argp);
4809 case CCISS_GETDRIVVER:
4810 return hpsa_getdrivver_ioctl(h, argp);
4811 case CCISS_PASSTHRU:
0390f0c0
SC		 4812 if (increment_passthru_count(h))
4813 return -EAGAIN;
4814 rc = hpsa_passthru_ioctl(h, argp);
4815 decrement_passthru_count(h);
4816 return rc;
edd16368 4817 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 4818 if (increment_passthru_count(h))
4819 return -EAGAIN;
4820 rc = hpsa_big_passthru_ioctl(h, argp);
4821 decrement_passthru_count(h);
4822 return rc;
edd16368
SC		 4823 default:
4824 return -ENOTTY;
4825 }
4826}
4827
6f039790
GKH		 4828static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
4829 u8 reset_type)
64670ac8
SC		 4830{
4831 struct CommandList *c;
4832
4833 c = cmd_alloc(h);
4834 if (!c)
4835 return -ENOMEM;
a2dac136
SC		 4836 /* fill_cmd can't fail here, no data buffer to map */
4837 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 4838 RAID_CTLR_LUNID, TYPE_MSG);
4839 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
4840 c->waiting = NULL;
4841 enqueue_cmd_and_start_io(h, c);
4842 /* Don't wait for completion, the reset won't complete. Don't free
4843 * the command either. This is the last command we will send before
4844 * re-initializing everything, so it doesn't matter and won't leak.
4845 */
4846 return 0;
4847}
4848
a2dac136 4849static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 4850 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 4851 int cmd_type)
4852{
4853 int pci_dir = XFER_NONE;
75167d2c 4854 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 4855
4856 c->cmd_type = CMD_IOCTL_PEND;
4857 c->Header.ReplyQueue = 0;
4858 if (buff != NULL && size > 0) {
4859 c->Header.SGList = 1;
4860 c->Header.SGTotal = 1;
4861 } else {
4862 c->Header.SGList = 0;
4863 c->Header.SGTotal = 0;
4864 }
4865 c->Header.Tag.lower = c->busaddr;
4866 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
4867
4868 c->Request.Type.Type = cmd_type;
4869 if (cmd_type == TYPE_CMD) {
4870 switch (cmd) {
4871 case HPSA_INQUIRY:
4872 /* are we trying to read a vital product page */
b7bb24eb 4873 if (page_code & VPD_PAGE) {
edd16368 4874 c->Request.CDB[1] = 0x01;
b7bb24eb 4875 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 4876 }
4877 c->Request.CDBLen = 6;
4878 c->Request.Type.Attribute = ATTR_SIMPLE;
4879 c->Request.Type.Direction = XFER_READ;
4880 c->Request.Timeout = 0;
4881 c->Request.CDB[0] = HPSA_INQUIRY;
4882 c->Request.CDB[4] = size & 0xFF;
4883 break;
4884 case HPSA_REPORT_LOG:
4885 case HPSA_REPORT_PHYS:
4886 /* Talking to controller so It's a physical command
4887 mode = 00 target = 0. Nothing to write.
4888 */
4889 c->Request.CDBLen = 12;
4890 c->Request.Type.Attribute = ATTR_SIMPLE;
4891 c->Request.Type.Direction = XFER_READ;
4892 c->Request.Timeout = 0;
4893 c->Request.CDB[0] = cmd;
4894 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
4895 c->Request.CDB[7] = (size >> 16) & 0xFF;
4896 c->Request.CDB[8] = (size >> 8) & 0xFF;
4897 c->Request.CDB[9] = size & 0xFF;
4898 break;
edd16368
SC		 4899 case HPSA_CACHE_FLUSH:
4900 c->Request.CDBLen = 12;
4901 c->Request.Type.Attribute = ATTR_SIMPLE;
4902 c->Request.Type.Direction = XFER_WRITE;
4903 c->Request.Timeout = 0;
4904 c->Request.CDB[0] = BMIC_WRITE;
4905 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 4906 c->Request.CDB[7] = (size >> 8) & 0xFF;
4907 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 4908 break;
4909 case TEST_UNIT_READY:
4910 c->Request.CDBLen = 6;
4911 c->Request.Type.Attribute = ATTR_SIMPLE;
4912 c->Request.Type.Direction = XFER_NONE;
4913 c->Request.Timeout = 0;
4914 break;
283b4a9b
SC		 4915 case HPSA_GET_RAID_MAP:
4916 c->Request.CDBLen = 12;
4917 c->Request.Type.Attribute = ATTR_SIMPLE;
4918 c->Request.Type.Direction = XFER_READ;
4919 c->Request.Timeout = 0;
4920 c->Request.CDB[0] = HPSA_CISS_READ;
4921 c->Request.CDB[1] = cmd;
4922 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
4923 c->Request.CDB[7] = (size >> 16) & 0xFF;
4924 c->Request.CDB[8] = (size >> 8) & 0xFF;
4925 c->Request.CDB[9] = size & 0xFF;
4926 break;
edd16368
SC		 4927 default:
4928 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
4929 BUG();
a2dac136 4930 return -1;
edd16368
SC		 4931 }
4932 } else if (cmd_type == TYPE_MSG) {
4933 switch (cmd) {
4934
4935 case HPSA_DEVICE_RESET_MSG:
4936 c->Request.CDBLen = 16;
4937 c->Request.Type.Type = 1; /* It is a MSG not a CMD */
4938 c->Request.Type.Attribute = ATTR_SIMPLE;
4939 c->Request.Type.Direction = XFER_NONE;
4940 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 4941 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
4942 c->Request.CDB[0] = cmd;
21e89afd 4943 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 4944 /* If bytes 4-7 are zero, it means reset the */
4945 /* LunID device */
4946 c->Request.CDB[4] = 0x00;
4947 c->Request.CDB[5] = 0x00;
4948 c->Request.CDB[6] = 0x00;
4949 c->Request.CDB[7] = 0x00;
75167d2c
SC		 4950 break;
4951 case HPSA_ABORT_MSG:
4952 a = buff; /* point to command to be aborted */
4953 dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n",
4954 a->Header.Tag.upper, a->Header.Tag.lower,
4955 c->Header.Tag.upper, c->Header.Tag.lower);
4956 c->Request.CDBLen = 16;
4957 c->Request.Type.Type = TYPE_MSG;
4958 c->Request.Type.Attribute = ATTR_SIMPLE;
4959 c->Request.Type.Direction = XFER_WRITE;
4960 c->Request.Timeout = 0; /* Don't time out */
4961 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
4962 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
4963 c->Request.CDB[2] = 0x00; /* reserved */
4964 c->Request.CDB[3] = 0x00; /* reserved */
4965 /* Tag to abort goes in CDB[4]-CDB[11] */
4966 c->Request.CDB[4] = a->Header.Tag.lower & 0xFF;
4967 c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF;
4968 c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF;
4969 c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF;
4970 c->Request.CDB[8] = a->Header.Tag.upper & 0xFF;
4971 c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF;
4972 c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF;
4973 c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF;
4974 c->Request.CDB[12] = 0x00; /* reserved */
4975 c->Request.CDB[13] = 0x00; /* reserved */
4976 c->Request.CDB[14] = 0x00; /* reserved */
4977 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 4978 break;
edd16368
SC		 4979 default:
4980 dev_warn(&h->pdev->dev, "unknown message type %d\n",
4981 cmd);
4982 BUG();
4983 }
4984 } else {
4985 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
4986 BUG();
4987 }
4988
4989 switch (c->Request.Type.Direction) {
4990 case XFER_READ:
4991 pci_dir = PCI_DMA_FROMDEVICE;
4992 break;
4993 case XFER_WRITE:
4994 pci_dir = PCI_DMA_TODEVICE;
4995 break;
4996 case XFER_NONE:
4997 pci_dir = PCI_DMA_NONE;
4998 break;
4999 default:
5000 pci_dir = PCI_DMA_BIDIRECTIONAL;
5001 }
a2dac136
SC		 5002 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5003 return -1;
5004 return 0;
edd16368
SC		 5005}
5006
5007/*
5008 * Map (physical) PCI mem into (virtual) kernel space
5009 */
5010static void __iomem *remap_pci_mem(ulong base, ulong size)
5011{
5012 ulong page_base = ((ulong) base) & PAGE_MASK;
5013 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5014 void __iomem *page_remapped = ioremap_nocache(page_base,
5015 page_offs + size);
edd16368
SC		 5016
5017 return page_remapped ? (page_remapped + page_offs) : NULL;
5018}
5019
5020/* Takes cmds off the submission queue and sends them to the hardware,
5021 * then puts them on the queue of cmds waiting for completion.
5022 */
5023static void start_io(struct ctlr_info *h)
5024{
5025 struct CommandList *c;
e16a33ad 5026 unsigned long flags;
edd16368 5027
e16a33ad 5028 spin_lock_irqsave(&h->lock, flags);
9e0fc764
SC		 5029 while (!list_empty(&h->reqQ)) {
5030 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 5031 /* can't do anything if fifo is full */
5032 if ((h->access.fifo_full(h))) {
396883e2 5033 h->fifo_recently_full = 1;
edd16368
SC		 5034 dev_warn(&h->pdev->dev, "fifo full\n");
5035 break;
5036 }
396883e2 5037 h->fifo_recently_full = 0;
edd16368
SC		 5038
5039 /* Get the first entry from the Request Q */
5040 removeQ(c);
5041 h->Qdepth--;
5042
edd16368
SC		 5043 /* Put job onto the completed Q */
5044 addQ(&h->cmpQ, c);
e16a33ad
MG		 5045
5046 /* Must increment commands_outstanding before unlocking
5047 * and submitting to avoid race checking for fifo full
5048 * condition.
5049 */
5050 h->commands_outstanding++;
5051 if (h->commands_outstanding > h->max_outstanding)
5052 h->max_outstanding = h->commands_outstanding;
5053
5054 /* Tell the controller execute command */
5055 spin_unlock_irqrestore(&h->lock, flags);
5056 h->access.submit_command(h, c);
5057 spin_lock_irqsave(&h->lock, flags);
edd16368 5058 }
e16a33ad 5059 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 5060}
5061
254f796b 5062static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5063{
254f796b 5064 return h->access.command_completed(h, q);
edd16368
SC		 5065}
5066
900c5440 5067static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5068{
5069 return h->access.intr_pending(h);
5070}
5071
5072static inline long interrupt_not_for_us(struct ctlr_info *h)
5073{
10f66018
SC		 5074 return (h->access.intr_pending(h) == 0) ||
5075 (h->interrupts_enabled == 0);
edd16368
SC		 5076}
5077
01a02ffc
SC		 5078static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5079 u32 raw_tag)
edd16368
SC		 5080{
5081 if (unlikely(tag_index >= h->nr_cmds)) {
5082 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5083 return 1;
5084 }
5085 return 0;
5086}
5087
5a3d16f5 5088static inline void finish_cmd(struct CommandList *c)
edd16368 5089{
e16a33ad 5090 unsigned long flags;
396883e2
SC		 5091 int io_may_be_stalled = 0;
5092 struct ctlr_info *h = c->h;
e16a33ad 5093
396883e2 5094 spin_lock_irqsave(&h->lock, flags);
edd16368 5095 removeQ(c);
396883e2
SC		 5096
5097 /*
5098 * Check for possibly stalled i/o.
5099 *
5100 * If a fifo_full condition is encountered, requests will back up
5101 * in h->reqQ. This queue is only emptied out by start_io which is
5102 * only called when a new i/o request comes in. If no i/o's are
5103 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
5104 * start_io from here if we detect such a danger.
5105 *
5106 * Normally, we shouldn't hit this case, but pounding on the
5107 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
5108 * commands_outstanding is low. We want to avoid calling
5109 * start_io from in here as much as possible, and esp. don't
5110 * want to get in a cycle where we call start_io every time
5111 * through here.
5112 */
5113 if (unlikely(h->fifo_recently_full) &&
5114 h->commands_outstanding < 5)
5115 io_may_be_stalled = 1;
5116
5117 spin_unlock_irqrestore(&h->lock, flags);
5118
e85c5974 5119 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5120 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5121 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5122 complete_scsi_command(c);
edd16368
SC		 5123 else if (c->cmd_type == CMD_IOCTL_PEND)
5124 complete(c->waiting);
396883e2
SC		 5125 if (unlikely(io_may_be_stalled))
5126 start_io(h);
edd16368
SC		 5127}
5128
a104c99f
SC		 5129static inline u32 hpsa_tag_contains_index(u32 tag)
5130{
a104c99f
SC		 5131 return tag & DIRECT_LOOKUP_BIT;
5132}
5133
5134static inline u32 hpsa_tag_to_index(u32 tag)
5135{
a104c99f
SC		 5136 return tag >> DIRECT_LOOKUP_SHIFT;
5137}
5138
a9a3a273
SC		 5139
5140static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5141{
a9a3a273
SC		 5142#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5143#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5144 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5145 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5146 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5147}
5148
303932fd 5149/* process completion of an indexed ("direct lookup") command */
1d94f94d 5150static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5151 u32 raw_tag)
5152{
5153 u32 tag_index;
5154 struct CommandList *c;
5155
5156 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 5157 if (!bad_tag(h, tag_index, raw_tag)) {
5158 c = h->cmd_pool + tag_index;
5159 finish_cmd(c);
5160 }
303932fd
DB		 5161}
5162
5163/* process completion of a non-indexed command */
1d94f94d 5164static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 5165 u32 raw_tag)
5166{
5167 u32 tag;
5168 struct CommandList *c = NULL;
e16a33ad 5169 unsigned long flags;
303932fd 5170
a9a3a273 5171 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 5172 spin_lock_irqsave(&h->lock, flags);
9e0fc764 5173 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 5174 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 5175 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 5176 finish_cmd(c);
1d94f94d 5177 return;
303932fd
DB		 5178 }
5179 }
e16a33ad 5180 spin_unlock_irqrestore(&h->lock, flags);
303932fd 5181 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 5182}
5183
64670ac8
SC		 5184/* Some controllers, like p400, will give us one interrupt
5185 * after a soft reset, even if we turned interrupts off.
5186 * Only need to check for this in the hpsa_xxx_discard_completions
5187 * functions.
5188 */
5189static int ignore_bogus_interrupt(struct ctlr_info *h)
5190{
5191 if (likely(!reset_devices))
5192 return 0;
5193
5194 if (likely(h->interrupts_enabled))
5195 return 0;
5196
5197 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5198 "(known firmware bug.) Ignoring.\n");
5199
5200 return 1;
5201}
5202
254f796b
MG		 5203/*
5204 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5205 * Relies on (h-q[x] == x) being true for x such that
5206 * 0 <= x < MAX_REPLY_QUEUES.
5207 */
5208static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5209{
254f796b
MG		 5210 return container_of((queue - *queue), struct ctlr_info, q[0]);
5211}
5212
5213static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5214{
5215 struct ctlr_info *h = queue_to_hba(queue);
5216 u8 q = *(u8 *) queue;
64670ac8
SC		 5217 u32 raw_tag;
5218
5219 if (ignore_bogus_interrupt(h))
5220 return IRQ_NONE;
5221
5222 if (interrupt_not_for_us(h))
5223 return IRQ_NONE;
a0c12413 5224 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5225 while (interrupt_pending(h)) {
254f796b 5226 raw_tag = get_next_completion(h, q);
64670ac8 5227 while (raw_tag != FIFO_EMPTY)
254f796b 5228 raw_tag = next_command(h, q);
64670ac8 5229 }
64670ac8
SC		 5230 return IRQ_HANDLED;
5231}
5232
254f796b 5233static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5234{
254f796b 5235 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5236 u32 raw_tag;
254f796b 5237 u8 q = *(u8 *) queue;
64670ac8
SC		 5238
5239 if (ignore_bogus_interrupt(h))
5240 return IRQ_NONE;
5241
a0c12413 5242 h->last_intr_timestamp = get_jiffies_64();
254f796b 5243 raw_tag = get_next_completion(h, q);
64670ac8 5244 while (raw_tag != FIFO_EMPTY)
254f796b 5245 raw_tag = next_command(h, q);
64670ac8
SC		 5246 return IRQ_HANDLED;
5247}
5248
254f796b 5249static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5250{
254f796b 5251 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5252 u32 raw_tag;
254f796b 5253 u8 q = *(u8 *) queue;
edd16368
SC		 5254
5255 if (interrupt_not_for_us(h))
5256 return IRQ_NONE;
a0c12413 5257 h->last_intr_timestamp = get_jiffies_64();
10f66018 5258 while (interrupt_pending(h)) {
254f796b 5259 raw_tag = get_next_completion(h, q);
10f66018 5260 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5261 if (likely(hpsa_tag_contains_index(raw_tag)))
5262 process_indexed_cmd(h, raw_tag);
10f66018 5263 else
1d94f94d 5264 process_nonindexed_cmd(h, raw_tag);
254f796b 5265 raw_tag = next_command(h, q);
10f66018
SC		 5266 }
5267 }
10f66018
SC		 5268 return IRQ_HANDLED;
5269}
5270
254f796b 5271static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5272{
254f796b 5273 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5274 u32 raw_tag;
254f796b 5275 u8 q = *(u8 *) queue;
10f66018 5276
a0c12413 5277 h->last_intr_timestamp = get_jiffies_64();
254f796b 5278 raw_tag = get_next_completion(h, q);
303932fd 5279 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5280 if (likely(hpsa_tag_contains_index(raw_tag)))
5281 process_indexed_cmd(h, raw_tag);
303932fd 5282 else
1d94f94d 5283 process_nonindexed_cmd(h, raw_tag);
254f796b 5284 raw_tag = next_command(h, q);
edd16368 5285 }
edd16368
SC		 5286 return IRQ_HANDLED;
5287}
5288
a9a3a273
SC		 5289/* Send a message CDB to the firmware. Careful, this only works
5290 * in simple mode, not performant mode due to the tag lookup.
5291 * We only ever use this immediately after a controller reset.
5292 */
6f039790
GKH		 5293static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5294 unsigned char type)
edd16368
SC		 5295{
5296 struct Command {
5297 struct CommandListHeader CommandHeader;
5298 struct RequestBlock Request;
5299 struct ErrDescriptor ErrorDescriptor;
5300 };
5301 struct Command *cmd;
5302 static const size_t cmd_sz = sizeof(*cmd) +
5303 sizeof(cmd->ErrorDescriptor);
5304 dma_addr_t paddr64;
5305 uint32_t paddr32, tag;
5306 void __iomem *vaddr;
5307 int i, err;
5308
5309 vaddr = pci_ioremap_bar(pdev, 0);
5310 if (vaddr == NULL)
5311 return -ENOMEM;
5312
5313 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5314 * CCISS commands, so they must be allocated from the lower 4GiB of
5315 * memory.
5316 */
5317 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5318 if (err) {
5319 iounmap(vaddr);
5320 return -ENOMEM;
5321 }
5322
5323 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5324 if (cmd == NULL) {
5325 iounmap(vaddr);
5326 return -ENOMEM;
5327 }
5328
5329 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5330 * although there's no guarantee, we assume that the address is at
5331 * least 4-byte aligned (most likely, it's page-aligned).
5332 */
5333 paddr32 = paddr64;
5334
5335 cmd->CommandHeader.ReplyQueue = 0;
5336 cmd->CommandHeader.SGList = 0;
5337 cmd->CommandHeader.SGTotal = 0;
5338 cmd->CommandHeader.Tag.lower = paddr32;
5339 cmd->CommandHeader.Tag.upper = 0;
5340 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5341
5342 cmd->Request.CDBLen = 16;
5343 cmd->Request.Type.Type = TYPE_MSG;
5344 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
5345 cmd->Request.Type.Direction = XFER_NONE;
5346 cmd->Request.Timeout = 0; /* Don't time out */
5347 cmd->Request.CDB[0] = opcode;
5348 cmd->Request.CDB[1] = type;
5349 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
5350 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
5351 cmd->ErrorDescriptor.Addr.upper = 0;
5352 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
5353
5354 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
5355
5356 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5357 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
a9a3a273 5358 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
edd16368
SC		 5359 break;
5360 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5361 }
5362
5363 iounmap(vaddr);
5364
5365 /* we leak the DMA buffer here ... no choice since the controller could
5366 * still complete the command.
5367 */
5368 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5369 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5370 opcode, type);
5371 return -ETIMEDOUT;
5372 }
5373
5374 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5375
5376 if (tag & HPSA_ERROR_BIT) {
5377 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5378 opcode, type);
5379 return -EIO;
5380 }
5381
5382 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5383 opcode, type);
5384 return 0;
5385}
5386
edd16368
SC		 5387#define hpsa_noop(p) hpsa_message(p, 3, 0)
5388
1df8552a 5389static int hpsa_controller_hard_reset(struct pci_dev *pdev,
cf0b08d0 5390 void * __iomem vaddr, u32 use_doorbell)
1df8552a
SC		 5391{
5392 u16 pmcsr;
5393 int pos;
5394
5395 if (use_doorbell) {
5396 /* For everything after the P600, the PCI power state method
5397 * of resetting the controller doesn't work, so we have this
5398 * other way using the doorbell register.
5399 */
5400 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5401 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239
SC		 5402
5403 /* PMC hardware guys tell us we need a 5 second delay after
5404 * doorbell reset and before any attempt to talk to the board
5405 * at all to ensure that this actually works and doesn't fall
5406 * over in some weird corner cases.
5407 */
5408 msleep(5000);
1df8552a
SC		 5409 } else { /* Try to do it the PCI power state way */
5410
5411 /* Quoting from the Open CISS Specification: "The Power
5412 * Management Control/Status Register (CSR) controls the power
5413 * state of the device. The normal operating state is D0,
5414 * CSR=00h. The software off state is D3, CSR=03h. To reset
5415 * the controller, place the interface device in D3 then to D0,
5416 * this causes a secondary PCI reset which will reset the
5417 * controller." */
5418
5419 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
5420 if (pos == 0) {
5421 dev_err(&pdev->dev,
5422 "hpsa_reset_controller: "
5423 "PCI PM not supported\n");
5424 return -ENODEV;
5425 }
5426 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
5427 /* enter the D3hot power management state */
5428 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
5429 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5430 pmcsr |= PCI_D3hot;
5431 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
5432
5433 msleep(500);
5434
5435 /* enter the D0 power management state */
5436 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5437 pmcsr |= PCI_D0;
5438 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
c4853efe
MM		 5439
5440 /*
5441 * The P600 requires a small delay when changing states.
5442 * Otherwise we may think the board did not reset and we bail.
5443 * This for kdump only and is particular to the P600.
5444 */
5445 msleep(500);
1df8552a
SC		 5446 }
5447 return 0;
5448}
5449
6f039790 5450static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5451{
5452 memset(driver_version, 0, len);
f79cfec6 5453 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5454}
5455
6f039790 5456static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5457{
5458 char *driver_version;
5459 int i, size = sizeof(cfgtable->driver_version);
5460
5461 driver_version = kmalloc(size, GFP_KERNEL);
5462 if (!driver_version)
5463 return -ENOMEM;
5464
5465 init_driver_version(driver_version, size);
5466 for (i = 0; i < size; i++)
5467 writeb(driver_version[i], &cfgtable->driver_version[i]);
5468 kfree(driver_version);
5469 return 0;
5470}
5471
6f039790
GKH		 5472static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5473 unsigned char *driver_ver)
580ada3c
SC		 5474{
5475 int i;
5476
5477 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5478 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5479}
5480
6f039790 5481static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5482{
5483
5484 char *driver_ver, *old_driver_ver;
5485 int rc, size = sizeof(cfgtable->driver_version);
5486
5487 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5488 if (!old_driver_ver)
5489 return -ENOMEM;
5490 driver_ver = old_driver_ver + size;
5491
5492 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5493 * should have been changed, otherwise we know the reset failed.
5494 */
5495 init_driver_version(old_driver_ver, size);
5496 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5497 rc = !memcmp(driver_ver, old_driver_ver, size);
5498 kfree(old_driver_ver);
5499 return rc;
5500}
edd16368 5501/* This does a hard reset of the controller using PCI power management
1df8552a 5502 * states or the using the doorbell register.
edd16368 5503 */
6f039790 5504static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5505{
1df8552a
SC		 5506 u64 cfg_offset;
5507 u32 cfg_base_addr;
5508 u64 cfg_base_addr_index;
5509 void __iomem *vaddr;
5510 unsigned long paddr;
580ada3c 5511 u32 misc_fw_support;
270d05de 5512 int rc;
1df8552a 5513 struct CfgTable __iomem *cfgtable;
cf0b08d0 5514 u32 use_doorbell;
18867659 5515 u32 board_id;
270d05de 5516 u16 command_register;
edd16368 5517
1df8552a
SC		 5518 /* For controllers as old as the P600, this is very nearly
5519 * the same thing as
edd16368
SC		 5520 *
5521 * pci_save_state(pci_dev);
5522 * pci_set_power_state(pci_dev, PCI_D3hot);
5523 * pci_set_power_state(pci_dev, PCI_D0);
5524 * pci_restore_state(pci_dev);
5525 *
1df8552a
SC		 5526 * For controllers newer than the P600, the pci power state
5527 * method of resetting doesn't work so we have another way
5528 * using the doorbell register.
edd16368 5529 */
18867659 5530
25c1e56a 5531 rc = hpsa_lookup_board_id(pdev, &board_id);
46380786 5532 if (rc < 0 || !ctlr_is_resettable(board_id)) {
25c1e56a
SC		 5533 dev_warn(&pdev->dev, "Not resetting device.\n");
5534 return -ENODEV;
5535 }
46380786
SC		 5536
5537 /* if controller is soft- but not hard resettable... */
5538 if (!ctlr_is_hard_resettable(board_id))
5539 return -ENOTSUPP; /* try soft reset later. */
18867659 5540
270d05de
SC		 5541 /* Save the PCI command register */
5542 pci_read_config_word(pdev, 4, &command_register);
5543 /* Turn the board off. This is so that later pci_restore_state()
5544 * won't turn the board on before the rest of config space is ready.
5545 */
5546 pci_disable_device(pdev);
5547 pci_save_state(pdev);
edd16368 5548
1df8552a
SC		 5549 /* find the first memory BAR, so we can find the cfg table */
5550 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5551 if (rc)
5552 return rc;
5553 vaddr = remap_pci_mem(paddr, 0x250);
5554 if (!vaddr)
5555 return -ENOMEM;
edd16368 5556
1df8552a
SC		 5557 /* find cfgtable in order to check if reset via doorbell is supported */
5558 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
5559 &cfg_base_addr_index, &cfg_offset);
5560 if (rc)
5561 goto unmap_vaddr;
5562 cfgtable = remap_pci_mem(pci_resource_start(pdev,
5563 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
5564 if (!cfgtable) {
5565 rc = -ENOMEM;
5566 goto unmap_vaddr;
5567 }
580ada3c
SC		 5568 rc = write_driver_ver_to_cfgtable(cfgtable);
5569 if (rc)
5570 goto unmap_vaddr;
edd16368 5571
cf0b08d0
SC		 5572 /* If reset via doorbell register is supported, use that.
5573 * There are two such methods. Favor the newest method.
5574 */
1df8552a 5575 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 5576 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
5577 if (use_doorbell) {
5578 use_doorbell = DOORBELL_CTLR_RESET2;
5579 } else {
5580 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
5581 if (use_doorbell) {
fba63097
MM		 5582 dev_warn(&pdev->dev, "Soft reset not supported. "
5583 "Firmware update is required.\n");
64670ac8 5584 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 5585 goto unmap_cfgtable;
5586 }
5587 }
edd16368 5588
1df8552a
SC		 5589 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
5590 if (rc)
5591 goto unmap_cfgtable;
edd16368 5592
270d05de
SC		 5593 pci_restore_state(pdev);
5594 rc = pci_enable_device(pdev);
5595 if (rc) {
5596 dev_warn(&pdev->dev, "failed to enable device.\n");
5597 goto unmap_cfgtable;
edd16368 5598 }
270d05de 5599 pci_write_config_word(pdev, 4, command_register);
edd16368 5600
1df8552a
SC		 5601 /* Some devices (notably the HP Smart Array 5i Controller)
5602 need a little pause here */
5603 msleep(HPSA_POST_RESET_PAUSE_MSECS);
5604
fe5389c8
SC		 5605 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
5606 if (rc) {
5607 dev_warn(&pdev->dev,
64670ac8
SC		 5608 "failed waiting for board to become ready "
5609 "after hard reset\n");
fe5389c8
SC		 5610 goto unmap_cfgtable;
5611 }
fe5389c8 5612
580ada3c
SC		 5613 rc = controller_reset_failed(vaddr);
5614 if (rc < 0)
5615 goto unmap_cfgtable;
5616 if (rc) {
64670ac8
SC		 5617 dev_warn(&pdev->dev, "Unable to successfully reset "
5618 "controller. Will try soft reset.\n");
5619 rc = -ENOTSUPP;
580ada3c 5620 } else {
64670ac8 5621 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 5622 }
5623
5624unmap_cfgtable:
5625 iounmap(cfgtable);
5626
5627unmap_vaddr:
5628 iounmap(vaddr);
5629 return rc;
edd16368
SC		 5630}
5631
5632/*
5633 * We cannot read the structure directly, for portability we must use
5634 * the io functions.
5635 * This is for debug only.
5636 */
edd16368
SC		 5637static void print_cfg_table(struct device *dev, struct CfgTable *tb)
5638{
58f8665c 5639#ifdef HPSA_DEBUG
edd16368
SC		 5640 int i;
5641 char temp_name[17];
5642
5643 dev_info(dev, "Controller Configuration information\n");
5644 dev_info(dev, "------------------------------------\n");
5645 for (i = 0; i < 4; i++)
5646 temp_name[i] = readb(&(tb->Signature[i]));
5647 temp_name[4] = '\0';
5648 dev_info(dev, " Signature = %s\n", temp_name);
5649 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
5650 dev_info(dev, " Transport methods supported = 0x%x\n",
5651 readl(&(tb->TransportSupport)));
5652 dev_info(dev, " Transport methods active = 0x%x\n",
5653 readl(&(tb->TransportActive)));
5654 dev_info(dev, " Requested transport Method = 0x%x\n",
5655 readl(&(tb->HostWrite.TransportRequest)));
5656 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
5657 readl(&(tb->HostWrite.CoalIntDelay)));
5658 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
5659 readl(&(tb->HostWrite.CoalIntCount)));
5660 dev_info(dev, " Max outstanding commands = 0x%d\n",
5661 readl(&(tb->CmdsOutMax)));
5662 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
5663 for (i = 0; i < 16; i++)
5664 temp_name[i] = readb(&(tb->ServerName[i]));
5665 temp_name[16] = '\0';
5666 dev_info(dev, " Server Name = %s\n", temp_name);
5667 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
5668 readl(&(tb->HeartBeat)));
edd16368 5669#endif /* HPSA_DEBUG */
58f8665c 5670}
edd16368
SC		 5671
5672static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
5673{
5674 int i, offset, mem_type, bar_type;
5675
5676 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
5677 return 0;
5678 offset = 0;
5679 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5680 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
5681 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
5682 offset += 4;
5683 else {
5684 mem_type = pci_resource_flags(pdev, i) &
5685 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
5686 switch (mem_type) {
5687 case PCI_BASE_ADDRESS_MEM_TYPE_32:
5688 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
5689 offset += 4; /* 32 bit */
5690 break;
5691 case PCI_BASE_ADDRESS_MEM_TYPE_64:
5692 offset += 8;
5693 break;
5694 default: /* reserved in PCI 2.2 */
5695 dev_warn(&pdev->dev,
5696 "base address is invalid\n");
5697 return -1;
5698 break;
5699 }
5700 }
5701 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
5702 return i + 1;
5703 }
5704 return -1;
5705}
5706
5707/* If MSI/MSI-X is supported by the kernel we will try to enable it on
5708 * controllers that are capable. If not, we use IO-APIC mode.
5709 */
5710
6f039790 5711static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 5712{
5713#ifdef CONFIG_PCI_MSI
254f796b
MG		 5714 int err, i;
5715 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
5716
5717 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
5718 hpsa_msix_entries[i].vector = 0;
5719 hpsa_msix_entries[i].entry = i;
5720 }
edd16368
SC		 5721
5722 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 5723 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
5724 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 5725 goto default_int_mode;
55c06c71
SC		 5726 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
5727 dev_info(&h->pdev->dev, "MSIX\n");
eee0f03a 5728 h->msix_vector = MAX_REPLY_QUEUES;
254f796b 5729 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
eee0f03a 5730 h->msix_vector);
edd16368 5731 if (err > 0) {
55c06c71 5732 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 5733 "available\n", err);
eee0f03a
HR		 5734 h->msix_vector = err;
5735 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
5736 h->msix_vector);
5737 }
5738 if (!err) {
5739 for (i = 0; i < h->msix_vector; i++)
5740 h->intr[i] = hpsa_msix_entries[i].vector;
5741 return;
edd16368 5742 } else {
55c06c71 5743 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
edd16368 5744 err);
eee0f03a 5745 h->msix_vector = 0;
edd16368
SC		 5746 goto default_int_mode;
5747 }
5748 }
55c06c71
SC		 5749 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
5750 dev_info(&h->pdev->dev, "MSI\n");
5751 if (!pci_enable_msi(h->pdev))
edd16368
SC		 5752 h->msi_vector = 1;
5753 else
55c06c71 5754 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 5755 }
5756default_int_mode:
5757#endif /* CONFIG_PCI_MSI */
5758 /* if we get here we're going to use the default interrupt mode */
a9a3a273 5759 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 5760}
5761
6f039790 5762static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 5763{
5764 int i;
5765 u32 subsystem_vendor_id, subsystem_device_id;
5766
5767 subsystem_vendor_id = pdev->subsystem_vendor;
5768 subsystem_device_id = pdev->subsystem_device;
5769 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
5770 subsystem_vendor_id;
5771
5772 for (i = 0; i < ARRAY_SIZE(products); i++)
5773 if (*board_id == products[i].board_id)
5774 return i;
5775
6798cc0a
SC		 5776 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
5777 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
5778 !hpsa_allow_any) {
e5c880d1
SC		 5779 dev_warn(&pdev->dev, "unrecognized board ID: "
5780 "0x%08x, ignoring.\n", *board_id);
5781 return -ENODEV;
5782 }
5783 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
5784}
5785
6f039790
GKH		 5786static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
5787 unsigned long *memory_bar)
3a7774ce
SC		 5788{
5789 int i;
5790
5791 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 5792 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 5793 /* addressing mode bits already removed */
12d2cd47
SC		 5794 *memory_bar = pci_resource_start(pdev, i);
5795 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 5796 *memory_bar);
5797 return 0;
5798 }
12d2cd47 5799 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 5800 return -ENODEV;
5801}
5802
6f039790
GKH		 5803static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
5804 int wait_for_ready)
2c4c8c8b 5805{
fe5389c8 5806 int i, iterations;
2c4c8c8b 5807 u32 scratchpad;
fe5389c8
SC		 5808 if (wait_for_ready)
5809 iterations = HPSA_BOARD_READY_ITERATIONS;
5810 else
5811 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 5812
fe5389c8
SC		 5813 for (i = 0; i < iterations; i++) {
5814 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
5815 if (wait_for_ready) {
5816 if (scratchpad == HPSA_FIRMWARE_READY)
5817 return 0;
5818 } else {
5819 if (scratchpad != HPSA_FIRMWARE_READY)
5820 return 0;
5821 }
2c4c8c8b
SC		 5822 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
5823 }
fe5389c8 5824 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 5825 return -ENODEV;
5826}
5827
6f039790
GKH		 5828static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
5829 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
5830 u64 *cfg_offset)
a51fd47f
SC		 5831{
5832 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
5833 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
5834 *cfg_base_addr &= (u32) 0x0000ffff;
5835 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
5836 if (*cfg_base_addr_index == -1) {
5837 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
5838 return -ENODEV;
5839 }
5840 return 0;
5841}
5842
6f039790 5843static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 5844{
01a02ffc
SC		 5845 u64 cfg_offset;
5846 u32 cfg_base_addr;
5847 u64 cfg_base_addr_index;
303932fd 5848 u32 trans_offset;
a51fd47f 5849 int rc;
77c4495c 5850
a51fd47f
SC		 5851 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
5852 &cfg_base_addr_index, &cfg_offset);
5853 if (rc)
5854 return rc;
77c4495c 5855 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 5856 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
77c4495c
SC		 5857 if (!h->cfgtable)
5858 return -ENOMEM;
580ada3c
SC		 5859 rc = write_driver_ver_to_cfgtable(h->cfgtable);
5860 if (rc)
5861 return rc;
77c4495c 5862 /* Find performant mode table. */
a51fd47f 5863 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 5864 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
5865 cfg_base_addr_index)+cfg_offset+trans_offset,
5866 sizeof(*h->transtable));
5867 if (!h->transtable)
5868 return -ENOMEM;
5869 return 0;
5870}
5871
6f039790 5872static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 5873{
5874 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 5875
5876 /* Limit commands in memory limited kdump scenario. */
5877 if (reset_devices && h->max_commands > 32)
5878 h->max_commands = 32;
5879
cba3d38b
SC		 5880 if (h->max_commands < 16) {
5881 dev_warn(&h->pdev->dev, "Controller reports "
5882 "max supported commands of %d, an obvious lie. "
5883 "Using 16. Ensure that firmware is up to date.\n",
5884 h->max_commands);
5885 h->max_commands = 16;
5886 }
5887}
5888
b93d7536
SC		 5889/* Interrogate the hardware for some limits:
5890 * max commands, max SG elements without chaining, and with chaining,
5891 * SG chain block size, etc.
5892 */
6f039790 5893static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 5894{
cba3d38b 5895 hpsa_get_max_perf_mode_cmds(h);
b93d7536
SC		 5896 h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
5897 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 5898 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
b93d7536
SC		 5899 /*
5900 * Limit in-command s/g elements to 32 save dma'able memory.
5901 * Howvever spec says if 0, use 31
5902 */
5903 h->max_cmd_sg_entries = 31;
5904 if (h->maxsgentries > 512) {
5905 h->max_cmd_sg_entries = 32;
5906 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
5907 h->maxsgentries--; /* save one for chain pointer */
5908 } else {
5909 h->maxsgentries = 31; /* default to traditional values */
5910 h->chainsize = 0;
5911 }
75167d2c
SC		 5912
5913 /* Find out what task management functions are supported and cache */
5914 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 5915 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
5916 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
5917 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5918 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 5919}
5920
76c46e49
SC		 5921static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
5922{
0fc9fd40 5923 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
76c46e49
SC		 5924 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
5925 return false;
5926 }
5927 return true;
5928}
5929
97a5e98c 5930static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 5931{
97a5e98c 5932 u32 driver_support;
f7c39101 5933
28e13446
SC		 5934#ifdef CONFIG_X86
5935 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
97a5e98c
SC		 5936 driver_support = readl(&(h->cfgtable->driver_support));
5937 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 5938#endif
28e13446
SC		 5939 driver_support |= ENABLE_UNIT_ATTN;
5940 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 5941}
5942
3d0eab67
SC		 5943/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
5944 * in a prefetch beyond physical memory.
5945 */
5946static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
5947{
5948 u32 dma_prefetch;
5949
5950 if (h->board_id != 0x3225103C)
5951 return;
5952 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
5953 dma_prefetch |= 0x8000;
5954 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
5955}
5956
76438d08
SC		 5957static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
5958{
5959 int i;
5960 u32 doorbell_value;
5961 unsigned long flags;
5962 /* wait until the clear_event_notify bit 6 is cleared by controller. */
5963 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
5964 spin_lock_irqsave(&h->lock, flags);
5965 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
5966 spin_unlock_irqrestore(&h->lock, flags);
5967 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
5968 break;
5969 /* delay and try again */
5970 msleep(20);
5971 }
5972}
5973
6f039790 5974static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 5975{
5976 int i;
6eaf46fd
SC		 5977 u32 doorbell_value;
5978 unsigned long flags;
eb6b2ae9
SC		 5979
5980 /* under certain very rare conditions, this can take awhile.
5981 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
5982 * as we enter this code.)
5983 */
5984 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 5985 spin_lock_irqsave(&h->lock, flags);
5986 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
5987 spin_unlock_irqrestore(&h->lock, flags);
382be668 5988 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 5989 break;
5990 /* delay and try again */
60d3f5b0 5991 usleep_range(10000, 20000);
eb6b2ae9 5992 }
3f4336f3
SC		 5993}
5994
6f039790 5995static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 5996{
5997 u32 trans_support;
5998
5999 trans_support = readl(&(h->cfgtable->TransportSupport));
6000 if (!(trans_support & SIMPLE_MODE))
6001 return -ENOTSUPP;
6002
6003 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6004
3f4336f3
SC		 6005 /* Update the field, and then ring the doorbell */
6006 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6007 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 6008 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6009 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 6010 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6011 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6012 goto error;
960a30e7 6013 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6014 return 0;
283b4a9b
SC		 6015error:
6016 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
6017 return -ENODEV;
eb6b2ae9
SC		 6018}
6019
6f039790 6020static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6021{
eb6b2ae9 6022 int prod_index, err;
edd16368 6023
e5c880d1
SC		 6024 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6025 if (prod_index < 0)
6026 return -ENODEV;
6027 h->product_name = products[prod_index].product_name;
6028 h->access = *(products[prod_index].access);
edd16368 6029
e5a44df8
MG		 6030 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6031 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6032
55c06c71 6033 err = pci_enable_device(h->pdev);
edd16368 6034 if (err) {
55c06c71 6035 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 6036 return err;
6037 }
6038
5cb460a6
SC		 6039 /* Enable bus mastering (pci_disable_device may disable this) */
6040 pci_set_master(h->pdev);
6041
f79cfec6 6042 err = pci_request_regions(h->pdev, HPSA);
edd16368 6043 if (err) {
55c06c71
SC		 6044 dev_err(&h->pdev->dev,
6045 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 6046 return err;
6047 }
6b3f4c52 6048 hpsa_interrupt_mode(h);
12d2cd47 6049 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6050 if (err)
edd16368 6051 goto err_out_free_res;
edd16368 6052 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 6053 if (!h->vaddr) {
6054 err = -ENOMEM;
6055 goto err_out_free_res;
6056 }
fe5389c8 6057 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6058 if (err)
edd16368 6059 goto err_out_free_res;
77c4495c
SC		 6060 err = hpsa_find_cfgtables(h);
6061 if (err)
edd16368 6062 goto err_out_free_res;
b93d7536 6063 hpsa_find_board_params(h);
edd16368 6064
76c46e49 6065 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 6066 err = -ENODEV;
6067 goto err_out_free_res;
6068 }
97a5e98c 6069 hpsa_set_driver_support_bits(h);
3d0eab67 6070 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6071 err = hpsa_enter_simple_mode(h);
6072 if (err)
edd16368 6073 goto err_out_free_res;
edd16368
SC		 6074 return 0;
6075
6076err_out_free_res:
204892e9
SC		 6077 if (h->transtable)
6078 iounmap(h->transtable);
6079 if (h->cfgtable)
6080 iounmap(h->cfgtable);
6081 if (h->vaddr)
6082 iounmap(h->vaddr);
f0bd0b68 6083 pci_disable_device(h->pdev);
55c06c71 6084 pci_release_regions(h->pdev);
edd16368
SC		 6085 return err;
6086}
6087
6f039790 6088static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6089{
6090 int rc;
6091
6092#define HBA_INQUIRY_BYTE_COUNT 64
6093 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6094 if (!h->hba_inquiry_data)
6095 return;
6096 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6097 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6098 if (rc != 0) {
6099 kfree(h->hba_inquiry_data);
6100 h->hba_inquiry_data = NULL;
6101 }
6102}
6103
6f039790 6104static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 6105{
1df8552a 6106 int rc, i;
4c2a8c40
SC		 6107
6108 if (!reset_devices)
6109 return 0;
6110
1df8552a
SC		 6111 /* Reset the controller with a PCI power-cycle or via doorbell */
6112 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 6113
1df8552a
SC		 6114 /* -ENOTSUPP here means we cannot reset the controller
6115 * but it's already (and still) up and running in
18867659
SC		 6116 * "performant mode". Or, it might be 640x, which can't reset
6117 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a
SC		 6118 */
6119 if (rc == -ENOTSUPP)
64670ac8 6120 return rc; /* just try to do the kdump anyhow. */
1df8552a
SC		 6121 if (rc)
6122 return -ENODEV;
4c2a8c40
SC		 6123
6124 /* Now try to get the controller to respond to a no-op */
2b870cb3 6125 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6126 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6127 if (hpsa_noop(pdev) == 0)
6128 break;
6129 else
6130 dev_warn(&pdev->dev, "no-op failed%s\n",
6131 (i < 11 ? "; re-trying" : ""));
6132 }
6133 return 0;
6134}
6135
6f039790 6136static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6137{
6138 h->cmd_pool_bits = kzalloc(
6139 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6140 sizeof(unsigned long), GFP_KERNEL);
6141 h->cmd_pool = pci_alloc_consistent(h->pdev,
6142 h->nr_cmds * sizeof(*h->cmd_pool),
6143 &(h->cmd_pool_dhandle));
6144 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6145 h->nr_cmds * sizeof(*h->errinfo_pool),
6146 &(h->errinfo_pool_dhandle));
6147 if ((h->cmd_pool_bits == NULL)
6148 || (h->cmd_pool == NULL)
6149 || (h->errinfo_pool == NULL)) {
6150 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
6151 return -ENOMEM;
6152 }
6153 return 0;
6154}
6155
6156static void hpsa_free_cmd_pool(struct ctlr_info *h)
6157{
6158 kfree(h->cmd_pool_bits);
6159 if (h->cmd_pool)
6160 pci_free_consistent(h->pdev,
6161 h->nr_cmds * sizeof(struct CommandList),
6162 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 6163 if (h->ioaccel2_cmd_pool)
6164 pci_free_consistent(h->pdev,
6165 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6166 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 6167 if (h->errinfo_pool)
6168 pci_free_consistent(h->pdev,
6169 h->nr_cmds * sizeof(struct ErrorInfo),
6170 h->errinfo_pool,
6171 h->errinfo_pool_dhandle);
e1f7de0c
MG		 6172 if (h->ioaccel_cmd_pool)
6173 pci_free_consistent(h->pdev,
6174 h->nr_cmds * sizeof(struct io_accel1_cmd),
6175 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 6176}
6177
0ae01a32
SC		 6178static int hpsa_request_irq(struct ctlr_info *h,
6179 irqreturn_t (*msixhandler)(int, void *),
6180 irqreturn_t (*intxhandler)(int, void *))
6181{
254f796b 6182 int rc, i;
0ae01a32 6183
254f796b
MG		 6184 /*
6185 * initialize h->q[x] = x so that interrupt handlers know which
6186 * queue to process.
6187 */
6188 for (i = 0; i < MAX_REPLY_QUEUES; i++)
6189 h->q[i] = (u8) i;
6190
eee0f03a 6191 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 6192 /* If performant mode and MSI-X, use multiple reply queues */
eee0f03a 6193 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 6194 rc = request_irq(h->intr[i], msixhandler,
6195 0, h->devname,
6196 &h->q[i]);
6197 } else {
6198 /* Use single reply pool */
eee0f03a 6199 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 6200 rc = request_irq(h->intr[h->intr_mode],
6201 msixhandler, 0, h->devname,
6202 &h->q[h->intr_mode]);
6203 } else {
6204 rc = request_irq(h->intr[h->intr_mode],
6205 intxhandler, IRQF_SHARED, h->devname,
6206 &h->q[h->intr_mode]);
6207 }
6208 }
0ae01a32
SC		 6209 if (rc) {
6210 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
6211 h->intr[h->intr_mode], h->devname);
6212 return -ENODEV;
6213 }
6214 return 0;
6215}
6216
6f039790 6217static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 6218{
6219 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6220 HPSA_RESET_TYPE_CONTROLLER)) {
6221 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6222 return -EIO;
6223 }
6224
6225 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6226 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6227 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6228 return -1;
6229 }
6230
6231 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6232 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
6233 dev_warn(&h->pdev->dev, "Board failed to become ready "
6234 "after soft reset.\n");
6235 return -1;
6236 }
6237
6238 return 0;
6239}
6240
254f796b
MG		 6241static void free_irqs(struct ctlr_info *h)
6242{
6243 int i;
6244
6245 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6246 /* Single reply queue, only one irq to free */
6247 i = h->intr_mode;
6248 free_irq(h->intr[i], &h->q[i]);
6249 return;
6250 }
6251
eee0f03a 6252 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 6253 free_irq(h->intr[i], &h->q[i]);
6254}
6255
0097f0f4 6256static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 6257{
254f796b 6258 free_irqs(h);
64670ac8 6259#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6260 if (h->msix_vector) {
6261 if (h->pdev->msix_enabled)
6262 pci_disable_msix(h->pdev);
6263 } else if (h->msi_vector) {
6264 if (h->pdev->msi_enabled)
6265 pci_disable_msi(h->pdev);
6266 }
64670ac8 6267#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6268}
6269
6270static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6271{
6272 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6273 hpsa_free_sg_chain_blocks(h);
6274 hpsa_free_cmd_pool(h);
e1f7de0c 6275 kfree(h->ioaccel1_blockFetchTable);
64670ac8
SC		 6276 kfree(h->blockFetchTable);
6277 pci_free_consistent(h->pdev, h->reply_pool_size,
6278 h->reply_pool, h->reply_pool_dhandle);
6279 if (h->vaddr)
6280 iounmap(h->vaddr);
6281 if (h->transtable)
6282 iounmap(h->transtable);
6283 if (h->cfgtable)
6284 iounmap(h->cfgtable);
6285 pci_release_regions(h->pdev);
6286 kfree(h);
6287}
6288
a0c12413
SC		 6289/* Called when controller lockup detected. */
6290static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
6291{
6292 struct CommandList *c = NULL;
6293
6294 assert_spin_locked(&h->lock);
6295 /* Mark all outstanding commands as failed and complete them. */
6296 while (!list_empty(list)) {
6297 c = list_entry(list->next, struct CommandList, list);
6298 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 6299 finish_cmd(c);
a0c12413
SC		 6300 }
6301}
6302
6303static void controller_lockup_detected(struct ctlr_info *h)
6304{
6305 unsigned long flags;
6306
a0c12413
SC		 6307 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6308 spin_lock_irqsave(&h->lock, flags);
6309 h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6310 spin_unlock_irqrestore(&h->lock, flags);
6311 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
6312 h->lockup_detected);
6313 pci_disable_device(h->pdev);
6314 spin_lock_irqsave(&h->lock, flags);
6315 fail_all_cmds_on_list(h, &h->cmpQ);
6316 fail_all_cmds_on_list(h, &h->reqQ);
6317 spin_unlock_irqrestore(&h->lock, flags);
6318}
6319
a0c12413
SC		 6320static void detect_controller_lockup(struct ctlr_info *h)
6321{
6322 u64 now;
6323 u32 heartbeat;
6324 unsigned long flags;
6325
a0c12413
SC		 6326 now = get_jiffies_64();
6327 /* If we've received an interrupt recently, we're ok. */
6328 if (time_after64(h->last_intr_timestamp +
e85c5974 6329 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6330 return;
6331
6332 /*
6333 * If we've already checked the heartbeat recently, we're ok.
6334 * This could happen if someone sends us a signal. We
6335 * otherwise don't care about signals in this thread.
6336 */
6337 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6338 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6339 return;
6340
6341 /* If heartbeat has not changed since we last looked, we're not ok. */
6342 spin_lock_irqsave(&h->lock, flags);
6343 heartbeat = readl(&h->cfgtable->HeartBeat);
6344 spin_unlock_irqrestore(&h->lock, flags);
6345 if (h->last_heartbeat == heartbeat) {
6346 controller_lockup_detected(h);
6347 return;
6348 }
6349
6350 /* We're ok. */
6351 h->last_heartbeat = heartbeat;
6352 h->last_heartbeat_timestamp = now;
6353}
6354
76438d08
SC		 6355static int hpsa_kickoff_rescan(struct ctlr_info *h)
6356{
6357 int i;
6358 char *event_type;
6359
e863d68e
ST		 6360 /* Clear the driver-requested rescan flag */
6361 h->drv_req_rescan = 0;
6362
76438d08 6363 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6364 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6365 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6366 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6367 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6368
6369 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6370 event_type = "state change";
6371 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6372 event_type = "configuration change";
6373 /* Stop sending new RAID offload reqs via the IO accelerator */
6374 scsi_block_requests(h->scsi_host);
6375 for (i = 0; i < h->ndevices; i++)
6376 h->dev[i]->offload_enabled = 0;
6377 hpsa_drain_commands(h);
6378 /* Set 'accelerator path config change' bit */
6379 dev_warn(&h->pdev->dev,
6380 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
6381 h->events, event_type);
6382 writel(h->events, &(h->cfgtable->clear_event_notify));
6383 /* Set the "clear event notify field update" bit 6 */
6384 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6385 /* Wait until ctlr clears 'clear event notify field', bit 6 */
6386 hpsa_wait_for_clear_event_notify_ack(h);
6387 scsi_unblock_requests(h->scsi_host);
6388 } else {
6389 /* Acknowledge controller notification events. */
6390 writel(h->events, &(h->cfgtable->clear_event_notify));
6391 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6392 hpsa_wait_for_clear_event_notify_ack(h);
6393#if 0
6394 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6395 hpsa_wait_for_mode_change_ack(h);
6396#endif
6397 }
6398
6399 /* Something in the device list may have changed to trigger
6400 * the event, so do a rescan.
6401 */
6402 hpsa_scan_start(h->scsi_host);
6403 /* release reference taken on scsi host in check_controller_events */
6404 scsi_host_put(h->scsi_host);
6405 return 0;
6406}
6407
6408/* Check a register on the controller to see if there are configuration
6409 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 6410 * we should rescan the controller for devices.
6411 * Also check flag for driver-initiated rescan.
6412 * If either flag or controller event indicate rescan, add the controller
76438d08
SC		 6413 * to the list of controllers needing to be rescanned, and gets a
6414 * reference to the associated scsi_host.
6415 */
6416static void hpsa_ctlr_needs_rescan(struct ctlr_info *h)
6417{
6418 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
6419 return;
6420
6421 h->events = readl(&(h->cfgtable->event_notify));
e863d68e 6422 if (!h->events && !h->drv_req_rescan)
76438d08
SC		 6423 return;
6424
6425 /*
6426 * Take a reference on scsi host for the duration of the scan
6427 * Release in hpsa_kickoff_rescan(). No lock needed for scan_list
6428 * as only a single thread accesses this list.
6429 */
6430 scsi_host_get(h->scsi_host);
6431 hpsa_kickoff_rescan(h);
6432}
6433
8a98db73 6434static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6435{
6436 unsigned long flags;
8a98db73
SC		 6437 struct ctlr_info *h = container_of(to_delayed_work(work),
6438 struct ctlr_info, monitor_ctlr_work);
6439 detect_controller_lockup(h);
6440 if (h->lockup_detected)
6441 return;
76438d08 6442 hpsa_ctlr_needs_rescan(h);
8a98db73
SC		 6443 spin_lock_irqsave(&h->lock, flags);
6444 if (h->remove_in_progress) {
6445 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6446 return;
6447 }
8a98db73
SC		 6448 schedule_delayed_work(&h->monitor_ctlr_work,
6449 h->heartbeat_sample_interval);
6450 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6451}
6452
6f039790 6453static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6454{
4c2a8c40 6455 int dac, rc;
edd16368 6456 struct ctlr_info *h;
64670ac8
SC		 6457 int try_soft_reset = 0;
6458 unsigned long flags;
edd16368
SC		 6459
6460 if (number_of_controllers == 0)
6461 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6462
4c2a8c40 6463 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6464 if (rc) {
6465 if (rc != -ENOTSUPP)
6466 return rc;
6467 /* If the reset fails in a particular way (it has no way to do
6468 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6469 * a soft reset once we get the controller configured up to the
6470 * point that it can accept a command.
6471 */
6472 try_soft_reset = 1;
6473 rc = 0;
6474 }
6475
6476reinit_after_soft_reset:
edd16368 6477
303932fd
DB		 6478 /* Command structures must be aligned on a 32-byte boundary because
6479 * the 5 lower bits of the address are used by the hardware. and by
6480 * the driver. See comments in hpsa.h for more info.
6481 */
283b4a9b 6482#define COMMANDLIST_ALIGNMENT 128
303932fd 6483 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6484 h = kzalloc(sizeof(*h), GFP_KERNEL);
6485 if (!h)
ecd9aad4 6486 return -ENOMEM;
edd16368 6487
55c06c71 6488 h->pdev = pdev;
a9a3a273 6489 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 6490 INIT_LIST_HEAD(&h->cmpQ);
6491 INIT_LIST_HEAD(&h->reqQ);
6eaf46fd
SC		 6492 spin_lock_init(&h->lock);
6493 spin_lock_init(&h->scan_lock);
0390f0c0 6494 spin_lock_init(&h->passthru_count_lock);
55c06c71 6495 rc = hpsa_pci_init(h);
ecd9aad4 6496 if (rc != 0)
edd16368
SC		 6497 goto clean1;
6498
f79cfec6 6499 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 6500 h->ctlr = number_of_controllers;
6501 number_of_controllers++;
edd16368
SC		 6502
6503 /* configure PCI DMA stuff */
ecd9aad4
SC		 6504 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6505 if (rc == 0) {
edd16368 6506 dac = 1;
ecd9aad4
SC		 6507 } else {
6508 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6509 if (rc == 0) {
6510 dac = 0;
6511 } else {
6512 dev_err(&pdev->dev, "no suitable DMA available\n");
6513 goto clean1;
6514 }
edd16368
SC		 6515 }
6516
6517 /* make sure the board interrupts are off */
6518 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 6519
0ae01a32 6520 if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 6521 goto clean2;
303932fd
DB		 6522 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
6523 h->devname, pdev->device,
a9a3a273 6524 h->intr[h->intr_mode], dac ? "" : " not");
2e9d1b36 6525 if (hpsa_allocate_cmd_pool(h))
edd16368 6526 goto clean4;
33a2ffce
SC		 6527 if (hpsa_allocate_sg_chain_blocks(h))
6528 goto clean4;
a08a8471
SC		 6529 init_waitqueue_head(&h->scan_wait_queue);
6530 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 6531
6532 pci_set_drvdata(pdev, h);
9a41338e
SC		 6533 h->ndevices = 0;
6534 h->scsi_host = NULL;
6535 spin_lock_init(&h->devlock);
64670ac8
SC		 6536 hpsa_put_ctlr_into_performant_mode(h);
6537
6538 /* At this point, the controller is ready to take commands.
6539 * Now, if reset_devices and the hard reset didn't work, try
6540 * the soft reset and see if that works.
6541 */
6542 if (try_soft_reset) {
6543
6544 /* This is kind of gross. We may or may not get a completion
6545 * from the soft reset command, and if we do, then the value
6546 * from the fifo may or may not be valid. So, we wait 10 secs
6547 * after the reset throwing away any completions we get during
6548 * that time. Unregister the interrupt handler and register
6549 * fake ones to scoop up any residual completions.
6550 */
6551 spin_lock_irqsave(&h->lock, flags);
6552 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6553 spin_unlock_irqrestore(&h->lock, flags);
254f796b 6554 free_irqs(h);
64670ac8
SC		 6555 rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
6556 hpsa_intx_discard_completions);
6557 if (rc) {
6558 dev_warn(&h->pdev->dev, "Failed to request_irq after "
6559 "soft reset.\n");
6560 goto clean4;
6561 }
6562
6563 rc = hpsa_kdump_soft_reset(h);
6564 if (rc)
6565 /* Neither hard nor soft reset worked, we're hosed. */
6566 goto clean4;
6567
6568 dev_info(&h->pdev->dev, "Board READY.\n");
6569 dev_info(&h->pdev->dev,
6570 "Waiting for stale completions to drain.\n");
6571 h->access.set_intr_mask(h, HPSA_INTR_ON);
6572 msleep(10000);
6573 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6574
6575 rc = controller_reset_failed(h->cfgtable);
6576 if (rc)
6577 dev_info(&h->pdev->dev,
6578 "Soft reset appears to have failed.\n");
6579
6580 /* since the controller's reset, we have to go back and re-init
6581 * everything. Easiest to just forget what we've done and do it
6582 * all over again.
6583 */
6584 hpsa_undo_allocations_after_kdump_soft_reset(h);
6585 try_soft_reset = 0;
6586 if (rc)
6587 /* don't go to clean4, we already unallocated */
6588 return -ENODEV;
6589
6590 goto reinit_after_soft_reset;
6591 }
edd16368 6592
da0697bd
ST		 6593 /* Enable Accelerated IO path at driver layer */
6594 h->acciopath_status = 1;
6595
e863d68e
ST		 6596 h->drv_req_rescan = 0;
6597
edd16368
SC		 6598 /* Turn the interrupts on so we can service requests */
6599 h->access.set_intr_mask(h, HPSA_INTR_ON);
6600
339b2b14 6601 hpsa_hba_inquiry(h);
edd16368 6602 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 6603
6604 /* Monitor the controller for firmware lockups */
6605 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
6606 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
6607 schedule_delayed_work(&h->monitor_ctlr_work,
6608 h->heartbeat_sample_interval);
88bf6d62 6609 return 0;
edd16368
SC		 6610
6611clean4:
33a2ffce 6612 hpsa_free_sg_chain_blocks(h);
2e9d1b36 6613 hpsa_free_cmd_pool(h);
254f796b 6614 free_irqs(h);
edd16368
SC		 6615clean2:
6616clean1:
edd16368 6617 kfree(h);
ecd9aad4 6618 return rc;
edd16368
SC		 6619}
6620
6621static void hpsa_flush_cache(struct ctlr_info *h)
6622{
6623 char *flush_buf;
6624 struct CommandList *c;
702890e3
SC		 6625 unsigned long flags;
6626
6627 /* Don't bother trying to flush the cache if locked up */
6628 spin_lock_irqsave(&h->lock, flags);
6629 if (unlikely(h->lockup_detected)) {
6630 spin_unlock_irqrestore(&h->lock, flags);
6631 return;
6632 }
6633 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 6634
6635 flush_buf = kzalloc(4, GFP_KERNEL);
6636 if (!flush_buf)
6637 return;
6638
6639 c = cmd_special_alloc(h);
6640 if (!c) {
6641 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
6642 goto out_of_memory;
6643 }
a2dac136
SC		 6644 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
6645 RAID_CTLR_LUNID, TYPE_CMD)) {
6646 goto out;
6647 }
edd16368
SC		 6648 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
6649 if (c->err_info->CommandStatus != 0)
a2dac136 6650out:
edd16368
SC		 6651 dev_warn(&h->pdev->dev,
6652 "error flushing cache on controller\n");
6653 cmd_special_free(h, c);
6654out_of_memory:
6655 kfree(flush_buf);
6656}
6657
6658static void hpsa_shutdown(struct pci_dev *pdev)
6659{
6660 struct ctlr_info *h;
6661
6662 h = pci_get_drvdata(pdev);
6663 /* Turn board interrupts off and send the flush cache command
6664 * sendcmd will turn off interrupt, and send the flush...
6665 * To write all data in the battery backed cache to disks
6666 */
6667 hpsa_flush_cache(h);
6668 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 6669 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 6670}
6671
6f039790 6672static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 6673{
6674 int i;
6675
6676 for (i = 0; i < h->ndevices; i++)
6677 kfree(h->dev[i]);
6678}
6679
6f039790 6680static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 6681{
6682 struct ctlr_info *h;
8a98db73 6683 unsigned long flags;
edd16368
SC		 6684
6685 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 6686 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 6687 return;
6688 }
6689 h = pci_get_drvdata(pdev);
8a98db73
SC		 6690
6691 /* Get rid of any controller monitoring work items */
6692 spin_lock_irqsave(&h->lock, flags);
6693 h->remove_in_progress = 1;
6694 cancel_delayed_work(&h->monitor_ctlr_work);
6695 spin_unlock_irqrestore(&h->lock, flags);
6696
edd16368
SC		 6697 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
6698 hpsa_shutdown(pdev);
6699 iounmap(h->vaddr);
204892e9
SC		 6700 iounmap(h->transtable);
6701 iounmap(h->cfgtable);
55e14e76 6702 hpsa_free_device_info(h);
33a2ffce 6703 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 6704 pci_free_consistent(h->pdev,
6705 h->nr_cmds * sizeof(struct CommandList),
6706 h->cmd_pool, h->cmd_pool_dhandle);
6707 pci_free_consistent(h->pdev,
6708 h->nr_cmds * sizeof(struct ErrorInfo),
6709 h->errinfo_pool, h->errinfo_pool_dhandle);
303932fd
DB		 6710 pci_free_consistent(h->pdev, h->reply_pool_size,
6711 h->reply_pool, h->reply_pool_dhandle);
edd16368 6712 kfree(h->cmd_pool_bits);
303932fd 6713 kfree(h->blockFetchTable);
e1f7de0c 6714 kfree(h->ioaccel1_blockFetchTable);
aca9012a 6715 kfree(h->ioaccel2_blockFetchTable);
339b2b14 6716 kfree(h->hba_inquiry_data);
f0bd0b68 6717 pci_disable_device(pdev);
edd16368 6718 pci_release_regions(pdev);
edd16368
SC		 6719 kfree(h);
6720}
6721
6722static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
6723 __attribute__((unused)) pm_message_t state)
6724{
6725 return -ENOSYS;
6726}
6727
6728static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
6729{
6730 return -ENOSYS;
6731}
6732
6733static struct pci_driver hpsa_pci_driver = {
f79cfec6 6734 .name = HPSA,
edd16368 6735 .probe = hpsa_init_one,
6f039790 6736 .remove = hpsa_remove_one,
edd16368
SC		 6737 .id_table = hpsa_pci_device_id, /* id_table */
6738 .shutdown = hpsa_shutdown,
6739 .suspend = hpsa_suspend,
6740 .resume = hpsa_resume,
6741};
6742
303932fd
DB		 6743/* Fill in bucket_map[], given nsgs (the max number of
6744 * scatter gather elements supported) and bucket[],
6745 * which is an array of 8 integers. The bucket[] array
6746 * contains 8 different DMA transfer sizes (in 16
6747 * byte increments) which the controller uses to fetch
6748 * commands. This function fills in bucket_map[], which
6749 * maps a given number of scatter gather elements to one of
6750 * the 8 DMA transfer sizes. The point of it is to allow the
6751 * controller to only do as much DMA as needed to fetch the
6752 * command, with the DMA transfer size encoded in the lower
6753 * bits of the command address.
6754 */
6755static void calc_bucket_map(int bucket[], int num_buckets,
e1f7de0c 6756 int nsgs, int min_blocks, int *bucket_map)
303932fd
DB		 6757{
6758 int i, j, b, size;
6759
303932fd
DB		 6760 /* Note, bucket_map must have nsgs+1 entries. */
6761 for (i = 0; i <= nsgs; i++) {
6762 /* Compute size of a command with i SG entries */
e1f7de0c 6763 size = i + min_blocks;
303932fd
DB		 6764 b = num_buckets; /* Assume the biggest bucket */
6765 /* Find the bucket that is just big enough */
e1f7de0c 6766 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 6767 if (bucket[j] >= size) {
6768 b = j;
6769 break;
6770 }
6771 }
6772 /* for a command with i SG entries, use bucket b. */
6773 bucket_map[i] = b;
6774 }
6775}
6776
e1f7de0c 6777static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 6778{
6c311b57
SC		 6779 int i;
6780 unsigned long register_value;
e1f7de0c
MG		 6781 unsigned long transMethod = CFGTBL_Trans_Performant |
6782 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 6783 CFGTBL_Trans_enable_directed_msix |
6784 (trans_support & (CFGTBL_Trans_io_accel1 |
6785 CFGTBL_Trans_io_accel2));
e1f7de0c 6786 struct access_method access = SA5_performant_access;
def342bd
SC		 6787
6788 /* This is a bit complicated. There are 8 registers on
6789 * the controller which we write to to tell it 8 different
6790 * sizes of commands which there may be. It's a way of
6791 * reducing the DMA done to fetch each command. Encoded into
6792 * each command's tag are 3 bits which communicate to the controller
6793 * which of the eight sizes that command fits within. The size of
6794 * each command depends on how many scatter gather entries there are.
6795 * Each SG entry requires 16 bytes. The eight registers are programmed
6796 * with the number of 16-byte blocks a command of that size requires.
6797 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 6798 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 6799 * blocks. Note, this only extends to the SG entries contained
6800 * within the command block, and does not extend to chained blocks
6801 * of SG elements. bft[] contains the eight values we write to
6802 * the registers. They are not evenly distributed, but have more
6803 * sizes for small commands, and fewer sizes for larger commands.
6804 */
d66ae08b 6805 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 6806#define MIN_IOACCEL2_BFT_ENTRY 5
6807#define HPSA_IOACCEL2_HEADER_SZ 4
6808 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
6809 13, 14, 15, 16, 17, 18, 19,
6810 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
6811 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
6812 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
6813 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
6814 16 * MIN_IOACCEL2_BFT_ENTRY);
6815 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 6816 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 6817 /* 5 = 1 s/g entry or 4k
6818 * 6 = 2 s/g entry or 8k
6819 * 8 = 4 s/g entry or 16k
6820 * 10 = 6 s/g entry or 24k
6821 */
303932fd 6822
303932fd
DB		 6823 /* Controller spec: zero out this buffer. */
6824 memset(h->reply_pool, 0, h->reply_pool_size);
303932fd 6825
d66ae08b
SC		 6826 bft[7] = SG_ENTRIES_IN_CMD + 4;
6827 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 6828 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 6829 for (i = 0; i < 8; i++)
6830 writel(bft[i], &h->transtable->BlockFetch[i]);
6831
6832 /* size of controller ring buffer */
6833 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 6834 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 6835 writel(0, &h->transtable->RepQCtrAddrLow32);
6836 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 6837
6838 for (i = 0; i < h->nreply_queues; i++) {
6839 writel(0, &h->transtable->RepQAddr[i].upper);
6840 writel(h->reply_pool_dhandle +
6841 (h->max_commands * sizeof(u64) * i),
6842 &h->transtable->RepQAddr[i].lower);
6843 }
6844
b9af4937 6845 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 6846 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
6847 /*
6848 * enable outbound interrupt coalescing in accelerator mode;
6849 */
6850 if (trans_support & CFGTBL_Trans_io_accel1) {
6851 access = SA5_ioaccel_mode1_access;
6852 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
6853 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 6854 } else {
6855 if (trans_support & CFGTBL_Trans_io_accel2) {
6856 access = SA5_ioaccel_mode2_access;
6857 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
6858 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
6859 }
e1f7de0c 6860 }
303932fd 6861 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 6862 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 6863 register_value = readl(&(h->cfgtable->TransportActive));
6864 if (!(register_value & CFGTBL_Trans_Performant)) {
6865 dev_warn(&h->pdev->dev, "unable to get board into"
6866 " performant mode\n");
6867 return;
6868 }
960a30e7 6869 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 6870 h->access = access;
6871 h->transMethod = transMethod;
6872
b9af4937
SC		 6873 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
6874 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 6875 return;
6876
b9af4937
SC		 6877 if (trans_support & CFGTBL_Trans_io_accel1) {
6878 /* Set up I/O accelerator mode */
6879 for (i = 0; i < h->nreply_queues; i++) {
6880 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
6881 h->reply_queue[i].current_entry =
6882 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
6883 }
6884 bft[7] = h->ioaccel_maxsg + 8;
6885 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
6886 h->ioaccel1_blockFetchTable);
e1f7de0c 6887
b9af4937
SC		 6888 /* initialize all reply queue entries to unused */
6889 memset(h->reply_pool, (u8) IOACCEL_MODE1_REPLY_UNUSED,
6890 h->reply_pool_size);
e1f7de0c 6891
b9af4937
SC		 6892 /* set all the constant fields in the accelerator command
6893 * frames once at init time to save CPU cycles later.
6894 */
6895 for (i = 0; i < h->nr_cmds; i++) {
6896 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
6897
6898 cp->function = IOACCEL1_FUNCTION_SCSIIO;
6899 cp->err_info = (u32) (h->errinfo_pool_dhandle +
6900 (i * sizeof(struct ErrorInfo)));
6901 cp->err_info_len = sizeof(struct ErrorInfo);
6902 cp->sgl_offset = IOACCEL1_SGLOFFSET;
6903 cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT;
6904 cp->timeout_sec = 0;
6905 cp->ReplyQueue = 0;
6906 cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) |
6907 DIRECT_LOOKUP_BIT;
6908 cp->Tag.upper = 0;
6909 cp->host_addr.lower =
6910 (u32) (h->ioaccel_cmd_pool_dhandle +
6911 (i * sizeof(struct io_accel1_cmd)));
6912 cp->host_addr.upper = 0;
6913 }
6914 } else if (trans_support & CFGTBL_Trans_io_accel2) {
6915 u64 cfg_offset, cfg_base_addr_index;
6916 u32 bft2_offset, cfg_base_addr;
6917 int rc;
6918
6919 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6920 &cfg_base_addr_index, &cfg_offset);
6921 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
6922 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
6923 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
6924 4, h->ioaccel2_blockFetchTable);
6925 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
6926 BUILD_BUG_ON(offsetof(struct CfgTable,
6927 io_accel_request_size_offset) != 0xb8);
6928 h->ioaccel2_bft2_regs =
6929 remap_pci_mem(pci_resource_start(h->pdev,
6930 cfg_base_addr_index) +
6931 cfg_offset + bft2_offset,
6932 ARRAY_SIZE(bft2) *
6933 sizeof(*h->ioaccel2_bft2_regs));
6934 for (i = 0; i < ARRAY_SIZE(bft2); i++)
6935 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 6936 }
b9af4937
SC		 6937 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6938 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 6939}
6940
6941static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
6942{
283b4a9b
SC		 6943 h->ioaccel_maxsg =
6944 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
6945 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
6946 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
6947
e1f7de0c
MG		 6948 /* Command structures must be aligned on a 128-byte boundary
6949 * because the 7 lower bits of the address are used by the
6950 * hardware.
6951 */
6952#define IOACCEL1_COMMANDLIST_ALIGNMENT 128
6953 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
6954 IOACCEL1_COMMANDLIST_ALIGNMENT);
6955 h->ioaccel_cmd_pool =
6956 pci_alloc_consistent(h->pdev,
6957 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
6958 &(h->ioaccel_cmd_pool_dhandle));
6959
6960 h->ioaccel1_blockFetchTable =
283b4a9b 6961 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 6962 sizeof(u32)), GFP_KERNEL);
6963
6964 if ((h->ioaccel_cmd_pool == NULL) ||
6965 (h->ioaccel1_blockFetchTable == NULL))
6966 goto clean_up;
6967
6968 memset(h->ioaccel_cmd_pool, 0,
6969 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
6970 return 0;
6971
6972clean_up:
6973 if (h->ioaccel_cmd_pool)
6974 pci_free_consistent(h->pdev,
6975 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
6976 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
6977 kfree(h->ioaccel1_blockFetchTable);
6978 return 1;
6c311b57
SC		 6979}
6980
aca9012a
SC		 6981static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
6982{
6983 /* Allocate ioaccel2 mode command blocks and block fetch table */
6984
6985 h->ioaccel_maxsg =
6986 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
6987 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
6988 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
6989
6990#define IOACCEL2_COMMANDLIST_ALIGNMENT 128
6991 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
6992 IOACCEL2_COMMANDLIST_ALIGNMENT);
6993 h->ioaccel2_cmd_pool =
6994 pci_alloc_consistent(h->pdev,
6995 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6996 &(h->ioaccel2_cmd_pool_dhandle));
6997
6998 h->ioaccel2_blockFetchTable =
6999 kmalloc(((h->ioaccel_maxsg + 1) *
7000 sizeof(u32)), GFP_KERNEL);
7001
7002 if ((h->ioaccel2_cmd_pool == NULL) ||
7003 (h->ioaccel2_blockFetchTable == NULL))
7004 goto clean_up;
7005
7006 memset(h->ioaccel2_cmd_pool, 0,
7007 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
7008 return 0;
7009
7010clean_up:
7011 if (h->ioaccel2_cmd_pool)
7012 pci_free_consistent(h->pdev,
7013 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7014 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
7015 kfree(h->ioaccel2_blockFetchTable);
7016 return 1;
7017}
7018
6f039790 7019static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 7020{
7021 u32 trans_support;
e1f7de0c
MG		 7022 unsigned long transMethod = CFGTBL_Trans_Performant |
7023 CFGTBL_Trans_use_short_tags;
254f796b 7024 int i;
6c311b57 7025
02ec19c8
SC		 7026 if (hpsa_simple_mode)
7027 return;
7028
e1f7de0c
MG		 7029 /* Check for I/O accelerator mode support */
7030 if (trans_support & CFGTBL_Trans_io_accel1) {
7031 transMethod |= CFGTBL_Trans_io_accel1 |
7032 CFGTBL_Trans_enable_directed_msix;
7033 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
7034 goto clean_up;
aca9012a
SC		 7035 } else {
7036 if (trans_support & CFGTBL_Trans_io_accel2) {
7037 transMethod |= CFGTBL_Trans_io_accel2 |
7038 CFGTBL_Trans_enable_directed_msix;
7039 if (ioaccel2_alloc_cmds_and_bft(h))
7040 goto clean_up;
7041 }
e1f7de0c
MG		 7042 }
7043
7044 /* TODO, check that this next line h->nreply_queues is correct */
6c311b57
SC		 7045 trans_support = readl(&(h->cfgtable->TransportSupport));
7046 if (!(trans_support & PERFORMANT_MODE))
7047 return;
7048
eee0f03a 7049 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 7050 hpsa_get_max_perf_mode_cmds(h);
6c311b57 7051 /* Performant mode ring buffer and supporting data structures */
254f796b 7052 h->reply_pool_size = h->max_commands * sizeof(u64) * h->nreply_queues;
6c311b57
SC		 7053 h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
7054 &(h->reply_pool_dhandle));
7055
254f796b
MG		 7056 for (i = 0; i < h->nreply_queues; i++) {
7057 h->reply_queue[i].head = &h->reply_pool[h->max_commands * i];
7058 h->reply_queue[i].size = h->max_commands;
7059 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
7060 h->reply_queue[i].current_entry = 0;
7061 }
7062
6c311b57 7063 /* Need a block fetch table for performant mode */
d66ae08b 7064 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57
SC		 7065 sizeof(u32)), GFP_KERNEL);
7066
7067 if ((h->reply_pool == NULL)
7068 || (h->blockFetchTable == NULL))
7069 goto clean_up;
7070
e1f7de0c 7071 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 7072 return;
7073
7074clean_up:
7075 if (h->reply_pool)
7076 pci_free_consistent(h->pdev, h->reply_pool_size,
7077 h->reply_pool, h->reply_pool_dhandle);
7078 kfree(h->blockFetchTable);
7079}
7080
76438d08
SC		 7081static void hpsa_drain_commands(struct ctlr_info *h)
7082{
7083 int cmds_out;
7084 unsigned long flags;
7085
7086 do { /* wait for all outstanding commands to drain out */
7087 spin_lock_irqsave(&h->lock, flags);
7088 cmds_out = h->commands_outstanding;
7089 spin_unlock_irqrestore(&h->lock, flags);
7090 if (cmds_out <= 0)
7091 break;
7092 msleep(100);
7093 } while (1);
7094}
7095
edd16368
SC		 7096/*
7097 * This is it. Register the PCI driver information for the cards we control
7098 * the OS will call our registered routines when it finds one of our cards.
7099 */
7100static int __init hpsa_init(void)
7101{
31468401 7102 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 7103}
7104
7105static void __exit hpsa_cleanup(void)
7106{
7107 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 7108}
7109
e1f7de0c
MG		 7110static void __attribute__((unused)) verify_offsets(void)
7111{
dd0e19f3
ST		 7112#define VERIFY_OFFSET(member, offset) \
7113 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
7114
7115 VERIFY_OFFSET(structure_size, 0);
7116 VERIFY_OFFSET(volume_blk_size, 4);
7117 VERIFY_OFFSET(volume_blk_cnt, 8);
7118 VERIFY_OFFSET(phys_blk_shift, 16);
7119 VERIFY_OFFSET(parity_rotation_shift, 17);
7120 VERIFY_OFFSET(strip_size, 18);
7121 VERIFY_OFFSET(disk_starting_blk, 20);
7122 VERIFY_OFFSET(disk_blk_cnt, 28);
7123 VERIFY_OFFSET(data_disks_per_row, 36);
7124 VERIFY_OFFSET(metadata_disks_per_row, 38);
7125 VERIFY_OFFSET(row_cnt, 40);
7126 VERIFY_OFFSET(layout_map_count, 42);
7127 VERIFY_OFFSET(flags, 44);
7128 VERIFY_OFFSET(dekindex, 46);
7129 /* VERIFY_OFFSET(reserved, 48 */
7130 VERIFY_OFFSET(data, 64);
7131
7132#undef VERIFY_OFFSET
7133
b66cc250
MM		 7134#define VERIFY_OFFSET(member, offset) \
7135 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
7136
7137 VERIFY_OFFSET(IU_type, 0);
7138 VERIFY_OFFSET(direction, 1);
7139 VERIFY_OFFSET(reply_queue, 2);
7140 /* VERIFY_OFFSET(reserved1, 3); */
7141 VERIFY_OFFSET(scsi_nexus, 4);
7142 VERIFY_OFFSET(Tag, 8);
7143 VERIFY_OFFSET(cdb, 16);
7144 VERIFY_OFFSET(cciss_lun, 32);
7145 VERIFY_OFFSET(data_len, 40);
7146 VERIFY_OFFSET(cmd_priority_task_attr, 44);
7147 VERIFY_OFFSET(sg_count, 45);
7148 /* VERIFY_OFFSET(reserved3 */
7149 VERIFY_OFFSET(err_ptr, 48);
7150 VERIFY_OFFSET(err_len, 56);
7151 /* VERIFY_OFFSET(reserved4 */
7152 VERIFY_OFFSET(sg, 64);
7153
7154#undef VERIFY_OFFSET
7155
e1f7de0c
MG		 7156#define VERIFY_OFFSET(member, offset) \
7157 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
7158
7159 VERIFY_OFFSET(dev_handle, 0x00);
7160 VERIFY_OFFSET(reserved1, 0x02);
7161 VERIFY_OFFSET(function, 0x03);
7162 VERIFY_OFFSET(reserved2, 0x04);
7163 VERIFY_OFFSET(err_info, 0x0C);
7164 VERIFY_OFFSET(reserved3, 0x10);
7165 VERIFY_OFFSET(err_info_len, 0x12);
7166 VERIFY_OFFSET(reserved4, 0x13);
7167 VERIFY_OFFSET(sgl_offset, 0x14);
7168 VERIFY_OFFSET(reserved5, 0x15);
7169 VERIFY_OFFSET(transfer_len, 0x1C);
7170 VERIFY_OFFSET(reserved6, 0x20);
7171 VERIFY_OFFSET(io_flags, 0x24);
7172 VERIFY_OFFSET(reserved7, 0x26);
7173 VERIFY_OFFSET(LUN, 0x34);
7174 VERIFY_OFFSET(control, 0x3C);
7175 VERIFY_OFFSET(CDB, 0x40);
7176 VERIFY_OFFSET(reserved8, 0x50);
7177 VERIFY_OFFSET(host_context_flags, 0x60);
7178 VERIFY_OFFSET(timeout_sec, 0x62);
7179 VERIFY_OFFSET(ReplyQueue, 0x64);
7180 VERIFY_OFFSET(reserved9, 0x65);
7181 VERIFY_OFFSET(Tag, 0x68);
7182 VERIFY_OFFSET(host_addr, 0x70);
7183 VERIFY_OFFSET(CISS_LUN, 0x78);
7184 VERIFY_OFFSET(SG, 0x78 + 8);
7185#undef VERIFY_OFFSET
7186}
7187
edd16368
SC		 7188module_init(hpsa_init);
7189module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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