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hpsa: correct check for non-disk devices
[deliverable/linux.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
1358f6dc
DB		 3 * Copyright 2014-2015 PMC-Sierra, Inc.
4 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
edd16368
SC		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
1358f6dc 15 * Questions/Comments/Bugfixes to storagedev@pmcs.com
edd16368
SC		 16 *
17 */
18
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/types.h>
22#include <linux/pci.h>
e5a44df8 23#include <linux/pci-aspm.h>
edd16368
SC		 24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/fs.h>
28#include <linux/timer.h>
edd16368
SC		 29#include <linux/init.h>
30#include <linux/spinlock.h>
edd16368
SC		 31#include <linux/compat.h>
32#include <linux/blktrace_api.h>
33#include <linux/uaccess.h>
34#include <linux/io.h>
35#include <linux/dma-mapping.h>
36#include <linux/completion.h>
37#include <linux/moduleparam.h>
38#include <scsi/scsi.h>
39#include <scsi/scsi_cmnd.h>
40#include <scsi/scsi_device.h>
41#include <scsi/scsi_host.h>
667e23d4 42#include <scsi/scsi_tcq.h>
9437ac43 43#include <scsi/scsi_eh.h>
73153fe5 44#include <scsi/scsi_dbg.h>
edd16368
SC		 45#include <linux/cciss_ioctl.h>
46#include <linux/string.h>
47#include <linux/bitmap.h>
60063497 48#include <linux/atomic.h>
a0c12413 49#include <linux/jiffies.h>
42a91641 50#include <linux/percpu-defs.h>
094963da 51#include <linux/percpu.h>
2b08b3e9 52#include <asm/unaligned.h>
283b4a9b 53#include <asm/div64.h>
edd16368
SC		 54#include "hpsa_cmd.h"
55#include "hpsa.h"
56
57/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
f532a3f9 58#define HPSA_DRIVER_VERSION "3.4.10-0"
edd16368 59#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 60#define HPSA "hpsa"
edd16368 61
007e7aa9
RE		 62/* How long to wait for CISS doorbell communication */
63#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
64#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
65#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
66#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 67#define MAX_IOCTL_CONFIG_WAIT 1000
68
69/*define how many times we will try a command because of bus resets */
70#define MAX_CMD_RETRIES 3
71
72/* Embedded module documentation macros - see modules.h */
73MODULE_AUTHOR("Hewlett-Packard Company");
74MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
75 HPSA_DRIVER_VERSION);
76MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
77MODULE_VERSION(HPSA_DRIVER_VERSION);
78MODULE_LICENSE("GPL");
79
80static int hpsa_allow_any;
81module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_allow_any,
83 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 84static int hpsa_simple_mode;
85module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
86MODULE_PARM_DESC(hpsa_simple_mode,
87 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 88
89/* define the PCI info for the cards we can control */
90static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
fdfa4b6d 131 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
cbb47dcb
DB		 132 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
133 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
134 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
135 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
8e616a5e
SC		 137 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
138 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
139 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
140 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
141 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 142 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 143 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 144 {0,}
145};
146
147MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
148
149/* board_id = Subsystem Device ID & Vendor ID
150 * product = Marketing Name for the board
151 * access = Address of the struct of function pointers
152 */
153static struct board_type products[] = {
edd16368
SC		 154 {0x3241103C, "Smart Array P212", &SA5_access},
155 {0x3243103C, "Smart Array P410", &SA5_access},
156 {0x3245103C, "Smart Array P410i", &SA5_access},
157 {0x3247103C, "Smart Array P411", &SA5_access},
158 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 159 {0x324A103C, "Smart Array P712m", &SA5_access},
160 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 161 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 162 {0x3350103C, "Smart Array P222", &SA5_access},
163 {0x3351103C, "Smart Array P420", &SA5_access},
164 {0x3352103C, "Smart Array P421", &SA5_access},
165 {0x3353103C, "Smart Array P822", &SA5_access},
166 {0x3354103C, "Smart Array P420i", &SA5_access},
167 {0x3355103C, "Smart Array P220i", &SA5_access},
168 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 169 {0x1921103C, "Smart Array P830i", &SA5_access},
170 {0x1922103C, "Smart Array P430", &SA5_access},
171 {0x1923103C, "Smart Array P431", &SA5_access},
172 {0x1924103C, "Smart Array P830", &SA5_access},
173 {0x1926103C, "Smart Array P731m", &SA5_access},
174 {0x1928103C, "Smart Array P230i", &SA5_access},
175 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 176 {0x21BD103C, "Smart Array P244br", &SA5_access},
177 {0x21BE103C, "Smart Array P741m", &SA5_access},
178 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
179 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 180 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 181 {0x21C2103C, "Smart Array P440", &SA5_access},
182 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 183 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 184 {0x21C5103C, "Smart Array P841", &SA5_access},
185 {0x21C6103C, "Smart HBA H244br", &SA5_access},
186 {0x21C7103C, "Smart HBA H240", &SA5_access},
187 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 188 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 189 {0x21CA103C, "Smart Array P246br", &SA5_access},
190 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 191 {0x21CC103C, "Smart Array", &SA5_access},
192 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 193 {0x21CE103C, "Smart HBA", &SA5_access},
fdfa4b6d 194 {0x05809005, "SmartHBA-SA", &SA5_access},
cbb47dcb
DB		 195 {0x05819005, "SmartHBA-SA 8i", &SA5_access},
196 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
197 {0x05839005, "SmartHBA-SA 8e", &SA5_access},
198 {0x05849005, "SmartHBA-SA 16i", &SA5_access},
199 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
8e616a5e
SC		 200 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
201 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
202 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
203 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
204 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 205 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
206};
207
a58e7e53
WS		 208#define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
209static const struct scsi_cmnd hpsa_cmd_busy;
210#define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
211static const struct scsi_cmnd hpsa_cmd_idle;
edd16368
SC		 212static int number_of_controllers;
213
10f66018
SC		 214static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
215static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 216static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 217
218#ifdef CONFIG_COMPAT
42a91641
DB		 219static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
220 void __user *arg);
edd16368
SC		 221#endif
222
223static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 224static struct CommandList *cmd_alloc(struct ctlr_info *h);
73153fe5
WS		 225static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
226static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
227 struct scsi_cmnd *scmd);
a2dac136 228static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 229 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 230 int cmd_type);
2c143342 231static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 232#define VPD_PAGE (1 << 8)
b48d9804 233#define HPSA_SIMPLE_ERROR_BITS 0x03
edd16368 234
f281233d 235static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 236static void hpsa_scan_start(struct Scsi_Host *);
237static int hpsa_scan_finished(struct Scsi_Host *sh,
238 unsigned long elapsed_time);
7c0a0229 239static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 240
241static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 242static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 243static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 244static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 245static void hpsa_slave_destroy(struct scsi_device *sdev);
246
8aa60681 247static void hpsa_update_scsi_devices(struct ctlr_info *h);
edd16368
SC		 248static int check_for_unit_attention(struct ctlr_info *h,
249 struct CommandList *c);
250static void check_ioctl_unit_attention(struct ctlr_info *h,
251 struct CommandList *c);
303932fd
DB		 252/* performant mode helper functions */
253static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 254 int nsgs, int min_blocks, u32 *bucket_map);
105a3dbc
RE		 255static void hpsa_free_performant_mode(struct ctlr_info *h);
256static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 257static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 258static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
259 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
260 u64 *cfg_offset);
261static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
262 unsigned long *memory_bar);
263static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
264static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
265 int wait_for_ready);
75167d2c 266static inline void finish_cmd(struct CommandList *c);
c706a795 267static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 268#define BOARD_NOT_READY 0
269#define BOARD_READY 1
23100dd9 270static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 271static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 272static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
273 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 274 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 275static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 276static u32 lockup_detected(struct ctlr_info *h);
277static int detect_controller_lockup(struct ctlr_info *h);
8270b862 278static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device);
edd16368 279
edd16368
SC		 280static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
281{
282 unsigned long *priv = shost_priv(sdev->host);
283 return (struct ctlr_info *) *priv;
284}
285
a23513e8
SC		 286static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
287{
288 unsigned long *priv = shost_priv(sh);
289 return (struct ctlr_info *) *priv;
290}
291
a58e7e53
WS		 292static inline bool hpsa_is_cmd_idle(struct CommandList *c)
293{
294 return c->scsi_cmd == SCSI_CMD_IDLE;
295}
296
d604f533
WS		 297static inline bool hpsa_is_pending_event(struct CommandList *c)
298{
299 return c->abort_pending || c->reset_pending;
300}
301
9437ac43
SC		 302/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
303static void decode_sense_data(const u8 *sense_data, int sense_data_len,
304 u8 *sense_key, u8 *asc, u8 *ascq)
305{
306 struct scsi_sense_hdr sshdr;
307 bool rc;
308
309 *sense_key = -1;
310 *asc = -1;
311 *ascq = -1;
312
313 if (sense_data_len < 1)
314 return;
315
316 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
317 if (rc) {
318 *sense_key = sshdr.sense_key;
319 *asc = sshdr.asc;
320 *ascq = sshdr.ascq;
321 }
322}
323
edd16368
SC		 324static int check_for_unit_attention(struct ctlr_info *h,
325 struct CommandList *c)
326{
9437ac43
SC		 327 u8 sense_key, asc, ascq;
328 int sense_len;
329
330 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
331 sense_len = sizeof(c->err_info->SenseInfo);
332 else
333 sense_len = c->err_info->SenseLen;
334
335 decode_sense_data(c->err_info->SenseInfo, sense_len,
336 &sense_key, &asc, &ascq);
81c27557 337 if (sense_key != UNIT_ATTENTION || asc == 0xff)
edd16368
SC		 338 return 0;
339
9437ac43 340 switch (asc) {
edd16368 341 case STATE_CHANGED:
9437ac43 342 dev_warn(&h->pdev->dev,
2946e82b
RE		 343 "%s: a state change detected, command retried\n",
344 h->devname);
edd16368
SC		 345 break;
346 case LUN_FAILED:
7f73695a 347 dev_warn(&h->pdev->dev,
2946e82b 348 "%s: LUN failure detected\n", h->devname);
edd16368
SC		 349 break;
350 case REPORT_LUNS_CHANGED:
7f73695a 351 dev_warn(&h->pdev->dev,
2946e82b 352 "%s: report LUN data changed\n", h->devname);
edd16368 353 /*
4f4eb9f1
ST		 354 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
355 * target (array) devices.
edd16368
SC		 356 */
357 break;
358 case POWER_OR_RESET:
2946e82b
RE		 359 dev_warn(&h->pdev->dev,
360 "%s: a power on or device reset detected\n",
361 h->devname);
edd16368
SC		 362 break;
363 case UNIT_ATTENTION_CLEARED:
2946e82b
RE		 364 dev_warn(&h->pdev->dev,
365 "%s: unit attention cleared by another initiator\n",
366 h->devname);
edd16368
SC		 367 break;
368 default:
2946e82b
RE		 369 dev_warn(&h->pdev->dev,
370 "%s: unknown unit attention detected\n",
371 h->devname);
edd16368
SC		 372 break;
373 }
374 return 1;
375}
376
852af20a
MB		 377static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
378{
379 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
380 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
381 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
382 return 0;
383 dev_warn(&h->pdev->dev, HPSA "device busy");
384 return 1;
385}
386
e985c58f
SC		 387static u32 lockup_detected(struct ctlr_info *h);
388static ssize_t host_show_lockup_detected(struct device *dev,
389 struct device_attribute *attr, char *buf)
390{
391 int ld;
392 struct ctlr_info *h;
393 struct Scsi_Host *shost = class_to_shost(dev);
394
395 h = shost_to_hba(shost);
396 ld = lockup_detected(h);
397
398 return sprintf(buf, "ld=%d\n", ld);
399}
400
da0697bd
ST		 401static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
402 struct device_attribute *attr,
403 const char *buf, size_t count)
404{
405 int status, len;
406 struct ctlr_info *h;
407 struct Scsi_Host *shost = class_to_shost(dev);
408 char tmpbuf[10];
409
410 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
411 return -EACCES;
412 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
413 strncpy(tmpbuf, buf, len);
414 tmpbuf[len] = '\0';
415 if (sscanf(tmpbuf, "%d", &status) != 1)
416 return -EINVAL;
417 h = shost_to_hba(shost);
418 h->acciopath_status = !!status;
419 dev_warn(&h->pdev->dev,
420 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
421 h->acciopath_status ? "enabled" : "disabled");
422 return count;
423}
424
2ba8bfc8
SC		 425static ssize_t host_store_raid_offload_debug(struct device *dev,
426 struct device_attribute *attr,
427 const char *buf, size_t count)
428{
429 int debug_level, len;
430 struct ctlr_info *h;
431 struct Scsi_Host *shost = class_to_shost(dev);
432 char tmpbuf[10];
433
434 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
435 return -EACCES;
436 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
437 strncpy(tmpbuf, buf, len);
438 tmpbuf[len] = '\0';
439 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
440 return -EINVAL;
441 if (debug_level < 0)
442 debug_level = 0;
443 h = shost_to_hba(shost);
444 h->raid_offload_debug = debug_level;
445 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
446 h->raid_offload_debug);
447 return count;
448}
449
edd16368
SC		 450static ssize_t host_store_rescan(struct device *dev,
451 struct device_attribute *attr,
452 const char *buf, size_t count)
453{
454 struct ctlr_info *h;
455 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 456 h = shost_to_hba(shost);
31468401 457 hpsa_scan_start(h->scsi_host);
edd16368
SC		 458 return count;
459}
460
d28ce020
SC		 461static ssize_t host_show_firmware_revision(struct device *dev,
462 struct device_attribute *attr, char *buf)
463{
464 struct ctlr_info *h;
465 struct Scsi_Host *shost = class_to_shost(dev);
466 unsigned char *fwrev;
467
468 h = shost_to_hba(shost);
469 if (!h->hba_inquiry_data)
470 return 0;
471 fwrev = &h->hba_inquiry_data[32];
472 return snprintf(buf, 20, "%c%c%c%c\n",
473 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
474}
475
94a13649
SC		 476static ssize_t host_show_commands_outstanding(struct device *dev,
477 struct device_attribute *attr, char *buf)
478{
479 struct Scsi_Host *shost = class_to_shost(dev);
480 struct ctlr_info *h = shost_to_hba(shost);
481
0cbf768e
SC		 482 return snprintf(buf, 20, "%d\n",
483 atomic_read(&h->commands_outstanding));
94a13649
SC		 484}
485
745a7a25
SC		 486static ssize_t host_show_transport_mode(struct device *dev,
487 struct device_attribute *attr, char *buf)
488{
489 struct ctlr_info *h;
490 struct Scsi_Host *shost = class_to_shost(dev);
491
492 h = shost_to_hba(shost);
493 return snprintf(buf, 20, "%s\n",
960a30e7 494 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 495 "performant" : "simple");
496}
497
da0697bd
ST		 498static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
499 struct device_attribute *attr, char *buf)
500{
501 struct ctlr_info *h;
502 struct Scsi_Host *shost = class_to_shost(dev);
503
504 h = shost_to_hba(shost);
505 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
506 (h->acciopath_status == 1) ? "enabled" : "disabled");
507}
508
46380786 509/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 510static u32 unresettable_controller[] = {
511 0x324a103C, /* Smart Array P712m */
9b5c48c2 512 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 513 0x3223103C, /* Smart Array P800 */
514 0x3234103C, /* Smart Array P400 */
515 0x3235103C, /* Smart Array P400i */
516 0x3211103C, /* Smart Array E200i */
517 0x3212103C, /* Smart Array E200 */
518 0x3213103C, /* Smart Array E200i */
519 0x3214103C, /* Smart Array E200i */
520 0x3215103C, /* Smart Array E200i */
521 0x3237103C, /* Smart Array E500 */
522 0x323D103C, /* Smart Array P700m */
7af0abbc 523 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 524 0x409C0E11, /* Smart Array 6400 */
525 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 526 0x40700E11, /* Smart Array 5300 */
527 0x40820E11, /* Smart Array 532 */
528 0x40830E11, /* Smart Array 5312 */
529 0x409A0E11, /* Smart Array 641 */
530 0x409B0E11, /* Smart Array 642 */
531 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 532};
533
46380786
SC		 534/* List of controllers which cannot even be soft reset */
535static u32 soft_unresettable_controller[] = {
7af0abbc 536 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 537 0x40700E11, /* Smart Array 5300 */
538 0x40820E11, /* Smart Array 532 */
539 0x40830E11, /* Smart Array 5312 */
540 0x409A0E11, /* Smart Array 641 */
541 0x409B0E11, /* Smart Array 642 */
542 0x40910E11, /* Smart Array 6i */
46380786
SC		 543 /* Exclude 640x boards. These are two pci devices in one slot
544 * which share a battery backed cache module. One controls the
545 * cache, the other accesses the cache through the one that controls
546 * it. If we reset the one controlling the cache, the other will
547 * likely not be happy. Just forbid resetting this conjoined mess.
548 * The 640x isn't really supported by hpsa anyway.
549 */
550 0x409C0E11, /* Smart Array 6400 */
551 0x409D0E11, /* Smart Array 6400 EM */
552};
553
9b5c48c2
SC		 554static u32 needs_abort_tags_swizzled[] = {
555 0x323D103C, /* Smart Array P700m */
556 0x324a103C, /* Smart Array P712m */
557 0x324b103C, /* SmartArray P711m */
558};
559
560static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 561{
562 int i;
563
9b5c48c2
SC		 564 for (i = 0; i < nelems; i++)
565 if (a[i] == board_id)
566 return 1;
567 return 0;
46380786
SC		 568}
569
9b5c48c2 570static int ctlr_is_hard_resettable(u32 board_id)
46380786 571{
9b5c48c2
SC		 572 return !board_id_in_array(unresettable_controller,
573 ARRAY_SIZE(unresettable_controller), board_id);
574}
46380786 575
9b5c48c2
SC		 576static int ctlr_is_soft_resettable(u32 board_id)
577{
578 return !board_id_in_array(soft_unresettable_controller,
579 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 580}
581
46380786
SC		 582static int ctlr_is_resettable(u32 board_id)
583{
584 return ctlr_is_hard_resettable(board_id) ||
585 ctlr_is_soft_resettable(board_id);
586}
587
9b5c48c2
SC		 588static int ctlr_needs_abort_tags_swizzled(u32 board_id)
589{
590 return board_id_in_array(needs_abort_tags_swizzled,
591 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
592}
593
941b1cda
SC		 594static ssize_t host_show_resettable(struct device *dev,
595 struct device_attribute *attr, char *buf)
596{
597 struct ctlr_info *h;
598 struct Scsi_Host *shost = class_to_shost(dev);
599
600 h = shost_to_hba(shost);
46380786 601 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 602}
603
edd16368
SC		 604static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
605{
606 return (scsi3addr[3] & 0xC0) == 0x40;
607}
608
f2ef0ce7
RE		 609static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
610 "1(+0)ADM", "UNKNOWN"
edd16368 611};
6b80b18f
ST		 612#define HPSA_RAID_0 0
613#define HPSA_RAID_4 1
614#define HPSA_RAID_1 2 /* also used for RAID 10 */
615#define HPSA_RAID_5 3 /* also used for RAID 50 */
616#define HPSA_RAID_51 4
617#define HPSA_RAID_6 5 /* also used for RAID 60 */
618#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 619#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
620
621static ssize_t raid_level_show(struct device *dev,
622 struct device_attribute *attr, char *buf)
623{
624 ssize_t l = 0;
82a72c0a 625 unsigned char rlevel;
edd16368
SC		 626 struct ctlr_info *h;
627 struct scsi_device *sdev;
628 struct hpsa_scsi_dev_t *hdev;
629 unsigned long flags;
630
631 sdev = to_scsi_device(dev);
632 h = sdev_to_hba(sdev);
633 spin_lock_irqsave(&h->lock, flags);
634 hdev = sdev->hostdata;
635 if (!hdev) {
636 spin_unlock_irqrestore(&h->lock, flags);
637 return -ENODEV;
638 }
639
640 /* Is this even a logical drive? */
641 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
642 spin_unlock_irqrestore(&h->lock, flags);
643 l = snprintf(buf, PAGE_SIZE, "N/A\n");
644 return l;
645 }
646
647 rlevel = hdev->raid_level;
648 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 649 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 650 rlevel = RAID_UNKNOWN;
651 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
652 return l;
653}
654
655static ssize_t lunid_show(struct device *dev,
656 struct device_attribute *attr, char *buf)
657{
658 struct ctlr_info *h;
659 struct scsi_device *sdev;
660 struct hpsa_scsi_dev_t *hdev;
661 unsigned long flags;
662 unsigned char lunid[8];
663
664 sdev = to_scsi_device(dev);
665 h = sdev_to_hba(sdev);
666 spin_lock_irqsave(&h->lock, flags);
667 hdev = sdev->hostdata;
668 if (!hdev) {
669 spin_unlock_irqrestore(&h->lock, flags);
670 return -ENODEV;
671 }
672 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
673 spin_unlock_irqrestore(&h->lock, flags);
674 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
675 lunid[0], lunid[1], lunid[2], lunid[3],
676 lunid[4], lunid[5], lunid[6], lunid[7]);
677}
678
679static ssize_t unique_id_show(struct device *dev,
680 struct device_attribute *attr, char *buf)
681{
682 struct ctlr_info *h;
683 struct scsi_device *sdev;
684 struct hpsa_scsi_dev_t *hdev;
685 unsigned long flags;
686 unsigned char sn[16];
687
688 sdev = to_scsi_device(dev);
689 h = sdev_to_hba(sdev);
690 spin_lock_irqsave(&h->lock, flags);
691 hdev = sdev->hostdata;
692 if (!hdev) {
693 spin_unlock_irqrestore(&h->lock, flags);
694 return -ENODEV;
695 }
696 memcpy(sn, hdev->device_id, sizeof(sn));
697 spin_unlock_irqrestore(&h->lock, flags);
698 return snprintf(buf, 16 * 2 + 2,
699 "%02X%02X%02X%02X%02X%02X%02X%02X"
700 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
701 sn[0], sn[1], sn[2], sn[3],
702 sn[4], sn[5], sn[6], sn[7],
703 sn[8], sn[9], sn[10], sn[11],
704 sn[12], sn[13], sn[14], sn[15]);
705}
706
c1988684
ST		 707static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
708 struct device_attribute *attr, char *buf)
709{
710 struct ctlr_info *h;
711 struct scsi_device *sdev;
712 struct hpsa_scsi_dev_t *hdev;
713 unsigned long flags;
714 int offload_enabled;
715
716 sdev = to_scsi_device(dev);
717 h = sdev_to_hba(sdev);
718 spin_lock_irqsave(&h->lock, flags);
719 hdev = sdev->hostdata;
720 if (!hdev) {
721 spin_unlock_irqrestore(&h->lock, flags);
722 return -ENODEV;
723 }
724 offload_enabled = hdev->offload_enabled;
725 spin_unlock_irqrestore(&h->lock, flags);
726 return snprintf(buf, 20, "%d\n", offload_enabled);
727}
728
8270b862
JH		 729#define MAX_PATHS 8
730#define PATH_STRING_LEN 50
731
732static ssize_t path_info_show(struct device *dev,
733 struct device_attribute *attr, char *buf)
734{
735 struct ctlr_info *h;
736 struct scsi_device *sdev;
737 struct hpsa_scsi_dev_t *hdev;
738 unsigned long flags;
739 int i;
740 int output_len = 0;
741 u8 box;
742 u8 bay;
743 u8 path_map_index = 0;
744 char *active;
745 unsigned char phys_connector[2];
746 unsigned char path[MAX_PATHS][PATH_STRING_LEN];
747
748 memset(path, 0, MAX_PATHS * PATH_STRING_LEN);
749 sdev = to_scsi_device(dev);
750 h = sdev_to_hba(sdev);
751 spin_lock_irqsave(&h->devlock, flags);
752 hdev = sdev->hostdata;
753 if (!hdev) {
754 spin_unlock_irqrestore(&h->devlock, flags);
755 return -ENODEV;
756 }
757
758 bay = hdev->bay;
759 for (i = 0; i < MAX_PATHS; i++) {
760 path_map_index = 1<<i;
761 if (i == hdev->active_path_index)
762 active = "Active";
763 else if (hdev->path_map & path_map_index)
764 active = "Inactive";
765 else
766 continue;
767
768 output_len = snprintf(path[i],
769 PATH_STRING_LEN, "[%d:%d:%d:%d] %20.20s ",
770 h->scsi_host->host_no,
771 hdev->bus, hdev->target, hdev->lun,
772 scsi_device_type(hdev->devtype));
773
774 if (is_ext_target(h, hdev) ||
775 (hdev->devtype == TYPE_RAID) ||
776 is_logical_dev_addr_mode(hdev->scsi3addr)) {
777 output_len += snprintf(path[i] + output_len,
778 PATH_STRING_LEN, "%s\n",
779 active);
780 continue;
781 }
782
783 box = hdev->box[i];
784 memcpy(&phys_connector, &hdev->phys_connector[i],
785 sizeof(phys_connector));
786 if (phys_connector[0] < '0')
787 phys_connector[0] = '0';
788 if (phys_connector[1] < '0')
789 phys_connector[1] = '0';
790 if (hdev->phys_connector[i] > 0)
791 output_len += snprintf(path[i] + output_len,
792 PATH_STRING_LEN,
793 "PORT: %.2s ",
794 phys_connector);
b9092b79
KB		 795 if (hdev->devtype == TYPE_DISK &&
796 hdev->expose_state != HPSA_DO_NOT_EXPOSE) {
8270b862
JH		 797 if (box == 0 || box == 0xFF) {
798 output_len += snprintf(path[i] + output_len,
799 PATH_STRING_LEN,
800 "BAY: %hhu %s\n",
801 bay, active);
802 } else {
803 output_len += snprintf(path[i] + output_len,
804 PATH_STRING_LEN,
805 "BOX: %hhu BAY: %hhu %s\n",
806 box, bay, active);
807 }
808 } else if (box != 0 && box != 0xFF) {
809 output_len += snprintf(path[i] + output_len,
810 PATH_STRING_LEN, "BOX: %hhu %s\n",
811 box, active);
812 } else
813 output_len += snprintf(path[i] + output_len,
814 PATH_STRING_LEN, "%s\n", active);
815 }
816
817 spin_unlock_irqrestore(&h->devlock, flags);
818 return snprintf(buf, output_len+1, "%s%s%s%s%s%s%s%s",
819 path[0], path[1], path[2], path[3],
820 path[4], path[5], path[6], path[7]);
821}
822
3f5eac3a
SC		 823static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
824static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
825static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
826static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 827static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
828 host_show_hp_ssd_smart_path_enabled, NULL);
8270b862 829static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
da0697bd
ST		 830static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
831 host_show_hp_ssd_smart_path_status,
832 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 833static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
834 host_store_raid_offload_debug);
3f5eac3a
SC		 835static DEVICE_ATTR(firmware_revision, S_IRUGO,
836 host_show_firmware_revision, NULL);
837static DEVICE_ATTR(commands_outstanding, S_IRUGO,
838 host_show_commands_outstanding, NULL);
839static DEVICE_ATTR(transport_mode, S_IRUGO,
840 host_show_transport_mode, NULL);
941b1cda
SC		 841static DEVICE_ATTR(resettable, S_IRUGO,
842 host_show_resettable, NULL);
e985c58f
SC		 843static DEVICE_ATTR(lockup_detected, S_IRUGO,
844 host_show_lockup_detected, NULL);
3f5eac3a
SC		 845
846static struct device_attribute *hpsa_sdev_attrs[] = {
847 &dev_attr_raid_level,
848 &dev_attr_lunid,
849 &dev_attr_unique_id,
c1988684 850 &dev_attr_hp_ssd_smart_path_enabled,
8270b862 851 &dev_attr_path_info,
e985c58f 852 &dev_attr_lockup_detected,
3f5eac3a
SC		 853 NULL,
854};
855
856static struct device_attribute *hpsa_shost_attrs[] = {
857 &dev_attr_rescan,
858 &dev_attr_firmware_revision,
859 &dev_attr_commands_outstanding,
860 &dev_attr_transport_mode,
941b1cda 861 &dev_attr_resettable,
da0697bd 862 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 863 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 864 NULL,
865};
866
41ce4c35
SC		 867#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
868 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
869
3f5eac3a
SC		 870static struct scsi_host_template hpsa_driver_template = {
871 .module = THIS_MODULE,
f79cfec6
SC		 872 .name = HPSA,
873 .proc_name = HPSA,
3f5eac3a
SC		 874 .queuecommand = hpsa_scsi_queue_command,
875 .scan_start = hpsa_scan_start,
876 .scan_finished = hpsa_scan_finished,
7c0a0229 877 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 878 .this_id = -1,
879 .use_clustering = ENABLE_CLUSTERING,
75167d2c 880 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 881 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
882 .ioctl = hpsa_ioctl,
883 .slave_alloc = hpsa_slave_alloc,
41ce4c35 884 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 885 .slave_destroy = hpsa_slave_destroy,
886#ifdef CONFIG_COMPAT
887 .compat_ioctl = hpsa_compat_ioctl,
888#endif
889 .sdev_attrs = hpsa_sdev_attrs,
890 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 891 .max_sectors = 8192,
54b2b50c 892 .no_write_same = 1,
3f5eac3a
SC		 893};
894
254f796b 895static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 896{
897 u32 a;
072b0518 898 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 899
e1f7de0c
MG		 900 if (h->transMethod & CFGTBL_Trans_io_accel1)
901 return h->access.command_completed(h, q);
902
3f5eac3a 903 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 904 return h->access.command_completed(h, q);
3f5eac3a 905
254f796b
MG		 906 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
907 a = rq->head[rq->current_entry];
908 rq->current_entry++;
0cbf768e 909 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 910 } else {
911 a = FIFO_EMPTY;
912 }
913 /* Check for wraparound */
254f796b
MG		 914 if (rq->current_entry == h->max_commands) {
915 rq->current_entry = 0;
916 rq->wraparound ^= 1;
3f5eac3a
SC		 917 }
918 return a;
919}
920
c349775e
ST		 921/*
922 * There are some special bits in the bus address of the
923 * command that we have to set for the controller to know
924 * how to process the command:
925 *
926 * Normal performant mode:
927 * bit 0: 1 means performant mode, 0 means simple mode.
928 * bits 1-3 = block fetch table entry
929 * bits 4-6 = command type (== 0)
930 *
931 * ioaccel1 mode:
932 * bit 0 = "performant mode" bit.
933 * bits 1-3 = block fetch table entry
934 * bits 4-6 = command type (== 110)
935 * (command type is needed because ioaccel1 mode
936 * commands are submitted through the same register as normal
937 * mode commands, so this is how the controller knows whether
938 * the command is normal mode or ioaccel1 mode.)
939 *
940 * ioaccel2 mode:
941 * bit 0 = "performant mode" bit.
942 * bits 1-4 = block fetch table entry (note extra bit)
943 * bits 4-6 = not needed, because ioaccel2 mode has
944 * a separate special register for submitting commands.
945 */
946
25163bd5
WS		 947/*
948 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 949 * set bit 0 for pull model, bits 3-1 for block fetch
950 * register number
951 */
25163bd5
WS		 952#define DEFAULT_REPLY_QUEUE (-1)
953static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
954 int reply_queue)
3f5eac3a 955{
254f796b 956 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 957 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 958 if (unlikely(!h->msix_vector))
959 return;
960 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 961 c->Header.ReplyQueue =
804a5cb5 962 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 963 else
964 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 965 }
3f5eac3a
SC		 966}
967
c349775e 968static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 969 struct CommandList *c,
970 int reply_queue)
c349775e
ST		 971{
972 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
973
25163bd5
WS		 974 /*
975 * Tell the controller to post the reply to the queue for this
c349775e
ST		 976 * processor. This seems to give the best I/O throughput.
977 */
25163bd5
WS		 978 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
979 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
980 else
981 cp->ReplyQueue = reply_queue % h->nreply_queues;
982 /*
983 * Set the bits in the address sent down to include:
c349775e
ST		 984 * - performant mode bit (bit 0)
985 * - pull count (bits 1-3)
986 * - command type (bits 4-6)
987 */
988 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
989 IOACCEL1_BUSADDR_CMDTYPE;
990}
991
8be986cc
SC		 992static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
993 struct CommandList *c,
994 int reply_queue)
995{
996 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
997 &h->ioaccel2_cmd_pool[c->cmdindex];
998
999 /* Tell the controller to post the reply to the queue for this
1000 * processor. This seems to give the best I/O throughput.
1001 */
1002 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1003 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1004 else
1005 cp->reply_queue = reply_queue % h->nreply_queues;
1006 /* Set the bits in the address sent down to include:
1007 * - performant mode bit not used in ioaccel mode 2
1008 * - pull count (bits 0-3)
1009 * - command type isn't needed for ioaccel2
1010 */
1011 c->busaddr |= h->ioaccel2_blockFetchTable[0];
1012}
1013
c349775e 1014static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1015 struct CommandList *c,
1016 int reply_queue)
c349775e
ST		 1017{
1018 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
1019
25163bd5
WS		 1020 /*
1021 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1022 * processor. This seems to give the best I/O throughput.
1023 */
25163bd5
WS		 1024 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1025 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1026 else
1027 cp->reply_queue = reply_queue % h->nreply_queues;
1028 /*
1029 * Set the bits in the address sent down to include:
c349775e
ST		 1030 * - performant mode bit not used in ioaccel mode 2
1031 * - pull count (bits 0-3)
1032 * - command type isn't needed for ioaccel2
1033 */
1034 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
1035}
1036
e85c5974
SC		 1037static int is_firmware_flash_cmd(u8 *cdb)
1038{
1039 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
1040}
1041
1042/*
1043 * During firmware flash, the heartbeat register may not update as frequently
1044 * as it should. So we dial down lockup detection during firmware flash. and
1045 * dial it back up when firmware flash completes.
1046 */
1047#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
1048#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
1049static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
1050 struct CommandList *c)
1051{
1052 if (!is_firmware_flash_cmd(c->Request.CDB))
1053 return;
1054 atomic_inc(&h->firmware_flash_in_progress);
1055 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
1056}
1057
1058static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
1059 struct CommandList *c)
1060{
1061 if (is_firmware_flash_cmd(c->Request.CDB) &&
1062 atomic_dec_and_test(&h->firmware_flash_in_progress))
1063 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
1064}
1065
25163bd5
WS		 1066static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
1067 struct CommandList *c, int reply_queue)
3f5eac3a 1068{
c05e8866
SC		 1069 dial_down_lockup_detection_during_fw_flash(h, c);
1070 atomic_inc(&h->commands_outstanding);
c349775e
ST		 1071 switch (c->cmd_type) {
1072 case CMD_IOACCEL1:
25163bd5 1073 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 1074 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 1075 break;
1076 case CMD_IOACCEL2:
25163bd5 1077 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 1078 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e 1079 break;
8be986cc
SC		 1080 case IOACCEL2_TMF:
1081 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
1082 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1083 break;
c349775e 1084 default:
25163bd5 1085 set_performant_mode(h, c, reply_queue);
c05e8866 1086 h->access.submit_command(h, c);
c349775e 1087 }
3f5eac3a
SC		 1088}
1089
a58e7e53 1090static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
25163bd5 1091{
d604f533 1092 if (unlikely(hpsa_is_pending_event(c)))
a58e7e53
WS		 1093 return finish_cmd(c);
1094
25163bd5
WS		 1095 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
1096}
1097
3f5eac3a
SC		 1098static inline int is_hba_lunid(unsigned char scsi3addr[])
1099{
1100 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
1101}
1102
1103static inline int is_scsi_rev_5(struct ctlr_info *h)
1104{
1105 if (!h->hba_inquiry_data)
1106 return 0;
1107 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1108 return 1;
1109 return 0;
1110}
1111
edd16368
SC		 1112static int hpsa_find_target_lun(struct ctlr_info *h,
1113 unsigned char scsi3addr[], int bus, int *target, int *lun)
1114{
1115 /* finds an unused bus, target, lun for a new physical device
1116 * assumes h->devlock is held
1117 */
1118 int i, found = 0;
cfe5badc 1119 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 1120
263d9401 1121 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 1122
1123 for (i = 0; i < h->ndevices; i++) {
1124 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 1125 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 1126 }
1127
263d9401
AM		 1128 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1129 if (i < HPSA_MAX_DEVICES) {
1130 /* *bus = 1; */
1131 *target = i;
1132 *lun = 0;
1133 found = 1;
edd16368
SC		 1134 }
1135 return !found;
1136}
1137
1d33d85d 1138static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
0d96ef5f
WS		 1139 struct hpsa_scsi_dev_t *dev, char *description)
1140{
9975ec9d
DB		 1141 if (h == NULL || h->pdev == NULL || h->scsi_host == NULL)
1142 return;
1143
0d96ef5f
WS		 1144 dev_printk(level, &h->pdev->dev,
1145 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
1146 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1147 description,
1148 scsi_device_type(dev->devtype),
1149 dev->vendor,
1150 dev->model,
1151 dev->raid_level > RAID_UNKNOWN ?
1152 "RAID-?" : raid_label[dev->raid_level],
1153 dev->offload_config ? '+' : '-',
1154 dev->offload_enabled ? '+' : '-',
1155 dev->expose_state);
1156}
1157
edd16368 1158/* Add an entry into h->dev[] array. */
8aa60681 1159static int hpsa_scsi_add_entry(struct ctlr_info *h,
edd16368
SC		 1160 struct hpsa_scsi_dev_t *device,
1161 struct hpsa_scsi_dev_t *added[], int *nadded)
1162{
1163 /* assumes h->devlock is held */
1164 int n = h->ndevices;
1165 int i;
1166 unsigned char addr1[8], addr2[8];
1167 struct hpsa_scsi_dev_t *sd;
1168
cfe5badc 1169 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1170 dev_err(&h->pdev->dev, "too many devices, some will be "
1171 "inaccessible.\n");
1172 return -1;
1173 }
1174
1175 /* physical devices do not have lun or target assigned until now. */
1176 if (device->lun != -1)
1177 /* Logical device, lun is already assigned. */
1178 goto lun_assigned;
1179
1180 /* If this device a non-zero lun of a multi-lun device
1181 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1182 * unit no, zero otherwise.
edd16368
SC		 1183 */
1184 if (device->scsi3addr[4] == 0) {
1185 /* This is not a non-zero lun of a multi-lun device */
1186 if (hpsa_find_target_lun(h, device->scsi3addr,
1187 device->bus, &device->target, &device->lun) != 0)
1188 return -1;
1189 goto lun_assigned;
1190 }
1191
1192 /* This is a non-zero lun of a multi-lun device.
1193 * Search through our list and find the device which
9a4178b7 1194 * has the same 8 byte LUN address, excepting byte 4 and 5.
edd16368
SC		 1195 * Assign the same bus and target for this new LUN.
1196 * Use the logical unit number from the firmware.
1197 */
1198 memcpy(addr1, device->scsi3addr, 8);
1199 addr1[4] = 0;
9a4178b7 1200 addr1[5] = 0;
edd16368
SC		 1201 for (i = 0; i < n; i++) {
1202 sd = h->dev[i];
1203 memcpy(addr2, sd->scsi3addr, 8);
1204 addr2[4] = 0;
9a4178b7 1205 addr2[5] = 0;
1206 /* differ only in byte 4 and 5? */
edd16368
SC		 1207 if (memcmp(addr1, addr2, 8) == 0) {
1208 device->bus = sd->bus;
1209 device->target = sd->target;
1210 device->lun = device->scsi3addr[4];
1211 break;
1212 }
1213 }
1214 if (device->lun == -1) {
1215 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1216 " suspect firmware bug or unsupported hardware "
1217 "configuration.\n");
1218 return -1;
1219 }
1220
1221lun_assigned:
1222
1223 h->dev[n] = device;
1224 h->ndevices++;
1225 added[*nadded] = device;
1226 (*nadded)++;
0d96ef5f
WS		 1227 hpsa_show_dev_msg(KERN_INFO, h, device,
1228 device->expose_state & HPSA_SCSI_ADD ? "added" : "masked");
a473d86c
RE		 1229 device->offload_to_be_enabled = device->offload_enabled;
1230 device->offload_enabled = 0;
edd16368
SC		 1231 return 0;
1232}
1233
bd9244f7 1234/* Update an entry in h->dev[] array. */
8aa60681 1235static void hpsa_scsi_update_entry(struct ctlr_info *h,
bd9244f7
ST		 1236 int entry, struct hpsa_scsi_dev_t *new_entry)
1237{
a473d86c 1238 int offload_enabled;
bd9244f7
ST		 1239 /* assumes h->devlock is held */
1240 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1241
1242 /* Raid level changed. */
1243 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1244
03383736
DB		 1245 /* Raid offload parameters changed. Careful about the ordering. */
1246 if (new_entry->offload_config && new_entry->offload_enabled) {
1247 /*
1248 * if drive is newly offload_enabled, we want to copy the
1249 * raid map data first. If previously offload_enabled and
1250 * offload_config were set, raid map data had better be
1251 * the same as it was before. if raid map data is changed
1252 * then it had better be the case that
1253 * h->dev[entry]->offload_enabled is currently 0.
1254 */
1255 h->dev[entry]->raid_map = new_entry->raid_map;
1256 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1257 }
a3144e0b
JH		 1258 if (new_entry->hba_ioaccel_enabled) {
1259 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1260 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1261 }
1262 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1263 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1264 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1265 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1266
41ce4c35
SC		 1267 /*
1268 * We can turn off ioaccel offload now, but need to delay turning
1269 * it on until we can update h->dev[entry]->phys_disk[], but we
1270 * can't do that until all the devices are updated.
1271 */
1272 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1273 if (!new_entry->offload_enabled)
1274 h->dev[entry]->offload_enabled = 0;
1275
a473d86c
RE		 1276 offload_enabled = h->dev[entry]->offload_enabled;
1277 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1278 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1279 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1280}
1281
2a8ccf31 1282/* Replace an entry from h->dev[] array. */
8aa60681 1283static void hpsa_scsi_replace_entry(struct ctlr_info *h,
2a8ccf31
SC		 1284 int entry, struct hpsa_scsi_dev_t *new_entry,
1285 struct hpsa_scsi_dev_t *added[], int *nadded,
1286 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1287{
1288 /* assumes h->devlock is held */
cfe5badc 1289 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1290 removed[*nremoved] = h->dev[entry];
1291 (*nremoved)++;
01350d05
SC		 1292
1293 /*
1294 * New physical devices won't have target/lun assigned yet
1295 * so we need to preserve the values in the slot we are replacing.
1296 */
1297 if (new_entry->target == -1) {
1298 new_entry->target = h->dev[entry]->target;
1299 new_entry->lun = h->dev[entry]->lun;
1300 }
1301
2a8ccf31
SC		 1302 h->dev[entry] = new_entry;
1303 added[*nadded] = new_entry;
1304 (*nadded)++;
0d96ef5f 1305 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1306 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1307 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1308}
1309
edd16368 1310/* Remove an entry from h->dev[] array. */
8aa60681 1311static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
edd16368
SC		 1312 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1313{
1314 /* assumes h->devlock is held */
1315 int i;
1316 struct hpsa_scsi_dev_t *sd;
1317
cfe5badc 1318 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1319
1320 sd = h->dev[entry];
1321 removed[*nremoved] = h->dev[entry];
1322 (*nremoved)++;
1323
1324 for (i = entry; i < h->ndevices-1; i++)
1325 h->dev[i] = h->dev[i+1];
1326 h->ndevices--;
0d96ef5f 1327 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1328}
1329
1330#define SCSI3ADDR_EQ(a, b) ( \
1331 (a)[7] == (b)[7] && \
1332 (a)[6] == (b)[6] && \
1333 (a)[5] == (b)[5] && \
1334 (a)[4] == (b)[4] && \
1335 (a)[3] == (b)[3] && \
1336 (a)[2] == (b)[2] && \
1337 (a)[1] == (b)[1] && \
1338 (a)[0] == (b)[0])
1339
1340static void fixup_botched_add(struct ctlr_info *h,
1341 struct hpsa_scsi_dev_t *added)
1342{
1343 /* called when scsi_add_device fails in order to re-adjust
1344 * h->dev[] to match the mid layer's view.
1345 */
1346 unsigned long flags;
1347 int i, j;
1348
1349 spin_lock_irqsave(&h->lock, flags);
1350 for (i = 0; i < h->ndevices; i++) {
1351 if (h->dev[i] == added) {
1352 for (j = i; j < h->ndevices-1; j++)
1353 h->dev[j] = h->dev[j+1];
1354 h->ndevices--;
1355 break;
1356 }
1357 }
1358 spin_unlock_irqrestore(&h->lock, flags);
1359 kfree(added);
1360}
1361
1362static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1363 struct hpsa_scsi_dev_t *dev2)
1364{
edd16368
SC		 1365 /* we compare everything except lun and target as these
1366 * are not yet assigned. Compare parts likely
1367 * to differ first
1368 */
1369 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1370 sizeof(dev1->scsi3addr)) != 0)
1371 return 0;
1372 if (memcmp(dev1->device_id, dev2->device_id,
1373 sizeof(dev1->device_id)) != 0)
1374 return 0;
1375 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1376 return 0;
1377 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1378 return 0;
edd16368
SC		 1379 if (dev1->devtype != dev2->devtype)
1380 return 0;
edd16368
SC		 1381 if (dev1->bus != dev2->bus)
1382 return 0;
1383 return 1;
1384}
1385
bd9244f7
ST		 1386static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1387 struct hpsa_scsi_dev_t *dev2)
1388{
1389 /* Device attributes that can change, but don't mean
1390 * that the device is a different device, nor that the OS
1391 * needs to be told anything about the change.
1392 */
1393 if (dev1->raid_level != dev2->raid_level)
1394 return 1;
250fb125
SC		 1395 if (dev1->offload_config != dev2->offload_config)
1396 return 1;
1397 if (dev1->offload_enabled != dev2->offload_enabled)
1398 return 1;
93849508
DB		 1399 if (!is_logical_dev_addr_mode(dev1->scsi3addr))
1400 if (dev1->queue_depth != dev2->queue_depth)
1401 return 1;
bd9244f7
ST		 1402 return 0;
1403}
1404
edd16368
SC		 1405/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1406 * and return needle location in *index. If scsi3addr matches, but not
1407 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1408 * location in *index.
1409 * In the case of a minor device attribute change, such as RAID level, just
1410 * return DEVICE_UPDATED, along with the updated device's location in index.
1411 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1412 */
1413static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1414 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1415 int *index)
1416{
1417 int i;
1418#define DEVICE_NOT_FOUND 0
1419#define DEVICE_CHANGED 1
1420#define DEVICE_SAME 2
bd9244f7 1421#define DEVICE_UPDATED 3
1d33d85d
DB		 1422 if (needle == NULL)
1423 return DEVICE_NOT_FOUND;
1424
edd16368 1425 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1426 if (haystack[i] == NULL) /* previously removed. */
1427 continue;
edd16368
SC		 1428 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1429 *index = i;
bd9244f7
ST		 1430 if (device_is_the_same(needle, haystack[i])) {
1431 if (device_updated(needle, haystack[i]))
1432 return DEVICE_UPDATED;
edd16368 1433 return DEVICE_SAME;
bd9244f7 1434 } else {
9846590e
SC		 1435 /* Keep offline devices offline */
1436 if (needle->volume_offline)
1437 return DEVICE_NOT_FOUND;
edd16368 1438 return DEVICE_CHANGED;
bd9244f7 1439 }
edd16368
SC		 1440 }
1441 }
1442 *index = -1;
1443 return DEVICE_NOT_FOUND;
1444}
1445
9846590e
SC		 1446static void hpsa_monitor_offline_device(struct ctlr_info *h,
1447 unsigned char scsi3addr[])
1448{
1449 struct offline_device_entry *device;
1450 unsigned long flags;
1451
1452 /* Check to see if device is already on the list */
1453 spin_lock_irqsave(&h->offline_device_lock, flags);
1454 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1455 if (memcmp(device->scsi3addr, scsi3addr,
1456 sizeof(device->scsi3addr)) == 0) {
1457 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1458 return;
1459 }
1460 }
1461 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1462
1463 /* Device is not on the list, add it. */
1464 device = kmalloc(sizeof(*device), GFP_KERNEL);
1465 if (!device) {
1466 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1467 return;
1468 }
1469 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1470 spin_lock_irqsave(&h->offline_device_lock, flags);
1471 list_add_tail(&device->offline_list, &h->offline_device_list);
1472 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1473}
1474
1475/* Print a message explaining various offline volume states */
1476static void hpsa_show_volume_status(struct ctlr_info *h,
1477 struct hpsa_scsi_dev_t *sd)
1478{
1479 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1480 dev_info(&h->pdev->dev,
1481 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1482 h->scsi_host->host_no,
1483 sd->bus, sd->target, sd->lun);
1484 switch (sd->volume_offline) {
1485 case HPSA_LV_OK:
1486 break;
1487 case HPSA_LV_UNDERGOING_ERASE:
1488 dev_info(&h->pdev->dev,
1489 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1490 h->scsi_host->host_no,
1491 sd->bus, sd->target, sd->lun);
1492 break;
5ca01204
SB		 1493 case HPSA_LV_NOT_AVAILABLE:
1494 dev_info(&h->pdev->dev,
1495 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
1496 h->scsi_host->host_no,
1497 sd->bus, sd->target, sd->lun);
1498 break;
9846590e
SC		 1499 case HPSA_LV_UNDERGOING_RPI:
1500 dev_info(&h->pdev->dev,
5ca01204 1501 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
9846590e
SC		 1502 h->scsi_host->host_no,
1503 sd->bus, sd->target, sd->lun);
1504 break;
1505 case HPSA_LV_PENDING_RPI:
1506 dev_info(&h->pdev->dev,
5ca01204
SB		 1507 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1508 h->scsi_host->host_no,
1509 sd->bus, sd->target, sd->lun);
9846590e
SC		 1510 break;
1511 case HPSA_LV_ENCRYPTED_NO_KEY:
1512 dev_info(&h->pdev->dev,
1513 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1514 h->scsi_host->host_no,
1515 sd->bus, sd->target, sd->lun);
1516 break;
1517 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1518 dev_info(&h->pdev->dev,
1519 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1520 h->scsi_host->host_no,
1521 sd->bus, sd->target, sd->lun);
1522 break;
1523 case HPSA_LV_UNDERGOING_ENCRYPTION:
1524 dev_info(&h->pdev->dev,
1525 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1526 h->scsi_host->host_no,
1527 sd->bus, sd->target, sd->lun);
1528 break;
1529 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1530 dev_info(&h->pdev->dev,
1531 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1532 h->scsi_host->host_no,
1533 sd->bus, sd->target, sd->lun);
1534 break;
1535 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1536 dev_info(&h->pdev->dev,
1537 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1538 h->scsi_host->host_no,
1539 sd->bus, sd->target, sd->lun);
1540 break;
1541 case HPSA_LV_PENDING_ENCRYPTION:
1542 dev_info(&h->pdev->dev,
1543 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1544 h->scsi_host->host_no,
1545 sd->bus, sd->target, sd->lun);
1546 break;
1547 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1548 dev_info(&h->pdev->dev,
1549 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1550 h->scsi_host->host_no,
1551 sd->bus, sd->target, sd->lun);
1552 break;
1553 }
1554}
1555
03383736
DB		 1556/*
1557 * Figure the list of physical drive pointers for a logical drive with
1558 * raid offload configured.
1559 */
1560static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1561 struct hpsa_scsi_dev_t *dev[], int ndevices,
1562 struct hpsa_scsi_dev_t *logical_drive)
1563{
1564 struct raid_map_data *map = &logical_drive->raid_map;
1565 struct raid_map_disk_data *dd = &map->data[0];
1566 int i, j;
1567 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1568 le16_to_cpu(map->metadata_disks_per_row);
1569 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1570 le16_to_cpu(map->layout_map_count) *
1571 total_disks_per_row;
1572 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1573 total_disks_per_row;
1574 int qdepth;
1575
1576 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1577 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1578
d604f533
WS		 1579 logical_drive->nphysical_disks = nraid_map_entries;
1580
03383736
DB		 1581 qdepth = 0;
1582 for (i = 0; i < nraid_map_entries; i++) {
1583 logical_drive->phys_disk[i] = NULL;
1584 if (!logical_drive->offload_config)
1585 continue;
1586 for (j = 0; j < ndevices; j++) {
1d33d85d
DB		 1587 if (dev[j] == NULL)
1588 continue;
03383736
DB		 1589 if (dev[j]->devtype != TYPE_DISK)
1590 continue;
1591 if (is_logical_dev_addr_mode(dev[j]->scsi3addr))
1592 continue;
1593 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1594 continue;
1595
1596 logical_drive->phys_disk[i] = dev[j];
1597 if (i < nphys_disk)
1598 qdepth = min(h->nr_cmds, qdepth +
1599 logical_drive->phys_disk[i]->queue_depth);
1600 break;
1601 }
1602
1603 /*
1604 * This can happen if a physical drive is removed and
1605 * the logical drive is degraded. In that case, the RAID
1606 * map data will refer to a physical disk which isn't actually
1607 * present. And in that case offload_enabled should already
1608 * be 0, but we'll turn it off here just in case
1609 */
1610 if (!logical_drive->phys_disk[i]) {
1611 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1612 logical_drive->offload_to_be_enabled = 0;
1613 logical_drive->queue_depth = 8;
03383736
DB		 1614 }
1615 }
1616 if (nraid_map_entries)
1617 /*
1618 * This is correct for reads, too high for full stripe writes,
1619 * way too high for partial stripe writes
1620 */
1621 logical_drive->queue_depth = qdepth;
1622 else
1623 logical_drive->queue_depth = h->nr_cmds;
1624}
1625
1626static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1627 struct hpsa_scsi_dev_t *dev[], int ndevices)
1628{
1629 int i;
1630
1631 for (i = 0; i < ndevices; i++) {
1d33d85d
DB		 1632 if (dev[i] == NULL)
1633 continue;
03383736
DB		 1634 if (dev[i]->devtype != TYPE_DISK)
1635 continue;
1636 if (!is_logical_dev_addr_mode(dev[i]->scsi3addr))
1637 continue;
41ce4c35
SC		 1638
1639 /*
1640 * If offload is currently enabled, the RAID map and
1641 * phys_disk[] assignment *better* not be changing
1642 * and since it isn't changing, we do not need to
1643 * update it.
1644 */
1645 if (dev[i]->offload_enabled)
1646 continue;
1647
03383736
DB		 1648 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1649 }
1650}
1651
8aa60681 1652static void adjust_hpsa_scsi_table(struct ctlr_info *h,
edd16368
SC		 1653 struct hpsa_scsi_dev_t *sd[], int nsds)
1654{
1655 /* sd contains scsi3 addresses and devtypes, and inquiry
1656 * data. This function takes what's in sd to be the current
1657 * reality and updates h->dev[] to reflect that reality.
1658 */
1659 int i, entry, device_change, changes = 0;
1660 struct hpsa_scsi_dev_t *csd;
1661 unsigned long flags;
1662 struct hpsa_scsi_dev_t **added, **removed;
1663 int nadded, nremoved;
1664 struct Scsi_Host *sh = NULL;
1665
da03ded0
DB		 1666 /*
1667 * A reset can cause a device status to change
1668 * re-schedule the scan to see what happened.
1669 */
1670 if (h->reset_in_progress) {
1671 h->drv_req_rescan = 1;
1672 return;
1673 }
1674
cfe5badc
ST		 1675 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1676 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1677
1678 if (!added || !removed) {
1679 dev_warn(&h->pdev->dev, "out of memory in "
1680 "adjust_hpsa_scsi_table\n");
1681 goto free_and_out;
1682 }
1683
1684 spin_lock_irqsave(&h->devlock, flags);
1685
1686 /* find any devices in h->dev[] that are not in
1687 * sd[] and remove them from h->dev[], and for any
1688 * devices which have changed, remove the old device
1689 * info and add the new device info.
bd9244f7
ST		 1690 * If minor device attributes change, just update
1691 * the existing device structure.
edd16368
SC		 1692 */
1693 i = 0;
1694 nremoved = 0;
1695 nadded = 0;
1696 while (i < h->ndevices) {
1697 csd = h->dev[i];
1698 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1699 if (device_change == DEVICE_NOT_FOUND) {
1700 changes++;
8aa60681 1701 hpsa_scsi_remove_entry(h, i, removed, &nremoved);
edd16368
SC		 1702 continue; /* remove ^^^, hence i not incremented */
1703 } else if (device_change == DEVICE_CHANGED) {
1704 changes++;
8aa60681 1705 hpsa_scsi_replace_entry(h, i, sd[entry],
2a8ccf31 1706 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1707 /* Set it to NULL to prevent it from being freed
1708 * at the bottom of hpsa_update_scsi_devices()
1709 */
1710 sd[entry] = NULL;
bd9244f7 1711 } else if (device_change == DEVICE_UPDATED) {
8aa60681 1712 hpsa_scsi_update_entry(h, i, sd[entry]);
edd16368
SC		 1713 }
1714 i++;
1715 }
1716
1717 /* Now, make sure every device listed in sd[] is also
1718 * listed in h->dev[], adding them if they aren't found
1719 */
1720
1721 for (i = 0; i < nsds; i++) {
1722 if (!sd[i]) /* if already added above. */
1723 continue;
9846590e
SC		 1724
1725 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1726 * as the SCSI mid-layer does not handle such devices well.
1727 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1728 * at 160Hz, and prevents the system from coming up.
1729 */
1730 if (sd[i]->volume_offline) {
1731 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1732 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1733 continue;
1734 }
1735
edd16368
SC		 1736 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1737 h->ndevices, &entry);
1738 if (device_change == DEVICE_NOT_FOUND) {
1739 changes++;
8aa60681 1740 if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
edd16368
SC		 1741 break;
1742 sd[i] = NULL; /* prevent from being freed later. */
1743 } else if (device_change == DEVICE_CHANGED) {
1744 /* should never happen... */
1745 changes++;
1746 dev_warn(&h->pdev->dev,
1747 "device unexpectedly changed.\n");
1748 /* but if it does happen, we just ignore that device */
1749 }
1750 }
41ce4c35
SC		 1751 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1752
1753 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1754 * any logical drives that need it enabled.
1755 */
1d33d85d
DB		 1756 for (i = 0; i < h->ndevices; i++) {
1757 if (h->dev[i] == NULL)
1758 continue;
41ce4c35 1759 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1d33d85d 1760 }
41ce4c35 1761
edd16368
SC		 1762 spin_unlock_irqrestore(&h->devlock, flags);
1763
9846590e
SC		 1764 /* Monitor devices which are in one of several NOT READY states to be
1765 * brought online later. This must be done without holding h->devlock,
1766 * so don't touch h->dev[]
1767 */
1768 for (i = 0; i < nsds; i++) {
1769 if (!sd[i]) /* if already added above. */
1770 continue;
1771 if (sd[i]->volume_offline)
1772 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1773 }
1774
edd16368
SC		 1775 /* Don't notify scsi mid layer of any changes the first time through
1776 * (or if there are no changes) scsi_scan_host will do it later the
1777 * first time through.
1778 */
8aa60681 1779 if (!changes)
edd16368
SC		 1780 goto free_and_out;
1781
1782 sh = h->scsi_host;
da03ded0
DB		 1783 if (sh == NULL) {
1784 dev_warn(&h->pdev->dev, "%s: scsi_host is null\n", __func__);
1785 goto free_and_out;
1786 }
edd16368
SC		 1787 /* Notify scsi mid layer of any removed devices */
1788 for (i = 0; i < nremoved; i++) {
1d33d85d
DB		 1789 if (removed[i] == NULL)
1790 continue;
41ce4c35
SC		 1791 if (removed[i]->expose_state & HPSA_SCSI_ADD) {
1792 struct scsi_device *sdev =
1793 scsi_device_lookup(sh, removed[i]->bus,
1794 removed[i]->target, removed[i]->lun);
1795 if (sdev != NULL) {
1796 scsi_remove_device(sdev);
1797 scsi_device_put(sdev);
1798 } else {
1799 /*
1800 * We don't expect to get here.
1801 * future cmds to this device will get selection
1802 * timeout as if the device was gone.
1803 */
0d96ef5f
WS		 1804 hpsa_show_dev_msg(KERN_WARNING, h, removed[i],
1805 "didn't find device for removal.");
41ce4c35 1806 }
edd16368
SC		 1807 }
1808 kfree(removed[i]);
1809 removed[i] = NULL;
1810 }
1811
1812 /* Notify scsi mid layer of any added devices */
1813 for (i = 0; i < nadded; i++) {
1d33d85d
DB		 1814 if (added[i] == NULL)
1815 continue;
41ce4c35
SC		 1816 if (!(added[i]->expose_state & HPSA_SCSI_ADD))
1817 continue;
edd16368
SC		 1818 if (scsi_add_device(sh, added[i]->bus,
1819 added[i]->target, added[i]->lun) == 0)
1820 continue;
1d33d85d 1821 dev_warn(&h->pdev->dev, "addition failed, device not added.");
edd16368
SC		 1822 /* now we have to remove it from h->dev,
1823 * since it didn't get added to scsi mid layer
1824 */
1825 fixup_botched_add(h, added[i]);
853633e8 1826 h->drv_req_rescan = 1;
edd16368
SC		 1827 }
1828
1829free_and_out:
1830 kfree(added);
1831 kfree(removed);
edd16368
SC		 1832}
1833
1834/*
9e03aa2f 1835 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1836 * Assume's h->devlock is held.
1837 */
1838static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1839 int bus, int target, int lun)
1840{
1841 int i;
1842 struct hpsa_scsi_dev_t *sd;
1843
1844 for (i = 0; i < h->ndevices; i++) {
1845 sd = h->dev[i];
1846 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1847 return sd;
1848 }
1849 return NULL;
1850}
1851
edd16368
SC		 1852static int hpsa_slave_alloc(struct scsi_device *sdev)
1853{
1854 struct hpsa_scsi_dev_t *sd;
1855 unsigned long flags;
1856 struct ctlr_info *h;
1857
1858 h = sdev_to_hba(sdev);
1859 spin_lock_irqsave(&h->devlock, flags);
1860 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1861 sdev_id(sdev), sdev->lun);
41ce4c35 1862 if (likely(sd)) {
03383736 1863 atomic_set(&sd->ioaccel_cmds_out, 0);
41ce4c35
SC		 1864 sdev->hostdata = (sd->expose_state & HPSA_SCSI_ADD) ? sd : NULL;
1865 } else
1866 sdev->hostdata = NULL;
edd16368
SC		 1867 spin_unlock_irqrestore(&h->devlock, flags);
1868 return 0;
1869}
1870
41ce4c35
SC		 1871/* configure scsi device based on internal per-device structure */
1872static int hpsa_slave_configure(struct scsi_device *sdev)
1873{
1874 struct hpsa_scsi_dev_t *sd;
1875 int queue_depth;
1876
1877 sd = sdev->hostdata;
1878 sdev->no_uld_attach = !sd || !(sd->expose_state & HPSA_ULD_ATTACH);
1879
1880 if (sd)
1881 queue_depth = sd->queue_depth != 0 ?
1882 sd->queue_depth : sdev->host->can_queue;
1883 else
1884 queue_depth = sdev->host->can_queue;
1885
1886 scsi_change_queue_depth(sdev, queue_depth);
1887
1888 return 0;
1889}
1890
edd16368
SC		 1891static void hpsa_slave_destroy(struct scsi_device *sdev)
1892{
bcc44255 1893 /* nothing to do. */
edd16368
SC		 1894}
1895
d9a729f3
WS		 1896static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1897{
1898 int i;
1899
1900 if (!h->ioaccel2_cmd_sg_list)
1901 return;
1902 for (i = 0; i < h->nr_cmds; i++) {
1903 kfree(h->ioaccel2_cmd_sg_list[i]);
1904 h->ioaccel2_cmd_sg_list[i] = NULL;
1905 }
1906 kfree(h->ioaccel2_cmd_sg_list);
1907 h->ioaccel2_cmd_sg_list = NULL;
1908}
1909
1910static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1911{
1912 int i;
1913
1914 if (h->chainsize <= 0)
1915 return 0;
1916
1917 h->ioaccel2_cmd_sg_list =
1918 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
1919 GFP_KERNEL);
1920 if (!h->ioaccel2_cmd_sg_list)
1921 return -ENOMEM;
1922 for (i = 0; i < h->nr_cmds; i++) {
1923 h->ioaccel2_cmd_sg_list[i] =
1924 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
1925 h->maxsgentries, GFP_KERNEL);
1926 if (!h->ioaccel2_cmd_sg_list[i])
1927 goto clean;
1928 }
1929 return 0;
1930
1931clean:
1932 hpsa_free_ioaccel2_sg_chain_blocks(h);
1933 return -ENOMEM;
1934}
1935
33a2ffce
SC		 1936static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1937{
1938 int i;
1939
1940 if (!h->cmd_sg_list)
1941 return;
1942 for (i = 0; i < h->nr_cmds; i++) {
1943 kfree(h->cmd_sg_list[i]);
1944 h->cmd_sg_list[i] = NULL;
1945 }
1946 kfree(h->cmd_sg_list);
1947 h->cmd_sg_list = NULL;
1948}
1949
105a3dbc 1950static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
33a2ffce
SC		 1951{
1952 int i;
1953
1954 if (h->chainsize <= 0)
1955 return 0;
1956
1957 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1958 GFP_KERNEL);
3d4e6af8
RE		 1959 if (!h->cmd_sg_list) {
1960 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1961 return -ENOMEM;
3d4e6af8 1962 }
33a2ffce
SC		 1963 for (i = 0; i < h->nr_cmds; i++) {
1964 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1965 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1966 if (!h->cmd_sg_list[i]) {
1967 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1968 goto clean;
3d4e6af8 1969 }
33a2ffce
SC		 1970 }
1971 return 0;
1972
1973clean:
1974 hpsa_free_sg_chain_blocks(h);
1975 return -ENOMEM;
1976}
1977
d9a729f3
WS		 1978static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
1979 struct io_accel2_cmd *cp, struct CommandList *c)
1980{
1981 struct ioaccel2_sg_element *chain_block;
1982 u64 temp64;
1983 u32 chain_size;
1984
1985 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
1986 chain_size = le32_to_cpu(cp->data_len);
1987 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
1988 PCI_DMA_TODEVICE);
1989 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1990 /* prevent subsequent unmapping */
1991 cp->sg->address = 0;
1992 return -1;
1993 }
1994 cp->sg->address = cpu_to_le64(temp64);
1995 return 0;
1996}
1997
1998static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
1999 struct io_accel2_cmd *cp)
2000{
2001 struct ioaccel2_sg_element *chain_sg;
2002 u64 temp64;
2003 u32 chain_size;
2004
2005 chain_sg = cp->sg;
2006 temp64 = le64_to_cpu(chain_sg->address);
2007 chain_size = le32_to_cpu(cp->data_len);
2008 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
2009}
2010
e2bea6df 2011static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 2012 struct CommandList *c)
2013{
2014 struct SGDescriptor *chain_sg, *chain_block;
2015 u64 temp64;
50a0decf 2016 u32 chain_len;
33a2ffce
SC		 2017
2018 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
2019 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 2020 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
2021 chain_len = sizeof(*chain_sg) *
2b08b3e9 2022 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 2023 chain_sg->Len = cpu_to_le32(chain_len);
2024 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 2025 PCI_DMA_TODEVICE);
e2bea6df
SC		 2026 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2027 /* prevent subsequent unmapping */
50a0decf 2028 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 2029 return -1;
2030 }
50a0decf 2031 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 2032 return 0;
33a2ffce
SC		 2033}
2034
2035static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
2036 struct CommandList *c)
2037{
2038 struct SGDescriptor *chain_sg;
33a2ffce 2039
50a0decf 2040 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 2041 return;
2042
2043 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 2044 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
2045 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 2046}
2047
a09c1441
ST		 2048
2049/* Decode the various types of errors on ioaccel2 path.
2050 * Return 1 for any error that should generate a RAID path retry.
2051 * Return 0 for errors that don't require a RAID path retry.
2052 */
2053static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 2054 struct CommandList *c,
2055 struct scsi_cmnd *cmd,
2056 struct io_accel2_cmd *c2)
2057{
2058 int data_len;
a09c1441 2059 int retry = 0;
c40820d5 2060 u32 ioaccel2_resid = 0;
c349775e
ST		 2061
2062 switch (c2->error_data.serv_response) {
2063 case IOACCEL2_SERV_RESPONSE_COMPLETE:
2064 switch (c2->error_data.status) {
2065 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
2066 break;
2067 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
ee6b1889 2068 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 2069 if (c2->error_data.data_present !=
ee6b1889
SC		 2070 IOACCEL2_SENSE_DATA_PRESENT) {
2071 memset(cmd->sense_buffer, 0,
2072 SCSI_SENSE_BUFFERSIZE);
c349775e 2073 break;
ee6b1889 2074 }
c349775e
ST		 2075 /* copy the sense data */
2076 data_len = c2->error_data.sense_data_len;
2077 if (data_len > SCSI_SENSE_BUFFERSIZE)
2078 data_len = SCSI_SENSE_BUFFERSIZE;
2079 if (data_len > sizeof(c2->error_data.sense_data_buff))
2080 data_len =
2081 sizeof(c2->error_data.sense_data_buff);
2082 memcpy(cmd->sense_buffer,
2083 c2->error_data.sense_data_buff, data_len);
a09c1441 2084 retry = 1;
c349775e
ST		 2085 break;
2086 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
a09c1441 2087 retry = 1;
c349775e
ST		 2088 break;
2089 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
a09c1441 2090 retry = 1;
c349775e
ST		 2091 break;
2092 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 2093 retry = 1;
c349775e
ST		 2094 break;
2095 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
a09c1441 2096 retry = 1;
c349775e
ST		 2097 break;
2098 default:
a09c1441 2099 retry = 1;
c349775e
ST		 2100 break;
2101 }
2102 break;
2103 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 2104 switch (c2->error_data.status) {
2105 case IOACCEL2_STATUS_SR_IO_ERROR:
2106 case IOACCEL2_STATUS_SR_IO_ABORTED:
2107 case IOACCEL2_STATUS_SR_OVERRUN:
2108 retry = 1;
2109 break;
2110 case IOACCEL2_STATUS_SR_UNDERRUN:
2111 cmd->result = (DID_OK << 16); /* host byte */
2112 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2113 ioaccel2_resid = get_unaligned_le32(
2114 &c2->error_data.resid_cnt[0]);
2115 scsi_set_resid(cmd, ioaccel2_resid);
2116 break;
2117 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
2118 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
2119 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
2120 /* We will get an event from ctlr to trigger rescan */
2121 retry = 1;
2122 break;
2123 default:
2124 retry = 1;
c40820d5 2125 }
c349775e
ST		 2126 break;
2127 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
2128 break;
2129 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
2130 break;
2131 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
a09c1441 2132 retry = 1;
c349775e
ST		 2133 break;
2134 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
c349775e
ST		 2135 break;
2136 default:
a09c1441 2137 retry = 1;
c349775e
ST		 2138 break;
2139 }
a09c1441
ST		 2140
2141 return retry; /* retry on raid path? */
c349775e
ST		 2142}
2143
a58e7e53
WS		 2144static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2145 struct CommandList *c)
2146{
d604f533
WS		 2147 bool do_wake = false;
2148
a58e7e53
WS		 2149 /*
2150 * Prevent the following race in the abort handler:
2151 *
2152 * 1. LLD is requested to abort a SCSI command
2153 * 2. The SCSI command completes
2154 * 3. The struct CommandList associated with step 2 is made available
2155 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2156 * 5. Abort handler follows scsi_cmnd->host_scribble and
2157 * finds struct CommandList and tries to aborts it
2158 * Now we have aborted the wrong command.
2159 *
d604f533
WS		 2160 * Reset c->scsi_cmd here so that the abort or reset handler will know
2161 * this command has completed. Then, check to see if the handler is
a58e7e53
WS		 2162 * waiting for this command, and, if so, wake it.
2163 */
2164 c->scsi_cmd = SCSI_CMD_IDLE;
d604f533 2165 mb(); /* Declare command idle before checking for pending events. */
a58e7e53 2166 if (c->abort_pending) {
d604f533 2167 do_wake = true;
a58e7e53 2168 c->abort_pending = false;
a58e7e53 2169 }
d604f533
WS		 2170 if (c->reset_pending) {
2171 unsigned long flags;
2172 struct hpsa_scsi_dev_t *dev;
2173
2174 /*
2175 * There appears to be a reset pending; lock the lock and
2176 * reconfirm. If so, then decrement the count of outstanding
2177 * commands and wake the reset command if this is the last one.
2178 */
2179 spin_lock_irqsave(&h->lock, flags);
2180 dev = c->reset_pending; /* Re-fetch under the lock. */
2181 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2182 do_wake = true;
2183 c->reset_pending = NULL;
2184 spin_unlock_irqrestore(&h->lock, flags);
2185 }
2186
2187 if (do_wake)
2188 wake_up_all(&h->event_sync_wait_queue);
a58e7e53
WS		 2189}
2190
73153fe5
WS		 2191static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2192 struct CommandList *c)
2193{
2194 hpsa_cmd_resolve_events(h, c);
2195 cmd_tagged_free(h, c);
2196}
2197
8a0ff92c
WS		 2198static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2199 struct CommandList *c, struct scsi_cmnd *cmd)
2200{
73153fe5 2201 hpsa_cmd_resolve_and_free(h, c);
8a0ff92c
WS		 2202 cmd->scsi_done(cmd);
2203}
2204
2205static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2206{
2207 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2208 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2209}
2210
a58e7e53
WS		 2211static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2212{
2213 cmd->result = DID_ABORT << 16;
2214}
2215
2216static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2217 struct scsi_cmnd *cmd)
2218{
2219 hpsa_set_scsi_cmd_aborted(cmd);
2220 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2221 c->Request.CDB, c->err_info->ScsiStatus);
73153fe5 2222 hpsa_cmd_resolve_and_free(h, c);
a58e7e53
WS		 2223}
2224
c349775e
ST		 2225static void process_ioaccel2_completion(struct ctlr_info *h,
2226 struct CommandList *c, struct scsi_cmnd *cmd,
2227 struct hpsa_scsi_dev_t *dev)
2228{
2229 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2230
2231 /* check for good status */
2232 if (likely(c2->error_data.serv_response == 0 &&
8a0ff92c
WS		 2233 c2->error_data.status == 0))
2234 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e 2235
8a0ff92c
WS		 2236 /*
2237 * Any RAID offload error results in retry which will use
c349775e
ST		 2238 * the normal I/O path so the controller can handle whatever's
2239 * wrong.
2240 */
2241 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
2242 c2->error_data.serv_response ==
2243 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 2244 if (c2->error_data.status ==
2245 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
2246 dev->offload_enabled = 0;
8a0ff92c
WS		 2247
2248 return hpsa_retry_cmd(h, c);
a09c1441 2249 }
080ef1cc
DB		 2250
2251 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
8a0ff92c 2252 return hpsa_retry_cmd(h, c);
080ef1cc 2253
8a0ff92c 2254 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e
ST		 2255}
2256
9437ac43
SC		 2257/* Returns 0 on success, < 0 otherwise. */
2258static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2259 struct CommandList *cp)
2260{
2261 u8 tmf_status = cp->err_info->ScsiStatus;
2262
2263 switch (tmf_status) {
2264 case CISS_TMF_COMPLETE:
2265 /*
2266 * CISS_TMF_COMPLETE never happens, instead,
2267 * ei->CommandStatus == 0 for this case.
2268 */
2269 case CISS_TMF_SUCCESS:
2270 return 0;
2271 case CISS_TMF_INVALID_FRAME:
2272 case CISS_TMF_NOT_SUPPORTED:
2273 case CISS_TMF_FAILED:
2274 case CISS_TMF_WRONG_LUN:
2275 case CISS_TMF_OVERLAPPED_TAG:
2276 break;
2277 default:
2278 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2279 tmf_status);
2280 break;
2281 }
2282 return -tmf_status;
2283}
2284
1fb011fb 2285static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2286{
2287 struct scsi_cmnd *cmd;
2288 struct ctlr_info *h;
2289 struct ErrorInfo *ei;
283b4a9b 2290 struct hpsa_scsi_dev_t *dev;
d9a729f3 2291 struct io_accel2_cmd *c2;
edd16368 2292
9437ac43
SC		 2293 u8 sense_key;
2294 u8 asc; /* additional sense code */
2295 u8 ascq; /* additional sense code qualifier */
db111e18 2296 unsigned long sense_data_size;
edd16368
SC		 2297
2298 ei = cp->err_info;
7fa3030c 2299 cmd = cp->scsi_cmd;
edd16368 2300 h = cp->h;
283b4a9b 2301 dev = cmd->device->hostdata;
d9a729f3 2302 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2303
2304 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2305 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2306 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2307 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2308
d9a729f3
WS		 2309 if ((cp->cmd_type == CMD_IOACCEL2) &&
2310 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2311 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2312
edd16368
SC		 2313 cmd->result = (DID_OK << 16); /* host byte */
2314 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2315
03383736
DB		 2316 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2317 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2318
25163bd5
WS		 2319 /*
2320 * We check for lockup status here as it may be set for
2321 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2322 * fail_all_oustanding_cmds()
2323 */
2324 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2325 /* DID_NO_CONNECT will prevent a retry */
2326 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 2327 return hpsa_cmd_free_and_done(h, cp, cmd);
25163bd5
WS		 2328 }
2329
d604f533
WS		 2330 if ((unlikely(hpsa_is_pending_event(cp)))) {
2331 if (cp->reset_pending)
2332 return hpsa_cmd_resolve_and_free(h, cp);
2333 if (cp->abort_pending)
2334 return hpsa_cmd_abort_and_free(h, cp, cmd);
2335 }
2336
c349775e
ST		 2337 if (cp->cmd_type == CMD_IOACCEL2)
2338 return process_ioaccel2_completion(h, cp, cmd, dev);
2339
6aa4c361 2340 scsi_set_resid(cmd, ei->ResidualCnt);
8a0ff92c
WS		 2341 if (ei->CommandStatus == 0)
2342 return hpsa_cmd_free_and_done(h, cp, cmd);
6aa4c361 2343
e1f7de0c
MG		 2344 /* For I/O accelerator commands, copy over some fields to the normal
2345 * CISS header used below for error handling.
2346 */
2347 if (cp->cmd_type == CMD_IOACCEL1) {
2348 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2349 cp->Header.SGList = scsi_sg_count(cmd);
2350 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2351 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2352 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2353 cp->Header.tag = c->tag;
e1f7de0c
MG		 2354 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2355 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2356
2357 /* Any RAID offload error results in retry which will use
2358 * the normal I/O path so the controller can handle whatever's
2359 * wrong.
2360 */
2361 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
2362 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2363 dev->offload_enabled = 0;
d604f533 2364 return hpsa_retry_cmd(h, cp);
283b4a9b 2365 }
e1f7de0c
MG		 2366 }
2367
edd16368
SC		 2368 /* an error has occurred */
2369 switch (ei->CommandStatus) {
2370
2371 case CMD_TARGET_STATUS:
9437ac43
SC		 2372 cmd->result |= ei->ScsiStatus;
2373 /* copy the sense data */
2374 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2375 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2376 else
2377 sense_data_size = sizeof(ei->SenseInfo);
2378 if (ei->SenseLen < sense_data_size)
2379 sense_data_size = ei->SenseLen;
2380 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2381 if (ei->ScsiStatus)
2382 decode_sense_data(ei->SenseInfo, sense_data_size,
2383 &sense_key, &asc, &ascq);
edd16368 2384 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2385 if (sense_key == ABORTED_COMMAND) {
2e311fba 2386 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2387 break;
2388 }
edd16368
SC		 2389 break;
2390 }
edd16368
SC		 2391 /* Problem was not a check condition
2392 * Pass it up to the upper layers...
2393 */
2394 if (ei->ScsiStatus) {
2395 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2396 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2397 "Returning result: 0x%x\n",
2398 cp, ei->ScsiStatus,
2399 sense_key, asc, ascq,
2400 cmd->result);
2401 } else { /* scsi status is zero??? How??? */
2402 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2403 "Returning no connection.\n", cp),
2404
2405 /* Ordinarily, this case should never happen,
2406 * but there is a bug in some released firmware
2407 * revisions that allows it to happen if, for
2408 * example, a 4100 backplane loses power and
2409 * the tape drive is in it. We assume that
2410 * it's a fatal error of some kind because we
2411 * can't show that it wasn't. We will make it
2412 * look like selection timeout since that is
2413 * the most common reason for this to occur,
2414 * and it's severe enough.
2415 */
2416
2417 cmd->result = DID_NO_CONNECT << 16;
2418 }
2419 break;
2420
2421 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2422 break;
2423 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2424 dev_warn(&h->pdev->dev,
2425 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2426 break;
2427 case CMD_INVALID: {
2428 /* print_bytes(cp, sizeof(*cp), 1, 0);
2429 print_cmd(cp); */
2430 /* We get CMD_INVALID if you address a non-existent device
2431 * instead of a selection timeout (no response). You will
2432 * see this if you yank out a drive, then try to access it.
2433 * This is kind of a shame because it means that any other
2434 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2435 * missing target. */
2436 cmd->result = DID_NO_CONNECT << 16;
2437 }
2438 break;
2439 case CMD_PROTOCOL_ERR:
256d0eaa 2440 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2441 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2442 cp->Request.CDB);
edd16368
SC		 2443 break;
2444 case CMD_HARDWARE_ERR:
2445 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2446 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2447 cp->Request.CDB);
edd16368
SC		 2448 break;
2449 case CMD_CONNECTION_LOST:
2450 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2451 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2452 cp->Request.CDB);
edd16368
SC		 2453 break;
2454 case CMD_ABORTED:
a58e7e53
WS		 2455 /* Return now to avoid calling scsi_done(). */
2456 return hpsa_cmd_abort_and_free(h, cp, cmd);
edd16368
SC		 2457 case CMD_ABORT_FAILED:
2458 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2459 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2460 cp->Request.CDB);
edd16368
SC		 2461 break;
2462 case CMD_UNSOLICITED_ABORT:
f6e76055 2463 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2464 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2465 cp->Request.CDB);
edd16368
SC		 2466 break;
2467 case CMD_TIMEOUT:
2468 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2469 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2470 cp->Request.CDB);
edd16368 2471 break;
1d5e2ed0
SC		 2472 case CMD_UNABORTABLE:
2473 cmd->result = DID_ERROR << 16;
2474 dev_warn(&h->pdev->dev, "Command unabortable\n");
2475 break;
9437ac43
SC		 2476 case CMD_TMF_STATUS:
2477 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2478 cmd->result = DID_ERROR << 16;
2479 break;
283b4a9b
SC		 2480 case CMD_IOACCEL_DISABLED:
2481 /* This only handles the direct pass-through case since RAID
2482 * offload is handled above. Just attempt a retry.
2483 */
2484 cmd->result = DID_SOFT_ERROR << 16;
2485 dev_warn(&h->pdev->dev,
2486 "cp %p had HP SSD Smart Path error\n", cp);
2487 break;
edd16368
SC		 2488 default:
2489 cmd->result = DID_ERROR << 16;
2490 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2491 cp, ei->CommandStatus);
2492 }
8a0ff92c
WS		 2493
2494 return hpsa_cmd_free_and_done(h, cp, cmd);
edd16368
SC		 2495}
2496
edd16368
SC		 2497static void hpsa_pci_unmap(struct pci_dev *pdev,
2498 struct CommandList *c, int sg_used, int data_direction)
2499{
2500 int i;
edd16368 2501
50a0decf
SC		 2502 for (i = 0; i < sg_used; i++)
2503 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2504 le32_to_cpu(c->SG[i].Len),
2505 data_direction);
edd16368
SC		 2506}
2507
a2dac136 2508static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2509 struct CommandList *cp,
2510 unsigned char *buf,
2511 size_t buflen,
2512 int data_direction)
2513{
01a02ffc 2514 u64 addr64;
edd16368
SC		 2515
2516 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2517 cp->Header.SGList = 0;
50a0decf 2518 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2519 return 0;
edd16368
SC		 2520 }
2521
50a0decf 2522 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2523 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2524 /* Prevent subsequent unmap of something never mapped */
eceaae18 2525 cp->Header.SGList = 0;
50a0decf 2526 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2527 return -1;
eceaae18 2528 }
50a0decf
SC		 2529 cp->SG[0].Addr = cpu_to_le64(addr64);
2530 cp->SG[0].Len = cpu_to_le32(buflen);
2531 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2532 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2533 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2534 return 0;
edd16368
SC		 2535}
2536
25163bd5
WS		 2537#define NO_TIMEOUT ((unsigned long) -1)
2538#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2539static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2540 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2541{
2542 DECLARE_COMPLETION_ONSTACK(wait);
2543
2544 c->waiting = &wait;
25163bd5
WS		 2545 __enqueue_cmd_and_start_io(h, c, reply_queue);
2546 if (timeout_msecs == NO_TIMEOUT) {
2547 /* TODO: get rid of this no-timeout thing */
2548 wait_for_completion_io(&wait);
2549 return IO_OK;
2550 }
2551 if (!wait_for_completion_io_timeout(&wait,
2552 msecs_to_jiffies(timeout_msecs))) {
2553 dev_warn(&h->pdev->dev, "Command timed out.\n");
2554 return -ETIMEDOUT;
2555 }
2556 return IO_OK;
2557}
2558
2559static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2560 int reply_queue, unsigned long timeout_msecs)
2561{
2562 if (unlikely(lockup_detected(h))) {
2563 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2564 return IO_OK;
2565 }
2566 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2567}
2568
094963da
SC		 2569static u32 lockup_detected(struct ctlr_info *h)
2570{
2571 int cpu;
2572 u32 rc, *lockup_detected;
2573
2574 cpu = get_cpu();
2575 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2576 rc = *lockup_detected;
2577 put_cpu();
2578 return rc;
2579}
2580
9c2fc160 2581#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2582static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2583 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2584{
9c2fc160 2585 int backoff_time = 10, retry_count = 0;
25163bd5 2586 int rc;
edd16368
SC		 2587
2588 do {
7630abd0 2589 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2590 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2591 timeout_msecs);
2592 if (rc)
2593 break;
edd16368 2594 retry_count++;
9c2fc160
SC		 2595 if (retry_count > 3) {
2596 msleep(backoff_time);
2597 if (backoff_time < 1000)
2598 backoff_time *= 2;
2599 }
852af20a 2600 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2601 check_for_busy(h, c)) &&
2602 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2603 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2604 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2605 rc = -EIO;
2606 return rc;
edd16368
SC		 2607}
2608
d1e8beac
SC		 2609static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2610 struct CommandList *c)
edd16368 2611{
d1e8beac
SC		 2612 const u8 *cdb = c->Request.CDB;
2613 const u8 *lun = c->Header.LUN.LunAddrBytes;
2614
2615 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2616 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2617 txt, lun[0], lun[1], lun[2], lun[3],
2618 lun[4], lun[5], lun[6], lun[7],
2619 cdb[0], cdb[1], cdb[2], cdb[3],
2620 cdb[4], cdb[5], cdb[6], cdb[7],
2621 cdb[8], cdb[9], cdb[10], cdb[11],
2622 cdb[12], cdb[13], cdb[14], cdb[15]);
2623}
2624
2625static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2626 struct CommandList *cp)
2627{
2628 const struct ErrorInfo *ei = cp->err_info;
edd16368 2629 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2630 u8 sense_key, asc, ascq;
2631 int sense_len;
edd16368 2632
edd16368
SC		 2633 switch (ei->CommandStatus) {
2634 case CMD_TARGET_STATUS:
9437ac43
SC		 2635 if (ei->SenseLen > sizeof(ei->SenseInfo))
2636 sense_len = sizeof(ei->SenseInfo);
2637 else
2638 sense_len = ei->SenseLen;
2639 decode_sense_data(ei->SenseInfo, sense_len,
2640 &sense_key, &asc, &ascq);
d1e8beac
SC		 2641 hpsa_print_cmd(h, "SCSI status", cp);
2642 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2643 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2644 sense_key, asc, ascq);
d1e8beac 2645 else
9437ac43 2646 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2647 if (ei->ScsiStatus == 0)
2648 dev_warn(d, "SCSI status is abnormally zero. "
2649 "(probably indicates selection timeout "
2650 "reported incorrectly due to a known "
2651 "firmware bug, circa July, 2001.)\n");
2652 break;
2653 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2654 break;
2655 case CMD_DATA_OVERRUN:
d1e8beac 2656 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2657 break;
2658 case CMD_INVALID: {
2659 /* controller unfortunately reports SCSI passthru's
2660 * to non-existent targets as invalid commands.
2661 */
d1e8beac
SC		 2662 hpsa_print_cmd(h, "invalid command", cp);
2663 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2664 }
2665 break;
2666 case CMD_PROTOCOL_ERR:
d1e8beac 2667 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2668 break;
2669 case CMD_HARDWARE_ERR:
d1e8beac 2670 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2671 break;
2672 case CMD_CONNECTION_LOST:
d1e8beac 2673 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2674 break;
2675 case CMD_ABORTED:
d1e8beac 2676 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2677 break;
2678 case CMD_ABORT_FAILED:
d1e8beac 2679 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2680 break;
2681 case CMD_UNSOLICITED_ABORT:
d1e8beac 2682 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2683 break;
2684 case CMD_TIMEOUT:
d1e8beac 2685 hpsa_print_cmd(h, "timed out", cp);
edd16368 2686 break;
1d5e2ed0 2687 case CMD_UNABORTABLE:
d1e8beac 2688 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2689 break;
25163bd5
WS		 2690 case CMD_CTLR_LOCKUP:
2691 hpsa_print_cmd(h, "controller lockup detected", cp);
2692 break;
edd16368 2693 default:
d1e8beac
SC		 2694 hpsa_print_cmd(h, "unknown status", cp);
2695 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2696 ei->CommandStatus);
2697 }
2698}
2699
2700static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2701 u16 page, unsigned char *buf,
edd16368
SC		 2702 unsigned char bufsize)
2703{
2704 int rc = IO_OK;
2705 struct CommandList *c;
2706 struct ErrorInfo *ei;
2707
45fcb86e 2708 c = cmd_alloc(h);
edd16368 2709
a2dac136
SC		 2710 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2711 page, scsi3addr, TYPE_CMD)) {
2712 rc = -1;
2713 goto out;
2714 }
25163bd5
WS		 2715 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2716 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2717 if (rc)
2718 goto out;
edd16368
SC		 2719 ei = c->err_info;
2720 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2721 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2722 rc = -1;
2723 }
a2dac136 2724out:
45fcb86e 2725 cmd_free(h, c);
edd16368
SC		 2726 return rc;
2727}
2728
bf711ac6 2729static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2730 u8 reset_type, int reply_queue)
edd16368
SC		 2731{
2732 int rc = IO_OK;
2733 struct CommandList *c;
2734 struct ErrorInfo *ei;
2735
45fcb86e 2736 c = cmd_alloc(h);
edd16368 2737
edd16368 2738
a2dac136 2739 /* fill_cmd can't fail here, no data buffer to map. */
0b9b7b6e 2740 (void) fill_cmd(c, reset_type, h, NULL, 0, 0,
bf711ac6 2741 scsi3addr, TYPE_MSG);
25163bd5
WS		 2742 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2743 if (rc) {
2744 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2745 goto out;
2746 }
edd16368
SC		 2747 /* no unmap needed here because no data xfer. */
2748
2749 ei = c->err_info;
2750 if (ei->CommandStatus != 0) {
d1e8beac 2751 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2752 rc = -1;
2753 }
25163bd5 2754out:
45fcb86e 2755 cmd_free(h, c);
edd16368
SC		 2756 return rc;
2757}
2758
d604f533
WS		 2759static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2760 struct hpsa_scsi_dev_t *dev,
2761 unsigned char *scsi3addr)
2762{
2763 int i;
2764 bool match = false;
2765 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2766 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2767
2768 if (hpsa_is_cmd_idle(c))
2769 return false;
2770
2771 switch (c->cmd_type) {
2772 case CMD_SCSI:
2773 case CMD_IOCTL_PEND:
2774 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2775 sizeof(c->Header.LUN.LunAddrBytes));
2776 break;
2777
2778 case CMD_IOACCEL1:
2779 case CMD_IOACCEL2:
2780 if (c->phys_disk == dev) {
2781 /* HBA mode match */
2782 match = true;
2783 } else {
2784 /* Possible RAID mode -- check each phys dev. */
2785 /* FIXME: Do we need to take out a lock here? If
2786 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2787 * instead. */
2788 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2789 /* FIXME: an alternate test might be
2790 *
2791 * match = dev->phys_disk[i]->ioaccel_handle
2792 * == c2->scsi_nexus; */
2793 match = dev->phys_disk[i] == c->phys_disk;
2794 }
2795 }
2796 break;
2797
2798 case IOACCEL2_TMF:
2799 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2800 match = dev->phys_disk[i]->ioaccel_handle ==
2801 le32_to_cpu(ac->it_nexus);
2802 }
2803 break;
2804
2805 case 0: /* The command is in the middle of being initialized. */
2806 match = false;
2807 break;
2808
2809 default:
2810 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
2811 c->cmd_type);
2812 BUG();
2813 }
2814
2815 return match;
2816}
2817
2818static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
2819 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
2820{
2821 int i;
2822 int rc = 0;
2823
2824 /* We can really only handle one reset at a time */
2825 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
2826 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
2827 return -EINTR;
2828 }
2829
2830 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
2831
2832 for (i = 0; i < h->nr_cmds; i++) {
2833 struct CommandList *c = h->cmd_pool + i;
2834 int refcount = atomic_inc_return(&c->refcount);
2835
2836 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
2837 unsigned long flags;
2838
2839 /*
2840 * Mark the target command as having a reset pending,
2841 * then lock a lock so that the command cannot complete
2842 * while we're considering it. If the command is not
2843 * idle then count it; otherwise revoke the event.
2844 */
2845 c->reset_pending = dev;
2846 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
2847 if (!hpsa_is_cmd_idle(c))
2848 atomic_inc(&dev->reset_cmds_out);
2849 else
2850 c->reset_pending = NULL;
2851 spin_unlock_irqrestore(&h->lock, flags);
2852 }
2853
2854 cmd_free(h, c);
2855 }
2856
2857 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
2858 if (!rc)
2859 wait_event(h->event_sync_wait_queue,
2860 atomic_read(&dev->reset_cmds_out) == 0 ||
2861 lockup_detected(h));
2862
2863 if (unlikely(lockup_detected(h))) {
77678d3a
DB		 2864 dev_warn(&h->pdev->dev,
2865 "Controller lockup detected during reset wait\n");
2866 rc = -ENODEV;
2867 }
d604f533
WS		 2868
2869 if (unlikely(rc))
2870 atomic_set(&dev->reset_cmds_out, 0);
2871
2872 mutex_unlock(&h->reset_mutex);
2873 return rc;
2874}
2875
edd16368
SC		 2876static void hpsa_get_raid_level(struct ctlr_info *h,
2877 unsigned char *scsi3addr, unsigned char *raid_level)
2878{
2879 int rc;
2880 unsigned char *buf;
2881
2882 *raid_level = RAID_UNKNOWN;
2883 buf = kzalloc(64, GFP_KERNEL);
2884 if (!buf)
2885 return;
b7bb24eb 2886 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2887 if (rc == 0)
2888 *raid_level = buf[8];
2889 if (*raid_level > RAID_UNKNOWN)
2890 *raid_level = RAID_UNKNOWN;
2891 kfree(buf);
2892 return;
2893}
2894
283b4a9b
SC		 2895#define HPSA_MAP_DEBUG
2896#ifdef HPSA_MAP_DEBUG
2897static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2898 struct raid_map_data *map_buff)
2899{
2900 struct raid_map_disk_data *dd = &map_buff->data[0];
2901 int map, row, col;
2902 u16 map_cnt, row_cnt, disks_per_row;
2903
2904 if (rc != 0)
2905 return;
2906
2ba8bfc8
SC		 2907 /* Show details only if debugging has been activated. */
2908 if (h->raid_offload_debug < 2)
2909 return;
2910
283b4a9b
SC		 2911 dev_info(&h->pdev->dev, "structure_size = %u\n",
2912 le32_to_cpu(map_buff->structure_size));
2913 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2914 le32_to_cpu(map_buff->volume_blk_size));
2915 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2916 le64_to_cpu(map_buff->volume_blk_cnt));
2917 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2918 map_buff->phys_blk_shift);
2919 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2920 map_buff->parity_rotation_shift);
2921 dev_info(&h->pdev->dev, "strip_size = %u\n",
2922 le16_to_cpu(map_buff->strip_size));
2923 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2924 le64_to_cpu(map_buff->disk_starting_blk));
2925 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2926 le64_to_cpu(map_buff->disk_blk_cnt));
2927 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2928 le16_to_cpu(map_buff->data_disks_per_row));
2929 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2930 le16_to_cpu(map_buff->metadata_disks_per_row));
2931 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2932 le16_to_cpu(map_buff->row_cnt));
2933 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2934 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2935 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2936 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2937 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2938 le16_to_cpu(map_buff->flags) &
2939 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2940 dev_info(&h->pdev->dev, "dekindex = %u\n",
2941 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2942 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2943 for (map = 0; map < map_cnt; map++) {
2944 dev_info(&h->pdev->dev, "Map%u:\n", map);
2945 row_cnt = le16_to_cpu(map_buff->row_cnt);
2946 for (row = 0; row < row_cnt; row++) {
2947 dev_info(&h->pdev->dev, " Row%u:\n", row);
2948 disks_per_row =
2949 le16_to_cpu(map_buff->data_disks_per_row);
2950 for (col = 0; col < disks_per_row; col++, dd++)
2951 dev_info(&h->pdev->dev,
2952 " D%02u: h=0x%04x xor=%u,%u\n",
2953 col, dd->ioaccel_handle,
2954 dd->xor_mult[0], dd->xor_mult[1]);
2955 disks_per_row =
2956 le16_to_cpu(map_buff->metadata_disks_per_row);
2957 for (col = 0; col < disks_per_row; col++, dd++)
2958 dev_info(&h->pdev->dev,
2959 " M%02u: h=0x%04x xor=%u,%u\n",
2960 col, dd->ioaccel_handle,
2961 dd->xor_mult[0], dd->xor_mult[1]);
2962 }
2963 }
2964}
2965#else
2966static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2967 __attribute__((unused)) int rc,
2968 __attribute__((unused)) struct raid_map_data *map_buff)
2969{
2970}
2971#endif
2972
2973static int hpsa_get_raid_map(struct ctlr_info *h,
2974 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2975{
2976 int rc = 0;
2977 struct CommandList *c;
2978 struct ErrorInfo *ei;
2979
45fcb86e 2980 c = cmd_alloc(h);
bf43caf3 2981
283b4a9b
SC		 2982 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2983 sizeof(this_device->raid_map), 0,
2984 scsi3addr, TYPE_CMD)) {
2dd02d74
RE		 2985 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
2986 cmd_free(h, c);
2987 return -1;
283b4a9b 2988 }
25163bd5
WS		 2989 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2990 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2991 if (rc)
2992 goto out;
283b4a9b
SC		 2993 ei = c->err_info;
2994 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2995 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 2996 rc = -1;
2997 goto out;
283b4a9b 2998 }
45fcb86e 2999 cmd_free(h, c);
283b4a9b
SC		 3000
3001 /* @todo in the future, dynamically allocate RAID map memory */
3002 if (le32_to_cpu(this_device->raid_map.structure_size) >
3003 sizeof(this_device->raid_map)) {
3004 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
3005 rc = -1;
3006 }
3007 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
3008 return rc;
25163bd5
WS		 3009out:
3010 cmd_free(h, c);
3011 return rc;
283b4a9b
SC		 3012}
3013
03383736
DB		 3014static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
3015 unsigned char scsi3addr[], u16 bmic_device_index,
3016 struct bmic_identify_physical_device *buf, size_t bufsize)
3017{
3018 int rc = IO_OK;
3019 struct CommandList *c;
3020 struct ErrorInfo *ei;
3021
3022 c = cmd_alloc(h);
3023 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
3024 0, RAID_CTLR_LUNID, TYPE_CMD);
3025 if (rc)
3026 goto out;
3027
3028 c->Request.CDB[2] = bmic_device_index & 0xff;
3029 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3030
25163bd5
WS		 3031 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
3032 NO_TIMEOUT);
03383736
DB		 3033 ei = c->err_info;
3034 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3035 hpsa_scsi_interpret_error(h, c);
3036 rc = -1;
3037 }
3038out:
3039 cmd_free(h, c);
3040 return rc;
3041}
3042
1b70150a
SC		 3043static int hpsa_vpd_page_supported(struct ctlr_info *h,
3044 unsigned char scsi3addr[], u8 page)
3045{
3046 int rc;
3047 int i;
3048 int pages;
3049 unsigned char *buf, bufsize;
3050
3051 buf = kzalloc(256, GFP_KERNEL);
3052 if (!buf)
3053 return 0;
3054
3055 /* Get the size of the page list first */
3056 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3057 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3058 buf, HPSA_VPD_HEADER_SZ);
3059 if (rc != 0)
3060 goto exit_unsupported;
3061 pages = buf[3];
3062 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3063 bufsize = pages + HPSA_VPD_HEADER_SZ;
3064 else
3065 bufsize = 255;
3066
3067 /* Get the whole VPD page list */
3068 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3069 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3070 buf, bufsize);
3071 if (rc != 0)
3072 goto exit_unsupported;
3073
3074 pages = buf[3];
3075 for (i = 1; i <= pages; i++)
3076 if (buf[3 + i] == page)
3077 goto exit_supported;
3078exit_unsupported:
3079 kfree(buf);
3080 return 0;
3081exit_supported:
3082 kfree(buf);
3083 return 1;
3084}
3085
283b4a9b
SC		 3086static void hpsa_get_ioaccel_status(struct ctlr_info *h,
3087 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3088{
3089 int rc;
3090 unsigned char *buf;
3091 u8 ioaccel_status;
3092
3093 this_device->offload_config = 0;
3094 this_device->offload_enabled = 0;
41ce4c35 3095 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 3096
3097 buf = kzalloc(64, GFP_KERNEL);
3098 if (!buf)
3099 return;
1b70150a
SC		 3100 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
3101 goto out;
283b4a9b 3102 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 3103 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 3104 if (rc != 0)
3105 goto out;
3106
3107#define IOACCEL_STATUS_BYTE 4
3108#define OFFLOAD_CONFIGURED_BIT 0x01
3109#define OFFLOAD_ENABLED_BIT 0x02
3110 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
3111 this_device->offload_config =
3112 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3113 if (this_device->offload_config) {
3114 this_device->offload_enabled =
3115 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3116 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3117 this_device->offload_enabled = 0;
3118 }
41ce4c35 3119 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 3120out:
3121 kfree(buf);
3122 return;
3123}
3124
edd16368
SC		 3125/* Get the device id from inquiry page 0x83 */
3126static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
3127 unsigned char *device_id, int buflen)
3128{
3129 int rc;
3130 unsigned char *buf;
3131
3132 if (buflen > 16)
3133 buflen = 16;
3134 buf = kzalloc(64, GFP_KERNEL);
3135 if (!buf)
a84d794d 3136 return -ENOMEM;
b7bb24eb 3137 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 3138 if (rc == 0)
3139 memcpy(device_id, &buf[8], buflen);
3140 kfree(buf);
3141 return rc != 0;
3142}
3143
3144static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 3145 void *buf, int bufsize,
edd16368
SC		 3146 int extended_response)
3147{
3148 int rc = IO_OK;
3149 struct CommandList *c;
3150 unsigned char scsi3addr[8];
3151 struct ErrorInfo *ei;
3152
45fcb86e 3153 c = cmd_alloc(h);
bf43caf3 3154
e89c0ae7
SC		 3155 /* address the controller */
3156 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 3157 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3158 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3159 rc = -1;
3160 goto out;
3161 }
edd16368
SC		 3162 if (extended_response)
3163 c->Request.CDB[1] = extended_response;
25163bd5
WS		 3164 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3165 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3166 if (rc)
3167 goto out;
edd16368
SC		 3168 ei = c->err_info;
3169 if (ei->CommandStatus != 0 &&
3170 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3171 hpsa_scsi_interpret_error(h, c);
edd16368 3172 rc = -1;
283b4a9b 3173 } else {
03383736
DB		 3174 struct ReportLUNdata *rld = buf;
3175
3176 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 3177 dev_err(&h->pdev->dev,
3178 "report luns requested format %u, got %u\n",
3179 extended_response,
03383736 3180 rld->extended_response_flag);
283b4a9b
SC		 3181 rc = -1;
3182 }
edd16368 3183 }
a2dac136 3184out:
45fcb86e 3185 cmd_free(h, c);
edd16368
SC		 3186 return rc;
3187}
3188
3189static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 3190 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 3191{
03383736
DB		 3192 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3193 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 3194}
3195
3196static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3197 struct ReportLUNdata *buf, int bufsize)
3198{
3199 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3200}
3201
3202static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3203 int bus, int target, int lun)
3204{
3205 device->bus = bus;
3206 device->target = target;
3207 device->lun = lun;
3208}
3209
9846590e
SC		 3210/* Use VPD inquiry to get details of volume status */
3211static int hpsa_get_volume_status(struct ctlr_info *h,
3212 unsigned char scsi3addr[])
3213{
3214 int rc;
3215 int status;
3216 int size;
3217 unsigned char *buf;
3218
3219 buf = kzalloc(64, GFP_KERNEL);
3220 if (!buf)
3221 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3222
3223 /* Does controller have VPD for logical volume status? */
24a4b078 3224 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 3225 goto exit_failed;
9846590e
SC		 3226
3227 /* Get the size of the VPD return buffer */
3228 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3229 buf, HPSA_VPD_HEADER_SZ);
24a4b078 3230 if (rc != 0)
9846590e 3231 goto exit_failed;
9846590e
SC		 3232 size = buf[3];
3233
3234 /* Now get the whole VPD buffer */
3235 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3236 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 3237 if (rc != 0)
9846590e 3238 goto exit_failed;
9846590e
SC		 3239 status = buf[4]; /* status byte */
3240
3241 kfree(buf);
3242 return status;
3243exit_failed:
3244 kfree(buf);
3245 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3246}
3247
3248/* Determine offline status of a volume.
3249 * Return either:
3250 * 0 (not offline)
67955ba3 3251 * 0xff (offline for unknown reasons)
9846590e
SC		 3252 * # (integer code indicating one of several NOT READY states
3253 * describing why a volume is to be kept offline)
3254 */
67955ba3 3255static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 3256 unsigned char scsi3addr[])
3257{
3258 struct CommandList *c;
9437ac43
SC		 3259 unsigned char *sense;
3260 u8 sense_key, asc, ascq;
3261 int sense_len;
25163bd5 3262 int rc, ldstat = 0;
9846590e
SC		 3263 u16 cmd_status;
3264 u8 scsi_status;
3265#define ASC_LUN_NOT_READY 0x04
3266#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3267#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3268
3269 c = cmd_alloc(h);
bf43caf3 3270
9846590e 3271 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
25163bd5
WS		 3272 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3273 if (rc) {
3274 cmd_free(h, c);
3275 return 0;
3276 }
9846590e 3277 sense = c->err_info->SenseInfo;
9437ac43
SC		 3278 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3279 sense_len = sizeof(c->err_info->SenseInfo);
3280 else
3281 sense_len = c->err_info->SenseLen;
3282 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 3283 cmd_status = c->err_info->CommandStatus;
3284 scsi_status = c->err_info->ScsiStatus;
3285 cmd_free(h, c);
3286 /* Is the volume 'not ready'? */
3287 if (cmd_status != CMD_TARGET_STATUS ||
3288 scsi_status != SAM_STAT_CHECK_CONDITION ||
3289 sense_key != NOT_READY ||
3290 asc != ASC_LUN_NOT_READY) {
3291 return 0;
3292 }
3293
3294 /* Determine the reason for not ready state */
3295 ldstat = hpsa_get_volume_status(h, scsi3addr);
3296
3297 /* Keep volume offline in certain cases: */
3298 switch (ldstat) {
3299 case HPSA_LV_UNDERGOING_ERASE:
5ca01204 3300 case HPSA_LV_NOT_AVAILABLE:
9846590e
SC		 3301 case HPSA_LV_UNDERGOING_RPI:
3302 case HPSA_LV_PENDING_RPI:
3303 case HPSA_LV_ENCRYPTED_NO_KEY:
3304 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3305 case HPSA_LV_UNDERGOING_ENCRYPTION:
3306 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3307 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3308 return ldstat;
3309 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3310 /* If VPD status page isn't available,
3311 * use ASC/ASCQ to determine state
3312 */
3313 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3314 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3315 return ldstat;
3316 break;
3317 default:
3318 break;
3319 }
3320 return 0;
3321}
3322
9b5c48c2
SC		 3323/*
3324 * Find out if a logical device supports aborts by simply trying one.
3325 * Smart Array may claim not to support aborts on logical drives, but
3326 * if a MSA2000 * is connected, the drives on that will be presented
3327 * by the Smart Array as logical drives, and aborts may be sent to
3328 * those devices successfully. So the simplest way to find out is
3329 * to simply try an abort and see how the device responds.
3330 */
3331static int hpsa_device_supports_aborts(struct ctlr_info *h,
3332 unsigned char *scsi3addr)
3333{
3334 struct CommandList *c;
3335 struct ErrorInfo *ei;
3336 int rc = 0;
3337
3338 u64 tag = (u64) -1; /* bogus tag */
3339
3340 /* Assume that physical devices support aborts */
3341 if (!is_logical_dev_addr_mode(scsi3addr))
3342 return 1;
3343
3344 c = cmd_alloc(h);
bf43caf3 3345
9b5c48c2
SC		 3346 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
3347 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3348 /* no unmap needed here because no data xfer. */
3349 ei = c->err_info;
3350 switch (ei->CommandStatus) {
3351 case CMD_INVALID:
3352 rc = 0;
3353 break;
3354 case CMD_UNABORTABLE:
3355 case CMD_ABORT_FAILED:
3356 rc = 1;
3357 break;
9437ac43
SC		 3358 case CMD_TMF_STATUS:
3359 rc = hpsa_evaluate_tmf_status(h, c);
3360 break;
9b5c48c2
SC		 3361 default:
3362 rc = 0;
3363 break;
3364 }
3365 cmd_free(h, c);
3366 return rc;
3367}
3368
edd16368 3369static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3370 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3371 unsigned char *is_OBDR_device)
edd16368 3372{
0b0e1d6c
SC		 3373
3374#define OBDR_SIG_OFFSET 43
3375#define OBDR_TAPE_SIG "$DR-10"
3376#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3377#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3378
ea6d3bc3 3379 unsigned char *inq_buff;
0b0e1d6c 3380 unsigned char *obdr_sig;
683fc444 3381 int rc = 0;
edd16368 3382
ea6d3bc3 3383 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
683fc444
DB		 3384 if (!inq_buff) {
3385 rc = -ENOMEM;
edd16368 3386 goto bail_out;
683fc444 3387 }
edd16368 3388
edd16368
SC		 3389 /* Do an inquiry to the device to see what it is. */
3390 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3391 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3392 /* Inquiry failed (msg printed already) */
3393 dev_err(&h->pdev->dev,
3394 "hpsa_update_device_info: inquiry failed\n");
683fc444 3395 rc = -EIO;
edd16368
SC		 3396 goto bail_out;
3397 }
3398
edd16368
SC		 3399 this_device->devtype = (inq_buff[0] & 0x1f);
3400 memcpy(this_device->scsi3addr, scsi3addr, 8);
3401 memcpy(this_device->vendor, &inq_buff[8],
3402 sizeof(this_device->vendor));
3403 memcpy(this_device->model, &inq_buff[16],
3404 sizeof(this_device->model));
edd16368
SC		 3405 memset(this_device->device_id, 0,
3406 sizeof(this_device->device_id));
3407 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
3408 sizeof(this_device->device_id));
3409
3410 if (this_device->devtype == TYPE_DISK &&
283b4a9b 3411 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3412 int volume_offline;
3413
edd16368 3414 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3415 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3416 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3417 volume_offline = hpsa_volume_offline(h, scsi3addr);
3418 if (volume_offline < 0 || volume_offline > 0xff)
3419 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3420 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3421 } else {
edd16368 3422 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3423 this_device->offload_config = 0;
3424 this_device->offload_enabled = 0;
41ce4c35 3425 this_device->offload_to_be_enabled = 0;
a3144e0b 3426 this_device->hba_ioaccel_enabled = 0;
9846590e 3427 this_device->volume_offline = 0;
03383736 3428 this_device->queue_depth = h->nr_cmds;
283b4a9b 3429 }
edd16368 3430
0b0e1d6c
SC		 3431 if (is_OBDR_device) {
3432 /* See if this is a One-Button-Disaster-Recovery device
3433 * by looking for "$DR-10" at offset 43 in inquiry data.
3434 */
3435 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3436 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3437 strncmp(obdr_sig, OBDR_TAPE_SIG,
3438 OBDR_SIG_LEN) == 0);
3439 }
edd16368
SC		 3440 kfree(inq_buff);
3441 return 0;
3442
3443bail_out:
3444 kfree(inq_buff);
683fc444 3445 return rc;
edd16368
SC		 3446}
3447
9b5c48c2
SC		 3448static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3449 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3450{
3451 unsigned long flags;
3452 int rc, entry;
3453 /*
3454 * See if this device supports aborts. If we already know
3455 * the device, we already know if it supports aborts, otherwise
3456 * we have to find out if it supports aborts by trying one.
3457 */
3458 spin_lock_irqsave(&h->devlock, flags);
3459 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3460 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3461 entry >= 0 && entry < h->ndevices) {
3462 dev->supports_aborts = h->dev[entry]->supports_aborts;
3463 spin_unlock_irqrestore(&h->devlock, flags);
3464 } else {
3465 spin_unlock_irqrestore(&h->devlock, flags);
3466 dev->supports_aborts =
3467 hpsa_device_supports_aborts(h, scsi3addr);
3468 if (dev->supports_aborts < 0)
3469 dev->supports_aborts = 0;
3470 }
3471}
3472
4f4eb9f1 3473static unsigned char *ext_target_model[] = {
edd16368
SC		 3474 "MSA2012",
3475 "MSA2024",
3476 "MSA2312",
3477 "MSA2324",
fda38518 3478 "P2000 G3 SAS",
e06c8e5c 3479 "MSA 2040 SAS",
edd16368
SC		 3480 NULL,
3481};
3482
4f4eb9f1 3483static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 3484{
3485 int i;
3486
4f4eb9f1
ST		 3487 for (i = 0; ext_target_model[i]; i++)
3488 if (strncmp(device->model, ext_target_model[i],
3489 strlen(ext_target_model[i])) == 0)
edd16368
SC		 3490 return 1;
3491 return 0;
3492}
3493
3494/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 3495 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 3496 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
3497 * Logical drive target and lun are assigned at this time, but
3498 * physical device lun and target assignment are deferred (assigned
3499 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
3500 */
3501static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3502 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3503{
1f310bde
SC		 3504 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
3505
3506 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3507 /* physical device, target and lun filled in later */
edd16368 3508 if (is_hba_lunid(lunaddrbytes))
1f310bde 3509 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 3510 else
1f310bde
SC		 3511 /* defer target, lun assignment for physical devices */
3512 hpsa_set_bus_target_lun(device, 2, -1, -1);
3513 return;
3514 }
3515 /* It's a logical device */
4f4eb9f1
ST		 3516 if (is_ext_target(h, device)) {
3517 /* external target way, put logicals on bus 1
1f310bde
SC		 3518 * and match target/lun numbers box
3519 * reports, other smart array, bus 0, target 0, match lunid
3520 */
3521 hpsa_set_bus_target_lun(device,
3522 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
3523 return;
edd16368 3524 }
1f310bde 3525 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 3526}
3527
3528/*
3529 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 3530 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 3531 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
3532 * it for some reason. *tmpdevice is the target we're adding,
3533 * this_device is a pointer into the current element of currentsd[]
3534 * that we're building up in update_scsi_devices(), below.
3535 * lunzerobits is a bitmap that tracks which targets already have a
3536 * lun 0 assigned.
3537 * Returns 1 if an enclosure was added, 0 if not.
3538 */
4f4eb9f1 3539static int add_ext_target_dev(struct ctlr_info *h,
edd16368 3540 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 3541 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 3542 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 3543{
3544 unsigned char scsi3addr[8];
3545
1f310bde 3546 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 3547 return 0; /* There is already a lun 0 on this target. */
3548
3549 if (!is_logical_dev_addr_mode(lunaddrbytes))
3550 return 0; /* It's the logical targets that may lack lun 0. */
3551
4f4eb9f1
ST		 3552 if (!is_ext_target(h, tmpdevice))
3553 return 0; /* Only external target devices have this problem. */
edd16368 3554
1f310bde 3555 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 3556 return 0;
3557
c4f8a299 3558 memset(scsi3addr, 0, 8);
1f310bde 3559 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 3560 if (is_hba_lunid(scsi3addr))
3561 return 0; /* Don't add the RAID controller here. */
3562
339b2b14
SC		 3563 if (is_scsi_rev_5(h))
3564 return 0; /* p1210m doesn't need to do this. */
3565
4f4eb9f1 3566 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 3567 dev_warn(&h->pdev->dev, "Maximum number of external "
3568 "target devices exceeded. Check your hardware "
edd16368
SC		 3569 "configuration.");
3570 return 0;
3571 }
3572
0b0e1d6c 3573 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 3574 return 0;
4f4eb9f1 3575 (*n_ext_target_devs)++;
1f310bde
SC		 3576 hpsa_set_bus_target_lun(this_device,
3577 tmpdevice->bus, tmpdevice->target, 0);
9b5c48c2 3578 hpsa_update_device_supports_aborts(h, this_device, scsi3addr);
1f310bde 3579 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 3580 return 1;
3581}
3582
54b6e9e9
ST		 3583/*
3584 * Get address of physical disk used for an ioaccel2 mode command:
3585 * 1. Extract ioaccel2 handle from the command.
3586 * 2. Find a matching ioaccel2 handle from list of physical disks.
3587 * 3. Return:
3588 * 1 and set scsi3addr to address of matching physical
3589 * 0 if no matching physical disk was found.
3590 */
3591static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3592 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3593{
41ce4c35
SC		 3594 struct io_accel2_cmd *c2 =
3595 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3596 unsigned long flags;
54b6e9e9 3597 int i;
54b6e9e9 3598
41ce4c35
SC		 3599 spin_lock_irqsave(&h->devlock, flags);
3600 for (i = 0; i < h->ndevices; i++)
3601 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3602 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3603 sizeof(h->dev[i]->scsi3addr));
3604 spin_unlock_irqrestore(&h->devlock, flags);
3605 return 1;
3606 }
3607 spin_unlock_irqrestore(&h->devlock, flags);
3608 return 0;
54b6e9e9 3609}
41ce4c35 3610
edd16368
SC		 3611/*
3612 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3613 * logdev. The number of luns in physdev and logdev are returned in
3614 * *nphysicals and *nlogicals, respectively.
3615 * Returns 0 on success, -1 otherwise.
3616 */
3617static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3618 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3619 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3620{
03383736 3621 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3622 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3623 return -1;
3624 }
03383736 3625 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3626 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3627 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3628 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3629 *nphysicals = HPSA_MAX_PHYS_LUN;
3630 }
03383736 3631 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3632 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3633 return -1;
3634 }
6df1e954 3635 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3636 /* Reject Logicals in excess of our max capability. */
3637 if (*nlogicals > HPSA_MAX_LUN) {
3638 dev_warn(&h->pdev->dev,
3639 "maximum logical LUNs (%d) exceeded. "
3640 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3641 *nlogicals - HPSA_MAX_LUN);
3642 *nlogicals = HPSA_MAX_LUN;
3643 }
3644 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3645 dev_warn(&h->pdev->dev,
3646 "maximum logical + physical LUNs (%d) exceeded. "
3647 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3648 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3649 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3650 }
3651 return 0;
3652}
3653
42a91641
DB		 3654static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3655 int i, int nphysicals, int nlogicals,
a93aa1fe 3656 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3657 struct ReportLUNdata *logdev_list)
3658{
3659 /* Helper function, figure out where the LUN ID info is coming from
3660 * given index i, lists of physical and logical devices, where in
3661 * the list the raid controller is supposed to appear (first or last)
3662 */
3663
3664 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3665 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3666
3667 if (i == raid_ctlr_position)
3668 return RAID_CTLR_LUNID;
3669
3670 if (i < logicals_start)
d5b5d964
SC		 3671 return &physdev_list->LUN[i -
3672 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3673
3674 if (i < last_device)
3675 return &logdev_list->LUN[i - nphysicals -
3676 (raid_ctlr_position == 0)][0];
3677 BUG();
3678 return NULL;
3679}
3680
03383736
DB		 3681/* get physical drive ioaccel handle and queue depth */
3682static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3683 struct hpsa_scsi_dev_t *dev,
f2039b03 3684 struct ReportExtendedLUNdata *rlep, int rle_index,
03383736
DB		 3685 struct bmic_identify_physical_device *id_phys)
3686{
3687 int rc;
f2039b03 3688 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
03383736
DB		 3689
3690 dev->ioaccel_handle = rle->ioaccel_handle;
f2039b03 3691 if ((rle->device_flags & 0x08) && dev->ioaccel_handle)
a3144e0b 3692 dev->hba_ioaccel_enabled = 1;
03383736 3693 memset(id_phys, 0, sizeof(*id_phys));
f2039b03
DB		 3694 rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0],
3695 GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys,
03383736
DB		 3696 sizeof(*id_phys));
3697 if (!rc)
3698 /* Reserve space for FW operations */
3699#define DRIVE_CMDS_RESERVED_FOR_FW 2
3700#define DRIVE_QUEUE_DEPTH 7
3701 dev->queue_depth =
3702 le16_to_cpu(id_phys->current_queue_depth_limit) -
3703 DRIVE_CMDS_RESERVED_FOR_FW;
3704 else
3705 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
03383736
DB		 3706}
3707
8270b862 3708static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
f2039b03 3709 struct ReportExtendedLUNdata *rlep, int rle_index,
8270b862
JH		 3710 struct bmic_identify_physical_device *id_phys)
3711{
f2039b03
DB		 3712 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
3713
3714 if ((rle->device_flags & 0x08) && this_device->ioaccel_handle)
8270b862
JH		 3715 this_device->hba_ioaccel_enabled = 1;
3716
3717 memcpy(&this_device->active_path_index,
3718 &id_phys->active_path_number,
3719 sizeof(this_device->active_path_index));
3720 memcpy(&this_device->path_map,
3721 &id_phys->redundant_path_present_map,
3722 sizeof(this_device->path_map));
3723 memcpy(&this_device->box,
3724 &id_phys->alternate_paths_phys_box_on_port,
3725 sizeof(this_device->box));
3726 memcpy(&this_device->phys_connector,
3727 &id_phys->alternate_paths_phys_connector,
3728 sizeof(this_device->phys_connector));
3729 memcpy(&this_device->bay,
3730 &id_phys->phys_bay_in_box,
3731 sizeof(this_device->bay));
3732}
3733
8aa60681 3734static void hpsa_update_scsi_devices(struct ctlr_info *h)
edd16368
SC		 3735{
3736 /* the idea here is we could get notified
3737 * that some devices have changed, so we do a report
3738 * physical luns and report logical luns cmd, and adjust
3739 * our list of devices accordingly.
3740 *
3741 * The scsi3addr's of devices won't change so long as the
3742 * adapter is not reset. That means we can rescan and
3743 * tell which devices we already know about, vs. new
3744 * devices, vs. disappearing devices.
3745 */
a93aa1fe 3746 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3747 struct ReportLUNdata *logdev_list = NULL;
03383736 3748 struct bmic_identify_physical_device *id_phys = NULL;
01a02ffc
SC		 3749 u32 nphysicals = 0;
3750 u32 nlogicals = 0;
3751 u32 ndev_allocated = 0;
edd16368
SC		 3752 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3753 int ncurrent = 0;
4f4eb9f1 3754 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3755 int raid_ctlr_position;
aca4a520 3756 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3757
cfe5badc 3758 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 3759 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3760 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 3761 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 3762 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
edd16368 3763
03383736
DB		 3764 if (!currentsd || !physdev_list || !logdev_list ||
3765 !tmpdevice || !id_phys) {
edd16368
SC		 3766 dev_err(&h->pdev->dev, "out of memory\n");
3767 goto out;
3768 }
3769 memset(lunzerobits, 0, sizeof(lunzerobits));
3770
853633e8
DB		 3771 h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */
3772
03383736 3773 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
853633e8
DB		 3774 logdev_list, &nlogicals)) {
3775 h->drv_req_rescan = 1;
edd16368 3776 goto out;
853633e8 3777 }
edd16368 3778
aca4a520
ST		 3779 /* We might see up to the maximum number of logical and physical disks
3780 * plus external target devices, and a device for the local RAID
3781 * controller.
edd16368 3782 */
aca4a520 3783 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3784
3785 /* Allocate the per device structures */
3786 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3787 if (i >= HPSA_MAX_DEVICES) {
3788 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3789 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3790 ndevs_to_allocate - HPSA_MAX_DEVICES);
3791 break;
3792 }
3793
edd16368
SC		 3794 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3795 if (!currentsd[i]) {
3796 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3797 __FILE__, __LINE__);
853633e8 3798 h->drv_req_rescan = 1;
edd16368
SC		 3799 goto out;
3800 }
3801 ndev_allocated++;
3802 }
3803
8645291b 3804 if (is_scsi_rev_5(h))
339b2b14
SC		 3805 raid_ctlr_position = 0;
3806 else
3807 raid_ctlr_position = nphysicals + nlogicals;
3808
edd16368 3809 /* adjust our table of devices */
4f4eb9f1 3810 n_ext_target_devs = 0;
edd16368 3811 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3812 u8 *lunaddrbytes, is_OBDR = 0;
683fc444 3813 int rc = 0;
f2039b03 3814 int phys_dev_index = i - (raid_ctlr_position == 0);
edd16368
SC		 3815
3816 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3817 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3818 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 3819
3820 /* skip masked non-disk devices */
3821 if (MASKED_DEVICE(lunaddrbytes))
3822 if (i < nphysicals + (raid_ctlr_position == 0) &&
f2039b03
DB		 3823 (physdev_list->
3824 LUN[phys_dev_index].device_flags & 0x01))
41ce4c35 3825 continue;
edd16368
SC		 3826
3827 /* Get device type, vendor, model, device id */
683fc444
DB		 3828 rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3829 &is_OBDR);
3830 if (rc == -ENOMEM) {
3831 dev_warn(&h->pdev->dev,
3832 "Out of memory, rescan deferred.\n");
853633e8 3833 h->drv_req_rescan = 1;
683fc444 3834 goto out;
853633e8 3835 }
683fc444
DB		 3836 if (rc) {
3837 dev_warn(&h->pdev->dev,
3838 "Inquiry failed, skipping device.\n");
3839 continue;
3840 }
3841
1f310bde 3842 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 3843 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 3844 this_device = currentsd[ncurrent];
3845
3846 /*
4f4eb9f1 3847 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3848 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3849 * is nonetheless an enclosure device there. We have to
3850 * present that otherwise linux won't find anything if
3851 * there is no lun 0.
3852 */
4f4eb9f1 3853 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3854 lunaddrbytes, lunzerobits,
4f4eb9f1 3855 &n_ext_target_devs)) {
edd16368
SC		 3856 ncurrent++;
3857 this_device = currentsd[ncurrent];
3858 }
3859
3860 *this_device = *tmpdevice;
edd16368 3861
41ce4c35
SC		 3862 /* do not expose masked devices */
3863 if (MASKED_DEVICE(lunaddrbytes) &&
3864 i < nphysicals + (raid_ctlr_position == 0)) {
41ce4c35
SC		 3865 this_device->expose_state = HPSA_DO_NOT_EXPOSE;
3866 } else {
3867 this_device->expose_state =
3868 HPSA_SG_ATTACH | HPSA_ULD_ATTACH;
3869 }
3870
edd16368 3871 switch (this_device->devtype) {
0b0e1d6c 3872 case TYPE_ROM:
edd16368
SC		 3873 /* We don't *really* support actual CD-ROM devices,
3874 * just "One Button Disaster Recovery" tape drive
3875 * which temporarily pretends to be a CD-ROM drive.
3876 * So we check that the device is really an OBDR tape
3877 * device by checking for "$DR-10" in bytes 43-48 of
3878 * the inquiry data.
3879 */
0b0e1d6c
SC		 3880 if (is_OBDR)
3881 ncurrent++;
edd16368
SC		 3882 break;
3883 case TYPE_DISK:
b9092b79
KB		 3884 if (i < nphysicals + (raid_ctlr_position == 0)) {
3885 /* The disk is in HBA mode. */
3886 /* Never use RAID mapper in HBA mode. */
ecf418d1 3887 this_device->offload_enabled = 0;
b9092b79 3888 hpsa_get_ioaccel_drive_info(h, this_device,
f2039b03
DB		 3889 physdev_list, phys_dev_index, id_phys);
3890 hpsa_get_path_info(this_device,
3891 physdev_list, phys_dev_index, id_phys);
b9092b79 3892 }
ecf418d1 3893 ncurrent++;
edd16368
SC		 3894 break;
3895 case TYPE_TAPE:
3896 case TYPE_MEDIUM_CHANGER:
41ce4c35 3897 case TYPE_ENCLOSURE:
b9092b79 3898 ncurrent++;
41ce4c35 3899 break;
edd16368
SC		 3900 case TYPE_RAID:
3901 /* Only present the Smartarray HBA as a RAID controller.
3902 * If it's a RAID controller other than the HBA itself
3903 * (an external RAID controller, MSA500 or similar)
3904 * don't present it.
3905 */
3906 if (!is_hba_lunid(lunaddrbytes))
3907 break;
3908 ncurrent++;
3909 break;
3910 default:
3911 break;
3912 }
cfe5badc 3913 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3914 break;
3915 }
8aa60681 3916 adjust_hpsa_scsi_table(h, currentsd, ncurrent);
edd16368
SC		 3917out:
3918 kfree(tmpdevice);
3919 for (i = 0; i < ndev_allocated; i++)
3920 kfree(currentsd[i]);
3921 kfree(currentsd);
edd16368
SC		 3922 kfree(physdev_list);
3923 kfree(logdev_list);
03383736 3924 kfree(id_phys);
edd16368
SC		 3925}
3926
ec5cbf04
WS		 3927static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3928 struct scatterlist *sg)
3929{
3930 u64 addr64 = (u64) sg_dma_address(sg);
3931 unsigned int len = sg_dma_len(sg);
3932
3933 desc->Addr = cpu_to_le64(addr64);
3934 desc->Len = cpu_to_le32(len);
3935 desc->Ext = 0;
3936}
3937
c7ee65b3
WS		 3938/*
3939 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3940 * dma mapping and fills in the scatter gather entries of the
3941 * hpsa command, cp.
3942 */
33a2ffce 3943static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3944 struct CommandList *cp,
3945 struct scsi_cmnd *cmd)
3946{
edd16368 3947 struct scatterlist *sg;
b3a7ba7c 3948 int use_sg, i, sg_limit, chained, last_sg;
33a2ffce 3949 struct SGDescriptor *curr_sg;
edd16368 3950
33a2ffce 3951 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3952
3953 use_sg = scsi_dma_map(cmd);
3954 if (use_sg < 0)
3955 return use_sg;
3956
3957 if (!use_sg)
3958 goto sglist_finished;
3959
b3a7ba7c
WS		 3960 /*
3961 * If the number of entries is greater than the max for a single list,
3962 * then we have a chained list; we will set up all but one entry in the
3963 * first list (the last entry is saved for link information);
3964 * otherwise, we don't have a chained list and we'll set up at each of
3965 * the entries in the one list.
3966 */
33a2ffce 3967 curr_sg = cp->SG;
b3a7ba7c
WS		 3968 chained = use_sg > h->max_cmd_sg_entries;
3969 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
3970 last_sg = scsi_sg_count(cmd) - 1;
3971 scsi_for_each_sg(cmd, sg, sg_limit, i) {
ec5cbf04 3972 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 3973 curr_sg++;
3974 }
ec5cbf04 3975
b3a7ba7c
WS		 3976 if (chained) {
3977 /*
3978 * Continue with the chained list. Set curr_sg to the chained
3979 * list. Modify the limit to the total count less the entries
3980 * we've already set up. Resume the scan at the list entry
3981 * where the previous loop left off.
3982 */
3983 curr_sg = h->cmd_sg_list[cp->cmdindex];
3984 sg_limit = use_sg - sg_limit;
3985 for_each_sg(sg, sg, sg_limit, i) {
3986 hpsa_set_sg_descriptor(curr_sg, sg);
3987 curr_sg++;
3988 }
3989 }
3990
ec5cbf04 3991 /* Back the pointer up to the last entry and mark it as "last". */
b3a7ba7c 3992 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3993
3994 if (use_sg + chained > h->maxSG)
3995 h->maxSG = use_sg + chained;
3996
3997 if (chained) {
3998 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3999 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 4000 if (hpsa_map_sg_chain_block(h, cp)) {
4001 scsi_dma_unmap(cmd);
4002 return -1;
4003 }
33a2ffce 4004 return 0;
edd16368
SC		 4005 }
4006
4007sglist_finished:
4008
01a02ffc 4009 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 4010 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 4011 return 0;
4012}
4013
283b4a9b
SC		 4014#define IO_ACCEL_INELIGIBLE (1)
4015static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
4016{
4017 int is_write = 0;
4018 u32 block;
4019 u32 block_cnt;
4020
4021 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
4022 switch (cdb[0]) {
4023 case WRITE_6:
4024 case WRITE_12:
4025 is_write = 1;
4026 case READ_6:
4027 case READ_12:
4028 if (*cdb_len == 6) {
c8a6c9a6 4029 block = get_unaligned_be16(&cdb[2]);
283b4a9b 4030 block_cnt = cdb[4];
c8a6c9a6
DB		 4031 if (block_cnt == 0)
4032 block_cnt = 256;
283b4a9b
SC		 4033 } else {
4034 BUG_ON(*cdb_len != 12);
c8a6c9a6
DB		 4035 block = get_unaligned_be32(&cdb[2]);
4036 block_cnt = get_unaligned_be32(&cdb[6]);
283b4a9b
SC		 4037 }
4038 if (block_cnt > 0xffff)
4039 return IO_ACCEL_INELIGIBLE;
4040
4041 cdb[0] = is_write ? WRITE_10 : READ_10;
4042 cdb[1] = 0;
4043 cdb[2] = (u8) (block >> 24);
4044 cdb[3] = (u8) (block >> 16);
4045 cdb[4] = (u8) (block >> 8);
4046 cdb[5] = (u8) (block);
4047 cdb[6] = 0;
4048 cdb[7] = (u8) (block_cnt >> 8);
4049 cdb[8] = (u8) (block_cnt);
4050 cdb[9] = 0;
4051 *cdb_len = 10;
4052 break;
4053 }
4054 return 0;
4055}
4056
c349775e 4057static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 4058 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4059 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 4060{
4061 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 4062 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
4063 unsigned int len;
4064 unsigned int total_len = 0;
4065 struct scatterlist *sg;
4066 u64 addr64;
4067 int use_sg, i;
4068 struct SGDescriptor *curr_sg;
4069 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
4070
283b4a9b 4071 /* TODO: implement chaining support */
03383736
DB		 4072 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
4073 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4074 return IO_ACCEL_INELIGIBLE;
03383736 4075 }
283b4a9b 4076
e1f7de0c
MG		 4077 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
4078
03383736
DB		 4079 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4080 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4081 return IO_ACCEL_INELIGIBLE;
03383736 4082 }
283b4a9b 4083
e1f7de0c
MG		 4084 c->cmd_type = CMD_IOACCEL1;
4085
4086 /* Adjust the DMA address to point to the accelerated command buffer */
4087 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
4088 (c->cmdindex * sizeof(*cp));
4089 BUG_ON(c->busaddr & 0x0000007F);
4090
4091 use_sg = scsi_dma_map(cmd);
03383736
DB		 4092 if (use_sg < 0) {
4093 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 4094 return use_sg;
03383736 4095 }
e1f7de0c
MG		 4096
4097 if (use_sg) {
4098 curr_sg = cp->SG;
4099 scsi_for_each_sg(cmd, sg, use_sg, i) {
4100 addr64 = (u64) sg_dma_address(sg);
4101 len = sg_dma_len(sg);
4102 total_len += len;
50a0decf
SC		 4103 curr_sg->Addr = cpu_to_le64(addr64);
4104 curr_sg->Len = cpu_to_le32(len);
4105 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 4106 curr_sg++;
4107 }
50a0decf 4108 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 4109
4110 switch (cmd->sc_data_direction) {
4111 case DMA_TO_DEVICE:
4112 control |= IOACCEL1_CONTROL_DATA_OUT;
4113 break;
4114 case DMA_FROM_DEVICE:
4115 control |= IOACCEL1_CONTROL_DATA_IN;
4116 break;
4117 case DMA_NONE:
4118 control |= IOACCEL1_CONTROL_NODATAXFER;
4119 break;
4120 default:
4121 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4122 cmd->sc_data_direction);
4123 BUG();
4124 break;
4125 }
4126 } else {
4127 control |= IOACCEL1_CONTROL_NODATAXFER;
4128 }
4129
c349775e 4130 c->Header.SGList = use_sg;
e1f7de0c 4131 /* Fill out the command structure to submit */
2b08b3e9
DB		 4132 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4133 cp->transfer_len = cpu_to_le32(total_len);
4134 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4135 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4136 cp->control = cpu_to_le32(control);
283b4a9b
SC		 4137 memcpy(cp->CDB, cdb, cdb_len);
4138 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 4139 /* Tag was already set at init time. */
283b4a9b 4140 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 4141 return 0;
4142}
edd16368 4143
283b4a9b
SC		 4144/*
4145 * Queue a command directly to a device behind the controller using the
4146 * I/O accelerator path.
4147 */
4148static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4149 struct CommandList *c)
4150{
4151 struct scsi_cmnd *cmd = c->scsi_cmd;
4152 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4153
03383736
DB		 4154 c->phys_disk = dev;
4155
283b4a9b 4156 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 4157 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 4158}
4159
dd0e19f3
ST		 4160/*
4161 * Set encryption parameters for the ioaccel2 request
4162 */
4163static void set_encrypt_ioaccel2(struct ctlr_info *h,
4164 struct CommandList *c, struct io_accel2_cmd *cp)
4165{
4166 struct scsi_cmnd *cmd = c->scsi_cmd;
4167 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4168 struct raid_map_data *map = &dev->raid_map;
4169 u64 first_block;
4170
dd0e19f3 4171 /* Are we doing encryption on this device */
2b08b3e9 4172 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 4173 return;
4174 /* Set the data encryption key index. */
4175 cp->dekindex = map->dekindex;
4176
4177 /* Set the encryption enable flag, encoded into direction field. */
4178 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4179
4180 /* Set encryption tweak values based on logical block address
4181 * If block size is 512, tweak value is LBA.
4182 * For other block sizes, tweak is (LBA * block size)/ 512)
4183 */
4184 switch (cmd->cmnd[0]) {
4185 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
4186 case WRITE_6:
4187 case READ_6:
2b08b3e9 4188 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 4189 break;
4190 case WRITE_10:
4191 case READ_10:
dd0e19f3
ST		 4192 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4193 case WRITE_12:
4194 case READ_12:
2b08b3e9 4195 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 4196 break;
4197 case WRITE_16:
4198 case READ_16:
2b08b3e9 4199 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 4200 break;
4201 default:
4202 dev_err(&h->pdev->dev,
2b08b3e9
DB		 4203 "ERROR: %s: size (0x%x) not supported for encryption\n",
4204 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 4205 BUG();
4206 break;
4207 }
2b08b3e9
DB		 4208
4209 if (le32_to_cpu(map->volume_blk_size) != 512)
4210 first_block = first_block *
4211 le32_to_cpu(map->volume_blk_size)/512;
4212
4213 cp->tweak_lower = cpu_to_le32(first_block);
4214 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 4215}
4216
c349775e
ST		 4217static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4218 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4219 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 4220{
4221 struct scsi_cmnd *cmd = c->scsi_cmd;
4222 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4223 struct ioaccel2_sg_element *curr_sg;
4224 int use_sg, i;
4225 struct scatterlist *sg;
4226 u64 addr64;
4227 u32 len;
4228 u32 total_len = 0;
4229
d9a729f3 4230 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 4231
03383736
DB		 4232 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4233 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4234 return IO_ACCEL_INELIGIBLE;
03383736
DB		 4235 }
4236
c349775e
ST		 4237 c->cmd_type = CMD_IOACCEL2;
4238 /* Adjust the DMA address to point to the accelerated command buffer */
4239 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4240 (c->cmdindex * sizeof(*cp));
4241 BUG_ON(c->busaddr & 0x0000007F);
4242
4243 memset(cp, 0, sizeof(*cp));
4244 cp->IU_type = IOACCEL2_IU_TYPE;
4245
4246 use_sg = scsi_dma_map(cmd);
03383736
DB		 4247 if (use_sg < 0) {
4248 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4249 return use_sg;
03383736 4250 }
c349775e
ST		 4251
4252 if (use_sg) {
c349775e 4253 curr_sg = cp->sg;
d9a729f3
WS		 4254 if (use_sg > h->ioaccel_maxsg) {
4255 addr64 = le64_to_cpu(
4256 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4257 curr_sg->address = cpu_to_le64(addr64);
4258 curr_sg->length = 0;
4259 curr_sg->reserved[0] = 0;
4260 curr_sg->reserved[1] = 0;
4261 curr_sg->reserved[2] = 0;
4262 curr_sg->chain_indicator = 0x80;
4263
4264 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4265 }
c349775e
ST		 4266 scsi_for_each_sg(cmd, sg, use_sg, i) {
4267 addr64 = (u64) sg_dma_address(sg);
4268 len = sg_dma_len(sg);
4269 total_len += len;
4270 curr_sg->address = cpu_to_le64(addr64);
4271 curr_sg->length = cpu_to_le32(len);
4272 curr_sg->reserved[0] = 0;
4273 curr_sg->reserved[1] = 0;
4274 curr_sg->reserved[2] = 0;
4275 curr_sg->chain_indicator = 0;
4276 curr_sg++;
4277 }
4278
4279 switch (cmd->sc_data_direction) {
4280 case DMA_TO_DEVICE:
dd0e19f3
ST		 4281 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4282 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 4283 break;
4284 case DMA_FROM_DEVICE:
dd0e19f3
ST		 4285 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4286 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 4287 break;
4288 case DMA_NONE:
dd0e19f3
ST		 4289 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4290 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 4291 break;
4292 default:
4293 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4294 cmd->sc_data_direction);
4295 BUG();
4296 break;
4297 }
4298 } else {
dd0e19f3
ST		 4299 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4300 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 4301 }
dd0e19f3
ST		 4302
4303 /* Set encryption parameters, if necessary */
4304 set_encrypt_ioaccel2(h, c, cp);
4305
2b08b3e9 4306 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 4307 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 4308 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 4309
c349775e
ST		 4310 cp->data_len = cpu_to_le32(total_len);
4311 cp->err_ptr = cpu_to_le64(c->busaddr +
4312 offsetof(struct io_accel2_cmd, error_data));
50a0decf 4313 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 4314
d9a729f3
WS		 4315 /* fill in sg elements */
4316 if (use_sg > h->ioaccel_maxsg) {
4317 cp->sg_count = 1;
4318 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4319 atomic_dec(&phys_disk->ioaccel_cmds_out);
4320 scsi_dma_unmap(cmd);
4321 return -1;
4322 }
4323 } else
4324 cp->sg_count = (u8) use_sg;
4325
c349775e
ST		 4326 enqueue_cmd_and_start_io(h, c);
4327 return 0;
4328}
4329
4330/*
4331 * Queue a command to the correct I/O accelerator path.
4332 */
4333static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4334 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4335 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 4336{
03383736
DB		 4337 /* Try to honor the device's queue depth */
4338 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4339 phys_disk->queue_depth) {
4340 atomic_dec(&phys_disk->ioaccel_cmds_out);
4341 return IO_ACCEL_INELIGIBLE;
4342 }
c349775e
ST		 4343 if (h->transMethod & CFGTBL_Trans_io_accel1)
4344 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4345 cdb, cdb_len, scsi3addr,
4346 phys_disk);
c349775e
ST		 4347 else
4348 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4349 cdb, cdb_len, scsi3addr,
4350 phys_disk);
c349775e
ST		 4351}
4352
6b80b18f
ST		 4353static void raid_map_helper(struct raid_map_data *map,
4354 int offload_to_mirror, u32 *map_index, u32 *current_group)
4355{
4356 if (offload_to_mirror == 0) {
4357 /* use physical disk in the first mirrored group. */
2b08b3e9 4358 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4359 return;
4360 }
4361 do {
4362 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4363 *current_group = *map_index /
4364 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4365 if (offload_to_mirror == *current_group)
4366 continue;
2b08b3e9 4367 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4368 /* select map index from next group */
2b08b3e9 4369 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4370 (*current_group)++;
4371 } else {
4372 /* select map index from first group */
2b08b3e9 4373 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4374 *current_group = 0;
4375 }
4376 } while (offload_to_mirror != *current_group);
4377}
4378
283b4a9b
SC		 4379/*
4380 * Attempt to perform offload RAID mapping for a logical volume I/O.
4381 */
4382static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4383 struct CommandList *c)
4384{
4385 struct scsi_cmnd *cmd = c->scsi_cmd;
4386 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4387 struct raid_map_data *map = &dev->raid_map;
4388 struct raid_map_disk_data *dd = &map->data[0];
4389 int is_write = 0;
4390 u32 map_index;
4391 u64 first_block, last_block;
4392 u32 block_cnt;
4393 u32 blocks_per_row;
4394 u64 first_row, last_row;
4395 u32 first_row_offset, last_row_offset;
4396 u32 first_column, last_column;
6b80b18f
ST		 4397 u64 r0_first_row, r0_last_row;
4398 u32 r5or6_blocks_per_row;
4399 u64 r5or6_first_row, r5or6_last_row;
4400 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4401 u32 r5or6_first_column, r5or6_last_column;
4402 u32 total_disks_per_row;
4403 u32 stripesize;
4404 u32 first_group, last_group, current_group;
283b4a9b
SC		 4405 u32 map_row;
4406 u32 disk_handle;
4407 u64 disk_block;
4408 u32 disk_block_cnt;
4409 u8 cdb[16];
4410 u8 cdb_len;
2b08b3e9 4411 u16 strip_size;
283b4a9b
SC		 4412#if BITS_PER_LONG == 32
4413 u64 tmpdiv;
4414#endif
6b80b18f 4415 int offload_to_mirror;
283b4a9b 4416
283b4a9b
SC		 4417 /* check for valid opcode, get LBA and block count */
4418 switch (cmd->cmnd[0]) {
4419 case WRITE_6:
4420 is_write = 1;
4421 case READ_6:
c8a6c9a6 4422 first_block = get_unaligned_be16(&cmd->cmnd[2]);
283b4a9b 4423 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4424 if (block_cnt == 0)
4425 block_cnt = 256;
283b4a9b
SC		 4426 break;
4427 case WRITE_10:
4428 is_write = 1;
4429 case READ_10:
4430 first_block =
4431 (((u64) cmd->cmnd[2]) << 24) |
4432 (((u64) cmd->cmnd[3]) << 16) |
4433 (((u64) cmd->cmnd[4]) << 8) |
4434 cmd->cmnd[5];
4435 block_cnt =
4436 (((u32) cmd->cmnd[7]) << 8) |
4437 cmd->cmnd[8];
4438 break;
4439 case WRITE_12:
4440 is_write = 1;
4441 case READ_12:
4442 first_block =
4443 (((u64) cmd->cmnd[2]) << 24) |
4444 (((u64) cmd->cmnd[3]) << 16) |
4445 (((u64) cmd->cmnd[4]) << 8) |
4446 cmd->cmnd[5];
4447 block_cnt =
4448 (((u32) cmd->cmnd[6]) << 24) |
4449 (((u32) cmd->cmnd[7]) << 16) |
4450 (((u32) cmd->cmnd[8]) << 8) |
4451 cmd->cmnd[9];
4452 break;
4453 case WRITE_16:
4454 is_write = 1;
4455 case READ_16:
4456 first_block =
4457 (((u64) cmd->cmnd[2]) << 56) |
4458 (((u64) cmd->cmnd[3]) << 48) |
4459 (((u64) cmd->cmnd[4]) << 40) |
4460 (((u64) cmd->cmnd[5]) << 32) |
4461 (((u64) cmd->cmnd[6]) << 24) |
4462 (((u64) cmd->cmnd[7]) << 16) |
4463 (((u64) cmd->cmnd[8]) << 8) |
4464 cmd->cmnd[9];
4465 block_cnt =
4466 (((u32) cmd->cmnd[10]) << 24) |
4467 (((u32) cmd->cmnd[11]) << 16) |
4468 (((u32) cmd->cmnd[12]) << 8) |
4469 cmd->cmnd[13];
4470 break;
4471 default:
4472 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4473 }
283b4a9b
SC		 4474 last_block = first_block + block_cnt - 1;
4475
4476 /* check for write to non-RAID-0 */
4477 if (is_write && dev->raid_level != 0)
4478 return IO_ACCEL_INELIGIBLE;
4479
4480 /* check for invalid block or wraparound */
2b08b3e9
DB		 4481 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4482 last_block < first_block)
283b4a9b
SC		 4483 return IO_ACCEL_INELIGIBLE;
4484
4485 /* calculate stripe information for the request */
2b08b3e9
DB		 4486 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4487 le16_to_cpu(map->strip_size);
4488 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4489#if BITS_PER_LONG == 32
4490 tmpdiv = first_block;
4491 (void) do_div(tmpdiv, blocks_per_row);
4492 first_row = tmpdiv;
4493 tmpdiv = last_block;
4494 (void) do_div(tmpdiv, blocks_per_row);
4495 last_row = tmpdiv;
4496 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4497 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4498 tmpdiv = first_row_offset;
2b08b3e9 4499 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4500 first_column = tmpdiv;
4501 tmpdiv = last_row_offset;
2b08b3e9 4502 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4503 last_column = tmpdiv;
4504#else
4505 first_row = first_block / blocks_per_row;
4506 last_row = last_block / blocks_per_row;
4507 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4508 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4509 first_column = first_row_offset / strip_size;
4510 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4511#endif
4512
4513 /* if this isn't a single row/column then give to the controller */
4514 if ((first_row != last_row) || (first_column != last_column))
4515 return IO_ACCEL_INELIGIBLE;
4516
4517 /* proceeding with driver mapping */
2b08b3e9
DB		 4518 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4519 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4520 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4521 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4522 map_index = (map_row * total_disks_per_row) + first_column;
4523
4524 switch (dev->raid_level) {
4525 case HPSA_RAID_0:
4526 break; /* nothing special to do */
4527 case HPSA_RAID_1:
4528 /* Handles load balance across RAID 1 members.
4529 * (2-drive R1 and R10 with even # of drives.)
4530 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4531 */
2b08b3e9 4532 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4533 if (dev->offload_to_mirror)
2b08b3e9 4534 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4535 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4536 break;
4537 case HPSA_RAID_ADM:
4538 /* Handles N-way mirrors (R1-ADM)
4539 * and R10 with # of drives divisible by 3.)
4540 */
2b08b3e9 4541 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4542
4543 offload_to_mirror = dev->offload_to_mirror;
4544 raid_map_helper(map, offload_to_mirror,
4545 &map_index, &current_group);
4546 /* set mirror group to use next time */
4547 offload_to_mirror =
2b08b3e9
DB		 4548 (offload_to_mirror >=
4549 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4550 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4551 dev->offload_to_mirror = offload_to_mirror;
4552 /* Avoid direct use of dev->offload_to_mirror within this
4553 * function since multiple threads might simultaneously
4554 * increment it beyond the range of dev->layout_map_count -1.
4555 */
4556 break;
4557 case HPSA_RAID_5:
4558 case HPSA_RAID_6:
2b08b3e9 4559 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4560 break;
4561
4562 /* Verify first and last block are in same RAID group */
4563 r5or6_blocks_per_row =
2b08b3e9
DB		 4564 le16_to_cpu(map->strip_size) *
4565 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4566 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4567 stripesize = r5or6_blocks_per_row *
4568 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4569#if BITS_PER_LONG == 32
4570 tmpdiv = first_block;
4571 first_group = do_div(tmpdiv, stripesize);
4572 tmpdiv = first_group;
4573 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4574 first_group = tmpdiv;
4575 tmpdiv = last_block;
4576 last_group = do_div(tmpdiv, stripesize);
4577 tmpdiv = last_group;
4578 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4579 last_group = tmpdiv;
4580#else
4581 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4582 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4583#endif
000ff7c2 4584 if (first_group != last_group)
6b80b18f
ST		 4585 return IO_ACCEL_INELIGIBLE;
4586
4587 /* Verify request is in a single row of RAID 5/6 */
4588#if BITS_PER_LONG == 32
4589 tmpdiv = first_block;
4590 (void) do_div(tmpdiv, stripesize);
4591 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4592 tmpdiv = last_block;
4593 (void) do_div(tmpdiv, stripesize);
4594 r5or6_last_row = r0_last_row = tmpdiv;
4595#else
4596 first_row = r5or6_first_row = r0_first_row =
4597 first_block / stripesize;
4598 r5or6_last_row = r0_last_row = last_block / stripesize;
4599#endif
4600 if (r5or6_first_row != r5or6_last_row)
4601 return IO_ACCEL_INELIGIBLE;
4602
4603
4604 /* Verify request is in a single column */
4605#if BITS_PER_LONG == 32
4606 tmpdiv = first_block;
4607 first_row_offset = do_div(tmpdiv, stripesize);
4608 tmpdiv = first_row_offset;
4609 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4610 r5or6_first_row_offset = first_row_offset;
4611 tmpdiv = last_block;
4612 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4613 tmpdiv = r5or6_last_row_offset;
4614 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4615 tmpdiv = r5or6_first_row_offset;
4616 (void) do_div(tmpdiv, map->strip_size);
4617 first_column = r5or6_first_column = tmpdiv;
4618 tmpdiv = r5or6_last_row_offset;
4619 (void) do_div(tmpdiv, map->strip_size);
4620 r5or6_last_column = tmpdiv;
4621#else
4622 first_row_offset = r5or6_first_row_offset =
4623 (u32)((first_block % stripesize) %
4624 r5or6_blocks_per_row);
4625
4626 r5or6_last_row_offset =
4627 (u32)((last_block % stripesize) %
4628 r5or6_blocks_per_row);
4629
4630 first_column = r5or6_first_column =
2b08b3e9 4631 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4632 r5or6_last_column =
2b08b3e9 4633 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4634#endif
4635 if (r5or6_first_column != r5or6_last_column)
4636 return IO_ACCEL_INELIGIBLE;
4637
4638 /* Request is eligible */
4639 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4640 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4641
4642 map_index = (first_group *
2b08b3e9 4643 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4644 (map_row * total_disks_per_row) + first_column;
4645 break;
4646 default:
4647 return IO_ACCEL_INELIGIBLE;
283b4a9b 4648 }
6b80b18f 4649
07543e0c
SC		 4650 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4651 return IO_ACCEL_INELIGIBLE;
4652
03383736
DB		 4653 c->phys_disk = dev->phys_disk[map_index];
4654
283b4a9b 4655 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 4656 disk_block = le64_to_cpu(map->disk_starting_blk) +
4657 first_row * le16_to_cpu(map->strip_size) +
4658 (first_row_offset - first_column *
4659 le16_to_cpu(map->strip_size));
283b4a9b
SC		 4660 disk_block_cnt = block_cnt;
4661
4662 /* handle differing logical/physical block sizes */
4663 if (map->phys_blk_shift) {
4664 disk_block <<= map->phys_blk_shift;
4665 disk_block_cnt <<= map->phys_blk_shift;
4666 }
4667 BUG_ON(disk_block_cnt > 0xffff);
4668
4669 /* build the new CDB for the physical disk I/O */
4670 if (disk_block > 0xffffffff) {
4671 cdb[0] = is_write ? WRITE_16 : READ_16;
4672 cdb[1] = 0;
4673 cdb[2] = (u8) (disk_block >> 56);
4674 cdb[3] = (u8) (disk_block >> 48);
4675 cdb[4] = (u8) (disk_block >> 40);
4676 cdb[5] = (u8) (disk_block >> 32);
4677 cdb[6] = (u8) (disk_block >> 24);
4678 cdb[7] = (u8) (disk_block >> 16);
4679 cdb[8] = (u8) (disk_block >> 8);
4680 cdb[9] = (u8) (disk_block);
4681 cdb[10] = (u8) (disk_block_cnt >> 24);
4682 cdb[11] = (u8) (disk_block_cnt >> 16);
4683 cdb[12] = (u8) (disk_block_cnt >> 8);
4684 cdb[13] = (u8) (disk_block_cnt);
4685 cdb[14] = 0;
4686 cdb[15] = 0;
4687 cdb_len = 16;
4688 } else {
4689 cdb[0] = is_write ? WRITE_10 : READ_10;
4690 cdb[1] = 0;
4691 cdb[2] = (u8) (disk_block >> 24);
4692 cdb[3] = (u8) (disk_block >> 16);
4693 cdb[4] = (u8) (disk_block >> 8);
4694 cdb[5] = (u8) (disk_block);
4695 cdb[6] = 0;
4696 cdb[7] = (u8) (disk_block_cnt >> 8);
4697 cdb[8] = (u8) (disk_block_cnt);
4698 cdb[9] = 0;
4699 cdb_len = 10;
4700 }
4701 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 4702 dev->scsi3addr,
4703 dev->phys_disk[map_index]);
283b4a9b
SC		 4704}
4705
25163bd5
WS		 4706/*
4707 * Submit commands down the "normal" RAID stack path
4708 * All callers to hpsa_ciss_submit must check lockup_detected
4709 * beforehand, before (opt.) and after calling cmd_alloc
4710 */
574f05d3
SC		 4711static int hpsa_ciss_submit(struct ctlr_info *h,
4712 struct CommandList *c, struct scsi_cmnd *cmd,
4713 unsigned char scsi3addr[])
edd16368 4714{
edd16368 4715 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 4716 c->cmd_type = CMD_SCSI;
4717 c->scsi_cmd = cmd;
4718 c->Header.ReplyQueue = 0; /* unused in simple mode */
4719 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 4720 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 4721
4722 /* Fill in the request block... */
4723
4724 c->Request.Timeout = 0;
edd16368
SC		 4725 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4726 c->Request.CDBLen = cmd->cmd_len;
4727 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 4728 switch (cmd->sc_data_direction) {
4729 case DMA_TO_DEVICE:
a505b86f
SC		 4730 c->Request.type_attr_dir =
4731 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 4732 break;
4733 case DMA_FROM_DEVICE:
a505b86f
SC		 4734 c->Request.type_attr_dir =
4735 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 4736 break;
4737 case DMA_NONE:
a505b86f
SC		 4738 c->Request.type_attr_dir =
4739 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 4740 break;
4741 case DMA_BIDIRECTIONAL:
4742 /* This can happen if a buggy application does a scsi passthru
4743 * and sets both inlen and outlen to non-zero. ( see
4744 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4745 */
4746
a505b86f
SC		 4747 c->Request.type_attr_dir =
4748 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 4749 /* This is technically wrong, and hpsa controllers should
4750 * reject it with CMD_INVALID, which is the most correct
4751 * response, but non-fibre backends appear to let it
4752 * slide by, and give the same results as if this field
4753 * were set correctly. Either way is acceptable for
4754 * our purposes here.
4755 */
4756
4757 break;
4758
4759 default:
4760 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4761 cmd->sc_data_direction);
4762 BUG();
4763 break;
4764 }
4765
33a2ffce 4766 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
73153fe5 4767 hpsa_cmd_resolve_and_free(h, c);
edd16368
SC		 4768 return SCSI_MLQUEUE_HOST_BUSY;
4769 }
4770 enqueue_cmd_and_start_io(h, c);
4771 /* the cmd'll come back via intr handler in complete_scsi_command() */
4772 return 0;
4773}
4774
360c73bd
SC		 4775static void hpsa_cmd_init(struct ctlr_info *h, int index,
4776 struct CommandList *c)
4777{
4778 dma_addr_t cmd_dma_handle, err_dma_handle;
4779
4780 /* Zero out all of commandlist except the last field, refcount */
4781 memset(c, 0, offsetof(struct CommandList, refcount));
4782 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
4783 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4784 c->err_info = h->errinfo_pool + index;
4785 memset(c->err_info, 0, sizeof(*c->err_info));
4786 err_dma_handle = h->errinfo_pool_dhandle
4787 + index * sizeof(*c->err_info);
4788 c->cmdindex = index;
4789 c->busaddr = (u32) cmd_dma_handle;
4790 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4791 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
4792 c->h = h;
a58e7e53 4793 c->scsi_cmd = SCSI_CMD_IDLE;
360c73bd
SC		 4794}
4795
4796static void hpsa_preinitialize_commands(struct ctlr_info *h)
4797{
4798 int i;
4799
4800 for (i = 0; i < h->nr_cmds; i++) {
4801 struct CommandList *c = h->cmd_pool + i;
4802
4803 hpsa_cmd_init(h, i, c);
4804 atomic_set(&c->refcount, 0);
4805 }
4806}
4807
4808static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
4809 struct CommandList *c)
4810{
4811 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4812
73153fe5
WS		 4813 BUG_ON(c->cmdindex != index);
4814
360c73bd
SC		 4815 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4816 memset(c->err_info, 0, sizeof(*c->err_info));
4817 c->busaddr = (u32) cmd_dma_handle;
4818}
4819
592a0ad5
WS		 4820static int hpsa_ioaccel_submit(struct ctlr_info *h,
4821 struct CommandList *c, struct scsi_cmnd *cmd,
4822 unsigned char *scsi3addr)
4823{
4824 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4825 int rc = IO_ACCEL_INELIGIBLE;
4826
4827 cmd->host_scribble = (unsigned char *) c;
4828
4829 if (dev->offload_enabled) {
4830 hpsa_cmd_init(h, c->cmdindex, c);
4831 c->cmd_type = CMD_SCSI;
4832 c->scsi_cmd = cmd;
4833 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4834 if (rc < 0) /* scsi_dma_map failed. */
4835 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 4836 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 4837 hpsa_cmd_init(h, c->cmdindex, c);
4838 c->cmd_type = CMD_SCSI;
4839 c->scsi_cmd = cmd;
4840 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4841 if (rc < 0) /* scsi_dma_map failed. */
4842 rc = SCSI_MLQUEUE_HOST_BUSY;
4843 }
4844 return rc;
4845}
4846
080ef1cc
DB		 4847static void hpsa_command_resubmit_worker(struct work_struct *work)
4848{
4849 struct scsi_cmnd *cmd;
4850 struct hpsa_scsi_dev_t *dev;
8a0ff92c 4851 struct CommandList *c = container_of(work, struct CommandList, work);
080ef1cc
DB		 4852
4853 cmd = c->scsi_cmd;
4854 dev = cmd->device->hostdata;
4855 if (!dev) {
4856 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 4857 return hpsa_cmd_free_and_done(c->h, c, cmd);
080ef1cc 4858 }
d604f533
WS		 4859 if (c->reset_pending)
4860 return hpsa_cmd_resolve_and_free(c->h, c);
a58e7e53
WS		 4861 if (c->abort_pending)
4862 return hpsa_cmd_abort_and_free(c->h, c, cmd);
592a0ad5
WS		 4863 if (c->cmd_type == CMD_IOACCEL2) {
4864 struct ctlr_info *h = c->h;
4865 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
4866 int rc;
4867
4868 if (c2->error_data.serv_response ==
4869 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
4870 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
4871 if (rc == 0)
4872 return;
4873 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4874 /*
4875 * If we get here, it means dma mapping failed.
4876 * Try again via scsi mid layer, which will
4877 * then get SCSI_MLQUEUE_HOST_BUSY.
4878 */
4879 cmd->result = DID_IMM_RETRY << 16;
8a0ff92c 4880 return hpsa_cmd_free_and_done(h, c, cmd);
592a0ad5
WS		 4881 }
4882 /* else, fall thru and resubmit down CISS path */
4883 }
4884 }
360c73bd 4885 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 4886 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4887 /*
4888 * If we get here, it means dma mapping failed. Try
4889 * again via scsi mid layer, which will then get
4890 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 4891 *
4892 * hpsa_ciss_submit will have already freed c
4893 * if it encountered a dma mapping failure.
080ef1cc
DB		 4894 */
4895 cmd->result = DID_IMM_RETRY << 16;
4896 cmd->scsi_done(cmd);
4897 }
4898}
4899
574f05d3
SC		 4900/* Running in struct Scsi_Host->host_lock less mode */
4901static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4902{
4903 struct ctlr_info *h;
4904 struct hpsa_scsi_dev_t *dev;
4905 unsigned char scsi3addr[8];
4906 struct CommandList *c;
4907 int rc = 0;
4908
4909 /* Get the ptr to our adapter structure out of cmd->host. */
4910 h = sdev_to_hba(cmd->device);
73153fe5
WS		 4911
4912 BUG_ON(cmd->request->tag < 0);
4913
574f05d3
SC		 4914 dev = cmd->device->hostdata;
4915 if (!dev) {
4916 cmd->result = DID_NO_CONNECT << 16;
4917 cmd->scsi_done(cmd);
4918 return 0;
4919 }
574f05d3 4920
73153fe5 4921 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
bf43caf3 4922
407863cb 4923 if (unlikely(lockup_detected(h))) {
25163bd5 4924 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 4925 cmd->scsi_done(cmd);
4926 return 0;
4927 }
73153fe5 4928 c = cmd_tagged_alloc(h, cmd);
574f05d3 4929
407863cb
SC		 4930 /*
4931 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 4932 * Retries always go down the normal I/O path.
4933 */
4934 if (likely(cmd->retries == 0 &&
4935 cmd->request->cmd_type == REQ_TYPE_FS &&
4936 h->acciopath_status)) {
592a0ad5
WS		 4937 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
4938 if (rc == 0)
4939 return 0;
4940 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
73153fe5 4941 hpsa_cmd_resolve_and_free(h, c);
592a0ad5 4942 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 4943 }
4944 }
4945 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4946}
4947
8ebc9248 4948static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 4949{
4950 unsigned long flags;
4951
8ebc9248
WS		 4952 spin_lock_irqsave(&h->scan_lock, flags);
4953 h->scan_finished = 1;
4954 wake_up_all(&h->scan_wait_queue);
4955 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 4956}
4957
a08a8471
SC		 4958static void hpsa_scan_start(struct Scsi_Host *sh)
4959{
4960 struct ctlr_info *h = shost_to_hba(sh);
4961 unsigned long flags;
4962
8ebc9248
WS		 4963 /*
4964 * Don't let rescans be initiated on a controller known to be locked
4965 * up. If the controller locks up *during* a rescan, that thread is
4966 * probably hosed, but at least we can prevent new rescan threads from
4967 * piling up on a locked up controller.
4968 */
4969 if (unlikely(lockup_detected(h)))
4970 return hpsa_scan_complete(h);
5f389360 4971
a08a8471
SC		 4972 /* wait until any scan already in progress is finished. */
4973 while (1) {
4974 spin_lock_irqsave(&h->scan_lock, flags);
4975 if (h->scan_finished)
4976 break;
4977 spin_unlock_irqrestore(&h->scan_lock, flags);
4978 wait_event(h->scan_wait_queue, h->scan_finished);
4979 /* Note: We don't need to worry about a race between this
4980 * thread and driver unload because the midlayer will
4981 * have incremented the reference count, so unload won't
4982 * happen if we're in here.
4983 */
4984 }
4985 h->scan_finished = 0; /* mark scan as in progress */
4986 spin_unlock_irqrestore(&h->scan_lock, flags);
4987
8ebc9248
WS		 4988 if (unlikely(lockup_detected(h)))
4989 return hpsa_scan_complete(h);
5f389360 4990
8aa60681 4991 hpsa_update_scsi_devices(h);
a08a8471 4992
8ebc9248 4993 hpsa_scan_complete(h);
a08a8471
SC		 4994}
4995
7c0a0229
DB		 4996static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4997{
03383736
DB		 4998 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
4999
5000 if (!logical_drive)
5001 return -ENODEV;
7c0a0229
DB		 5002
5003 if (qdepth < 1)
5004 qdepth = 1;
03383736
DB		 5005 else if (qdepth > logical_drive->queue_depth)
5006 qdepth = logical_drive->queue_depth;
5007
5008 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 5009}
5010
a08a8471
SC		 5011static int hpsa_scan_finished(struct Scsi_Host *sh,
5012 unsigned long elapsed_time)
5013{
5014 struct ctlr_info *h = shost_to_hba(sh);
5015 unsigned long flags;
5016 int finished;
5017
5018 spin_lock_irqsave(&h->scan_lock, flags);
5019 finished = h->scan_finished;
5020 spin_unlock_irqrestore(&h->scan_lock, flags);
5021 return finished;
5022}
5023
2946e82b 5024static int hpsa_scsi_host_alloc(struct ctlr_info *h)
edd16368 5025{
b705690d
SC		 5026 struct Scsi_Host *sh;
5027 int error;
edd16368 5028
b705690d 5029 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2946e82b
RE		 5030 if (sh == NULL) {
5031 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
5032 return -ENOMEM;
5033 }
b705690d
SC		 5034
5035 sh->io_port = 0;
5036 sh->n_io_port = 0;
5037 sh->this_id = -1;
5038 sh->max_channel = 3;
5039 sh->max_cmd_len = MAX_COMMAND_SIZE;
5040 sh->max_lun = HPSA_MAX_LUN;
5041 sh->max_id = HPSA_MAX_LUN;
41ce4c35 5042 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 5043 sh->cmd_per_lun = sh->can_queue;
b705690d 5044 sh->sg_tablesize = h->maxsgentries;
b705690d
SC		 5045 sh->hostdata[0] = (unsigned long) h;
5046 sh->irq = h->intr[h->intr_mode];
5047 sh->unique_id = sh->irq;
73153fe5
WS		 5048 error = scsi_init_shared_tag_map(sh, sh->can_queue);
5049 if (error) {
5050 dev_err(&h->pdev->dev,
5051 "%s: scsi_init_shared_tag_map failed for controller %d\n",
5052 __func__, h->ctlr);
2946e82b
RE		 5053 scsi_host_put(sh);
5054 return error;
73153fe5 5055 }
2946e82b 5056 h->scsi_host = sh;
b705690d 5057 return 0;
2946e82b 5058}
b705690d 5059
2946e82b
RE		 5060static int hpsa_scsi_add_host(struct ctlr_info *h)
5061{
5062 int rv;
5063
5064 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
5065 if (rv) {
5066 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
5067 return rv;
5068 }
5069 scsi_scan_host(h->scsi_host);
5070 return 0;
edd16368
SC		 5071}
5072
73153fe5
WS		 5073/*
5074 * The block layer has already gone to the trouble of picking out a unique,
5075 * small-integer tag for this request. We use an offset from that value as
5076 * an index to select our command block. (The offset allows us to reserve the
5077 * low-numbered entries for our own uses.)
5078 */
5079static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
5080{
5081 int idx = scmd->request->tag;
5082
5083 if (idx < 0)
5084 return idx;
5085
5086 /* Offset to leave space for internal cmds. */
5087 return idx += HPSA_NRESERVED_CMDS;
5088}
5089
b69324ff
WS		 5090/*
5091 * Send a TEST_UNIT_READY command to the specified LUN using the specified
5092 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5093 */
5094static int hpsa_send_test_unit_ready(struct ctlr_info *h,
5095 struct CommandList *c, unsigned char lunaddr[],
5096 int reply_queue)
5097{
5098 int rc;
5099
5100 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
5101 (void) fill_cmd(c, TEST_UNIT_READY, h,
5102 NULL, 0, 0, lunaddr, TYPE_CMD);
5103 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5104 if (rc)
5105 return rc;
5106 /* no unmap needed here because no data xfer. */
5107
5108 /* Check if the unit is already ready. */
5109 if (c->err_info->CommandStatus == CMD_SUCCESS)
5110 return 0;
5111
5112 /*
5113 * The first command sent after reset will receive "unit attention" to
5114 * indicate that the LUN has been reset...this is actually what we're
5115 * looking for (but, success is good too).
5116 */
5117 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5118 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5119 (c->err_info->SenseInfo[2] == NO_SENSE ||
5120 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5121 return 0;
5122
5123 return 1;
5124}
5125
5126/*
5127 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5128 * returns zero when the unit is ready, and non-zero when giving up.
5129 */
5130static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5131 struct CommandList *c,
5132 unsigned char lunaddr[], int reply_queue)
edd16368 5133{
8919358e 5134 int rc;
edd16368
SC		 5135 int count = 0;
5136 int waittime = 1; /* seconds */
edd16368
SC		 5137
5138 /* Send test unit ready until device ready, or give up. */
b69324ff 5139 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
edd16368 5140
b69324ff
WS		 5141 /*
5142 * Wait for a bit. do this first, because if we send
edd16368
SC		 5143 * the TUR right away, the reset will just abort it.
5144 */
5145 msleep(1000 * waittime);
b69324ff
WS		 5146
5147 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5148 if (!rc)
5149 break;
edd16368
SC		 5150
5151 /* Increase wait time with each try, up to a point. */
5152 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
b69324ff 5153 waittime *= 2;
edd16368 5154
b69324ff
WS		 5155 dev_warn(&h->pdev->dev,
5156 "waiting %d secs for device to become ready.\n",
5157 waittime);
5158 }
edd16368 5159
b69324ff
WS		 5160 return rc;
5161}
edd16368 5162
b69324ff
WS		 5163static int wait_for_device_to_become_ready(struct ctlr_info *h,
5164 unsigned char lunaddr[],
5165 int reply_queue)
5166{
5167 int first_queue;
5168 int last_queue;
5169 int rq;
5170 int rc = 0;
5171 struct CommandList *c;
5172
5173 c = cmd_alloc(h);
5174
5175 /*
5176 * If no specific reply queue was requested, then send the TUR
5177 * repeatedly, requesting a reply on each reply queue; otherwise execute
5178 * the loop exactly once using only the specified queue.
5179 */
5180 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5181 first_queue = 0;
5182 last_queue = h->nreply_queues - 1;
5183 } else {
5184 first_queue = reply_queue;
5185 last_queue = reply_queue;
5186 }
5187
5188 for (rq = first_queue; rq <= last_queue; rq++) {
5189 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5190 if (rc)
edd16368 5191 break;
edd16368
SC		 5192 }
5193
5194 if (rc)
5195 dev_warn(&h->pdev->dev, "giving up on device.\n");
5196 else
5197 dev_warn(&h->pdev->dev, "device is ready.\n");
5198
45fcb86e 5199 cmd_free(h, c);
edd16368
SC		 5200 return rc;
5201}
5202
5203/* Need at least one of these error handlers to keep ../scsi/hosts.c from
5204 * complaining. Doing a host- or bus-reset can't do anything good here.
5205 */
5206static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5207{
5208 int rc;
5209 struct ctlr_info *h;
5210 struct hpsa_scsi_dev_t *dev;
0b9b7b6e 5211 u8 reset_type;
2dc127bb 5212 char msg[48];
edd16368
SC		 5213
5214 /* find the controller to which the command to be aborted was sent */
5215 h = sdev_to_hba(scsicmd->device);
5216 if (h == NULL) /* paranoia */
5217 return FAILED;
e345893b
DB		 5218
5219 if (lockup_detected(h))
5220 return FAILED;
5221
edd16368
SC		 5222 dev = scsicmd->device->hostdata;
5223 if (!dev) {
d604f533 5224 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
edd16368
SC		 5225 return FAILED;
5226 }
25163bd5
WS		 5227
5228 /* if controller locked up, we can guarantee command won't complete */
5229 if (lockup_detected(h)) {
2dc127bb
DC		 5230 snprintf(msg, sizeof(msg),
5231 "cmd %d RESET FAILED, lockup detected",
5232 hpsa_get_cmd_index(scsicmd));
73153fe5 5233 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5234 return FAILED;
5235 }
5236
5237 /* this reset request might be the result of a lockup; check */
5238 if (detect_controller_lockup(h)) {
2dc127bb
DC		 5239 snprintf(msg, sizeof(msg),
5240 "cmd %d RESET FAILED, new lockup detected",
5241 hpsa_get_cmd_index(scsicmd));
73153fe5 5242 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5243 return FAILED;
5244 }
5245
d604f533
WS		 5246 /* Do not attempt on controller */
5247 if (is_hba_lunid(dev->scsi3addr))
5248 return SUCCESS;
5249
0b9b7b6e
ST		 5250 if (is_logical_dev_addr_mode(dev->scsi3addr))
5251 reset_type = HPSA_DEVICE_RESET_MSG;
5252 else
5253 reset_type = HPSA_PHYS_TARGET_RESET;
5254
5255 sprintf(msg, "resetting %s",
5256 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ");
5257 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5 5258
da03ded0
DB		 5259 h->reset_in_progress = 1;
5260
edd16368 5261 /* send a reset to the SCSI LUN which the command was sent to */
0b9b7b6e 5262 rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type,
d604f533 5263 DEFAULT_REPLY_QUEUE);
0b9b7b6e
ST		 5264 sprintf(msg, "reset %s %s",
5265 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ",
5266 rc == 0 ? "completed successfully" : "failed");
d604f533 5267 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
da03ded0 5268 h->reset_in_progress = 0;
d604f533 5269 return rc == 0 ? SUCCESS : FAILED;
edd16368
SC		 5270}
5271
6cba3f19
SC		 5272static void swizzle_abort_tag(u8 *tag)
5273{
5274 u8 original_tag[8];
5275
5276 memcpy(original_tag, tag, 8);
5277 tag[0] = original_tag[3];
5278 tag[1] = original_tag[2];
5279 tag[2] = original_tag[1];
5280 tag[3] = original_tag[0];
5281 tag[4] = original_tag[7];
5282 tag[5] = original_tag[6];
5283 tag[6] = original_tag[5];
5284 tag[7] = original_tag[4];
5285}
5286
17eb87d2 5287static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 5288 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 5289{
2b08b3e9 5290 u64 tag;
17eb87d2
ST		 5291 if (c->cmd_type == CMD_IOACCEL1) {
5292 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5293 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 5294 tag = le64_to_cpu(cm1->tag);
5295 *tagupper = cpu_to_le32(tag >> 32);
5296 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 5297 return;
5298 }
5299 if (c->cmd_type == CMD_IOACCEL2) {
5300 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5301 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 5302 /* upper tag not used in ioaccel2 mode */
5303 memset(tagupper, 0, sizeof(*tagupper));
5304 *taglower = cm2->Tag;
54b6e9e9 5305 return;
17eb87d2 5306 }
2b08b3e9
DB		 5307 tag = le64_to_cpu(c->Header.tag);
5308 *tagupper = cpu_to_le32(tag >> 32);
5309 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 5310}
5311
75167d2c 5312static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 5313 struct CommandList *abort, int reply_queue)
75167d2c
SC		 5314{
5315 int rc = IO_OK;
5316 struct CommandList *c;
5317 struct ErrorInfo *ei;
2b08b3e9 5318 __le32 tagupper, taglower;
75167d2c 5319
45fcb86e 5320 c = cmd_alloc(h);
75167d2c 5321
a2dac136 5322 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 5323 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 5324 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 5325 if (h->needs_abort_tags_swizzled)
6cba3f19 5326 swizzle_abort_tag(&c->Request.CDB[4]);
25163bd5 5327 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
17eb87d2 5328 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5329 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 5330 __func__, tagupper, taglower);
75167d2c
SC		 5331 /* no unmap needed here because no data xfer. */
5332
5333 ei = c->err_info;
5334 switch (ei->CommandStatus) {
5335 case CMD_SUCCESS:
5336 break;
9437ac43
SC		 5337 case CMD_TMF_STATUS:
5338 rc = hpsa_evaluate_tmf_status(h, c);
5339 break;
75167d2c
SC		 5340 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5341 rc = -1;
5342 break;
5343 default:
5344 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 5345 __func__, tagupper, taglower);
d1e8beac 5346 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 5347 rc = -1;
5348 break;
5349 }
45fcb86e 5350 cmd_free(h, c);
dd0e19f3
ST		 5351 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5352 __func__, tagupper, taglower);
75167d2c
SC		 5353 return rc;
5354}
5355
8be986cc
SC		 5356static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5357 struct CommandList *command_to_abort, int reply_queue)
5358{
5359 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5360 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5361 struct io_accel2_cmd *c2a =
5362 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
a58e7e53 5363 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
8be986cc
SC		 5364 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5365
5366 /*
5367 * We're overlaying struct hpsa_tmf_struct on top of something which
5368 * was allocated as a struct io_accel2_cmd, so we better be sure it
5369 * actually fits, and doesn't overrun the error info space.
5370 */
5371 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5372 sizeof(struct io_accel2_cmd));
5373 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5374 offsetof(struct hpsa_tmf_struct, error_len) +
5375 sizeof(ac->error_len));
5376
5377 c->cmd_type = IOACCEL2_TMF;
a58e7e53
WS		 5378 c->scsi_cmd = SCSI_CMD_BUSY;
5379
8be986cc
SC		 5380 /* Adjust the DMA address to point to the accelerated command buffer */
5381 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5382 (c->cmdindex * sizeof(struct io_accel2_cmd));
5383 BUG_ON(c->busaddr & 0x0000007F);
5384
5385 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5386 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5387 ac->reply_queue = reply_queue;
5388 ac->tmf = IOACCEL2_TMF_ABORT;
5389 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5390 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5391 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5392 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5393 ac->error_ptr = cpu_to_le64(c->busaddr +
5394 offsetof(struct io_accel2_cmd, error_data));
5395 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5396}
5397
54b6e9e9
ST		 5398/* ioaccel2 path firmware cannot handle abort task requests.
5399 * Change abort requests to physical target reset, and send to the
5400 * address of the physical disk used for the ioaccel 2 command.
5401 * Return 0 on success (IO_OK)
5402 * -1 on failure
5403 */
5404
5405static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 5406 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 5407{
5408 int rc = IO_OK;
5409 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5410 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5411 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5412 unsigned char *psa = &phys_scsi3addr[0];
5413
5414 /* Get a pointer to the hpsa logical device. */
7fa3030c 5415 scmd = abort->scsi_cmd;
54b6e9e9
ST		 5416 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5417 if (dev == NULL) {
5418 dev_warn(&h->pdev->dev,
5419 "Cannot abort: no device pointer for command.\n");
5420 return -1; /* not abortable */
5421 }
5422
2ba8bfc8
SC		 5423 if (h->raid_offload_debug > 0)
5424 dev_info(&h->pdev->dev,
0d96ef5f 5425 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 5426 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 5427 "Reset as abort",
2ba8bfc8
SC		 5428 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5429 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5430
54b6e9e9
ST		 5431 if (!dev->offload_enabled) {
5432 dev_warn(&h->pdev->dev,
5433 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5434 return -1; /* not abortable */
5435 }
5436
5437 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5438 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5439 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5440 return -1; /* not abortable */
5441 }
5442
5443 /* send the reset */
2ba8bfc8
SC		 5444 if (h->raid_offload_debug > 0)
5445 dev_info(&h->pdev->dev,
5446 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5447 psa[0], psa[1], psa[2], psa[3],
5448 psa[4], psa[5], psa[6], psa[7]);
d604f533 5449 rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 5450 if (rc != 0) {
5451 dev_warn(&h->pdev->dev,
5452 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5453 psa[0], psa[1], psa[2], psa[3],
5454 psa[4], psa[5], psa[6], psa[7]);
5455 return rc; /* failed to reset */
5456 }
5457
5458 /* wait for device to recover */
b69324ff 5459 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
54b6e9e9
ST		 5460 dev_warn(&h->pdev->dev,
5461 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5462 psa[0], psa[1], psa[2], psa[3],
5463 psa[4], psa[5], psa[6], psa[7]);
5464 return -1; /* failed to recover */
5465 }
5466
5467 /* device recovered */
5468 dev_info(&h->pdev->dev,
5469 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5470 psa[0], psa[1], psa[2], psa[3],
5471 psa[4], psa[5], psa[6], psa[7]);
5472
5473 return rc; /* success */
5474}
5475
8be986cc
SC		 5476static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
5477 struct CommandList *abort, int reply_queue)
5478{
5479 int rc = IO_OK;
5480 struct CommandList *c;
5481 __le32 taglower, tagupper;
5482 struct hpsa_scsi_dev_t *dev;
5483 struct io_accel2_cmd *c2;
5484
5485 dev = abort->scsi_cmd->device->hostdata;
5486 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
5487 return -1;
5488
5489 c = cmd_alloc(h);
5490 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
5491 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5492 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5493 hpsa_get_tag(h, abort, &taglower, &tagupper);
5494 dev_dbg(&h->pdev->dev,
5495 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
5496 __func__, tagupper, taglower);
5497 /* no unmap needed here because no data xfer. */
5498
5499 dev_dbg(&h->pdev->dev,
5500 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
5501 __func__, tagupper, taglower, c2->error_data.serv_response);
5502 switch (c2->error_data.serv_response) {
5503 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
5504 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
5505 rc = 0;
5506 break;
5507 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
5508 case IOACCEL2_SERV_RESPONSE_FAILURE:
5509 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
5510 rc = -1;
5511 break;
5512 default:
5513 dev_warn(&h->pdev->dev,
5514 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
5515 __func__, tagupper, taglower,
5516 c2->error_data.serv_response);
5517 rc = -1;
5518 }
5519 cmd_free(h, c);
5520 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
5521 tagupper, taglower);
5522 return rc;
5523}
5524
6cba3f19 5525static int hpsa_send_abort_both_ways(struct ctlr_info *h,
25163bd5 5526 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
6cba3f19 5527{
8be986cc
SC		 5528 /*
5529 * ioccelerator mode 2 commands should be aborted via the
54b6e9e9 5530 * accelerated path, since RAID path is unaware of these commands,
8be986cc
SC		 5531 * but not all underlying firmware can handle abort TMF.
5532 * Change abort to physical device reset when abort TMF is unsupported.
54b6e9e9 5533 */
8be986cc
SC		 5534 if (abort->cmd_type == CMD_IOACCEL2) {
5535 if (HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)
5536 return hpsa_send_abort_ioaccel2(h, abort,
5537 reply_queue);
5538 else
5539 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
25163bd5 5540 abort, reply_queue);
8be986cc 5541 }
9b5c48c2 5542 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
25163bd5 5543}
54b6e9e9 5544
25163bd5
WS		 5545/* Find out which reply queue a command was meant to return on */
5546static int hpsa_extract_reply_queue(struct ctlr_info *h,
5547 struct CommandList *c)
5548{
5549 if (c->cmd_type == CMD_IOACCEL2)
5550 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5551 return c->Header.ReplyQueue;
6cba3f19
SC		 5552}
5553
9b5c48c2
SC		 5554/*
5555 * Limit concurrency of abort commands to prevent
5556 * over-subscription of commands
5557 */
5558static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5559{
5560#define ABORT_CMD_WAIT_MSECS 5000
5561 return !wait_event_timeout(h->abort_cmd_wait_queue,
5562 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5563 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5564}
5565
75167d2c
SC		 5566/* Send an abort for the specified command.
5567 * If the device and controller support it,
5568 * send a task abort request.
5569 */
5570static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5571{
5572
a58e7e53 5573 int rc;
75167d2c
SC		 5574 struct ctlr_info *h;
5575 struct hpsa_scsi_dev_t *dev;
5576 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 5577 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
5578 char msg[256]; /* For debug messaging. */
5579 int ml = 0;
2b08b3e9 5580 __le32 tagupper, taglower;
25163bd5
WS		 5581 int refcount, reply_queue;
5582
5583 if (sc == NULL)
5584 return FAILED;
75167d2c 5585
9b5c48c2
SC		 5586 if (sc->device == NULL)
5587 return FAILED;
5588
75167d2c
SC		 5589 /* Find the controller of the command to be aborted */
5590 h = sdev_to_hba(sc->device);
9b5c48c2 5591 if (h == NULL)
75167d2c
SC		 5592 return FAILED;
5593
25163bd5
WS		 5594 /* Find the device of the command to be aborted */
5595 dev = sc->device->hostdata;
5596 if (!dev) {
5597 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
5598 msg);
e345893b 5599 return FAILED;
25163bd5
WS		 5600 }
5601
5602 /* If controller locked up, we can guarantee command won't complete */
5603 if (lockup_detected(h)) {
5604 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5605 "ABORT FAILED, lockup detected");
5606 return FAILED;
5607 }
5608
5609 /* This is a good time to check if controller lockup has occurred */
5610 if (detect_controller_lockup(h)) {
5611 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5612 "ABORT FAILED, new lockup detected");
5613 return FAILED;
5614 }
e345893b 5615
75167d2c
SC		 5616 /* Check that controller supports some kind of task abort */
5617 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5618 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5619 return FAILED;
5620
5621 memset(msg, 0, sizeof(msg));
4b761557 5622 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
75167d2c 5623 h->scsi_host->host_no, sc->device->channel,
0d96ef5f 5624 sc->device->id, sc->device->lun,
4b761557 5625 "Aborting command", sc);
75167d2c 5626
75167d2c
SC		 5627 /* Get SCSI command to be aborted */
5628 abort = (struct CommandList *) sc->host_scribble;
5629 if (abort == NULL) {
281a7fd0
WS		 5630 /* This can happen if the command already completed. */
5631 return SUCCESS;
5632 }
5633 refcount = atomic_inc_return(&abort->refcount);
5634 if (refcount == 1) { /* Command is done already. */
5635 cmd_free(h, abort);
5636 return SUCCESS;
75167d2c 5637 }
9b5c48c2
SC		 5638
5639 /* Don't bother trying the abort if we know it won't work. */
5640 if (abort->cmd_type != CMD_IOACCEL2 &&
5641 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5642 cmd_free(h, abort);
5643 return FAILED;
5644 }
5645
a58e7e53
WS		 5646 /*
5647 * Check that we're aborting the right command.
5648 * It's possible the CommandList already completed and got re-used.
5649 */
5650 if (abort->scsi_cmd != sc) {
5651 cmd_free(h, abort);
5652 return SUCCESS;
5653 }
5654
5655 abort->abort_pending = true;
17eb87d2 5656 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5657 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 5658 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 5659 as = abort->scsi_cmd;
75167d2c 5660 if (as != NULL)
4b761557
RE		 5661 ml += sprintf(msg+ml,
5662 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
5663 as->cmd_len, as->cmnd[0], as->cmnd[1],
5664 as->serial_number);
5665 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
0d96ef5f 5666 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
4b761557 5667
75167d2c
SC		 5668 /*
5669 * Command is in flight, or possibly already completed
5670 * by the firmware (but not to the scsi mid layer) but we can't
5671 * distinguish which. Send the abort down.
5672 */
9b5c48c2
SC		 5673 if (wait_for_available_abort_cmd(h)) {
5674 dev_warn(&h->pdev->dev,
4b761557
RE		 5675 "%s FAILED, timeout waiting for an abort command to become available.\n",
5676 msg);
9b5c48c2
SC		 5677 cmd_free(h, abort);
5678 return FAILED;
5679 }
25163bd5 5680 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
9b5c48c2
SC		 5681 atomic_inc(&h->abort_cmds_available);
5682 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 5683 if (rc != 0) {
4b761557 5684 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
0d96ef5f 5685 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4b761557 5686 "FAILED to abort command");
281a7fd0 5687 cmd_free(h, abort);
75167d2c
SC		 5688 return FAILED;
5689 }
4b761557 5690 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
d604f533 5691 wait_event(h->event_sync_wait_queue,
a58e7e53 5692 abort->scsi_cmd != sc || lockup_detected(h));
281a7fd0 5693 cmd_free(h, abort);
a58e7e53 5694 return !lockup_detected(h) ? SUCCESS : FAILED;
75167d2c
SC		 5695}
5696
73153fe5
WS		 5697/*
5698 * For operations with an associated SCSI command, a command block is allocated
5699 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
5700 * block request tag as an index into a table of entries. cmd_tagged_free() is
5701 * the complement, although cmd_free() may be called instead.
5702 */
5703static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
5704 struct scsi_cmnd *scmd)
5705{
5706 int idx = hpsa_get_cmd_index(scmd);
5707 struct CommandList *c = h->cmd_pool + idx;
5708
5709 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
5710 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
5711 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
5712 /* The index value comes from the block layer, so if it's out of
5713 * bounds, it's probably not our bug.
5714 */
5715 BUG();
5716 }
5717
5718 atomic_inc(&c->refcount);
5719 if (unlikely(!hpsa_is_cmd_idle(c))) {
5720 /*
5721 * We expect that the SCSI layer will hand us a unique tag
5722 * value. Thus, there should never be a collision here between
5723 * two requests...because if the selected command isn't idle
5724 * then someone is going to be very disappointed.
5725 */
5726 dev_err(&h->pdev->dev,
5727 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
5728 idx);
5729 if (c->scsi_cmd != NULL)
5730 scsi_print_command(c->scsi_cmd);
5731 scsi_print_command(scmd);
5732 }
5733
5734 hpsa_cmd_partial_init(h, idx, c);
5735 return c;
5736}
5737
5738static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
5739{
5740 /*
5741 * Release our reference to the block. We don't need to do anything
5742 * else to free it, because it is accessed by index. (There's no point
5743 * in checking the result of the decrement, since we cannot guarantee
5744 * that there isn't a concurrent abort which is also accessing it.)
5745 */
5746 (void)atomic_dec(&c->refcount);
5747}
5748
edd16368
SC		 5749/*
5750 * For operations that cannot sleep, a command block is allocated at init,
5751 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
5752 * which ones are free or in use. Lock must be held when calling this.
5753 * cmd_free() is the complement.
bf43caf3
RE		 5754 * This function never gives up and returns NULL. If it hangs,
5755 * another thread must call cmd_free() to free some tags.
edd16368 5756 */
281a7fd0 5757
edd16368
SC		 5758static struct CommandList *cmd_alloc(struct ctlr_info *h)
5759{
5760 struct CommandList *c;
360c73bd 5761 int refcount, i;
73153fe5 5762 int offset = 0;
4c413128 5763
33811026
RE		 5764 /*
5765 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 5766 * multiple threads could get in here, and one thread could
5767 * be scanning through the list of bits looking for a free
5768 * one, but the free ones are always behind him, and other
5769 * threads sneak in behind him and eat them before he can
5770 * get to them, so that while there is always a free one, a
5771 * very unlucky thread might be starved anyway, never able to
5772 * beat the other threads. In reality, this happens so
5773 * infrequently as to be indistinguishable from never.
73153fe5
WS		 5774 *
5775 * Note that we start allocating commands before the SCSI host structure
5776 * is initialized. Since the search starts at bit zero, this
5777 * all works, since we have at least one command structure available;
5778 * however, it means that the structures with the low indexes have to be
5779 * reserved for driver-initiated requests, while requests from the block
5780 * layer will use the higher indexes.
4c413128 5781 */
edd16368 5782
281a7fd0 5783 for (;;) {
73153fe5
WS		 5784 i = find_next_zero_bit(h->cmd_pool_bits,
5785 HPSA_NRESERVED_CMDS,
5786 offset);
5787 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
281a7fd0
WS		 5788 offset = 0;
5789 continue;
5790 }
5791 c = h->cmd_pool + i;
5792 refcount = atomic_inc_return(&c->refcount);
5793 if (unlikely(refcount > 1)) {
5794 cmd_free(h, c); /* already in use */
73153fe5 5795 offset = (i + 1) % HPSA_NRESERVED_CMDS;
281a7fd0
WS		 5796 continue;
5797 }
5798 set_bit(i & (BITS_PER_LONG - 1),
5799 h->cmd_pool_bits + (i / BITS_PER_LONG));
5800 break; /* it's ours now. */
5801 }
360c73bd 5802 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 5803 return c;
5804}
5805
73153fe5
WS		 5806/*
5807 * This is the complementary operation to cmd_alloc(). Note, however, in some
5808 * corner cases it may also be used to free blocks allocated by
5809 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
5810 * the clear-bit is harmless.
5811 */
edd16368
SC		 5812static void cmd_free(struct ctlr_info *h, struct CommandList *c)
5813{
281a7fd0
WS		 5814 if (atomic_dec_and_test(&c->refcount)) {
5815 int i;
edd16368 5816
281a7fd0
WS		 5817 i = c - h->cmd_pool;
5818 clear_bit(i & (BITS_PER_LONG - 1),
5819 h->cmd_pool_bits + (i / BITS_PER_LONG));
5820 }
edd16368
SC		 5821}
5822
edd16368
SC		 5823#ifdef CONFIG_COMPAT
5824
42a91641
DB		 5825static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
5826 void __user *arg)
edd16368
SC		 5827{
5828 IOCTL32_Command_struct __user *arg32 =
5829 (IOCTL32_Command_struct __user *) arg;
5830 IOCTL_Command_struct arg64;
5831 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5832 int err;
5833 u32 cp;
5834
938abd84 5835 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5836 err = 0;
5837 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5838 sizeof(arg64.LUN_info));
5839 err |= copy_from_user(&arg64.Request, &arg32->Request,
5840 sizeof(arg64.Request));
5841 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5842 sizeof(arg64.error_info));
5843 err |= get_user(arg64.buf_size, &arg32->buf_size);
5844 err |= get_user(cp, &arg32->buf);
5845 arg64.buf = compat_ptr(cp);
5846 err |= copy_to_user(p, &arg64, sizeof(arg64));
5847
5848 if (err)
5849 return -EFAULT;
5850
42a91641 5851 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 5852 if (err)
5853 return err;
5854 err |= copy_in_user(&arg32->error_info, &p->error_info,
5855 sizeof(arg32->error_info));
5856 if (err)
5857 return -EFAULT;
5858 return err;
5859}
5860
5861static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 5862 int cmd, void __user *arg)
edd16368
SC		 5863{
5864 BIG_IOCTL32_Command_struct __user *arg32 =
5865 (BIG_IOCTL32_Command_struct __user *) arg;
5866 BIG_IOCTL_Command_struct arg64;
5867 BIG_IOCTL_Command_struct __user *p =
5868 compat_alloc_user_space(sizeof(arg64));
5869 int err;
5870 u32 cp;
5871
938abd84 5872 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5873 err = 0;
5874 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5875 sizeof(arg64.LUN_info));
5876 err |= copy_from_user(&arg64.Request, &arg32->Request,
5877 sizeof(arg64.Request));
5878 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5879 sizeof(arg64.error_info));
5880 err |= get_user(arg64.buf_size, &arg32->buf_size);
5881 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5882 err |= get_user(cp, &arg32->buf);
5883 arg64.buf = compat_ptr(cp);
5884 err |= copy_to_user(p, &arg64, sizeof(arg64));
5885
5886 if (err)
5887 return -EFAULT;
5888
42a91641 5889 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 5890 if (err)
5891 return err;
5892 err |= copy_in_user(&arg32->error_info, &p->error_info,
5893 sizeof(arg32->error_info));
5894 if (err)
5895 return -EFAULT;
5896 return err;
5897}
71fe75a7 5898
42a91641 5899static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 5900{
5901 switch (cmd) {
5902 case CCISS_GETPCIINFO:
5903 case CCISS_GETINTINFO:
5904 case CCISS_SETINTINFO:
5905 case CCISS_GETNODENAME:
5906 case CCISS_SETNODENAME:
5907 case CCISS_GETHEARTBEAT:
5908 case CCISS_GETBUSTYPES:
5909 case CCISS_GETFIRMVER:
5910 case CCISS_GETDRIVVER:
5911 case CCISS_REVALIDVOLS:
5912 case CCISS_DEREGDISK:
5913 case CCISS_REGNEWDISK:
5914 case CCISS_REGNEWD:
5915 case CCISS_RESCANDISK:
5916 case CCISS_GETLUNINFO:
5917 return hpsa_ioctl(dev, cmd, arg);
5918
5919 case CCISS_PASSTHRU32:
5920 return hpsa_ioctl32_passthru(dev, cmd, arg);
5921 case CCISS_BIG_PASSTHRU32:
5922 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5923
5924 default:
5925 return -ENOIOCTLCMD;
5926 }
5927}
edd16368
SC		 5928#endif
5929
5930static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5931{
5932 struct hpsa_pci_info pciinfo;
5933
5934 if (!argp)
5935 return -EINVAL;
5936 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5937 pciinfo.bus = h->pdev->bus->number;
5938 pciinfo.dev_fn = h->pdev->devfn;
5939 pciinfo.board_id = h->board_id;
5940 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5941 return -EFAULT;
5942 return 0;
5943}
5944
5945static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
5946{
5947 DriverVer_type DriverVer;
5948 unsigned char vmaj, vmin, vsubmin;
5949 int rc;
5950
5951 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
5952 &vmaj, &vmin, &vsubmin);
5953 if (rc != 3) {
5954 dev_info(&h->pdev->dev, "driver version string '%s' "
5955 "unrecognized.", HPSA_DRIVER_VERSION);
5956 vmaj = 0;
5957 vmin = 0;
5958 vsubmin = 0;
5959 }
5960 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
5961 if (!argp)
5962 return -EINVAL;
5963 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
5964 return -EFAULT;
5965 return 0;
5966}
5967
5968static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5969{
5970 IOCTL_Command_struct iocommand;
5971 struct CommandList *c;
5972 char *buff = NULL;
50a0decf 5973 u64 temp64;
c1f63c8f 5974 int rc = 0;
edd16368
SC		 5975
5976 if (!argp)
5977 return -EINVAL;
5978 if (!capable(CAP_SYS_RAWIO))
5979 return -EPERM;
5980 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
5981 return -EFAULT;
5982 if ((iocommand.buf_size < 1) &&
5983 (iocommand.Request.Type.Direction != XFER_NONE)) {
5984 return -EINVAL;
5985 }
5986 if (iocommand.buf_size > 0) {
5987 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
5988 if (buff == NULL)
2dd02d74 5989 return -ENOMEM;
9233fb10 5990 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 5991 /* Copy the data into the buffer we created */
5992 if (copy_from_user(buff, iocommand.buf,
5993 iocommand.buf_size)) {
c1f63c8f
SC		 5994 rc = -EFAULT;
5995 goto out_kfree;
b03a7771
SC		 5996 }
5997 } else {
5998 memset(buff, 0, iocommand.buf_size);
edd16368 5999 }
b03a7771 6000 }
45fcb86e 6001 c = cmd_alloc(h);
bf43caf3 6002
edd16368
SC		 6003 /* Fill in the command type */
6004 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6005 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6006 /* Fill in Command Header */
6007 c->Header.ReplyQueue = 0; /* unused in simple mode */
6008 if (iocommand.buf_size > 0) { /* buffer to fill */
6009 c->Header.SGList = 1;
50a0decf 6010 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6011 } else { /* no buffers to fill */
6012 c->Header.SGList = 0;
50a0decf 6013 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 6014 }
6015 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6016
6017 /* Fill in Request block */
6018 memcpy(&c->Request, &iocommand.Request,
6019 sizeof(c->Request));
6020
6021 /* Fill in the scatter gather information */
6022 if (iocommand.buf_size > 0) {
50a0decf 6023 temp64 = pci_map_single(h->pdev, buff,
edd16368 6024 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6025 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
6026 c->SG[0].Addr = cpu_to_le64(0);
6027 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 6028 rc = -ENOMEM;
6029 goto out;
6030 }
50a0decf
SC		 6031 c->SG[0].Addr = cpu_to_le64(temp64);
6032 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
6033 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 6034 }
25163bd5 6035 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
c2dd32e0
SC		 6036 if (iocommand.buf_size > 0)
6037 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 6038 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6039 if (rc) {
6040 rc = -EIO;
6041 goto out;
6042 }
edd16368
SC		 6043
6044 /* Copy the error information out */
6045 memcpy(&iocommand.error_info, c->err_info,
6046 sizeof(iocommand.error_info));
6047 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 6048 rc = -EFAULT;
6049 goto out;
edd16368 6050 }
9233fb10 6051 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 6052 iocommand.buf_size > 0) {
edd16368
SC		 6053 /* Copy the data out of the buffer we created */
6054 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 6055 rc = -EFAULT;
6056 goto out;
edd16368
SC		 6057 }
6058 }
c1f63c8f 6059out:
45fcb86e 6060 cmd_free(h, c);
c1f63c8f
SC		 6061out_kfree:
6062 kfree(buff);
6063 return rc;
edd16368
SC		 6064}
6065
6066static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6067{
6068 BIG_IOCTL_Command_struct *ioc;
6069 struct CommandList *c;
6070 unsigned char **buff = NULL;
6071 int *buff_size = NULL;
50a0decf 6072 u64 temp64;
edd16368
SC		 6073 BYTE sg_used = 0;
6074 int status = 0;
01a02ffc
SC		 6075 u32 left;
6076 u32 sz;
edd16368
SC		 6077 BYTE __user *data_ptr;
6078
6079 if (!argp)
6080 return -EINVAL;
6081 if (!capable(CAP_SYS_RAWIO))
6082 return -EPERM;
6083 ioc = (BIG_IOCTL_Command_struct *)
6084 kmalloc(sizeof(*ioc), GFP_KERNEL);
6085 if (!ioc) {
6086 status = -ENOMEM;
6087 goto cleanup1;
6088 }
6089 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
6090 status = -EFAULT;
6091 goto cleanup1;
6092 }
6093 if ((ioc->buf_size < 1) &&
6094 (ioc->Request.Type.Direction != XFER_NONE)) {
6095 status = -EINVAL;
6096 goto cleanup1;
6097 }
6098 /* Check kmalloc limits using all SGs */
6099 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
6100 status = -EINVAL;
6101 goto cleanup1;
6102 }
d66ae08b 6103 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 6104 status = -EINVAL;
6105 goto cleanup1;
6106 }
d66ae08b 6107 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 6108 if (!buff) {
6109 status = -ENOMEM;
6110 goto cleanup1;
6111 }
d66ae08b 6112 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 6113 if (!buff_size) {
6114 status = -ENOMEM;
6115 goto cleanup1;
6116 }
6117 left = ioc->buf_size;
6118 data_ptr = ioc->buf;
6119 while (left) {
6120 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6121 buff_size[sg_used] = sz;
6122 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6123 if (buff[sg_used] == NULL) {
6124 status = -ENOMEM;
6125 goto cleanup1;
6126 }
9233fb10 6127 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 6128 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 6129 status = -EFAULT;
edd16368
SC		 6130 goto cleanup1;
6131 }
6132 } else
6133 memset(buff[sg_used], 0, sz);
6134 left -= sz;
6135 data_ptr += sz;
6136 sg_used++;
6137 }
45fcb86e 6138 c = cmd_alloc(h);
bf43caf3 6139
edd16368 6140 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6141 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368 6142 c->Header.ReplyQueue = 0;
50a0decf
SC		 6143 c->Header.SGList = (u8) sg_used;
6144 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 6145 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6146 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6147 if (ioc->buf_size > 0) {
6148 int i;
6149 for (i = 0; i < sg_used; i++) {
50a0decf 6150 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 6151 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6152 if (dma_mapping_error(&h->pdev->dev,
6153 (dma_addr_t) temp64)) {
6154 c->SG[i].Addr = cpu_to_le64(0);
6155 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 6156 hpsa_pci_unmap(h->pdev, c, i,
6157 PCI_DMA_BIDIRECTIONAL);
6158 status = -ENOMEM;
e2d4a1f6 6159 goto cleanup0;
bcc48ffa 6160 }
50a0decf
SC		 6161 c->SG[i].Addr = cpu_to_le64(temp64);
6162 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6163 c->SG[i].Ext = cpu_to_le32(0);
edd16368 6164 }
50a0decf 6165 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 6166 }
25163bd5 6167 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
b03a7771
SC		 6168 if (sg_used)
6169 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 6170 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6171 if (status) {
6172 status = -EIO;
6173 goto cleanup0;
6174 }
6175
edd16368
SC		 6176 /* Copy the error information out */
6177 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6178 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 6179 status = -EFAULT;
e2d4a1f6 6180 goto cleanup0;
edd16368 6181 }
9233fb10 6182 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 6183 int i;
6184
edd16368
SC		 6185 /* Copy the data out of the buffer we created */
6186 BYTE __user *ptr = ioc->buf;
6187 for (i = 0; i < sg_used; i++) {
6188 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 6189 status = -EFAULT;
e2d4a1f6 6190 goto cleanup0;
edd16368
SC		 6191 }
6192 ptr += buff_size[i];
6193 }
6194 }
edd16368 6195 status = 0;
e2d4a1f6 6196cleanup0:
45fcb86e 6197 cmd_free(h, c);
edd16368
SC		 6198cleanup1:
6199 if (buff) {
2b08b3e9
DB		 6200 int i;
6201
edd16368
SC		 6202 for (i = 0; i < sg_used; i++)
6203 kfree(buff[i]);
6204 kfree(buff);
6205 }
6206 kfree(buff_size);
6207 kfree(ioc);
6208 return status;
6209}
6210
6211static void check_ioctl_unit_attention(struct ctlr_info *h,
6212 struct CommandList *c)
6213{
6214 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6215 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6216 (void) check_for_unit_attention(h, c);
6217}
0390f0c0 6218
edd16368
SC		 6219/*
6220 * ioctl
6221 */
42a91641 6222static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 6223{
6224 struct ctlr_info *h;
6225 void __user *argp = (void __user *)arg;
0390f0c0 6226 int rc;
edd16368
SC		 6227
6228 h = sdev_to_hba(dev);
6229
6230 switch (cmd) {
6231 case CCISS_DEREGDISK:
6232 case CCISS_REGNEWDISK:
6233 case CCISS_REGNEWD:
a08a8471 6234 hpsa_scan_start(h->scsi_host);
edd16368
SC		 6235 return 0;
6236 case CCISS_GETPCIINFO:
6237 return hpsa_getpciinfo_ioctl(h, argp);
6238 case CCISS_GETDRIVVER:
6239 return hpsa_getdrivver_ioctl(h, argp);
6240 case CCISS_PASSTHRU:
34f0c627 6241 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6242 return -EAGAIN;
6243 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 6244 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6245 return rc;
edd16368 6246 case CCISS_BIG_PASSTHRU:
34f0c627 6247 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6248 return -EAGAIN;
6249 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 6250 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6251 return rc;
edd16368
SC		 6252 default:
6253 return -ENOTTY;
6254 }
6255}
6256
bf43caf3 6257static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6f039790 6258 u8 reset_type)
64670ac8
SC		 6259{
6260 struct CommandList *c;
6261
6262 c = cmd_alloc(h);
bf43caf3 6263
a2dac136
SC		 6264 /* fill_cmd can't fail here, no data buffer to map */
6265 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 6266 RAID_CTLR_LUNID, TYPE_MSG);
6267 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6268 c->waiting = NULL;
6269 enqueue_cmd_and_start_io(h, c);
6270 /* Don't wait for completion, the reset won't complete. Don't free
6271 * the command either. This is the last command we will send before
6272 * re-initializing everything, so it doesn't matter and won't leak.
6273 */
bf43caf3 6274 return;
64670ac8
SC		 6275}
6276
a2dac136 6277static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 6278 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 6279 int cmd_type)
6280{
6281 int pci_dir = XFER_NONE;
9b5c48c2 6282 u64 tag; /* for commands to be aborted */
edd16368
SC		 6283
6284 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6285 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6286 c->Header.ReplyQueue = 0;
6287 if (buff != NULL && size > 0) {
6288 c->Header.SGList = 1;
50a0decf 6289 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6290 } else {
6291 c->Header.SGList = 0;
50a0decf 6292 c->Header.SGTotal = cpu_to_le16(0);
edd16368 6293 }
edd16368
SC		 6294 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6295
edd16368
SC		 6296 if (cmd_type == TYPE_CMD) {
6297 switch (cmd) {
6298 case HPSA_INQUIRY:
6299 /* are we trying to read a vital product page */
b7bb24eb 6300 if (page_code & VPD_PAGE) {
edd16368 6301 c->Request.CDB[1] = 0x01;
b7bb24eb 6302 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 6303 }
6304 c->Request.CDBLen = 6;
a505b86f
SC		 6305 c->Request.type_attr_dir =
6306 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6307 c->Request.Timeout = 0;
6308 c->Request.CDB[0] = HPSA_INQUIRY;
6309 c->Request.CDB[4] = size & 0xFF;
6310 break;
6311 case HPSA_REPORT_LOG:
6312 case HPSA_REPORT_PHYS:
6313 /* Talking to controller so It's a physical command
6314 mode = 00 target = 0. Nothing to write.
6315 */
6316 c->Request.CDBLen = 12;
a505b86f
SC		 6317 c->Request.type_attr_dir =
6318 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6319 c->Request.Timeout = 0;
6320 c->Request.CDB[0] = cmd;
6321 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6322 c->Request.CDB[7] = (size >> 16) & 0xFF;
6323 c->Request.CDB[8] = (size >> 8) & 0xFF;
6324 c->Request.CDB[9] = size & 0xFF;
6325 break;
edd16368
SC		 6326 case HPSA_CACHE_FLUSH:
6327 c->Request.CDBLen = 12;
a505b86f
SC		 6328 c->Request.type_attr_dir =
6329 TYPE_ATTR_DIR(cmd_type,
6330 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 6331 c->Request.Timeout = 0;
6332 c->Request.CDB[0] = BMIC_WRITE;
6333 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 6334 c->Request.CDB[7] = (size >> 8) & 0xFF;
6335 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 6336 break;
6337 case TEST_UNIT_READY:
6338 c->Request.CDBLen = 6;
a505b86f
SC		 6339 c->Request.type_attr_dir =
6340 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 6341 c->Request.Timeout = 0;
6342 break;
283b4a9b
SC		 6343 case HPSA_GET_RAID_MAP:
6344 c->Request.CDBLen = 12;
a505b86f
SC		 6345 c->Request.type_attr_dir =
6346 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 6347 c->Request.Timeout = 0;
6348 c->Request.CDB[0] = HPSA_CISS_READ;
6349 c->Request.CDB[1] = cmd;
6350 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6351 c->Request.CDB[7] = (size >> 16) & 0xFF;
6352 c->Request.CDB[8] = (size >> 8) & 0xFF;
6353 c->Request.CDB[9] = size & 0xFF;
6354 break;
316b221a
SC		 6355 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6356 c->Request.CDBLen = 10;
a505b86f
SC		 6357 c->Request.type_attr_dir =
6358 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 6359 c->Request.Timeout = 0;
6360 c->Request.CDB[0] = BMIC_READ;
6361 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6362 c->Request.CDB[7] = (size >> 16) & 0xFF;
6363 c->Request.CDB[8] = (size >> 8) & 0xFF;
6364 break;
03383736
DB		 6365 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6366 c->Request.CDBLen = 10;
6367 c->Request.type_attr_dir =
6368 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6369 c->Request.Timeout = 0;
6370 c->Request.CDB[0] = BMIC_READ;
6371 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6372 c->Request.CDB[7] = (size >> 16) & 0xFF;
6373 c->Request.CDB[8] = (size >> 8) & 0XFF;
6374 break;
edd16368
SC		 6375 default:
6376 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6377 BUG();
a2dac136 6378 return -1;
edd16368
SC		 6379 }
6380 } else if (cmd_type == TYPE_MSG) {
6381 switch (cmd) {
6382
0b9b7b6e
ST		 6383 case HPSA_PHYS_TARGET_RESET:
6384 c->Request.CDBLen = 16;
6385 c->Request.type_attr_dir =
6386 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
6387 c->Request.Timeout = 0; /* Don't time out */
6388 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6389 c->Request.CDB[0] = HPSA_RESET;
6390 c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE;
6391 /* Physical target reset needs no control bytes 4-7*/
6392 c->Request.CDB[4] = 0x00;
6393 c->Request.CDB[5] = 0x00;
6394 c->Request.CDB[6] = 0x00;
6395 c->Request.CDB[7] = 0x00;
6396 break;
edd16368
SC		 6397 case HPSA_DEVICE_RESET_MSG:
6398 c->Request.CDBLen = 16;
a505b86f
SC		 6399 c->Request.type_attr_dir =
6400 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 6401 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 6402 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6403 c->Request.CDB[0] = cmd;
21e89afd 6404 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 6405 /* If bytes 4-7 are zero, it means reset the */
6406 /* LunID device */
6407 c->Request.CDB[4] = 0x00;
6408 c->Request.CDB[5] = 0x00;
6409 c->Request.CDB[6] = 0x00;
6410 c->Request.CDB[7] = 0x00;
75167d2c
SC		 6411 break;
6412 case HPSA_ABORT_MSG:
9b5c48c2 6413 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 6414 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 6415 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
6416 tag, c->Header.tag);
75167d2c 6417 c->Request.CDBLen = 16;
a505b86f
SC		 6418 c->Request.type_attr_dir =
6419 TYPE_ATTR_DIR(cmd_type,
6420 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 6421 c->Request.Timeout = 0; /* Don't time out */
6422 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
6423 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
6424 c->Request.CDB[2] = 0x00; /* reserved */
6425 c->Request.CDB[3] = 0x00; /* reserved */
6426 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 6427 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 6428 c->Request.CDB[12] = 0x00; /* reserved */
6429 c->Request.CDB[13] = 0x00; /* reserved */
6430 c->Request.CDB[14] = 0x00; /* reserved */
6431 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 6432 break;
edd16368
SC		 6433 default:
6434 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6435 cmd);
6436 BUG();
6437 }
6438 } else {
6439 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6440 BUG();
6441 }
6442
a505b86f 6443 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 6444 case XFER_READ:
6445 pci_dir = PCI_DMA_FROMDEVICE;
6446 break;
6447 case XFER_WRITE:
6448 pci_dir = PCI_DMA_TODEVICE;
6449 break;
6450 case XFER_NONE:
6451 pci_dir = PCI_DMA_NONE;
6452 break;
6453 default:
6454 pci_dir = PCI_DMA_BIDIRECTIONAL;
6455 }
a2dac136
SC		 6456 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
6457 return -1;
6458 return 0;
edd16368
SC		 6459}
6460
6461/*
6462 * Map (physical) PCI mem into (virtual) kernel space
6463 */
6464static void __iomem *remap_pci_mem(ulong base, ulong size)
6465{
6466 ulong page_base = ((ulong) base) & PAGE_MASK;
6467 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 6468 void __iomem *page_remapped = ioremap_nocache(page_base,
6469 page_offs + size);
edd16368
SC		 6470
6471 return page_remapped ? (page_remapped + page_offs) : NULL;
6472}
6473
254f796b 6474static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 6475{
254f796b 6476 return h->access.command_completed(h, q);
edd16368
SC		 6477}
6478
900c5440 6479static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 6480{
6481 return h->access.intr_pending(h);
6482}
6483
6484static inline long interrupt_not_for_us(struct ctlr_info *h)
6485{
10f66018
SC		 6486 return (h->access.intr_pending(h) == 0) ||
6487 (h->interrupts_enabled == 0);
edd16368
SC		 6488}
6489
01a02ffc
SC		 6490static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6491 u32 raw_tag)
edd16368
SC		 6492{
6493 if (unlikely(tag_index >= h->nr_cmds)) {
6494 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6495 return 1;
6496 }
6497 return 0;
6498}
6499
5a3d16f5 6500static inline void finish_cmd(struct CommandList *c)
edd16368 6501{
e85c5974 6502 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 6503 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6504 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 6505 complete_scsi_command(c);
8be986cc 6506 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
edd16368 6507 complete(c->waiting);
a104c99f
SC		 6508}
6509
303932fd 6510/* process completion of an indexed ("direct lookup") command */
1d94f94d 6511static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 6512 u32 raw_tag)
6513{
6514 u32 tag_index;
6515 struct CommandList *c;
6516
f2405db8 6517 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 6518 if (!bad_tag(h, tag_index, raw_tag)) {
6519 c = h->cmd_pool + tag_index;
6520 finish_cmd(c);
6521 }
303932fd
DB		 6522}
6523
64670ac8
SC		 6524/* Some controllers, like p400, will give us one interrupt
6525 * after a soft reset, even if we turned interrupts off.
6526 * Only need to check for this in the hpsa_xxx_discard_completions
6527 * functions.
6528 */
6529static int ignore_bogus_interrupt(struct ctlr_info *h)
6530{
6531 if (likely(!reset_devices))
6532 return 0;
6533
6534 if (likely(h->interrupts_enabled))
6535 return 0;
6536
6537 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
6538 "(known firmware bug.) Ignoring.\n");
6539
6540 return 1;
6541}
6542
254f796b
MG		 6543/*
6544 * Convert &h->q[x] (passed to interrupt handlers) back to h.
6545 * Relies on (h-q[x] == x) being true for x such that
6546 * 0 <= x < MAX_REPLY_QUEUES.
6547 */
6548static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 6549{
254f796b
MG		 6550 return container_of((queue - *queue), struct ctlr_info, q[0]);
6551}
6552
6553static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6554{
6555 struct ctlr_info *h = queue_to_hba(queue);
6556 u8 q = *(u8 *) queue;
64670ac8
SC		 6557 u32 raw_tag;
6558
6559 if (ignore_bogus_interrupt(h))
6560 return IRQ_NONE;
6561
6562 if (interrupt_not_for_us(h))
6563 return IRQ_NONE;
a0c12413 6564 h->last_intr_timestamp = get_jiffies_64();
64670ac8 6565 while (interrupt_pending(h)) {
254f796b 6566 raw_tag = get_next_completion(h, q);
64670ac8 6567 while (raw_tag != FIFO_EMPTY)
254f796b 6568 raw_tag = next_command(h, q);
64670ac8 6569 }
64670ac8
SC		 6570 return IRQ_HANDLED;
6571}
6572
254f796b 6573static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 6574{
254f796b 6575 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 6576 u32 raw_tag;
254f796b 6577 u8 q = *(u8 *) queue;
64670ac8
SC		 6578
6579 if (ignore_bogus_interrupt(h))
6580 return IRQ_NONE;
6581
a0c12413 6582 h->last_intr_timestamp = get_jiffies_64();
254f796b 6583 raw_tag = get_next_completion(h, q);
64670ac8 6584 while (raw_tag != FIFO_EMPTY)
254f796b 6585 raw_tag = next_command(h, q);
64670ac8
SC		 6586 return IRQ_HANDLED;
6587}
6588
254f796b 6589static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 6590{
254f796b 6591 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 6592 u32 raw_tag;
254f796b 6593 u8 q = *(u8 *) queue;
edd16368
SC		 6594
6595 if (interrupt_not_for_us(h))
6596 return IRQ_NONE;
a0c12413 6597 h->last_intr_timestamp = get_jiffies_64();
10f66018 6598 while (interrupt_pending(h)) {
254f796b 6599 raw_tag = get_next_completion(h, q);
10f66018 6600 while (raw_tag != FIFO_EMPTY) {
f2405db8 6601 process_indexed_cmd(h, raw_tag);
254f796b 6602 raw_tag = next_command(h, q);
10f66018
SC		 6603 }
6604 }
10f66018
SC		 6605 return IRQ_HANDLED;
6606}
6607
254f796b 6608static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 6609{
254f796b 6610 struct ctlr_info *h = queue_to_hba(queue);
10f66018 6611 u32 raw_tag;
254f796b 6612 u8 q = *(u8 *) queue;
10f66018 6613
a0c12413 6614 h->last_intr_timestamp = get_jiffies_64();
254f796b 6615 raw_tag = get_next_completion(h, q);
303932fd 6616 while (raw_tag != FIFO_EMPTY) {
f2405db8 6617 process_indexed_cmd(h, raw_tag);
254f796b 6618 raw_tag = next_command(h, q);
edd16368 6619 }
edd16368
SC		 6620 return IRQ_HANDLED;
6621}
6622
a9a3a273
SC		 6623/* Send a message CDB to the firmware. Careful, this only works
6624 * in simple mode, not performant mode due to the tag lookup.
6625 * We only ever use this immediately after a controller reset.
6626 */
6f039790
GKH		 6627static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
6628 unsigned char type)
edd16368
SC		 6629{
6630 struct Command {
6631 struct CommandListHeader CommandHeader;
6632 struct RequestBlock Request;
6633 struct ErrDescriptor ErrorDescriptor;
6634 };
6635 struct Command *cmd;
6636 static const size_t cmd_sz = sizeof(*cmd) +
6637 sizeof(cmd->ErrorDescriptor);
6638 dma_addr_t paddr64;
2b08b3e9
DB		 6639 __le32 paddr32;
6640 u32 tag;
edd16368
SC		 6641 void __iomem *vaddr;
6642 int i, err;
6643
6644 vaddr = pci_ioremap_bar(pdev, 0);
6645 if (vaddr == NULL)
6646 return -ENOMEM;
6647
6648 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
6649 * CCISS commands, so they must be allocated from the lower 4GiB of
6650 * memory.
6651 */
6652 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6653 if (err) {
6654 iounmap(vaddr);
1eaec8f3 6655 return err;
edd16368
SC		 6656 }
6657
6658 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
6659 if (cmd == NULL) {
6660 iounmap(vaddr);
6661 return -ENOMEM;
6662 }
6663
6664 /* This must fit, because of the 32-bit consistent DMA mask. Also,
6665 * although there's no guarantee, we assume that the address is at
6666 * least 4-byte aligned (most likely, it's page-aligned).
6667 */
2b08b3e9 6668 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 6669
6670 cmd->CommandHeader.ReplyQueue = 0;
6671 cmd->CommandHeader.SGList = 0;
50a0decf 6672 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 6673 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 6674 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
6675
6676 cmd->Request.CDBLen = 16;
a505b86f
SC		 6677 cmd->Request.type_attr_dir =
6678 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 6679 cmd->Request.Timeout = 0; /* Don't time out */
6680 cmd->Request.CDB[0] = opcode;
6681 cmd->Request.CDB[1] = type;
6682 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 6683 cmd->ErrorDescriptor.Addr =
2b08b3e9 6684 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 6685 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 6686
2b08b3e9 6687 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 6688
6689 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
6690 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 6691 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 6692 break;
6693 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
6694 }
6695
6696 iounmap(vaddr);
6697
6698 /* we leak the DMA buffer here ... no choice since the controller could
6699 * still complete the command.
6700 */
6701 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
6702 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
6703 opcode, type);
6704 return -ETIMEDOUT;
6705 }
6706
6707 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
6708
6709 if (tag & HPSA_ERROR_BIT) {
6710 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
6711 opcode, type);
6712 return -EIO;
6713 }
6714
6715 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
6716 opcode, type);
6717 return 0;
6718}
6719
edd16368
SC		 6720#define hpsa_noop(p) hpsa_message(p, 3, 0)
6721
1df8552a 6722static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 6723 void __iomem *vaddr, u32 use_doorbell)
1df8552a 6724{
1df8552a
SC		 6725
6726 if (use_doorbell) {
6727 /* For everything after the P600, the PCI power state method
6728 * of resetting the controller doesn't work, so we have this
6729 * other way using the doorbell register.
6730 */
6731 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 6732 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 6733
00701a96 6734 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 6735 * doorbell reset and before any attempt to talk to the board
6736 * at all to ensure that this actually works and doesn't fall
6737 * over in some weird corner cases.
6738 */
00701a96 6739 msleep(10000);
1df8552a
SC		 6740 } else { /* Try to do it the PCI power state way */
6741
6742 /* Quoting from the Open CISS Specification: "The Power
6743 * Management Control/Status Register (CSR) controls the power
6744 * state of the device. The normal operating state is D0,
6745 * CSR=00h. The software off state is D3, CSR=03h. To reset
6746 * the controller, place the interface device in D3 then to D0,
6747 * this causes a secondary PCI reset which will reset the
6748 * controller." */
2662cab8
DB		 6749
6750 int rc = 0;
6751
1df8552a 6752 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 6753
1df8552a 6754 /* enter the D3hot power management state */
2662cab8
DB		 6755 rc = pci_set_power_state(pdev, PCI_D3hot);
6756 if (rc)
6757 return rc;
1df8552a
SC		 6758
6759 msleep(500);
6760
6761 /* enter the D0 power management state */
2662cab8
DB		 6762 rc = pci_set_power_state(pdev, PCI_D0);
6763 if (rc)
6764 return rc;
c4853efe
MM		 6765
6766 /*
6767 * The P600 requires a small delay when changing states.
6768 * Otherwise we may think the board did not reset and we bail.
6769 * This for kdump only and is particular to the P600.
6770 */
6771 msleep(500);
1df8552a
SC		 6772 }
6773 return 0;
6774}
6775
6f039790 6776static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 6777{
6778 memset(driver_version, 0, len);
f79cfec6 6779 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 6780}
6781
6f039790 6782static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6783{
6784 char *driver_version;
6785 int i, size = sizeof(cfgtable->driver_version);
6786
6787 driver_version = kmalloc(size, GFP_KERNEL);
6788 if (!driver_version)
6789 return -ENOMEM;
6790
6791 init_driver_version(driver_version, size);
6792 for (i = 0; i < size; i++)
6793 writeb(driver_version[i], &cfgtable->driver_version[i]);
6794 kfree(driver_version);
6795 return 0;
6796}
6797
6f039790
GKH		 6798static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
6799 unsigned char *driver_ver)
580ada3c
SC		 6800{
6801 int i;
6802
6803 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
6804 driver_ver[i] = readb(&cfgtable->driver_version[i]);
6805}
6806
6f039790 6807static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6808{
6809
6810 char *driver_ver, *old_driver_ver;
6811 int rc, size = sizeof(cfgtable->driver_version);
6812
6813 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
6814 if (!old_driver_ver)
6815 return -ENOMEM;
6816 driver_ver = old_driver_ver + size;
6817
6818 /* After a reset, the 32 bytes of "driver version" in the cfgtable
6819 * should have been changed, otherwise we know the reset failed.
6820 */
6821 init_driver_version(old_driver_ver, size);
6822 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
6823 rc = !memcmp(driver_ver, old_driver_ver, size);
6824 kfree(old_driver_ver);
6825 return rc;
6826}
edd16368 6827/* This does a hard reset of the controller using PCI power management
1df8552a 6828 * states or the using the doorbell register.
edd16368 6829 */
6b6c1cd7 6830static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 6831{
1df8552a
SC		 6832 u64 cfg_offset;
6833 u32 cfg_base_addr;
6834 u64 cfg_base_addr_index;
6835 void __iomem *vaddr;
6836 unsigned long paddr;
580ada3c 6837 u32 misc_fw_support;
270d05de 6838 int rc;
1df8552a 6839 struct CfgTable __iomem *cfgtable;
cf0b08d0 6840 u32 use_doorbell;
270d05de 6841 u16 command_register;
edd16368 6842
1df8552a
SC		 6843 /* For controllers as old as the P600, this is very nearly
6844 * the same thing as
edd16368
SC		 6845 *
6846 * pci_save_state(pci_dev);
6847 * pci_set_power_state(pci_dev, PCI_D3hot);
6848 * pci_set_power_state(pci_dev, PCI_D0);
6849 * pci_restore_state(pci_dev);
6850 *
1df8552a
SC		 6851 * For controllers newer than the P600, the pci power state
6852 * method of resetting doesn't work so we have another way
6853 * using the doorbell register.
edd16368 6854 */
18867659 6855
60f923b9
RE		 6856 if (!ctlr_is_resettable(board_id)) {
6857 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 6858 return -ENODEV;
6859 }
46380786
SC		 6860
6861 /* if controller is soft- but not hard resettable... */
6862 if (!ctlr_is_hard_resettable(board_id))
6863 return -ENOTSUPP; /* try soft reset later. */
18867659 6864
270d05de
SC		 6865 /* Save the PCI command register */
6866 pci_read_config_word(pdev, 4, &command_register);
270d05de 6867 pci_save_state(pdev);
edd16368 6868
1df8552a
SC		 6869 /* find the first memory BAR, so we can find the cfg table */
6870 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6871 if (rc)
6872 return rc;
6873 vaddr = remap_pci_mem(paddr, 0x250);
6874 if (!vaddr)
6875 return -ENOMEM;
edd16368 6876
1df8552a
SC		 6877 /* find cfgtable in order to check if reset via doorbell is supported */
6878 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6879 &cfg_base_addr_index, &cfg_offset);
6880 if (rc)
6881 goto unmap_vaddr;
6882 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6883 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6884 if (!cfgtable) {
6885 rc = -ENOMEM;
6886 goto unmap_vaddr;
6887 }
580ada3c
SC		 6888 rc = write_driver_ver_to_cfgtable(cfgtable);
6889 if (rc)
03741d95 6890 goto unmap_cfgtable;
edd16368 6891
cf0b08d0
SC		 6892 /* If reset via doorbell register is supported, use that.
6893 * There are two such methods. Favor the newest method.
6894 */
1df8552a 6895 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6896 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6897 if (use_doorbell) {
6898 use_doorbell = DOORBELL_CTLR_RESET2;
6899 } else {
6900 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6901 if (use_doorbell) {
050f7147
SC		 6902 dev_warn(&pdev->dev,
6903 "Soft reset not supported. Firmware update is required.\n");
64670ac8 6904 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6905 goto unmap_cfgtable;
6906 }
6907 }
edd16368 6908
1df8552a
SC		 6909 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6910 if (rc)
6911 goto unmap_cfgtable;
edd16368 6912
270d05de 6913 pci_restore_state(pdev);
270d05de 6914 pci_write_config_word(pdev, 4, command_register);
edd16368 6915
1df8552a
SC		 6916 /* Some devices (notably the HP Smart Array 5i Controller)
6917 need a little pause here */
6918 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6919
fe5389c8
SC		 6920 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6921 if (rc) {
6922 dev_warn(&pdev->dev,
050f7147 6923 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 6924 goto unmap_cfgtable;
6925 }
fe5389c8 6926
580ada3c
SC		 6927 rc = controller_reset_failed(vaddr);
6928 if (rc < 0)
6929 goto unmap_cfgtable;
6930 if (rc) {
64670ac8
SC		 6931 dev_warn(&pdev->dev, "Unable to successfully reset "
6932 "controller. Will try soft reset.\n");
6933 rc = -ENOTSUPP;
580ada3c 6934 } else {
64670ac8 6935 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6936 }
6937
6938unmap_cfgtable:
6939 iounmap(cfgtable);
6940
6941unmap_vaddr:
6942 iounmap(vaddr);
6943 return rc;
edd16368
SC		 6944}
6945
6946/*
6947 * We cannot read the structure directly, for portability we must use
6948 * the io functions.
6949 * This is for debug only.
6950 */
42a91641 6951static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 6952{
58f8665c 6953#ifdef HPSA_DEBUG
edd16368
SC		 6954 int i;
6955 char temp_name[17];
6956
6957 dev_info(dev, "Controller Configuration information\n");
6958 dev_info(dev, "------------------------------------\n");
6959 for (i = 0; i < 4; i++)
6960 temp_name[i] = readb(&(tb->Signature[i]));
6961 temp_name[4] = '\0';
6962 dev_info(dev, " Signature = %s\n", temp_name);
6963 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6964 dev_info(dev, " Transport methods supported = 0x%x\n",
6965 readl(&(tb->TransportSupport)));
6966 dev_info(dev, " Transport methods active = 0x%x\n",
6967 readl(&(tb->TransportActive)));
6968 dev_info(dev, " Requested transport Method = 0x%x\n",
6969 readl(&(tb->HostWrite.TransportRequest)));
6970 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6971 readl(&(tb->HostWrite.CoalIntDelay)));
6972 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6973 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 6974 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 6975 readl(&(tb->CmdsOutMax)));
6976 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6977 for (i = 0; i < 16; i++)
6978 temp_name[i] = readb(&(tb->ServerName[i]));
6979 temp_name[16] = '\0';
6980 dev_info(dev, " Server Name = %s\n", temp_name);
6981 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6982 readl(&(tb->HeartBeat)));
edd16368 6983#endif /* HPSA_DEBUG */
58f8665c 6984}
edd16368
SC		 6985
6986static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6987{
6988 int i, offset, mem_type, bar_type;
6989
6990 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6991 return 0;
6992 offset = 0;
6993 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6994 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6995 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6996 offset += 4;
6997 else {
6998 mem_type = pci_resource_flags(pdev, i) &
6999 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
7000 switch (mem_type) {
7001 case PCI_BASE_ADDRESS_MEM_TYPE_32:
7002 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
7003 offset += 4; /* 32 bit */
7004 break;
7005 case PCI_BASE_ADDRESS_MEM_TYPE_64:
7006 offset += 8;
7007 break;
7008 default: /* reserved in PCI 2.2 */
7009 dev_warn(&pdev->dev,
7010 "base address is invalid\n");
7011 return -1;
7012 break;
7013 }
7014 }
7015 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
7016 return i + 1;
7017 }
7018 return -1;
7019}
7020
cc64c817
RE		 7021static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
7022{
7023 if (h->msix_vector) {
7024 if (h->pdev->msix_enabled)
7025 pci_disable_msix(h->pdev);
105a3dbc 7026 h->msix_vector = 0;
cc64c817
RE		 7027 } else if (h->msi_vector) {
7028 if (h->pdev->msi_enabled)
7029 pci_disable_msi(h->pdev);
105a3dbc 7030 h->msi_vector = 0;
cc64c817
RE		 7031 }
7032}
7033
edd16368 7034/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 7035 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 7036 */
6f039790 7037static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 7038{
7039#ifdef CONFIG_PCI_MSI
254f796b
MG		 7040 int err, i;
7041 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
7042
7043 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
7044 hpsa_msix_entries[i].vector = 0;
7045 hpsa_msix_entries[i].entry = i;
7046 }
edd16368
SC		 7047
7048 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 7049 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
7050 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 7051 goto default_int_mode;
55c06c71 7052 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 7053 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 7054 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 7055 if (h->msix_vector > num_online_cpus())
7056 h->msix_vector = num_online_cpus();
18fce3c4
AG		 7057 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
7058 1, h->msix_vector);
7059 if (err < 0) {
7060 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
7061 h->msix_vector = 0;
7062 goto single_msi_mode;
7063 } else if (err < h->msix_vector) {
55c06c71 7064 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 7065 "available\n", err);
edd16368 7066 }
18fce3c4
AG		 7067 h->msix_vector = err;
7068 for (i = 0; i < h->msix_vector; i++)
7069 h->intr[i] = hpsa_msix_entries[i].vector;
7070 return;
edd16368 7071 }
18fce3c4 7072single_msi_mode:
55c06c71 7073 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 7074 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 7075 if (!pci_enable_msi(h->pdev))
edd16368
SC		 7076 h->msi_vector = 1;
7077 else
55c06c71 7078 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 7079 }
7080default_int_mode:
7081#endif /* CONFIG_PCI_MSI */
7082 /* if we get here we're going to use the default interrupt mode */
a9a3a273 7083 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 7084}
7085
6f039790 7086static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 7087{
7088 int i;
7089 u32 subsystem_vendor_id, subsystem_device_id;
7090
7091 subsystem_vendor_id = pdev->subsystem_vendor;
7092 subsystem_device_id = pdev->subsystem_device;
7093 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
7094 subsystem_vendor_id;
7095
7096 for (i = 0; i < ARRAY_SIZE(products); i++)
7097 if (*board_id == products[i].board_id)
7098 return i;
7099
6798cc0a
SC		 7100 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
7101 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
7102 !hpsa_allow_any) {
e5c880d1
SC		 7103 dev_warn(&pdev->dev, "unrecognized board ID: "
7104 "0x%08x, ignoring.\n", *board_id);
7105 return -ENODEV;
7106 }
7107 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
7108}
7109
6f039790
GKH		 7110static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
7111 unsigned long *memory_bar)
3a7774ce
SC		 7112{
7113 int i;
7114
7115 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 7116 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 7117 /* addressing mode bits already removed */
12d2cd47
SC		 7118 *memory_bar = pci_resource_start(pdev, i);
7119 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 7120 *memory_bar);
7121 return 0;
7122 }
12d2cd47 7123 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 7124 return -ENODEV;
7125}
7126
6f039790
GKH		 7127static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7128 int wait_for_ready)
2c4c8c8b 7129{
fe5389c8 7130 int i, iterations;
2c4c8c8b 7131 u32 scratchpad;
fe5389c8
SC		 7132 if (wait_for_ready)
7133 iterations = HPSA_BOARD_READY_ITERATIONS;
7134 else
7135 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 7136
fe5389c8
SC		 7137 for (i = 0; i < iterations; i++) {
7138 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7139 if (wait_for_ready) {
7140 if (scratchpad == HPSA_FIRMWARE_READY)
7141 return 0;
7142 } else {
7143 if (scratchpad != HPSA_FIRMWARE_READY)
7144 return 0;
7145 }
2c4c8c8b
SC		 7146 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7147 }
fe5389c8 7148 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 7149 return -ENODEV;
7150}
7151
6f039790
GKH		 7152static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7153 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7154 u64 *cfg_offset)
a51fd47f
SC		 7155{
7156 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7157 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7158 *cfg_base_addr &= (u32) 0x0000ffff;
7159 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7160 if (*cfg_base_addr_index == -1) {
7161 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7162 return -ENODEV;
7163 }
7164 return 0;
7165}
7166
195f2c65
RE		 7167static void hpsa_free_cfgtables(struct ctlr_info *h)
7168{
105a3dbc 7169 if (h->transtable) {
195f2c65 7170 iounmap(h->transtable);
105a3dbc
RE		 7171 h->transtable = NULL;
7172 }
7173 if (h->cfgtable) {
195f2c65 7174 iounmap(h->cfgtable);
105a3dbc
RE		 7175 h->cfgtable = NULL;
7176 }
195f2c65
RE		 7177}
7178
7179/* Find and map CISS config table and transfer table
7180+ * several items must be unmapped (freed) later
7181+ * */
6f039790 7182static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 7183{
01a02ffc
SC		 7184 u64 cfg_offset;
7185 u32 cfg_base_addr;
7186 u64 cfg_base_addr_index;
303932fd 7187 u32 trans_offset;
a51fd47f 7188 int rc;
77c4495c 7189
a51fd47f
SC		 7190 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7191 &cfg_base_addr_index, &cfg_offset);
7192 if (rc)
7193 return rc;
77c4495c 7194 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 7195 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 7196 if (!h->cfgtable) {
7197 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 7198 return -ENOMEM;
cd3c81c4 7199 }
580ada3c
SC		 7200 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7201 if (rc)
7202 return rc;
77c4495c 7203 /* Find performant mode table. */
a51fd47f 7204 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 7205 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7206 cfg_base_addr_index)+cfg_offset+trans_offset,
7207 sizeof(*h->transtable));
195f2c65
RE		 7208 if (!h->transtable) {
7209 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7210 hpsa_free_cfgtables(h);
77c4495c 7211 return -ENOMEM;
195f2c65 7212 }
77c4495c
SC		 7213 return 0;
7214}
7215
6f039790 7216static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 7217{
41ce4c35
SC		 7218#define MIN_MAX_COMMANDS 16
7219 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7220
7221 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 7222
7223 /* Limit commands in memory limited kdump scenario. */
7224 if (reset_devices && h->max_commands > 32)
7225 h->max_commands = 32;
7226
41ce4c35
SC		 7227 if (h->max_commands < MIN_MAX_COMMANDS) {
7228 dev_warn(&h->pdev->dev,
7229 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7230 h->max_commands,
7231 MIN_MAX_COMMANDS);
7232 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 7233 }
7234}
7235
c7ee65b3
WS		 7236/* If the controller reports that the total max sg entries is greater than 512,
7237 * then we know that chained SG blocks work. (Original smart arrays did not
7238 * support chained SG blocks and would return zero for max sg entries.)
7239 */
7240static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7241{
7242 return h->maxsgentries > 512;
7243}
7244
b93d7536
SC		 7245/* Interrogate the hardware for some limits:
7246 * max commands, max SG elements without chaining, and with chaining,
7247 * SG chain block size, etc.
7248 */
6f039790 7249static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 7250{
cba3d38b 7251 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 7252 h->nr_cmds = h->max_commands;
b93d7536 7253 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 7254 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 7255 if (hpsa_supports_chained_sg_blocks(h)) {
7256 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 7257 h->max_cmd_sg_entries = 32;
1a63ea6f 7258 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 7259 h->maxsgentries--; /* save one for chain pointer */
7260 } else {
c7ee65b3
WS		 7261 /*
7262 * Original smart arrays supported at most 31 s/g entries
7263 * embedded inline in the command (trying to use more
7264 * would lock up the controller)
7265 */
7266 h->max_cmd_sg_entries = 31;
1a63ea6f 7267 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 7268 h->chainsize = 0;
b93d7536 7269 }
75167d2c
SC		 7270
7271 /* Find out what task management functions are supported and cache */
7272 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 7273 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7274 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7275 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7276 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
8be986cc
SC		 7277 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7278 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
b93d7536
SC		 7279}
7280
76c46e49
SC		 7281static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7282{
0fc9fd40 7283 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 7284 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 7285 return false;
7286 }
7287 return true;
7288}
7289
97a5e98c 7290static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 7291{
97a5e98c 7292 u32 driver_support;
f7c39101 7293
97a5e98c 7294 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 7295 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7296#ifdef CONFIG_X86
97a5e98c 7297 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 7298#endif
28e13446
SC		 7299 driver_support |= ENABLE_UNIT_ATTN;
7300 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 7301}
7302
3d0eab67
SC		 7303/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7304 * in a prefetch beyond physical memory.
7305 */
7306static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7307{
7308 u32 dma_prefetch;
7309
7310 if (h->board_id != 0x3225103C)
7311 return;
7312 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7313 dma_prefetch |= 0x8000;
7314 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7315}
7316
c706a795 7317static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 7318{
7319 int i;
7320 u32 doorbell_value;
7321 unsigned long flags;
7322 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 7323 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 7324 spin_lock_irqsave(&h->lock, flags);
7325 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7326 spin_unlock_irqrestore(&h->lock, flags);
7327 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 7328 goto done;
76438d08 7329 /* delay and try again */
007e7aa9 7330 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 7331 }
c706a795
RE		 7332 return -ENODEV;
7333done:
7334 return 0;
76438d08
SC		 7335}
7336
c706a795 7337static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 7338{
7339 int i;
6eaf46fd
SC		 7340 u32 doorbell_value;
7341 unsigned long flags;
eb6b2ae9
SC		 7342
7343 /* under certain very rare conditions, this can take awhile.
7344 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7345 * as we enter this code.)
7346 */
007e7aa9 7347 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 7348 if (h->remove_in_progress)
7349 goto done;
6eaf46fd
SC		 7350 spin_lock_irqsave(&h->lock, flags);
7351 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7352 spin_unlock_irqrestore(&h->lock, flags);
382be668 7353 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 7354 goto done;
eb6b2ae9 7355 /* delay and try again */
007e7aa9 7356 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 7357 }
c706a795
RE		 7358 return -ENODEV;
7359done:
7360 return 0;
3f4336f3
SC		 7361}
7362
c706a795 7363/* return -ENODEV or other reason on error, 0 on success */
6f039790 7364static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 7365{
7366 u32 trans_support;
7367
7368 trans_support = readl(&(h->cfgtable->TransportSupport));
7369 if (!(trans_support & SIMPLE_MODE))
7370 return -ENOTSUPP;
7371
7372 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 7373
3f4336f3
SC		 7374 /* Update the field, and then ring the doorbell */
7375 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 7376 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 7377 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7378 if (hpsa_wait_for_mode_change_ack(h))
7379 goto error;
eb6b2ae9 7380 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 7381 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7382 goto error;
960a30e7 7383 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 7384 return 0;
283b4a9b 7385error:
050f7147 7386 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 7387 return -ENODEV;
eb6b2ae9
SC		 7388}
7389
195f2c65
RE		 7390/* free items allocated or mapped by hpsa_pci_init */
7391static void hpsa_free_pci_init(struct ctlr_info *h)
7392{
7393 hpsa_free_cfgtables(h); /* pci_init 4 */
7394 iounmap(h->vaddr); /* pci_init 3 */
105a3dbc 7395 h->vaddr = NULL;
195f2c65 7396 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
943a7021
RE		 7397 /*
7398 * call pci_disable_device before pci_release_regions per
7399 * Documentation/PCI/pci.txt
7400 */
195f2c65 7401 pci_disable_device(h->pdev); /* pci_init 1 */
943a7021 7402 pci_release_regions(h->pdev); /* pci_init 2 */
195f2c65
RE		 7403}
7404
7405/* several items must be freed later */
6f039790 7406static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 7407{
eb6b2ae9 7408 int prod_index, err;
edd16368 7409
e5c880d1
SC		 7410 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
7411 if (prod_index < 0)
60f923b9 7412 return prod_index;
e5c880d1
SC		 7413 h->product_name = products[prod_index].product_name;
7414 h->access = *(products[prod_index].access);
edd16368 7415
9b5c48c2
SC		 7416 h->needs_abort_tags_swizzled =
7417 ctlr_needs_abort_tags_swizzled(h->board_id);
7418
e5a44df8
MG		 7419 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7420 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7421
55c06c71 7422 err = pci_enable_device(h->pdev);
edd16368 7423 if (err) {
195f2c65 7424 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
943a7021 7425 pci_disable_device(h->pdev);
edd16368
SC		 7426 return err;
7427 }
7428
f79cfec6 7429 err = pci_request_regions(h->pdev, HPSA);
edd16368 7430 if (err) {
55c06c71 7431 dev_err(&h->pdev->dev,
195f2c65 7432 "failed to obtain PCI resources\n");
943a7021
RE		 7433 pci_disable_device(h->pdev);
7434 return err;
edd16368 7435 }
4fa604e1
RE		 7436
7437 pci_set_master(h->pdev);
7438
6b3f4c52 7439 hpsa_interrupt_mode(h);
12d2cd47 7440 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 7441 if (err)
195f2c65 7442 goto clean2; /* intmode+region, pci */
edd16368 7443 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 7444 if (!h->vaddr) {
195f2c65 7445 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 7446 err = -ENOMEM;
195f2c65 7447 goto clean2; /* intmode+region, pci */
204892e9 7448 }
fe5389c8 7449 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 7450 if (err)
195f2c65 7451 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 7452 err = hpsa_find_cfgtables(h);
7453 if (err)
195f2c65 7454 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 7455 hpsa_find_board_params(h);
edd16368 7456
76c46e49 7457 if (!hpsa_CISS_signature_present(h)) {
edd16368 7458 err = -ENODEV;
195f2c65 7459 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 7460 }
97a5e98c 7461 hpsa_set_driver_support_bits(h);
3d0eab67 7462 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 7463 err = hpsa_enter_simple_mode(h);
7464 if (err)
195f2c65 7465 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 7466 return 0;
7467
195f2c65
RE		 7468clean4: /* cfgtables, vaddr, intmode+region, pci */
7469 hpsa_free_cfgtables(h);
7470clean3: /* vaddr, intmode+region, pci */
7471 iounmap(h->vaddr);
105a3dbc 7472 h->vaddr = NULL;
195f2c65
RE		 7473clean2: /* intmode+region, pci */
7474 hpsa_disable_interrupt_mode(h);
943a7021
RE		 7475 /*
7476 * call pci_disable_device before pci_release_regions per
7477 * Documentation/PCI/pci.txt
7478 */
195f2c65 7479 pci_disable_device(h->pdev);
943a7021 7480 pci_release_regions(h->pdev);
edd16368
SC		 7481 return err;
7482}
7483
6f039790 7484static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 7485{
7486 int rc;
7487
7488#define HBA_INQUIRY_BYTE_COUNT 64
7489 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7490 if (!h->hba_inquiry_data)
7491 return;
7492 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7493 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7494 if (rc != 0) {
7495 kfree(h->hba_inquiry_data);
7496 h->hba_inquiry_data = NULL;
7497 }
7498}
7499
6b6c1cd7 7500static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 7501{
1df8552a 7502 int rc, i;
3b747298 7503 void __iomem *vaddr;
4c2a8c40
SC		 7504
7505 if (!reset_devices)
7506 return 0;
7507
132aa220
TH		 7508 /* kdump kernel is loading, we don't know in which state is
7509 * the pci interface. The dev->enable_cnt is equal zero
7510 * so we call enable+disable, wait a while and switch it on.
7511 */
7512 rc = pci_enable_device(pdev);
7513 if (rc) {
7514 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7515 return -ENODEV;
7516 }
7517 pci_disable_device(pdev);
7518 msleep(260); /* a randomly chosen number */
7519 rc = pci_enable_device(pdev);
7520 if (rc) {
7521 dev_warn(&pdev->dev, "failed to enable device.\n");
7522 return -ENODEV;
7523 }
4fa604e1 7524
859c75ab 7525 pci_set_master(pdev);
4fa604e1 7526
3b747298
TH		 7527 vaddr = pci_ioremap_bar(pdev, 0);
7528 if (vaddr == NULL) {
7529 rc = -ENOMEM;
7530 goto out_disable;
7531 }
7532 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
7533 iounmap(vaddr);
7534
1df8552a 7535 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 7536 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 7537
1df8552a
SC		 7538 /* -ENOTSUPP here means we cannot reset the controller
7539 * but it's already (and still) up and running in
18867659
SC		 7540 * "performant mode". Or, it might be 640x, which can't reset
7541 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 7542 */
adf1b3a3 7543 if (rc)
132aa220 7544 goto out_disable;
4c2a8c40
SC		 7545
7546 /* Now try to get the controller to respond to a no-op */
1ba66c9c 7547 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 7548 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
7549 if (hpsa_noop(pdev) == 0)
7550 break;
7551 else
7552 dev_warn(&pdev->dev, "no-op failed%s\n",
7553 (i < 11 ? "; re-trying" : ""));
7554 }
132aa220
TH		 7555
7556out_disable:
7557
7558 pci_disable_device(pdev);
7559 return rc;
4c2a8c40
SC		 7560}
7561
1fb7c98a
RE		 7562static void hpsa_free_cmd_pool(struct ctlr_info *h)
7563{
7564 kfree(h->cmd_pool_bits);
105a3dbc
RE		 7565 h->cmd_pool_bits = NULL;
7566 if (h->cmd_pool) {
1fb7c98a
RE		 7567 pci_free_consistent(h->pdev,
7568 h->nr_cmds * sizeof(struct CommandList),
7569 h->cmd_pool,
7570 h->cmd_pool_dhandle);
105a3dbc
RE		 7571 h->cmd_pool = NULL;
7572 h->cmd_pool_dhandle = 0;
7573 }
7574 if (h->errinfo_pool) {
1fb7c98a
RE		 7575 pci_free_consistent(h->pdev,
7576 h->nr_cmds * sizeof(struct ErrorInfo),
7577 h->errinfo_pool,
7578 h->errinfo_pool_dhandle);
105a3dbc
RE		 7579 h->errinfo_pool = NULL;
7580 h->errinfo_pool_dhandle = 0;
7581 }
1fb7c98a
RE		 7582}
7583
d37ffbe4 7584static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 7585{
7586 h->cmd_pool_bits = kzalloc(
7587 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
7588 sizeof(unsigned long), GFP_KERNEL);
7589 h->cmd_pool = pci_alloc_consistent(h->pdev,
7590 h->nr_cmds * sizeof(*h->cmd_pool),
7591 &(h->cmd_pool_dhandle));
7592 h->errinfo_pool = pci_alloc_consistent(h->pdev,
7593 h->nr_cmds * sizeof(*h->errinfo_pool),
7594 &(h->errinfo_pool_dhandle));
7595 if ((h->cmd_pool_bits == NULL)
7596 || (h->cmd_pool == NULL)
7597 || (h->errinfo_pool == NULL)) {
7598 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 7599 goto clean_up;
2e9d1b36 7600 }
360c73bd 7601 hpsa_preinitialize_commands(h);
2e9d1b36 7602 return 0;
2c143342
RE		 7603clean_up:
7604 hpsa_free_cmd_pool(h);
7605 return -ENOMEM;
2e9d1b36
SC		 7606}
7607
41b3cf08
SC		 7608static void hpsa_irq_affinity_hints(struct ctlr_info *h)
7609{
ec429952 7610 int i, cpu;
41b3cf08
SC		 7611
7612 cpu = cpumask_first(cpu_online_mask);
7613 for (i = 0; i < h->msix_vector; i++) {
ec429952 7614 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 7615 cpu = cpumask_next(cpu, cpu_online_mask);
7616 }
7617}
7618
ec501a18
RE		 7619/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
7620static void hpsa_free_irqs(struct ctlr_info *h)
7621{
7622 int i;
7623
7624 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
7625 /* Single reply queue, only one irq to free */
7626 i = h->intr_mode;
7627 irq_set_affinity_hint(h->intr[i], NULL);
7628 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7629 h->q[i] = 0;
ec501a18
RE		 7630 return;
7631 }
7632
7633 for (i = 0; i < h->msix_vector; i++) {
7634 irq_set_affinity_hint(h->intr[i], NULL);
7635 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7636 h->q[i] = 0;
ec501a18 7637 }
a4e17fc1
RE		 7638 for (; i < MAX_REPLY_QUEUES; i++)
7639 h->q[i] = 0;
ec501a18
RE		 7640}
7641
9ee61794
RE		 7642/* returns 0 on success; cleans up and returns -Enn on error */
7643static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 7644 irqreturn_t (*msixhandler)(int, void *),
7645 irqreturn_t (*intxhandler)(int, void *))
7646{
254f796b 7647 int rc, i;
0ae01a32 7648
254f796b
MG		 7649 /*
7650 * initialize h->q[x] = x so that interrupt handlers know which
7651 * queue to process.
7652 */
7653 for (i = 0; i < MAX_REPLY_QUEUES; i++)
7654 h->q[i] = (u8) i;
7655
eee0f03a 7656 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 7657 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 7658 for (i = 0; i < h->msix_vector; i++) {
8b47004a 7659 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
254f796b 7660 rc = request_irq(h->intr[i], msixhandler,
8b47004a 7661 0, h->intrname[i],
254f796b 7662 &h->q[i]);
a4e17fc1
RE		 7663 if (rc) {
7664 int j;
7665
7666 dev_err(&h->pdev->dev,
7667 "failed to get irq %d for %s\n",
7668 h->intr[i], h->devname);
7669 for (j = 0; j < i; j++) {
7670 free_irq(h->intr[j], &h->q[j]);
7671 h->q[j] = 0;
7672 }
7673 for (; j < MAX_REPLY_QUEUES; j++)
7674 h->q[j] = 0;
7675 return rc;
7676 }
7677 }
41b3cf08 7678 hpsa_irq_affinity_hints(h);
254f796b
MG		 7679 } else {
7680 /* Use single reply pool */
eee0f03a 7681 if (h->msix_vector > 0 || h->msi_vector) {
8b47004a
RE		 7682 if (h->msix_vector)
7683 sprintf(h->intrname[h->intr_mode],
7684 "%s-msix", h->devname);
7685 else
7686 sprintf(h->intrname[h->intr_mode],
7687 "%s-msi", h->devname);
254f796b 7688 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7689 msixhandler, 0,
7690 h->intrname[h->intr_mode],
254f796b
MG		 7691 &h->q[h->intr_mode]);
7692 } else {
8b47004a
RE		 7693 sprintf(h->intrname[h->intr_mode],
7694 "%s-intx", h->devname);
254f796b 7695 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7696 intxhandler, IRQF_SHARED,
7697 h->intrname[h->intr_mode],
254f796b
MG		 7698 &h->q[h->intr_mode]);
7699 }
105a3dbc 7700 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
254f796b 7701 }
0ae01a32 7702 if (rc) {
195f2c65 7703 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 7704 h->intr[h->intr_mode], h->devname);
195f2c65 7705 hpsa_free_irqs(h);
0ae01a32
SC		 7706 return -ENODEV;
7707 }
7708 return 0;
7709}
7710
6f039790 7711static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8 7712{
39c53f55 7713 int rc;
bf43caf3 7714 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
64670ac8
SC		 7715
7716 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
39c53f55
RE		 7717 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
7718 if (rc) {
64670ac8 7719 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
39c53f55 7720 return rc;
64670ac8
SC		 7721 }
7722
7723 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
39c53f55
RE		 7724 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
7725 if (rc) {
64670ac8
SC		 7726 dev_warn(&h->pdev->dev, "Board failed to become ready "
7727 "after soft reset.\n");
39c53f55 7728 return rc;
64670ac8
SC		 7729 }
7730
7731 return 0;
7732}
7733
072b0518
SC		 7734static void hpsa_free_reply_queues(struct ctlr_info *h)
7735{
7736 int i;
7737
7738 for (i = 0; i < h->nreply_queues; i++) {
7739 if (!h->reply_queue[i].head)
7740 continue;
1fb7c98a
RE		 7741 pci_free_consistent(h->pdev,
7742 h->reply_queue_size,
7743 h->reply_queue[i].head,
7744 h->reply_queue[i].busaddr);
072b0518
SC		 7745 h->reply_queue[i].head = NULL;
7746 h->reply_queue[i].busaddr = 0;
7747 }
105a3dbc 7748 h->reply_queue_size = 0;
072b0518
SC		 7749}
7750
0097f0f4
SC		 7751static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
7752{
105a3dbc
RE		 7753 hpsa_free_performant_mode(h); /* init_one 7 */
7754 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
7755 hpsa_free_cmd_pool(h); /* init_one 5 */
7756 hpsa_free_irqs(h); /* init_one 4 */
2946e82b
RE		 7757 scsi_host_put(h->scsi_host); /* init_one 3 */
7758 h->scsi_host = NULL; /* init_one 3 */
7759 hpsa_free_pci_init(h); /* init_one 2_5 */
9ecd953a
RE		 7760 free_percpu(h->lockup_detected); /* init_one 2 */
7761 h->lockup_detected = NULL; /* init_one 2 */
7762 if (h->resubmit_wq) {
7763 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
7764 h->resubmit_wq = NULL;
7765 }
7766 if (h->rescan_ctlr_wq) {
7767 destroy_workqueue(h->rescan_ctlr_wq);
7768 h->rescan_ctlr_wq = NULL;
7769 }
105a3dbc 7770 kfree(h); /* init_one 1 */
64670ac8
SC		 7771}
7772
a0c12413 7773/* Called when controller lockup detected. */
f2405db8 7774static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 7775{
281a7fd0
WS		 7776 int i, refcount;
7777 struct CommandList *c;
25163bd5 7778 int failcount = 0;
a0c12413 7779
080ef1cc 7780 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 7781 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7782 c = h->cmd_pool + i;
281a7fd0
WS		 7783 refcount = atomic_inc_return(&c->refcount);
7784 if (refcount > 1) {
25163bd5 7785 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 7786 finish_cmd(c);
433b5f4d 7787 atomic_dec(&h->commands_outstanding);
25163bd5 7788 failcount++;
281a7fd0
WS		 7789 }
7790 cmd_free(h, c);
a0c12413 7791 }
25163bd5
WS		 7792 dev_warn(&h->pdev->dev,
7793 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 7794}
7795
094963da
SC		 7796static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
7797{
c8ed0010 7798 int cpu;
094963da 7799
c8ed0010 7800 for_each_online_cpu(cpu) {
094963da
SC		 7801 u32 *lockup_detected;
7802 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
7803 *lockup_detected = value;
094963da
SC		 7804 }
7805 wmb(); /* be sure the per-cpu variables are out to memory */
7806}
7807
a0c12413
SC		 7808static void controller_lockup_detected(struct ctlr_info *h)
7809{
7810 unsigned long flags;
094963da 7811 u32 lockup_detected;
a0c12413 7812
a0c12413
SC		 7813 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7814 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 7815 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
7816 if (!lockup_detected) {
7817 /* no heartbeat, but controller gave us a zero. */
7818 dev_warn(&h->pdev->dev,
25163bd5
WS		 7819 "lockup detected after %d but scratchpad register is zero\n",
7820 h->heartbeat_sample_interval / HZ);
094963da
SC		 7821 lockup_detected = 0xffffffff;
7822 }
7823 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 7824 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 7825 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
7826 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 7827 pci_disable_device(h->pdev);
f2405db8 7828 fail_all_outstanding_cmds(h);
a0c12413
SC		 7829}
7830
25163bd5 7831static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 7832{
7833 u64 now;
7834 u32 heartbeat;
7835 unsigned long flags;
7836
a0c12413
SC		 7837 now = get_jiffies_64();
7838 /* If we've received an interrupt recently, we're ok. */
7839 if (time_after64(h->last_intr_timestamp +
e85c5974 7840 (h->heartbeat_sample_interval), now))
25163bd5 7841 return false;
a0c12413
SC		 7842
7843 /*
7844 * If we've already checked the heartbeat recently, we're ok.
7845 * This could happen if someone sends us a signal. We
7846 * otherwise don't care about signals in this thread.
7847 */
7848 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 7849 (h->heartbeat_sample_interval), now))
25163bd5 7850 return false;
a0c12413
SC		 7851
7852 /* If heartbeat has not changed since we last looked, we're not ok. */
7853 spin_lock_irqsave(&h->lock, flags);
7854 heartbeat = readl(&h->cfgtable->HeartBeat);
7855 spin_unlock_irqrestore(&h->lock, flags);
7856 if (h->last_heartbeat == heartbeat) {
7857 controller_lockup_detected(h);
25163bd5 7858 return true;
a0c12413
SC		 7859 }
7860
7861 /* We're ok. */
7862 h->last_heartbeat = heartbeat;
7863 h->last_heartbeat_timestamp = now;
25163bd5 7864 return false;
a0c12413
SC		 7865}
7866
9846590e 7867static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 7868{
7869 int i;
7870 char *event_type;
7871
e4aa3e6a
SC		 7872 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7873 return;
7874
76438d08 7875 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 7876 if ((h->transMethod & (CFGTBL_Trans_io_accel1
7877 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 7878 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
7879 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
7880
7881 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
7882 event_type = "state change";
7883 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
7884 event_type = "configuration change";
7885 /* Stop sending new RAID offload reqs via the IO accelerator */
7886 scsi_block_requests(h->scsi_host);
7887 for (i = 0; i < h->ndevices; i++)
7888 h->dev[i]->offload_enabled = 0;
23100dd9 7889 hpsa_drain_accel_commands(h);
76438d08
SC		 7890 /* Set 'accelerator path config change' bit */
7891 dev_warn(&h->pdev->dev,
7892 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7893 h->events, event_type);
7894 writel(h->events, &(h->cfgtable->clear_event_notify));
7895 /* Set the "clear event notify field update" bit 6 */
7896 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7897 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7898 hpsa_wait_for_clear_event_notify_ack(h);
7899 scsi_unblock_requests(h->scsi_host);
7900 } else {
7901 /* Acknowledge controller notification events. */
7902 writel(h->events, &(h->cfgtable->clear_event_notify));
7903 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7904 hpsa_wait_for_clear_event_notify_ack(h);
7905#if 0
7906 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7907 hpsa_wait_for_mode_change_ack(h);
7908#endif
7909 }
9846590e 7910 return;
76438d08
SC		 7911}
7912
7913/* Check a register on the controller to see if there are configuration
7914 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 7915 * we should rescan the controller for devices.
7916 * Also check flag for driver-initiated rescan.
76438d08 7917 */
9846590e 7918static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 7919{
853633e8
DB		 7920 if (h->drv_req_rescan) {
7921 h->drv_req_rescan = 0;
7922 return 1;
7923 }
7924
76438d08 7925 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 7926 return 0;
76438d08
SC		 7927
7928 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 7929 return h->events & RESCAN_REQUIRED_EVENT_BITS;
7930}
76438d08 7931
9846590e
SC		 7932/*
7933 * Check if any of the offline devices have become ready
7934 */
7935static int hpsa_offline_devices_ready(struct ctlr_info *h)
7936{
7937 unsigned long flags;
7938 struct offline_device_entry *d;
7939 struct list_head *this, *tmp;
7940
7941 spin_lock_irqsave(&h->offline_device_lock, flags);
7942 list_for_each_safe(this, tmp, &h->offline_device_list) {
7943 d = list_entry(this, struct offline_device_entry,
7944 offline_list);
7945 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 7946 if (!hpsa_volume_offline(h, d->scsi3addr)) {
7947 spin_lock_irqsave(&h->offline_device_lock, flags);
7948 list_del(&d->offline_list);
7949 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 7950 return 1;
d1fea47c 7951 }
9846590e
SC		 7952 spin_lock_irqsave(&h->offline_device_lock, flags);
7953 }
7954 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7955 return 0;
76438d08
SC		 7956}
7957
6636e7f4 7958static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 7959{
7960 unsigned long flags;
8a98db73 7961 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 7962 struct ctlr_info, rescan_ctlr_work);
7963
7964
7965 if (h->remove_in_progress)
8a98db73 7966 return;
9846590e
SC		 7967
7968 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
7969 scsi_host_get(h->scsi_host);
9846590e
SC		 7970 hpsa_ack_ctlr_events(h);
7971 hpsa_scan_start(h->scsi_host);
7972 scsi_host_put(h->scsi_host);
7973 }
8a98db73 7974 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 7975 if (!h->remove_in_progress)
7976 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7977 h->heartbeat_sample_interval);
7978 spin_unlock_irqrestore(&h->lock, flags);
7979}
7980
7981static void hpsa_monitor_ctlr_worker(struct work_struct *work)
7982{
7983 unsigned long flags;
7984 struct ctlr_info *h = container_of(to_delayed_work(work),
7985 struct ctlr_info, monitor_ctlr_work);
7986
7987 detect_controller_lockup(h);
7988 if (lockup_detected(h))
a0c12413 7989 return;
6636e7f4
DB		 7990
7991 spin_lock_irqsave(&h->lock, flags);
7992 if (!h->remove_in_progress)
7993 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 7994 h->heartbeat_sample_interval);
7995 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 7996}
7997
6636e7f4
DB		 7998static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
7999 char *name)
8000{
8001 struct workqueue_struct *wq = NULL;
6636e7f4 8002
397ea9cb 8003 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 8004 if (!wq)
8005 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
8006
8007 return wq;
8008}
8009
6f039790 8010static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 8011{
4c2a8c40 8012 int dac, rc;
edd16368 8013 struct ctlr_info *h;
64670ac8
SC		 8014 int try_soft_reset = 0;
8015 unsigned long flags;
6b6c1cd7 8016 u32 board_id;
edd16368
SC		 8017
8018 if (number_of_controllers == 0)
8019 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 8020
6b6c1cd7
TH		 8021 rc = hpsa_lookup_board_id(pdev, &board_id);
8022 if (rc < 0) {
8023 dev_warn(&pdev->dev, "Board ID not found\n");
8024 return rc;
8025 }
8026
8027 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 8028 if (rc) {
8029 if (rc != -ENOTSUPP)
8030 return rc;
8031 /* If the reset fails in a particular way (it has no way to do
8032 * a proper hard reset, so returns -ENOTSUPP) we can try to do
8033 * a soft reset once we get the controller configured up to the
8034 * point that it can accept a command.
8035 */
8036 try_soft_reset = 1;
8037 rc = 0;
8038 }
8039
8040reinit_after_soft_reset:
edd16368 8041
303932fd
DB		 8042 /* Command structures must be aligned on a 32-byte boundary because
8043 * the 5 lower bits of the address are used by the hardware. and by
8044 * the driver. See comments in hpsa.h for more info.
8045 */
303932fd 8046 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368 8047 h = kzalloc(sizeof(*h), GFP_KERNEL);
105a3dbc
RE		 8048 if (!h) {
8049 dev_err(&pdev->dev, "Failed to allocate controller head\n");
ecd9aad4 8050 return -ENOMEM;
105a3dbc 8051 }
edd16368 8052
55c06c71 8053 h->pdev = pdev;
105a3dbc 8054
a9a3a273 8055 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 8056 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 8057 spin_lock_init(&h->lock);
9846590e 8058 spin_lock_init(&h->offline_device_lock);
6eaf46fd 8059 spin_lock_init(&h->scan_lock);
34f0c627 8060 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 8061 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da
SC		 8062
8063 /* Allocate and clear per-cpu variable lockup_detected */
8064 h->lockup_detected = alloc_percpu(u32);
2a5ac326 8065 if (!h->lockup_detected) {
105a3dbc 8066 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
2a5ac326 8067 rc = -ENOMEM;
2efa5929 8068 goto clean1; /* aer/h */
2a5ac326 8069 }
094963da
SC		 8070 set_lockup_detected_for_all_cpus(h, 0);
8071
55c06c71 8072 rc = hpsa_pci_init(h);
105a3dbc 8073 if (rc)
2946e82b
RE		 8074 goto clean2; /* lu, aer/h */
8075
8076 /* relies on h-> settings made by hpsa_pci_init, including
8077 * interrupt_mode h->intr */
8078 rc = hpsa_scsi_host_alloc(h);
8079 if (rc)
8080 goto clean2_5; /* pci, lu, aer/h */
edd16368 8081
2946e82b 8082 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
edd16368
SC		 8083 h->ctlr = number_of_controllers;
8084 number_of_controllers++;
edd16368
SC		 8085
8086 /* configure PCI DMA stuff */
ecd9aad4
SC		 8087 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
8088 if (rc == 0) {
edd16368 8089 dac = 1;
ecd9aad4
SC		 8090 } else {
8091 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8092 if (rc == 0) {
8093 dac = 0;
8094 } else {
8095 dev_err(&pdev->dev, "no suitable DMA available\n");
2946e82b 8096 goto clean3; /* shost, pci, lu, aer/h */
ecd9aad4 8097 }
edd16368
SC		 8098 }
8099
8100 /* make sure the board interrupts are off */
8101 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 8102
105a3dbc
RE		 8103 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
8104 if (rc)
2946e82b 8105 goto clean3; /* shost, pci, lu, aer/h */
d37ffbe4 8106 rc = hpsa_alloc_cmd_pool(h);
8947fd10 8107 if (rc)
2946e82b 8108 goto clean4; /* irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8109 rc = hpsa_alloc_sg_chain_blocks(h);
8110 if (rc)
2946e82b 8111 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
a08a8471 8112 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 8113 init_waitqueue_head(&h->abort_cmd_wait_queue);
d604f533
WS		 8114 init_waitqueue_head(&h->event_sync_wait_queue);
8115 mutex_init(&h->reset_mutex);
a08a8471 8116 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 8117
8118 pci_set_drvdata(pdev, h);
9a41338e 8119 h->ndevices = 0;
2946e82b 8120
9a41338e 8121 spin_lock_init(&h->devlock);
105a3dbc
RE		 8122 rc = hpsa_put_ctlr_into_performant_mode(h);
8123 if (rc)
2946e82b
RE		 8124 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8125
8126 /* hook into SCSI subsystem */
8127 rc = hpsa_scsi_add_host(h);
8128 if (rc)
8129 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
2efa5929
RE		 8130
8131 /* create the resubmit workqueue */
8132 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8133 if (!h->rescan_ctlr_wq) {
8134 rc = -ENOMEM;
8135 goto clean7;
8136 }
8137
8138 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8139 if (!h->resubmit_wq) {
8140 rc = -ENOMEM;
8141 goto clean7; /* aer/h */
8142 }
64670ac8 8143
105a3dbc
RE		 8144 /*
8145 * At this point, the controller is ready to take commands.
64670ac8
SC		 8146 * Now, if reset_devices and the hard reset didn't work, try
8147 * the soft reset and see if that works.
8148 */
8149 if (try_soft_reset) {
8150
8151 /* This is kind of gross. We may or may not get a completion
8152 * from the soft reset command, and if we do, then the value
8153 * from the fifo may or may not be valid. So, we wait 10 secs
8154 * after the reset throwing away any completions we get during
8155 * that time. Unregister the interrupt handler and register
8156 * fake ones to scoop up any residual completions.
8157 */
8158 spin_lock_irqsave(&h->lock, flags);
8159 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8160 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 8161 hpsa_free_irqs(h);
9ee61794 8162 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 8163 hpsa_intx_discard_completions);
8164 if (rc) {
9ee61794
RE		 8165 dev_warn(&h->pdev->dev,
8166 "Failed to request_irq after soft reset.\n");
d498757c 8167 /*
b2ef480c
RE		 8168 * cannot goto clean7 or free_irqs will be called
8169 * again. Instead, do its work
8170 */
8171 hpsa_free_performant_mode(h); /* clean7 */
8172 hpsa_free_sg_chain_blocks(h); /* clean6 */
8173 hpsa_free_cmd_pool(h); /* clean5 */
8174 /*
8175 * skip hpsa_free_irqs(h) clean4 since that
8176 * was just called before request_irqs failed
d498757c
RE		 8177 */
8178 goto clean3;
64670ac8
SC		 8179 }
8180
8181 rc = hpsa_kdump_soft_reset(h);
8182 if (rc)
8183 /* Neither hard nor soft reset worked, we're hosed. */
7ef7323f 8184 goto clean7;
64670ac8
SC		 8185
8186 dev_info(&h->pdev->dev, "Board READY.\n");
8187 dev_info(&h->pdev->dev,
8188 "Waiting for stale completions to drain.\n");
8189 h->access.set_intr_mask(h, HPSA_INTR_ON);
8190 msleep(10000);
8191 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8192
8193 rc = controller_reset_failed(h->cfgtable);
8194 if (rc)
8195 dev_info(&h->pdev->dev,
8196 "Soft reset appears to have failed.\n");
8197
8198 /* since the controller's reset, we have to go back and re-init
8199 * everything. Easiest to just forget what we've done and do it
8200 * all over again.
8201 */
8202 hpsa_undo_allocations_after_kdump_soft_reset(h);
8203 try_soft_reset = 0;
8204 if (rc)
b2ef480c 8205 /* don't goto clean, we already unallocated */
64670ac8
SC		 8206 return -ENODEV;
8207
8208 goto reinit_after_soft_reset;
8209 }
edd16368 8210
105a3dbc
RE		 8211 /* Enable Accelerated IO path at driver layer */
8212 h->acciopath_status = 1;
da0697bd 8213
e863d68e 8214
edd16368
SC		 8215 /* Turn the interrupts on so we can service requests */
8216 h->access.set_intr_mask(h, HPSA_INTR_ON);
8217
339b2b14 8218 hpsa_hba_inquiry(h);
8a98db73
SC		 8219
8220 /* Monitor the controller for firmware lockups */
8221 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8222 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8223 schedule_delayed_work(&h->monitor_ctlr_work,
8224 h->heartbeat_sample_interval);
6636e7f4
DB		 8225 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8226 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8227 h->heartbeat_sample_interval);
88bf6d62 8228 return 0;
edd16368 8229
2946e82b 8230clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8231 hpsa_free_performant_mode(h);
8232 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8233clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
33a2ffce 8234 hpsa_free_sg_chain_blocks(h);
2946e82b 8235clean5: /* cmd, irq, shost, pci, lu, aer/h */
2e9d1b36 8236 hpsa_free_cmd_pool(h);
2946e82b 8237clean4: /* irq, shost, pci, lu, aer/h */
ec501a18 8238 hpsa_free_irqs(h);
2946e82b
RE		 8239clean3: /* shost, pci, lu, aer/h */
8240 scsi_host_put(h->scsi_host);
8241 h->scsi_host = NULL;
8242clean2_5: /* pci, lu, aer/h */
195f2c65 8243 hpsa_free_pci_init(h);
2946e82b 8244clean2: /* lu, aer/h */
105a3dbc
RE		 8245 if (h->lockup_detected) {
8246 free_percpu(h->lockup_detected);
8247 h->lockup_detected = NULL;
8248 }
8249clean1: /* wq/aer/h */
8250 if (h->resubmit_wq) {
080ef1cc 8251 destroy_workqueue(h->resubmit_wq);
105a3dbc
RE		 8252 h->resubmit_wq = NULL;
8253 }
8254 if (h->rescan_ctlr_wq) {
6636e7f4 8255 destroy_workqueue(h->rescan_ctlr_wq);
105a3dbc
RE		 8256 h->rescan_ctlr_wq = NULL;
8257 }
edd16368 8258 kfree(h);
ecd9aad4 8259 return rc;
edd16368
SC		 8260}
8261
8262static void hpsa_flush_cache(struct ctlr_info *h)
8263{
8264 char *flush_buf;
8265 struct CommandList *c;
25163bd5 8266 int rc;
702890e3 8267
094963da 8268 if (unlikely(lockup_detected(h)))
702890e3 8269 return;
edd16368
SC		 8270 flush_buf = kzalloc(4, GFP_KERNEL);
8271 if (!flush_buf)
8272 return;
8273
45fcb86e 8274 c = cmd_alloc(h);
bf43caf3 8275
a2dac136
SC		 8276 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8277 RAID_CTLR_LUNID, TYPE_CMD)) {
8278 goto out;
8279 }
25163bd5
WS		 8280 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8281 PCI_DMA_TODEVICE, NO_TIMEOUT);
8282 if (rc)
8283 goto out;
edd16368 8284 if (c->err_info->CommandStatus != 0)
a2dac136 8285out:
edd16368
SC		 8286 dev_warn(&h->pdev->dev,
8287 "error flushing cache on controller\n");
45fcb86e 8288 cmd_free(h, c);
edd16368
SC		 8289 kfree(flush_buf);
8290}
8291
8292static void hpsa_shutdown(struct pci_dev *pdev)
8293{
8294 struct ctlr_info *h;
8295
8296 h = pci_get_drvdata(pdev);
8297 /* Turn board interrupts off and send the flush cache command
8298 * sendcmd will turn off interrupt, and send the flush...
8299 * To write all data in the battery backed cache to disks
8300 */
8301 hpsa_flush_cache(h);
8302 h->access.set_intr_mask(h, HPSA_INTR_OFF);
105a3dbc 8303 hpsa_free_irqs(h); /* init_one 4 */
cc64c817 8304 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 8305}
8306
6f039790 8307static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 8308{
8309 int i;
8310
105a3dbc 8311 for (i = 0; i < h->ndevices; i++) {
55e14e76 8312 kfree(h->dev[i]);
105a3dbc
RE		 8313 h->dev[i] = NULL;
8314 }
55e14e76
SC		 8315}
8316
6f039790 8317static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 8318{
8319 struct ctlr_info *h;
8a98db73 8320 unsigned long flags;
edd16368
SC		 8321
8322 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 8323 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 8324 return;
8325 }
8326 h = pci_get_drvdata(pdev);
8a98db73
SC		 8327
8328 /* Get rid of any controller monitoring work items */
8329 spin_lock_irqsave(&h->lock, flags);
8330 h->remove_in_progress = 1;
8a98db73 8331 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 8332 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8333 cancel_delayed_work_sync(&h->rescan_ctlr_work);
8334 destroy_workqueue(h->rescan_ctlr_wq);
8335 destroy_workqueue(h->resubmit_wq);
cc64c817 8336
2d041306
DB		 8337 /*
8338 * Call before disabling interrupts.
8339 * scsi_remove_host can trigger I/O operations especially
8340 * when multipath is enabled. There can be SYNCHRONIZE CACHE
8341 * operations which cannot complete and will hang the system.
8342 */
8343 if (h->scsi_host)
8344 scsi_remove_host(h->scsi_host); /* init_one 8 */
105a3dbc 8345 /* includes hpsa_free_irqs - init_one 4 */
195f2c65 8346 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 8347 hpsa_shutdown(pdev);
cc64c817 8348
105a3dbc
RE		 8349 hpsa_free_device_info(h); /* scan */
8350
2946e82b
RE		 8351 kfree(h->hba_inquiry_data); /* init_one 10 */
8352 h->hba_inquiry_data = NULL; /* init_one 10 */
2946e82b 8353 hpsa_free_ioaccel2_sg_chain_blocks(h);
105a3dbc
RE		 8354 hpsa_free_performant_mode(h); /* init_one 7 */
8355 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8356 hpsa_free_cmd_pool(h); /* init_one 5 */
8357
8358 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
195f2c65 8359
2946e82b
RE		 8360 scsi_host_put(h->scsi_host); /* init_one 3 */
8361 h->scsi_host = NULL; /* init_one 3 */
8362
195f2c65 8363 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
2946e82b 8364 hpsa_free_pci_init(h); /* init_one 2.5 */
195f2c65 8365
105a3dbc
RE		 8366 free_percpu(h->lockup_detected); /* init_one 2 */
8367 h->lockup_detected = NULL; /* init_one 2 */
8368 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
8369 kfree(h); /* init_one 1 */
edd16368
SC		 8370}
8371
8372static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8373 __attribute__((unused)) pm_message_t state)
8374{
8375 return -ENOSYS;
8376}
8377
8378static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8379{
8380 return -ENOSYS;
8381}
8382
8383static struct pci_driver hpsa_pci_driver = {
f79cfec6 8384 .name = HPSA,
edd16368 8385 .probe = hpsa_init_one,
6f039790 8386 .remove = hpsa_remove_one,
edd16368
SC		 8387 .id_table = hpsa_pci_device_id, /* id_table */
8388 .shutdown = hpsa_shutdown,
8389 .suspend = hpsa_suspend,
8390 .resume = hpsa_resume,
8391};
8392
303932fd
DB		 8393/* Fill in bucket_map[], given nsgs (the max number of
8394 * scatter gather elements supported) and bucket[],
8395 * which is an array of 8 integers. The bucket[] array
8396 * contains 8 different DMA transfer sizes (in 16
8397 * byte increments) which the controller uses to fetch
8398 * commands. This function fills in bucket_map[], which
8399 * maps a given number of scatter gather elements to one of
8400 * the 8 DMA transfer sizes. The point of it is to allow the
8401 * controller to only do as much DMA as needed to fetch the
8402 * command, with the DMA transfer size encoded in the lower
8403 * bits of the command address.
8404 */
8405static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 8406 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 8407{
8408 int i, j, b, size;
8409
303932fd
DB		 8410 /* Note, bucket_map must have nsgs+1 entries. */
8411 for (i = 0; i <= nsgs; i++) {
8412 /* Compute size of a command with i SG entries */
e1f7de0c 8413 size = i + min_blocks;
303932fd
DB		 8414 b = num_buckets; /* Assume the biggest bucket */
8415 /* Find the bucket that is just big enough */
e1f7de0c 8416 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 8417 if (bucket[j] >= size) {
8418 b = j;
8419 break;
8420 }
8421 }
8422 /* for a command with i SG entries, use bucket b. */
8423 bucket_map[i] = b;
8424 }
8425}
8426
105a3dbc
RE		 8427/*
8428 * return -ENODEV on err, 0 on success (or no action)
8429 * allocates numerous items that must be freed later
8430 */
c706a795 8431static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 8432{
6c311b57
SC		 8433 int i;
8434 unsigned long register_value;
e1f7de0c
MG		 8435 unsigned long transMethod = CFGTBL_Trans_Performant |
8436 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 8437 CFGTBL_Trans_enable_directed_msix |
8438 (trans_support & (CFGTBL_Trans_io_accel1 |
8439 CFGTBL_Trans_io_accel2));
e1f7de0c 8440 struct access_method access = SA5_performant_access;
def342bd
SC		 8441
8442 /* This is a bit complicated. There are 8 registers on
8443 * the controller which we write to to tell it 8 different
8444 * sizes of commands which there may be. It's a way of
8445 * reducing the DMA done to fetch each command. Encoded into
8446 * each command's tag are 3 bits which communicate to the controller
8447 * which of the eight sizes that command fits within. The size of
8448 * each command depends on how many scatter gather entries there are.
8449 * Each SG entry requires 16 bytes. The eight registers are programmed
8450 * with the number of 16-byte blocks a command of that size requires.
8451 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 8452 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 8453 * blocks. Note, this only extends to the SG entries contained
8454 * within the command block, and does not extend to chained blocks
8455 * of SG elements. bft[] contains the eight values we write to
8456 * the registers. They are not evenly distributed, but have more
8457 * sizes for small commands, and fewer sizes for larger commands.
8458 */
d66ae08b 8459 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 8460#define MIN_IOACCEL2_BFT_ENTRY 5
8461#define HPSA_IOACCEL2_HEADER_SZ 4
8462 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
8463 13, 14, 15, 16, 17, 18, 19,
8464 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
8465 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
8466 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
8467 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
8468 16 * MIN_IOACCEL2_BFT_ENTRY);
8469 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 8470 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 8471 /* 5 = 1 s/g entry or 4k
8472 * 6 = 2 s/g entry or 8k
8473 * 8 = 4 s/g entry or 16k
8474 * 10 = 6 s/g entry or 24k
8475 */
303932fd 8476
b3a52e79
SC		 8477 /* If the controller supports either ioaccel method then
8478 * we can also use the RAID stack submit path that does not
8479 * perform the superfluous readl() after each command submission.
8480 */
8481 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
8482 access = SA5_performant_access_no_read;
8483
303932fd 8484 /* Controller spec: zero out this buffer. */
072b0518
SC		 8485 for (i = 0; i < h->nreply_queues; i++)
8486 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 8487
d66ae08b
SC		 8488 bft[7] = SG_ENTRIES_IN_CMD + 4;
8489 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 8490 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 8491 for (i = 0; i < 8; i++)
8492 writel(bft[i], &h->transtable->BlockFetch[i]);
8493
8494 /* size of controller ring buffer */
8495 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 8496 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 8497 writel(0, &h->transtable->RepQCtrAddrLow32);
8498 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 8499
8500 for (i = 0; i < h->nreply_queues; i++) {
8501 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 8502 writel(h->reply_queue[i].busaddr,
254f796b
MG		 8503 &h->transtable->RepQAddr[i].lower);
8504 }
8505
b9af4937 8506 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 8507 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
8508 /*
8509 * enable outbound interrupt coalescing in accelerator mode;
8510 */
8511 if (trans_support & CFGTBL_Trans_io_accel1) {
8512 access = SA5_ioaccel_mode1_access;
8513 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8514 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 8515 } else {
8516 if (trans_support & CFGTBL_Trans_io_accel2) {
8517 access = SA5_ioaccel_mode2_access;
8518 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8519 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
8520 }
e1f7de0c 8521 }
303932fd 8522 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8523 if (hpsa_wait_for_mode_change_ack(h)) {
8524 dev_err(&h->pdev->dev,
8525 "performant mode problem - doorbell timeout\n");
8526 return -ENODEV;
8527 }
303932fd
DB		 8528 register_value = readl(&(h->cfgtable->TransportActive));
8529 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 8530 dev_err(&h->pdev->dev,
8531 "performant mode problem - transport not active\n");
c706a795 8532 return -ENODEV;
303932fd 8533 }
960a30e7 8534 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 8535 h->access = access;
8536 h->transMethod = transMethod;
8537
b9af4937
SC		 8538 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
8539 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 8540 return 0;
e1f7de0c 8541
b9af4937
SC		 8542 if (trans_support & CFGTBL_Trans_io_accel1) {
8543 /* Set up I/O accelerator mode */
8544 for (i = 0; i < h->nreply_queues; i++) {
8545 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
8546 h->reply_queue[i].current_entry =
8547 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
8548 }
8549 bft[7] = h->ioaccel_maxsg + 8;
8550 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
8551 h->ioaccel1_blockFetchTable);
e1f7de0c 8552
b9af4937 8553 /* initialize all reply queue entries to unused */
072b0518
SC		 8554 for (i = 0; i < h->nreply_queues; i++)
8555 memset(h->reply_queue[i].head,
8556 (u8) IOACCEL_MODE1_REPLY_UNUSED,
8557 h->reply_queue_size);
e1f7de0c 8558
b9af4937
SC		 8559 /* set all the constant fields in the accelerator command
8560 * frames once at init time to save CPU cycles later.
8561 */
8562 for (i = 0; i < h->nr_cmds; i++) {
8563 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
8564
8565 cp->function = IOACCEL1_FUNCTION_SCSIIO;
8566 cp->err_info = (u32) (h->errinfo_pool_dhandle +
8567 (i * sizeof(struct ErrorInfo)));
8568 cp->err_info_len = sizeof(struct ErrorInfo);
8569 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 8570 cp->host_context_flags =
8571 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 8572 cp->timeout_sec = 0;
8573 cp->ReplyQueue = 0;
50a0decf 8574 cp->tag =
f2405db8 8575 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 8576 cp->host_addr =
8577 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 8578 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 8579 }
8580 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8581 u64 cfg_offset, cfg_base_addr_index;
8582 u32 bft2_offset, cfg_base_addr;
8583 int rc;
8584
8585 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
8586 &cfg_base_addr_index, &cfg_offset);
8587 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
8588 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
8589 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
8590 4, h->ioaccel2_blockFetchTable);
8591 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
8592 BUILD_BUG_ON(offsetof(struct CfgTable,
8593 io_accel_request_size_offset) != 0xb8);
8594 h->ioaccel2_bft2_regs =
8595 remap_pci_mem(pci_resource_start(h->pdev,
8596 cfg_base_addr_index) +
8597 cfg_offset + bft2_offset,
8598 ARRAY_SIZE(bft2) *
8599 sizeof(*h->ioaccel2_bft2_regs));
8600 for (i = 0; i < ARRAY_SIZE(bft2); i++)
8601 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 8602 }
b9af4937 8603 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8604 if (hpsa_wait_for_mode_change_ack(h)) {
8605 dev_err(&h->pdev->dev,
8606 "performant mode problem - enabling ioaccel mode\n");
8607 return -ENODEV;
8608 }
8609 return 0;
e1f7de0c
MG		 8610}
8611
1fb7c98a
RE		 8612/* Free ioaccel1 mode command blocks and block fetch table */
8613static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
8614{
105a3dbc 8615 if (h->ioaccel_cmd_pool) {
1fb7c98a
RE		 8616 pci_free_consistent(h->pdev,
8617 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8618 h->ioaccel_cmd_pool,
8619 h->ioaccel_cmd_pool_dhandle);
105a3dbc
RE		 8620 h->ioaccel_cmd_pool = NULL;
8621 h->ioaccel_cmd_pool_dhandle = 0;
8622 }
1fb7c98a 8623 kfree(h->ioaccel1_blockFetchTable);
105a3dbc 8624 h->ioaccel1_blockFetchTable = NULL;
1fb7c98a
RE		 8625}
8626
d37ffbe4
RE		 8627/* Allocate ioaccel1 mode command blocks and block fetch table */
8628static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 8629{
283b4a9b
SC		 8630 h->ioaccel_maxsg =
8631 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8632 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
8633 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
8634
e1f7de0c
MG		 8635 /* Command structures must be aligned on a 128-byte boundary
8636 * because the 7 lower bits of the address are used by the
8637 * hardware.
8638 */
e1f7de0c
MG		 8639 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
8640 IOACCEL1_COMMANDLIST_ALIGNMENT);
8641 h->ioaccel_cmd_pool =
8642 pci_alloc_consistent(h->pdev,
8643 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8644 &(h->ioaccel_cmd_pool_dhandle));
8645
8646 h->ioaccel1_blockFetchTable =
283b4a9b 8647 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 8648 sizeof(u32)), GFP_KERNEL);
8649
8650 if ((h->ioaccel_cmd_pool == NULL) ||
8651 (h->ioaccel1_blockFetchTable == NULL))
8652 goto clean_up;
8653
8654 memset(h->ioaccel_cmd_pool, 0,
8655 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
8656 return 0;
8657
8658clean_up:
1fb7c98a 8659 hpsa_free_ioaccel1_cmd_and_bft(h);
2dd02d74 8660 return -ENOMEM;
6c311b57
SC		 8661}
8662
1fb7c98a
RE		 8663/* Free ioaccel2 mode command blocks and block fetch table */
8664static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
8665{
d9a729f3
WS		 8666 hpsa_free_ioaccel2_sg_chain_blocks(h);
8667
105a3dbc 8668 if (h->ioaccel2_cmd_pool) {
1fb7c98a
RE		 8669 pci_free_consistent(h->pdev,
8670 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8671 h->ioaccel2_cmd_pool,
8672 h->ioaccel2_cmd_pool_dhandle);
105a3dbc
RE		 8673 h->ioaccel2_cmd_pool = NULL;
8674 h->ioaccel2_cmd_pool_dhandle = 0;
8675 }
1fb7c98a 8676 kfree(h->ioaccel2_blockFetchTable);
105a3dbc 8677 h->ioaccel2_blockFetchTable = NULL;
1fb7c98a
RE		 8678}
8679
d37ffbe4
RE		 8680/* Allocate ioaccel2 mode command blocks and block fetch table */
8681static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 8682{
d9a729f3
WS		 8683 int rc;
8684
aca9012a
SC		 8685 /* Allocate ioaccel2 mode command blocks and block fetch table */
8686
8687 h->ioaccel_maxsg =
8688 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8689 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
8690 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
8691
aca9012a
SC		 8692 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
8693 IOACCEL2_COMMANDLIST_ALIGNMENT);
8694 h->ioaccel2_cmd_pool =
8695 pci_alloc_consistent(h->pdev,
8696 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8697 &(h->ioaccel2_cmd_pool_dhandle));
8698
8699 h->ioaccel2_blockFetchTable =
8700 kmalloc(((h->ioaccel_maxsg + 1) *
8701 sizeof(u32)), GFP_KERNEL);
8702
8703 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 8704 (h->ioaccel2_blockFetchTable == NULL)) {
8705 rc = -ENOMEM;
8706 goto clean_up;
8707 }
8708
8709 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
8710 if (rc)
aca9012a
SC		 8711 goto clean_up;
8712
8713 memset(h->ioaccel2_cmd_pool, 0,
8714 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
8715 return 0;
8716
8717clean_up:
1fb7c98a 8718 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 8719 return rc;
aca9012a
SC		 8720}
8721
105a3dbc
RE		 8722/* Free items allocated by hpsa_put_ctlr_into_performant_mode */
8723static void hpsa_free_performant_mode(struct ctlr_info *h)
8724{
8725 kfree(h->blockFetchTable);
8726 h->blockFetchTable = NULL;
8727 hpsa_free_reply_queues(h);
8728 hpsa_free_ioaccel1_cmd_and_bft(h);
8729 hpsa_free_ioaccel2_cmd_and_bft(h);
8730}
8731
8732/* return -ENODEV on error, 0 on success (or no action)
8733 * allocates numerous items that must be freed later
8734 */
8735static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 8736{
8737 u32 trans_support;
e1f7de0c
MG		 8738 unsigned long transMethod = CFGTBL_Trans_Performant |
8739 CFGTBL_Trans_use_short_tags;
105a3dbc 8740 int i, rc;
6c311b57 8741
02ec19c8 8742 if (hpsa_simple_mode)
105a3dbc 8743 return 0;
02ec19c8 8744
67c99a72 8745 trans_support = readl(&(h->cfgtable->TransportSupport));
8746 if (!(trans_support & PERFORMANT_MODE))
105a3dbc 8747 return 0;
67c99a72 8748
e1f7de0c
MG		 8749 /* Check for I/O accelerator mode support */
8750 if (trans_support & CFGTBL_Trans_io_accel1) {
8751 transMethod |= CFGTBL_Trans_io_accel1 |
8752 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8753 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
8754 if (rc)
8755 return rc;
8756 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8757 transMethod |= CFGTBL_Trans_io_accel2 |
aca9012a 8758 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8759 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
8760 if (rc)
8761 return rc;
e1f7de0c
MG		 8762 }
8763
eee0f03a 8764 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 8765 hpsa_get_max_perf_mode_cmds(h);
6c311b57 8766 /* Performant mode ring buffer and supporting data structures */
072b0518 8767 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 8768
254f796b 8769 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 8770 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
8771 h->reply_queue_size,
8772 &(h->reply_queue[i].busaddr));
105a3dbc
RE		 8773 if (!h->reply_queue[i].head) {
8774 rc = -ENOMEM;
8775 goto clean1; /* rq, ioaccel */
8776 }
254f796b
MG		 8777 h->reply_queue[i].size = h->max_commands;
8778 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
8779 h->reply_queue[i].current_entry = 0;
8780 }
8781
6c311b57 8782 /* Need a block fetch table for performant mode */
d66ae08b 8783 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 8784 sizeof(u32)), GFP_KERNEL);
105a3dbc
RE		 8785 if (!h->blockFetchTable) {
8786 rc = -ENOMEM;
8787 goto clean1; /* rq, ioaccel */
8788 }
6c311b57 8789
105a3dbc
RE		 8790 rc = hpsa_enter_performant_mode(h, trans_support);
8791 if (rc)
8792 goto clean2; /* bft, rq, ioaccel */
8793 return 0;
303932fd 8794
105a3dbc 8795clean2: /* bft, rq, ioaccel */
303932fd 8796 kfree(h->blockFetchTable);
105a3dbc
RE		 8797 h->blockFetchTable = NULL;
8798clean1: /* rq, ioaccel */
8799 hpsa_free_reply_queues(h);
8800 hpsa_free_ioaccel1_cmd_and_bft(h);
8801 hpsa_free_ioaccel2_cmd_and_bft(h);
8802 return rc;
303932fd
DB		 8803}
8804
23100dd9 8805static int is_accelerated_cmd(struct CommandList *c)
76438d08 8806{
23100dd9
SC		 8807 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
8808}
8809
8810static void hpsa_drain_accel_commands(struct ctlr_info *h)
8811{
8812 struct CommandList *c = NULL;
f2405db8 8813 int i, accel_cmds_out;
281a7fd0 8814 int refcount;
76438d08 8815
f2405db8 8816 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 8817 accel_cmds_out = 0;
f2405db8 8818 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8819 c = h->cmd_pool + i;
281a7fd0
WS		 8820 refcount = atomic_inc_return(&c->refcount);
8821 if (refcount > 1) /* Command is allocated */
8822 accel_cmds_out += is_accelerated_cmd(c);
8823 cmd_free(h, c);
f2405db8 8824 }
23100dd9 8825 if (accel_cmds_out <= 0)
281a7fd0 8826 break;
76438d08
SC		 8827 msleep(100);
8828 } while (1);
8829}
8830
edd16368
SC		 8831/*
8832 * This is it. Register the PCI driver information for the cards we control
8833 * the OS will call our registered routines when it finds one of our cards.
8834 */
8835static int __init hpsa_init(void)
8836{
31468401 8837 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 8838}
8839
8840static void __exit hpsa_cleanup(void)
8841{
8842 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 8843}
8844
e1f7de0c
MG		 8845static void __attribute__((unused)) verify_offsets(void)
8846{
dd0e19f3
ST		 8847#define VERIFY_OFFSET(member, offset) \
8848 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
8849
8850 VERIFY_OFFSET(structure_size, 0);
8851 VERIFY_OFFSET(volume_blk_size, 4);
8852 VERIFY_OFFSET(volume_blk_cnt, 8);
8853 VERIFY_OFFSET(phys_blk_shift, 16);
8854 VERIFY_OFFSET(parity_rotation_shift, 17);
8855 VERIFY_OFFSET(strip_size, 18);
8856 VERIFY_OFFSET(disk_starting_blk, 20);
8857 VERIFY_OFFSET(disk_blk_cnt, 28);
8858 VERIFY_OFFSET(data_disks_per_row, 36);
8859 VERIFY_OFFSET(metadata_disks_per_row, 38);
8860 VERIFY_OFFSET(row_cnt, 40);
8861 VERIFY_OFFSET(layout_map_count, 42);
8862 VERIFY_OFFSET(flags, 44);
8863 VERIFY_OFFSET(dekindex, 46);
8864 /* VERIFY_OFFSET(reserved, 48 */
8865 VERIFY_OFFSET(data, 64);
8866
8867#undef VERIFY_OFFSET
8868
b66cc250
MM		 8869#define VERIFY_OFFSET(member, offset) \
8870 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
8871
8872 VERIFY_OFFSET(IU_type, 0);
8873 VERIFY_OFFSET(direction, 1);
8874 VERIFY_OFFSET(reply_queue, 2);
8875 /* VERIFY_OFFSET(reserved1, 3); */
8876 VERIFY_OFFSET(scsi_nexus, 4);
8877 VERIFY_OFFSET(Tag, 8);
8878 VERIFY_OFFSET(cdb, 16);
8879 VERIFY_OFFSET(cciss_lun, 32);
8880 VERIFY_OFFSET(data_len, 40);
8881 VERIFY_OFFSET(cmd_priority_task_attr, 44);
8882 VERIFY_OFFSET(sg_count, 45);
8883 /* VERIFY_OFFSET(reserved3 */
8884 VERIFY_OFFSET(err_ptr, 48);
8885 VERIFY_OFFSET(err_len, 56);
8886 /* VERIFY_OFFSET(reserved4 */
8887 VERIFY_OFFSET(sg, 64);
8888
8889#undef VERIFY_OFFSET
8890
e1f7de0c
MG		 8891#define VERIFY_OFFSET(member, offset) \
8892 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
8893
8894 VERIFY_OFFSET(dev_handle, 0x00);
8895 VERIFY_OFFSET(reserved1, 0x02);
8896 VERIFY_OFFSET(function, 0x03);
8897 VERIFY_OFFSET(reserved2, 0x04);
8898 VERIFY_OFFSET(err_info, 0x0C);
8899 VERIFY_OFFSET(reserved3, 0x10);
8900 VERIFY_OFFSET(err_info_len, 0x12);
8901 VERIFY_OFFSET(reserved4, 0x13);
8902 VERIFY_OFFSET(sgl_offset, 0x14);
8903 VERIFY_OFFSET(reserved5, 0x15);
8904 VERIFY_OFFSET(transfer_len, 0x1C);
8905 VERIFY_OFFSET(reserved6, 0x20);
8906 VERIFY_OFFSET(io_flags, 0x24);
8907 VERIFY_OFFSET(reserved7, 0x26);
8908 VERIFY_OFFSET(LUN, 0x34);
8909 VERIFY_OFFSET(control, 0x3C);
8910 VERIFY_OFFSET(CDB, 0x40);
8911 VERIFY_OFFSET(reserved8, 0x50);
8912 VERIFY_OFFSET(host_context_flags, 0x60);
8913 VERIFY_OFFSET(timeout_sec, 0x62);
8914 VERIFY_OFFSET(ReplyQueue, 0x64);
8915 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 8916 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 8917 VERIFY_OFFSET(host_addr, 0x70);
8918 VERIFY_OFFSET(CISS_LUN, 0x78);
8919 VERIFY_OFFSET(SG, 0x78 + 8);
8920#undef VERIFY_OFFSET
8921}
8922
edd16368
SC		 8923module_init(hpsa_init);
8924module_exit(hpsa_cleanup);
Linux kernel - Deliverables
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