Commit | Line | Data |
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edd16368 SC |
1 | /* |
2 | * Disk Array driver for HP Smart Array SAS controllers | |
1358f6dc DB |
3 | * Copyright 2014-2015 PMC-Sierra, Inc. |
4 | * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. | |
edd16368 SC |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; version 2 of the License. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
13 | * NON INFRINGEMENT. See the GNU General Public License for more details. | |
14 | * | |
1358f6dc | 15 | * Questions/Comments/Bugfixes to storagedev@pmcs.com |
edd16368 SC |
16 | * |
17 | */ | |
18 | #ifndef HPSA_H | |
19 | #define HPSA_H | |
20 | ||
21 | #include <scsi/scsicam.h> | |
22 | ||
23 | #define IO_OK 0 | |
24 | #define IO_ERROR 1 | |
25 | ||
26 | struct ctlr_info; | |
27 | ||
28 | struct access_method { | |
29 | void (*submit_command)(struct ctlr_info *h, | |
30 | struct CommandList *c); | |
31 | void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); | |
900c5440 | 32 | bool (*intr_pending)(struct ctlr_info *h); |
254f796b | 33 | unsigned long (*command_completed)(struct ctlr_info *h, u8 q); |
edd16368 SC |
34 | }; |
35 | ||
36 | struct hpsa_scsi_dev_t { | |
3ad7de6b | 37 | unsigned int devtype; |
edd16368 SC |
38 | int bus, target, lun; /* as presented to the OS */ |
39 | unsigned char scsi3addr[8]; /* as presented to the HW */ | |
04fa2f44 | 40 | u8 physical_device : 1; |
2a168208 | 41 | u8 expose_device; |
edd16368 SC |
42 | #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" |
43 | unsigned char device_id[16]; /* from inquiry pg. 0x83 */ | |
44 | unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ | |
45 | unsigned char model[16]; /* bytes 16-31 of inquiry data */ | |
edd16368 | 46 | unsigned char raid_level; /* from inquiry page 0xC1 */ |
9846590e | 47 | unsigned char volume_offline; /* discovered via TUR or VPD */ |
03383736 | 48 | u16 queue_depth; /* max queue_depth for this device */ |
d604f533 | 49 | atomic_t reset_cmds_out; /* Count of commands to-be affected */ |
03383736 DB |
50 | atomic_t ioaccel_cmds_out; /* Only used for physical devices |
51 | * counts commands sent to physical | |
52 | * device via "ioaccel" path. | |
53 | */ | |
e1f7de0c | 54 | u32 ioaccel_handle; |
8270b862 JH |
55 | u8 active_path_index; |
56 | u8 path_map; | |
57 | u8 bay; | |
58 | u8 box[8]; | |
59 | u16 phys_connector[8]; | |
283b4a9b SC |
60 | int offload_config; /* I/O accel RAID offload configured */ |
61 | int offload_enabled; /* I/O accel RAID offload enabled */ | |
41ce4c35 | 62 | int offload_to_be_enabled; |
a3144e0b | 63 | int hba_ioaccel_enabled; |
283b4a9b SC |
64 | int offload_to_mirror; /* Send next I/O accelerator RAID |
65 | * offload request to mirror drive | |
66 | */ | |
67 | struct raid_map_data raid_map; /* I/O accelerator RAID map */ | |
68 | ||
03383736 DB |
69 | /* |
70 | * Pointers from logical drive map indices to the phys drives that | |
71 | * make those logical drives. Note, multiple logical drives may | |
72 | * share physical drives. You can have for instance 5 physical | |
73 | * drives with 3 logical drives each using those same 5 physical | |
74 | * disks. We need these pointers for counting i/o's out to physical | |
75 | * devices in order to honor physical device queue depth limits. | |
76 | */ | |
77 | struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES]; | |
d604f533 | 78 | int nphysical_disks; |
9b5c48c2 | 79 | int supports_aborts; |
66749d0d | 80 | int external; /* 1-from external array 0-not <0-unknown */ |
edd16368 SC |
81 | }; |
82 | ||
072b0518 | 83 | struct reply_queue_buffer { |
254f796b MG |
84 | u64 *head; |
85 | size_t size; | |
86 | u8 wraparound; | |
87 | u32 current_entry; | |
072b0518 | 88 | dma_addr_t busaddr; |
254f796b MG |
89 | }; |
90 | ||
316b221a SC |
91 | #pragma pack(1) |
92 | struct bmic_controller_parameters { | |
93 | u8 led_flags; | |
94 | u8 enable_command_list_verification; | |
95 | u8 backed_out_write_drives; | |
96 | u16 stripes_for_parity; | |
97 | u8 parity_distribution_mode_flags; | |
98 | u16 max_driver_requests; | |
99 | u16 elevator_trend_count; | |
100 | u8 disable_elevator; | |
101 | u8 force_scan_complete; | |
102 | u8 scsi_transfer_mode; | |
103 | u8 force_narrow; | |
104 | u8 rebuild_priority; | |
105 | u8 expand_priority; | |
106 | u8 host_sdb_asic_fix; | |
107 | u8 pdpi_burst_from_host_disabled; | |
108 | char software_name[64]; | |
109 | char hardware_name[32]; | |
110 | u8 bridge_revision; | |
111 | u8 snapshot_priority; | |
112 | u32 os_specific; | |
113 | u8 post_prompt_timeout; | |
114 | u8 automatic_drive_slamming; | |
115 | u8 reserved1; | |
116 | u8 nvram_flags; | |
117 | u8 cache_nvram_flags; | |
118 | u8 drive_config_flags; | |
119 | u16 reserved2; | |
120 | u8 temp_warning_level; | |
121 | u8 temp_shutdown_level; | |
122 | u8 temp_condition_reset; | |
123 | u8 max_coalesce_commands; | |
124 | u32 max_coalesce_delay; | |
125 | u8 orca_password[4]; | |
126 | u8 access_id[16]; | |
127 | u8 reserved[356]; | |
128 | }; | |
129 | #pragma pack() | |
130 | ||
edd16368 SC |
131 | struct ctlr_info { |
132 | int ctlr; | |
133 | char devname[8]; | |
134 | char *product_name; | |
edd16368 | 135 | struct pci_dev *pdev; |
01a02ffc | 136 | u32 board_id; |
edd16368 SC |
137 | void __iomem *vaddr; |
138 | unsigned long paddr; | |
139 | int nr_cmds; /* Number of commands allowed on this controller */ | |
d54c5c24 SC |
140 | #define HPSA_CMDS_RESERVED_FOR_ABORTS 2 |
141 | #define HPSA_CMDS_RESERVED_FOR_DRIVER 1 | |
edd16368 SC |
142 | struct CfgTable __iomem *cfgtable; |
143 | int interrupts_enabled; | |
edd16368 | 144 | int max_commands; |
0cbf768e | 145 | atomic_t commands_outstanding; |
303932fd DB |
146 | # define PERF_MODE_INT 0 |
147 | # define DOORBELL_INT 1 | |
edd16368 SC |
148 | # define SIMPLE_MODE_INT 2 |
149 | # define MEMQ_MODE_INT 3 | |
254f796b | 150 | unsigned int intr[MAX_REPLY_QUEUES]; |
edd16368 SC |
151 | unsigned int msix_vector; |
152 | unsigned int msi_vector; | |
a9a3a273 | 153 | int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ |
edd16368 SC |
154 | struct access_method access; |
155 | ||
156 | /* queue and queue Info */ | |
edd16368 | 157 | unsigned int Qdepth; |
edd16368 SC |
158 | unsigned int maxSG; |
159 | spinlock_t lock; | |
33a2ffce SC |
160 | int maxsgentries; |
161 | u8 max_cmd_sg_entries; | |
162 | int chainsize; | |
163 | struct SGDescriptor **cmd_sg_list; | |
d9a729f3 | 164 | struct ioaccel2_sg_element **ioaccel2_cmd_sg_list; |
edd16368 SC |
165 | |
166 | /* pointers to command and error info pool */ | |
167 | struct CommandList *cmd_pool; | |
168 | dma_addr_t cmd_pool_dhandle; | |
e1f7de0c MG |
169 | struct io_accel1_cmd *ioaccel_cmd_pool; |
170 | dma_addr_t ioaccel_cmd_pool_dhandle; | |
aca9012a SC |
171 | struct io_accel2_cmd *ioaccel2_cmd_pool; |
172 | dma_addr_t ioaccel2_cmd_pool_dhandle; | |
edd16368 SC |
173 | struct ErrorInfo *errinfo_pool; |
174 | dma_addr_t errinfo_pool_dhandle; | |
175 | unsigned long *cmd_pool_bits; | |
a08a8471 SC |
176 | int scan_finished; |
177 | spinlock_t scan_lock; | |
178 | wait_queue_head_t scan_wait_queue; | |
edd16368 SC |
179 | |
180 | struct Scsi_Host *scsi_host; | |
181 | spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ | |
182 | int ndevices; /* number of used elements in .dev[] array. */ | |
cfe5badc | 183 | struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES]; |
303932fd DB |
184 | /* |
185 | * Performant mode tables. | |
186 | */ | |
187 | u32 trans_support; | |
188 | u32 trans_offset; | |
42a91641 | 189 | struct TransTable_struct __iomem *transtable; |
303932fd DB |
190 | unsigned long transMethod; |
191 | ||
0390f0c0 | 192 | /* cap concurrent passthrus at some reasonable maximum */ |
45fcb86e | 193 | #define HPSA_MAX_CONCURRENT_PASSTHRUS (10) |
34f0c627 | 194 | atomic_t passthru_cmds_avail; |
0390f0c0 | 195 | |
303932fd | 196 | /* |
254f796b | 197 | * Performant mode completion buffers |
303932fd | 198 | */ |
072b0518 SC |
199 | size_t reply_queue_size; |
200 | struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES]; | |
254f796b | 201 | u8 nreply_queues; |
303932fd | 202 | u32 *blockFetchTable; |
e1f7de0c | 203 | u32 *ioaccel1_blockFetchTable; |
aca9012a | 204 | u32 *ioaccel2_blockFetchTable; |
42a91641 | 205 | u32 __iomem *ioaccel2_bft2_regs; |
339b2b14 | 206 | unsigned char *hba_inquiry_data; |
283b4a9b SC |
207 | u32 driver_support; |
208 | u32 fw_support; | |
209 | int ioaccel_support; | |
210 | int ioaccel_maxsg; | |
a0c12413 SC |
211 | u64 last_intr_timestamp; |
212 | u32 last_heartbeat; | |
213 | u64 last_heartbeat_timestamp; | |
e85c5974 SC |
214 | u32 heartbeat_sample_interval; |
215 | atomic_t firmware_flash_in_progress; | |
42a91641 | 216 | u32 __percpu *lockup_detected; |
8a98db73 | 217 | struct delayed_work monitor_ctlr_work; |
6636e7f4 | 218 | struct delayed_work rescan_ctlr_work; |
8a98db73 | 219 | int remove_in_progress; |
254f796b MG |
220 | /* Address of h->q[x] is passed to intr handler to know which queue */ |
221 | u8 q[MAX_REPLY_QUEUES]; | |
8b47004a | 222 | char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */ |
75167d2c SC |
223 | u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ |
224 | #define HPSATMF_BITS_SUPPORTED (1 << 0) | |
225 | #define HPSATMF_PHYS_LUN_RESET (1 << 1) | |
226 | #define HPSATMF_PHYS_NEX_RESET (1 << 2) | |
227 | #define HPSATMF_PHYS_TASK_ABORT (1 << 3) | |
228 | #define HPSATMF_PHYS_TSET_ABORT (1 << 4) | |
229 | #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) | |
230 | #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) | |
231 | #define HPSATMF_PHYS_QRY_TASK (1 << 7) | |
232 | #define HPSATMF_PHYS_QRY_TSET (1 << 8) | |
233 | #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) | |
8be986cc | 234 | #define HPSATMF_IOACCEL_ENABLED (1 << 15) |
75167d2c SC |
235 | #define HPSATMF_MASK_SUPPORTED (1 << 16) |
236 | #define HPSATMF_LOG_LUN_RESET (1 << 17) | |
237 | #define HPSATMF_LOG_NEX_RESET (1 << 18) | |
238 | #define HPSATMF_LOG_TASK_ABORT (1 << 19) | |
239 | #define HPSATMF_LOG_TSET_ABORT (1 << 20) | |
240 | #define HPSATMF_LOG_CLEAR_ACA (1 << 21) | |
241 | #define HPSATMF_LOG_CLEAR_TSET (1 << 22) | |
242 | #define HPSATMF_LOG_QRY_TASK (1 << 23) | |
243 | #define HPSATMF_LOG_QRY_TSET (1 << 24) | |
244 | #define HPSATMF_LOG_QRY_ASYNC (1 << 25) | |
76438d08 | 245 | u32 events; |
faff6ee0 SC |
246 | #define CTLR_STATE_CHANGE_EVENT (1 << 0) |
247 | #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1) | |
248 | #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4) | |
249 | #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5) | |
250 | #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6) | |
251 | #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30) | |
252 | #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31) | |
253 | ||
254 | #define RESCAN_REQUIRED_EVENT_BITS \ | |
7b2c46ee | 255 | (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \ |
faff6ee0 SC |
256 | CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \ |
257 | CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \ | |
faff6ee0 SC |
258 | CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \ |
259 | CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE) | |
9846590e SC |
260 | spinlock_t offline_device_lock; |
261 | struct list_head offline_device_list; | |
da0697bd | 262 | int acciopath_status; |
853633e8 | 263 | int drv_req_rescan; |
2ba8bfc8 | 264 | int raid_offload_debug; |
9b5c48c2 | 265 | int needs_abort_tags_swizzled; |
080ef1cc | 266 | struct workqueue_struct *resubmit_wq; |
6636e7f4 | 267 | struct workqueue_struct *rescan_ctlr_wq; |
9b5c48c2 SC |
268 | atomic_t abort_cmds_available; |
269 | wait_queue_head_t abort_cmd_wait_queue; | |
d604f533 WS |
270 | wait_queue_head_t event_sync_wait_queue; |
271 | struct mutex reset_mutex; | |
da03ded0 | 272 | u8 reset_in_progress; |
edd16368 | 273 | }; |
9846590e SC |
274 | |
275 | struct offline_device_entry { | |
276 | unsigned char scsi3addr[8]; | |
277 | struct list_head offline_list; | |
278 | }; | |
279 | ||
edd16368 SC |
280 | #define HPSA_ABORT_MSG 0 |
281 | #define HPSA_DEVICE_RESET_MSG 1 | |
64670ac8 SC |
282 | #define HPSA_RESET_TYPE_CONTROLLER 0x00 |
283 | #define HPSA_RESET_TYPE_BUS 0x01 | |
284 | #define HPSA_RESET_TYPE_TARGET 0x03 | |
285 | #define HPSA_RESET_TYPE_LUN 0x04 | |
0b9b7b6e | 286 | #define HPSA_PHYS_TARGET_RESET 0x99 /* not defined by cciss spec */ |
edd16368 | 287 | #define HPSA_MSG_SEND_RETRY_LIMIT 10 |
516fda49 | 288 | #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) |
edd16368 SC |
289 | |
290 | /* Maximum time in seconds driver will wait for command completions | |
291 | * when polling before giving up. | |
292 | */ | |
293 | #define HPSA_MAX_POLL_TIME_SECS (20) | |
294 | ||
295 | /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines | |
296 | * how many times to retry TEST UNIT READY on a device | |
297 | * while waiting for it to become ready before giving up. | |
298 | * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval | |
299 | * between sending TURs while waiting for a device | |
300 | * to become ready. | |
301 | */ | |
302 | #define HPSA_TUR_RETRY_LIMIT (20) | |
303 | #define HPSA_MAX_WAIT_INTERVAL_SECS (30) | |
304 | ||
305 | /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board | |
306 | * to become ready, in seconds, before giving up on it. | |
307 | * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait | |
308 | * between polling the board to see if it is ready, in | |
309 | * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and | |
310 | * HPSA_BOARD_READY_ITERATIONS are derived from those. | |
311 | */ | |
312 | #define HPSA_BOARD_READY_WAIT_SECS (120) | |
2ed7127b | 313 | #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) |
edd16368 SC |
314 | #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) |
315 | #define HPSA_BOARD_READY_POLL_INTERVAL \ | |
316 | ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) | |
317 | #define HPSA_BOARD_READY_ITERATIONS \ | |
318 | ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ | |
319 | HPSA_BOARD_READY_POLL_INTERVAL_MSECS) | |
fe5389c8 SC |
320 | #define HPSA_BOARD_NOT_READY_ITERATIONS \ |
321 | ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ | |
322 | HPSA_BOARD_READY_POLL_INTERVAL_MSECS) | |
edd16368 SC |
323 | #define HPSA_POST_RESET_PAUSE_MSECS (3000) |
324 | #define HPSA_POST_RESET_NOOP_RETRIES (12) | |
325 | ||
326 | /* Defining the diffent access_menthods */ | |
327 | /* | |
328 | * Memory mapped FIFO interface (SMART 53xx cards) | |
329 | */ | |
330 | #define SA5_DOORBELL 0x20 | |
331 | #define SA5_REQUEST_PORT_OFFSET 0x40 | |
281a7fd0 WS |
332 | #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0 |
333 | #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4 | |
edd16368 SC |
334 | #define SA5_REPLY_INTR_MASK_OFFSET 0x34 |
335 | #define SA5_REPLY_PORT_OFFSET 0x44 | |
336 | #define SA5_INTR_STATUS 0x30 | |
337 | #define SA5_SCRATCHPAD_OFFSET 0xB0 | |
338 | ||
339 | #define SA5_CTCFG_OFFSET 0xB4 | |
340 | #define SA5_CTMEM_OFFSET 0xB8 | |
341 | ||
342 | #define SA5_INTR_OFF 0x08 | |
343 | #define SA5B_INTR_OFF 0x04 | |
344 | #define SA5_INTR_PENDING 0x08 | |
345 | #define SA5B_INTR_PENDING 0x04 | |
346 | #define FIFO_EMPTY 0xffffffff | |
347 | #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ | |
348 | ||
349 | #define HPSA_ERROR_BIT 0x02 | |
edd16368 | 350 | |
303932fd DB |
351 | /* Performant mode flags */ |
352 | #define SA5_PERF_INTR_PENDING 0x04 | |
353 | #define SA5_PERF_INTR_OFF 0x05 | |
354 | #define SA5_OUTDB_STATUS_PERF_BIT 0x01 | |
355 | #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 | |
356 | #define SA5_OUTDB_CLEAR 0xA0 | |
357 | #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 | |
358 | #define SA5_OUTDB_STATUS 0x9C | |
359 | ||
360 | ||
edd16368 SC |
361 | #define HPSA_INTR_ON 1 |
362 | #define HPSA_INTR_OFF 0 | |
b66cc250 MM |
363 | |
364 | /* | |
365 | * Inbound Post Queue offsets for IO Accelerator Mode 2 | |
366 | */ | |
367 | #define IOACCEL2_INBOUND_POSTQ_32 0x48 | |
368 | #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 | |
369 | #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 | |
370 | ||
c795505a KB |
371 | #define HPSA_PHYSICAL_DEVICE_BUS 0 |
372 | #define HPSA_RAID_VOLUME_BUS 1 | |
373 | #define HPSA_EXTERNAL_RAID_VOLUME_BUS 2 | |
374 | #define HPSA_HBA_BUS 3 | |
375 | ||
edd16368 SC |
376 | /* |
377 | Send the command to the hardware | |
378 | */ | |
379 | static void SA5_submit_command(struct ctlr_info *h, | |
380 | struct CommandList *c) | |
381 | { | |
edd16368 | 382 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); |
fec62c36 | 383 | (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); |
edd16368 SC |
384 | } |
385 | ||
b3a52e79 SC |
386 | static void SA5_submit_command_no_read(struct ctlr_info *h, |
387 | struct CommandList *c) | |
388 | { | |
389 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); | |
390 | } | |
391 | ||
c349775e ST |
392 | static void SA5_submit_command_ioaccel2(struct ctlr_info *h, |
393 | struct CommandList *c) | |
394 | { | |
c05e8866 | 395 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); |
c349775e ST |
396 | } |
397 | ||
edd16368 SC |
398 | /* |
399 | * This card is the opposite of the other cards. | |
400 | * 0 turns interrupts on... | |
401 | * 0x08 turns them off... | |
402 | */ | |
403 | static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) | |
404 | { | |
405 | if (val) { /* Turn interrupts on */ | |
406 | h->interrupts_enabled = 1; | |
407 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
8cd21da7 | 408 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
edd16368 SC |
409 | } else { /* Turn them off */ |
410 | h->interrupts_enabled = 0; | |
411 | writel(SA5_INTR_OFF, | |
412 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
8cd21da7 | 413 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
edd16368 SC |
414 | } |
415 | } | |
303932fd DB |
416 | |
417 | static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) | |
418 | { | |
419 | if (val) { /* turn on interrupts */ | |
420 | h->interrupts_enabled = 1; | |
421 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
8cd21da7 | 422 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
303932fd DB |
423 | } else { |
424 | h->interrupts_enabled = 0; | |
425 | writel(SA5_PERF_INTR_OFF, | |
426 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
8cd21da7 | 427 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
303932fd DB |
428 | } |
429 | } | |
430 | ||
254f796b | 431 | static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) |
303932fd | 432 | { |
072b0518 | 433 | struct reply_queue_buffer *rq = &h->reply_queue[q]; |
0cbf768e | 434 | unsigned long register_value = FIFO_EMPTY; |
303932fd | 435 | |
303932fd | 436 | /* msi auto clears the interrupt pending bit. */ |
bee266a6 | 437 | if (unlikely(!(h->msi_vector || h->msix_vector))) { |
2c17d2da SC |
438 | /* flush the controller write of the reply queue by reading |
439 | * outbound doorbell status register. | |
440 | */ | |
bee266a6 | 441 | (void) readl(h->vaddr + SA5_OUTDB_STATUS); |
303932fd DB |
442 | writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); |
443 | /* Do a read in order to flush the write to the controller | |
444 | * (as per spec.) | |
445 | */ | |
bee266a6 | 446 | (void) readl(h->vaddr + SA5_OUTDB_STATUS); |
303932fd DB |
447 | } |
448 | ||
bee266a6 | 449 | if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) { |
254f796b MG |
450 | register_value = rq->head[rq->current_entry]; |
451 | rq->current_entry++; | |
0cbf768e | 452 | atomic_dec(&h->commands_outstanding); |
303932fd DB |
453 | } else { |
454 | register_value = FIFO_EMPTY; | |
455 | } | |
456 | /* Check for wraparound */ | |
254f796b MG |
457 | if (rq->current_entry == h->max_commands) { |
458 | rq->current_entry = 0; | |
459 | rq->wraparound ^= 1; | |
303932fd | 460 | } |
303932fd DB |
461 | return register_value; |
462 | } | |
463 | ||
edd16368 SC |
464 | /* |
465 | * returns value read from hardware. | |
466 | * returns FIFO_EMPTY if there is nothing to read | |
467 | */ | |
254f796b MG |
468 | static unsigned long SA5_completed(struct ctlr_info *h, |
469 | __attribute__((unused)) u8 q) | |
edd16368 SC |
470 | { |
471 | unsigned long register_value | |
472 | = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); | |
473 | ||
0cbf768e SC |
474 | if (register_value != FIFO_EMPTY) |
475 | atomic_dec(&h->commands_outstanding); | |
edd16368 SC |
476 | |
477 | #ifdef HPSA_DEBUG | |
478 | if (register_value != FIFO_EMPTY) | |
84ca0be2 | 479 | dev_dbg(&h->pdev->dev, "Read %lx back from board\n", |
edd16368 SC |
480 | register_value); |
481 | else | |
f79cfec6 | 482 | dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); |
edd16368 SC |
483 | #endif |
484 | ||
485 | return register_value; | |
486 | } | |
487 | /* | |
488 | * Returns true if an interrupt is pending.. | |
489 | */ | |
900c5440 | 490 | static bool SA5_intr_pending(struct ctlr_info *h) |
edd16368 SC |
491 | { |
492 | unsigned long register_value = | |
493 | readl(h->vaddr + SA5_INTR_STATUS); | |
900c5440 | 494 | return register_value & SA5_INTR_PENDING; |
edd16368 SC |
495 | } |
496 | ||
303932fd DB |
497 | static bool SA5_performant_intr_pending(struct ctlr_info *h) |
498 | { | |
499 | unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); | |
500 | ||
501 | if (!register_value) | |
502 | return false; | |
503 | ||
303932fd DB |
504 | /* Read outbound doorbell to flush */ |
505 | register_value = readl(h->vaddr + SA5_OUTDB_STATUS); | |
506 | return register_value & SA5_OUTDB_STATUS_PERF_BIT; | |
507 | } | |
edd16368 | 508 | |
e1f7de0c MG |
509 | #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100 |
510 | ||
511 | static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) | |
512 | { | |
513 | unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); | |
514 | ||
515 | return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ? | |
516 | true : false; | |
517 | } | |
518 | ||
519 | #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 | |
520 | #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 | |
521 | #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC | |
522 | #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL | |
523 | ||
283b4a9b | 524 | static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) |
e1f7de0c MG |
525 | { |
526 | u64 register_value; | |
072b0518 | 527 | struct reply_queue_buffer *rq = &h->reply_queue[q]; |
e1f7de0c MG |
528 | |
529 | BUG_ON(q >= h->nreply_queues); | |
530 | ||
531 | register_value = rq->head[rq->current_entry]; | |
532 | if (register_value != IOACCEL_MODE1_REPLY_UNUSED) { | |
533 | rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED; | |
534 | if (++rq->current_entry == rq->size) | |
535 | rq->current_entry = 0; | |
283b4a9b SC |
536 | /* |
537 | * @todo | |
538 | * | |
539 | * Don't really need to write the new index after each command, | |
540 | * but with current driver design this is easiest. | |
541 | */ | |
542 | wmb(); | |
543 | writel((q << 24) | rq->current_entry, h->vaddr + | |
544 | IOACCEL_MODE1_CONSUMER_INDEX); | |
0cbf768e | 545 | atomic_dec(&h->commands_outstanding); |
e1f7de0c MG |
546 | } |
547 | return (unsigned long) register_value; | |
548 | } | |
549 | ||
edd16368 SC |
550 | static struct access_method SA5_access = { |
551 | SA5_submit_command, | |
552 | SA5_intr_mask, | |
edd16368 SC |
553 | SA5_intr_pending, |
554 | SA5_completed, | |
555 | }; | |
556 | ||
e1f7de0c MG |
557 | static struct access_method SA5_ioaccel_mode1_access = { |
558 | SA5_submit_command, | |
559 | SA5_performant_intr_mask, | |
e1f7de0c MG |
560 | SA5_ioaccel_mode1_intr_pending, |
561 | SA5_ioaccel_mode1_completed, | |
562 | }; | |
563 | ||
c349775e ST |
564 | static struct access_method SA5_ioaccel_mode2_access = { |
565 | SA5_submit_command_ioaccel2, | |
566 | SA5_performant_intr_mask, | |
c349775e ST |
567 | SA5_performant_intr_pending, |
568 | SA5_performant_completed, | |
569 | }; | |
570 | ||
303932fd DB |
571 | static struct access_method SA5_performant_access = { |
572 | SA5_submit_command, | |
573 | SA5_performant_intr_mask, | |
303932fd DB |
574 | SA5_performant_intr_pending, |
575 | SA5_performant_completed, | |
576 | }; | |
577 | ||
b3a52e79 SC |
578 | static struct access_method SA5_performant_access_no_read = { |
579 | SA5_submit_command_no_read, | |
580 | SA5_performant_intr_mask, | |
b3a52e79 SC |
581 | SA5_performant_intr_pending, |
582 | SA5_performant_completed, | |
583 | }; | |
584 | ||
edd16368 | 585 | struct board_type { |
01a02ffc | 586 | u32 board_id; |
edd16368 SC |
587 | char *product_name; |
588 | struct access_method *access; | |
589 | }; | |
590 | ||
edd16368 SC |
591 | #endif /* HPSA_H */ |
592 |