[deliverable/linux.git] / drivers / scsi / hpsa.h

/*
 *    Disk Array driver for HP Smart Array SAS controllers
 *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; version 2 of the License.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *    NON INFRINGEMENT.  See the GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
 *
 */
#ifndef HPSA_H
#define HPSA_H

#include <scsi/scsicam.h>

#define IO_OK		0
#define IO_ERROR	1

struct ctlr_info;

struct access_method {
	void (*submit_command)(struct ctlr_info *h,
		struct CommandList *c);
	void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
	unsigned long (*fifo_full)(struct ctlr_info *h);
	bool (*intr_pending)(struct ctlr_info *h);
	unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
};

struct hpsa_scsi_dev_t {
	int devtype;
	int bus, target, lun;		/* as presented to the OS */
	unsigned char scsi3addr[8];	/* as presented to the HW */
#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
	unsigned char device_id[16];    /* from inquiry pg. 0x83 */
	unsigned char vendor[8];        /* bytes 8-15 of inquiry data */
	unsigned char model[16];        /* bytes 16-31 of inquiry data */
	unsigned char raid_level;	/* from inquiry page 0xC1 */
};

struct reply_pool {
	u64 *head;
	size_t size;
	u8 wraparound;
	u32 current_entry;
};

struct ctlr_info {
	int	ctlr;
	char	devname[8];
	char    *product_name;
	struct pci_dev *pdev;
	u32	board_id;
	void __iomem *vaddr;
	unsigned long paddr;
	int 	nr_cmds; /* Number of commands allowed on this controller */
	struct CfgTable __iomem *cfgtable;
	int	interrupts_enabled;
	int	major;
	int 	max_commands;
	int	commands_outstanding;
	int 	max_outstanding; /* Debug */
	int	usage_count;  /* number of opens all all minor devices */
#	define PERF_MODE_INT	0
#	define DOORBELL_INT	1
#	define SIMPLE_MODE_INT	2
#	define MEMQ_MODE_INT	3
	unsigned int intr[MAX_REPLY_QUEUES];
	unsigned int msix_vector;
	unsigned int msi_vector;
	int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
	struct access_method access;

	/* queue and queue Info */
	struct list_head reqQ;
	struct list_head cmpQ;
	unsigned int Qdepth;
	unsigned int maxSG;
	spinlock_t lock;
	int maxsgentries;
	u8 max_cmd_sg_entries;
	int chainsize;
	struct SGDescriptor **cmd_sg_list;

	/* pointers to command and error info pool */
	struct CommandList 	*cmd_pool;
	dma_addr_t		cmd_pool_dhandle;
	struct ErrorInfo 	*errinfo_pool;
	dma_addr_t		errinfo_pool_dhandle;
	unsigned long  		*cmd_pool_bits;
	int			scan_finished;
	spinlock_t		scan_lock;
	wait_queue_head_t	scan_wait_queue;

	struct Scsi_Host *scsi_host;
	spinlock_t devlock; /* to protect hba[ctlr]->dev[];  */
	int ndevices; /* number of used elements in .dev[] array. */
	struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
	/*
	 * Performant mode tables.
	 */
	u32 trans_support;
	u32 trans_offset;
	struct TransTable_struct *transtable;
	unsigned long transMethod;

	/* cap concurrent passthrus at some reasonable maximum */
#define HPSA_MAX_CONCURRENT_PASSTHRUS (20)
	spinlock_t passthru_count_lock; /* protects passthru_count */
	int passthru_count;

	/*
	 * Performant mode completion buffers
	 */
	u64 *reply_pool;
	size_t reply_pool_size;
	struct reply_pool reply_queue[MAX_REPLY_QUEUES];
	u8 nreply_queues;
	dma_addr_t reply_pool_dhandle;
	u32 *blockFetchTable;
	unsigned char *hba_inquiry_data;
	u64 last_intr_timestamp;
	u32 last_heartbeat;
	u64 last_heartbeat_timestamp;
	u32 heartbeat_sample_interval;
	atomic_t firmware_flash_in_progress;
	u32 lockup_detected;
	struct list_head lockup_list;
	u32 fifo_recently_full;
	/* Address of h->q[x] is passed to intr handler to know which queue */
	u8 q[MAX_REPLY_QUEUES];
	u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
#define HPSATMF_BITS_SUPPORTED  (1 << 0)
#define HPSATMF_PHYS_LUN_RESET  (1 << 1)
#define HPSATMF_PHYS_NEX_RESET  (1 << 2)
#define HPSATMF_PHYS_TASK_ABORT (1 << 3)
#define HPSATMF_PHYS_TSET_ABORT (1 << 4)
#define HPSATMF_PHYS_CLEAR_ACA  (1 << 5)
#define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
#define HPSATMF_PHYS_QRY_TASK   (1 << 7)
#define HPSATMF_PHYS_QRY_TSET   (1 << 8)
#define HPSATMF_PHYS_QRY_ASYNC  (1 << 9)
#define HPSATMF_MASK_SUPPORTED  (1 << 16)
#define HPSATMF_LOG_LUN_RESET   (1 << 17)
#define HPSATMF_LOG_NEX_RESET   (1 << 18)
#define HPSATMF_LOG_TASK_ABORT  (1 << 19)
#define HPSATMF_LOG_TSET_ABORT  (1 << 20)
#define HPSATMF_LOG_CLEAR_ACA   (1 << 21)
#define HPSATMF_LOG_CLEAR_TSET  (1 << 22)
#define HPSATMF_LOG_QRY_TASK    (1 << 23)
#define HPSATMF_LOG_QRY_TSET    (1 << 24)
#define HPSATMF_LOG_QRY_ASYNC   (1 << 25)
};
#define HPSA_ABORT_MSG 0
#define HPSA_DEVICE_RESET_MSG 1
#define HPSA_RESET_TYPE_CONTROLLER 0x00
#define HPSA_RESET_TYPE_BUS 0x01
#define HPSA_RESET_TYPE_TARGET 0x03
#define HPSA_RESET_TYPE_LUN 0x04
#define HPSA_MSG_SEND_RETRY_LIMIT 10
#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)

/* Maximum time in seconds driver will wait for command completions
 * when polling before giving up.
 */
#define HPSA_MAX_POLL_TIME_SECS (20)

/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
 * how many times to retry TEST UNIT READY on a device
 * while waiting for it to become ready before giving up.
 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
 * between sending TURs while waiting for a device
 * to become ready.
 */
#define HPSA_TUR_RETRY_LIMIT (20)
#define HPSA_MAX_WAIT_INTERVAL_SECS (30)

/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
 * to become ready, in seconds, before giving up on it.
 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
 * between polling the board to see if it is ready, in
 * milliseconds.  HPSA_BOARD_READY_POLL_INTERVAL and
 * HPSA_BOARD_READY_ITERATIONS are derived from those.
 */
#define HPSA_BOARD_READY_WAIT_SECS (120)
#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
#define HPSA_BOARD_READY_POLL_INTERVAL \
	((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
#define HPSA_BOARD_READY_ITERATIONS \
	((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
#define HPSA_BOARD_NOT_READY_ITERATIONS \
	((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
#define HPSA_POST_RESET_PAUSE_MSECS (3000)
#define HPSA_POST_RESET_NOOP_RETRIES (12)

/*  Defining the diffent access_menthods */
/*
 * Memory mapped FIFO interface (SMART 53xx cards)
 */
#define SA5_DOORBELL	0x20
#define SA5_REQUEST_PORT_OFFSET	0x40
#define SA5_REPLY_INTR_MASK_OFFSET	0x34
#define SA5_REPLY_PORT_OFFSET		0x44
#define SA5_INTR_STATUS		0x30
#define SA5_SCRATCHPAD_OFFSET	0xB0

#define SA5_CTCFG_OFFSET	0xB4
#define SA5_CTMEM_OFFSET	0xB8

#define SA5_INTR_OFF		0x08
#define SA5B_INTR_OFF		0x04
#define SA5_INTR_PENDING	0x08
#define SA5B_INTR_PENDING	0x04
#define FIFO_EMPTY		0xffffffff
#define HPSA_FIRMWARE_READY	0xffff0000 /* value in scratchpad register */

#define HPSA_ERROR_BIT		0x02

/* Performant mode flags */
#define SA5_PERF_INTR_PENDING   0x04
#define SA5_PERF_INTR_OFF       0x05
#define SA5_OUTDB_STATUS_PERF_BIT       0x01
#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
#define SA5_OUTDB_CLEAR         0xA0
#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
#define SA5_OUTDB_STATUS        0x9C


#define HPSA_INTR_ON 	1
#define HPSA_INTR_OFF	0
/*
	Send the command to the hardware
*/
static void SA5_submit_command(struct ctlr_info *h,
	struct CommandList *c)
{
	dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
		c->Header.Tag.lower);
	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
}

/*
 *  This card is the opposite of the other cards.
 *   0 turns interrupts on...
 *   0x08 turns them off...
 */
static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
{
	if (val) { /* Turn interrupts on */
		h->interrupts_enabled = 1;
		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	} else { /* Turn them off */
		h->interrupts_enabled = 0;
		writel(SA5_INTR_OFF,
			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	}
}

static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
{
	if (val) { /* turn on interrupts */
		h->interrupts_enabled = 1;
		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	} else {
		h->interrupts_enabled = 0;
		writel(SA5_PERF_INTR_OFF,
			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	}
}

static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
{
	struct reply_pool *rq = &h->reply_queue[q];
	unsigned long flags, register_value = FIFO_EMPTY;

	/* msi auto clears the interrupt pending bit. */
	if (!(h->msi_vector || h->msix_vector)) {
		/* flush the controller write of the reply queue by reading
		 * outbound doorbell status register.
		 */
		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
		/* Do a read in order to flush the write to the controller
		 * (as per spec.)
		 */
		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	}

	if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
		register_value = rq->head[rq->current_entry];
		rq->current_entry++;
		spin_lock_irqsave(&h->lock, flags);
		h->commands_outstanding--;
		spin_unlock_irqrestore(&h->lock, flags);
	} else {
		register_value = FIFO_EMPTY;
	}
	/* Check for wraparound */
	if (rq->current_entry == h->max_commands) {
		rq->current_entry = 0;
		rq->wraparound ^= 1;
	}
	return register_value;
}

/*
 *  Returns true if fifo is full.
 *
 */
static unsigned long SA5_fifo_full(struct ctlr_info *h)
{
	if (h->commands_outstanding >= h->max_commands)
		return 1;
	else
		return 0;

}
/*
 *   returns value read from hardware.
 *     returns FIFO_EMPTY if there is nothing to read
 */
static unsigned long SA5_completed(struct ctlr_info *h,
	__attribute__((unused)) u8 q)
{
	unsigned long register_value
		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
	unsigned long flags;

	if (register_value != FIFO_EMPTY) {
		spin_lock_irqsave(&h->lock, flags);
		h->commands_outstanding--;
		spin_unlock_irqrestore(&h->lock, flags);
	}

#ifdef HPSA_DEBUG
	if (register_value != FIFO_EMPTY)
		dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
			register_value);
	else
		dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
#endif

	return register_value;
}
/*
 *	Returns true if an interrupt is pending..
 */
static bool SA5_intr_pending(struct ctlr_info *h)
{
	unsigned long register_value  =
		readl(h->vaddr + SA5_INTR_STATUS);
	dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
	return register_value & SA5_INTR_PENDING;
}

static bool SA5_performant_intr_pending(struct ctlr_info *h)
{
	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);

	if (!register_value)
		return false;

	if (h->msi_vector || h->msix_vector)
		return true;

	/* Read outbound doorbell to flush */
	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	return register_value & SA5_OUTDB_STATUS_PERF_BIT;
}

static struct access_method SA5_access = {
	SA5_submit_command,
	SA5_intr_mask,
	SA5_fifo_full,
	SA5_intr_pending,
	SA5_completed,
};

static struct access_method SA5_performant_access = {
	SA5_submit_command,
	SA5_performant_intr_mask,
	SA5_fifo_full,
	SA5_performant_intr_pending,
	SA5_performant_completed,
};

struct board_type {
	u32	board_id;
	char	*product_name;
	struct access_method *access;
};

#endif /* HPSA_H */
Commit	Line	Data
edd16368 SC	1	/*
	2	* Disk Array driver for HP Smart Array SAS controllers
	3	* Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; version 2 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	12	* NON INFRINGEMENT. See the GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	17	*
	18	* Questions/Comments/Bugfixes to iss_storagedev@hp.com
	19	*
	20	*/
	21	#ifndef HPSA_H
	22	#define HPSA_H
	23
	24	#include <scsi/scsicam.h>
	25
	26	#define IO_OK 0
	27	#define IO_ERROR 1
	28
	29	struct ctlr_info;
	30
	31	struct access_method {
	32	void (submit_command)(struct ctlr_info h,
	33	struct CommandList *c);
	34	void (set_intr_mask)(struct ctlr_info h, unsigned long val);
	35	unsigned long (fifo_full)(struct ctlr_info h);
900c5440	36	bool (intr_pending)(struct ctlr_info h);
254f796b	37	unsigned long (command_completed)(struct ctlr_info h, u8 q);
edd16368 SC	38	};
	39
	40	struct hpsa_scsi_dev_t {
	41	int devtype;
	42	int bus, target, lun; /* as presented to the OS */
	43	unsigned char scsi3addr[8]; /* as presented to the HW */
	44	#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
	45	unsigned char device_id[16]; /* from inquiry pg. 0x83 */
	46	unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
	47	unsigned char model[16]; /* bytes 16-31 of inquiry data */
edd16368 SC	48	unsigned char raid_level; /* from inquiry page 0xC1 */
	49	};
	50
254f796b MG	51	struct reply_pool {
	52	u64 *head;
	53	size_t size;
	54	u8 wraparound;
	55	u32 current_entry;
	56	};
	57
edd16368 SC	58	struct ctlr_info {
	59	int ctlr;
	60	char devname[8];
	61	char *product_name;
edd16368	62	struct pci_dev *pdev;
01a02ffc	63	u32 board_id;
edd16368 SC	64	void __iomem *vaddr;
	65	unsigned long paddr;
	66	int nr_cmds; /* Number of commands allowed on this controller */
	67	struct CfgTable __iomem *cfgtable;
	68	int interrupts_enabled;
	69	int major;
	70	int max_commands;
	71	int commands_outstanding;
	72	int max_outstanding; /* Debug */
	73	int usage_count; /* number of opens all all minor devices */
303932fd DB	74	# define PERF_MODE_INT 0
303932fd DB	75	# define DOORBELL_INT 1
edd16368 SC	76	# define SIMPLE_MODE_INT 2
edd16368 SC	77	# define MEMQ_MODE_INT 3
254f796b	78	unsigned int intr[MAX_REPLY_QUEUES];
edd16368 SC	79	unsigned int msix_vector;
edd16368 SC	80	unsigned int msi_vector;
a9a3a273	81	int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
edd16368 SC	82	struct access_method access;
	83
	84	/* queue and queue Info */
9e0fc764 SC	85	struct list_head reqQ;
9e0fc764 SC	86	struct list_head cmpQ;
edd16368	87	unsigned int Qdepth;
edd16368 SC	88	unsigned int maxSG;
edd16368 SC	89	spinlock_t lock;
33a2ffce SC	90	int maxsgentries;
	91	u8 max_cmd_sg_entries;
	92	int chainsize;
	93	struct SGDescriptor **cmd_sg_list;
edd16368 SC	94
	95	/* pointers to command and error info pool */
	96	struct CommandList *cmd_pool;
	97	dma_addr_t cmd_pool_dhandle;
	98	struct ErrorInfo *errinfo_pool;
	99	dma_addr_t errinfo_pool_dhandle;
	100	unsigned long *cmd_pool_bits;
a08a8471 SC	101	int scan_finished;
	102	spinlock_t scan_lock;
	103	wait_queue_head_t scan_wait_queue;
edd16368 SC	104
	105	struct Scsi_Host *scsi_host;
	106	spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
	107	int ndevices; /* number of used elements in .dev[] array. */
cfe5badc	108	struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
303932fd DB	109	/*
	110	* Performant mode tables.
	111	*/
	112	u32 trans_support;
	113	u32 trans_offset;
	114	struct TransTable_struct *transtable;
	115	unsigned long transMethod;
	116
0390f0c0 SC	117	/* cap concurrent passthrus at some reasonable maximum */
	118	#define HPSA_MAX_CONCURRENT_PASSTHRUS (20)
	119	spinlock_t passthru_count_lock; /* protects passthru_count */
	120	int passthru_count;
	121
303932fd	122	/*
254f796b	123	* Performant mode completion buffers
303932fd DB	124	*/
303932fd DB	125	u64 *reply_pool;
303932fd	126	size_t reply_pool_size;
254f796b MG	127	struct reply_pool reply_queue[MAX_REPLY_QUEUES];
	128	u8 nreply_queues;
	129	dma_addr_t reply_pool_dhandle;
303932fd	130	u32 *blockFetchTable;
339b2b14	131	unsigned char *hba_inquiry_data;
a0c12413 SC	132	u64 last_intr_timestamp;
	133	u32 last_heartbeat;
	134	u64 last_heartbeat_timestamp;
e85c5974 SC	135	u32 heartbeat_sample_interval;
e85c5974 SC	136	atomic_t firmware_flash_in_progress;
a0c12413 SC	137	u32 lockup_detected;
a0c12413 SC	138	struct list_head lockup_list;
396883e2	139	u32 fifo_recently_full;
254f796b MG	140	/* Address of h->q[x] is passed to intr handler to know which queue */
254f796b MG	141	u8 q[MAX_REPLY_QUEUES];
75167d2c SC	142	u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
	143	#define HPSATMF_BITS_SUPPORTED (1 << 0)
	144	#define HPSATMF_PHYS_LUN_RESET (1 << 1)
	145	#define HPSATMF_PHYS_NEX_RESET (1 << 2)
	146	#define HPSATMF_PHYS_TASK_ABORT (1 << 3)
	147	#define HPSATMF_PHYS_TSET_ABORT (1 << 4)
	148	#define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
	149	#define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
	150	#define HPSATMF_PHYS_QRY_TASK (1 << 7)
	151	#define HPSATMF_PHYS_QRY_TSET (1 << 8)
	152	#define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
	153	#define HPSATMF_MASK_SUPPORTED (1 << 16)
	154	#define HPSATMF_LOG_LUN_RESET (1 << 17)
	155	#define HPSATMF_LOG_NEX_RESET (1 << 18)
	156	#define HPSATMF_LOG_TASK_ABORT (1 << 19)
	157	#define HPSATMF_LOG_TSET_ABORT (1 << 20)
	158	#define HPSATMF_LOG_CLEAR_ACA (1 << 21)
	159	#define HPSATMF_LOG_CLEAR_TSET (1 << 22)
	160	#define HPSATMF_LOG_QRY_TASK (1 << 23)
	161	#define HPSATMF_LOG_QRY_TSET (1 << 24)
	162	#define HPSATMF_LOG_QRY_ASYNC (1 << 25)
edd16368 SC	163	};
	164	#define HPSA_ABORT_MSG 0
	165	#define HPSA_DEVICE_RESET_MSG 1
64670ac8 SC	166	#define HPSA_RESET_TYPE_CONTROLLER 0x00
	167	#define HPSA_RESET_TYPE_BUS 0x01
	168	#define HPSA_RESET_TYPE_TARGET 0x03
	169	#define HPSA_RESET_TYPE_LUN 0x04
edd16368	170	#define HPSA_MSG_SEND_RETRY_LIMIT 10
516fda49	171	#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
edd16368 SC	172
	173	/* Maximum time in seconds driver will wait for command completions
	174	* when polling before giving up.
	175	*/
	176	#define HPSA_MAX_POLL_TIME_SECS (20)
	177
	178	/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
	179	* how many times to retry TEST UNIT READY on a device
	180	* while waiting for it to become ready before giving up.
	181	* HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
	182	* between sending TURs while waiting for a device
	183	* to become ready.
	184	*/
	185	#define HPSA_TUR_RETRY_LIMIT (20)
	186	#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
	187
	188	/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
	189	* to become ready, in seconds, before giving up on it.
	190	* HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
	191	* between polling the board to see if it is ready, in
	192	* milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
	193	* HPSA_BOARD_READY_ITERATIONS are derived from those.
	194	*/
	195	#define HPSA_BOARD_READY_WAIT_SECS (120)
2ed7127b	196	#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
edd16368 SC	197	#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
	198	#define HPSA_BOARD_READY_POLL_INTERVAL \
	199	((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
	200	#define HPSA_BOARD_READY_ITERATIONS \
	201	((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
	202	HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
fe5389c8 SC	203	#define HPSA_BOARD_NOT_READY_ITERATIONS \
	204	((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
	205	HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
edd16368 SC	206	#define HPSA_POST_RESET_PAUSE_MSECS (3000)
	207	#define HPSA_POST_RESET_NOOP_RETRIES (12)
	208
	209	/* Defining the diffent access_menthods */
	210	/*
	211	* Memory mapped FIFO interface (SMART 53xx cards)
	212	*/
	213	#define SA5_DOORBELL 0x20
	214	#define SA5_REQUEST_PORT_OFFSET 0x40
	215	#define SA5_REPLY_INTR_MASK_OFFSET 0x34
	216	#define SA5_REPLY_PORT_OFFSET 0x44
	217	#define SA5_INTR_STATUS 0x30
	218	#define SA5_SCRATCHPAD_OFFSET 0xB0
	219
	220	#define SA5_CTCFG_OFFSET 0xB4
	221	#define SA5_CTMEM_OFFSET 0xB8
	222
	223	#define SA5_INTR_OFF 0x08
	224	#define SA5B_INTR_OFF 0x04
	225	#define SA5_INTR_PENDING 0x08
	226	#define SA5B_INTR_PENDING 0x04
	227	#define FIFO_EMPTY 0xffffffff
	228	#define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
	229
	230	#define HPSA_ERROR_BIT 0x02
edd16368	231
303932fd DB	232	/* Performant mode flags */
	233	#define SA5_PERF_INTR_PENDING 0x04
	234	#define SA5_PERF_INTR_OFF 0x05
	235	#define SA5_OUTDB_STATUS_PERF_BIT 0x01
	236	#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
	237	#define SA5_OUTDB_CLEAR 0xA0
	238	#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
	239	#define SA5_OUTDB_STATUS 0x9C
	240
	241
edd16368 SC	242	#define HPSA_INTR_ON 1
	243	#define HPSA_INTR_OFF 0
	244	/*
	245	Send the command to the hardware
	246	*/
	247	static void SA5_submit_command(struct ctlr_info *h,
	248	struct CommandList *c)
	249	{
303932fd DB	250	dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
303932fd DB	251	c->Header.Tag.lower);
edd16368	252	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
fec62c36	253	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
edd16368 SC	254	}
	255
	256	/*
	257	* This card is the opposite of the other cards.
	258	* 0 turns interrupts on...
	259	* 0x08 turns them off...
	260	*/
	261	static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
	262	{
	263	if (val) { /* Turn interrupts on */
	264	h->interrupts_enabled = 1;
	265	writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	266	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
edd16368 SC	267	} else { /* Turn them off */
	268	h->interrupts_enabled = 0;
	269	writel(SA5_INTR_OFF,
	270	h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	271	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
edd16368 SC	272	}
edd16368 SC	273	}
303932fd DB	274
	275	static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
	276	{
	277	if (val) { /* turn on interrupts */
	278	h->interrupts_enabled = 1;
	279	writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	280	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
303932fd DB	281	} else {
	282	h->interrupts_enabled = 0;
	283	writel(SA5_PERF_INTR_OFF,
	284	h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	285	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
303932fd DB	286	}
	287	}
	288
254f796b	289	static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
303932fd	290	{
254f796b	291	struct reply_pool *rq = &h->reply_queue[q];
e16a33ad	292	unsigned long flags, register_value = FIFO_EMPTY;
303932fd	293
303932fd DB	294	/* msi auto clears the interrupt pending bit. */
303932fd DB	295	if (!(h->msi_vector \|\| h->msix_vector)) {
2c17d2da SC	296	/* flush the controller write of the reply queue by reading
	297	* outbound doorbell status register.
	298	*/
	299	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
303932fd DB	300	writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
	301	/* Do a read in order to flush the write to the controller
	302	* (as per spec.)
	303	*/
	304	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	305	}
	306
254f796b MG	307	if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
	308	register_value = rq->head[rq->current_entry];
	309	rq->current_entry++;
e16a33ad	310	spin_lock_irqsave(&h->lock, flags);
303932fd	311	h->commands_outstanding--;
e16a33ad	312	spin_unlock_irqrestore(&h->lock, flags);
303932fd DB	313	} else {
	314	register_value = FIFO_EMPTY;
	315	}
	316	/* Check for wraparound */
254f796b MG	317	if (rq->current_entry == h->max_commands) {
	318	rq->current_entry = 0;
	319	rq->wraparound ^= 1;
303932fd	320	}
303932fd DB	321	return register_value;
	322	}
	323
edd16368 SC	324	/*
	325	* Returns true if fifo is full.
	326	*
	327	*/
	328	static unsigned long SA5_fifo_full(struct ctlr_info *h)
	329	{
	330	if (h->commands_outstanding >= h->max_commands)
	331	return 1;
	332	else
	333	return 0;
	334
	335	}
	336	/*
	337	* returns value read from hardware.
	338	* returns FIFO_EMPTY if there is nothing to read
	339	*/
254f796b MG	340	static unsigned long SA5_completed(struct ctlr_info *h,
254f796b MG	341	__attribute__((unused)) u8 q)
edd16368 SC	342	{
	343	unsigned long register_value
	344	= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
e16a33ad	345	unsigned long flags;
edd16368	346
e16a33ad MG	347	if (register_value != FIFO_EMPTY) {
e16a33ad MG	348	spin_lock_irqsave(&h->lock, flags);
edd16368	349	h->commands_outstanding--;
e16a33ad MG	350	spin_unlock_irqrestore(&h->lock, flags);
e16a33ad MG	351	}
edd16368 SC	352
	353	#ifdef HPSA_DEBUG
	354	if (register_value != FIFO_EMPTY)
84ca0be2	355	dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
edd16368 SC	356	register_value);
edd16368 SC	357	else
f79cfec6	358	dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
edd16368 SC	359	#endif
	360
	361	return register_value;
	362	}
	363	/*
	364	* Returns true if an interrupt is pending..
	365	*/
900c5440	366	static bool SA5_intr_pending(struct ctlr_info *h)
edd16368 SC	367	{
	368	unsigned long register_value =
	369	readl(h->vaddr + SA5_INTR_STATUS);
84ca0be2	370	dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
900c5440	371	return register_value & SA5_INTR_PENDING;
edd16368 SC	372	}
edd16368 SC	373
303932fd DB	374	static bool SA5_performant_intr_pending(struct ctlr_info *h)
	375	{
	376	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
	377
	378	if (!register_value)
	379	return false;
	380
	381	if (h->msi_vector \|\| h->msix_vector)
	382	return true;
	383
	384	/* Read outbound doorbell to flush */
	385	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	386	return register_value & SA5_OUTDB_STATUS_PERF_BIT;
	387	}
edd16368 SC	388
	389	static struct access_method SA5_access = {
	390	SA5_submit_command,
	391	SA5_intr_mask,
	392	SA5_fifo_full,
	393	SA5_intr_pending,
	394	SA5_completed,
	395	};
	396
303932fd DB	397	static struct access_method SA5_performant_access = {
	398	SA5_submit_command,
	399	SA5_performant_intr_mask,
	400	SA5_fifo_full,
	401	SA5_performant_intr_pending,
	402	SA5_performant_completed,
	403	};
	404
edd16368	405	struct board_type {
01a02ffc	406	u32 board_id;
edd16368 SC	407	char *product_name;
	408	struct access_method *access;
	409	};
	410
edd16368 SC	411	#endif /* HPSA_H */
edd16368 SC	412