[deliverable/linux.git] / drivers / scsi / hpsa_cmd.h

/*
 *    Disk Array driver for HP Smart Array SAS controllers
 *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; version 2 of the License.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *    NON INFRINGEMENT.  See the GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
 *
 */
#ifndef HPSA_CMD_H
#define HPSA_CMD_H

/* general boundary defintions */
#define SENSEINFOBYTES          32 /* may vary between hbas */
#define MAXSGENTRIES            32
#define HPSA_SG_CHAIN		0x80000000
#define MAXREPLYQS              256

/* Command Status value */
#define CMD_SUCCESS             0x0000
#define CMD_TARGET_STATUS       0x0001
#define CMD_DATA_UNDERRUN       0x0002
#define CMD_DATA_OVERRUN        0x0003
#define CMD_INVALID             0x0004
#define CMD_PROTOCOL_ERR        0x0005
#define CMD_HARDWARE_ERR        0x0006
#define CMD_CONNECTION_LOST     0x0007
#define CMD_ABORTED             0x0008
#define CMD_ABORT_FAILED        0x0009
#define CMD_UNSOLICITED_ABORT   0x000A
#define CMD_TIMEOUT             0x000B
#define CMD_UNABORTABLE		0x000C

/* Unit Attentions ASC's as defined for the MSA2012sa */
#define POWER_OR_RESET			0x29
#define STATE_CHANGED			0x2a
#define UNIT_ATTENTION_CLEARED		0x2f
#define LUN_FAILED			0x3e
#define REPORT_LUNS_CHANGED		0x3f

/* Unit Attentions ASCQ's as defined for the MSA2012sa */

	/* These ASCQ's defined for ASC = POWER_OR_RESET */
#define POWER_ON_RESET			0x00
#define POWER_ON_REBOOT			0x01
#define SCSI_BUS_RESET			0x02
#define MSA_TARGET_RESET		0x03
#define CONTROLLER_FAILOVER		0x04
#define TRANSCEIVER_SE			0x05
#define TRANSCEIVER_LVD			0x06

	/* These ASCQ's defined for ASC = STATE_CHANGED */
#define RESERVATION_PREEMPTED		0x03
#define ASYM_ACCESS_CHANGED		0x06
#define LUN_CAPACITY_CHANGED		0x09

/* transfer direction */
#define XFER_NONE               0x00
#define XFER_WRITE              0x01
#define XFER_READ               0x02
#define XFER_RSVD               0x03

/* task attribute */
#define ATTR_UNTAGGED           0x00
#define ATTR_SIMPLE             0x04
#define ATTR_HEADOFQUEUE        0x05
#define ATTR_ORDERED            0x06
#define ATTR_ACA                0x07

/* cdb type */
#define TYPE_CMD				0x00
#define TYPE_MSG				0x01

/* config space register offsets */
#define CFG_VENDORID            0x00
#define CFG_DEVICEID            0x02
#define CFG_I2OBAR              0x10
#define CFG_MEM1BAR             0x14

/* i2o space register offsets */
#define I2O_IBDB_SET            0x20
#define I2O_IBDB_CLEAR          0x70
#define I2O_INT_STATUS          0x30
#define I2O_INT_MASK            0x34
#define I2O_IBPOST_Q            0x40
#define I2O_OBPOST_Q            0x44
#define I2O_DMA1_CFG		0x214

/* Configuration Table */
#define CFGTBL_ChangeReq        0x00000001l
#define CFGTBL_AccCmds          0x00000001l
#define DOORBELL_CTLR_RESET	0x00000004l
#define DOORBELL_CTLR_RESET2	0x00000020l

#define CFGTBL_Trans_Simple     0x00000002l
#define CFGTBL_Trans_Performant 0x00000004l
#define CFGTBL_Trans_use_short_tags 0x20000000l

#define CFGTBL_BusType_Ultra2   0x00000001l
#define CFGTBL_BusType_Ultra3   0x00000002l
#define CFGTBL_BusType_Fibre1G  0x00000100l
#define CFGTBL_BusType_Fibre2G  0x00000200l
struct vals32 {
	u32   lower;
	u32   upper;
};

union u64bit {
	struct vals32 val32;
	u64 val;
};

/* FIXME this is a per controller value (barf!) */
#define HPSA_MAX_TARGETS_PER_CTLR 16
#define HPSA_MAX_LUN 256
#define HPSA_MAX_PHYS_LUN 1024

/* SCSI-3 Commands */
#pragma pack(1)

#define HPSA_INQUIRY 0x12
struct InquiryData {
	u8 data_byte[36];
};

#define HPSA_REPORT_LOG 0xc2    /* Report Logical LUNs */
#define HPSA_REPORT_PHYS 0xc3   /* Report Physical LUNs */
struct ReportLUNdata {
	u8 LUNListLength[4];
	u32 reserved;
	u8 LUN[HPSA_MAX_LUN][8];
};

struct ReportExtendedLUNdata {
	u8 LUNListLength[4];
	u8 extended_response_flag;
	u8 reserved[3];
	u8 LUN[HPSA_MAX_LUN][24];
};

struct SenseSubsystem_info {
	u8 reserved[36];
	u8 portname[8];
	u8 reserved1[1108];
};

/* BMIC commands */
#define BMIC_READ 0x26
#define BMIC_WRITE 0x27
#define BMIC_CACHE_FLUSH 0xc2
#define HPSA_CACHE_FLUSH 0x01	/* C2 was already being used by HPSA */

/* Command List Structure */
union SCSI3Addr {
	struct {
		u8 Dev;
		u8 Bus:6;
		u8 Mode:2;        /* b00 */
	} PeripDev;
	struct {
		u8 DevLSB;
		u8 DevMSB:6;
		u8 Mode:2;        /* b01 */
	} LogDev;
	struct {
		u8 Dev:5;
		u8 Bus:3;
		u8 Targ:6;
		u8 Mode:2;        /* b10 */
	} LogUnit;
};

struct PhysDevAddr {
	u32             TargetId:24;
	u32             Bus:6;
	u32             Mode:2;
	/* 2 level target device addr */
	union SCSI3Addr  Target[2];
};

struct LogDevAddr {
	u32            VolId:30;
	u32            Mode:2;
	u8             reserved[4];
};

union LUNAddr {
	u8               LunAddrBytes[8];
	union SCSI3Addr    SCSI3Lun[4];
	struct PhysDevAddr PhysDev;
	struct LogDevAddr  LogDev;
};

struct CommandListHeader {
	u8              ReplyQueue;
	u8              SGList;
	u16             SGTotal;
	struct vals32     Tag;
	union LUNAddr     LUN;
};

struct RequestBlock {
	u8   CDBLen;
	struct {
		u8 Type:3;
		u8 Attribute:3;
		u8 Direction:2;
	} Type;
	u16  Timeout;
	u8   CDB[16];
};

struct ErrDescriptor {
	struct vals32 Addr;
	u32  Len;
};

struct SGDescriptor {
	struct vals32 Addr;
	u32  Len;
	u32  Ext;
};

union MoreErrInfo {
	struct {
		u8  Reserved[3];
		u8  Type;
		u32 ErrorInfo;
	} Common_Info;
	struct {
		u8  Reserved[2];
		u8  offense_size; /* size of offending entry */
		u8  offense_num;  /* byte # of offense 0-base */
		u32 offense_value;
	} Invalid_Cmd;
};
struct ErrorInfo {
	u8               ScsiStatus;
	u8               SenseLen;
	u16              CommandStatus;
	u32              ResidualCnt;
	union MoreErrInfo  MoreErrInfo;
	u8               SenseInfo[SENSEINFOBYTES];
};
/* Command types */
#define CMD_IOCTL_PEND  0x01
#define CMD_SCSI	0x03

#define DIRECT_LOOKUP_SHIFT 5
#define DIRECT_LOOKUP_BIT 0x10
#define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))

#define HPSA_ERROR_BIT          0x02
struct ctlr_info; /* defined in hpsa.h */
/* The size of this structure needs to be divisible by 32
 * on all architectures because low 5 bits of the addresses
 * are used as follows:
 *
 * bit 0: to device, used to indicate "performant mode" command
 *        from device, indidcates error status.
 * bit 1-3: to device, indicates block fetch table entry for
 *          reducing DMA in fetching commands from host memory.
 * bit 4: used to indicate whether tag is "direct lookup" (index),
 *        or a bus address.
 */

struct CommandList {
	struct CommandListHeader Header;
	struct RequestBlock      Request;
	struct ErrDescriptor     ErrDesc;
	struct SGDescriptor      SG[MAXSGENTRIES];
	/* information associated with the command */
	u32			   busaddr; /* physical addr of this record */
	struct ErrorInfo *err_info; /* pointer to the allocated mem */
	struct ctlr_info	   *h;
	int			   cmd_type;
	long			   cmdindex;
	struct list_head list;
	struct request *rq;
	struct completion *waiting;
	void   *scsi_cmd;

/* on 64 bit architectures, to get this to be 32-byte-aligned
 * it so happens we need PAD_64 bytes of padding, on 32 bit systems,
 * we need PAD_32 bytes of padding (see below).   This does that.
 * If it happens that 64 bit and 32 bit systems need different
 * padding, PAD_32 and PAD_64 can be set independently, and.
 * the code below will do the right thing.
 */
#define IS_32_BIT ((8 - sizeof(long))/4)
#define IS_64_BIT (!IS_32_BIT)
#define PAD_32 (4)
#define PAD_64 (4)
#define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
	u8 pad[COMMANDLIST_PAD];
};

/* Configuration Table Structure */
struct HostWrite {
	u32 TransportRequest;
	u32 Reserved;
	u32 CoalIntDelay;
	u32 CoalIntCount;
};

#define SIMPLE_MODE     0x02
#define PERFORMANT_MODE 0x04
#define MEMQ_MODE       0x08

struct CfgTable {
	u8            Signature[4];
	u32		SpecValence;
	u32           TransportSupport;
	u32           TransportActive;
	struct 		HostWrite HostWrite;
	u32           CmdsOutMax;
	u32           BusTypes;
	u32           TransMethodOffset;
	u8            ServerName[16];
	u32           HeartBeat;
	u32           SCSI_Prefetch;
	u32	 	MaxScatterGatherElements;
	u32		MaxLogicalUnits;
	u32		MaxPhysicalDevices;
	u32		MaxPhysicalDrivesPerLogicalUnit;
	u32		MaxPerformantModeCommands;
	u8		reserved[0x78 - 0x58];
	u32		misc_fw_support; /* offset 0x78 */
#define			MISC_FW_DOORBELL_RESET (0x02)
#define			MISC_FW_DOORBELL_RESET2 (0x010)
	u8		driver_version[32];
};

#define NUM_BLOCKFETCH_ENTRIES 8
struct TransTable_struct {
	u32            BlockFetch[NUM_BLOCKFETCH_ENTRIES];
	u32            RepQSize;
	u32            RepQCount;
	u32            RepQCtrAddrLow32;
	u32            RepQCtrAddrHigh32;
	u32            RepQAddr0Low32;
	u32            RepQAddr0High32;
};

struct hpsa_pci_info {
	unsigned char	bus;
	unsigned char	dev_fn;
	unsigned short	domain;
	u32		board_id;
};

#pragma pack()
#endif /* HPSA_CMD_H */
Commit	Line	Data
edd16368 SC	1	/*
	2	* Disk Array driver for HP Smart Array SAS controllers
	3	* Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; version 2 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	12	* NON INFRINGEMENT. See the GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	17	*
	18	* Questions/Comments/Bugfixes to iss_storagedev@hp.com
	19	*
	20	*/
	21	#ifndef HPSA_CMD_H
	22	#define HPSA_CMD_H
	23
	24	/* general boundary defintions */
	25	#define SENSEINFOBYTES 32 /* may vary between hbas */
33a2ffce SC	26	#define MAXSGENTRIES 32
33a2ffce SC	27	#define HPSA_SG_CHAIN 0x80000000
edd16368 SC	28	#define MAXREPLYQS 256
	29
	30	/* Command Status value */
	31	#define CMD_SUCCESS 0x0000
	32	#define CMD_TARGET_STATUS 0x0001
	33	#define CMD_DATA_UNDERRUN 0x0002
	34	#define CMD_DATA_OVERRUN 0x0003
	35	#define CMD_INVALID 0x0004
	36	#define CMD_PROTOCOL_ERR 0x0005
	37	#define CMD_HARDWARE_ERR 0x0006
	38	#define CMD_CONNECTION_LOST 0x0007
	39	#define CMD_ABORTED 0x0008
	40	#define CMD_ABORT_FAILED 0x0009
	41	#define CMD_UNSOLICITED_ABORT 0x000A
	42	#define CMD_TIMEOUT 0x000B
	43	#define CMD_UNABORTABLE 0x000C
	44
	45	/* Unit Attentions ASC's as defined for the MSA2012sa */
	46	#define POWER_OR_RESET 0x29
	47	#define STATE_CHANGED 0x2a
	48	#define UNIT_ATTENTION_CLEARED 0x2f
	49	#define LUN_FAILED 0x3e
	50	#define REPORT_LUNS_CHANGED 0x3f
	51
	52	/* Unit Attentions ASCQ's as defined for the MSA2012sa */
	53
	54	/* These ASCQ's defined for ASC = POWER_OR_RESET */
	55	#define POWER_ON_RESET 0x00
	56	#define POWER_ON_REBOOT 0x01
	57	#define SCSI_BUS_RESET 0x02
	58	#define MSA_TARGET_RESET 0x03
	59	#define CONTROLLER_FAILOVER 0x04
	60	#define TRANSCEIVER_SE 0x05
	61	#define TRANSCEIVER_LVD 0x06
	62
	63	/* These ASCQ's defined for ASC = STATE_CHANGED */
	64	#define RESERVATION_PREEMPTED 0x03
	65	#define ASYM_ACCESS_CHANGED 0x06
	66	#define LUN_CAPACITY_CHANGED 0x09
	67
	68	/* transfer direction */
	69	#define XFER_NONE 0x00
	70	#define XFER_WRITE 0x01
	71	#define XFER_READ 0x02
	72	#define XFER_RSVD 0x03
	73
	74	/* task attribute */
	75	#define ATTR_UNTAGGED 0x00
	76	#define ATTR_SIMPLE 0x04
	77	#define ATTR_HEADOFQUEUE 0x05
	78	#define ATTR_ORDERED 0x06
	79	#define ATTR_ACA 0x07
	80
	81	/* cdb type */
	82	#define TYPE_CMD 0x00
	83	#define TYPE_MSG 0x01
	84
	85	/* config space register offsets */
	86	#define CFG_VENDORID 0x00
	87	#define CFG_DEVICEID 0x02
	88	#define CFG_I2OBAR 0x10
	89	#define CFG_MEM1BAR 0x14
	90
	91	/* i2o space register offsets */
92	#define I2O_IBDB_SET 0x20
93	#define I2O_IBDB_CLEAR 0x70
94	#define I2O_INT_STATUS 0x30
95	#define I2O_INT_MASK 0x34
96	#define I2O_IBPOST_Q 0x40
97	#define I2O_OBPOST_Q 0x44
98	#define I2O_DMA1_CFG 0x214
99
100	/* Configuration Table */
101	#define CFGTBL_ChangeReq 0x00000001l
102	#define CFGTBL_AccCmds 0x00000001l
1df8552a	103	#define DOORBELL_CTLR_RESET 0x00000004l
cf0b08d0	104	#define DOORBELL_CTLR_RESET2 0x00000020l
edd16368 SC	105
edd16368 SC	106	#define CFGTBL_Trans_Simple 0x00000002l
303932fd	107	#define CFGTBL_Trans_Performant 0x00000004l
960a30e7	108	#define CFGTBL_Trans_use_short_tags 0x20000000l
edd16368 SC	109
	110	#define CFGTBL_BusType_Ultra2 0x00000001l
	111	#define CFGTBL_BusType_Ultra3 0x00000002l
	112	#define CFGTBL_BusType_Fibre1G 0x00000100l
	113	#define CFGTBL_BusType_Fibre2G 0x00000200l
	114	struct vals32 {
01a02ffc SC	115	u32 lower;
01a02ffc SC	116	u32 upper;
edd16368 SC	117	};
	118
	119	union u64bit {
	120	struct vals32 val32;
01a02ffc	121	u64 val;
edd16368 SC	122	};
	123
	124	/* FIXME this is a per controller value (barf!) */
	125	#define HPSA_MAX_TARGETS_PER_CTLR 16
	126	#define HPSA_MAX_LUN 256
	127	#define HPSA_MAX_PHYS_LUN 1024
	128
	129	/* SCSI-3 Commands */
	130	#pragma pack(1)
	131
	132	#define HPSA_INQUIRY 0x12
	133	struct InquiryData {
01a02ffc	134	u8 data_byte[36];
edd16368 SC	135	};
	136
	137	#define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */
	138	#define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
	139	struct ReportLUNdata {
01a02ffc SC	140	u8 LUNListLength[4];
	141	u32 reserved;
	142	u8 LUN[HPSA_MAX_LUN][8];
edd16368 SC	143	};
	144
	145	struct ReportExtendedLUNdata {
01a02ffc SC	146	u8 LUNListLength[4];
	147	u8 extended_response_flag;
	148	u8 reserved[3];
	149	u8 LUN[HPSA_MAX_LUN][24];
edd16368 SC	150	};
	151
	152	struct SenseSubsystem_info {
01a02ffc SC	153	u8 reserved[36];
	154	u8 portname[8];
	155	u8 reserved1[1108];
edd16368 SC	156	};
edd16368 SC	157
edd16368 SC	158	/* BMIC commands */
	159	#define BMIC_READ 0x26
	160	#define BMIC_WRITE 0x27
	161	#define BMIC_CACHE_FLUSH 0xc2
	162	#define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */
	163
	164	/* Command List Structure */
	165	union SCSI3Addr {
	166	struct {
01a02ffc SC	167	u8 Dev;
	168	u8 Bus:6;
	169	u8 Mode:2; /* b00 */
edd16368 SC	170	} PeripDev;
edd16368 SC	171	struct {
01a02ffc SC	172	u8 DevLSB;
	173	u8 DevMSB:6;
	174	u8 Mode:2; /* b01 */
edd16368 SC	175	} LogDev;
edd16368 SC	176	struct {
01a02ffc SC	177	u8 Dev:5;
	178	u8 Bus:3;
	179	u8 Targ:6;
	180	u8 Mode:2; /* b10 */
edd16368 SC	181	} LogUnit;
	182	};
	183
	184	struct PhysDevAddr {
01a02ffc SC	185	u32 TargetId:24;
	186	u32 Bus:6;
	187	u32 Mode:2;
edd16368 SC	188	/* 2 level target device addr */
	189	union SCSI3Addr Target[2];
	190	};
	191
	192	struct LogDevAddr {
01a02ffc SC	193	u32 VolId:30;
	194	u32 Mode:2;
	195	u8 reserved[4];
edd16368 SC	196	};
	197
	198	union LUNAddr {
01a02ffc	199	u8 LunAddrBytes[8];
edd16368 SC	200	union SCSI3Addr SCSI3Lun[4];
	201	struct PhysDevAddr PhysDev;
	202	struct LogDevAddr LogDev;
	203	};
	204
	205	struct CommandListHeader {
01a02ffc SC	206	u8 ReplyQueue;
	207	u8 SGList;
	208	u16 SGTotal;
edd16368 SC	209	struct vals32 Tag;
	210	union LUNAddr LUN;
	211	};
	212
	213	struct RequestBlock {
01a02ffc	214	u8 CDBLen;
edd16368	215	struct {
01a02ffc SC	216	u8 Type:3;
	217	u8 Attribute:3;
	218	u8 Direction:2;
edd16368	219	} Type;
01a02ffc SC	220	u16 Timeout;
01a02ffc SC	221	u8 CDB[16];
edd16368 SC	222	};
	223
	224	struct ErrDescriptor {
	225	struct vals32 Addr;
01a02ffc	226	u32 Len;
edd16368 SC	227	};
	228
	229	struct SGDescriptor {
	230	struct vals32 Addr;
01a02ffc SC	231	u32 Len;
01a02ffc SC	232	u32 Ext;
edd16368 SC	233	};
	234
	235	union MoreErrInfo {
	236	struct {
01a02ffc SC	237	u8 Reserved[3];
	238	u8 Type;
	239	u32 ErrorInfo;
edd16368 SC	240	} Common_Info;
edd16368 SC	241	struct {
01a02ffc SC	242	u8 Reserved[2];
	243	u8 offense_size; /* size of offending entry */
	244	u8 offense_num; /* byte # of offense 0-base */
	245	u32 offense_value;
edd16368 SC	246	} Invalid_Cmd;
	247	};
	248	struct ErrorInfo {
01a02ffc SC	249	u8 ScsiStatus;
	250	u8 SenseLen;
	251	u16 CommandStatus;
	252	u32 ResidualCnt;
edd16368	253	union MoreErrInfo MoreErrInfo;
01a02ffc	254	u8 SenseInfo[SENSEINFOBYTES];
edd16368 SC	255	};
	256	/* Command types */
	257	#define CMD_IOCTL_PEND 0x01
	258	#define CMD_SCSI 0x03
	259
303932fd DB	260	#define DIRECT_LOOKUP_SHIFT 5
303932fd DB	261	#define DIRECT_LOOKUP_BIT 0x10
d896f3f3	262	#define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
303932fd DB	263
303932fd DB	264	#define HPSA_ERROR_BIT 0x02
edd16368	265	struct ctlr_info; /* defined in hpsa.h */
303932fd DB	266	/* The size of this structure needs to be divisible by 32
	267	* on all architectures because low 5 bits of the addresses
	268	* are used as follows:
	269	*
	270	* bit 0: to device, used to indicate "performant mode" command
	271	* from device, indidcates error status.
	272	* bit 1-3: to device, indicates block fetch table entry for
	273	* reducing DMA in fetching commands from host memory.
	274	* bit 4: used to indicate whether tag is "direct lookup" (index),
	275	* or a bus address.
edd16368	276	*/
303932fd	277
edd16368 SC	278	struct CommandList {
	279	struct CommandListHeader Header;
	280	struct RequestBlock Request;
	281	struct ErrDescriptor ErrDesc;
	282	struct SGDescriptor SG[MAXSGENTRIES];
	283	/* information associated with the command */
01a02ffc	284	u32 busaddr; /* physical addr of this record */
edd16368 SC	285	struct ErrorInfo err_info; / pointer to the allocated mem */
	286	struct ctlr_info *h;
	287	int cmd_type;
	288	long cmdindex;
9e0fc764	289	struct list_head list;
edd16368 SC	290	struct request *rq;
edd16368 SC	291	struct completion *waiting;
edd16368	292	void *scsi_cmd;
303932fd DB	293
303932fd DB	294	/* on 64 bit architectures, to get this to be 32-byte-aligned
db61bfcf SC	295	* it so happens we need PAD_64 bytes of padding, on 32 bit systems,
	296	* we need PAD_32 bytes of padding (see below). This does that.
	297	* If it happens that 64 bit and 32 bit systems need different
	298	* padding, PAD_32 and PAD_64 can be set independently, and.
	299	* the code below will do the right thing.
303932fd	300	*/
db61bfcf SC	301	#define IS_32_BIT ((8 - sizeof(long))/4)
db61bfcf SC	302	#define IS_64_BIT (!IS_32_BIT)
43aebfa1 SC	303	#define PAD_32 (4)
43aebfa1 SC	304	#define PAD_64 (4)
db61bfcf	305	#define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
303932fd	306	u8 pad[COMMANDLIST_PAD];
edd16368 SC	307	};
	308
	309	/* Configuration Table Structure */
	310	struct HostWrite {
01a02ffc SC	311	u32 TransportRequest;
	312	u32 Reserved;
	313	u32 CoalIntDelay;
	314	u32 CoalIntCount;
edd16368 SC	315	};
edd16368 SC	316
303932fd DB	317	#define SIMPLE_MODE 0x02
	318	#define PERFORMANT_MODE 0x04
	319	#define MEMQ_MODE 0x08
	320
edd16368	321	struct CfgTable {
303932fd DB	322	u8 Signature[4];
	323	u32 SpecValence;
	324	u32 TransportSupport;
	325	u32 TransportActive;
	326	struct HostWrite HostWrite;
	327	u32 CmdsOutMax;
	328	u32 BusTypes;
	329	u32 TransMethodOffset;
	330	u8 ServerName[16];
	331	u32 HeartBeat;
	332	u32 SCSI_Prefetch;
	333	u32 MaxScatterGatherElements;
	334	u32 MaxLogicalUnits;
	335	u32 MaxPhysicalDevices;
	336	u32 MaxPhysicalDrivesPerLogicalUnit;
	337	u32 MaxPerformantModeCommands;
1df8552a SC	338	u8 reserved[0x78 - 0x58];
	339	u32 misc_fw_support; /* offset 0x78 */
	340	#define MISC_FW_DOORBELL_RESET (0x02)
cf0b08d0	341	#define MISC_FW_DOORBELL_RESET2 (0x010)
580ada3c	342	u8 driver_version[32];
303932fd DB	343	};
	344
	345	#define NUM_BLOCKFETCH_ENTRIES 8
	346	struct TransTable_struct {
	347	u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES];
	348	u32 RepQSize;
	349	u32 RepQCount;
	350	u32 RepQCtrAddrLow32;
	351	u32 RepQCtrAddrHigh32;
	352	u32 RepQAddr0Low32;
	353	u32 RepQAddr0High32;
edd16368 SC	354	};
	355
	356	struct hpsa_pci_info {
	357	unsigned char bus;
	358	unsigned char dev_fn;
	359	unsigned short domain;
01a02ffc	360	u32 board_id;
edd16368 SC	361	};
	362
	363	#pragma pack()
	364	#endif /* HPSA_CMD_H */