[deliverable/linux.git] / drivers / scsi / hpsa_cmd.h

/*
 *    Disk Array driver for HP Smart Array SAS controllers
 *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; version 2 of the License.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *    NON INFRINGEMENT.  See the GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
 *
 */
#ifndef HPSA_CMD_H
#define HPSA_CMD_H

/* general boundary defintions */
#define SENSEINFOBYTES          32 /* may vary between hbas */
#define MAXSGENTRIES            31
#define MAXREPLYQS              256

/* Command Status value */
#define CMD_SUCCESS             0x0000
#define CMD_TARGET_STATUS       0x0001
#define CMD_DATA_UNDERRUN       0x0002
#define CMD_DATA_OVERRUN        0x0003
#define CMD_INVALID             0x0004
#define CMD_PROTOCOL_ERR        0x0005
#define CMD_HARDWARE_ERR        0x0006
#define CMD_CONNECTION_LOST     0x0007
#define CMD_ABORTED             0x0008
#define CMD_ABORT_FAILED        0x0009
#define CMD_UNSOLICITED_ABORT   0x000A
#define CMD_TIMEOUT             0x000B
#define CMD_UNABORTABLE		0x000C

/* Unit Attentions ASC's as defined for the MSA2012sa */
#define POWER_OR_RESET			0x29
#define STATE_CHANGED			0x2a
#define UNIT_ATTENTION_CLEARED		0x2f
#define LUN_FAILED			0x3e
#define REPORT_LUNS_CHANGED		0x3f

/* Unit Attentions ASCQ's as defined for the MSA2012sa */

	/* These ASCQ's defined for ASC = POWER_OR_RESET */
#define POWER_ON_RESET			0x00
#define POWER_ON_REBOOT			0x01
#define SCSI_BUS_RESET			0x02
#define MSA_TARGET_RESET		0x03
#define CONTROLLER_FAILOVER		0x04
#define TRANSCEIVER_SE			0x05
#define TRANSCEIVER_LVD			0x06

	/* These ASCQ's defined for ASC = STATE_CHANGED */
#define RESERVATION_PREEMPTED		0x03
#define ASYM_ACCESS_CHANGED		0x06
#define LUN_CAPACITY_CHANGED		0x09

/* transfer direction */
#define XFER_NONE               0x00
#define XFER_WRITE              0x01
#define XFER_READ               0x02
#define XFER_RSVD               0x03

/* task attribute */
#define ATTR_UNTAGGED           0x00
#define ATTR_SIMPLE             0x04
#define ATTR_HEADOFQUEUE        0x05
#define ATTR_ORDERED            0x06
#define ATTR_ACA                0x07

/* cdb type */
#define TYPE_CMD				0x00
#define TYPE_MSG				0x01

/* config space register offsets */
#define CFG_VENDORID            0x00
#define CFG_DEVICEID            0x02
#define CFG_I2OBAR              0x10
#define CFG_MEM1BAR             0x14

/* i2o space register offsets */
#define I2O_IBDB_SET            0x20
#define I2O_IBDB_CLEAR          0x70
#define I2O_INT_STATUS          0x30
#define I2O_INT_MASK            0x34
#define I2O_IBPOST_Q            0x40
#define I2O_OBPOST_Q            0x44
#define I2O_DMA1_CFG		0x214

/* Configuration Table */
#define CFGTBL_ChangeReq        0x00000001l
#define CFGTBL_AccCmds          0x00000001l

#define CFGTBL_Trans_Simple     0x00000002l
#define CFGTBL_Trans_Performant 0x00000004l

#define CFGTBL_BusType_Ultra2   0x00000001l
#define CFGTBL_BusType_Ultra3   0x00000002l
#define CFGTBL_BusType_Fibre1G  0x00000100l
#define CFGTBL_BusType_Fibre2G  0x00000200l
struct vals32 {
	u32   lower;
	u32   upper;
};

union u64bit {
	struct vals32 val32;
	u64 val;
};

/* FIXME this is a per controller value (barf!) */
#define HPSA_MAX_TARGETS_PER_CTLR 16
#define HPSA_MAX_LUN 256
#define HPSA_MAX_PHYS_LUN 1024

/* SCSI-3 Commands */
#pragma pack(1)

#define HPSA_INQUIRY 0x12
struct InquiryData {
	u8 data_byte[36];
};

#define HPSA_REPORT_LOG 0xc2    /* Report Logical LUNs */
#define HPSA_REPORT_PHYS 0xc3   /* Report Physical LUNs */
struct ReportLUNdata {
	u8 LUNListLength[4];
	u32 reserved;
	u8 LUN[HPSA_MAX_LUN][8];
};

struct ReportExtendedLUNdata {
	u8 LUNListLength[4];
	u8 extended_response_flag;
	u8 reserved[3];
	u8 LUN[HPSA_MAX_LUN][24];
};

struct SenseSubsystem_info {
	u8 reserved[36];
	u8 portname[8];
	u8 reserved1[1108];
};

#define HPSA_READ_CAPACITY 0x25 /* Read Capacity */
struct ReadCapdata {
	u8 total_size[4];	/* Total size in blocks */
	u8 block_size[4];	/* Size of blocks in bytes */
};

#if 0
/* 12 byte commands not implemented in firmware yet. */
#define HPSA_READ 	0xa8
#define HPSA_WRITE	0xaa
#endif

#define HPSA_READ   0x28    /* Read(10) */
#define HPSA_WRITE  0x2a    /* Write(10) */

/* BMIC commands */
#define BMIC_READ 0x26
#define BMIC_WRITE 0x27
#define BMIC_CACHE_FLUSH 0xc2
#define HPSA_CACHE_FLUSH 0x01	/* C2 was already being used by HPSA */

/* Command List Structure */
union SCSI3Addr {
	struct {
		u8 Dev;
		u8 Bus:6;
		u8 Mode:2;        /* b00 */
	} PeripDev;
	struct {
		u8 DevLSB;
		u8 DevMSB:6;
		u8 Mode:2;        /* b01 */
	} LogDev;
	struct {
		u8 Dev:5;
		u8 Bus:3;
		u8 Targ:6;
		u8 Mode:2;        /* b10 */
	} LogUnit;
};

struct PhysDevAddr {
	u32             TargetId:24;
	u32             Bus:6;
	u32             Mode:2;
	/* 2 level target device addr */
	union SCSI3Addr  Target[2];
};

struct LogDevAddr {
	u32            VolId:30;
	u32            Mode:2;
	u8             reserved[4];
};

union LUNAddr {
	u8               LunAddrBytes[8];
	union SCSI3Addr    SCSI3Lun[4];
	struct PhysDevAddr PhysDev;
	struct LogDevAddr  LogDev;
};

struct CommandListHeader {
	u8              ReplyQueue;
	u8              SGList;
	u16             SGTotal;
	struct vals32     Tag;
	union LUNAddr     LUN;
};

struct RequestBlock {
	u8   CDBLen;
	struct {
		u8 Type:3;
		u8 Attribute:3;
		u8 Direction:2;
	} Type;
	u16  Timeout;
	u8   CDB[16];
};

struct ErrDescriptor {
	struct vals32 Addr;
	u32  Len;
};

struct SGDescriptor {
	struct vals32 Addr;
	u32  Len;
	u32  Ext;
};

union MoreErrInfo {
	struct {
		u8  Reserved[3];
		u8  Type;
		u32 ErrorInfo;
	} Common_Info;
	struct {
		u8  Reserved[2];
		u8  offense_size; /* size of offending entry */
		u8  offense_num;  /* byte # of offense 0-base */
		u32 offense_value;
	} Invalid_Cmd;
};
struct ErrorInfo {
	u8               ScsiStatus;
	u8               SenseLen;
	u16              CommandStatus;
	u32              ResidualCnt;
	union MoreErrInfo  MoreErrInfo;
	u8               SenseInfo[SENSEINFOBYTES];
};
/* Command types */
#define CMD_IOCTL_PEND  0x01
#define CMD_SCSI	0x03

/* This structure needs to be divisible by 32 for new
 * indexing method and performant mode.
 */
#define PAD32 32
#define PAD64DIFF 0
#define USEEXTRA ((sizeof(void *) - 4)/4)
#define PADSIZE (PAD32 + PAD64DIFF * USEEXTRA)

#define DIRECT_LOOKUP_SHIFT 5
#define DIRECT_LOOKUP_BIT 0x10

#define HPSA_ERROR_BIT          0x02
struct ctlr_info; /* defined in hpsa.h */
/* The size of this structure needs to be divisible by 32
 * on all architectures because low 5 bits of the addresses
 * are used as follows:
 *
 * bit 0: to device, used to indicate "performant mode" command
 *        from device, indidcates error status.
 * bit 1-3: to device, indicates block fetch table entry for
 *          reducing DMA in fetching commands from host memory.
 * bit 4: used to indicate whether tag is "direct lookup" (index),
 *        or a bus address.
 */

struct CommandList {
	struct CommandListHeader Header;
	struct RequestBlock      Request;
	struct ErrDescriptor     ErrDesc;
	struct SGDescriptor      SG[MAXSGENTRIES];
	/* information associated with the command */
	u32			   busaddr; /* physical addr of this record */
	struct ErrorInfo *err_info; /* pointer to the allocated mem */
	struct ctlr_info	   *h;
	int			   cmd_type;
	long			   cmdindex;
	struct hlist_node list;
	struct CommandList *prev;
	struct CommandList *next;
	struct request *rq;
	struct completion *waiting;
	int	 retry_count;
	void   *scsi_cmd;

/* on 64 bit architectures, to get this to be 32-byte-aligned
 * it so happens we need PAD_64 bytes of padding, on 32 bit systems,
 * we need PAD_32 bytes of padding (see below).   This does that.
 * If it happens that 64 bit and 32 bit systems need different
 * padding, PAD_32 and PAD_64 can be set independently, and.
 * the code below will do the right thing.
 */
#define IS_32_BIT ((8 - sizeof(long))/4)
#define IS_64_BIT (!IS_32_BIT)
#define PAD_32 (8)
#define PAD_64 (0)
#define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
	u8 pad[COMMANDLIST_PAD];
};

/* Configuration Table Structure */
struct HostWrite {
	u32 TransportRequest;
	u32 Reserved;
	u32 CoalIntDelay;
	u32 CoalIntCount;
};

#define SIMPLE_MODE     0x02
#define PERFORMANT_MODE 0x04
#define MEMQ_MODE       0x08

struct CfgTable {
	u8            Signature[4];
	u32		SpecValence;
	u32           TransportSupport;
	u32           TransportActive;
	struct 		HostWrite HostWrite;
	u32           CmdsOutMax;
	u32           BusTypes;
	u32           TransMethodOffset;
	u8            ServerName[16];
	u32           HeartBeat;
	u32           SCSI_Prefetch;
	u32	 	MaxScatterGatherElements;
	u32		MaxLogicalUnits;
	u32		MaxPhysicalDevices;
	u32		MaxPhysicalDrivesPerLogicalUnit;
	u32		MaxPerformantModeCommands;
};

#define NUM_BLOCKFETCH_ENTRIES 8
struct TransTable_struct {
	u32            BlockFetch[NUM_BLOCKFETCH_ENTRIES];
	u32            RepQSize;
	u32            RepQCount;
	u32            RepQCtrAddrLow32;
	u32            RepQCtrAddrHigh32;
	u32            RepQAddr0Low32;
	u32            RepQAddr0High32;
};

struct hpsa_pci_info {
	unsigned char	bus;
	unsigned char	dev_fn;
	unsigned short	domain;
	u32		board_id;
};

#pragma pack()
#endif /* HPSA_CMD_H */
Commit	Line	Data
edd16368 SC	1	/*
	2	* Disk Array driver for HP Smart Array SAS controllers
	3	* Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; version 2 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	12	* NON INFRINGEMENT. See the GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	17	*
	18	* Questions/Comments/Bugfixes to iss_storagedev@hp.com
	19	*
	20	*/
	21	#ifndef HPSA_CMD_H
	22	#define HPSA_CMD_H
	23
	24	/* general boundary defintions */
	25	#define SENSEINFOBYTES 32 /* may vary between hbas */
	26	#define MAXSGENTRIES 31
	27	#define MAXREPLYQS 256
	28
	29	/* Command Status value */
	30	#define CMD_SUCCESS 0x0000
	31	#define CMD_TARGET_STATUS 0x0001
	32	#define CMD_DATA_UNDERRUN 0x0002
	33	#define CMD_DATA_OVERRUN 0x0003
	34	#define CMD_INVALID 0x0004
	35	#define CMD_PROTOCOL_ERR 0x0005
	36	#define CMD_HARDWARE_ERR 0x0006
	37	#define CMD_CONNECTION_LOST 0x0007
	38	#define CMD_ABORTED 0x0008
	39	#define CMD_ABORT_FAILED 0x0009
	40	#define CMD_UNSOLICITED_ABORT 0x000A
	41	#define CMD_TIMEOUT 0x000B
	42	#define CMD_UNABORTABLE 0x000C
	43
	44	/* Unit Attentions ASC's as defined for the MSA2012sa */
	45	#define POWER_OR_RESET 0x29
	46	#define STATE_CHANGED 0x2a
	47	#define UNIT_ATTENTION_CLEARED 0x2f
	48	#define LUN_FAILED 0x3e
	49	#define REPORT_LUNS_CHANGED 0x3f
	50
	51	/* Unit Attentions ASCQ's as defined for the MSA2012sa */
	52
	53	/* These ASCQ's defined for ASC = POWER_OR_RESET */
	54	#define POWER_ON_RESET 0x00
	55	#define POWER_ON_REBOOT 0x01
	56	#define SCSI_BUS_RESET 0x02
	57	#define MSA_TARGET_RESET 0x03
	58	#define CONTROLLER_FAILOVER 0x04
	59	#define TRANSCEIVER_SE 0x05
	60	#define TRANSCEIVER_LVD 0x06
	61
	62	/* These ASCQ's defined for ASC = STATE_CHANGED */
	63	#define RESERVATION_PREEMPTED 0x03
	64	#define ASYM_ACCESS_CHANGED 0x06
65	#define LUN_CAPACITY_CHANGED 0x09
66
67	/* transfer direction */
68	#define XFER_NONE 0x00
69	#define XFER_WRITE 0x01
70	#define XFER_READ 0x02
71	#define XFER_RSVD 0x03
72
73	/* task attribute */
74	#define ATTR_UNTAGGED 0x00
75	#define ATTR_SIMPLE 0x04
76	#define ATTR_HEADOFQUEUE 0x05
77	#define ATTR_ORDERED 0x06
78	#define ATTR_ACA 0x07
79
80	/* cdb type */
81	#define TYPE_CMD 0x00
82	#define TYPE_MSG 0x01
83
84	/* config space register offsets */
85	#define CFG_VENDORID 0x00
86	#define CFG_DEVICEID 0x02
87	#define CFG_I2OBAR 0x10
88	#define CFG_MEM1BAR 0x14
89
90	/* i2o space register offsets */
91	#define I2O_IBDB_SET 0x20
92	#define I2O_IBDB_CLEAR 0x70
93	#define I2O_INT_STATUS 0x30
94	#define I2O_INT_MASK 0x34
95	#define I2O_IBPOST_Q 0x40
96	#define I2O_OBPOST_Q 0x44
97	#define I2O_DMA1_CFG 0x214
98
99	/* Configuration Table */
100	#define CFGTBL_ChangeReq 0x00000001l
101	#define CFGTBL_AccCmds 0x00000001l
102
103	#define CFGTBL_Trans_Simple 0x00000002l
303932fd	104	#define CFGTBL_Trans_Performant 0x00000004l
edd16368 SC	105
	106	#define CFGTBL_BusType_Ultra2 0x00000001l
	107	#define CFGTBL_BusType_Ultra3 0x00000002l
	108	#define CFGTBL_BusType_Fibre1G 0x00000100l
	109	#define CFGTBL_BusType_Fibre2G 0x00000200l
	110	struct vals32 {
01a02ffc SC	111	u32 lower;
01a02ffc SC	112	u32 upper;
edd16368 SC	113	};
	114
	115	union u64bit {
	116	struct vals32 val32;
01a02ffc	117	u64 val;
edd16368 SC	118	};
	119
	120	/* FIXME this is a per controller value (barf!) */
	121	#define HPSA_MAX_TARGETS_PER_CTLR 16
	122	#define HPSA_MAX_LUN 256
	123	#define HPSA_MAX_PHYS_LUN 1024
	124
	125	/* SCSI-3 Commands */
	126	#pragma pack(1)
	127
	128	#define HPSA_INQUIRY 0x12
	129	struct InquiryData {
01a02ffc	130	u8 data_byte[36];
edd16368 SC	131	};
	132
	133	#define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */
	134	#define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
	135	struct ReportLUNdata {
01a02ffc SC	136	u8 LUNListLength[4];
	137	u32 reserved;
	138	u8 LUN[HPSA_MAX_LUN][8];
edd16368 SC	139	};
	140
	141	struct ReportExtendedLUNdata {
01a02ffc SC	142	u8 LUNListLength[4];
	143	u8 extended_response_flag;
	144	u8 reserved[3];
	145	u8 LUN[HPSA_MAX_LUN][24];
edd16368 SC	146	};
	147
	148	struct SenseSubsystem_info {
01a02ffc SC	149	u8 reserved[36];
	150	u8 portname[8];
	151	u8 reserved1[1108];
edd16368 SC	152	};
	153
	154	#define HPSA_READ_CAPACITY 0x25 /* Read Capacity */
	155	struct ReadCapdata {
01a02ffc SC	156	u8 total_size[4]; /* Total size in blocks */
01a02ffc SC	157	u8 block_size[4]; /* Size of blocks in bytes */
edd16368 SC	158	};
	159
	160	#if 0
	161	/* 12 byte commands not implemented in firmware yet. */
	162	#define HPSA_READ 0xa8
	163	#define HPSA_WRITE 0xaa
	164	#endif
	165
	166	#define HPSA_READ 0x28 /* Read(10) */
	167	#define HPSA_WRITE 0x2a /* Write(10) */
	168
	169	/* BMIC commands */
	170	#define BMIC_READ 0x26
	171	#define BMIC_WRITE 0x27
	172	#define BMIC_CACHE_FLUSH 0xc2
	173	#define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */
	174
	175	/* Command List Structure */
	176	union SCSI3Addr {
	177	struct {
01a02ffc SC	178	u8 Dev;
	179	u8 Bus:6;
	180	u8 Mode:2; /* b00 */
edd16368 SC	181	} PeripDev;
edd16368 SC	182	struct {
01a02ffc SC	183	u8 DevLSB;
	184	u8 DevMSB:6;
	185	u8 Mode:2; /* b01 */
edd16368 SC	186	} LogDev;
edd16368 SC	187	struct {
01a02ffc SC	188	u8 Dev:5;
	189	u8 Bus:3;
	190	u8 Targ:6;
	191	u8 Mode:2; /* b10 */
edd16368 SC	192	} LogUnit;
	193	};
	194
	195	struct PhysDevAddr {
01a02ffc SC	196	u32 TargetId:24;
	197	u32 Bus:6;
	198	u32 Mode:2;
edd16368 SC	199	/* 2 level target device addr */
	200	union SCSI3Addr Target[2];
	201	};
	202
	203	struct LogDevAddr {
01a02ffc SC	204	u32 VolId:30;
	205	u32 Mode:2;
	206	u8 reserved[4];
edd16368 SC	207	};
	208
	209	union LUNAddr {
01a02ffc	210	u8 LunAddrBytes[8];
edd16368 SC	211	union SCSI3Addr SCSI3Lun[4];
	212	struct PhysDevAddr PhysDev;
	213	struct LogDevAddr LogDev;
	214	};
	215
	216	struct CommandListHeader {
01a02ffc SC	217	u8 ReplyQueue;
	218	u8 SGList;
	219	u16 SGTotal;
edd16368 SC	220	struct vals32 Tag;
	221	union LUNAddr LUN;
	222	};
	223
	224	struct RequestBlock {
01a02ffc	225	u8 CDBLen;
edd16368	226	struct {
01a02ffc SC	227	u8 Type:3;
	228	u8 Attribute:3;
	229	u8 Direction:2;
edd16368	230	} Type;
01a02ffc SC	231	u16 Timeout;
01a02ffc SC	232	u8 CDB[16];
edd16368 SC	233	};
	234
	235	struct ErrDescriptor {
	236	struct vals32 Addr;
01a02ffc	237	u32 Len;
edd16368 SC	238	};
	239
	240	struct SGDescriptor {
	241	struct vals32 Addr;
01a02ffc SC	242	u32 Len;
01a02ffc SC	243	u32 Ext;
edd16368 SC	244	};
	245
	246	union MoreErrInfo {
	247	struct {
01a02ffc SC	248	u8 Reserved[3];
	249	u8 Type;
	250	u32 ErrorInfo;
edd16368 SC	251	} Common_Info;
edd16368 SC	252	struct {
01a02ffc SC	253	u8 Reserved[2];
	254	u8 offense_size; /* size of offending entry */
	255	u8 offense_num; /* byte # of offense 0-base */
	256	u32 offense_value;
edd16368 SC	257	} Invalid_Cmd;
	258	};
	259	struct ErrorInfo {
01a02ffc SC	260	u8 ScsiStatus;
	261	u8 SenseLen;
	262	u16 CommandStatus;
	263	u32 ResidualCnt;
edd16368	264	union MoreErrInfo MoreErrInfo;
01a02ffc	265	u8 SenseInfo[SENSEINFOBYTES];
edd16368 SC	266	};
	267	/* Command types */
	268	#define CMD_IOCTL_PEND 0x01
	269	#define CMD_SCSI 0x03
	270
303932fd DB	271	/* This structure needs to be divisible by 32 for new
	272	* indexing method and performant mode.
	273	*/
	274	#define PAD32 32
	275	#define PAD64DIFF 0
	276	#define USEEXTRA ((sizeof(void *) - 4)/4)
	277	#define PADSIZE (PAD32 + PAD64DIFF * USEEXTRA)
	278
	279	#define DIRECT_LOOKUP_SHIFT 5
	280	#define DIRECT_LOOKUP_BIT 0x10
	281
	282	#define HPSA_ERROR_BIT 0x02
edd16368	283	struct ctlr_info; /* defined in hpsa.h */
303932fd DB	284	/* The size of this structure needs to be divisible by 32
	285	* on all architectures because low 5 bits of the addresses
	286	* are used as follows:
	287	*
	288	* bit 0: to device, used to indicate "performant mode" command
	289	* from device, indidcates error status.
	290	* bit 1-3: to device, indicates block fetch table entry for
	291	* reducing DMA in fetching commands from host memory.
	292	* bit 4: used to indicate whether tag is "direct lookup" (index),
	293	* or a bus address.
edd16368	294	*/
303932fd	295
edd16368 SC	296	struct CommandList {
	297	struct CommandListHeader Header;
	298	struct RequestBlock Request;
	299	struct ErrDescriptor ErrDesc;
	300	struct SGDescriptor SG[MAXSGENTRIES];
	301	/* information associated with the command */
01a02ffc	302	u32 busaddr; /* physical addr of this record */
edd16368 SC	303	struct ErrorInfo err_info; / pointer to the allocated mem */
	304	struct ctlr_info *h;
	305	int cmd_type;
	306	long cmdindex;
	307	struct hlist_node list;
	308	struct CommandList *prev;
	309	struct CommandList *next;
	310	struct request *rq;
	311	struct completion *waiting;
	312	int retry_count;
	313	void *scsi_cmd;
303932fd DB	314
303932fd DB	315	/* on 64 bit architectures, to get this to be 32-byte-aligned
db61bfcf SC	316	* it so happens we need PAD_64 bytes of padding, on 32 bit systems,
	317	* we need PAD_32 bytes of padding (see below). This does that.
	318	* If it happens that 64 bit and 32 bit systems need different
	319	* padding, PAD_32 and PAD_64 can be set independently, and.
	320	* the code below will do the right thing.
303932fd	321	*/
db61bfcf SC	322	#define IS_32_BIT ((8 - sizeof(long))/4)
	323	#define IS_64_BIT (!IS_32_BIT)
	324	#define PAD_32 (8)
	325	#define PAD_64 (0)
	326	#define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
303932fd	327	u8 pad[COMMANDLIST_PAD];
edd16368 SC	328	};
	329
	330	/* Configuration Table Structure */
	331	struct HostWrite {
01a02ffc SC	332	u32 TransportRequest;
	333	u32 Reserved;
	334	u32 CoalIntDelay;
	335	u32 CoalIntCount;
edd16368 SC	336	};
edd16368 SC	337
303932fd DB	338	#define SIMPLE_MODE 0x02
	339	#define PERFORMANT_MODE 0x04
	340	#define MEMQ_MODE 0x08
	341
edd16368	342	struct CfgTable {
303932fd DB	343	u8 Signature[4];
	344	u32 SpecValence;
	345	u32 TransportSupport;
	346	u32 TransportActive;
	347	struct HostWrite HostWrite;
	348	u32 CmdsOutMax;
	349	u32 BusTypes;
	350	u32 TransMethodOffset;
	351	u8 ServerName[16];
	352	u32 HeartBeat;
	353	u32 SCSI_Prefetch;
	354	u32 MaxScatterGatherElements;
	355	u32 MaxLogicalUnits;
	356	u32 MaxPhysicalDevices;
	357	u32 MaxPhysicalDrivesPerLogicalUnit;
	358	u32 MaxPerformantModeCommands;
	359	};
	360
	361	#define NUM_BLOCKFETCH_ENTRIES 8
	362	struct TransTable_struct {
	363	u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES];
	364	u32 RepQSize;
	365	u32 RepQCount;
	366	u32 RepQCtrAddrLow32;
	367	u32 RepQCtrAddrHigh32;
	368	u32 RepQAddr0Low32;
	369	u32 RepQAddr0High32;
edd16368 SC	370	};
	371
	372	struct hpsa_pci_info {
	373	unsigned char bus;
	374	unsigned char dev_fn;
	375	unsigned short domain;
01a02ffc	376	u32 board_id;
edd16368 SC	377	};
	378
	379	#pragma pack()
	380	#endif /* HPSA_CMD_H */