projects / deliverable / linux.git / blame
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|---|---|---|
| 6f231dda DW |
1 | /* |
| 2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
| 3 | * redistributing this file, you may do so under either license. | |
| 4 | * | |
| 5 | * GPL LICENSE SUMMARY | |
| 6 | * | |
| 7 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify | |
| 10 | * it under the terms of version 2 of the GNU General Public License as | |
| 11 | * published by the Free Software Foundation. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, but | |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 16 | * General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
| 21 | * The full GNU General Public License is included in this distribution | |
| 22 | * in the file called LICENSE.GPL. | |
| 23 | * | |
| 24 | * BSD LICENSE | |
| 25 | * | |
| 26 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. | |
| 27 | * All rights reserved. | |
| 28 | * | |
| 29 | * Redistribution and use in source and binary forms, with or without | |
| 30 | * modification, are permitted provided that the following conditions | |
| 31 | * are met: | |
| 32 | * | |
| 33 | * * Redistributions of source code must retain the above copyright | |
| 34 | * notice, this list of conditions and the following disclaimer. | |
| 35 | * * Redistributions in binary form must reproduce the above copyright | |
| 36 | * notice, this list of conditions and the following disclaimer in | |
| 37 | * the documentation and/or other materials provided with the | |
| 38 | * distribution. | |
| 39 | * * Neither the name of Intel Corporation nor the names of its | |
| 40 | * contributors may be used to endorse or promote products derived | |
| 41 | * from this software without specific prior written permission. | |
| 42 | * | |
| 43 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| 44 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| 45 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| 46 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| 47 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| 48 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| 49 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| 50 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| 51 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 52 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| 53 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 54 | */ | |
| 55 | ||
| 56 | #ifndef _SCI_BASE_PORT_H_ | |
| 57 | #define _SCI_BASE_PORT_H_ | |
| 58 | ||
| 59 | #include "sci_base_state_machine.h" | |
| 60 | #include "sci_object.h" | |
| 61 | ||
| 62 | /** | |
| 63 | * enum sci_base_port_states - This enumeration depicts all the states for the | |
| 64 | * common port state machine. | |
| 65 | * | |
| 66 | * | |
| 67 | */ | |
| 68 | enum sci_base_port_states { | |
| 69 | /** | |
| 70 | * This state indicates that the port has successfully been stopped. | |
| 71 | * In this state no new IO operations are permitted. | |
| 72 | * This state is entered from the STOPPING state. | |
| 73 | */ | |
| 74 | SCI_BASE_PORT_STATE_STOPPED, | |
| 75 | ||
| 76 | /** | |
| 77 | * This state indicates that the port is in the process of stopping. | |
| 78 | * In this state no new IO operations are permitted, but existing IO | |
| 79 | * operations are allowed to complete. | |
| 80 | * This state is entered from the READY state. | |
| 81 | */ | |
| 82 | SCI_BASE_PORT_STATE_STOPPING, | |
| 83 | ||
| 84 | /** | |
| 85 | * This state indicates the port is now ready. Thus, the user is | |
| 86 | * able to perform IO operations on this port. | |
| 87 | * This state is entered from the STARTING state. | |
| 88 | */ | |
| 89 | SCI_BASE_PORT_STATE_READY, | |
| 90 | ||
| 91 | /** | |
| 92 | * This state indicates the port is in the process of performing a hard | |
| 93 | * reset. Thus, the user is unable to perform IO operations on this | |
| 94 | * port. | |
| 95 | * This state is entered from the READY state. | |
| 96 | */ | |
| 97 | SCI_BASE_PORT_STATE_RESETTING, | |
| 98 | ||
| 99 | /** | |
| 100 | * This state indicates the port has failed a reset request. This state | |
| 101 | * is entered when a port reset request times out. | |
| 102 | * This state is entered from the RESETTING state. | |
| 103 | */ | |
| 104 | SCI_BASE_PORT_STATE_FAILED, | |
| 105 | ||
| 106 | SCI_BASE_PORT_MAX_STATES | |
| 107 | ||
| 108 | }; | |
| 109 | ||
| 110 | /** | |
| 111 | * struct sci_base_port - The base port object abstracts the fields common to | |
| 112 | * all SCI port objects. | |
| 113 | * | |
| 114 | * | |
| 115 | */ | |
| 116 | struct sci_base_port { | |
| 117 | /** | |
| 118 | * The field specifies that the parent object for the base controller | |
| 119 | * is the base object itself. | |
| 120 | */ | |
| 121 | struct sci_base_object parent; | |
| 122 | ||
| 123 | /** | |
| 124 | * This field contains the information for the base port state machine. | |
| 125 | */ | |
| 126 | struct sci_base_state_machine state_machine; | |
| 127 | }; | |
| 128 | ||
| 129 | struct sci_base_phy; | |
| 130 | ||
| 131 | typedef enum sci_status (*SCI_BASE_PORT_HANDLER_T)( | |
| 132 | struct sci_base_port * | |
| 133 | ); | |
| 134 | ||
| 135 | typedef enum sci_status (*SCI_BASE_PORT_PHY_HANDLER_T)( | |
| 136 | struct sci_base_port *, | |
| 137 | struct sci_base_phy * | |
| 138 | ); | |
| 139 | ||
| 140 | typedef enum sci_status (*SCI_BASE_PORT_RESET_HANDLER_T)( | |
| 141 | struct sci_base_port *, | |
| 142 | u32 timeout | |
| 143 | ); | |
| 144 | ||
| 145 | /** | |
| 146 | * struct sci_base_port_state_handler - This structure contains all of the | |
| 147 | * state handler methods common to base port state machines. Handler | |
| 148 | * methods provide the ability to change the behavior for user requests or | |
| 149 | * transitions depending on the state the machine is in. | |
| 150 | * | |
| 151 | * | |
| 152 | */ | |
| 153 | struct sci_base_port_state_handler { | |
| 154 | /** | |
| 155 | * The start_handler specifies the method invoked when a user attempts to | |
| 156 | * start a port. | |
| 157 | */ | |
| 158 | SCI_BASE_PORT_HANDLER_T start_handler; | |
| 159 | ||
| 160 | /** | |
| 161 | * The stop_handler specifies the method invoked when a user attempts to | |
| 162 | * stop a port. | |
| 163 | */ | |
| 164 | SCI_BASE_PORT_HANDLER_T stop_handler; | |
| 165 | ||
| 166 | /** | |
| 167 | * The destruct_handler specifies the method invoked when attempting to | |
| 168 | * destruct a port. | |
| 169 | */ | |
| 170 | SCI_BASE_PORT_HANDLER_T destruct_handler; | |
| 171 | ||
| 172 | /** | |
| 173 | * The reset_handler specifies the method invoked when a user attempts to | |
| 174 | * hard reset a port. | |
| 175 | */ | |
| 176 | SCI_BASE_PORT_RESET_HANDLER_T reset_handler; | |
| 177 | ||
| 178 | /** | |
| 179 | * The add_phy_handler specifies the method invoked when a user attempts to | |
| 180 | * add another phy into the port. | |
| 181 | */ | |
| 182 | SCI_BASE_PORT_PHY_HANDLER_T add_phy_handler; | |
| 183 | ||
| 184 | /** | |
| 185 | * The remove_phy_handler specifies the method invoked when a user | |
| 186 | * attempts to remove a phy from the port. | |
| 187 | */ | |
| 188 | SCI_BASE_PORT_PHY_HANDLER_T remove_phy_handler; | |
| 189 | ||
| 190 | }; | |
| 6f231dda | 191 | #endif /* _SCI_BASE_PORT_H_ */ |