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6f231dda DW |
1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
3 | * redistributing this file, you may do so under either license. | |
4 | * | |
5 | * GPL LICENSE SUMMARY | |
6 | * | |
7 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of version 2 of the GNU General Public License as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * BSD LICENSE | |
25 | * | |
26 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. | |
27 | * All rights reserved. | |
28 | * | |
29 | * Redistribution and use in source and binary forms, with or without | |
30 | * modification, are permitted provided that the following conditions | |
31 | * are met: | |
32 | * | |
33 | * * Redistributions of source code must retain the above copyright | |
34 | * notice, this list of conditions and the following disclaimer. | |
35 | * * Redistributions in binary form must reproduce the above copyright | |
36 | * notice, this list of conditions and the following disclaimer in | |
37 | * the documentation and/or other materials provided with the | |
38 | * distribution. | |
39 | * * Neither the name of Intel Corporation nor the names of its | |
40 | * contributors may be used to endorse or promote products derived | |
41 | * from this software without specific prior written permission. | |
42 | * | |
43 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
44 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
45 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
46 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
47 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
48 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
49 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
50 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
51 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
52 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
53 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
54 | */ | |
55 | ||
56 | #include <linux/device.h> | |
f2f30080 | 57 | #include <scsi/sas.h> |
6f231dda DW |
58 | #include "scic_controller.h" |
59 | #include "scic_phy.h" | |
60 | #include "scic_port.h" | |
6f231dda | 61 | #include "scic_sds_controller.h" |
bc99aa47 | 62 | #include "scu_registers.h" |
6f231dda DW |
63 | #include "scic_sds_phy.h" |
64 | #include "scic_sds_port_configuration_agent.h" | |
65 | #include "scic_sds_port.h" | |
88f3b62a | 66 | #include "remote_device.h" |
6f231dda | 67 | #include "scic_sds_request.h" |
6f231dda DW |
68 | #include "sci_environment.h" |
69 | #include "sci_util.h" | |
70 | #include "scu_completion_codes.h" | |
71 | #include "scu_constants.h" | |
72 | #include "scu_event_codes.h" | |
73 | #include "scu_remote_node_context.h" | |
74 | #include "scu_task_context.h" | |
75 | #include "scu_unsolicited_frame.h" | |
76 | ||
77 | #define SCU_CONTEXT_RAM_INIT_STALL_TIME 200 | |
78 | ||
79 | /** | |
80 | * smu_dcc_get_max_ports() - | |
81 | * | |
82 | * This macro returns the maximum number of logical ports supported by the | |
83 | * hardware. The caller passes in the value read from the device context | |
84 | * capacity register and this macro will mash and shift the value appropriately. | |
85 | */ | |
86 | #define smu_dcc_get_max_ports(dcc_value) \ | |
87 | (\ | |
88 | (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \ | |
89 | >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \ | |
90 | ) | |
91 | ||
92 | /** | |
93 | * smu_dcc_get_max_task_context() - | |
94 | * | |
95 | * This macro returns the maximum number of task contexts supported by the | |
96 | * hardware. The caller passes in the value read from the device context | |
97 | * capacity register and this macro will mash and shift the value appropriately. | |
98 | */ | |
99 | #define smu_dcc_get_max_task_context(dcc_value) \ | |
100 | (\ | |
101 | (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \ | |
102 | >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \ | |
103 | ) | |
104 | ||
105 | /** | |
106 | * smu_dcc_get_max_remote_node_context() - | |
107 | * | |
108 | * This macro returns the maximum number of remote node contexts supported by | |
109 | * the hardware. The caller passes in the value read from the device context | |
110 | * capacity register and this macro will mash and shift the value appropriately. | |
111 | */ | |
112 | #define smu_dcc_get_max_remote_node_context(dcc_value) \ | |
113 | (\ | |
114 | (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \ | |
115 | >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \ | |
116 | ) | |
117 | ||
118 | ||
119 | static void scic_sds_controller_power_control_timer_handler( | |
120 | void *controller); | |
121 | #define SCIC_SDS_CONTROLLER_MIN_TIMER_COUNT 3 | |
122 | #define SCIC_SDS_CONTROLLER_MAX_TIMER_COUNT 3 | |
123 | ||
124 | /** | |
125 | * | |
126 | * | |
127 | * The number of milliseconds to wait for a phy to start. | |
128 | */ | |
129 | #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 100 | |
130 | ||
131 | /** | |
132 | * | |
133 | * | |
134 | * The number of milliseconds to wait while a given phy is consuming power | |
135 | * before allowing another set of phys to consume power. Ultimately, this will | |
136 | * be specified by OEM parameter. | |
137 | */ | |
138 | #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500 | |
139 | ||
140 | /** | |
141 | * COMPLETION_QUEUE_CYCLE_BIT() - | |
142 | * | |
143 | * This macro will return the cycle bit of the completion queue entry | |
144 | */ | |
145 | #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000) | |
146 | ||
147 | /** | |
148 | * NORMALIZE_GET_POINTER() - | |
149 | * | |
150 | * This macro will normalize the completion queue get pointer so its value can | |
151 | * be used as an index into an array | |
152 | */ | |
153 | #define NORMALIZE_GET_POINTER(x) \ | |
154 | ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK) | |
155 | ||
156 | /** | |
157 | * NORMALIZE_PUT_POINTER() - | |
158 | * | |
159 | * This macro will normalize the completion queue put pointer so its value can | |
160 | * be used as an array inde | |
161 | */ | |
162 | #define NORMALIZE_PUT_POINTER(x) \ | |
163 | ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK) | |
164 | ||
165 | ||
166 | /** | |
167 | * NORMALIZE_GET_POINTER_CYCLE_BIT() - | |
168 | * | |
169 | * This macro will normalize the completion queue cycle pointer so it matches | |
170 | * the completion queue cycle bit | |
171 | */ | |
172 | #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \ | |
173 | ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT)) | |
174 | ||
175 | /** | |
176 | * NORMALIZE_EVENT_POINTER() - | |
177 | * | |
178 | * This macro will normalize the completion queue event entry so its value can | |
179 | * be used as an index. | |
180 | */ | |
181 | #define NORMALIZE_EVENT_POINTER(x) \ | |
182 | (\ | |
183 | ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \ | |
184 | >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \ | |
185 | ) | |
186 | ||
187 | /** | |
188 | * INCREMENT_COMPLETION_QUEUE_GET() - | |
189 | * | |
190 | * This macro will increment the controllers completion queue index value and | |
191 | * possibly toggle the cycle bit if the completion queue index wraps back to 0. | |
192 | */ | |
193 | #define INCREMENT_COMPLETION_QUEUE_GET(controller, index, cycle) \ | |
194 | INCREMENT_QUEUE_GET(\ | |
195 | (index), \ | |
196 | (cycle), \ | |
197 | (controller)->completion_queue_entries, \ | |
198 | SMU_CQGR_CYCLE_BIT \ | |
199 | ) | |
200 | ||
201 | /** | |
202 | * INCREMENT_EVENT_QUEUE_GET() - | |
203 | * | |
204 | * This macro will increment the controllers event queue index value and | |
205 | * possibly toggle the event cycle bit if the event queue index wraps back to 0. | |
206 | */ | |
207 | #define INCREMENT_EVENT_QUEUE_GET(controller, index, cycle) \ | |
208 | INCREMENT_QUEUE_GET(\ | |
209 | (index), \ | |
210 | (cycle), \ | |
211 | (controller)->completion_event_entries, \ | |
212 | SMU_CQGR_EVENT_CYCLE_BIT \ | |
213 | ) | |
214 | ||
35173d57 | 215 | static void scic_sds_controller_initialize_power_control(struct scic_sds_controller *scic) |
6f231dda | 216 | { |
cc3dbd0a | 217 | struct isci_host *ihost = scic_to_ihost(scic); |
35173d57 DW |
218 | scic->power_control.timer = isci_timer_create(ihost, |
219 | scic, | |
220 | scic_sds_controller_power_control_timer_handler); | |
6f231dda | 221 | |
35173d57 | 222 | memset(scic->power_control.requesters, 0, |
09d7da13 | 223 | sizeof(scic->power_control.requesters)); |
6f231dda | 224 | |
09d7da13 DJ |
225 | scic->power_control.phys_waiting = 0; |
226 | scic->power_control.phys_granted_power = 0; | |
6f231dda DW |
227 | } |
228 | ||
bc5c9674 | 229 | int scic_controller_mem_init(struct scic_sds_controller *scic) |
6f231dda | 230 | { |
bc5c9674 CH |
231 | struct device *dev = scic_to_dev(scic); |
232 | dma_addr_t dma_handle; | |
233 | enum sci_status result; | |
6f231dda | 234 | |
bc5c9674 CH |
235 | scic->completion_queue = dmam_alloc_coherent(dev, |
236 | scic->completion_queue_entries * sizeof(u32), | |
237 | &dma_handle, GFP_KERNEL); | |
238 | if (!scic->completion_queue) | |
239 | return -ENOMEM; | |
240 | ||
241 | writel(lower_32_bits(dma_handle), | |
242 | &scic->smu_registers->completion_queue_lower); | |
243 | writel(upper_32_bits(dma_handle), | |
244 | &scic->smu_registers->completion_queue_upper); | |
245 | ||
246 | scic->remote_node_context_table = dmam_alloc_coherent(dev, | |
247 | scic->remote_node_entries * | |
248 | sizeof(union scu_remote_node_context), | |
249 | &dma_handle, GFP_KERNEL); | |
250 | if (!scic->remote_node_context_table) | |
251 | return -ENOMEM; | |
252 | ||
253 | writel(lower_32_bits(dma_handle), | |
254 | &scic->smu_registers->remote_node_context_lower); | |
255 | writel(upper_32_bits(dma_handle), | |
256 | &scic->smu_registers->remote_node_context_upper); | |
257 | ||
258 | scic->task_context_table = dmam_alloc_coherent(dev, | |
259 | scic->task_context_entries * | |
260 | sizeof(struct scu_task_context), | |
261 | &dma_handle, GFP_KERNEL); | |
262 | if (!scic->task_context_table) | |
263 | return -ENOMEM; | |
264 | ||
265 | writel(lower_32_bits(dma_handle), | |
266 | &scic->smu_registers->host_task_table_lower); | |
267 | writel(upper_32_bits(dma_handle), | |
268 | &scic->smu_registers->host_task_table_upper); | |
269 | ||
270 | result = scic_sds_unsolicited_frame_control_construct(scic); | |
271 | if (result) | |
272 | return result; | |
6f231dda DW |
273 | |
274 | /* | |
275 | * Inform the silicon as to the location of the UF headers and | |
bc99aa47 CH |
276 | * address table. |
277 | */ | |
bc5c9674 CH |
278 | writel(lower_32_bits(scic->uf_control.headers.physical_address), |
279 | &scic->scu_registers->sdma.uf_header_base_address_lower); | |
280 | writel(upper_32_bits(scic->uf_control.headers.physical_address), | |
281 | &scic->scu_registers->sdma.uf_header_base_address_upper); | |
282 | ||
283 | writel(lower_32_bits(scic->uf_control.address_table.physical_address), | |
284 | &scic->scu_registers->sdma.uf_address_table_lower); | |
285 | writel(upper_32_bits(scic->uf_control.address_table.physical_address), | |
286 | &scic->scu_registers->sdma.uf_address_table_upper); | |
bc99aa47 | 287 | |
bc5c9674 | 288 | return 0; |
6f231dda DW |
289 | } |
290 | ||
291 | /** | |
292 | * This method initializes the task context data for the controller. | |
e2023b87 | 293 | * @scic: |
6f231dda DW |
294 | * |
295 | */ | |
bc99aa47 CH |
296 | static void |
297 | scic_sds_controller_assign_task_entries(struct scic_sds_controller *controller) | |
6f231dda DW |
298 | { |
299 | u32 task_assignment; | |
300 | ||
301 | /* | |
302 | * Assign all the TCs to function 0 | |
bc99aa47 CH |
303 | * TODO: Do we actually need to read this register to write it back? |
304 | */ | |
6f231dda DW |
305 | |
306 | task_assignment = | |
bc99aa47 CH |
307 | readl(&controller->smu_registers->task_context_assignment[0]); |
308 | ||
309 | task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) | | |
310 | (SMU_TCA_GEN_VAL(ENDING, controller->task_context_entries - 1)) | | |
311 | (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE)); | |
312 | ||
313 | writel(task_assignment, | |
314 | &controller->smu_registers->task_context_assignment[0]); | |
6f231dda | 315 | |
6f231dda DW |
316 | } |
317 | ||
318 | /** | |
319 | * This method initializes the hardware completion queue. | |
320 | * | |
321 | * | |
322 | */ | |
35173d57 | 323 | static void scic_sds_controller_initialize_completion_queue( |
e2023b87 | 324 | struct scic_sds_controller *scic) |
6f231dda DW |
325 | { |
326 | u32 index; | |
327 | u32 completion_queue_control_value; | |
328 | u32 completion_queue_get_value; | |
329 | u32 completion_queue_put_value; | |
330 | ||
e2023b87 | 331 | scic->completion_queue_get = 0; |
6f231dda DW |
332 | |
333 | completion_queue_control_value = ( | |
e2023b87 DJ |
334 | SMU_CQC_QUEUE_LIMIT_SET(scic->completion_queue_entries - 1) |
335 | | SMU_CQC_EVENT_LIMIT_SET(scic->completion_event_entries - 1) | |
6f231dda DW |
336 | ); |
337 | ||
bc99aa47 | 338 | writel(completion_queue_control_value, |
e2023b87 | 339 | &scic->smu_registers->completion_queue_control); |
bc99aa47 | 340 | |
6f231dda DW |
341 | |
342 | /* Set the completion queue get pointer and enable the queue */ | |
343 | completion_queue_get_value = ( | |
344 | (SMU_CQGR_GEN_VAL(POINTER, 0)) | |
345 | | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0)) | |
346 | | (SMU_CQGR_GEN_BIT(ENABLE)) | |
347 | | (SMU_CQGR_GEN_BIT(EVENT_ENABLE)) | |
348 | ); | |
349 | ||
bc99aa47 | 350 | writel(completion_queue_get_value, |
e2023b87 | 351 | &scic->smu_registers->completion_queue_get); |
6f231dda DW |
352 | |
353 | /* Set the completion queue put pointer */ | |
354 | completion_queue_put_value = ( | |
355 | (SMU_CQPR_GEN_VAL(POINTER, 0)) | |
356 | | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0)) | |
357 | ); | |
358 | ||
bc99aa47 | 359 | writel(completion_queue_put_value, |
e2023b87 | 360 | &scic->smu_registers->completion_queue_put); |
6f231dda DW |
361 | |
362 | /* Initialize the cycle bit of the completion queue entries */ | |
e2023b87 | 363 | for (index = 0; index < scic->completion_queue_entries; index++) { |
6f231dda DW |
364 | /* |
365 | * If get.cycle_bit != completion_queue.cycle_bit | |
366 | * its not a valid completion queue entry | |
367 | * so at system start all entries are invalid */ | |
e2023b87 | 368 | scic->completion_queue[index] = 0x80000000; |
6f231dda DW |
369 | } |
370 | } | |
371 | ||
372 | /** | |
373 | * This method initializes the hardware unsolicited frame queue. | |
374 | * | |
375 | * | |
376 | */ | |
35173d57 | 377 | static void scic_sds_controller_initialize_unsolicited_frame_queue( |
e2023b87 | 378 | struct scic_sds_controller *scic) |
6f231dda DW |
379 | { |
380 | u32 frame_queue_control_value; | |
381 | u32 frame_queue_get_value; | |
382 | u32 frame_queue_put_value; | |
383 | ||
384 | /* Write the queue size */ | |
385 | frame_queue_control_value = | |
e2023b87 DJ |
386 | SCU_UFQC_GEN_VAL(QUEUE_SIZE, |
387 | scic->uf_control.address_table.count); | |
6f231dda | 388 | |
bc99aa47 | 389 | writel(frame_queue_control_value, |
e2023b87 | 390 | &scic->scu_registers->sdma.unsolicited_frame_queue_control); |
6f231dda DW |
391 | |
392 | /* Setup the get pointer for the unsolicited frame queue */ | |
393 | frame_queue_get_value = ( | |
394 | SCU_UFQGP_GEN_VAL(POINTER, 0) | |
395 | | SCU_UFQGP_GEN_BIT(ENABLE_BIT) | |
396 | ); | |
397 | ||
bc99aa47 | 398 | writel(frame_queue_get_value, |
e2023b87 | 399 | &scic->scu_registers->sdma.unsolicited_frame_get_pointer); |
6f231dda DW |
400 | /* Setup the put pointer for the unsolicited frame queue */ |
401 | frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0); | |
bc99aa47 | 402 | writel(frame_queue_put_value, |
e2023b87 | 403 | &scic->scu_registers->sdma.unsolicited_frame_put_pointer); |
6f231dda DW |
404 | } |
405 | ||
406 | /** | |
407 | * This method enables the hardware port task scheduler. | |
408 | * | |
409 | * | |
410 | */ | |
35173d57 | 411 | static void scic_sds_controller_enable_port_task_scheduler( |
e2023b87 | 412 | struct scic_sds_controller *scic) |
6f231dda DW |
413 | { |
414 | u32 port_task_scheduler_value; | |
415 | ||
bc99aa47 | 416 | port_task_scheduler_value = |
e2023b87 | 417 | readl(&scic->scu_registers->peg0.ptsg.control); |
6f231dda | 418 | port_task_scheduler_value |= |
e2023b87 DJ |
419 | (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) | |
420 | SCU_PTSGCR_GEN_BIT(PTSG_ENABLE)); | |
bc99aa47 | 421 | writel(port_task_scheduler_value, |
e2023b87 | 422 | &scic->scu_registers->peg0.ptsg.control); |
6f231dda DW |
423 | } |
424 | ||
6f231dda DW |
425 | /** |
426 | * | |
427 | * | |
428 | * This macro is used to delay between writes to the AFE registers during AFE | |
429 | * initialization. | |
430 | */ | |
431 | #define AFE_REGISTER_WRITE_DELAY 10 | |
432 | ||
6f231dda DW |
433 | /* Initialize the AFE for this phy index. We need to read the AFE setup from |
434 | * the OEM parameters none | |
435 | */ | |
35173d57 | 436 | static void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic) |
6f231dda | 437 | { |
4711ba10 | 438 | const struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1; |
6f231dda DW |
439 | u32 afe_status; |
440 | u32 phy_id; | |
441 | ||
442 | /* Clear DFX Status registers */ | |
bc99aa47 | 443 | writel(0x0081000f, &scic->scu_registers->afe.afe_dfx_master_control0); |
7392d275 | 444 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda | 445 | |
e76d8057 MP |
446 | if (is_b0()) { |
447 | /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement | |
448 | * Timer, PM Stagger Timer */ | |
449 | writel(0x0007BFFF, &scic->scu_registers->afe.afe_pmsn_master_control2); | |
450 | udelay(AFE_REGISTER_WRITE_DELAY); | |
451 | } | |
452 | ||
6f231dda DW |
453 | /* Configure bias currents to normal */ |
454 | if (is_a0()) | |
bc99aa47 | 455 | writel(0x00005500, &scic->scu_registers->afe.afe_bias_control); |
e76d8057 | 456 | else if (is_a2()) |
bc99aa47 | 457 | writel(0x00005A00, &scic->scu_registers->afe.afe_bias_control); |
e76d8057 MP |
458 | else if (is_b0()) |
459 | writel(0x00005F00, &scic->scu_registers->afe.afe_bias_control); | |
6f231dda | 460 | |
7392d275 | 461 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda DW |
462 | |
463 | /* Enable PLL */ | |
464 | if (is_b0()) | |
bc99aa47 | 465 | writel(0x80040A08, &scic->scu_registers->afe.afe_pll_control0); |
6f231dda | 466 | else |
bc99aa47 | 467 | writel(0x80040908, &scic->scu_registers->afe.afe_pll_control0); |
d9def184 | 468 | |
7392d275 | 469 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda DW |
470 | |
471 | /* Wait for the PLL to lock */ | |
472 | do { | |
bc99aa47 | 473 | afe_status = readl(&scic->scu_registers->afe.afe_common_block_status); |
7392d275 | 474 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda DW |
475 | } while ((afe_status & 0x00001000) == 0); |
476 | ||
e76d8057 | 477 | if (is_a0() || is_a2()) { |
6f231dda | 478 | /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */ |
bc99aa47 | 479 | writel(0x7bcc96ad, &scic->scu_registers->afe.afe_pmsn_master_control0); |
7392d275 | 480 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda DW |
481 | } |
482 | ||
483 | for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) { | |
4711ba10 DW |
484 | const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id]; |
485 | ||
6f231dda DW |
486 | if (is_b0()) { |
487 | /* Configure transmitter SSC parameters */ | |
bc99aa47 | 488 | writel(0x00030000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control); |
7392d275 | 489 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda DW |
490 | } else { |
491 | /* | |
492 | * All defaults, except the Receive Word Alignament/Comma Detect | |
493 | * Enable....(0xe800) */ | |
bc99aa47 | 494 | writel(0x00004512, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0); |
7392d275 | 495 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda | 496 | |
bc99aa47 | 497 | writel(0x0050100F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control1); |
7392d275 | 498 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda DW |
499 | } |
500 | ||
501 | /* | |
502 | * Power up TX and RX out from power down (PWRDNTX and PWRDNRX) | |
503 | * & increase TX int & ext bias 20%....(0xe85c) */ | |
504 | if (is_a0()) | |
bc99aa47 | 505 | writel(0x000003D4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); |
6f231dda | 506 | else if (is_a2()) |
bc99aa47 | 507 | writel(0x000003F0, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); |
6f231dda DW |
508 | else { |
509 | /* Power down TX and RX (PWRDNTX and PWRDNRX) */ | |
bc99aa47 | 510 | writel(0x000003d7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); |
7392d275 | 511 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda DW |
512 | |
513 | /* | |
514 | * Power up TX and RX out from power down (PWRDNTX and PWRDNRX) | |
515 | * & increase TX int & ext bias 20%....(0xe85c) */ | |
bc99aa47 | 516 | writel(0x000003d4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); |
6f231dda | 517 | } |
7392d275 | 518 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda DW |
519 | |
520 | if (is_a0() || is_a2()) { | |
521 | /* Enable TX equalization (0xe824) */ | |
bc99aa47 | 522 | writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control); |
7392d275 | 523 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda DW |
524 | } |
525 | ||
526 | /* | |
527 | * RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, TPD=0x0(TX Power On), | |
528 | * RDD=0x0(RX Detect Enabled) ....(0xe800) */ | |
bc99aa47 | 529 | writel(0x00004100, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0); |
7392d275 | 530 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda DW |
531 | |
532 | /* Leave DFE/FFE on */ | |
533 | if (is_a0()) | |
bc99aa47 | 534 | writel(0x3F09983F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0); |
6f231dda | 535 | else if (is_a2()) |
bc99aa47 | 536 | writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0); |
6f231dda | 537 | else { |
bc99aa47 | 538 | writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0); |
7392d275 | 539 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda | 540 | /* Enable TX equalization (0xe824) */ |
bc99aa47 | 541 | writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control); |
6f231dda | 542 | } |
7392d275 | 543 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda | 544 | |
bc99aa47 CH |
545 | writel(oem_phy->afe_tx_amp_control0, |
546 | &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control0); | |
7392d275 | 547 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda | 548 | |
bc99aa47 CH |
549 | writel(oem_phy->afe_tx_amp_control1, |
550 | &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control1); | |
7392d275 | 551 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda | 552 | |
bc99aa47 CH |
553 | writel(oem_phy->afe_tx_amp_control2, |
554 | &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control2); | |
7392d275 | 555 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda | 556 | |
bc99aa47 CH |
557 | writel(oem_phy->afe_tx_amp_control3, |
558 | &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control3); | |
7392d275 | 559 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda DW |
560 | } |
561 | ||
562 | /* Transfer control to the PEs */ | |
bc99aa47 | 563 | writel(0x00010f00, &scic->scu_registers->afe.afe_dfx_master_control0); |
7392d275 | 564 | udelay(AFE_REGISTER_WRITE_DELAY); |
6f231dda DW |
565 | } |
566 | ||
567 | /* | |
568 | * ****************************************************************************- | |
569 | * * SCIC SDS Controller Internal Start/Stop Routines | |
570 | * ****************************************************************************- */ | |
571 | ||
572 | ||
573 | /** | |
574 | * This method will attempt to transition into the ready state for the | |
575 | * controller and indicate that the controller start operation has completed | |
576 | * if all criteria are met. | |
e2023b87 | 577 | * @scic: This parameter indicates the controller object for which |
6f231dda DW |
578 | * to transition to ready. |
579 | * @status: This parameter indicates the status value to be pass into the call | |
580 | * to scic_cb_controller_start_complete(). | |
581 | * | |
582 | * none. | |
583 | */ | |
584 | static void scic_sds_controller_transition_to_ready( | |
09d7da13 | 585 | struct scic_sds_controller *scic, |
6f231dda DW |
586 | enum sci_status status) |
587 | { | |
cc3dbd0a | 588 | struct isci_host *ihost = scic_to_ihost(scic); |
09d7da13 | 589 | |
ca841f0e CH |
590 | if (scic->state_machine.current_state_id == |
591 | SCI_BASE_CONTROLLER_STATE_STARTING) { | |
6f231dda DW |
592 | /* |
593 | * We move into the ready state, because some of the phys/ports | |
09d7da13 DJ |
594 | * may be up and operational. |
595 | */ | |
ca841f0e | 596 | sci_base_state_machine_change_state(&scic->state_machine, |
068b2c03 | 597 | SCI_BASE_CONTROLLER_STATE_READY); |
6f231dda | 598 | |
09d7da13 | 599 | isci_host_start_complete(ihost, status); |
6f231dda DW |
600 | } |
601 | } | |
602 | ||
35173d57 | 603 | static void scic_sds_controller_timeout_handler(void *_scic) |
6f231dda | 604 | { |
09d7da13 | 605 | struct scic_sds_controller *scic = _scic; |
cc3dbd0a | 606 | struct isci_host *ihost = scic_to_ihost(scic); |
ca841f0e | 607 | struct sci_base_state_machine *sm = &scic->state_machine; |
6f231dda | 608 | |
068b2c03 DW |
609 | if (sm->current_state_id == SCI_BASE_CONTROLLER_STATE_STARTING) |
610 | scic_sds_controller_transition_to_ready(scic, SCI_FAILURE_TIMEOUT); | |
611 | else if (sm->current_state_id == SCI_BASE_CONTROLLER_STATE_STOPPING) { | |
612 | sci_base_state_machine_change_state(sm, SCI_BASE_CONTROLLER_STATE_FAILED); | |
09d7da13 | 613 | isci_host_stop_complete(ihost, SCI_FAILURE_TIMEOUT); |
6f231dda DW |
614 | } else /* / @todo Now what do we want to do in this case? */ |
615 | dev_err(scic_to_dev(scic), | |
616 | "%s: Controller timer fired when controller was not " | |
617 | "in a state being timed.\n", | |
618 | __func__); | |
619 | } | |
620 | ||
35173d57 | 621 | static enum sci_status scic_sds_controller_stop_ports(struct scic_sds_controller *scic) |
6f231dda DW |
622 | { |
623 | u32 index; | |
624 | enum sci_status port_status; | |
625 | enum sci_status status = SCI_SUCCESS; | |
e531381e | 626 | struct isci_host *ihost = scic_to_ihost(scic); |
6f231dda DW |
627 | |
628 | for (index = 0; index < scic->logical_port_entries; index++) { | |
e531381e | 629 | struct scic_sds_port *sci_port = &ihost->ports[index].sci; |
41e2b905 | 630 | scic_sds_port_handler_t stop; |
a8d4b9fe | 631 | |
41e2b905 MT |
632 | stop = sci_port->state_handlers->stop_handler; |
633 | port_status = stop(sci_port); | |
6f231dda DW |
634 | |
635 | if ((port_status != SCI_SUCCESS) && | |
636 | (port_status != SCI_FAILURE_INVALID_STATE)) { | |
637 | status = SCI_FAILURE; | |
638 | ||
639 | dev_warn(scic_to_dev(scic), | |
640 | "%s: Controller stop operation failed to " | |
641 | "stop port %d because of status %d.\n", | |
642 | __func__, | |
a8d4b9fe | 643 | sci_port->logical_port_index, |
6f231dda DW |
644 | port_status); |
645 | } | |
646 | } | |
647 | ||
648 | return status; | |
649 | } | |
650 | ||
09d7da13 DJ |
651 | static inline void scic_sds_controller_phy_timer_start( |
652 | struct scic_sds_controller *scic) | |
6f231dda | 653 | { |
09d7da13 DJ |
654 | isci_timer_start(scic->phy_startup_timer, |
655 | SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT); | |
6f231dda | 656 | |
09d7da13 | 657 | scic->phy_startup_timer_pending = true; |
6f231dda DW |
658 | } |
659 | ||
35173d57 | 660 | static void scic_sds_controller_phy_timer_stop(struct scic_sds_controller *scic) |
6f231dda | 661 | { |
09d7da13 | 662 | isci_timer_stop(scic->phy_startup_timer); |
6f231dda | 663 | |
09d7da13 | 664 | scic->phy_startup_timer_pending = false; |
6f231dda DW |
665 | } |
666 | ||
667 | /** | |
35173d57 DW |
668 | * scic_sds_controller_start_next_phy - start phy |
669 | * @scic: controller | |
6f231dda | 670 | * |
35173d57 DW |
671 | * If all the phys have been started, then attempt to transition the |
672 | * controller to the READY state and inform the user | |
673 | * (scic_cb_controller_start_complete()). | |
6f231dda | 674 | */ |
35173d57 | 675 | static enum sci_status scic_sds_controller_start_next_phy(struct scic_sds_controller *scic) |
6f231dda | 676 | { |
4b33981a | 677 | struct isci_host *ihost = scic_to_ihost(scic); |
07373a5c HD |
678 | struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1; |
679 | struct scic_sds_phy *sci_phy; | |
6f231dda DW |
680 | enum sci_status status; |
681 | ||
682 | status = SCI_SUCCESS; | |
683 | ||
07373a5c HD |
684 | if (scic->phy_startup_timer_pending) |
685 | return status; | |
6f231dda | 686 | |
07373a5c HD |
687 | if (scic->next_phy_to_start >= SCI_MAX_PHYS) { |
688 | bool is_controller_start_complete = true; | |
689 | u32 state; | |
690 | u8 index; | |
6f231dda | 691 | |
07373a5c | 692 | for (index = 0; index < SCI_MAX_PHYS; index++) { |
4b33981a | 693 | sci_phy = &ihost->phys[index].sci; |
d857d9a0 | 694 | state = sci_phy->state_machine.current_state_id; |
07373a5c HD |
695 | |
696 | if (!scic_sds_phy_get_port(sci_phy)) | |
697 | continue; | |
698 | ||
699 | /* The controller start operation is complete iff: | |
700 | * - all links have been given an opportunity to start | |
701 | * - have no indication of a connected device | |
702 | * - have an indication of a connected device and it has | |
703 | * finished the link training process. | |
704 | */ | |
705 | if ((sci_phy->is_in_link_training == false && | |
706 | state == SCI_BASE_PHY_STATE_INITIAL) || | |
707 | (sci_phy->is_in_link_training == false && | |
708 | state == SCI_BASE_PHY_STATE_STOPPED) || | |
709 | (sci_phy->is_in_link_training == true && | |
710 | state == SCI_BASE_PHY_STATE_STARTING)) { | |
711 | is_controller_start_complete = false; | |
712 | break; | |
6f231dda | 713 | } |
07373a5c | 714 | } |
6f231dda | 715 | |
07373a5c HD |
716 | /* |
717 | * The controller has successfully finished the start process. | |
718 | * Inform the SCI Core user and transition to the READY state. */ | |
719 | if (is_controller_start_complete == true) { | |
720 | scic_sds_controller_transition_to_ready(scic, SCI_SUCCESS); | |
721 | scic_sds_controller_phy_timer_stop(scic); | |
722 | } | |
723 | } else { | |
4b33981a | 724 | sci_phy = &ihost->phys[scic->next_phy_to_start].sci; |
07373a5c HD |
725 | |
726 | if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) { | |
727 | if (scic_sds_phy_get_port(sci_phy) == NULL) { | |
728 | scic->next_phy_to_start++; | |
729 | ||
730 | /* Caution recursion ahead be forwarned | |
731 | * | |
732 | * The PHY was never added to a PORT in MPC mode | |
733 | * so start the next phy in sequence This phy | |
734 | * will never go link up and will not draw power | |
735 | * the OEM parameters either configured the phy | |
736 | * incorrectly for the PORT or it was never | |
737 | * assigned to a PORT | |
738 | */ | |
739 | return scic_sds_controller_start_next_phy(scic); | |
6f231dda | 740 | } |
07373a5c | 741 | } |
6f231dda | 742 | |
07373a5c | 743 | status = scic_sds_phy_start(sci_phy); |
6f231dda | 744 | |
07373a5c HD |
745 | if (status == SCI_SUCCESS) { |
746 | scic_sds_controller_phy_timer_start(scic); | |
747 | } else { | |
748 | dev_warn(scic_to_dev(scic), | |
749 | "%s: Controller stop operation failed " | |
750 | "to stop phy %d because of status " | |
751 | "%d.\n", | |
752 | __func__, | |
4b33981a | 753 | ihost->phys[scic->next_phy_to_start].sci.phy_index, |
07373a5c | 754 | status); |
6f231dda | 755 | } |
07373a5c HD |
756 | |
757 | scic->next_phy_to_start++; | |
6f231dda DW |
758 | } |
759 | ||
760 | return status; | |
761 | } | |
762 | ||
35173d57 DW |
763 | static void scic_sds_controller_phy_startup_timeout_handler(void *_scic) |
764 | { | |
765 | struct scic_sds_controller *scic = _scic; | |
766 | enum sci_status status; | |
767 | ||
768 | scic->phy_startup_timer_pending = false; | |
769 | status = SCI_FAILURE; | |
770 | while (status != SCI_SUCCESS) | |
771 | status = scic_sds_controller_start_next_phy(scic); | |
772 | } | |
773 | ||
774 | static enum sci_status scic_sds_controller_initialize_phy_startup(struct scic_sds_controller *scic) | |
775 | { | |
cc3dbd0a | 776 | struct isci_host *ihost = scic_to_ihost(scic); |
35173d57 DW |
777 | |
778 | scic->phy_startup_timer = isci_timer_create(ihost, | |
779 | scic, | |
780 | scic_sds_controller_phy_startup_timeout_handler); | |
781 | ||
782 | if (scic->phy_startup_timer == NULL) | |
783 | return SCI_FAILURE_INSUFFICIENT_RESOURCES; | |
784 | else { | |
785 | scic->next_phy_to_start = 0; | |
786 | scic->phy_startup_timer_pending = false; | |
787 | } | |
788 | ||
789 | return SCI_SUCCESS; | |
790 | } | |
791 | ||
792 | static enum sci_status scic_sds_controller_stop_phys(struct scic_sds_controller *scic) | |
6f231dda DW |
793 | { |
794 | u32 index; | |
795 | enum sci_status status; | |
796 | enum sci_status phy_status; | |
4b33981a | 797 | struct isci_host *ihost = scic_to_ihost(scic); |
6f231dda DW |
798 | |
799 | status = SCI_SUCCESS; | |
800 | ||
801 | for (index = 0; index < SCI_MAX_PHYS; index++) { | |
4b33981a | 802 | phy_status = scic_sds_phy_stop(&ihost->phys[index].sci); |
6f231dda | 803 | |
4b33981a DW |
804 | if (phy_status != SCI_SUCCESS && |
805 | phy_status != SCI_FAILURE_INVALID_STATE) { | |
6f231dda DW |
806 | status = SCI_FAILURE; |
807 | ||
35173d57 | 808 | dev_warn(scic_to_dev(scic), |
6f231dda DW |
809 | "%s: Controller stop operation failed to stop " |
810 | "phy %d because of status %d.\n", | |
811 | __func__, | |
4b33981a | 812 | ihost->phys[index].sci.phy_index, phy_status); |
6f231dda DW |
813 | } |
814 | } | |
815 | ||
816 | return status; | |
817 | } | |
818 | ||
35173d57 | 819 | static enum sci_status scic_sds_controller_stop_devices(struct scic_sds_controller *scic) |
6f231dda DW |
820 | { |
821 | u32 index; | |
822 | enum sci_status status; | |
823 | enum sci_status device_status; | |
824 | ||
825 | status = SCI_SUCCESS; | |
826 | ||
35173d57 DW |
827 | for (index = 0; index < scic->remote_node_entries; index++) { |
828 | if (scic->device_table[index] != NULL) { | |
6f231dda | 829 | /* / @todo What timeout value do we want to provide to this request? */ |
35173d57 | 830 | device_status = scic_remote_device_stop(scic->device_table[index], 0); |
6f231dda DW |
831 | |
832 | if ((device_status != SCI_SUCCESS) && | |
833 | (device_status != SCI_FAILURE_INVALID_STATE)) { | |
35173d57 | 834 | dev_warn(scic_to_dev(scic), |
6f231dda DW |
835 | "%s: Controller stop operation failed " |
836 | "to stop device 0x%p because of " | |
837 | "status %d.\n", | |
838 | __func__, | |
35173d57 | 839 | scic->device_table[index], device_status); |
6f231dda DW |
840 | } |
841 | } | |
842 | } | |
843 | ||
844 | return status; | |
845 | } | |
846 | ||
35173d57 | 847 | static void scic_sds_controller_power_control_timer_start(struct scic_sds_controller *scic) |
6f231dda | 848 | { |
09d7da13 DJ |
849 | isci_timer_start(scic->power_control.timer, |
850 | SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); | |
6f231dda | 851 | |
09d7da13 | 852 | scic->power_control.timer_started = true; |
6f231dda DW |
853 | } |
854 | ||
35173d57 | 855 | static void scic_sds_controller_power_control_timer_stop(struct scic_sds_controller *scic) |
07373a5c HD |
856 | { |
857 | if (scic->power_control.timer_started) { | |
09d7da13 | 858 | isci_timer_stop(scic->power_control.timer); |
07373a5c HD |
859 | scic->power_control.timer_started = false; |
860 | } | |
861 | } | |
862 | ||
35173d57 | 863 | static void scic_sds_controller_power_control_timer_restart(struct scic_sds_controller *scic) |
07373a5c HD |
864 | { |
865 | scic_sds_controller_power_control_timer_stop(scic); | |
866 | scic_sds_controller_power_control_timer_start(scic); | |
867 | } | |
868 | ||
6f231dda DW |
869 | static void scic_sds_controller_power_control_timer_handler( |
870 | void *controller) | |
871 | { | |
e2023b87 | 872 | struct scic_sds_controller *scic; |
6f231dda | 873 | |
e2023b87 | 874 | scic = (struct scic_sds_controller *)controller; |
6f231dda | 875 | |
e2023b87 | 876 | scic->power_control.phys_granted_power = 0; |
07373a5c | 877 | |
e2023b87 DJ |
878 | if (scic->power_control.phys_waiting == 0) { |
879 | scic->power_control.timer_started = false; | |
6f231dda | 880 | } else { |
e2023b87 | 881 | struct scic_sds_phy *sci_phy = NULL; |
6f231dda DW |
882 | u8 i; |
883 | ||
884 | for (i = 0; | |
885 | (i < SCI_MAX_PHYS) | |
e2023b87 | 886 | && (scic->power_control.phys_waiting != 0); |
6f231dda | 887 | i++) { |
e2023b87 DJ |
888 | if (scic->power_control.requesters[i] != NULL) { |
889 | if (scic->power_control.phys_granted_power < | |
890 | scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up) { | |
891 | sci_phy = scic->power_control.requesters[i]; | |
892 | scic->power_control.requesters[i] = NULL; | |
893 | scic->power_control.phys_waiting--; | |
894 | scic->power_control.phys_granted_power++; | |
895 | scic_sds_phy_consume_power_handler(sci_phy); | |
07373a5c HD |
896 | } else { |
897 | break; | |
898 | } | |
6f231dda DW |
899 | } |
900 | } | |
901 | ||
902 | /* | |
903 | * It doesn't matter if the power list is empty, we need to start the | |
07373a5c HD |
904 | * timer in case another phy becomes ready. |
905 | */ | |
e2023b87 | 906 | scic_sds_controller_power_control_timer_start(scic); |
6f231dda DW |
907 | } |
908 | } | |
909 | ||
910 | /** | |
911 | * This method inserts the phy in the stagger spinup control queue. | |
e2023b87 | 912 | * @scic: |
6f231dda DW |
913 | * |
914 | * | |
915 | */ | |
916 | void scic_sds_controller_power_control_queue_insert( | |
e2023b87 DJ |
917 | struct scic_sds_controller *scic, |
918 | struct scic_sds_phy *sci_phy) | |
6f231dda | 919 | { |
e2023b87 | 920 | BUG_ON(sci_phy == NULL); |
6f231dda | 921 | |
e2023b87 DJ |
922 | if (scic->power_control.phys_granted_power < |
923 | scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up) { | |
924 | scic->power_control.phys_granted_power++; | |
925 | scic_sds_phy_consume_power_handler(sci_phy); | |
07373a5c HD |
926 | |
927 | /* | |
928 | * stop and start the power_control timer. When the timer fires, the | |
929 | * no_of_phys_granted_power will be set to 0 | |
930 | */ | |
e2023b87 | 931 | scic_sds_controller_power_control_timer_restart(scic); |
07373a5c HD |
932 | } else { |
933 | /* Add the phy in the waiting list */ | |
e2023b87 DJ |
934 | scic->power_control.requesters[sci_phy->phy_index] = sci_phy; |
935 | scic->power_control.phys_waiting++; | |
6f231dda DW |
936 | } |
937 | } | |
938 | ||
939 | /** | |
940 | * This method removes the phy from the stagger spinup control queue. | |
e2023b87 | 941 | * @scic: |
6f231dda DW |
942 | * |
943 | * | |
944 | */ | |
945 | void scic_sds_controller_power_control_queue_remove( | |
e2023b87 DJ |
946 | struct scic_sds_controller *scic, |
947 | struct scic_sds_phy *sci_phy) | |
6f231dda | 948 | { |
e2023b87 | 949 | BUG_ON(sci_phy == NULL); |
6f231dda | 950 | |
e2023b87 DJ |
951 | if (scic->power_control.requesters[sci_phy->phy_index] != NULL) { |
952 | scic->power_control.phys_waiting--; | |
6f231dda DW |
953 | } |
954 | ||
e2023b87 | 955 | scic->power_control.requesters[sci_phy->phy_index] = NULL; |
6f231dda DW |
956 | } |
957 | ||
958 | /* | |
959 | * ****************************************************************************- | |
960 | * * SCIC SDS Controller Completion Routines | |
961 | * ****************************************************************************- */ | |
962 | ||
963 | /** | |
964 | * This method returns a true value if the completion queue has entries that | |
965 | * can be processed | |
e2023b87 | 966 | * @scic: |
6f231dda DW |
967 | * |
968 | * bool true if the completion queue has entries to process false if the | |
969 | * completion queue has no entries to process | |
970 | */ | |
971 | static bool scic_sds_controller_completion_queue_has_entries( | |
e2023b87 | 972 | struct scic_sds_controller *scic) |
6f231dda | 973 | { |
e2023b87 | 974 | u32 get_value = scic->completion_queue_get; |
6f231dda DW |
975 | u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK; |
976 | ||
e2023b87 DJ |
977 | if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) == |
978 | COMPLETION_QUEUE_CYCLE_BIT(scic->completion_queue[get_index])) | |
6f231dda | 979 | return true; |
6f231dda DW |
980 | |
981 | return false; | |
982 | } | |
983 | ||
6f231dda DW |
984 | /** |
985 | * This method processes a task completion notification. This is called from | |
986 | * within the controller completion handler. | |
e2023b87 | 987 | * @scic: |
6f231dda DW |
988 | * @completion_entry: |
989 | * | |
990 | */ | |
991 | static void scic_sds_controller_task_completion( | |
e2023b87 | 992 | struct scic_sds_controller *scic, |
6f231dda DW |
993 | u32 completion_entry) |
994 | { | |
995 | u32 index; | |
996 | struct scic_sds_request *io_request; | |
997 | ||
998 | index = SCU_GET_COMPLETION_INDEX(completion_entry); | |
e2023b87 | 999 | io_request = scic->io_request_table[index]; |
6f231dda DW |
1000 | |
1001 | /* Make sure that we really want to process this IO request */ | |
1002 | if ( | |
a7e536c7 | 1003 | (io_request != NULL) |
6f231dda DW |
1004 | && (io_request->io_tag != SCI_CONTROLLER_INVALID_IO_TAG) |
1005 | && ( | |
1006 | scic_sds_io_tag_get_sequence(io_request->io_tag) | |
e2023b87 | 1007 | == scic->io_request_sequence[index] |
6f231dda DW |
1008 | ) |
1009 | ) { | |
1010 | /* Yep this is a valid io request pass it along to the io request handler */ | |
1011 | scic_sds_io_request_tc_completion(io_request, completion_entry); | |
1012 | } | |
1013 | } | |
1014 | ||
1015 | /** | |
1016 | * This method processes an SDMA completion event. This is called from within | |
1017 | * the controller completion handler. | |
e2023b87 | 1018 | * @scic: |
6f231dda DW |
1019 | * @completion_entry: |
1020 | * | |
1021 | */ | |
1022 | static void scic_sds_controller_sdma_completion( | |
e2023b87 | 1023 | struct scic_sds_controller *scic, |
6f231dda DW |
1024 | u32 completion_entry) |
1025 | { | |
1026 | u32 index; | |
1027 | struct scic_sds_request *io_request; | |
1028 | struct scic_sds_remote_device *device; | |
1029 | ||
1030 | index = SCU_GET_COMPLETION_INDEX(completion_entry); | |
1031 | ||
1032 | switch (scu_get_command_request_type(completion_entry)) { | |
1033 | case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC: | |
1034 | case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC: | |
e2023b87 DJ |
1035 | io_request = scic->io_request_table[index]; |
1036 | dev_warn(scic_to_dev(scic), | |
6f231dda DW |
1037 | "%s: SCIC SDS Completion type SDMA %x for io request " |
1038 | "%p\n", | |
1039 | __func__, | |
1040 | completion_entry, | |
1041 | io_request); | |
1042 | /* @todo For a post TC operation we need to fail the IO | |
1043 | * request | |
1044 | */ | |
1045 | break; | |
1046 | ||
1047 | case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC: | |
1048 | case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC: | |
1049 | case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC: | |
e2023b87 DJ |
1050 | device = scic->device_table[index]; |
1051 | dev_warn(scic_to_dev(scic), | |
6f231dda DW |
1052 | "%s: SCIC SDS Completion type SDMA %x for remote " |
1053 | "device %p\n", | |
1054 | __func__, | |
1055 | completion_entry, | |
1056 | device); | |
1057 | /* @todo For a port RNC operation we need to fail the | |
1058 | * device | |
1059 | */ | |
1060 | break; | |
1061 | ||
1062 | default: | |
e2023b87 | 1063 | dev_warn(scic_to_dev(scic), |
6f231dda DW |
1064 | "%s: SCIC SDS Completion unknown SDMA completion " |
1065 | "type %x\n", | |
1066 | __func__, | |
1067 | completion_entry); | |
1068 | break; | |
1069 | ||
1070 | } | |
1071 | } | |
1072 | ||
4b33981a DW |
1073 | static void scic_sds_controller_unsolicited_frame(struct scic_sds_controller *scic, |
1074 | u32 completion_entry) | |
6f231dda DW |
1075 | { |
1076 | u32 index; | |
1077 | u32 frame_index; | |
1078 | ||
4b33981a | 1079 | struct isci_host *ihost = scic_to_ihost(scic); |
6f231dda DW |
1080 | struct scu_unsolicited_frame_header *frame_header; |
1081 | struct scic_sds_phy *phy; | |
1082 | struct scic_sds_remote_device *device; | |
1083 | ||
1084 | enum sci_status result = SCI_FAILURE; | |
1085 | ||
1086 | frame_index = SCU_GET_FRAME_INDEX(completion_entry); | |
1087 | ||
4b33981a DW |
1088 | frame_header = scic->uf_control.buffers.array[frame_index].header; |
1089 | scic->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE; | |
6f231dda DW |
1090 | |
1091 | if (SCU_GET_FRAME_ERROR(completion_entry)) { | |
1092 | /* | |
1093 | * / @todo If the IAF frame or SIGNATURE FIS frame has an error will | |
1094 | * / this cause a problem? We expect the phy initialization will | |
1095 | * / fail if there is an error in the frame. */ | |
e2023b87 | 1096 | scic_sds_controller_release_frame(scic, frame_index); |
6f231dda DW |
1097 | return; |
1098 | } | |
1099 | ||
1100 | if (frame_header->is_address_frame) { | |
1101 | index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry); | |
4b33981a DW |
1102 | phy = &ihost->phys[index].sci; |
1103 | result = scic_sds_phy_frame_handler(phy, frame_index); | |
6f231dda DW |
1104 | } else { |
1105 | ||
1106 | index = SCU_GET_COMPLETION_INDEX(completion_entry); | |
1107 | ||
1108 | if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) { | |
1109 | /* | |
1110 | * This is a signature fis or a frame from a direct attached SATA | |
1111 | * device that has not yet been created. In either case forwared | |
1112 | * the frame to the PE and let it take care of the frame data. */ | |
1113 | index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry); | |
4b33981a | 1114 | phy = &ihost->phys[index].sci; |
6f231dda DW |
1115 | result = scic_sds_phy_frame_handler(phy, frame_index); |
1116 | } else { | |
e2023b87 DJ |
1117 | if (index < scic->remote_node_entries) |
1118 | device = scic->device_table[index]; | |
6f231dda DW |
1119 | else |
1120 | device = NULL; | |
1121 | ||
1122 | if (device != NULL) | |
1123 | result = scic_sds_remote_device_frame_handler(device, frame_index); | |
1124 | else | |
e2023b87 | 1125 | scic_sds_controller_release_frame(scic, frame_index); |
6f231dda DW |
1126 | } |
1127 | } | |
1128 | ||
1129 | if (result != SCI_SUCCESS) { | |
1130 | /* | |
1131 | * / @todo Is there any reason to report some additional error message | |
1132 | * / when we get this failure notifiction? */ | |
1133 | } | |
1134 | } | |
1135 | ||
4b33981a DW |
1136 | static void scic_sds_controller_event_completion(struct scic_sds_controller *scic, |
1137 | u32 completion_entry) | |
6f231dda | 1138 | { |
4b33981a | 1139 | struct isci_host *ihost = scic_to_ihost(scic); |
6f231dda DW |
1140 | struct scic_sds_request *io_request; |
1141 | struct scic_sds_remote_device *device; | |
1142 | struct scic_sds_phy *phy; | |
4b33981a | 1143 | u32 index; |
6f231dda DW |
1144 | |
1145 | index = SCU_GET_COMPLETION_INDEX(completion_entry); | |
1146 | ||
1147 | switch (scu_get_event_type(completion_entry)) { | |
1148 | case SCU_EVENT_TYPE_SMU_COMMAND_ERROR: | |
1149 | /* / @todo The driver did something wrong and we need to fix the condtion. */ | |
e2023b87 | 1150 | dev_err(scic_to_dev(scic), |
6f231dda DW |
1151 | "%s: SCIC Controller 0x%p received SMU command error " |
1152 | "0x%x\n", | |
1153 | __func__, | |
e2023b87 | 1154 | scic, |
6f231dda DW |
1155 | completion_entry); |
1156 | break; | |
1157 | ||
1158 | case SCU_EVENT_TYPE_SMU_PCQ_ERROR: | |
1159 | case SCU_EVENT_TYPE_SMU_ERROR: | |
1160 | case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR: | |
1161 | /* | |
1162 | * / @todo This is a hardware failure and its likely that we want to | |
1163 | * / reset the controller. */ | |
e2023b87 | 1164 | dev_err(scic_to_dev(scic), |
6f231dda DW |
1165 | "%s: SCIC Controller 0x%p received fatal controller " |
1166 | "event 0x%x\n", | |
1167 | __func__, | |
e2023b87 | 1168 | scic, |
6f231dda DW |
1169 | completion_entry); |
1170 | break; | |
1171 | ||
1172 | case SCU_EVENT_TYPE_TRANSPORT_ERROR: | |
e2023b87 | 1173 | io_request = scic->io_request_table[index]; |
6f231dda DW |
1174 | scic_sds_io_request_event_handler(io_request, completion_entry); |
1175 | break; | |
1176 | ||
1177 | case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT: | |
1178 | switch (scu_get_event_specifier(completion_entry)) { | |
1179 | case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE: | |
1180 | case SCU_EVENT_SPECIFIC_TASK_TIMEOUT: | |
e2023b87 | 1181 | io_request = scic->io_request_table[index]; |
a7e536c7 | 1182 | if (io_request != NULL) |
6f231dda DW |
1183 | scic_sds_io_request_event_handler(io_request, completion_entry); |
1184 | else | |
e2023b87 | 1185 | dev_warn(scic_to_dev(scic), |
6f231dda DW |
1186 | "%s: SCIC Controller 0x%p received " |
1187 | "event 0x%x for io request object " | |
1188 | "that doesnt exist.\n", | |
1189 | __func__, | |
e2023b87 | 1190 | scic, |
6f231dda DW |
1191 | completion_entry); |
1192 | ||
1193 | break; | |
1194 | ||
1195 | case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT: | |
e2023b87 | 1196 | device = scic->device_table[index]; |
a7e536c7 | 1197 | if (device != NULL) |
6f231dda DW |
1198 | scic_sds_remote_device_event_handler(device, completion_entry); |
1199 | else | |
e2023b87 | 1200 | dev_warn(scic_to_dev(scic), |
6f231dda DW |
1201 | "%s: SCIC Controller 0x%p received " |
1202 | "event 0x%x for remote device object " | |
1203 | "that doesnt exist.\n", | |
1204 | __func__, | |
e2023b87 | 1205 | scic, |
6f231dda DW |
1206 | completion_entry); |
1207 | ||
1208 | break; | |
1209 | } | |
1210 | break; | |
1211 | ||
1212 | case SCU_EVENT_TYPE_BROADCAST_CHANGE: | |
1213 | /* | |
1214 | * direct the broadcast change event to the phy first and then let | |
1215 | * the phy redirect the broadcast change to the port object */ | |
1216 | case SCU_EVENT_TYPE_ERR_CNT_EVENT: | |
1217 | /* | |
1218 | * direct error counter event to the phy object since that is where | |
1219 | * we get the event notification. This is a type 4 event. */ | |
1220 | case SCU_EVENT_TYPE_OSSP_EVENT: | |
1221 | index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry); | |
4b33981a | 1222 | phy = &ihost->phys[index].sci; |
6f231dda DW |
1223 | scic_sds_phy_event_handler(phy, completion_entry); |
1224 | break; | |
1225 | ||
1226 | case SCU_EVENT_TYPE_RNC_SUSPEND_TX: | |
1227 | case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX: | |
1228 | case SCU_EVENT_TYPE_RNC_OPS_MISC: | |
e2023b87 DJ |
1229 | if (index < scic->remote_node_entries) { |
1230 | device = scic->device_table[index]; | |
6f231dda DW |
1231 | |
1232 | if (device != NULL) | |
1233 | scic_sds_remote_device_event_handler(device, completion_entry); | |
1234 | } else | |
e2023b87 | 1235 | dev_err(scic_to_dev(scic), |
6f231dda DW |
1236 | "%s: SCIC Controller 0x%p received event 0x%x " |
1237 | "for remote device object 0x%0x that doesnt " | |
1238 | "exist.\n", | |
1239 | __func__, | |
e2023b87 | 1240 | scic, |
6f231dda DW |
1241 | completion_entry, |
1242 | index); | |
1243 | ||
1244 | break; | |
1245 | ||
1246 | default: | |
e2023b87 | 1247 | dev_warn(scic_to_dev(scic), |
6f231dda DW |
1248 | "%s: SCIC Controller received unknown event code %x\n", |
1249 | __func__, | |
1250 | completion_entry); | |
1251 | break; | |
1252 | } | |
1253 | } | |
1254 | ||
1255 | /** | |
1256 | * This method is a private routine for processing the completion queue entries. | |
e2023b87 | 1257 | * @scic: |
6f231dda DW |
1258 | * |
1259 | */ | |
1260 | static void scic_sds_controller_process_completions( | |
e2023b87 | 1261 | struct scic_sds_controller *scic) |
6f231dda DW |
1262 | { |
1263 | u32 completion_count = 0; | |
1264 | u32 completion_entry; | |
1265 | u32 get_index; | |
1266 | u32 get_cycle; | |
1267 | u32 event_index; | |
1268 | u32 event_cycle; | |
1269 | ||
e2023b87 | 1270 | dev_dbg(scic_to_dev(scic), |
6f231dda DW |
1271 | "%s: completion queue begining get:0x%08x\n", |
1272 | __func__, | |
e2023b87 | 1273 | scic->completion_queue_get); |
6f231dda DW |
1274 | |
1275 | /* Get the component parts of the completion queue */ | |
e2023b87 DJ |
1276 | get_index = NORMALIZE_GET_POINTER(scic->completion_queue_get); |
1277 | get_cycle = SMU_CQGR_CYCLE_BIT & scic->completion_queue_get; | |
6f231dda | 1278 | |
e2023b87 DJ |
1279 | event_index = NORMALIZE_EVENT_POINTER(scic->completion_queue_get); |
1280 | event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & scic->completion_queue_get; | |
6f231dda DW |
1281 | |
1282 | while ( | |
1283 | NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle) | |
e2023b87 | 1284 | == COMPLETION_QUEUE_CYCLE_BIT(scic->completion_queue[get_index]) |
6f231dda DW |
1285 | ) { |
1286 | completion_count++; | |
1287 | ||
e2023b87 DJ |
1288 | completion_entry = scic->completion_queue[get_index]; |
1289 | INCREMENT_COMPLETION_QUEUE_GET(scic, get_index, get_cycle); | |
6f231dda | 1290 | |
e2023b87 | 1291 | dev_dbg(scic_to_dev(scic), |
6f231dda DW |
1292 | "%s: completion queue entry:0x%08x\n", |
1293 | __func__, | |
1294 | completion_entry); | |
1295 | ||
1296 | switch (SCU_GET_COMPLETION_TYPE(completion_entry)) { | |
1297 | case SCU_COMPLETION_TYPE_TASK: | |
e2023b87 | 1298 | scic_sds_controller_task_completion(scic, completion_entry); |
6f231dda DW |
1299 | break; |
1300 | ||
1301 | case SCU_COMPLETION_TYPE_SDMA: | |
e2023b87 | 1302 | scic_sds_controller_sdma_completion(scic, completion_entry); |
6f231dda DW |
1303 | break; |
1304 | ||
1305 | case SCU_COMPLETION_TYPE_UFI: | |
e2023b87 | 1306 | scic_sds_controller_unsolicited_frame(scic, completion_entry); |
6f231dda DW |
1307 | break; |
1308 | ||
1309 | case SCU_COMPLETION_TYPE_EVENT: | |
e2023b87 DJ |
1310 | INCREMENT_EVENT_QUEUE_GET(scic, event_index, event_cycle); |
1311 | scic_sds_controller_event_completion(scic, completion_entry); | |
6f231dda DW |
1312 | break; |
1313 | ||
1314 | case SCU_COMPLETION_TYPE_NOTIFY: | |
1315 | /* | |
1316 | * Presently we do the same thing with a notify event that we do with the | |
1317 | * other event codes. */ | |
e2023b87 DJ |
1318 | INCREMENT_EVENT_QUEUE_GET(scic, event_index, event_cycle); |
1319 | scic_sds_controller_event_completion(scic, completion_entry); | |
6f231dda DW |
1320 | break; |
1321 | ||
1322 | default: | |
e2023b87 | 1323 | dev_warn(scic_to_dev(scic), |
6f231dda DW |
1324 | "%s: SCIC Controller received unknown " |
1325 | "completion type %x\n", | |
1326 | __func__, | |
1327 | completion_entry); | |
1328 | break; | |
1329 | } | |
1330 | } | |
1331 | ||
1332 | /* Update the get register if we completed one or more entries */ | |
1333 | if (completion_count > 0) { | |
e2023b87 DJ |
1334 | scic->completion_queue_get = |
1335 | SMU_CQGR_GEN_BIT(ENABLE) | | |
1336 | SMU_CQGR_GEN_BIT(EVENT_ENABLE) | | |
1337 | event_cycle | | |
1338 | SMU_CQGR_GEN_VAL(EVENT_POINTER, event_index) | | |
1339 | get_cycle | | |
1340 | SMU_CQGR_GEN_VAL(POINTER, get_index); | |
6f231dda | 1341 | |
e2023b87 DJ |
1342 | writel(scic->completion_queue_get, |
1343 | &scic->smu_registers->completion_queue_get); | |
bc99aa47 | 1344 | |
6f231dda DW |
1345 | } |
1346 | ||
e2023b87 | 1347 | dev_dbg(scic_to_dev(scic), |
6f231dda DW |
1348 | "%s: completion queue ending get:0x%08x\n", |
1349 | __func__, | |
e2023b87 | 1350 | scic->completion_queue_get); |
6f231dda DW |
1351 | |
1352 | } | |
1353 | ||
c7ef4031 | 1354 | bool scic_sds_controller_isr(struct scic_sds_controller *scic) |
6f231dda DW |
1355 | { |
1356 | if (scic_sds_controller_completion_queue_has_entries(scic)) { | |
1357 | return true; | |
1358 | } else { | |
1359 | /* | |
1360 | * we have a spurious interrupt it could be that we have already | |
1361 | * emptied the completion queue from a previous interrupt */ | |
bc99aa47 | 1362 | writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status); |
6f231dda DW |
1363 | |
1364 | /* | |
1365 | * There is a race in the hardware that could cause us not to be notified | |
1366 | * of an interrupt completion if we do not take this step. We will mask | |
1367 | * then unmask the interrupts so if there is another interrupt pending | |
1368 | * the clearing of the interrupt source we get the next interrupt message. */ | |
bc99aa47 CH |
1369 | writel(0xFF000000, &scic->smu_registers->interrupt_mask); |
1370 | writel(0, &scic->smu_registers->interrupt_mask); | |
6f231dda DW |
1371 | } |
1372 | ||
1373 | return false; | |
1374 | } | |
1375 | ||
c7ef4031 | 1376 | void scic_sds_controller_completion_handler(struct scic_sds_controller *scic) |
6f231dda DW |
1377 | { |
1378 | /* Empty out the completion queue */ | |
1379 | if (scic_sds_controller_completion_queue_has_entries(scic)) | |
1380 | scic_sds_controller_process_completions(scic); | |
1381 | ||
1382 | /* Clear the interrupt and enable all interrupts again */ | |
bc99aa47 | 1383 | writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status); |
6f231dda | 1384 | /* Could we write the value of SMU_ISR_COMPLETION? */ |
bc99aa47 CH |
1385 | writel(0xFF000000, &scic->smu_registers->interrupt_mask); |
1386 | writel(0, &scic->smu_registers->interrupt_mask); | |
6f231dda DW |
1387 | } |
1388 | ||
92f4f0f5 | 1389 | bool scic_sds_controller_error_isr(struct scic_sds_controller *scic) |
6f231dda DW |
1390 | { |
1391 | u32 interrupt_status; | |
1392 | ||
bc99aa47 CH |
1393 | interrupt_status = |
1394 | readl(&scic->smu_registers->interrupt_status); | |
6f231dda DW |
1395 | interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND); |
1396 | ||
1397 | if (interrupt_status != 0) { | |
1398 | /* | |
1399 | * There is an error interrupt pending so let it through and handle | |
1400 | * in the callback */ | |
1401 | return true; | |
1402 | } | |
1403 | ||
1404 | /* | |
1405 | * There is a race in the hardware that could cause us not to be notified | |
1406 | * of an interrupt completion if we do not take this step. We will mask | |
1407 | * then unmask the error interrupts so if there was another interrupt | |
1408 | * pending we will be notified. | |
1409 | * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */ | |
bc99aa47 CH |
1410 | writel(0xff, &scic->smu_registers->interrupt_mask); |
1411 | writel(0, &scic->smu_registers->interrupt_mask); | |
6f231dda DW |
1412 | |
1413 | return false; | |
1414 | } | |
1415 | ||
92f4f0f5 | 1416 | void scic_sds_controller_error_handler(struct scic_sds_controller *scic) |
6f231dda DW |
1417 | { |
1418 | u32 interrupt_status; | |
1419 | ||
bc99aa47 CH |
1420 | interrupt_status = |
1421 | readl(&scic->smu_registers->interrupt_status); | |
6f231dda DW |
1422 | |
1423 | if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) && | |
1424 | scic_sds_controller_completion_queue_has_entries(scic)) { | |
1425 | ||
1426 | scic_sds_controller_process_completions(scic); | |
bc99aa47 | 1427 | writel(SMU_ISR_QUEUE_SUSPEND, &scic->smu_registers->interrupt_status); |
6f231dda | 1428 | } else { |
92f4f0f5 | 1429 | dev_err(scic_to_dev(scic), "%s: status: %#x\n", __func__, |
6f231dda DW |
1430 | interrupt_status); |
1431 | ||
ca841f0e | 1432 | sci_base_state_machine_change_state(&scic->state_machine, |
068b2c03 | 1433 | SCI_BASE_CONTROLLER_STATE_FAILED); |
6f231dda DW |
1434 | |
1435 | return; | |
1436 | } | |
1437 | ||
068b2c03 DW |
1438 | /* If we dont process any completions I am not sure that we want to do this. |
1439 | * We are in the middle of a hardware fault and should probably be reset. | |
1440 | */ | |
bc99aa47 | 1441 | writel(0, &scic->smu_registers->interrupt_mask); |
6f231dda DW |
1442 | } |
1443 | ||
1444 | ||
6f231dda DW |
1445 | |
1446 | ||
c629582d CH |
1447 | void scic_sds_controller_link_up(struct scic_sds_controller *scic, |
1448 | struct scic_sds_port *port, struct scic_sds_phy *phy) | |
1449 | { | |
1450 | switch (scic->state_machine.current_state_id) { | |
1451 | case SCI_BASE_CONTROLLER_STATE_STARTING: | |
1452 | scic_sds_controller_phy_timer_stop(scic); | |
1453 | scic->port_agent.link_up_handler(scic, &scic->port_agent, | |
1454 | port, phy); | |
1455 | scic_sds_controller_start_next_phy(scic); | |
1456 | break; | |
1457 | case SCI_BASE_CONTROLLER_STATE_READY: | |
1458 | scic->port_agent.link_up_handler(scic, &scic->port_agent, | |
1459 | port, phy); | |
1460 | break; | |
1461 | default: | |
d7628d05 | 1462 | dev_dbg(scic_to_dev(scic), |
6f231dda | 1463 | "%s: SCIC Controller linkup event from phy %d in " |
c629582d CH |
1464 | "unexpected state %d\n", __func__, phy->phy_index, |
1465 | scic->state_machine.current_state_id); | |
1466 | } | |
6f231dda DW |
1467 | } |
1468 | ||
c629582d CH |
1469 | void scic_sds_controller_link_down(struct scic_sds_controller *scic, |
1470 | struct scic_sds_port *port, struct scic_sds_phy *phy) | |
6f231dda | 1471 | { |
c629582d CH |
1472 | switch (scic->state_machine.current_state_id) { |
1473 | case SCI_BASE_CONTROLLER_STATE_STARTING: | |
1474 | case SCI_BASE_CONTROLLER_STATE_READY: | |
1475 | scic->port_agent.link_down_handler(scic, &scic->port_agent, | |
1476 | port, phy); | |
1477 | break; | |
1478 | default: | |
d7628d05 | 1479 | dev_dbg(scic_to_dev(scic), |
6f231dda DW |
1480 | "%s: SCIC Controller linkdown event from phy %d in " |
1481 | "unexpected state %d\n", | |
1482 | __func__, | |
c629582d CH |
1483 | phy->phy_index, |
1484 | scic->state_machine.current_state_id); | |
1485 | } | |
6f231dda DW |
1486 | } |
1487 | ||
c658b109 PM |
1488 | /** |
1489 | * This is a helper method to determine if any remote devices on this | |
1490 | * controller are still in the stopping state. | |
1491 | * | |
1492 | */ | |
35173d57 | 1493 | static bool scic_sds_controller_has_remote_devices_stopping( |
0ea99d52 | 1494 | struct scic_sds_controller *controller) |
c658b109 PM |
1495 | { |
1496 | u32 index; | |
1497 | ||
0ea99d52 MT |
1498 | for (index = 0; index < controller->remote_node_entries; index++) { |
1499 | if ((controller->device_table[index] != NULL) && | |
1500 | (controller->device_table[index]->state_machine.current_state_id | |
c658b109 PM |
1501 | == SCI_BASE_REMOTE_DEVICE_STATE_STOPPING)) |
1502 | return true; | |
1503 | } | |
1504 | ||
1505 | return false; | |
1506 | } | |
1507 | ||
1508 | /** | |
1509 | * This method is called by the remote device to inform the controller | |
1510 | * object that the remote device has stopped. | |
c658b109 | 1511 | */ |
d7628d05 DJ |
1512 | void scic_sds_controller_remote_device_stopped(struct scic_sds_controller *scic, |
1513 | struct scic_sds_remote_device *sci_dev) | |
c658b109 | 1514 | { |
c629582d CH |
1515 | if (scic->state_machine.current_state_id != |
1516 | SCI_BASE_CONTROLLER_STATE_STOPPING) { | |
d7628d05 | 1517 | dev_dbg(scic_to_dev(scic), |
c629582d CH |
1518 | "SCIC Controller 0x%p remote device stopped event " |
1519 | "from device 0x%p in unexpected state %d\n", | |
1520 | scic, sci_dev, | |
1521 | scic->state_machine.current_state_id); | |
1522 | return; | |
c658b109 | 1523 | } |
c658b109 | 1524 | |
c629582d CH |
1525 | if (!scic_sds_controller_has_remote_devices_stopping(scic)) { |
1526 | sci_base_state_machine_change_state(&scic->state_machine, | |
1527 | SCI_BASE_CONTROLLER_STATE_STOPPED); | |
1528 | } | |
1529 | } | |
c658b109 | 1530 | |
6f231dda DW |
1531 | /** |
1532 | * This method will write to the SCU PCP register the request value. The method | |
1533 | * is used to suspend/resume ports, devices, and phys. | |
e2023b87 | 1534 | * @scic: |
6f231dda DW |
1535 | * |
1536 | * | |
1537 | */ | |
1538 | void scic_sds_controller_post_request( | |
e2023b87 | 1539 | struct scic_sds_controller *scic, |
6f231dda DW |
1540 | u32 request) |
1541 | { | |
e2023b87 | 1542 | dev_dbg(scic_to_dev(scic), |
6f231dda DW |
1543 | "%s: SCIC Controller 0x%p post request 0x%08x\n", |
1544 | __func__, | |
e2023b87 | 1545 | scic, |
6f231dda DW |
1546 | request); |
1547 | ||
e2023b87 | 1548 | writel(request, &scic->smu_registers->post_context_port); |
6f231dda DW |
1549 | } |
1550 | ||
1551 | /** | |
1552 | * This method will copy the soft copy of the task context into the physical | |
1553 | * memory accessible by the controller. | |
e2023b87 | 1554 | * @scic: This parameter specifies the controller for which to copy |
6f231dda | 1555 | * the task context. |
e2023b87 | 1556 | * @sci_req: This parameter specifies the request for which the task |
6f231dda DW |
1557 | * context is being copied. |
1558 | * | |
1559 | * After this call is made the SCIC_SDS_IO_REQUEST object will always point to | |
1560 | * the physical memory version of the task context. Thus, all subsequent | |
1561 | * updates to the task context are performed in the TC table (i.e. DMAable | |
1562 | * memory). none | |
1563 | */ | |
1564 | void scic_sds_controller_copy_task_context( | |
e2023b87 DJ |
1565 | struct scic_sds_controller *scic, |
1566 | struct scic_sds_request *sci_req) | |
6f231dda DW |
1567 | { |
1568 | struct scu_task_context *task_context_buffer; | |
1569 | ||
1570 | task_context_buffer = scic_sds_controller_get_task_context_buffer( | |
e2023b87 | 1571 | scic, sci_req->io_tag); |
6f231dda | 1572 | |
e2023b87 DJ |
1573 | memcpy(task_context_buffer, |
1574 | sci_req->task_context_buffer, | |
67ea838d | 1575 | offsetof(struct scu_task_context, sgl_snapshot_ac)); |
6f231dda DW |
1576 | |
1577 | /* | |
1578 | * Now that the soft copy of the TC has been copied into the TC | |
1579 | * table accessible by the silicon. Thus, any further changes to | |
1580 | * the TC (e.g. TC termination) occur in the appropriate location. */ | |
e2023b87 | 1581 | sci_req->task_context_buffer = task_context_buffer; |
6f231dda DW |
1582 | } |
1583 | ||
1584 | /** | |
1585 | * This method returns the task context buffer for the given io tag. | |
e2023b87 | 1586 | * @scic: |
6f231dda DW |
1587 | * @io_tag: |
1588 | * | |
1589 | * struct scu_task_context* | |
1590 | */ | |
1591 | struct scu_task_context *scic_sds_controller_get_task_context_buffer( | |
e2023b87 | 1592 | struct scic_sds_controller *scic, |
6f231dda DW |
1593 | u16 io_tag |
1594 | ) { | |
1595 | u16 task_index = scic_sds_io_tag_get_index(io_tag); | |
1596 | ||
e2023b87 DJ |
1597 | if (task_index < scic->task_context_entries) { |
1598 | return &scic->task_context_table[task_index]; | |
6f231dda DW |
1599 | } |
1600 | ||
1601 | return NULL; | |
1602 | } | |
1603 | ||
2d9c2240 DJ |
1604 | struct scic_sds_request *scic_request_by_tag(struct scic_sds_controller *scic, |
1605 | u16 io_tag) | |
1606 | { | |
6f231dda DW |
1607 | u16 task_index; |
1608 | u16 task_sequence; | |
1609 | ||
1610 | task_index = scic_sds_io_tag_get_index(io_tag); | |
1611 | ||
e2023b87 DJ |
1612 | if (task_index < scic->task_context_entries) { |
1613 | if (scic->io_request_table[task_index] != NULL) { | |
6f231dda DW |
1614 | task_sequence = scic_sds_io_tag_get_sequence(io_tag); |
1615 | ||
e2023b87 DJ |
1616 | if (task_sequence == scic->io_request_sequence[task_index]) { |
1617 | return scic->io_request_table[task_index]; | |
6f231dda DW |
1618 | } |
1619 | } | |
1620 | } | |
1621 | ||
a7e536c7 | 1622 | return NULL; |
6f231dda DW |
1623 | } |
1624 | ||
1625 | /** | |
1626 | * This method allocates remote node index and the reserves the remote node | |
1627 | * context space for use. This method can fail if there are no more remote | |
1628 | * node index available. | |
e2023b87 | 1629 | * @scic: This is the controller object which contains the set of |
6f231dda | 1630 | * free remote node ids |
e2023b87 | 1631 | * @sci_dev: This is the device object which is requesting the a remote node |
6f231dda DW |
1632 | * id |
1633 | * @node_id: This is the remote node id that is assinged to the device if one | |
1634 | * is available | |
1635 | * | |
1636 | * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote | |
1637 | * node index available. | |
1638 | */ | |
1639 | enum sci_status scic_sds_controller_allocate_remote_node_context( | |
e2023b87 DJ |
1640 | struct scic_sds_controller *scic, |
1641 | struct scic_sds_remote_device *sci_dev, | |
6f231dda DW |
1642 | u16 *node_id) |
1643 | { | |
1644 | u16 node_index; | |
e2023b87 | 1645 | u32 remote_node_count = scic_sds_remote_device_node_count(sci_dev); |
6f231dda DW |
1646 | |
1647 | node_index = scic_sds_remote_node_table_allocate_remote_node( | |
e2023b87 | 1648 | &scic->available_remote_nodes, remote_node_count |
6f231dda DW |
1649 | ); |
1650 | ||
1651 | if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) { | |
e2023b87 | 1652 | scic->device_table[node_index] = sci_dev; |
6f231dda DW |
1653 | |
1654 | *node_id = node_index; | |
1655 | ||
1656 | return SCI_SUCCESS; | |
1657 | } | |
1658 | ||
1659 | return SCI_FAILURE_INSUFFICIENT_RESOURCES; | |
1660 | } | |
1661 | ||
1662 | /** | |
1663 | * This method frees the remote node index back to the available pool. Once | |
1664 | * this is done the remote node context buffer is no longer valid and can | |
1665 | * not be used. | |
e2023b87 DJ |
1666 | * @scic: |
1667 | * @sci_dev: | |
6f231dda DW |
1668 | * @node_id: |
1669 | * | |
1670 | */ | |
1671 | void scic_sds_controller_free_remote_node_context( | |
e2023b87 DJ |
1672 | struct scic_sds_controller *scic, |
1673 | struct scic_sds_remote_device *sci_dev, | |
6f231dda DW |
1674 | u16 node_id) |
1675 | { | |
e2023b87 | 1676 | u32 remote_node_count = scic_sds_remote_device_node_count(sci_dev); |
6f231dda | 1677 | |
e2023b87 DJ |
1678 | if (scic->device_table[node_id] == sci_dev) { |
1679 | scic->device_table[node_id] = NULL; | |
6f231dda DW |
1680 | |
1681 | scic_sds_remote_node_table_release_remote_node_index( | |
e2023b87 | 1682 | &scic->available_remote_nodes, remote_node_count, node_id |
6f231dda DW |
1683 | ); |
1684 | } | |
1685 | } | |
1686 | ||
1687 | /** | |
1688 | * This method returns the union scu_remote_node_context for the specified remote | |
1689 | * node id. | |
e2023b87 | 1690 | * @scic: |
6f231dda DW |
1691 | * @node_id: |
1692 | * | |
1693 | * union scu_remote_node_context* | |
1694 | */ | |
1695 | union scu_remote_node_context *scic_sds_controller_get_remote_node_context_buffer( | |
e2023b87 | 1696 | struct scic_sds_controller *scic, |
6f231dda DW |
1697 | u16 node_id |
1698 | ) { | |
1699 | if ( | |
e2023b87 DJ |
1700 | (node_id < scic->remote_node_entries) |
1701 | && (scic->device_table[node_id] != NULL) | |
6f231dda | 1702 | ) { |
e2023b87 | 1703 | return &scic->remote_node_context_table[node_id]; |
6f231dda DW |
1704 | } |
1705 | ||
1706 | return NULL; | |
1707 | } | |
1708 | ||
1709 | /** | |
1710 | * | |
1711 | * @resposne_buffer: This is the buffer into which the D2H register FIS will be | |
1712 | * constructed. | |
1713 | * @frame_header: This is the frame header returned by the hardware. | |
1714 | * @frame_buffer: This is the frame buffer returned by the hardware. | |
1715 | * | |
1716 | * This method will combind the frame header and frame buffer to create a SATA | |
1717 | * D2H register FIS none | |
1718 | */ | |
1719 | void scic_sds_controller_copy_sata_response( | |
1720 | void *response_buffer, | |
1721 | void *frame_header, | |
1722 | void *frame_buffer) | |
1723 | { | |
f2f30080 | 1724 | memcpy(response_buffer, frame_header, sizeof(u32)); |
6f231dda | 1725 | |
f2f30080 DJ |
1726 | memcpy(response_buffer + sizeof(u32), |
1727 | frame_buffer, | |
1728 | sizeof(struct dev_to_host_fis) - sizeof(u32)); | |
6f231dda DW |
1729 | } |
1730 | ||
1731 | /** | |
1732 | * This method releases the frame once this is done the frame is available for | |
1733 | * re-use by the hardware. The data contained in the frame header and frame | |
1734 | * buffer is no longer valid. The UF queue get pointer is only updated if UF | |
1735 | * control indicates this is appropriate. | |
e2023b87 | 1736 | * @scic: |
6f231dda DW |
1737 | * @frame_index: |
1738 | * | |
1739 | */ | |
1740 | void scic_sds_controller_release_frame( | |
e2023b87 | 1741 | struct scic_sds_controller *scic, |
6f231dda DW |
1742 | u32 frame_index) |
1743 | { | |
1744 | if (scic_sds_unsolicited_frame_control_release_frame( | |
e2023b87 DJ |
1745 | &scic->uf_control, frame_index) == true) |
1746 | writel(scic->uf_control.get, | |
1747 | &scic->scu_registers->sdma.unsolicited_frame_get_pointer); | |
6f231dda DW |
1748 | } |
1749 | ||
1750 | /** | |
1751 | * This method sets user parameters and OEM parameters to default values. | |
1752 | * Users can override these values utilizing the scic_user_parameters_set() | |
1753 | * and scic_oem_parameters_set() methods. | |
07373a5c | 1754 | * @scic: This parameter specifies the controller for which to set the |
6f231dda DW |
1755 | * configuration parameters to their default values. |
1756 | * | |
1757 | */ | |
d9def184 | 1758 | static void scic_sds_controller_set_default_config_parameters(struct scic_sds_controller *scic) |
6f231dda | 1759 | { |
cc3dbd0a | 1760 | struct isci_host *ihost = scic_to_ihost(scic); |
6f231dda DW |
1761 | u16 index; |
1762 | ||
07373a5c HD |
1763 | /* Default to APC mode. */ |
1764 | scic->oem_parameters.sds1.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE; | |
1765 | ||
1766 | /* Default to APC mode. */ | |
1767 | scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up = 1; | |
1768 | ||
6f231dda | 1769 | /* Default to no SSC operation. */ |
d9def184 | 1770 | scic->oem_parameters.sds1.controller.do_enable_ssc = false; |
6f231dda DW |
1771 | |
1772 | /* Initialize all of the port parameter information to narrow ports. */ | |
1773 | for (index = 0; index < SCI_MAX_PORTS; index++) { | |
d9def184 | 1774 | scic->oem_parameters.sds1.ports[index].phy_mask = 0; |
6f231dda DW |
1775 | } |
1776 | ||
1777 | /* Initialize all of the phy parameter information. */ | |
1778 | for (index = 0; index < SCI_MAX_PHYS; index++) { | |
d044af17 DW |
1779 | /* Default to 6G (i.e. Gen 3) for now. */ |
1780 | scic->user_parameters.sds1.phys[index].max_speed_generation = 3; | |
d9def184 JD |
1781 | |
1782 | /* the frequencies cannot be 0 */ | |
1783 | scic->user_parameters.sds1.phys[index].align_insertion_frequency = 0x7f; | |
1784 | scic->user_parameters.sds1.phys[index].in_connection_align_insertion_frequency = 0xff; | |
1785 | scic->user_parameters.sds1.phys[index].notify_enable_spin_up_insertion_frequency = 0x33; | |
6f231dda DW |
1786 | |
1787 | /* | |
1788 | * Previous Vitesse based expanders had a arbitration issue that | |
1789 | * is worked around by having the upper 32-bits of SAS address | |
1790 | * with a value greater then the Vitesse company identifier. | |
1791 | * Hence, usage of 0x5FCFFFFF. */ | |
4711ba10 | 1792 | scic->oem_parameters.sds1.phys[index].sas_address.low = 0x1 + ihost->id; |
d9def184 | 1793 | scic->oem_parameters.sds1.phys[index].sas_address.high = 0x5FCFFFFF; |
6f231dda DW |
1794 | } |
1795 | ||
d9def184 JD |
1796 | scic->user_parameters.sds1.stp_inactivity_timeout = 5; |
1797 | scic->user_parameters.sds1.ssp_inactivity_timeout = 5; | |
1798 | scic->user_parameters.sds1.stp_max_occupancy_timeout = 5; | |
1799 | scic->user_parameters.sds1.ssp_max_occupancy_timeout = 20; | |
1800 | scic->user_parameters.sds1.no_outbound_task_timeout = 20; | |
6f231dda DW |
1801 | } |
1802 | ||
35173d57 DW |
1803 | /** |
1804 | * scic_controller_get_suggested_start_timeout() - This method returns the | |
1805 | * suggested scic_controller_start() timeout amount. The user is free to | |
1806 | * use any timeout value, but this method provides the suggested minimum | |
1807 | * start timeout value. The returned value is based upon empirical | |
1808 | * information determined as a result of interoperability testing. | |
1809 | * @controller: the handle to the controller object for which to return the | |
1810 | * suggested start timeout. | |
1811 | * | |
1812 | * This method returns the number of milliseconds for the suggested start | |
1813 | * operation timeout. | |
1814 | */ | |
6f231dda DW |
1815 | u32 scic_controller_get_suggested_start_timeout( |
1816 | struct scic_sds_controller *sc) | |
1817 | { | |
1818 | /* Validate the user supplied parameters. */ | |
a7e536c7 | 1819 | if (sc == NULL) |
6f231dda DW |
1820 | return 0; |
1821 | ||
1822 | /* | |
1823 | * The suggested minimum timeout value for a controller start operation: | |
1824 | * | |
1825 | * Signature FIS Timeout | |
1826 | * + Phy Start Timeout | |
1827 | * + Number of Phy Spin Up Intervals | |
1828 | * --------------------------------- | |
1829 | * Number of milliseconds for the controller start operation. | |
1830 | * | |
1831 | * NOTE: The number of phy spin up intervals will be equivalent | |
1832 | * to the number of phys divided by the number phys allowed | |
1833 | * per interval - 1 (once OEM parameters are supported). | |
1834 | * Currently we assume only 1 phy per interval. */ | |
1835 | ||
d9def184 | 1836 | return SCIC_SDS_SIGNATURE_FIS_TIMEOUT |
6f231dda | 1837 | + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT |
d9def184 | 1838 | + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); |
6f231dda DW |
1839 | } |
1840 | ||
35173d57 DW |
1841 | /** |
1842 | * scic_controller_stop() - This method will stop an individual controller | |
1843 | * object.This method will invoke the associated user callback upon | |
1844 | * completion. The completion callback is called when the following | |
1845 | * conditions are met: -# the method return status is SCI_SUCCESS. -# the | |
1846 | * controller has been quiesced. This method will ensure that all IO | |
1847 | * requests are quiesced, phys are stopped, and all additional operation by | |
1848 | * the hardware is halted. | |
1849 | * @controller: the handle to the controller object to stop. | |
1850 | * @timeout: This parameter specifies the number of milliseconds in which the | |
1851 | * stop operation should complete. | |
1852 | * | |
1853 | * The controller must be in the STARTED or STOPPED state. Indicate if the | |
1854 | * controller stop method succeeded or failed in some way. SCI_SUCCESS if the | |
1855 | * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the | |
1856 | * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the | |
1857 | * controller is not either in the STARTED or STOPPED states. | |
1858 | */ | |
6f231dda DW |
1859 | enum sci_status scic_controller_stop( |
1860 | struct scic_sds_controller *scic, | |
1861 | u32 timeout) | |
1862 | { | |
c629582d CH |
1863 | if (scic->state_machine.current_state_id != |
1864 | SCI_BASE_CONTROLLER_STATE_READY) { | |
6f231dda | 1865 | dev_warn(scic_to_dev(scic), |
c629582d CH |
1866 | "SCIC Controller stop operation requested in " |
1867 | "invalid state\n"); | |
1868 | return SCI_FAILURE_INVALID_STATE; | |
1869 | } | |
6f231dda | 1870 | |
c629582d CH |
1871 | isci_timer_start(scic->timeout_timer, timeout); |
1872 | sci_base_state_machine_change_state(&scic->state_machine, | |
1873 | SCI_BASE_CONTROLLER_STATE_STOPPING); | |
1874 | return SCI_SUCCESS; | |
6f231dda DW |
1875 | } |
1876 | ||
35173d57 DW |
1877 | /** |
1878 | * scic_controller_reset() - This method will reset the supplied core | |
1879 | * controller regardless of the state of said controller. This operation is | |
1880 | * considered destructive. In other words, all current operations are wiped | |
1881 | * out. No IO completions for outstanding devices occur. Outstanding IO | |
1882 | * requests are not aborted or completed at the actual remote device. | |
1883 | * @controller: the handle to the controller object to reset. | |
1884 | * | |
1885 | * Indicate if the controller reset method succeeded or failed in some way. | |
1886 | * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if | |
1887 | * the controller reset operation is unable to complete. | |
1888 | */ | |
6f231dda DW |
1889 | enum sci_status scic_controller_reset( |
1890 | struct scic_sds_controller *scic) | |
1891 | { | |
c629582d CH |
1892 | switch (scic->state_machine.current_state_id) { |
1893 | case SCI_BASE_CONTROLLER_STATE_RESET: | |
1894 | case SCI_BASE_CONTROLLER_STATE_READY: | |
1895 | case SCI_BASE_CONTROLLER_STATE_STOPPED: | |
1896 | case SCI_BASE_CONTROLLER_STATE_FAILED: | |
1897 | /* | |
1898 | * The reset operation is not a graceful cleanup, just | |
1899 | * perform the state transition. | |
1900 | */ | |
1901 | sci_base_state_machine_change_state(&scic->state_machine, | |
1902 | SCI_BASE_CONTROLLER_STATE_RESETTING); | |
1903 | return SCI_SUCCESS; | |
1904 | default: | |
6f231dda | 1905 | dev_warn(scic_to_dev(scic), |
c629582d CH |
1906 | "SCIC Controller reset operation requested in " |
1907 | "invalid state\n"); | |
1908 | return SCI_FAILURE_INVALID_STATE; | |
1909 | } | |
6f231dda DW |
1910 | } |
1911 | ||
35173d57 DW |
1912 | /** |
1913 | * scic_controller_start_io() - This method is called by the SCI user to | |
1914 | * send/start an IO request. If the method invocation is successful, then | |
1915 | * the IO request has been queued to the hardware for processing. | |
1916 | * @controller: the handle to the controller object for which to start an IO | |
1917 | * request. | |
1918 | * @remote_device: the handle to the remote device object for which to start an | |
1919 | * IO request. | |
1920 | * @io_request: the handle to the io request object to start. | |
1921 | * @io_tag: This parameter specifies a previously allocated IO tag that the | |
1922 | * user desires to be utilized for this request. This parameter is optional. | |
1923 | * The user is allowed to supply SCI_CONTROLLER_INVALID_IO_TAG as the value | |
1924 | * for this parameter. | |
1925 | * | |
1926 | * - IO tags are a protected resource. It is incumbent upon the SCI Core user | |
1927 | * to ensure that each of the methods that may allocate or free available IO | |
1928 | * tags are handled in a mutually exclusive manner. This method is one of said | |
1929 | * methods requiring proper critical code section protection (e.g. semaphore, | |
1930 | * spin-lock, etc.). - For SATA, the user is required to manage NCQ tags. As a | |
1931 | * result, it is expected the user will have set the NCQ tag field in the host | |
1932 | * to device register FIS prior to calling this method. There is also a | |
1933 | * requirement for the user to call scic_stp_io_set_ncq_tag() prior to invoking | |
1934 | * the scic_controller_start_io() method. scic_controller_allocate_tag() for | |
1935 | * more information on allocating a tag. Indicate if the controller | |
467e855a | 1936 | * successfully started the IO request. SCI_SUCCESS if the IO request was |
35173d57 DW |
1937 | * successfully started. Determine the failure situations and return values. |
1938 | */ | |
467e855a | 1939 | enum sci_status scic_controller_start_io( |
6f231dda | 1940 | struct scic_sds_controller *scic, |
c629582d CH |
1941 | struct scic_sds_remote_device *rdev, |
1942 | struct scic_sds_request *req, | |
6f231dda DW |
1943 | u16 io_tag) |
1944 | { | |
c629582d | 1945 | enum sci_status status; |
6f231dda | 1946 | |
c629582d CH |
1947 | if (scic->state_machine.current_state_id != |
1948 | SCI_BASE_CONTROLLER_STATE_READY) { | |
1949 | dev_warn(scic_to_dev(scic), "invalid state to start I/O"); | |
1950 | return SCI_FAILURE_INVALID_STATE; | |
1951 | } | |
6f231dda | 1952 | |
c629582d CH |
1953 | status = scic_sds_remote_device_start_io(scic, rdev, req); |
1954 | if (status != SCI_SUCCESS) | |
1955 | return status; | |
1956 | ||
1957 | scic->io_request_table[scic_sds_io_tag_get_index(req->io_tag)] = req; | |
1958 | scic_sds_controller_post_request(scic, scic_sds_request_get_post_context(req)); | |
1959 | return SCI_SUCCESS; | |
6f231dda DW |
1960 | } |
1961 | ||
35173d57 DW |
1962 | /** |
1963 | * scic_controller_terminate_request() - This method is called by the SCI Core | |
1964 | * user to terminate an ongoing (i.e. started) core IO request. This does | |
1965 | * not abort the IO request at the target, but rather removes the IO request | |
1966 | * from the host controller. | |
1967 | * @controller: the handle to the controller object for which to terminate a | |
1968 | * request. | |
1969 | * @remote_device: the handle to the remote device object for which to | |
1970 | * terminate a request. | |
1971 | * @request: the handle to the io or task management request object to | |
1972 | * terminate. | |
1973 | * | |
1974 | * Indicate if the controller successfully began the terminate process for the | |
1975 | * IO request. SCI_SUCCESS if the terminate process was successfully started | |
1976 | * for the request. Determine the failure situations and return values. | |
1977 | */ | |
6f231dda DW |
1978 | enum sci_status scic_controller_terminate_request( |
1979 | struct scic_sds_controller *scic, | |
c629582d CH |
1980 | struct scic_sds_remote_device *rdev, |
1981 | struct scic_sds_request *req) | |
6f231dda | 1982 | { |
c629582d | 1983 | enum sci_status status; |
6f231dda | 1984 | |
c629582d CH |
1985 | if (scic->state_machine.current_state_id != |
1986 | SCI_BASE_CONTROLLER_STATE_READY) { | |
1987 | dev_warn(scic_to_dev(scic), | |
1988 | "invalid state to terminate request\n"); | |
1989 | return SCI_FAILURE_INVALID_STATE; | |
1990 | } | |
6f231dda | 1991 | |
c629582d CH |
1992 | status = scic_sds_io_request_terminate(req); |
1993 | if (status != SCI_SUCCESS) | |
1994 | return status; | |
1995 | ||
1996 | /* | |
1997 | * Utilize the original post context command and or in the POST_TC_ABORT | |
1998 | * request sub-type. | |
1999 | */ | |
2000 | scic_sds_controller_post_request(scic, | |
2001 | scic_sds_request_get_post_context(req) | | |
2002 | SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT); | |
2003 | return SCI_SUCCESS; | |
6f231dda DW |
2004 | } |
2005 | ||
35173d57 DW |
2006 | /** |
2007 | * scic_controller_complete_io() - This method will perform core specific | |
2008 | * completion operations for an IO request. After this method is invoked, | |
2009 | * the user should consider the IO request as invalid until it is properly | |
2010 | * reused (i.e. re-constructed). | |
2011 | * @controller: The handle to the controller object for which to complete the | |
2012 | * IO request. | |
2013 | * @remote_device: The handle to the remote device object for which to complete | |
2014 | * the IO request. | |
2015 | * @io_request: the handle to the io request object to complete. | |
2016 | * | |
2017 | * - IO tags are a protected resource. It is incumbent upon the SCI Core user | |
2018 | * to ensure that each of the methods that may allocate or free available IO | |
2019 | * tags are handled in a mutually exclusive manner. This method is one of said | |
2020 | * methods requiring proper critical code section protection (e.g. semaphore, | |
2021 | * spin-lock, etc.). - If the IO tag for a request was allocated, by the SCI | |
2022 | * Core user, using the scic_controller_allocate_io_tag() method, then it is | |
2023 | * the responsibility of the caller to invoke the scic_controller_free_io_tag() | |
2024 | * method to free the tag (i.e. this method will not free the IO tag). Indicate | |
2025 | * if the controller successfully completed the IO request. SCI_SUCCESS if the | |
2026 | * completion process was successful. | |
2027 | */ | |
6f231dda DW |
2028 | enum sci_status scic_controller_complete_io( |
2029 | struct scic_sds_controller *scic, | |
c629582d | 2030 | struct scic_sds_remote_device *rdev, |
38aa74eb | 2031 | struct scic_sds_request *request) |
6f231dda | 2032 | { |
c629582d CH |
2033 | enum sci_status status; |
2034 | u16 index; | |
2035 | ||
2036 | switch (scic->state_machine.current_state_id) { | |
2037 | case SCI_BASE_CONTROLLER_STATE_STOPPING: | |
2038 | /* XXX: Implement this function */ | |
2039 | return SCI_FAILURE; | |
2040 | case SCI_BASE_CONTROLLER_STATE_READY: | |
2041 | status = scic_sds_remote_device_complete_io(scic, rdev, request); | |
2042 | if (status != SCI_SUCCESS) | |
2043 | return status; | |
2044 | ||
2045 | index = scic_sds_io_tag_get_index(request->io_tag); | |
2046 | scic->io_request_table[index] = NULL; | |
2047 | return SCI_SUCCESS; | |
2048 | default: | |
2049 | dev_warn(scic_to_dev(scic), "invalid state to complete I/O"); | |
2050 | return SCI_FAILURE_INVALID_STATE; | |
2051 | } | |
2052 | ||
2053 | } | |
2054 | ||
2055 | enum sci_status scic_controller_continue_io(struct scic_sds_request *sci_req) | |
2056 | { | |
2057 | struct scic_sds_controller *scic = sci_req->owning_controller; | |
6f231dda | 2058 | |
c629582d CH |
2059 | if (scic->state_machine.current_state_id != |
2060 | SCI_BASE_CONTROLLER_STATE_READY) { | |
2061 | dev_warn(scic_to_dev(scic), "invalid state to continue I/O"); | |
2062 | return SCI_FAILURE_INVALID_STATE; | |
2063 | } | |
6f231dda | 2064 | |
c629582d CH |
2065 | scic->io_request_table[scic_sds_io_tag_get_index(sci_req->io_tag)] = sci_req; |
2066 | scic_sds_controller_post_request(scic, scic_sds_request_get_post_context(sci_req)); | |
2067 | return SCI_SUCCESS; | |
6f231dda DW |
2068 | } |
2069 | ||
35173d57 DW |
2070 | /** |
2071 | * scic_controller_start_task() - This method is called by the SCIC user to | |
2072 | * send/start a framework task management request. | |
2073 | * @controller: the handle to the controller object for which to start the task | |
2074 | * management request. | |
2075 | * @remote_device: the handle to the remote device object for which to start | |
2076 | * the task management request. | |
2077 | * @task_request: the handle to the task request object to start. | |
2078 | * @io_tag: This parameter specifies a previously allocated IO tag that the | |
2079 | * user desires to be utilized for this request. Note this not the io_tag | |
2080 | * of the request being managed. It is to be utilized for the task request | |
2081 | * itself. This parameter is optional. The user is allowed to supply | |
2082 | * SCI_CONTROLLER_INVALID_IO_TAG as the value for this parameter. | |
2083 | * | |
2084 | * - IO tags are a protected resource. It is incumbent upon the SCI Core user | |
2085 | * to ensure that each of the methods that may allocate or free available IO | |
2086 | * tags are handled in a mutually exclusive manner. This method is one of said | |
2087 | * methods requiring proper critical code section protection (e.g. semaphore, | |
2088 | * spin-lock, etc.). - The user must synchronize this task with completion | |
2089 | * queue processing. If they are not synchronized then it is possible for the | |
2090 | * io requests that are being managed by the task request can complete before | |
2091 | * starting the task request. scic_controller_allocate_tag() for more | |
2092 | * information on allocating a tag. Indicate if the controller successfully | |
2093 | * started the IO request. SCI_TASK_SUCCESS if the task request was | |
2094 | * successfully started. SCI_TASK_FAILURE_REQUIRES_SCSI_ABORT This value is | |
2095 | * returned if there is/are task(s) outstanding that require termination or | |
2096 | * completion before this request can succeed. | |
2097 | */ | |
6f231dda DW |
2098 | enum sci_task_status scic_controller_start_task( |
2099 | struct scic_sds_controller *scic, | |
c629582d CH |
2100 | struct scic_sds_remote_device *rdev, |
2101 | struct scic_sds_request *req, | |
6f231dda DW |
2102 | u16 task_tag) |
2103 | { | |
c629582d | 2104 | enum sci_status status; |
6f231dda | 2105 | |
c629582d CH |
2106 | if (scic->state_machine.current_state_id != |
2107 | SCI_BASE_CONTROLLER_STATE_READY) { | |
6f231dda DW |
2108 | dev_warn(scic_to_dev(scic), |
2109 | "%s: SCIC Controller starting task from invalid " | |
2110 | "state\n", | |
2111 | __func__); | |
c629582d CH |
2112 | return SCI_TASK_FAILURE_INVALID_STATE; |
2113 | } | |
6f231dda | 2114 | |
c629582d CH |
2115 | status = scic_sds_remote_device_start_task(scic, rdev, req); |
2116 | switch (status) { | |
2117 | case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS: | |
2118 | scic->io_request_table[scic_sds_io_tag_get_index(req->io_tag)] = req; | |
6f231dda | 2119 | |
c629582d CH |
2120 | /* |
2121 | * We will let framework know this task request started successfully, | |
2122 | * although core is still woring on starting the request (to post tc when | |
2123 | * RNC is resumed.) | |
2124 | */ | |
2125 | return SCI_SUCCESS; | |
2126 | case SCI_SUCCESS: | |
2127 | scic->io_request_table[scic_sds_io_tag_get_index(req->io_tag)] = req; | |
6f231dda | 2128 | |
c629582d CH |
2129 | scic_sds_controller_post_request(scic, |
2130 | scic_sds_request_get_post_context(req)); | |
2131 | break; | |
2132 | default: | |
2133 | break; | |
2134 | } | |
6f231dda DW |
2135 | |
2136 | return status; | |
2137 | } | |
2138 | ||
35173d57 DW |
2139 | /** |
2140 | * scic_controller_allocate_io_tag() - This method will allocate a tag from the | |
2141 | * pool of free IO tags. Direct allocation of IO tags by the SCI Core user | |
2142 | * is optional. The scic_controller_start_io() method will allocate an IO | |
2143 | * tag if this method is not utilized and the tag is not supplied to the IO | |
2144 | * construct routine. Direct allocation of IO tags may provide additional | |
2145 | * performance improvements in environments capable of supporting this usage | |
2146 | * model. Additionally, direct allocation of IO tags also provides | |
2147 | * additional flexibility to the SCI Core user. Specifically, the user may | |
2148 | * retain IO tags across the lives of multiple IO requests. | |
2149 | * @controller: the handle to the controller object for which to allocate the | |
2150 | * tag. | |
2151 | * | |
2152 | * IO tags are a protected resource. It is incumbent upon the SCI Core user to | |
2153 | * ensure that each of the methods that may allocate or free available IO tags | |
2154 | * are handled in a mutually exclusive manner. This method is one of said | |
2155 | * methods requiring proper critical code section protection (e.g. semaphore, | |
2156 | * spin-lock, etc.). An unsigned integer representing an available IO tag. | |
2157 | * SCI_CONTROLLER_INVALID_IO_TAG This value is returned if there are no | |
2158 | * currently available tags to be allocated. All return other values indicate a | |
2159 | * legitimate tag. | |
2160 | */ | |
6f231dda DW |
2161 | u16 scic_controller_allocate_io_tag( |
2162 | struct scic_sds_controller *scic) | |
2163 | { | |
2164 | u16 task_context; | |
2165 | u16 sequence_count; | |
2166 | ||
2167 | if (!sci_pool_empty(scic->tci_pool)) { | |
2168 | sci_pool_get(scic->tci_pool, task_context); | |
2169 | ||
2170 | sequence_count = scic->io_request_sequence[task_context]; | |
2171 | ||
2172 | return scic_sds_io_tag_construct(sequence_count, task_context); | |
2173 | } | |
2174 | ||
2175 | return SCI_CONTROLLER_INVALID_IO_TAG; | |
2176 | } | |
2177 | ||
35173d57 DW |
2178 | /** |
2179 | * scic_controller_free_io_tag() - This method will free an IO tag to the pool | |
2180 | * of free IO tags. This method provides the SCI Core user more flexibility | |
2181 | * with regards to IO tags. The user may desire to keep an IO tag after an | |
2182 | * IO request has completed, because they plan on re-using the tag for a | |
2183 | * subsequent IO request. This method is only legal if the tag was | |
2184 | * allocated via scic_controller_allocate_io_tag(). | |
2185 | * @controller: This parameter specifies the handle to the controller object | |
2186 | * for which to free/return the tag. | |
2187 | * @io_tag: This parameter represents the tag to be freed to the pool of | |
2188 | * available tags. | |
2189 | * | |
2190 | * - IO tags are a protected resource. It is incumbent upon the SCI Core user | |
2191 | * to ensure that each of the methods that may allocate or free available IO | |
2192 | * tags are handled in a mutually exclusive manner. This method is one of said | |
2193 | * methods requiring proper critical code section protection (e.g. semaphore, | |
2194 | * spin-lock, etc.). - If the IO tag for a request was allocated, by the SCI | |
2195 | * Core user, using the scic_controller_allocate_io_tag() method, then it is | |
2196 | * the responsibility of the caller to invoke this method to free the tag. This | |
2197 | * method returns an indication of whether the tag was successfully put back | |
2198 | * (freed) to the pool of available tags. SCI_SUCCESS This return value | |
2199 | * indicates the tag was successfully placed into the pool of available IO | |
2200 | * tags. SCI_FAILURE_INVALID_IO_TAG This value is returned if the supplied tag | |
2201 | * is not a valid IO tag value. | |
2202 | */ | |
6f231dda DW |
2203 | enum sci_status scic_controller_free_io_tag( |
2204 | struct scic_sds_controller *scic, | |
2205 | u16 io_tag) | |
2206 | { | |
2207 | u16 sequence; | |
2208 | u16 index; | |
2209 | ||
2210 | BUG_ON(io_tag == SCI_CONTROLLER_INVALID_IO_TAG); | |
2211 | ||
2212 | sequence = scic_sds_io_tag_get_sequence(io_tag); | |
2213 | index = scic_sds_io_tag_get_index(io_tag); | |
2214 | ||
2215 | if (!sci_pool_full(scic->tci_pool)) { | |
2216 | if (sequence == scic->io_request_sequence[index]) { | |
2217 | scic_sds_io_sequence_increment( | |
2218 | scic->io_request_sequence[index]); | |
2219 | ||
2220 | sci_pool_put(scic->tci_pool, index); | |
2221 | ||
2222 | return SCI_SUCCESS; | |
2223 | } | |
2224 | } | |
2225 | ||
2226 | return SCI_FAILURE_INVALID_IO_TAG; | |
2227 | } | |
2228 | ||
6f231dda DW |
2229 | void scic_controller_enable_interrupts( |
2230 | struct scic_sds_controller *scic) | |
2231 | { | |
2232 | BUG_ON(scic->smu_registers == NULL); | |
bc99aa47 | 2233 | writel(0, &scic->smu_registers->interrupt_mask); |
6f231dda DW |
2234 | } |
2235 | ||
6f231dda DW |
2236 | void scic_controller_disable_interrupts( |
2237 | struct scic_sds_controller *scic) | |
2238 | { | |
2239 | BUG_ON(scic->smu_registers == NULL); | |
bc99aa47 | 2240 | writel(0xffffffff, &scic->smu_registers->interrupt_mask); |
6f231dda DW |
2241 | } |
2242 | ||
35173d57 | 2243 | static enum sci_status scic_controller_set_mode( |
6f231dda DW |
2244 | struct scic_sds_controller *scic, |
2245 | enum sci_controller_mode operating_mode) | |
2246 | { | |
2247 | enum sci_status status = SCI_SUCCESS; | |
2248 | ||
ca841f0e | 2249 | if ((scic->state_machine.current_state_id == |
6f231dda | 2250 | SCI_BASE_CONTROLLER_STATE_INITIALIZING) || |
ca841f0e | 2251 | (scic->state_machine.current_state_id == |
6f231dda DW |
2252 | SCI_BASE_CONTROLLER_STATE_INITIALIZED)) { |
2253 | switch (operating_mode) { | |
2254 | case SCI_MODE_SPEED: | |
2255 | scic->remote_node_entries = SCI_MAX_REMOTE_DEVICES; | |
2256 | scic->task_context_entries = SCU_IO_REQUEST_COUNT; | |
2257 | scic->uf_control.buffers.count = | |
2258 | SCU_UNSOLICITED_FRAME_COUNT; | |
2259 | scic->completion_event_entries = SCU_EVENT_COUNT; | |
2260 | scic->completion_queue_entries = | |
2261 | SCU_COMPLETION_QUEUE_COUNT; | |
6f231dda DW |
2262 | break; |
2263 | ||
2264 | case SCI_MODE_SIZE: | |
2265 | scic->remote_node_entries = SCI_MIN_REMOTE_DEVICES; | |
2266 | scic->task_context_entries = SCI_MIN_IO_REQUESTS; | |
2267 | scic->uf_control.buffers.count = | |
2268 | SCU_MIN_UNSOLICITED_FRAMES; | |
2269 | scic->completion_event_entries = SCU_MIN_EVENTS; | |
2270 | scic->completion_queue_entries = | |
2271 | SCU_MIN_COMPLETION_QUEUE_ENTRIES; | |
6f231dda DW |
2272 | break; |
2273 | ||
2274 | default: | |
2275 | status = SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
2276 | break; | |
2277 | } | |
2278 | } else | |
2279 | status = SCI_FAILURE_INVALID_STATE; | |
2280 | ||
2281 | return status; | |
2282 | } | |
2283 | ||
2284 | /** | |
2285 | * scic_sds_controller_reset_hardware() - | |
2286 | * | |
2287 | * This method will reset the controller hardware. | |
2288 | */ | |
35173d57 | 2289 | static void scic_sds_controller_reset_hardware( |
6f231dda DW |
2290 | struct scic_sds_controller *scic) |
2291 | { | |
2292 | /* Disable interrupts so we dont take any spurious interrupts */ | |
2293 | scic_controller_disable_interrupts(scic); | |
2294 | ||
2295 | /* Reset the SCU */ | |
bc99aa47 | 2296 | writel(0xFFFFFFFF, &scic->smu_registers->soft_reset_control); |
6f231dda DW |
2297 | |
2298 | /* Delay for 1ms to before clearing the CQP and UFQPR. */ | |
7392d275 | 2299 | udelay(1000); |
6f231dda DW |
2300 | |
2301 | /* The write to the CQGR clears the CQP */ | |
bc99aa47 | 2302 | writel(0x00000000, &scic->smu_registers->completion_queue_get); |
6f231dda DW |
2303 | |
2304 | /* The write to the UFQGP clears the UFQPR */ | |
bc99aa47 | 2305 | writel(0, &scic->scu_registers->sdma.unsolicited_frame_get_pointer); |
6f231dda DW |
2306 | } |
2307 | ||
6f231dda DW |
2308 | enum sci_status scic_user_parameters_set( |
2309 | struct scic_sds_controller *scic, | |
2310 | union scic_user_parameters *scic_parms) | |
2311 | { | |
ca841f0e | 2312 | u32 state = scic->state_machine.current_state_id; |
b5f18a20 DJ |
2313 | |
2314 | if (state == SCI_BASE_CONTROLLER_STATE_RESET || | |
2315 | state == SCI_BASE_CONTROLLER_STATE_INITIALIZING || | |
2316 | state == SCI_BASE_CONTROLLER_STATE_INITIALIZED) { | |
6f231dda DW |
2317 | u16 index; |
2318 | ||
2319 | /* | |
2320 | * Validate the user parameters. If they are not legal, then | |
b5f18a20 DJ |
2321 | * return a failure. |
2322 | */ | |
6f231dda | 2323 | for (index = 0; index < SCI_MAX_PHYS; index++) { |
b5f18a20 DJ |
2324 | struct sci_phy_user_params *user_phy; |
2325 | ||
2326 | user_phy = &scic_parms->sds1.phys[index]; | |
2327 | ||
2328 | if (!((user_phy->max_speed_generation <= | |
2329 | SCIC_SDS_PARM_MAX_SPEED) && | |
2330 | (user_phy->max_speed_generation > | |
2331 | SCIC_SDS_PARM_NO_SPEED))) | |
d9def184 JD |
2332 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; |
2333 | ||
b5f18a20 DJ |
2334 | if (user_phy->in_connection_align_insertion_frequency < |
2335 | 3) | |
d9def184 | 2336 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; |
b5f18a20 DJ |
2337 | |
2338 | if ((user_phy->in_connection_align_insertion_frequency < | |
2339 | 3) || | |
2340 | (user_phy->align_insertion_frequency == 0) || | |
2341 | (user_phy-> | |
2342 | notify_enable_spin_up_insertion_frequency == | |
2343 | 0)) | |
6f231dda DW |
2344 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; |
2345 | } | |
2346 | ||
d9def184 | 2347 | if ((scic_parms->sds1.stp_inactivity_timeout == 0) || |
b5f18a20 DJ |
2348 | (scic_parms->sds1.ssp_inactivity_timeout == 0) || |
2349 | (scic_parms->sds1.stp_max_occupancy_timeout == 0) || | |
2350 | (scic_parms->sds1.ssp_max_occupancy_timeout == 0) || | |
2351 | (scic_parms->sds1.no_outbound_task_timeout == 0)) | |
d9def184 JD |
2352 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; |
2353 | ||
6f231dda DW |
2354 | memcpy(&scic->user_parameters, scic_parms, sizeof(*scic_parms)); |
2355 | ||
2356 | return SCI_SUCCESS; | |
2357 | } | |
2358 | ||
2359 | return SCI_FAILURE_INVALID_STATE; | |
2360 | } | |
2361 | ||
2d70de5a | 2362 | int scic_oem_parameters_validate(struct scic_sds_oem_params *oem) |
6f231dda | 2363 | { |
2d70de5a | 2364 | int i; |
4711ba10 | 2365 | |
2d70de5a DW |
2366 | for (i = 0; i < SCI_MAX_PORTS; i++) |
2367 | if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX) | |
2368 | return -EINVAL; | |
6f231dda | 2369 | |
2d70de5a DW |
2370 | for (i = 0; i < SCI_MAX_PHYS; i++) |
2371 | if (oem->phys[i].sas_address.high == 0 && | |
2372 | oem->phys[i].sas_address.low == 0) | |
2373 | return -EINVAL; | |
6f231dda | 2374 | |
2d70de5a DW |
2375 | if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) { |
2376 | for (i = 0; i < SCI_MAX_PHYS; i++) | |
2377 | if (oem->ports[i].phy_mask != 0) | |
2378 | return -EINVAL; | |
2379 | } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) { | |
2380 | u8 phy_mask = 0; | |
6f231dda | 2381 | |
2d70de5a DW |
2382 | for (i = 0; i < SCI_MAX_PHYS; i++) |
2383 | phy_mask |= oem->ports[i].phy_mask; | |
07373a5c | 2384 | |
2d70de5a DW |
2385 | if (phy_mask == 0) |
2386 | return -EINVAL; | |
2387 | } else | |
2388 | return -EINVAL; | |
07373a5c | 2389 | |
2d70de5a DW |
2390 | if (oem->controller.max_concurrent_dev_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT) |
2391 | return -EINVAL; | |
07373a5c | 2392 | |
2d70de5a DW |
2393 | return 0; |
2394 | } | |
2395 | ||
2396 | enum sci_status scic_oem_parameters_set(struct scic_sds_controller *scic, | |
2397 | union scic_oem_parameters *scic_parms) | |
2398 | { | |
2399 | u32 state = scic->state_machine.current_state_id; | |
2400 | ||
2401 | if (state == SCI_BASE_CONTROLLER_STATE_RESET || | |
2402 | state == SCI_BASE_CONTROLLER_STATE_INITIALIZING || | |
2403 | state == SCI_BASE_CONTROLLER_STATE_INITIALIZED) { | |
2404 | ||
2405 | if (scic_oem_parameters_validate(&scic_parms->sds1)) | |
2406 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
4711ba10 DW |
2407 | scic->oem_parameters.sds1 = scic_parms->sds1; |
2408 | ||
6f231dda DW |
2409 | return SCI_SUCCESS; |
2410 | } | |
2411 | ||
2412 | return SCI_FAILURE_INVALID_STATE; | |
2413 | } | |
2414 | ||
6f231dda DW |
2415 | void scic_oem_parameters_get( |
2416 | struct scic_sds_controller *scic, | |
2417 | union scic_oem_parameters *scic_parms) | |
2418 | { | |
2419 | memcpy(scic_parms, (&scic->oem_parameters), sizeof(*scic_parms)); | |
2420 | } | |
2421 | ||
6f231dda DW |
2422 | #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853 |
2423 | #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280 | |
2424 | #define INTERRUPT_COALESCE_TIMEOUT_MAX_US 2700000 | |
2425 | #define INTERRUPT_COALESCE_NUMBER_MAX 256 | |
2426 | #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN 7 | |
2427 | #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX 28 | |
2428 | ||
35173d57 DW |
2429 | /** |
2430 | * scic_controller_set_interrupt_coalescence() - This method allows the user to | |
2431 | * configure the interrupt coalescence. | |
2432 | * @controller: This parameter represents the handle to the controller object | |
2433 | * for which its interrupt coalesce register is overridden. | |
2434 | * @coalesce_number: Used to control the number of entries in the Completion | |
2435 | * Queue before an interrupt is generated. If the number of entries exceed | |
2436 | * this number, an interrupt will be generated. The valid range of the input | |
2437 | * is [0, 256]. A setting of 0 results in coalescing being disabled. | |
2438 | * @coalesce_timeout: Timeout value in microseconds. The valid range of the | |
2439 | * input is [0, 2700000] . A setting of 0 is allowed and results in no | |
2440 | * interrupt coalescing timeout. | |
2441 | * | |
2442 | * Indicate if the user successfully set the interrupt coalesce parameters. | |
2443 | * SCI_SUCCESS The user successfully updated the interrutp coalescence. | |
2444 | * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range. | |
2445 | */ | |
2446 | static enum sci_status scic_controller_set_interrupt_coalescence( | |
6f231dda DW |
2447 | struct scic_sds_controller *scic_controller, |
2448 | u32 coalesce_number, | |
2449 | u32 coalesce_timeout) | |
2450 | { | |
2451 | u8 timeout_encode = 0; | |
2452 | u32 min = 0; | |
2453 | u32 max = 0; | |
2454 | ||
2455 | /* Check if the input parameters fall in the range. */ | |
2456 | if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX) | |
2457 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
2458 | ||
2459 | /* | |
2460 | * Defined encoding for interrupt coalescing timeout: | |
2461 | * Value Min Max Units | |
2462 | * ----- --- --- ----- | |
2463 | * 0 - - Disabled | |
2464 | * 1 13.3 20.0 ns | |
2465 | * 2 26.7 40.0 | |
2466 | * 3 53.3 80.0 | |
2467 | * 4 106.7 160.0 | |
2468 | * 5 213.3 320.0 | |
2469 | * 6 426.7 640.0 | |
2470 | * 7 853.3 1280.0 | |
2471 | * 8 1.7 2.6 us | |
2472 | * 9 3.4 5.1 | |
2473 | * 10 6.8 10.2 | |
2474 | * 11 13.7 20.5 | |
2475 | * 12 27.3 41.0 | |
2476 | * 13 54.6 81.9 | |
2477 | * 14 109.2 163.8 | |
2478 | * 15 218.5 327.7 | |
2479 | * 16 436.9 655.4 | |
2480 | * 17 873.8 1310.7 | |
2481 | * 18 1.7 2.6 ms | |
2482 | * 19 3.5 5.2 | |
2483 | * 20 7.0 10.5 | |
2484 | * 21 14.0 21.0 | |
2485 | * 22 28.0 41.9 | |
2486 | * 23 55.9 83.9 | |
2487 | * 24 111.8 167.8 | |
2488 | * 25 223.7 335.5 | |
2489 | * 26 447.4 671.1 | |
2490 | * 27 894.8 1342.2 | |
2491 | * 28 1.8 2.7 s | |
2492 | * Others Undefined */ | |
2493 | ||
2494 | /* | |
2495 | * Use the table above to decide the encode of interrupt coalescing timeout | |
2496 | * value for register writing. */ | |
2497 | if (coalesce_timeout == 0) | |
2498 | timeout_encode = 0; | |
2499 | else{ | |
2500 | /* make the timeout value in unit of (10 ns). */ | |
2501 | coalesce_timeout = coalesce_timeout * 100; | |
2502 | min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10; | |
2503 | max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10; | |
2504 | ||
2505 | /* get the encode of timeout for register writing. */ | |
2506 | for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN; | |
2507 | timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX; | |
2508 | timeout_encode++) { | |
2509 | if (min <= coalesce_timeout && max > coalesce_timeout) | |
2510 | break; | |
2511 | else if (coalesce_timeout >= max && coalesce_timeout < min * 2 | |
2512 | && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) { | |
2513 | if ((coalesce_timeout - max) < (2 * min - coalesce_timeout)) | |
2514 | break; | |
2515 | else{ | |
2516 | timeout_encode++; | |
2517 | break; | |
2518 | } | |
2519 | } else { | |
2520 | max = max * 2; | |
2521 | min = min * 2; | |
2522 | } | |
2523 | } | |
2524 | ||
2525 | if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1) | |
2526 | /* the value is out of range. */ | |
2527 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
2528 | } | |
2529 | ||
bc99aa47 CH |
2530 | writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) | |
2531 | SMU_ICC_GEN_VAL(TIMER, timeout_encode), | |
2532 | &scic_controller->smu_registers->interrupt_coalesce_control); | |
2533 | ||
6f231dda DW |
2534 | |
2535 | scic_controller->interrupt_coalesce_number = (u16)coalesce_number; | |
2536 | scic_controller->interrupt_coalesce_timeout = coalesce_timeout / 100; | |
2537 | ||
2538 | return SCI_SUCCESS; | |
2539 | } | |
2540 | ||
2541 | ||
6f231dda | 2542 | |
cc3dbd0a | 2543 | enum sci_status scic_controller_initialize(struct scic_sds_controller *scic) |
6f231dda | 2544 | { |
ca841f0e | 2545 | struct sci_base_state_machine *sm = &scic->state_machine; |
6f231dda | 2546 | enum sci_status result = SCI_SUCCESS; |
cc3dbd0a | 2547 | struct isci_host *ihost = scic_to_ihost(scic); |
068b2c03 | 2548 | u32 index, state; |
6f231dda | 2549 | |
c629582d CH |
2550 | if (scic->state_machine.current_state_id != |
2551 | SCI_BASE_CONTROLLER_STATE_RESET) { | |
2552 | dev_warn(scic_to_dev(scic), | |
2553 | "SCIC Controller initialize operation requested " | |
2554 | "in invalid state\n"); | |
2555 | return SCI_FAILURE_INVALID_STATE; | |
2556 | } | |
2557 | ||
068b2c03 | 2558 | sci_base_state_machine_change_state(sm, SCI_BASE_CONTROLLER_STATE_INITIALIZING); |
6f231dda | 2559 | |
09d7da13 DJ |
2560 | scic->timeout_timer = isci_timer_create(ihost, |
2561 | scic, | |
2562 | scic_sds_controller_timeout_handler); | |
6f231dda | 2563 | |
09d7da13 | 2564 | scic_sds_controller_initialize_phy_startup(scic); |
6f231dda | 2565 | |
09d7da13 | 2566 | scic_sds_controller_initialize_power_control(scic); |
6f231dda DW |
2567 | |
2568 | /* | |
2569 | * There is nothing to do here for B0 since we do not have to | |
2570 | * program the AFE registers. | |
2571 | * / @todo The AFE settings are supposed to be correct for the B0 but | |
2572 | * / presently they seem to be wrong. */ | |
09d7da13 | 2573 | scic_sds_controller_afe_initialization(scic); |
6f231dda | 2574 | |
09d7da13 | 2575 | if (result == SCI_SUCCESS) { |
6f231dda DW |
2576 | u32 status; |
2577 | u32 terminate_loop; | |
2578 | ||
2579 | /* Take the hardware out of reset */ | |
bc99aa47 | 2580 | writel(0, &scic->smu_registers->soft_reset_control); |
6f231dda DW |
2581 | |
2582 | /* | |
2583 | * / @todo Provide meaningfull error code for hardware failure | |
2584 | * result = SCI_FAILURE_CONTROLLER_HARDWARE; */ | |
2585 | result = SCI_FAILURE; | |
2586 | terminate_loop = 100; | |
2587 | ||
2588 | while (terminate_loop-- && (result != SCI_SUCCESS)) { | |
2589 | /* Loop until the hardware reports success */ | |
7392d275 | 2590 | udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME); |
bc99aa47 | 2591 | status = readl(&scic->smu_registers->control_status); |
6f231dda | 2592 | |
09d7da13 DJ |
2593 | if ((status & SCU_RAM_INIT_COMPLETED) == |
2594 | SCU_RAM_INIT_COMPLETED) | |
6f231dda | 2595 | result = SCI_SUCCESS; |
6f231dda DW |
2596 | } |
2597 | } | |
2598 | ||
2599 | if (result == SCI_SUCCESS) { | |
2600 | u32 max_supported_ports; | |
2601 | u32 max_supported_devices; | |
2602 | u32 max_supported_io_requests; | |
2603 | u32 device_context_capacity; | |
2604 | ||
2605 | /* | |
2606 | * Determine what are the actaul device capacities that the | |
2607 | * hardware will support */ | |
bc99aa47 CH |
2608 | device_context_capacity = |
2609 | readl(&scic->smu_registers->device_context_capacity); | |
2610 | ||
6f231dda | 2611 | |
09d7da13 DJ |
2612 | max_supported_ports = smu_dcc_get_max_ports(device_context_capacity); |
2613 | max_supported_devices = smu_dcc_get_max_remote_node_context(device_context_capacity); | |
2614 | max_supported_io_requests = smu_dcc_get_max_task_context(device_context_capacity); | |
6f231dda | 2615 | |
09d7da13 DJ |
2616 | /* |
2617 | * Make all PEs that are unassigned match up with the | |
2618 | * logical ports | |
2619 | */ | |
6f231dda | 2620 | for (index = 0; index < max_supported_ports; index++) { |
467e855a BB |
2621 | struct scu_port_task_scheduler_group_registers __iomem |
2622 | *ptsg = &scic->scu_registers->peg0.ptsg; | |
09d7da13 | 2623 | |
bc99aa47 | 2624 | writel(index, &ptsg->protocol_engine[index]); |
6f231dda DW |
2625 | } |
2626 | ||
2627 | /* Record the smaller of the two capacity values */ | |
09d7da13 DJ |
2628 | scic->logical_port_entries = |
2629 | min(max_supported_ports, scic->logical_port_entries); | |
6f231dda | 2630 | |
09d7da13 DJ |
2631 | scic->task_context_entries = |
2632 | min(max_supported_io_requests, | |
2633 | scic->task_context_entries); | |
6f231dda | 2634 | |
09d7da13 DJ |
2635 | scic->remote_node_entries = |
2636 | min(max_supported_devices, scic->remote_node_entries); | |
6f231dda DW |
2637 | |
2638 | /* | |
2639 | * Now that we have the correct hardware reported minimum values | |
2640 | * build the MDL for the controller. Default to a performance | |
09d7da13 DJ |
2641 | * configuration. |
2642 | */ | |
2643 | scic_controller_set_mode(scic, SCI_MODE_SPEED); | |
6f231dda DW |
2644 | } |
2645 | ||
2646 | /* Initialize hardware PCI Relaxed ordering in DMA engines */ | |
2647 | if (result == SCI_SUCCESS) { | |
2648 | u32 dma_configuration; | |
2649 | ||
2650 | /* Configure the payload DMA */ | |
bc99aa47 CH |
2651 | dma_configuration = |
2652 | readl(&scic->scu_registers->sdma.pdma_configuration); | |
09d7da13 DJ |
2653 | dma_configuration |= |
2654 | SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE); | |
bc99aa47 CH |
2655 | writel(dma_configuration, |
2656 | &scic->scu_registers->sdma.pdma_configuration); | |
6f231dda DW |
2657 | |
2658 | /* Configure the control DMA */ | |
bc99aa47 CH |
2659 | dma_configuration = |
2660 | readl(&scic->scu_registers->sdma.cdma_configuration); | |
09d7da13 DJ |
2661 | dma_configuration |= |
2662 | SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE); | |
bc99aa47 CH |
2663 | writel(dma_configuration, |
2664 | &scic->scu_registers->sdma.cdma_configuration); | |
6f231dda DW |
2665 | } |
2666 | ||
2667 | /* | |
2668 | * Initialize the PHYs before the PORTs because the PHY registers | |
09d7da13 DJ |
2669 | * are accessed during the port initialization. |
2670 | */ | |
6f231dda DW |
2671 | if (result == SCI_SUCCESS) { |
2672 | /* Initialize the phys */ | |
2673 | for (index = 0; | |
2674 | (result == SCI_SUCCESS) && (index < SCI_MAX_PHYS); | |
2675 | index++) { | |
2676 | result = scic_sds_phy_initialize( | |
4b33981a | 2677 | &ihost->phys[index].sci, |
09d7da13 DJ |
2678 | &scic->scu_registers->peg0.pe[index].tl, |
2679 | &scic->scu_registers->peg0.pe[index].ll); | |
6f231dda DW |
2680 | } |
2681 | } | |
2682 | ||
2683 | if (result == SCI_SUCCESS) { | |
2684 | /* Initialize the logical ports */ | |
2685 | for (index = 0; | |
09d7da13 DJ |
2686 | (index < scic->logical_port_entries) && |
2687 | (result == SCI_SUCCESS); | |
6f231dda DW |
2688 | index++) { |
2689 | result = scic_sds_port_initialize( | |
e531381e | 2690 | &ihost->ports[index].sci, |
09d7da13 DJ |
2691 | &scic->scu_registers->peg0.ptsg.port[index], |
2692 | &scic->scu_registers->peg0.ptsg.protocol_engine, | |
2693 | &scic->scu_registers->peg0.viit[index]); | |
6f231dda DW |
2694 | } |
2695 | } | |
2696 | ||
09d7da13 | 2697 | if (result == SCI_SUCCESS) |
6f231dda | 2698 | result = scic_sds_port_configuration_agent_initialize( |
09d7da13 DJ |
2699 | scic, |
2700 | &scic->port_agent); | |
6f231dda DW |
2701 | |
2702 | /* Advance the controller state machine */ | |
09d7da13 | 2703 | if (result == SCI_SUCCESS) |
068b2c03 | 2704 | state = SCI_BASE_CONTROLLER_STATE_INITIALIZED; |
09d7da13 | 2705 | else |
068b2c03 DW |
2706 | state = SCI_BASE_CONTROLLER_STATE_FAILED; |
2707 | sci_base_state_machine_change_state(sm, state); | |
6f231dda DW |
2708 | |
2709 | return result; | |
2710 | } | |
2711 | ||
c629582d | 2712 | enum sci_status scic_controller_start(struct scic_sds_controller *scic, |
e531381e | 2713 | u32 timeout) |
6f231dda | 2714 | { |
e531381e | 2715 | struct isci_host *ihost = scic_to_ihost(scic); |
6f231dda | 2716 | enum sci_status result; |
c629582d CH |
2717 | u16 index; |
2718 | ||
2719 | if (scic->state_machine.current_state_id != | |
2720 | SCI_BASE_CONTROLLER_STATE_INITIALIZED) { | |
2721 | dev_warn(scic_to_dev(scic), | |
2722 | "SCIC Controller start operation requested in " | |
2723 | "invalid state\n"); | |
2724 | return SCI_FAILURE_INVALID_STATE; | |
2725 | } | |
6f231dda | 2726 | |
bc5c9674 CH |
2727 | /* Build the TCi free pool */ |
2728 | sci_pool_initialize(scic->tci_pool); | |
2729 | for (index = 0; index < scic->task_context_entries; index++) | |
2730 | sci_pool_put(scic->tci_pool, index); | |
6f231dda | 2731 | |
bc5c9674 CH |
2732 | /* Build the RNi free pool */ |
2733 | scic_sds_remote_node_table_initialize( | |
2734 | &scic->available_remote_nodes, | |
2735 | scic->remote_node_entries); | |
6f231dda | 2736 | |
bc5c9674 CH |
2737 | /* |
2738 | * Before anything else lets make sure we will not be | |
2739 | * interrupted by the hardware. | |
2740 | */ | |
2741 | scic_controller_disable_interrupts(scic); | |
6f231dda | 2742 | |
bc5c9674 CH |
2743 | /* Enable the port task scheduler */ |
2744 | scic_sds_controller_enable_port_task_scheduler(scic); | |
6f231dda | 2745 | |
bc5c9674 CH |
2746 | /* Assign all the task entries to scic physical function */ |
2747 | scic_sds_controller_assign_task_entries(scic); | |
6f231dda | 2748 | |
d3757c3a | 2749 | /* Now initialize the completion queue */ |
bc5c9674 | 2750 | scic_sds_controller_initialize_completion_queue(scic); |
6f231dda | 2751 | |
bc5c9674 CH |
2752 | /* Initialize the unsolicited frame queue for use */ |
2753 | scic_sds_controller_initialize_unsolicited_frame_queue(scic); | |
6f231dda | 2754 | |
a8d4b9fe | 2755 | /* Start all of the ports on this controller */ |
bc5c9674 | 2756 | for (index = 0; index < scic->logical_port_entries; index++) { |
e531381e | 2757 | struct scic_sds_port *sci_port = &ihost->ports[index].sci; |
a8d4b9fe | 2758 | |
e531381e | 2759 | result = sci_port->state_handlers->start_handler(sci_port); |
bc5c9674 CH |
2760 | if (result) |
2761 | return result; | |
a8d4b9fe TC |
2762 | } |
2763 | ||
bc5c9674 | 2764 | scic_sds_controller_start_next_phy(scic); |
6f231dda | 2765 | |
bc5c9674 | 2766 | isci_timer_start(scic->timeout_timer, timeout); |
6f231dda | 2767 | |
bc5c9674 CH |
2768 | sci_base_state_machine_change_state(&scic->state_machine, |
2769 | SCI_BASE_CONTROLLER_STATE_STARTING); | |
6f231dda | 2770 | |
bc5c9674 | 2771 | return SCI_SUCCESS; |
6f231dda DW |
2772 | } |
2773 | ||
6f231dda DW |
2774 | /** |
2775 | * | |
9a0fff7b | 2776 | * @object: This is the object which is cast to a struct scic_sds_controller |
6f231dda DW |
2777 | * object. |
2778 | * | |
2779 | * This method implements the actions taken by the struct scic_sds_controller on entry | |
2780 | * to the SCI_BASE_CONTROLLER_STATE_INITIAL. - Set the state handlers to the | |
d3757c3a | 2781 | * controllers initial state. none This function should initialize the |
6f231dda DW |
2782 | * controller object. |
2783 | */ | |
9a0fff7b | 2784 | static void scic_sds_controller_initial_state_enter(void *object) |
6f231dda | 2785 | { |
d3757c3a | 2786 | struct scic_sds_controller *scic = object; |
6f231dda | 2787 | |
e2023b87 | 2788 | sci_base_state_machine_change_state(&scic->state_machine, |
ca841f0e | 2789 | SCI_BASE_CONTROLLER_STATE_RESET); |
6f231dda DW |
2790 | } |
2791 | ||
2792 | /** | |
2793 | * | |
9a0fff7b | 2794 | * @object: This is the object which is cast to a struct scic_sds_controller |
6f231dda DW |
2795 | * object. |
2796 | * | |
2797 | * This method implements the actions taken by the struct scic_sds_controller on exit | |
2798 | * from the SCI_BASE_CONTROLLER_STATE_STARTING. - This function stops the | |
2799 | * controller starting timeout timer. none | |
2800 | */ | |
9a0fff7b | 2801 | static inline void scic_sds_controller_starting_state_exit(void *object) |
6f231dda | 2802 | { |
d3757c3a | 2803 | struct scic_sds_controller *scic = object; |
6f231dda | 2804 | |
09d7da13 | 2805 | isci_timer_stop(scic->timeout_timer); |
6f231dda DW |
2806 | } |
2807 | ||
2808 | /** | |
2809 | * | |
9a0fff7b | 2810 | * @object: This is the object which is cast to a struct scic_sds_controller |
6f231dda DW |
2811 | * object. |
2812 | * | |
2813 | * This method implements the actions taken by the struct scic_sds_controller on entry | |
2814 | * to the SCI_BASE_CONTROLLER_STATE_READY. - Set the state handlers to the | |
2815 | * controllers ready state. none | |
2816 | */ | |
9a0fff7b | 2817 | static void scic_sds_controller_ready_state_enter(void *object) |
6f231dda | 2818 | { |
d3757c3a | 2819 | struct scic_sds_controller *scic = object; |
6f231dda DW |
2820 | |
2821 | /* set the default interrupt coalescence number and timeout value. */ | |
2822 | scic_controller_set_interrupt_coalescence( | |
e2023b87 | 2823 | scic, 0x10, 250); |
6f231dda DW |
2824 | } |
2825 | ||
2826 | /** | |
2827 | * | |
9a0fff7b | 2828 | * @object: This is the object which is cast to a struct scic_sds_controller |
6f231dda DW |
2829 | * object. |
2830 | * | |
2831 | * This method implements the actions taken by the struct scic_sds_controller on exit | |
2832 | * from the SCI_BASE_CONTROLLER_STATE_READY. - This function does nothing. none | |
2833 | */ | |
9a0fff7b | 2834 | static void scic_sds_controller_ready_state_exit(void *object) |
6f231dda | 2835 | { |
d3757c3a | 2836 | struct scic_sds_controller *scic = object; |
6f231dda DW |
2837 | |
2838 | /* disable interrupt coalescence. */ | |
e2023b87 | 2839 | scic_controller_set_interrupt_coalescence(scic, 0, 0); |
6f231dda DW |
2840 | } |
2841 | ||
2842 | /** | |
2843 | * | |
9a0fff7b | 2844 | * @object: This is the object which is cast to a struct scic_sds_controller |
6f231dda DW |
2845 | * object. |
2846 | * | |
2847 | * This method implements the actions taken by the struct scic_sds_controller on entry | |
2848 | * to the SCI_BASE_CONTROLLER_STATE_READY. - Set the state handlers to the | |
2849 | * controllers ready state. - Stop the phys on this controller - Stop the ports | |
2850 | * on this controller - Stop all of the remote devices on this controller none | |
2851 | */ | |
9a0fff7b | 2852 | static void scic_sds_controller_stopping_state_enter(void *object) |
6f231dda | 2853 | { |
d3757c3a | 2854 | struct scic_sds_controller *scic = object; |
6f231dda DW |
2855 | |
2856 | /* Stop all of the components for this controller */ | |
e2023b87 DJ |
2857 | scic_sds_controller_stop_phys(scic); |
2858 | scic_sds_controller_stop_ports(scic); | |
2859 | scic_sds_controller_stop_devices(scic); | |
6f231dda DW |
2860 | } |
2861 | ||
2862 | /** | |
2863 | * | |
9a0fff7b | 2864 | * @object: This is the object which is cast to a struct |
09d7da13 | 2865 | * scic_sds_controller object. |
6f231dda | 2866 | * |
d3757c3a | 2867 | * This function implements the actions taken by the struct scic_sds_controller |
09d7da13 DJ |
2868 | * on exit from the SCI_BASE_CONTROLLER_STATE_STOPPING. - |
2869 | * This function stops the controller stopping timeout timer. | |
6f231dda | 2870 | */ |
9a0fff7b | 2871 | static inline void scic_sds_controller_stopping_state_exit(void *object) |
6f231dda | 2872 | { |
d3757c3a | 2873 | struct scic_sds_controller *scic = object; |
6f231dda | 2874 | |
09d7da13 | 2875 | isci_timer_stop(scic->timeout_timer); |
6f231dda DW |
2876 | } |
2877 | ||
9a0fff7b | 2878 | static void scic_sds_controller_resetting_state_enter(void *object) |
6f231dda | 2879 | { |
d3757c3a | 2880 | struct scic_sds_controller *scic = object; |
6f231dda | 2881 | |
068b2c03 | 2882 | scic_sds_controller_reset_hardware(scic); |
ca841f0e | 2883 | sci_base_state_machine_change_state(&scic->state_machine, |
068b2c03 | 2884 | SCI_BASE_CONTROLLER_STATE_RESET); |
6f231dda DW |
2885 | } |
2886 | ||
35173d57 | 2887 | static const struct sci_base_state scic_sds_controller_state_table[] = { |
6f231dda DW |
2888 | [SCI_BASE_CONTROLLER_STATE_INITIAL] = { |
2889 | .enter_state = scic_sds_controller_initial_state_enter, | |
2890 | }, | |
2891 | [SCI_BASE_CONTROLLER_STATE_RESET] = {}, | |
2892 | [SCI_BASE_CONTROLLER_STATE_INITIALIZING] = {}, | |
2893 | [SCI_BASE_CONTROLLER_STATE_INITIALIZED] = {}, | |
2894 | [SCI_BASE_CONTROLLER_STATE_STARTING] = { | |
2895 | .exit_state = scic_sds_controller_starting_state_exit, | |
2896 | }, | |
2897 | [SCI_BASE_CONTROLLER_STATE_READY] = { | |
2898 | .enter_state = scic_sds_controller_ready_state_enter, | |
2899 | .exit_state = scic_sds_controller_ready_state_exit, | |
2900 | }, | |
2901 | [SCI_BASE_CONTROLLER_STATE_RESETTING] = { | |
2902 | .enter_state = scic_sds_controller_resetting_state_enter, | |
2903 | }, | |
2904 | [SCI_BASE_CONTROLLER_STATE_STOPPING] = { | |
2905 | .enter_state = scic_sds_controller_stopping_state_enter, | |
2906 | .exit_state = scic_sds_controller_stopping_state_exit, | |
2907 | }, | |
2908 | [SCI_BASE_CONTROLLER_STATE_STOPPED] = {}, | |
2909 | [SCI_BASE_CONTROLLER_STATE_FAILED] = {} | |
2910 | }; | |
35173d57 DW |
2911 | |
2912 | /** | |
2913 | * scic_controller_construct() - This method will attempt to construct a | |
2914 | * controller object utilizing the supplied parameter information. | |
2915 | * @c: This parameter specifies the controller to be constructed. | |
2916 | * @scu_base: mapped base address of the scu registers | |
2917 | * @smu_base: mapped base address of the smu registers | |
2918 | * | |
2919 | * Indicate if the controller was successfully constructed or if it failed in | |
2920 | * some way. SCI_SUCCESS This value is returned if the controller was | |
2921 | * successfully constructed. SCI_WARNING_TIMER_CONFLICT This value is returned | |
2922 | * if the interrupt coalescence timer may cause SAS compliance issues for SMP | |
2923 | * Target mode response processing. SCI_FAILURE_UNSUPPORTED_CONTROLLER_TYPE | |
2924 | * This value is returned if the controller does not support the supplied type. | |
2925 | * SCI_FAILURE_UNSUPPORTED_INIT_DATA_VERSION This value is returned if the | |
2926 | * controller does not support the supplied initialization data version. | |
2927 | */ | |
2928 | enum sci_status scic_controller_construct(struct scic_sds_controller *scic, | |
2929 | void __iomem *scu_base, | |
2930 | void __iomem *smu_base) | |
2931 | { | |
4b33981a | 2932 | struct isci_host *ihost = scic_to_ihost(scic); |
35173d57 DW |
2933 | u8 i; |
2934 | ||
ca841f0e | 2935 | sci_base_state_machine_construct(&scic->state_machine, |
d3757c3a | 2936 | scic, scic_sds_controller_state_table, |
ca841f0e CH |
2937 | SCI_BASE_CONTROLLER_STATE_INITIAL); |
2938 | ||
ca841f0e | 2939 | sci_base_state_machine_start(&scic->state_machine); |
35173d57 DW |
2940 | |
2941 | scic->scu_registers = scu_base; | |
2942 | scic->smu_registers = smu_base; | |
2943 | ||
2944 | scic_sds_port_configuration_agent_construct(&scic->port_agent); | |
2945 | ||
2946 | /* Construct the ports for this controller */ | |
2947 | for (i = 0; i < SCI_MAX_PORTS; i++) | |
e531381e DW |
2948 | scic_sds_port_construct(&ihost->ports[i].sci, i, scic); |
2949 | scic_sds_port_construct(&ihost->ports[i].sci, SCIC_SDS_DUMMY_PORT, scic); | |
35173d57 DW |
2950 | |
2951 | /* Construct the phys for this controller */ | |
2952 | for (i = 0; i < SCI_MAX_PHYS; i++) { | |
2953 | /* Add all the PHYs to the dummy port */ | |
4b33981a | 2954 | scic_sds_phy_construct(&ihost->phys[i].sci, |
e531381e | 2955 | &ihost->ports[SCI_MAX_PORTS].sci, i); |
35173d57 DW |
2956 | } |
2957 | ||
2958 | scic->invalid_phy_mask = 0; | |
2959 | ||
2960 | /* Set the default maximum values */ | |
2961 | scic->completion_event_entries = SCU_EVENT_COUNT; | |
2962 | scic->completion_queue_entries = SCU_COMPLETION_QUEUE_COUNT; | |
2963 | scic->remote_node_entries = SCI_MAX_REMOTE_DEVICES; | |
2964 | scic->logical_port_entries = SCI_MAX_PORTS; | |
2965 | scic->task_context_entries = SCU_IO_REQUEST_COUNT; | |
2966 | scic->uf_control.buffers.count = SCU_UNSOLICITED_FRAME_COUNT; | |
2967 | scic->uf_control.address_table.count = SCU_UNSOLICITED_FRAME_COUNT; | |
2968 | ||
2969 | /* Initialize the User and OEM parameters to default values. */ | |
2970 | scic_sds_controller_set_default_config_parameters(scic); | |
2971 | ||
2972 | return scic_controller_reset(scic); | |
2973 | } |