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[deliverable/linux.git] / drivers / scsi / libata-core.c
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1da177e4 1/*
af36d7f0
JG		 2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT		 33 */
34
35#include <linux/config.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/list.h>
41#include <linux/mm.h>
42#include <linux/highmem.h>
43#include <linux/spinlock.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/timer.h>
47#include <linux/interrupt.h>
48#include <linux/completion.h>
49#include <linux/suspend.h>
50#include <linux/workqueue.h>
67846b30 51#include <linux/jiffies.h>
378f058c 52#include <linux/scatterlist.h>
1da177e4 53#include <scsi/scsi.h>
1da177e4 54#include "scsi_priv.h"
193515d5 55#include <scsi/scsi_cmnd.h>
1da177e4
LT		 56#include <scsi/scsi_host.h>
57#include <linux/libata.h>
58#include <asm/io.h>
59#include <asm/semaphore.h>
60#include <asm/byteorder.h>
61
62#include "libata.h"
63
59a10b17 64static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev);
8bf62ece 65static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev);
1da177e4
LT		 66static void ata_set_mode(struct ata_port *ap);
67static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev);
057ace5e 68static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift);
1da177e4 69static int fgb(u32 bitmap);
057ace5e 70static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 71 u8 *xfer_mode_out,
72 unsigned int *xfer_shift_out);
e33b9dfa 73static void ata_pio_error(struct ata_port *ap);
1da177e4
LT		 74
75static unsigned int ata_unique_id = 1;
76static struct workqueue_struct *ata_wq;
77
1623c81e
JG		 78int atapi_enabled = 0;
79module_param(atapi_enabled, int, 0444);
80MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
81
1da177e4
LT		 82MODULE_AUTHOR("Jeff Garzik");
83MODULE_DESCRIPTION("Library module for ATA devices");
84MODULE_LICENSE("GPL");
85MODULE_VERSION(DRV_VERSION);
86
0baab86b 87
1da177e4
LT		 88/**
89 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
90 * @tf: Taskfile to convert
91 * @fis: Buffer into which data will output
92 * @pmp: Port multiplier port
93 *
94 * Converts a standard ATA taskfile to a Serial ATA
95 * FIS structure (Register - Host to Device).
96 *
97 * LOCKING:
98 * Inherited from caller.
99 */
100
057ace5e 101void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT		 102{
103 fis[0] = 0x27; /* Register - Host to Device FIS */
104 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
105 bit 7 indicates Command FIS */
106 fis[2] = tf->command;
107 fis[3] = tf->feature;
108
109 fis[4] = tf->lbal;
110 fis[5] = tf->lbam;
111 fis[6] = tf->lbah;
112 fis[7] = tf->device;
113
114 fis[8] = tf->hob_lbal;
115 fis[9] = tf->hob_lbam;
116 fis[10] = tf->hob_lbah;
117 fis[11] = tf->hob_feature;
118
119 fis[12] = tf->nsect;
120 fis[13] = tf->hob_nsect;
121 fis[14] = 0;
122 fis[15] = tf->ctl;
123
124 fis[16] = 0;
125 fis[17] = 0;
126 fis[18] = 0;
127 fis[19] = 0;
128}
129
130/**
131 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
132 * @fis: Buffer from which data will be input
133 * @tf: Taskfile to output
134 *
e12a1be6 135 * Converts a serial ATA FIS structure to a standard ATA taskfile.
1da177e4
LT		 136 *
137 * LOCKING:
138 * Inherited from caller.
139 */
140
057ace5e 141void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT		 142{
143 tf->command = fis[2]; /* status */
144 tf->feature = fis[3]; /* error */
145
146 tf->lbal = fis[4];
147 tf->lbam = fis[5];
148 tf->lbah = fis[6];
149 tf->device = fis[7];
150
151 tf->hob_lbal = fis[8];
152 tf->hob_lbam = fis[9];
153 tf->hob_lbah = fis[10];
154
155 tf->nsect = fis[12];
156 tf->hob_nsect = fis[13];
157}
158
8cbd6df1
AL		 159static const u8 ata_rw_cmds[] = {
160 /* pio multi */
161 ATA_CMD_READ_MULTI,
162 ATA_CMD_WRITE_MULTI,
163 ATA_CMD_READ_MULTI_EXT,
164 ATA_CMD_WRITE_MULTI_EXT,
9a3dccc4
TH		 165 0,
166 0,
167 0,
168 ATA_CMD_WRITE_MULTI_FUA_EXT,
8cbd6df1
AL		 169 /* pio */
170 ATA_CMD_PIO_READ,
171 ATA_CMD_PIO_WRITE,
172 ATA_CMD_PIO_READ_EXT,
173 ATA_CMD_PIO_WRITE_EXT,
9a3dccc4
TH		 174 0,
175 0,
176 0,
177 0,
8cbd6df1
AL		 178 /* dma */
179 ATA_CMD_READ,
180 ATA_CMD_WRITE,
181 ATA_CMD_READ_EXT,
9a3dccc4
TH		 182 ATA_CMD_WRITE_EXT,
183 0,
184 0,
185 0,
186 ATA_CMD_WRITE_FUA_EXT
8cbd6df1 187};
1da177e4
LT		 188
189/**
8cbd6df1
AL		 190 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
191 * @qc: command to examine and configure
1da177e4 192 *
8cbd6df1
AL		 193 * Examine the device configuration and tf->flags to calculate
194 * the proper read/write commands and protocol to use.
1da177e4
LT		 195 *
196 * LOCKING:
197 * caller.
198 */
9a3dccc4 199int ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 200{
8cbd6df1
AL		 201 struct ata_taskfile *tf = &qc->tf;
202 struct ata_device *dev = qc->dev;
9a3dccc4 203 u8 cmd;
1da177e4 204
9a3dccc4 205 int index, fua, lba48, write;
8cbd6df1 206
9a3dccc4 207 fua = (tf->flags & ATA_TFLAG_FUA) ? 4 : 0;
8cbd6df1
AL		 208 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
209 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 210
8cbd6df1
AL		 211 if (dev->flags & ATA_DFLAG_PIO) {
212 tf->protocol = ATA_PROT_PIO;
9a3dccc4 213 index = dev->multi_count ? 0 : 8;
8d238e01
AC		 214 } else if (lba48 && (qc->ap->flags & ATA_FLAG_PIO_LBA48)) {
215 /* Unable to use DMA due to host limitation */
216 tf->protocol = ATA_PROT_PIO;
aef9d533 217 index = dev->multi_count ? 0 : 8;
8cbd6df1
AL		 218 } else {
219 tf->protocol = ATA_PROT_DMA;
9a3dccc4 220 index = 16;
8cbd6df1 221 }
1da177e4 222
9a3dccc4
TH		 223 cmd = ata_rw_cmds[index + fua + lba48 + write];
224 if (cmd) {
225 tf->command = cmd;
226 return 0;
227 }
228 return -1;
1da177e4
LT		 229}
230
98ac62de 231static const char * const xfer_mode_str[] = {
1da177e4
LT		 232 "UDMA/16",
233 "UDMA/25",
234 "UDMA/33",
235 "UDMA/44",
236 "UDMA/66",
237 "UDMA/100",
238 "UDMA/133",
239 "UDMA7",
240 "MWDMA0",
241 "MWDMA1",
242 "MWDMA2",
243 "PIO0",
244 "PIO1",
245 "PIO2",
246 "PIO3",
247 "PIO4",
248};
249
250/**
251 * ata_udma_string - convert UDMA bit offset to string
252 * @mask: mask of bits supported; only highest bit counts.
253 *
254 * Determine string which represents the highest speed
255 * (highest bit in @udma_mask).
256 *
257 * LOCKING:
258 * None.
259 *
260 * RETURNS:
261 * Constant C string representing highest speed listed in
262 * @udma_mask, or the constant C string "<n/a>".
263 */
264
265static const char *ata_mode_string(unsigned int mask)
266{
267 int i;
268
269 for (i = 7; i >= 0; i--)
270 if (mask & (1 << i))
271 goto out;
272 for (i = ATA_SHIFT_MWDMA + 2; i >= ATA_SHIFT_MWDMA; i--)
273 if (mask & (1 << i))
274 goto out;
275 for (i = ATA_SHIFT_PIO + 4; i >= ATA_SHIFT_PIO; i--)
276 if (mask & (1 << i))
277 goto out;
278
279 return "<n/a>";
280
281out:
282 return xfer_mode_str[i];
283}
284
285/**
286 * ata_pio_devchk - PATA device presence detection
287 * @ap: ATA channel to examine
288 * @device: Device to examine (starting at zero)
289 *
290 * This technique was originally described in
291 * Hale Landis's ATADRVR (www.ata-atapi.com), and
292 * later found its way into the ATA/ATAPI spec.
293 *
294 * Write a pattern to the ATA shadow registers,
295 * and if a device is present, it will respond by
296 * correctly storing and echoing back the
297 * ATA shadow register contents.
298 *
299 * LOCKING:
300 * caller.
301 */
302
303static unsigned int ata_pio_devchk(struct ata_port *ap,
304 unsigned int device)
305{
306 struct ata_ioports *ioaddr = &ap->ioaddr;
307 u8 nsect, lbal;
308
309 ap->ops->dev_select(ap, device);
310
311 outb(0x55, ioaddr->nsect_addr);
312 outb(0xaa, ioaddr->lbal_addr);
313
314 outb(0xaa, ioaddr->nsect_addr);
315 outb(0x55, ioaddr->lbal_addr);
316
317 outb(0x55, ioaddr->nsect_addr);
318 outb(0xaa, ioaddr->lbal_addr);
319
320 nsect = inb(ioaddr->nsect_addr);
321 lbal = inb(ioaddr->lbal_addr);
322
323 if ((nsect == 0x55) && (lbal == 0xaa))
324 return 1; /* we found a device */
325
326 return 0; /* nothing found */
327}
328
329/**
330 * ata_mmio_devchk - PATA device presence detection
331 * @ap: ATA channel to examine
332 * @device: Device to examine (starting at zero)
333 *
334 * This technique was originally described in
335 * Hale Landis's ATADRVR (www.ata-atapi.com), and
336 * later found its way into the ATA/ATAPI spec.
337 *
338 * Write a pattern to the ATA shadow registers,
339 * and if a device is present, it will respond by
340 * correctly storing and echoing back the
341 * ATA shadow register contents.
342 *
343 * LOCKING:
344 * caller.
345 */
346
347static unsigned int ata_mmio_devchk(struct ata_port *ap,
348 unsigned int device)
349{
350 struct ata_ioports *ioaddr = &ap->ioaddr;
351 u8 nsect, lbal;
352
353 ap->ops->dev_select(ap, device);
354
355 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
356 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
357
358 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
359 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
360
361 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
362 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
363
364 nsect = readb((void __iomem *) ioaddr->nsect_addr);
365 lbal = readb((void __iomem *) ioaddr->lbal_addr);
366
367 if ((nsect == 0x55) && (lbal == 0xaa))
368 return 1; /* we found a device */
369
370 return 0; /* nothing found */
371}
372
373/**
374 * ata_devchk - PATA device presence detection
375 * @ap: ATA channel to examine
376 * @device: Device to examine (starting at zero)
377 *
378 * Dispatch ATA device presence detection, depending
379 * on whether we are using PIO or MMIO to talk to the
380 * ATA shadow registers.
381 *
382 * LOCKING:
383 * caller.
384 */
385
386static unsigned int ata_devchk(struct ata_port *ap,
387 unsigned int device)
388{
389 if (ap->flags & ATA_FLAG_MMIO)
390 return ata_mmio_devchk(ap, device);
391 return ata_pio_devchk(ap, device);
392}
393
394/**
395 * ata_dev_classify - determine device type based on ATA-spec signature
396 * @tf: ATA taskfile register set for device to be identified
397 *
398 * Determine from taskfile register contents whether a device is
399 * ATA or ATAPI, as per "Signature and persistence" section
400 * of ATA/PI spec (volume 1, sect 5.14).
401 *
402 * LOCKING:
403 * None.
404 *
405 * RETURNS:
406 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
407 * the event of failure.
408 */
409
057ace5e 410unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT		 411{
412 /* Apple's open source Darwin code hints that some devices only
413 * put a proper signature into the LBA mid/high registers,
414 * So, we only check those. It's sufficient for uniqueness.
415 */
416
417 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
418 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
419 DPRINTK("found ATA device by sig\n");
420 return ATA_DEV_ATA;
421 }
422
423 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
424 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
425 DPRINTK("found ATAPI device by sig\n");
426 return ATA_DEV_ATAPI;
427 }
428
429 DPRINTK("unknown device\n");
430 return ATA_DEV_UNKNOWN;
431}
432
433/**
434 * ata_dev_try_classify - Parse returned ATA device signature
435 * @ap: ATA channel to examine
436 * @device: Device to examine (starting at zero)
b4dc7623 437 * @r_err: Value of error register on completion
1da177e4
LT		 438 *
439 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
440 * an ATA/ATAPI-defined set of values is placed in the ATA
441 * shadow registers, indicating the results of device detection
442 * and diagnostics.
443 *
444 * Select the ATA device, and read the values from the ATA shadow
445 * registers. Then parse according to the Error register value,
446 * and the spec-defined values examined by ata_dev_classify().
447 *
448 * LOCKING:
449 * caller.
b4dc7623
TH		 450 *
451 * RETURNS:
452 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1da177e4
LT		 453 */
454
b4dc7623
TH		 455static unsigned int
456ata_dev_try_classify(struct ata_port *ap, unsigned int device, u8 *r_err)
1da177e4 457{
1da177e4
LT		 458 struct ata_taskfile tf;
459 unsigned int class;
460 u8 err;
461
462 ap->ops->dev_select(ap, device);
463
464 memset(&tf, 0, sizeof(tf));
465
1da177e4 466 ap->ops->tf_read(ap, &tf);
0169e284 467 err = tf.feature;
b4dc7623
TH		 468 if (r_err)
469 *r_err = err;
1da177e4
LT		 470
471 /* see if device passed diags */
472 if (err == 1)
473 /* do nothing */ ;
474 else if ((device == 0) && (err == 0x81))
475 /* do nothing */ ;
476 else
b4dc7623 477 return ATA_DEV_NONE;
1da177e4 478
b4dc7623 479 /* determine if device is ATA or ATAPI */
1da177e4 480 class = ata_dev_classify(&tf);
b4dc7623 481
1da177e4 482 if (class == ATA_DEV_UNKNOWN)
b4dc7623 483 return ATA_DEV_NONE;
1da177e4 484 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
b4dc7623
TH		 485 return ATA_DEV_NONE;
486 return class;
1da177e4
LT		 487}
488
489/**
490 * ata_dev_id_string - Convert IDENTIFY DEVICE page into string
491 * @id: IDENTIFY DEVICE results we will examine
492 * @s: string into which data is output
493 * @ofs: offset into identify device page
494 * @len: length of string to return. must be an even number.
495 *
496 * The strings in the IDENTIFY DEVICE page are broken up into
497 * 16-bit chunks. Run through the string, and output each
498 * 8-bit chunk linearly, regardless of platform.
499 *
500 * LOCKING:
501 * caller.
502 */
503
057ace5e 504void ata_dev_id_string(const u16 *id, unsigned char *s,
1da177e4
LT		 505 unsigned int ofs, unsigned int len)
506{
507 unsigned int c;
508
509 while (len > 0) {
510 c = id[ofs] >> 8;
511 *s = c;
512 s++;
513
514 c = id[ofs] & 0xff;
515 *s = c;
516 s++;
517
518 ofs++;
519 len -= 2;
520 }
521}
522
0baab86b
EF		 523
524/**
525 * ata_noop_dev_select - Select device 0/1 on ATA bus
526 * @ap: ATA channel to manipulate
527 * @device: ATA device (numbered from zero) to select
528 *
529 * This function performs no actual function.
530 *
531 * May be used as the dev_select() entry in ata_port_operations.
532 *
533 * LOCKING:
534 * caller.
535 */
1da177e4
LT		 536void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
537{
538}
539
0baab86b 540
1da177e4
LT		 541/**
542 * ata_std_dev_select - Select device 0/1 on ATA bus
543 * @ap: ATA channel to manipulate
544 * @device: ATA device (numbered from zero) to select
545 *
546 * Use the method defined in the ATA specification to
547 * make either device 0, or device 1, active on the
0baab86b
EF		 548 * ATA channel. Works with both PIO and MMIO.
549 *
550 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT		 551 *
552 * LOCKING:
553 * caller.
554 */
555
556void ata_std_dev_select (struct ata_port *ap, unsigned int device)
557{
558 u8 tmp;
559
560 if (device == 0)
561 tmp = ATA_DEVICE_OBS;
562 else
563 tmp = ATA_DEVICE_OBS | ATA_DEV1;
564
565 if (ap->flags & ATA_FLAG_MMIO) {
566 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
567 } else {
568 outb(tmp, ap->ioaddr.device_addr);
569 }
570 ata_pause(ap); /* needed; also flushes, for mmio */
571}
572
573/**
574 * ata_dev_select - Select device 0/1 on ATA bus
575 * @ap: ATA channel to manipulate
576 * @device: ATA device (numbered from zero) to select
577 * @wait: non-zero to wait for Status register BSY bit to clear
578 * @can_sleep: non-zero if context allows sleeping
579 *
580 * Use the method defined in the ATA specification to
581 * make either device 0, or device 1, active on the
582 * ATA channel.
583 *
584 * This is a high-level version of ata_std_dev_select(),
585 * which additionally provides the services of inserting
586 * the proper pauses and status polling, where needed.
587 *
588 * LOCKING:
589 * caller.
590 */
591
592void ata_dev_select(struct ata_port *ap, unsigned int device,
593 unsigned int wait, unsigned int can_sleep)
594{
595 VPRINTK("ENTER, ata%u: device %u, wait %u\n",
596 ap->id, device, wait);
597
598 if (wait)
599 ata_wait_idle(ap);
600
601 ap->ops->dev_select(ap, device);
602
603 if (wait) {
604 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
605 msleep(150);
606 ata_wait_idle(ap);
607 }
608}
609
610/**
611 * ata_dump_id - IDENTIFY DEVICE info debugging output
612 * @dev: Device whose IDENTIFY DEVICE page we will dump
613 *
614 * Dump selected 16-bit words from a detected device's
615 * IDENTIFY PAGE page.
616 *
617 * LOCKING:
618 * caller.
619 */
620
057ace5e 621static inline void ata_dump_id(const struct ata_device *dev)
1da177e4
LT		 622{
623 DPRINTK("49==0x%04x "
624 "53==0x%04x "
625 "63==0x%04x "
626 "64==0x%04x "
627 "75==0x%04x \n",
628 dev->id[49],
629 dev->id[53],
630 dev->id[63],
631 dev->id[64],
632 dev->id[75]);
633 DPRINTK("80==0x%04x "
634 "81==0x%04x "
635 "82==0x%04x "
636 "83==0x%04x "
637 "84==0x%04x \n",
638 dev->id[80],
639 dev->id[81],
640 dev->id[82],
641 dev->id[83],
642 dev->id[84]);
643 DPRINTK("88==0x%04x "
644 "93==0x%04x\n",
645 dev->id[88],
646 dev->id[93]);
647}
648
11e29e21
AC		 649/*
650 * Compute the PIO modes available for this device. This is not as
651 * trivial as it seems if we must consider early devices correctly.
652 *
653 * FIXME: pre IDE drive timing (do we care ?).
654 */
655
057ace5e 656static unsigned int ata_pio_modes(const struct ata_device *adev)
11e29e21
AC		 657{
658 u16 modes;
659
ffa29456
AC		 660 /* Usual case. Word 53 indicates word 64 is valid */
661 if (adev->id[ATA_ID_FIELD_VALID] & (1 << 1)) {
11e29e21
AC		 662 modes = adev->id[ATA_ID_PIO_MODES] & 0x03;
663 modes <<= 3;
664 modes |= 0x7;
665 return modes;
666 }
667
ffa29456
AC		 668 /* If word 64 isn't valid then Word 51 high byte holds the PIO timing
669 number for the maximum. Turn it into a mask and return it */
670 modes = (2 << ((adev->id[ATA_ID_OLD_PIO_MODES] >> 8) & 0xFF)) - 1 ;
11e29e21 671 return modes;
ffa29456
AC		 672 /* But wait.. there's more. Design your standards by committee and
673 you too can get a free iordy field to process. However its the
674 speeds not the modes that are supported... Note drivers using the
675 timing API will get this right anyway */
11e29e21
AC		 676}
677
95064379
TH		 678static inline void
679ata_queue_pio_task(struct ata_port *ap)
680{
c18d06f8
TH		 681 if (!(ap->flags & ATA_FLAG_FLUSH_PIO_TASK))
682 queue_work(ata_wq, &ap->pio_task);
95064379
TH		 683}
684
685static inline void
686ata_queue_delayed_pio_task(struct ata_port *ap, unsigned long delay)
687{
c18d06f8
TH		 688 if (!(ap->flags & ATA_FLAG_FLUSH_PIO_TASK))
689 queue_delayed_work(ata_wq, &ap->pio_task, delay);
690}
691
692/**
41232d3e 693 * ata_flush_pio_tasks - Flush pio_task
c18d06f8
TH		 694 * @ap: the target ata_port
695 *
41232d3e 696 * After this function completes, pio_task is
c18d06f8
TH		 697 * guranteed not to be running or scheduled.
698 *
699 * LOCKING:
700 * Kernel thread context (may sleep)
701 */
702
703static void ata_flush_pio_tasks(struct ata_port *ap)
704{
705 int tmp = 0;
706 unsigned long flags;
707
708 DPRINTK("ENTER\n");
709
710 spin_lock_irqsave(&ap->host_set->lock, flags);
711 ap->flags |= ATA_FLAG_FLUSH_PIO_TASK;
712 spin_unlock_irqrestore(&ap->host_set->lock, flags);
713
714 DPRINTK("flush #1\n");
715 flush_workqueue(ata_wq);
716
717 /*
718 * At this point, if a task is running, it's guaranteed to see
719 * the FLUSH flag; thus, it will never queue pio tasks again.
720 * Cancel and flush.
721 */
722 tmp |= cancel_delayed_work(&ap->pio_task);
c18d06f8
TH		 723 if (!tmp) {
724 DPRINTK("flush #2\n");
725 flush_workqueue(ata_wq);
726 }
727
728 spin_lock_irqsave(&ap->host_set->lock, flags);
729 ap->flags &= ~ATA_FLAG_FLUSH_PIO_TASK;
730 spin_unlock_irqrestore(&ap->host_set->lock, flags);
731
732 DPRINTK("EXIT\n");
95064379
TH		 733}
734
77853bf2 735void ata_qc_complete_internal(struct ata_queued_cmd *qc)
64f043d8 736{
77853bf2 737 struct completion *waiting = qc->private_data;
64f043d8 738
77853bf2 739 qc->ap->ops->tf_read(qc->ap, &qc->tf);
a2a7a662 740 complete(waiting);
a2a7a662
TH		 741}
742
743/**
744 * ata_exec_internal - execute libata internal command
745 * @ap: Port to which the command is sent
746 * @dev: Device to which the command is sent
747 * @tf: Taskfile registers for the command and the result
748 * @dma_dir: Data tranfer direction of the command
749 * @buf: Data buffer of the command
750 * @buflen: Length of data buffer
751 *
752 * Executes libata internal command with timeout. @tf contains
753 * command on entry and result on return. Timeout and error
754 * conditions are reported via return value. No recovery action
755 * is taken after a command times out. It's caller's duty to
756 * clean up after timeout.
757 *
758 * LOCKING:
759 * None. Should be called with kernel context, might sleep.
760 */
761
762static unsigned
763ata_exec_internal(struct ata_port *ap, struct ata_device *dev,
764 struct ata_taskfile *tf,
765 int dma_dir, void *buf, unsigned int buflen)
766{
767 u8 command = tf->command;
768 struct ata_queued_cmd *qc;
769 DECLARE_COMPLETION(wait);
770 unsigned long flags;
77853bf2 771 unsigned int err_mask;
a2a7a662
TH		 772
773 spin_lock_irqsave(&ap->host_set->lock, flags);
774
775 qc = ata_qc_new_init(ap, dev);
776 BUG_ON(qc == NULL);
777
778 qc->tf = *tf;
779 qc->dma_dir = dma_dir;
780 if (dma_dir != DMA_NONE) {
781 ata_sg_init_one(qc, buf, buflen);
782 qc->nsect = buflen / ATA_SECT_SIZE;
783 }
784
77853bf2 785 qc->private_data = &wait;
a2a7a662
TH		 786 qc->complete_fn = ata_qc_complete_internal;
787
9a3d9eb0
TH		 788 qc->err_mask = ata_qc_issue(qc);
789 if (qc->err_mask)
8e436af9 790 ata_qc_complete(qc);
a2a7a662
TH		 791
792 spin_unlock_irqrestore(&ap->host_set->lock, flags);
793
794 if (!wait_for_completion_timeout(&wait, ATA_TMOUT_INTERNAL)) {
795 spin_lock_irqsave(&ap->host_set->lock, flags);
796
797 /* We're racing with irq here. If we lose, the
798 * following test prevents us from completing the qc
799 * again. If completion irq occurs after here but
800 * before the caller cleans up, it will result in a
801 * spurious interrupt. We can live with that.
802 */
77853bf2 803 if (qc->flags & ATA_QCFLAG_ACTIVE) {
11a56d24 804 qc->err_mask = AC_ERR_TIMEOUT;
a2a7a662
TH		 805 ata_qc_complete(qc);
806 printk(KERN_WARNING "ata%u: qc timeout (cmd 0x%x)\n",
807 ap->id, command);
64f043d8
JG		 808 }
809
a2a7a662 810 spin_unlock_irqrestore(&ap->host_set->lock, flags);
64f043d8
JG		 811 }
812
77853bf2
TH		 813 *tf = qc->tf;
814 err_mask = qc->err_mask;
815
816 ata_qc_free(qc);
817
818 return err_mask;
64f043d8
JG		 819}
820
1bc4ccff
AC		 821/**
822 * ata_pio_need_iordy - check if iordy needed
823 * @adev: ATA device
824 *
825 * Check if the current speed of the device requires IORDY. Used
826 * by various controllers for chip configuration.
827 */
828
829unsigned int ata_pio_need_iordy(const struct ata_device *adev)
830{
831 int pio;
832 int speed = adev->pio_mode - XFER_PIO_0;
833
834 if (speed < 2)
835 return 0;
836 if (speed > 2)
837 return 1;
838
839 /* If we have no drive specific rule, then PIO 2 is non IORDY */
840
841 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE */
842 pio = adev->id[ATA_ID_EIDE_PIO];
843 /* Is the speed faster than the drive allows non IORDY ? */
844 if (pio) {
845 /* This is cycle times not frequency - watch the logic! */
846 if (pio > 240) /* PIO2 is 240nS per cycle */
847 return 1;
848 return 0;
849 }
850 }
851 return 0;
852}
853
1da177e4
LT		 854/**
855 * ata_dev_identify - obtain IDENTIFY x DEVICE page
856 * @ap: port on which device we wish to probe resides
857 * @device: device bus address, starting at zero
858 *
859 * Following bus reset, we issue the IDENTIFY [PACKET] DEVICE
860 * command, and read back the 512-byte device information page.
861 * The device information page is fed to us via the standard
862 * PIO-IN protocol, but we hand-code it here. (TODO: investigate
863 * using standard PIO-IN paths)
864 *
865 * After reading the device information page, we use several
866 * bits of information from it to initialize data structures
867 * that will be used during the lifetime of the ata_device.
868 * Other data from the info page is used to disqualify certain
869 * older ATA devices we do not wish to support.
870 *
871 * LOCKING:
872 * Inherited from caller. Some functions called by this function
873 * obtain the host_set lock.
874 */
875
876static void ata_dev_identify(struct ata_port *ap, unsigned int device)
877{
878 struct ata_device *dev = &ap->device[device];
8bf62ece 879 unsigned int major_version;
1da177e4
LT		 880 u16 tmp;
881 unsigned long xfer_modes;
1da177e4 882 unsigned int using_edd;
a0123703
TH		 883 struct ata_taskfile tf;
884 unsigned int err_mask;
1da177e4
LT		 885 int rc;
886
887 if (!ata_dev_present(dev)) {
888 DPRINTK("ENTER/EXIT (host %u, dev %u) -- nodev\n",
889 ap->id, device);
890 return;
891 }
892
893 if (ap->flags & (ATA_FLAG_SRST | ATA_FLAG_SATA_RESET))
894 using_edd = 0;
895 else
896 using_edd = 1;
897
898 DPRINTK("ENTER, host %u, dev %u\n", ap->id, device);
899
a4631474
TH		 900 WARN_ON(dev->class != ATA_DEV_ATA && dev->class != ATA_DEV_ATAPI &&
901 dev->class != ATA_DEV_NONE);
1da177e4
LT		 902
903 ata_dev_select(ap, device, 1, 1); /* select device 0/1 */
904
1da177e4 905retry:
a0123703
TH		 906 ata_tf_init(ap, &tf, device);
907
1da177e4 908 if (dev->class == ATA_DEV_ATA) {
a0123703 909 tf.command = ATA_CMD_ID_ATA;
1da177e4
LT		 910 DPRINTK("do ATA identify\n");
911 } else {
a0123703 912 tf.command = ATA_CMD_ID_ATAPI;
1da177e4
LT		 913 DPRINTK("do ATAPI identify\n");
914 }
915
a0123703 916 tf.protocol = ATA_PROT_PIO;
1da177e4 917
a0123703
TH		 918 err_mask = ata_exec_internal(ap, dev, &tf, DMA_FROM_DEVICE,
919 dev->id, sizeof(dev->id));
1da177e4 920
a0123703
TH		 921 if (err_mask) {
922 if (err_mask & ~AC_ERR_DEV)
923 goto err_out;
1da177e4 924
1da177e4
LT		 925 /*
926 * arg! EDD works for all test cases, but seems to return
927 * the ATA signature for some ATAPI devices. Until the
928 * reason for this is found and fixed, we fix up the mess
929 * here. If IDENTIFY DEVICE returns command aborted
930 * (as ATAPI devices do), then we issue an
931 * IDENTIFY PACKET DEVICE.
932 *
933 * ATA software reset (SRST, the default) does not appear
934 * to have this problem.
935 */
7c398335 936 if ((using_edd) && (dev->class == ATA_DEV_ATA)) {
a0123703 937 u8 err = tf.feature;
1da177e4
LT		 938 if (err & ATA_ABORTED) {
939 dev->class = ATA_DEV_ATAPI;
1da177e4
LT		 940 goto retry;
941 }
942 }
943 goto err_out;
944 }
945
946 swap_buf_le16(dev->id, ATA_ID_WORDS);
947
948 /* print device capabilities */
949 printk(KERN_DEBUG "ata%u: dev %u cfg "
950 "49:%04x 82:%04x 83:%04x 84:%04x 85:%04x 86:%04x 87:%04x 88:%04x\n",
951 ap->id, device, dev->id[49],
952 dev->id[82], dev->id[83], dev->id[84],
953 dev->id[85], dev->id[86], dev->id[87],
954 dev->id[88]);
955
956 /*
957 * common ATA, ATAPI feature tests
958 */
959
8bf62ece
AL		 960 /* we require DMA support (bits 8 of word 49) */
961 if (!ata_id_has_dma(dev->id)) {
962 printk(KERN_DEBUG "ata%u: no dma\n", ap->id);
1da177e4
LT		 963 goto err_out_nosup;
964 }
965
966 /* quick-n-dirty find max transfer mode; for printk only */
967 xfer_modes = dev->id[ATA_ID_UDMA_MODES];
968 if (!xfer_modes)
969 xfer_modes = (dev->id[ATA_ID_MWDMA_MODES]) << ATA_SHIFT_MWDMA;
11e29e21
AC		 970 if (!xfer_modes)
971 xfer_modes = ata_pio_modes(dev);
1da177e4
LT		 972
973 ata_dump_id(dev);
974
975 /* ATA-specific feature tests */
976 if (dev->class == ATA_DEV_ATA) {
977 if (!ata_id_is_ata(dev->id)) /* sanity check */
978 goto err_out_nosup;
979
8bf62ece 980 /* get major version */
1da177e4 981 tmp = dev->id[ATA_ID_MAJOR_VER];
8bf62ece
AL		 982 for (major_version = 14; major_version >= 1; major_version--)
983 if (tmp & (1 << major_version))
1da177e4
LT		 984 break;
985
8bf62ece
AL		 986 /*
987 * The exact sequence expected by certain pre-ATA4 drives is:
988 * SRST RESET
989 * IDENTIFY
990 * INITIALIZE DEVICE PARAMETERS
991 * anything else..
992 * Some drives were very specific about that exact sequence.
993 */
59a10b17 994 if (major_version < 4 || (!ata_id_has_lba(dev->id))) {
8bf62ece
AL		 995 ata_dev_init_params(ap, dev);
996
59a10b17
AL		 997 /* current CHS translation info (id[53-58]) might be
998 * changed. reread the identify device info.
999 */
1000 ata_dev_reread_id(ap, dev);
1001 }
1002
8bf62ece
AL		 1003 if (ata_id_has_lba(dev->id)) {
1004 dev->flags |= ATA_DFLAG_LBA;
1005
1006 if (ata_id_has_lba48(dev->id)) {
1007 dev->flags |= ATA_DFLAG_LBA48;
1008 dev->n_sectors = ata_id_u64(dev->id, 100);
1009 } else {
1010 dev->n_sectors = ata_id_u32(dev->id, 60);
1011 }
1012
1013 /* print device info to dmesg */
1014 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors:%s\n",
1015 ap->id, device,
1016 major_version,
1017 ata_mode_string(xfer_modes),
1018 (unsigned long long)dev->n_sectors,
1019 dev->flags & ATA_DFLAG_LBA48 ? " LBA48" : " LBA");
1020 } else {
1021 /* CHS */
1022
1023 /* Default translation */
1024 dev->cylinders = dev->id[1];
1025 dev->heads = dev->id[3];
1026 dev->sectors = dev->id[6];
1027 dev->n_sectors = dev->cylinders * dev->heads * dev->sectors;
1028
1029 if (ata_id_current_chs_valid(dev->id)) {
1030 /* Current CHS translation is valid. */
1031 dev->cylinders = dev->id[54];
1032 dev->heads = dev->id[55];
1033 dev->sectors = dev->id[56];
1034
1035 dev->n_sectors = ata_id_u32(dev->id, 57);
1036 }
1037
1038 /* print device info to dmesg */
1039 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors: CHS %d/%d/%d\n",
1040 ap->id, device,
1041 major_version,
1042 ata_mode_string(xfer_modes),
1043 (unsigned long long)dev->n_sectors,
1044 (int)dev->cylinders, (int)dev->heads, (int)dev->sectors);
1da177e4 1045
1da177e4
LT		 1046 }
1047
07f6f7d0
AL		 1048 if (dev->id[59] & 0x100) {
1049 dev->multi_count = dev->id[59] & 0xff;
1050 DPRINTK("ata%u: dev %u multi count %u\n",
1051 ap->id, device, dev->multi_count);
1052 }
1053
1da177e4 1054 ap->host->max_cmd_len = 16;
1da177e4
LT		 1055 }
1056
1057 /* ATAPI-specific feature tests */
2c13b7ce 1058 else if (dev->class == ATA_DEV_ATAPI) {
1da177e4
LT		 1059 if (ata_id_is_ata(dev->id)) /* sanity check */
1060 goto err_out_nosup;
1061
1062 rc = atapi_cdb_len(dev->id);
1063 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
1064 printk(KERN_WARNING "ata%u: unsupported CDB len\n", ap->id);
1065 goto err_out_nosup;
1066 }
1067 ap->cdb_len = (unsigned int) rc;
1068 ap->host->max_cmd_len = (unsigned char) ap->cdb_len;
1069
312f7da2
AL		 1070 if (ata_id_cdb_intr(dev->id))
1071 dev->flags |= ATA_DFLAG_CDB_INTR;
1072
1da177e4
LT		 1073 /* print device info to dmesg */
1074 printk(KERN_INFO "ata%u: dev %u ATAPI, max %s\n",
1075 ap->id, device,
1076 ata_mode_string(xfer_modes));
1077 }
1078
1079 DPRINTK("EXIT, drv_stat = 0x%x\n", ata_chk_status(ap));
1080 return;
1081
1082err_out_nosup:
1083 printk(KERN_WARNING "ata%u: dev %u not supported, ignoring\n",
1084 ap->id, device);
1085err_out:
1086 dev->class++; /* converts ATA_DEV_xxx into ATA_DEV_xxx_UNSUP */
1087 DPRINTK("EXIT, err\n");
1088}
1089
6f2f3812 1090
057ace5e 1091static inline u8 ata_dev_knobble(const struct ata_port *ap)
6f2f3812
BC		 1092{
1093 return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ap->device->id)));
1094}
1095
1096/**
c893a3ae
RD		 1097 * ata_dev_config - Run device specific handlers & check for SATA->PATA bridges
1098 * @ap: Bus
1099 * @i: Device
6f2f3812 1100 *
c893a3ae 1101 * LOCKING:
6f2f3812 1102 */
8a60a071 1103
6f2f3812
BC		 1104void ata_dev_config(struct ata_port *ap, unsigned int i)
1105{
1106 /* limit bridge transfers to udma5, 200 sectors */
1107 if (ata_dev_knobble(ap)) {
1108 printk(KERN_INFO "ata%u(%u): applying bridge limits\n",
1109 ap->id, ap->device->devno);
1110 ap->udma_mask &= ATA_UDMA5;
1111 ap->host->max_sectors = ATA_MAX_SECTORS;
1112 ap->host->hostt->max_sectors = ATA_MAX_SECTORS;
9d824d07 1113 ap->device[i].flags |= ATA_DFLAG_LOCK_SECTORS;
6f2f3812
BC		 1114 }
1115
1116 if (ap->ops->dev_config)
1117 ap->ops->dev_config(ap, &ap->device[i]);
1118}
1119
1da177e4
LT		 1120/**
1121 * ata_bus_probe - Reset and probe ATA bus
1122 * @ap: Bus to probe
1123 *
0cba632b
JG		 1124 * Master ATA bus probing function. Initiates a hardware-dependent
1125 * bus reset, then attempts to identify any devices found on
1126 * the bus.
1127 *
1da177e4 1128 * LOCKING:
0cba632b 1129 * PCI/etc. bus probe sem.
1da177e4
LT		 1130 *
1131 * RETURNS:
1132 * Zero on success, non-zero on error.
1133 */
1134
1135static int ata_bus_probe(struct ata_port *ap)
1136{
1137 unsigned int i, found = 0;
1138
c19ba8af
TH		 1139 if (ap->ops->probe_reset) {
1140 unsigned int classes[ATA_MAX_DEVICES];
1141 int rc;
1142
1143 ata_port_probe(ap);
1144
1145 rc = ap->ops->probe_reset(ap, classes);
1146 if (rc == 0) {
1147 for (i = 0; i < ATA_MAX_DEVICES; i++)
1148 ap->device[i].class = classes[i];
1149 } else {
1150 printk(KERN_ERR "ata%u: probe reset failed, "
1151 "disabling port\n", ap->id);
1152 ata_port_disable(ap);
1153 }
1154 } else
1155 ap->ops->phy_reset(ap);
1156
1da177e4
LT		 1157 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1158 goto err_out;
1159
1160 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1161 ata_dev_identify(ap, i);
1162 if (ata_dev_present(&ap->device[i])) {
1163 found = 1;
6f2f3812 1164 ata_dev_config(ap,i);
1da177e4
LT		 1165 }
1166 }
1167
1168 if ((!found) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1169 goto err_out_disable;
1170
1171 ata_set_mode(ap);
1172 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1173 goto err_out_disable;
1174
1175 return 0;
1176
1177err_out_disable:
1178 ap->ops->port_disable(ap);
1179err_out:
1180 return -1;
1181}
1182
1183/**
0cba632b
JG		 1184 * ata_port_probe - Mark port as enabled
1185 * @ap: Port for which we indicate enablement
1da177e4 1186 *
0cba632b
JG		 1187 * Modify @ap data structure such that the system
1188 * thinks that the entire port is enabled.
1189 *
1190 * LOCKING: host_set lock, or some other form of
1191 * serialization.
1da177e4
LT		 1192 */
1193
1194void ata_port_probe(struct ata_port *ap)
1195{
1196 ap->flags &= ~ATA_FLAG_PORT_DISABLED;
1197}
1198
3be680b7
TH		 1199/**
1200 * sata_print_link_status - Print SATA link status
1201 * @ap: SATA port to printk link status about
1202 *
1203 * This function prints link speed and status of a SATA link.
1204 *
1205 * LOCKING:
1206 * None.
1207 */
1208static void sata_print_link_status(struct ata_port *ap)
1209{
1210 u32 sstatus, tmp;
1211 const char *speed;
1212
1213 if (!ap->ops->scr_read)
1214 return;
1215
1216 sstatus = scr_read(ap, SCR_STATUS);
1217
1218 if (sata_dev_present(ap)) {
1219 tmp = (sstatus >> 4) & 0xf;
1220 if (tmp & (1 << 0))
1221 speed = "1.5";
1222 else if (tmp & (1 << 1))
1223 speed = "3.0";
1224 else
1225 speed = "<unknown>";
1226 printk(KERN_INFO "ata%u: SATA link up %s Gbps (SStatus %X)\n",
1227 ap->id, speed, sstatus);
1228 } else {
1229 printk(KERN_INFO "ata%u: SATA link down (SStatus %X)\n",
1230 ap->id, sstatus);
1231 }
1232}
1233
1da177e4 1234/**
780a87f7
JG		 1235 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1236 * @ap: SATA port associated with target SATA PHY.
1da177e4 1237 *
780a87f7
JG		 1238 * This function issues commands to standard SATA Sxxx
1239 * PHY registers, to wake up the phy (and device), and
1240 * clear any reset condition.
1da177e4
LT		 1241 *
1242 * LOCKING:
0cba632b 1243 * PCI/etc. bus probe sem.
1da177e4
LT		 1244 *
1245 */
1246void __sata_phy_reset(struct ata_port *ap)
1247{
1248 u32 sstatus;
1249 unsigned long timeout = jiffies + (HZ * 5);
1250
1251 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e
BR		 1252 /* issue phy wake/reset */
1253 scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH		 1254 /* Couldn't find anything in SATA I/II specs, but
1255 * AHCI-1.1 10.4.2 says at least 1 ms. */
1256 mdelay(1);
1da177e4 1257 }
cdcca89e 1258 scr_write_flush(ap, SCR_CONTROL, 0x300); /* phy wake/clear reset */
1da177e4
LT		 1259
1260 /* wait for phy to become ready, if necessary */
1261 do {
1262 msleep(200);
1263 sstatus = scr_read(ap, SCR_STATUS);
1264 if ((sstatus & 0xf) != 1)
1265 break;
1266 } while (time_before(jiffies, timeout));
1267
3be680b7
TH		 1268 /* print link status */
1269 sata_print_link_status(ap);
656563e3 1270
3be680b7
TH		 1271 /* TODO: phy layer with polling, timeouts, etc. */
1272 if (sata_dev_present(ap))
1da177e4 1273 ata_port_probe(ap);
3be680b7 1274 else
1da177e4 1275 ata_port_disable(ap);
1da177e4
LT		 1276
1277 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1278 return;
1279
1280 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1281 ata_port_disable(ap);
1282 return;
1283 }
1284
1285 ap->cbl = ATA_CBL_SATA;
1286}
1287
1288/**
780a87f7
JG		 1289 * sata_phy_reset - Reset SATA bus.
1290 * @ap: SATA port associated with target SATA PHY.
1da177e4 1291 *
780a87f7
JG		 1292 * This function resets the SATA bus, and then probes
1293 * the bus for devices.
1da177e4
LT		 1294 *
1295 * LOCKING:
0cba632b 1296 * PCI/etc. bus probe sem.
1da177e4
LT		 1297 *
1298 */
1299void sata_phy_reset(struct ata_port *ap)
1300{
1301 __sata_phy_reset(ap);
1302 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1303 return;
1304 ata_bus_reset(ap);
1305}
1306
1307/**
780a87f7
JG		 1308 * ata_port_disable - Disable port.
1309 * @ap: Port to be disabled.
1da177e4 1310 *
780a87f7
JG		 1311 * Modify @ap data structure such that the system
1312 * thinks that the entire port is disabled, and should
1313 * never attempt to probe or communicate with devices
1314 * on this port.
1315 *
1316 * LOCKING: host_set lock, or some other form of
1317 * serialization.
1da177e4
LT		 1318 */
1319
1320void ata_port_disable(struct ata_port *ap)
1321{
1322 ap->device[0].class = ATA_DEV_NONE;
1323 ap->device[1].class = ATA_DEV_NONE;
1324 ap->flags |= ATA_FLAG_PORT_DISABLED;
1325}
1326
452503f9
AC		 1327/*
1328 * This mode timing computation functionality is ported over from
1329 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1330 */
1331/*
1332 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
1333 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
1334 * for PIO 5, which is a nonstandard extension and UDMA6, which
1335 * is currently supported only by Maxtor drives.
1336 */
1337
1338static const struct ata_timing ata_timing[] = {
1339
1340 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1341 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1342 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1343 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1344
1345 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1346 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1347 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1348
1349/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
1350
1351 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1352 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1353 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
1354
1355 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
1356 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
1357 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
1358
1359/* { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, */
1360 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
1361 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
1362
1363 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
1364 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
1365 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
1366
1367/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
1368
1369 { 0xFF }
1370};
1371
1372#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
1373#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
1374
1375static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
1376{
1377 q->setup = EZ(t->setup * 1000, T);
1378 q->act8b = EZ(t->act8b * 1000, T);
1379 q->rec8b = EZ(t->rec8b * 1000, T);
1380 q->cyc8b = EZ(t->cyc8b * 1000, T);
1381 q->active = EZ(t->active * 1000, T);
1382 q->recover = EZ(t->recover * 1000, T);
1383 q->cycle = EZ(t->cycle * 1000, T);
1384 q->udma = EZ(t->udma * 1000, UT);
1385}
1386
1387void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
1388 struct ata_timing *m, unsigned int what)
1389{
1390 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
1391 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
1392 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
1393 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
1394 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
1395 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
1396 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
1397 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
1398}
1399
1400static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
1401{
1402 const struct ata_timing *t;
1403
1404 for (t = ata_timing; t->mode != speed; t++)
91190758 1405 if (t->mode == 0xFF)
452503f9
AC		 1406 return NULL;
1407 return t;
1408}
1409
1410int ata_timing_compute(struct ata_device *adev, unsigned short speed,
1411 struct ata_timing *t, int T, int UT)
1412{
1413 const struct ata_timing *s;
1414 struct ata_timing p;
1415
1416 /*
1417 * Find the mode.
75b1f2f8 1418 */
452503f9
AC		 1419
1420 if (!(s = ata_timing_find_mode(speed)))
1421 return -EINVAL;
1422
75b1f2f8
AL		 1423 memcpy(t, s, sizeof(*s));
1424
452503f9
AC		 1425 /*
1426 * If the drive is an EIDE drive, it can tell us it needs extended
1427 * PIO/MW_DMA cycle timing.
1428 */
1429
1430 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
1431 memset(&p, 0, sizeof(p));
1432 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
1433 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
1434 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
1435 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
1436 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
1437 }
1438 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
1439 }
1440
1441 /*
1442 * Convert the timing to bus clock counts.
1443 */
1444
75b1f2f8 1445 ata_timing_quantize(t, t, T, UT);
452503f9
AC		 1446
1447 /*
c893a3ae
RD		 1448 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
1449 * S.M.A.R.T * and some other commands. We have to ensure that the
1450 * DMA cycle timing is slower/equal than the fastest PIO timing.
452503f9
AC		 1451 */
1452
1453 if (speed > XFER_PIO_4) {
1454 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
1455 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
1456 }
1457
1458 /*
c893a3ae 1459 * Lengthen active & recovery time so that cycle time is correct.
452503f9
AC		 1460 */
1461
1462 if (t->act8b + t->rec8b < t->cyc8b) {
1463 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
1464 t->rec8b = t->cyc8b - t->act8b;
1465 }
1466
1467 if (t->active + t->recover < t->cycle) {
1468 t->active += (t->cycle - (t->active + t->recover)) / 2;
1469 t->recover = t->cycle - t->active;
1470 }
1471
1472 return 0;
1473}
1474
057ace5e 1475static const struct {
1da177e4
LT		 1476 unsigned int shift;
1477 u8 base;
1478} xfer_mode_classes[] = {
1479 { ATA_SHIFT_UDMA, XFER_UDMA_0 },
1480 { ATA_SHIFT_MWDMA, XFER_MW_DMA_0 },
1481 { ATA_SHIFT_PIO, XFER_PIO_0 },
1482};
1483
858119e1 1484static u8 base_from_shift(unsigned int shift)
1da177e4
LT		 1485{
1486 int i;
1487
1488 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++)
1489 if (xfer_mode_classes[i].shift == shift)
1490 return xfer_mode_classes[i].base;
1491
1492 return 0xff;
1493}
1494
1495static void ata_dev_set_mode(struct ata_port *ap, struct ata_device *dev)
1496{
1497 int ofs, idx;
1498 u8 base;
1499
1500 if (!ata_dev_present(dev) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1501 return;
1502
1503 if (dev->xfer_shift == ATA_SHIFT_PIO)
1504 dev->flags |= ATA_DFLAG_PIO;
1505
1506 ata_dev_set_xfermode(ap, dev);
1507
1508 base = base_from_shift(dev->xfer_shift);
1509 ofs = dev->xfer_mode - base;
1510 idx = ofs + dev->xfer_shift;
1511 WARN_ON(idx >= ARRAY_SIZE(xfer_mode_str));
1512
1513 DPRINTK("idx=%d xfer_shift=%u, xfer_mode=0x%x, base=0x%x, offset=%d\n",
1514 idx, dev->xfer_shift, (int)dev->xfer_mode, (int)base, ofs);
1515
1516 printk(KERN_INFO "ata%u: dev %u configured for %s\n",
1517 ap->id, dev->devno, xfer_mode_str[idx]);
1518}
1519
1520static int ata_host_set_pio(struct ata_port *ap)
1521{
1522 unsigned int mask;
1523 int x, i;
1524 u8 base, xfer_mode;
1525
1526 mask = ata_get_mode_mask(ap, ATA_SHIFT_PIO);
1527 x = fgb(mask);
1528 if (x < 0) {
1529 printk(KERN_WARNING "ata%u: no PIO support\n", ap->id);
1530 return -1;
1531 }
1532
1533 base = base_from_shift(ATA_SHIFT_PIO);
1534 xfer_mode = base + x;
1535
1536 DPRINTK("base 0x%x xfer_mode 0x%x mask 0x%x x %d\n",
1537 (int)base, (int)xfer_mode, mask, x);
1538
1539 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1540 struct ata_device *dev = &ap->device[i];
1541 if (ata_dev_present(dev)) {
1542 dev->pio_mode = xfer_mode;
1543 dev->xfer_mode = xfer_mode;
1544 dev->xfer_shift = ATA_SHIFT_PIO;
1545 if (ap->ops->set_piomode)
1546 ap->ops->set_piomode(ap, dev);
1547 }
1548 }
1549
1550 return 0;
1551}
1552
1553static void ata_host_set_dma(struct ata_port *ap, u8 xfer_mode,
1554 unsigned int xfer_shift)
1555{
1556 int i;
1557
1558 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1559 struct ata_device *dev = &ap->device[i];
1560 if (ata_dev_present(dev)) {
1561 dev->dma_mode = xfer_mode;
1562 dev->xfer_mode = xfer_mode;
1563 dev->xfer_shift = xfer_shift;
1564 if (ap->ops->set_dmamode)
1565 ap->ops->set_dmamode(ap, dev);
1566 }
1567 }
1568}
1569
1570/**
1571 * ata_set_mode - Program timings and issue SET FEATURES - XFER
1572 * @ap: port on which timings will be programmed
1573 *
780a87f7
JG		 1574 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.).
1575 *
1da177e4 1576 * LOCKING:
0cba632b 1577 * PCI/etc. bus probe sem.
1da177e4
LT		 1578 */
1579static void ata_set_mode(struct ata_port *ap)
1580{
8cbd6df1 1581 unsigned int xfer_shift;
1da177e4
LT		 1582 u8 xfer_mode;
1583 int rc;
1584
1585 /* step 1: always set host PIO timings */
1586 rc = ata_host_set_pio(ap);
1587 if (rc)
1588 goto err_out;
1589
1590 /* step 2: choose the best data xfer mode */
1591 xfer_mode = xfer_shift = 0;
1592 rc = ata_choose_xfer_mode(ap, &xfer_mode, &xfer_shift);
1593 if (rc)
1594 goto err_out;
1595
1596 /* step 3: if that xfer mode isn't PIO, set host DMA timings */
1597 if (xfer_shift != ATA_SHIFT_PIO)
1598 ata_host_set_dma(ap, xfer_mode, xfer_shift);
1599
1600 /* step 4: update devices' xfer mode */
1601 ata_dev_set_mode(ap, &ap->device[0]);
1602 ata_dev_set_mode(ap, &ap->device[1]);
1603
1604 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1605 return;
1606
1607 if (ap->ops->post_set_mode)
1608 ap->ops->post_set_mode(ap);
1609
1da177e4
LT		 1610 return;
1611
1612err_out:
1613 ata_port_disable(ap);
1614}
1615
1fdffbce
JG		 1616/**
1617 * ata_tf_to_host - issue ATA taskfile to host controller
1618 * @ap: port to which command is being issued
1619 * @tf: ATA taskfile register set
1620 *
1621 * Issues ATA taskfile register set to ATA host controller,
1622 * with proper synchronization with interrupt handler and
1623 * other threads.
1624 *
1625 * LOCKING:
1626 * spin_lock_irqsave(host_set lock)
1627 */
1628
1629static inline void ata_tf_to_host(struct ata_port *ap,
1630 const struct ata_taskfile *tf)
1631{
1632 ap->ops->tf_load(ap, tf);
1633 ap->ops->exec_command(ap, tf);
1634}
1635
1da177e4
LT		 1636/**
1637 * ata_busy_sleep - sleep until BSY clears, or timeout
1638 * @ap: port containing status register to be polled
1639 * @tmout_pat: impatience timeout
1640 * @tmout: overall timeout
1641 *
780a87f7
JG		 1642 * Sleep until ATA Status register bit BSY clears,
1643 * or a timeout occurs.
1644 *
1645 * LOCKING: None.
1da177e4
LT		 1646 */
1647
6f8b9958
TH		 1648unsigned int ata_busy_sleep (struct ata_port *ap,
1649 unsigned long tmout_pat, unsigned long tmout)
1da177e4
LT		 1650{
1651 unsigned long timer_start, timeout;
1652 u8 status;
1653
1654 status = ata_busy_wait(ap, ATA_BUSY, 300);
1655 timer_start = jiffies;
1656 timeout = timer_start + tmout_pat;
1657 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1658 msleep(50);
1659 status = ata_busy_wait(ap, ATA_BUSY, 3);
1660 }
1661
1662 if (status & ATA_BUSY)
1663 printk(KERN_WARNING "ata%u is slow to respond, "
1664 "please be patient\n", ap->id);
1665
1666 timeout = timer_start + tmout;
1667 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1668 msleep(50);
1669 status = ata_chk_status(ap);
1670 }
1671
1672 if (status & ATA_BUSY) {
1673 printk(KERN_ERR "ata%u failed to respond (%lu secs)\n",
1674 ap->id, tmout / HZ);
1675 return 1;
1676 }
1677
1678 return 0;
1679}
1680
1681static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
1682{
1683 struct ata_ioports *ioaddr = &ap->ioaddr;
1684 unsigned int dev0 = devmask & (1 << 0);
1685 unsigned int dev1 = devmask & (1 << 1);
1686 unsigned long timeout;
1687
1688 /* if device 0 was found in ata_devchk, wait for its
1689 * BSY bit to clear
1690 */
1691 if (dev0)
1692 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1693
1694 /* if device 1 was found in ata_devchk, wait for
1695 * register access, then wait for BSY to clear
1696 */
1697 timeout = jiffies + ATA_TMOUT_BOOT;
1698 while (dev1) {
1699 u8 nsect, lbal;
1700
1701 ap->ops->dev_select(ap, 1);
1702 if (ap->flags & ATA_FLAG_MMIO) {
1703 nsect = readb((void __iomem *) ioaddr->nsect_addr);
1704 lbal = readb((void __iomem *) ioaddr->lbal_addr);
1705 } else {
1706 nsect = inb(ioaddr->nsect_addr);
1707 lbal = inb(ioaddr->lbal_addr);
1708 }
1709 if ((nsect == 1) && (lbal == 1))
1710 break;
1711 if (time_after(jiffies, timeout)) {
1712 dev1 = 0;
1713 break;
1714 }
1715 msleep(50); /* give drive a breather */
1716 }
1717 if (dev1)
1718 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1719
1720 /* is all this really necessary? */
1721 ap->ops->dev_select(ap, 0);
1722 if (dev1)
1723 ap->ops->dev_select(ap, 1);
1724 if (dev0)
1725 ap->ops->dev_select(ap, 0);
1726}
1727
1728/**
0cba632b
JG		 1729 * ata_bus_edd - Issue EXECUTE DEVICE DIAGNOSTIC command.
1730 * @ap: Port to reset and probe
1731 *
1732 * Use the EXECUTE DEVICE DIAGNOSTIC command to reset and
1733 * probe the bus. Not often used these days.
1da177e4
LT		 1734 *
1735 * LOCKING:
0cba632b 1736 * PCI/etc. bus probe sem.
e5338254 1737 * Obtains host_set lock.
1da177e4
LT		 1738 *
1739 */
1740
1741static unsigned int ata_bus_edd(struct ata_port *ap)
1742{
1743 struct ata_taskfile tf;
e5338254 1744 unsigned long flags;
1da177e4
LT		 1745
1746 /* set up execute-device-diag (bus reset) taskfile */
1747 /* also, take interrupts to a known state (disabled) */
1748 DPRINTK("execute-device-diag\n");
1749 ata_tf_init(ap, &tf, 0);
1750 tf.ctl |= ATA_NIEN;
1751 tf.command = ATA_CMD_EDD;
1752 tf.protocol = ATA_PROT_NODATA;
1753
1754 /* do bus reset */
e5338254 1755 spin_lock_irqsave(&ap->host_set->lock, flags);
1da177e4 1756 ata_tf_to_host(ap, &tf);
e5338254 1757 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1da177e4
LT		 1758
1759 /* spec says at least 2ms. but who knows with those
1760 * crazy ATAPI devices...
1761 */
1762 msleep(150);
1763
1764 return ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1765}
1766
1767static unsigned int ata_bus_softreset(struct ata_port *ap,
1768 unsigned int devmask)
1769{
1770 struct ata_ioports *ioaddr = &ap->ioaddr;
1771
1772 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
1773
1774 /* software reset. causes dev0 to be selected */
1775 if (ap->flags & ATA_FLAG_MMIO) {
1776 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1777 udelay(20); /* FIXME: flush */
1778 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
1779 udelay(20); /* FIXME: flush */
1780 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1781 } else {
1782 outb(ap->ctl, ioaddr->ctl_addr);
1783 udelay(10);
1784 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1785 udelay(10);
1786 outb(ap->ctl, ioaddr->ctl_addr);
1787 }
1788
1789 /* spec mandates ">= 2ms" before checking status.
1790 * We wait 150ms, because that was the magic delay used for
1791 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1792 * between when the ATA command register is written, and then
1793 * status is checked. Because waiting for "a while" before
1794 * checking status is fine, post SRST, we perform this magic
1795 * delay here as well.
1796 */
1797 msleep(150);
1798
1799 ata_bus_post_reset(ap, devmask);
1800
1801 return 0;
1802}
1803
1804/**
1805 * ata_bus_reset - reset host port and associated ATA channel
1806 * @ap: port to reset
1807 *
1808 * This is typically the first time we actually start issuing
1809 * commands to the ATA channel. We wait for BSY to clear, then
1810 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
1811 * result. Determine what devices, if any, are on the channel
1812 * by looking at the device 0/1 error register. Look at the signature
1813 * stored in each device's taskfile registers, to determine if
1814 * the device is ATA or ATAPI.
1815 *
1816 * LOCKING:
0cba632b
JG		 1817 * PCI/etc. bus probe sem.
1818 * Obtains host_set lock.
1da177e4
LT		 1819 *
1820 * SIDE EFFECTS:
1821 * Sets ATA_FLAG_PORT_DISABLED if bus reset fails.
1822 */
1823
1824void ata_bus_reset(struct ata_port *ap)
1825{
1826 struct ata_ioports *ioaddr = &ap->ioaddr;
1827 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1828 u8 err;
1829 unsigned int dev0, dev1 = 0, rc = 0, devmask = 0;
1830
1831 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
1832
1833 /* determine if device 0/1 are present */
1834 if (ap->flags & ATA_FLAG_SATA_RESET)
1835 dev0 = 1;
1836 else {
1837 dev0 = ata_devchk(ap, 0);
1838 if (slave_possible)
1839 dev1 = ata_devchk(ap, 1);
1840 }
1841
1842 if (dev0)
1843 devmask |= (1 << 0);
1844 if (dev1)
1845 devmask |= (1 << 1);
1846
1847 /* select device 0 again */
1848 ap->ops->dev_select(ap, 0);
1849
1850 /* issue bus reset */
1851 if (ap->flags & ATA_FLAG_SRST)
1852 rc = ata_bus_softreset(ap, devmask);
1853 else if ((ap->flags & ATA_FLAG_SATA_RESET) == 0) {
1854 /* set up device control */
1855 if (ap->flags & ATA_FLAG_MMIO)
1856 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1857 else
1858 outb(ap->ctl, ioaddr->ctl_addr);
1859 rc = ata_bus_edd(ap);
1860 }
1861
1862 if (rc)
1863 goto err_out;
1864
1865 /*
1866 * determine by signature whether we have ATA or ATAPI devices
1867 */
b4dc7623 1868 ap->device[0].class = ata_dev_try_classify(ap, 0, &err);
1da177e4 1869 if ((slave_possible) && (err != 0x81))
b4dc7623 1870 ap->device[1].class = ata_dev_try_classify(ap, 1, &err);
1da177e4
LT		 1871
1872 /* re-enable interrupts */
1873 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
1874 ata_irq_on(ap);
1875
1876 /* is double-select really necessary? */
1877 if (ap->device[1].class != ATA_DEV_NONE)
1878 ap->ops->dev_select(ap, 1);
1879 if (ap->device[0].class != ATA_DEV_NONE)
1880 ap->ops->dev_select(ap, 0);
1881
1882 /* if no devices were detected, disable this port */
1883 if ((ap->device[0].class == ATA_DEV_NONE) &&
1884 (ap->device[1].class == ATA_DEV_NONE))
1885 goto err_out;
1886
1887 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
1888 /* set up device control for ATA_FLAG_SATA_RESET */
1889 if (ap->flags & ATA_FLAG_MMIO)
1890 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1891 else
1892 outb(ap->ctl, ioaddr->ctl_addr);
1893 }
1894
1895 DPRINTK("EXIT\n");
1896 return;
1897
1898err_out:
1899 printk(KERN_ERR "ata%u: disabling port\n", ap->id);
1900 ap->ops->port_disable(ap);
1901
1902 DPRINTK("EXIT\n");
1903}
1904
7a7921e8
TH		 1905static int sata_phy_resume(struct ata_port *ap)
1906{
1907 unsigned long timeout = jiffies + (HZ * 5);
1908 u32 sstatus;
1909
1910 scr_write_flush(ap, SCR_CONTROL, 0x300);
1911
1912 /* Wait for phy to become ready, if necessary. */
1913 do {
1914 msleep(200);
1915 sstatus = scr_read(ap, SCR_STATUS);
1916 if ((sstatus & 0xf) != 1)
1917 return 0;
1918 } while (time_before(jiffies, timeout));
1919
1920 return -1;
1921}
1922
8a19ac89
TH		 1923/**
1924 * ata_std_probeinit - initialize probing
1925 * @ap: port to be probed
1926 *
1927 * @ap is about to be probed. Initialize it. This function is
1928 * to be used as standard callback for ata_drive_probe_reset().
3a39746a
TH		 1929 *
1930 * NOTE!!! Do not use this function as probeinit if a low level
1931 * driver implements only hardreset. Just pass NULL as probeinit
1932 * in that case. Using this function is probably okay but doing
1933 * so makes reset sequence different from the original
1934 * ->phy_reset implementation and Jeff nervous. :-P
8a19ac89
TH		 1935 */
1936extern void ata_std_probeinit(struct ata_port *ap)
1937{
3a39746a 1938 if (ap->flags & ATA_FLAG_SATA && ap->ops->scr_read) {
8a19ac89 1939 sata_phy_resume(ap);
3a39746a
TH		 1940 if (sata_dev_present(ap))
1941 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1942 }
8a19ac89
TH		 1943}
1944
c2bd5804
TH		 1945/**
1946 * ata_std_softreset - reset host port via ATA SRST
1947 * @ap: port to reset
1948 * @verbose: fail verbosely
1949 * @classes: resulting classes of attached devices
1950 *
1951 * Reset host port using ATA SRST. This function is to be used
1952 * as standard callback for ata_drive_*_reset() functions.
1953 *
1954 * LOCKING:
1955 * Kernel thread context (may sleep)
1956 *
1957 * RETURNS:
1958 * 0 on success, -errno otherwise.
1959 */
1960int ata_std_softreset(struct ata_port *ap, int verbose, unsigned int *classes)
1961{
1962 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1963 unsigned int devmask = 0, err_mask;
1964 u8 err;
1965
1966 DPRINTK("ENTER\n");
1967
3a39746a
TH		 1968 if (ap->ops->scr_read && !sata_dev_present(ap)) {
1969 classes[0] = ATA_DEV_NONE;
1970 goto out;
1971 }
1972
c2bd5804
TH		 1973 /* determine if device 0/1 are present */
1974 if (ata_devchk(ap, 0))
1975 devmask |= (1 << 0);
1976 if (slave_possible && ata_devchk(ap, 1))
1977 devmask |= (1 << 1);
1978
c2bd5804
TH		 1979 /* select device 0 again */
1980 ap->ops->dev_select(ap, 0);
1981
1982 /* issue bus reset */
1983 DPRINTK("about to softreset, devmask=%x\n", devmask);
1984 err_mask = ata_bus_softreset(ap, devmask);
1985 if (err_mask) {
1986 if (verbose)
1987 printk(KERN_ERR "ata%u: SRST failed (err_mask=0x%x)\n",
1988 ap->id, err_mask);
1989 else
1990 DPRINTK("EXIT, softreset failed (err_mask=0x%x)\n",
1991 err_mask);
1992 return -EIO;
1993 }
1994
1995 /* determine by signature whether we have ATA or ATAPI devices */
1996 classes[0] = ata_dev_try_classify(ap, 0, &err);
1997 if (slave_possible && err != 0x81)
1998 classes[1] = ata_dev_try_classify(ap, 1, &err);
1999
3a39746a 2000 out:
c2bd5804
TH		 2001 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2002 return 0;
2003}
2004
2005/**
2006 * sata_std_hardreset - reset host port via SATA phy reset
2007 * @ap: port to reset
2008 * @verbose: fail verbosely
2009 * @class: resulting class of attached device
2010 *
2011 * SATA phy-reset host port using DET bits of SControl register.
2012 * This function is to be used as standard callback for
2013 * ata_drive_*_reset().
2014 *
2015 * LOCKING:
2016 * Kernel thread context (may sleep)
2017 *
2018 * RETURNS:
2019 * 0 on success, -errno otherwise.
2020 */
2021int sata_std_hardreset(struct ata_port *ap, int verbose, unsigned int *class)
2022{
c2bd5804
TH		 2023 DPRINTK("ENTER\n");
2024
2025 /* Issue phy wake/reset */
2026 scr_write_flush(ap, SCR_CONTROL, 0x301);
2027
2028 /*
2029 * Couldn't find anything in SATA I/II specs, but AHCI-1.1
2030 * 10.4.2 says at least 1 ms.
2031 */
2032 msleep(1);
2033
7a7921e8
TH		 2034 /* Bring phy back */
2035 sata_phy_resume(ap);
c2bd5804 2036
c2bd5804
TH		 2037 /* TODO: phy layer with polling, timeouts, etc. */
2038 if (!sata_dev_present(ap)) {
2039 *class = ATA_DEV_NONE;
2040 DPRINTK("EXIT, link offline\n");
2041 return 0;
2042 }
2043
2044 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
2045 if (verbose)
2046 printk(KERN_ERR "ata%u: COMRESET failed "
2047 "(device not ready)\n", ap->id);
2048 else
2049 DPRINTK("EXIT, device not ready\n");
2050 return -EIO;
2051 }
2052
3a39746a
TH		 2053 ap->ops->dev_select(ap, 0); /* probably unnecessary */
2054
c2bd5804
TH		 2055 *class = ata_dev_try_classify(ap, 0, NULL);
2056
2057 DPRINTK("EXIT, class=%u\n", *class);
2058 return 0;
2059}
2060
2061/**
2062 * ata_std_postreset - standard postreset callback
2063 * @ap: the target ata_port
2064 * @classes: classes of attached devices
2065 *
2066 * This function is invoked after a successful reset. Note that
2067 * the device might have been reset more than once using
2068 * different reset methods before postreset is invoked.
2069 * postreset is also reponsible for setting cable type.
2070 *
2071 * This function is to be used as standard callback for
2072 * ata_drive_*_reset().
2073 *
2074 * LOCKING:
2075 * Kernel thread context (may sleep)
2076 */
2077void ata_std_postreset(struct ata_port *ap, unsigned int *classes)
2078{
2079 DPRINTK("ENTER\n");
2080
2081 /* set cable type */
2082 if (ap->cbl == ATA_CBL_NONE && ap->flags & ATA_FLAG_SATA)
2083 ap->cbl = ATA_CBL_SATA;
2084
2085 /* print link status */
2086 if (ap->cbl == ATA_CBL_SATA)
2087 sata_print_link_status(ap);
2088
3a39746a
TH		 2089 /* re-enable interrupts */
2090 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2091 ata_irq_on(ap);
c2bd5804
TH		 2092
2093 /* is double-select really necessary? */
2094 if (classes[0] != ATA_DEV_NONE)
2095 ap->ops->dev_select(ap, 1);
2096 if (classes[1] != ATA_DEV_NONE)
2097 ap->ops->dev_select(ap, 0);
2098
3a39746a
TH		 2099 /* bail out if no device is present */
2100 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2101 DPRINTK("EXIT, no device\n");
2102 return;
2103 }
2104
2105 /* set up device control */
2106 if (ap->ioaddr.ctl_addr) {
2107 if (ap->flags & ATA_FLAG_MMIO)
2108 writeb(ap->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
2109 else
2110 outb(ap->ctl, ap->ioaddr.ctl_addr);
2111 }
c2bd5804
TH		 2112
2113 DPRINTK("EXIT\n");
2114}
2115
2116/**
2117 * ata_std_probe_reset - standard probe reset method
2118 * @ap: prot to perform probe-reset
2119 * @classes: resulting classes of attached devices
2120 *
2121 * The stock off-the-shelf ->probe_reset method.
2122 *
2123 * LOCKING:
2124 * Kernel thread context (may sleep)
2125 *
2126 * RETURNS:
2127 * 0 on success, -errno otherwise.
2128 */
2129int ata_std_probe_reset(struct ata_port *ap, unsigned int *classes)
2130{
2131 ata_reset_fn_t hardreset;
2132
2133 hardreset = NULL;
b911fc3a 2134 if (ap->flags & ATA_FLAG_SATA && ap->ops->scr_read)
c2bd5804
TH		 2135 hardreset = sata_std_hardreset;
2136
8a19ac89 2137 return ata_drive_probe_reset(ap, ata_std_probeinit,
7944ea95 2138 ata_std_softreset, hardreset,
c2bd5804
TH		 2139 ata_std_postreset, classes);
2140}
2141
a62c0fc5
TH		 2142static int do_probe_reset(struct ata_port *ap, ata_reset_fn_t reset,
2143 ata_postreset_fn_t postreset,
2144 unsigned int *classes)
2145{
2146 int i, rc;
2147
2148 for (i = 0; i < ATA_MAX_DEVICES; i++)
2149 classes[i] = ATA_DEV_UNKNOWN;
2150
2151 rc = reset(ap, 0, classes);
2152 if (rc)
2153 return rc;
2154
2155 /* If any class isn't ATA_DEV_UNKNOWN, consider classification
2156 * is complete and convert all ATA_DEV_UNKNOWN to
2157 * ATA_DEV_NONE.
2158 */
2159 for (i = 0; i < ATA_MAX_DEVICES; i++)
2160 if (classes[i] != ATA_DEV_UNKNOWN)
2161 break;
2162
2163 if (i < ATA_MAX_DEVICES)
2164 for (i = 0; i < ATA_MAX_DEVICES; i++)
2165 if (classes[i] == ATA_DEV_UNKNOWN)
2166 classes[i] = ATA_DEV_NONE;
2167
2168 if (postreset)
2169 postreset(ap, classes);
2170
2171 return classes[0] != ATA_DEV_UNKNOWN ? 0 : -ENODEV;
2172}
2173
2174/**
2175 * ata_drive_probe_reset - Perform probe reset with given methods
2176 * @ap: port to reset
7944ea95 2177 * @probeinit: probeinit method (can be NULL)
a62c0fc5
TH		 2178 * @softreset: softreset method (can be NULL)
2179 * @hardreset: hardreset method (can be NULL)
2180 * @postreset: postreset method (can be NULL)
2181 * @classes: resulting classes of attached devices
2182 *
2183 * Reset the specified port and classify attached devices using
2184 * given methods. This function prefers softreset but tries all
2185 * possible reset sequences to reset and classify devices. This
2186 * function is intended to be used for constructing ->probe_reset
2187 * callback by low level drivers.
2188 *
2189 * Reset methods should follow the following rules.
2190 *
2191 * - Return 0 on sucess, -errno on failure.
2192 * - If classification is supported, fill classes[] with
2193 * recognized class codes.
2194 * - If classification is not supported, leave classes[] alone.
2195 * - If verbose is non-zero, print error message on failure;
2196 * otherwise, shut up.
2197 *
2198 * LOCKING:
2199 * Kernel thread context (may sleep)
2200 *
2201 * RETURNS:
2202 * 0 on success, -EINVAL if no reset method is avaliable, -ENODEV
2203 * if classification fails, and any error code from reset
2204 * methods.
2205 */
7944ea95 2206int ata_drive_probe_reset(struct ata_port *ap, ata_probeinit_fn_t probeinit,
a62c0fc5
TH		 2207 ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
2208 ata_postreset_fn_t postreset, unsigned int *classes)
2209{
2210 int rc = -EINVAL;
2211
7944ea95
TH		 2212 if (probeinit)
2213 probeinit(ap);
2214
a62c0fc5
TH		 2215 if (softreset) {
2216 rc = do_probe_reset(ap, softreset, postreset, classes);
2217 if (rc == 0)
2218 return 0;
2219 }
2220
2221 if (!hardreset)
2222 return rc;
2223
2224 rc = do_probe_reset(ap, hardreset, postreset, classes);
2225 if (rc == 0 || rc != -ENODEV)
2226 return rc;
2227
2228 if (softreset)
2229 rc = do_probe_reset(ap, softreset, postreset, classes);
2230
2231 return rc;
2232}
2233
057ace5e
JG		 2234static void ata_pr_blacklisted(const struct ata_port *ap,
2235 const struct ata_device *dev)
1da177e4
LT		 2236{
2237 printk(KERN_WARNING "ata%u: dev %u is on DMA blacklist, disabling DMA\n",
2238 ap->id, dev->devno);
2239}
2240
98ac62de 2241static const char * const ata_dma_blacklist [] = {
1da177e4
LT		 2242 "WDC AC11000H",
2243 "WDC AC22100H",
2244 "WDC AC32500H",
2245 "WDC AC33100H",
2246 "WDC AC31600H",
2247 "WDC AC32100H",
2248 "WDC AC23200L",
2249 "Compaq CRD-8241B",
2250 "CRD-8400B",
2251 "CRD-8480B",
2252 "CRD-8482B",
2253 "CRD-84",
2254 "SanDisk SDP3B",
2255 "SanDisk SDP3B-64",
2256 "SANYO CD-ROM CRD",
2257 "HITACHI CDR-8",
2258 "HITACHI CDR-8335",
2259 "HITACHI CDR-8435",
2260 "Toshiba CD-ROM XM-6202B",
e922256a 2261 "TOSHIBA CD-ROM XM-1702BC",
1da177e4
LT		 2262 "CD-532E-A",
2263 "E-IDE CD-ROM CR-840",
2264 "CD-ROM Drive/F5A",
2265 "WPI CDD-820",
2266 "SAMSUNG CD-ROM SC-148C",
2267 "SAMSUNG CD-ROM SC",
2268 "SanDisk SDP3B-64",
1da177e4
LT		 2269 "ATAPI CD-ROM DRIVE 40X MAXIMUM",
2270 "_NEC DV5800A",
2271};
2272
057ace5e 2273static int ata_dma_blacklisted(const struct ata_device *dev)
1da177e4
LT		 2274{
2275 unsigned char model_num[40];
2276 char *s;
2277 unsigned int len;
2278 int i;
2279
2280 ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
2281 sizeof(model_num));
2282 s = &model_num[0];
2283 len = strnlen(s, sizeof(model_num));
2284
2285 /* ATAPI specifies that empty space is blank-filled; remove blanks */
2286 while ((len > 0) && (s[len - 1] == ' ')) {
2287 len--;
2288 s[len] = 0;
2289 }
2290
2291 for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i++)
2292 if (!strncmp(ata_dma_blacklist[i], s, len))
2293 return 1;
2294
2295 return 0;
2296}
2297
057ace5e 2298static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift)
1da177e4 2299{
057ace5e 2300 const struct ata_device *master, *slave;
1da177e4
LT		 2301 unsigned int mask;
2302
2303 master = &ap->device[0];
2304 slave = &ap->device[1];
2305
a4631474 2306 WARN_ON(!ata_dev_present(master) && !ata_dev_present(slave));
1da177e4
LT		 2307
2308 if (shift == ATA_SHIFT_UDMA) {
2309 mask = ap->udma_mask;
2310 if (ata_dev_present(master)) {
2311 mask &= (master->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2312 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2313 mask = 0;
2314 ata_pr_blacklisted(ap, master);
2315 }
2316 }
2317 if (ata_dev_present(slave)) {
2318 mask &= (slave->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2319 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2320 mask = 0;
2321 ata_pr_blacklisted(ap, slave);
2322 }
2323 }
2324 }
2325 else if (shift == ATA_SHIFT_MWDMA) {
2326 mask = ap->mwdma_mask;
2327 if (ata_dev_present(master)) {
2328 mask &= (master->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2329 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2330 mask = 0;
2331 ata_pr_blacklisted(ap, master);
2332 }
2333 }
2334 if (ata_dev_present(slave)) {
2335 mask &= (slave->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2336 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2337 mask = 0;
2338 ata_pr_blacklisted(ap, slave);
2339 }
2340 }
2341 }
2342 else if (shift == ATA_SHIFT_PIO) {
2343 mask = ap->pio_mask;
2344 if (ata_dev_present(master)) {
2345 /* spec doesn't return explicit support for
2346 * PIO0-2, so we fake it
2347 */
2348 u16 tmp_mode = master->id[ATA_ID_PIO_MODES] & 0x03;
2349 tmp_mode <<= 3;
2350 tmp_mode |= 0x7;
2351 mask &= tmp_mode;
2352 }
2353 if (ata_dev_present(slave)) {
2354 /* spec doesn't return explicit support for
2355 * PIO0-2, so we fake it
2356 */
2357 u16 tmp_mode = slave->id[ATA_ID_PIO_MODES] & 0x03;
2358 tmp_mode <<= 3;
2359 tmp_mode |= 0x7;
2360 mask &= tmp_mode;
2361 }
2362 }
2363 else {
2364 mask = 0xffffffff; /* shut up compiler warning */
2365 BUG();
2366 }
2367
2368 return mask;
2369}
2370
2371/* find greatest bit */
2372static int fgb(u32 bitmap)
2373{
2374 unsigned int i;
2375 int x = -1;
2376
2377 for (i = 0; i < 32; i++)
2378 if (bitmap & (1 << i))
2379 x = i;
2380
2381 return x;
2382}
2383
2384/**
2385 * ata_choose_xfer_mode - attempt to find best transfer mode
2386 * @ap: Port for which an xfer mode will be selected
2387 * @xfer_mode_out: (output) SET FEATURES - XFER MODE code
2388 * @xfer_shift_out: (output) bit shift that selects this mode
2389 *
0cba632b
JG		 2390 * Based on host and device capabilities, determine the
2391 * maximum transfer mode that is amenable to all.
2392 *
1da177e4 2393 * LOCKING:
0cba632b 2394 * PCI/etc. bus probe sem.
1da177e4
LT		 2395 *
2396 * RETURNS:
2397 * Zero on success, negative on error.
2398 */
2399
057ace5e 2400static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 2401 u8 *xfer_mode_out,
2402 unsigned int *xfer_shift_out)
2403{
2404 unsigned int mask, shift;
2405 int x, i;
2406
2407 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++) {
2408 shift = xfer_mode_classes[i].shift;
2409 mask = ata_get_mode_mask(ap, shift);
2410
2411 x = fgb(mask);
2412 if (x >= 0) {
2413 *xfer_mode_out = xfer_mode_classes[i].base + x;
2414 *xfer_shift_out = shift;
2415 return 0;
2416 }
2417 }
2418
2419 return -1;
2420}
2421
2422/**
2423 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
2424 * @ap: Port associated with device @dev
2425 * @dev: Device to which command will be sent
2426 *
780a87f7
JG		 2427 * Issue SET FEATURES - XFER MODE command to device @dev
2428 * on port @ap.
2429 *
1da177e4 2430 * LOCKING:
0cba632b 2431 * PCI/etc. bus probe sem.
1da177e4
LT		 2432 */
2433
2434static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev)
2435{
a0123703 2436 struct ata_taskfile tf;
1da177e4
LT		 2437
2438 /* set up set-features taskfile */
2439 DPRINTK("set features - xfer mode\n");
2440
a0123703
TH		 2441 ata_tf_init(ap, &tf, dev->devno);
2442 tf.command = ATA_CMD_SET_FEATURES;
2443 tf.feature = SETFEATURES_XFER;
2444 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2445 tf.protocol = ATA_PROT_NODATA;
2446 tf.nsect = dev->xfer_mode;
1da177e4 2447
a0123703
TH		 2448 if (ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0)) {
2449 printk(KERN_ERR "ata%u: failed to set xfermode, disabled\n",
2450 ap->id);
1da177e4 2451 ata_port_disable(ap);
a0123703 2452 }
1da177e4
LT		 2453
2454 DPRINTK("EXIT\n");
2455}
2456
59a10b17
AL		 2457/**
2458 * ata_dev_reread_id - Reread the device identify device info
2459 * @ap: port where the device is
2460 * @dev: device to reread the identify device info
2461 *
2462 * LOCKING:
2463 */
2464
2465static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev)
2466{
a0123703 2467 struct ata_taskfile tf;
59a10b17 2468
a0123703 2469 ata_tf_init(ap, &tf, dev->devno);
59a10b17
AL		 2470
2471 if (dev->class == ATA_DEV_ATA) {
a0123703 2472 tf.command = ATA_CMD_ID_ATA;
59a10b17
AL		 2473 DPRINTK("do ATA identify\n");
2474 } else {
a0123703 2475 tf.command = ATA_CMD_ID_ATAPI;
59a10b17
AL		 2476 DPRINTK("do ATAPI identify\n");
2477 }
2478
a0123703
TH		 2479 tf.flags |= ATA_TFLAG_DEVICE;
2480 tf.protocol = ATA_PROT_PIO;
59a10b17 2481
a0123703
TH		 2482 if (ata_exec_internal(ap, dev, &tf, DMA_FROM_DEVICE,
2483 dev->id, sizeof(dev->id)))
59a10b17
AL		 2484 goto err_out;
2485
59a10b17
AL		 2486 swap_buf_le16(dev->id, ATA_ID_WORDS);
2487
2488 ata_dump_id(dev);
2489
2490 DPRINTK("EXIT\n");
2491
2492 return;
2493err_out:
a0123703 2494 printk(KERN_ERR "ata%u: failed to reread ID, disabled\n", ap->id);
59a10b17
AL		 2495 ata_port_disable(ap);
2496}
2497
8bf62ece
AL		 2498/**
2499 * ata_dev_init_params - Issue INIT DEV PARAMS command
2500 * @ap: Port associated with device @dev
2501 * @dev: Device to which command will be sent
2502 *
2503 * LOCKING:
2504 */
2505
2506static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev)
2507{
a0123703 2508 struct ata_taskfile tf;
8bf62ece
AL		 2509 u16 sectors = dev->id[6];
2510 u16 heads = dev->id[3];
2511
2512 /* Number of sectors per track 1-255. Number of heads 1-16 */
2513 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
2514 return;
2515
2516 /* set up init dev params taskfile */
2517 DPRINTK("init dev params \n");
2518
a0123703
TH		 2519 ata_tf_init(ap, &tf, dev->devno);
2520 tf.command = ATA_CMD_INIT_DEV_PARAMS;
2521 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2522 tf.protocol = ATA_PROT_NODATA;
2523 tf.nsect = sectors;
2524 tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
8bf62ece 2525
a0123703
TH		 2526 if (ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0)) {
2527 printk(KERN_ERR "ata%u: failed to init parameters, disabled\n",
2528 ap->id);
8bf62ece 2529 ata_port_disable(ap);
a0123703 2530 }
8bf62ece
AL		 2531
2532 DPRINTK("EXIT\n");
2533}
2534
1da177e4 2535/**
0cba632b
JG		 2536 * ata_sg_clean - Unmap DMA memory associated with command
2537 * @qc: Command containing DMA memory to be released
2538 *
2539 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT		 2540 *
2541 * LOCKING:
0cba632b 2542 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2543 */
2544
2545static void ata_sg_clean(struct ata_queued_cmd *qc)
2546{
2547 struct ata_port *ap = qc->ap;
cedc9a47 2548 struct scatterlist *sg = qc->__sg;
1da177e4 2549 int dir = qc->dma_dir;
cedc9a47 2550 void *pad_buf = NULL;
1da177e4 2551
a4631474
TH		 2552 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
2553 WARN_ON(sg == NULL);
1da177e4
LT		 2554
2555 if (qc->flags & ATA_QCFLAG_SINGLE)
a4631474 2556 WARN_ON(qc->n_elem != 1);
1da177e4 2557
2c13b7ce 2558 VPRINTK("unmapping %u sg elements\n", qc->n_elem);
1da177e4 2559
cedc9a47
JG		 2560 /* if we padded the buffer out to 32-bit bound, and data
2561 * xfer direction is from-device, we must copy from the
2562 * pad buffer back into the supplied buffer
2563 */
2564 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
2565 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2566
2567 if (qc->flags & ATA_QCFLAG_SG) {
e1410f2d
JG		 2568 if (qc->n_elem)
2569 dma_unmap_sg(ap->host_set->dev, sg, qc->n_elem, dir);
cedc9a47
JG		 2570 /* restore last sg */
2571 sg[qc->orig_n_elem - 1].length += qc->pad_len;
2572 if (pad_buf) {
2573 struct scatterlist *psg = &qc->pad_sgent;
2574 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2575 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
dfa15988 2576 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 2577 }
2578 } else {
e1410f2d
JG		 2579 if (sg_dma_len(&sg[0]) > 0)
2580 dma_unmap_single(ap->host_set->dev,
2581 sg_dma_address(&sg[0]), sg_dma_len(&sg[0]),
2582 dir);
cedc9a47
JG		 2583 /* restore sg */
2584 sg->length += qc->pad_len;
2585 if (pad_buf)
2586 memcpy(qc->buf_virt + sg->length - qc->pad_len,
2587 pad_buf, qc->pad_len);
2588 }
1da177e4
LT		 2589
2590 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 2591 qc->__sg = NULL;
1da177e4
LT		 2592}
2593
2594/**
2595 * ata_fill_sg - Fill PCI IDE PRD table
2596 * @qc: Metadata associated with taskfile to be transferred
2597 *
780a87f7
JG		 2598 * Fill PCI IDE PRD (scatter-gather) table with segments
2599 * associated with the current disk command.
2600 *
1da177e4 2601 * LOCKING:
780a87f7 2602 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2603 *
2604 */
2605static void ata_fill_sg(struct ata_queued_cmd *qc)
2606{
1da177e4 2607 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2608 struct scatterlist *sg;
2609 unsigned int idx;
1da177e4 2610
a4631474
TH		 2611 WARN_ON(qc->__sg == NULL);
2612 WARN_ON(qc->n_elem == 0);
1da177e4
LT		 2613
2614 idx = 0;
cedc9a47 2615 ata_for_each_sg(sg, qc) {
1da177e4
LT		 2616 u32 addr, offset;
2617 u32 sg_len, len;
2618
2619 /* determine if physical DMA addr spans 64K boundary.
2620 * Note h/w doesn't support 64-bit, so we unconditionally
2621 * truncate dma_addr_t to u32.
2622 */
2623 addr = (u32) sg_dma_address(sg);
2624 sg_len = sg_dma_len(sg);
2625
2626 while (sg_len) {
2627 offset = addr & 0xffff;
2628 len = sg_len;
2629 if ((offset + sg_len) > 0x10000)
2630 len = 0x10000 - offset;
2631
2632 ap->prd[idx].addr = cpu_to_le32(addr);
2633 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
2634 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
2635
2636 idx++;
2637 sg_len -= len;
2638 addr += len;
2639 }
2640 }
2641
2642 if (idx)
2643 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2644}
2645/**
2646 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
2647 * @qc: Metadata associated with taskfile to check
2648 *
780a87f7
JG		 2649 * Allow low-level driver to filter ATA PACKET commands, returning
2650 * a status indicating whether or not it is OK to use DMA for the
2651 * supplied PACKET command.
2652 *
1da177e4 2653 * LOCKING:
0cba632b
JG		 2654 * spin_lock_irqsave(host_set lock)
2655 *
1da177e4
LT		 2656 * RETURNS: 0 when ATAPI DMA can be used
2657 * nonzero otherwise
2658 */
2659int ata_check_atapi_dma(struct ata_queued_cmd *qc)
2660{
2661 struct ata_port *ap = qc->ap;
2662 int rc = 0; /* Assume ATAPI DMA is OK by default */
2663
2664 if (ap->ops->check_atapi_dma)
2665 rc = ap->ops->check_atapi_dma(qc);
2666
2667 return rc;
2668}
2669/**
2670 * ata_qc_prep - Prepare taskfile for submission
2671 * @qc: Metadata associated with taskfile to be prepared
2672 *
780a87f7
JG		 2673 * Prepare ATA taskfile for submission.
2674 *
1da177e4
LT		 2675 * LOCKING:
2676 * spin_lock_irqsave(host_set lock)
2677 */
2678void ata_qc_prep(struct ata_queued_cmd *qc)
2679{
2680 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2681 return;
2682
2683 ata_fill_sg(qc);
2684}
2685
0cba632b
JG		 2686/**
2687 * ata_sg_init_one - Associate command with memory buffer
2688 * @qc: Command to be associated
2689 * @buf: Memory buffer
2690 * @buflen: Length of memory buffer, in bytes.
2691 *
2692 * Initialize the data-related elements of queued_cmd @qc
2693 * to point to a single memory buffer, @buf of byte length @buflen.
2694 *
2695 * LOCKING:
2696 * spin_lock_irqsave(host_set lock)
2697 */
2698
1da177e4
LT		 2699void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
2700{
2701 struct scatterlist *sg;
2702
2703 qc->flags |= ATA_QCFLAG_SINGLE;
2704
2705 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 2706 qc->__sg = &qc->sgent;
1da177e4 2707 qc->n_elem = 1;
cedc9a47 2708 qc->orig_n_elem = 1;
1da177e4
LT		 2709 qc->buf_virt = buf;
2710
cedc9a47 2711 sg = qc->__sg;
f0612bbc 2712 sg_init_one(sg, buf, buflen);
1da177e4
LT		 2713}
2714
0cba632b
JG		 2715/**
2716 * ata_sg_init - Associate command with scatter-gather table.
2717 * @qc: Command to be associated
2718 * @sg: Scatter-gather table.
2719 * @n_elem: Number of elements in s/g table.
2720 *
2721 * Initialize the data-related elements of queued_cmd @qc
2722 * to point to a scatter-gather table @sg, containing @n_elem
2723 * elements.
2724 *
2725 * LOCKING:
2726 * spin_lock_irqsave(host_set lock)
2727 */
2728
1da177e4
LT		 2729void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
2730 unsigned int n_elem)
2731{
2732 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 2733 qc->__sg = sg;
1da177e4 2734 qc->n_elem = n_elem;
cedc9a47 2735 qc->orig_n_elem = n_elem;
1da177e4
LT		 2736}
2737
2738/**
0cba632b
JG		 2739 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
2740 * @qc: Command with memory buffer to be mapped.
2741 *
2742 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT		 2743 *
2744 * LOCKING:
2745 * spin_lock_irqsave(host_set lock)
2746 *
2747 * RETURNS:
0cba632b 2748 * Zero on success, negative on error.
1da177e4
LT		 2749 */
2750
2751static int ata_sg_setup_one(struct ata_queued_cmd *qc)
2752{
2753 struct ata_port *ap = qc->ap;
2754 int dir = qc->dma_dir;
cedc9a47 2755 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 2756 dma_addr_t dma_address;
2757
cedc9a47
JG		 2758 /* we must lengthen transfers to end on a 32-bit boundary */
2759 qc->pad_len = sg->length & 3;
2760 if (qc->pad_len) {
2761 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2762 struct scatterlist *psg = &qc->pad_sgent;
2763
a4631474 2764 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 2765
2766 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2767
2768 if (qc->tf.flags & ATA_TFLAG_WRITE)
2769 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
2770 qc->pad_len);
2771
2772 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2773 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2774 /* trim sg */
2775 sg->length -= qc->pad_len;
2776
2777 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
2778 sg->length, qc->pad_len);
2779 }
2780
e1410f2d
JG		 2781 if (!sg->length) {
2782 sg_dma_address(sg) = 0;
2783 goto skip_map;
2784 }
2785
1da177e4 2786 dma_address = dma_map_single(ap->host_set->dev, qc->buf_virt,
32529e01 2787 sg->length, dir);
537a95d9
TH		 2788 if (dma_mapping_error(dma_address)) {
2789 /* restore sg */
2790 sg->length += qc->pad_len;
1da177e4 2791 return -1;
537a95d9 2792 }
1da177e4
LT		 2793
2794 sg_dma_address(sg) = dma_address;
e1410f2d 2795skip_map:
32529e01 2796 sg_dma_len(sg) = sg->length;
1da177e4
LT		 2797
2798 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
2799 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
2800
2801 return 0;
2802}
2803
2804/**
0cba632b
JG		 2805 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
2806 * @qc: Command with scatter-gather table to be mapped.
2807 *
2808 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT		 2809 *
2810 * LOCKING:
2811 * spin_lock_irqsave(host_set lock)
2812 *
2813 * RETURNS:
0cba632b 2814 * Zero on success, negative on error.
1da177e4
LT		 2815 *
2816 */
2817
2818static int ata_sg_setup(struct ata_queued_cmd *qc)
2819{
2820 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2821 struct scatterlist *sg = qc->__sg;
2822 struct scatterlist *lsg = &sg[qc->n_elem - 1];
e1410f2d 2823 int n_elem, pre_n_elem, dir, trim_sg = 0;
1da177e4
LT		 2824
2825 VPRINTK("ENTER, ata%u\n", ap->id);
a4631474 2826 WARN_ON(!(qc->flags & ATA_QCFLAG_SG));
1da177e4 2827
cedc9a47
JG		 2828 /* we must lengthen transfers to end on a 32-bit boundary */
2829 qc->pad_len = lsg->length & 3;
2830 if (qc->pad_len) {
2831 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2832 struct scatterlist *psg = &qc->pad_sgent;
2833 unsigned int offset;
2834
a4631474 2835 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 2836
2837 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2838
2839 /*
2840 * psg->page/offset are used to copy to-be-written
2841 * data in this function or read data in ata_sg_clean.
2842 */
2843 offset = lsg->offset + lsg->length - qc->pad_len;
2844 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
2845 psg->offset = offset_in_page(offset);
2846
2847 if (qc->tf.flags & ATA_TFLAG_WRITE) {
2848 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2849 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
dfa15988 2850 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 2851 }
2852
2853 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2854 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2855 /* trim last sg */
2856 lsg->length -= qc->pad_len;
e1410f2d
JG		 2857 if (lsg->length == 0)
2858 trim_sg = 1;
cedc9a47
JG		 2859
2860 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
2861 qc->n_elem - 1, lsg->length, qc->pad_len);
2862 }
2863
e1410f2d
JG		 2864 pre_n_elem = qc->n_elem;
2865 if (trim_sg && pre_n_elem)
2866 pre_n_elem--;
2867
2868 if (!pre_n_elem) {
2869 n_elem = 0;
2870 goto skip_map;
2871 }
2872
1da177e4 2873 dir = qc->dma_dir;
e1410f2d 2874 n_elem = dma_map_sg(ap->host_set->dev, sg, pre_n_elem, dir);
537a95d9
TH		 2875 if (n_elem < 1) {
2876 /* restore last sg */
2877 lsg->length += qc->pad_len;
1da177e4 2878 return -1;
537a95d9 2879 }
1da177e4
LT		 2880
2881 DPRINTK("%d sg elements mapped\n", n_elem);
2882
e1410f2d 2883skip_map:
1da177e4
LT		 2884 qc->n_elem = n_elem;
2885
2886 return 0;
2887}
2888
40e8c82c
TH		 2889/**
2890 * ata_poll_qc_complete - turn irq back on and finish qc
2891 * @qc: Command to complete
8e8b77dd 2892 * @err_mask: ATA status register content
40e8c82c
TH		 2893 *
2894 * LOCKING:
2895 * None. (grabs host lock)
2896 */
2897
a22e2eb0 2898void ata_poll_qc_complete(struct ata_queued_cmd *qc)
40e8c82c
TH		 2899{
2900 struct ata_port *ap = qc->ap;
b8f6153e 2901 unsigned long flags;
40e8c82c 2902
b8f6153e 2903 spin_lock_irqsave(&ap->host_set->lock, flags);
40e8c82c 2904 ata_irq_on(ap);
a22e2eb0 2905 ata_qc_complete(qc);
b8f6153e 2906 spin_unlock_irqrestore(&ap->host_set->lock, flags);
40e8c82c
TH		 2907}
2908
1da177e4 2909/**
c893a3ae 2910 * ata_pio_poll - poll using PIO, depending on current state
6f0ef4fa 2911 * @ap: the target ata_port
1da177e4
LT		 2912 *
2913 * LOCKING:
0cba632b 2914 * None. (executing in kernel thread context)
1da177e4
LT		 2915 *
2916 * RETURNS:
6f0ef4fa 2917 * timeout value to use
1da177e4
LT		 2918 */
2919
2920static unsigned long ata_pio_poll(struct ata_port *ap)
2921{
c14b8331 2922 struct ata_queued_cmd *qc;
1da177e4 2923 u8 status;
14be71f4
AL		 2924 unsigned int poll_state = HSM_ST_UNKNOWN;
2925 unsigned int reg_state = HSM_ST_UNKNOWN;
14be71f4 2926
c14b8331 2927 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 2928 WARN_ON(qc == NULL);
c14b8331 2929
14be71f4
AL		 2930 switch (ap->hsm_task_state) {
2931 case HSM_ST:
2932 case HSM_ST_POLL:
2933 poll_state = HSM_ST_POLL;
2934 reg_state = HSM_ST;
1da177e4 2935 break;
14be71f4
AL		 2936 case HSM_ST_LAST:
2937 case HSM_ST_LAST_POLL:
2938 poll_state = HSM_ST_LAST_POLL;
2939 reg_state = HSM_ST_LAST;
1da177e4
LT		 2940 break;
2941 default:
2942 BUG();
2943 break;
2944 }
2945
2946 status = ata_chk_status(ap);
2947 if (status & ATA_BUSY) {
2948 if (time_after(jiffies, ap->pio_task_timeout)) {
11a56d24 2949 qc->err_mask |= AC_ERR_TIMEOUT;
7c398335 2950 ap->hsm_task_state = HSM_ST_TMOUT;
1da177e4
LT		 2951 return 0;
2952 }
14be71f4 2953 ap->hsm_task_state = poll_state;
1da177e4
LT		 2954 return ATA_SHORT_PAUSE;
2955 }
2956
14be71f4 2957 ap->hsm_task_state = reg_state;
1da177e4
LT		 2958 return 0;
2959}
2960
2961/**
6f0ef4fa
RD		 2962 * ata_pio_complete - check if drive is busy or idle
2963 * @ap: the target ata_port
1da177e4
LT		 2964 *
2965 * LOCKING:
0cba632b 2966 * None. (executing in kernel thread context)
7fb6ec28
JG		 2967 *
2968 * RETURNS:
fbcdd80b
AL		 2969 * Zero if qc completed.
2970 * Non-zero if has next.
1da177e4
LT		 2971 */
2972
7fb6ec28 2973static int ata_pio_complete (struct ata_port *ap)
1da177e4
LT		 2974{
2975 struct ata_queued_cmd *qc;
2976 u8 drv_stat;
2977
2978 /*
31433ea3
AC		 2979 * This is purely heuristic. This is a fast path. Sometimes when
2980 * we enter, BSY will be cleared in a chk-status or two. If not,
2981 * the drive is probably seeking or something. Snooze for a couple
2982 * msecs, then chk-status again. If still busy, fall back to
07f6f7d0 2983 * HSM_ST_LAST_POLL state.
1da177e4 2984 */
fe79e683
AL		 2985 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
2986 if (drv_stat & ATA_BUSY) {
1da177e4 2987 msleep(2);
fe79e683
AL		 2988 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
2989 if (drv_stat & ATA_BUSY) {
14be71f4 2990 ap->hsm_task_state = HSM_ST_LAST_POLL;
1da177e4 2991 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
fbcdd80b 2992 return 1;
1da177e4
LT		 2993 }
2994 }
2995
c14b8331 2996 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 2997 WARN_ON(qc == NULL);
c14b8331 2998
1da177e4
LT		 2999 drv_stat = ata_wait_idle(ap);
3000 if (!ata_ok(drv_stat)) {
1c848984 3001 qc->err_mask |= __ac_err_mask(drv_stat);
14be71f4 3002 ap->hsm_task_state = HSM_ST_ERR;
fbcdd80b 3003 return 1;
1da177e4
LT		 3004 }
3005
14be71f4 3006 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3007
a4631474 3008 WARN_ON(qc->err_mask);
a22e2eb0 3009 ata_poll_qc_complete(qc);
7fb6ec28
JG		 3010
3011 /* another command may start at this point */
3012
fbcdd80b 3013 return 0;
1da177e4
LT		 3014}
3015
0baab86b
EF		 3016
3017/**
c893a3ae 3018 * swap_buf_le16 - swap halves of 16-bit words in place
0baab86b
EF		 3019 * @buf: Buffer to swap
3020 * @buf_words: Number of 16-bit words in buffer.
3021 *
3022 * Swap halves of 16-bit words if needed to convert from
3023 * little-endian byte order to native cpu byte order, or
3024 * vice-versa.
3025 *
3026 * LOCKING:
6f0ef4fa 3027 * Inherited from caller.
0baab86b 3028 */
1da177e4
LT		 3029void swap_buf_le16(u16 *buf, unsigned int buf_words)
3030{
3031#ifdef __BIG_ENDIAN
3032 unsigned int i;
3033
3034 for (i = 0; i < buf_words; i++)
3035 buf[i] = le16_to_cpu(buf[i]);
3036#endif /* __BIG_ENDIAN */
3037}
3038
6ae4cfb5
AL		 3039/**
3040 * ata_mmio_data_xfer - Transfer data by MMIO
3041 * @ap: port to read/write
3042 * @buf: data buffer
3043 * @buflen: buffer length
344babaa 3044 * @write_data: read/write
6ae4cfb5
AL		 3045 *
3046 * Transfer data from/to the device data register by MMIO.
3047 *
3048 * LOCKING:
3049 * Inherited from caller.
6ae4cfb5
AL		 3050 */
3051
1da177e4
LT		 3052static void ata_mmio_data_xfer(struct ata_port *ap, unsigned char *buf,
3053 unsigned int buflen, int write_data)
3054{
3055 unsigned int i;
3056 unsigned int words = buflen >> 1;
3057 u16 *buf16 = (u16 *) buf;
3058 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
3059
6ae4cfb5 3060 /* Transfer multiple of 2 bytes */
1da177e4
LT		 3061 if (write_data) {
3062 for (i = 0; i < words; i++)
3063 writew(le16_to_cpu(buf16[i]), mmio);
3064 } else {
3065 for (i = 0; i < words; i++)
3066 buf16[i] = cpu_to_le16(readw(mmio));
3067 }
6ae4cfb5
AL		 3068
3069 /* Transfer trailing 1 byte, if any. */
3070 if (unlikely(buflen & 0x01)) {
3071 u16 align_buf[1] = { 0 };
3072 unsigned char *trailing_buf = buf + buflen - 1;
3073
3074 if (write_data) {
3075 memcpy(align_buf, trailing_buf, 1);
3076 writew(le16_to_cpu(align_buf[0]), mmio);
3077 } else {
3078 align_buf[0] = cpu_to_le16(readw(mmio));
3079 memcpy(trailing_buf, align_buf, 1);
3080 }
3081 }
1da177e4
LT		 3082}
3083
6ae4cfb5
AL		 3084/**
3085 * ata_pio_data_xfer - Transfer data by PIO
3086 * @ap: port to read/write
3087 * @buf: data buffer
3088 * @buflen: buffer length
344babaa 3089 * @write_data: read/write
6ae4cfb5
AL		 3090 *
3091 * Transfer data from/to the device data register by PIO.
3092 *
3093 * LOCKING:
3094 * Inherited from caller.
6ae4cfb5
AL		 3095 */
3096
1da177e4
LT		 3097static void ata_pio_data_xfer(struct ata_port *ap, unsigned char *buf,
3098 unsigned int buflen, int write_data)
3099{
6ae4cfb5 3100 unsigned int words = buflen >> 1;
1da177e4 3101
6ae4cfb5 3102 /* Transfer multiple of 2 bytes */
1da177e4 3103 if (write_data)
6ae4cfb5 3104 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 3105 else
6ae4cfb5
AL		 3106 insw(ap->ioaddr.data_addr, buf, words);
3107
3108 /* Transfer trailing 1 byte, if any. */
3109 if (unlikely(buflen & 0x01)) {
3110 u16 align_buf[1] = { 0 };
3111 unsigned char *trailing_buf = buf + buflen - 1;
3112
3113 if (write_data) {
3114 memcpy(align_buf, trailing_buf, 1);
3115 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
3116 } else {
3117 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
3118 memcpy(trailing_buf, align_buf, 1);
3119 }
3120 }
1da177e4
LT		 3121}
3122
6ae4cfb5
AL		 3123/**
3124 * ata_data_xfer - Transfer data from/to the data register.
3125 * @ap: port to read/write
3126 * @buf: data buffer
3127 * @buflen: buffer length
3128 * @do_write: read/write
3129 *
3130 * Transfer data from/to the device data register.
3131 *
3132 * LOCKING:
3133 * Inherited from caller.
6ae4cfb5
AL		 3134 */
3135
1da177e4
LT		 3136static void ata_data_xfer(struct ata_port *ap, unsigned char *buf,
3137 unsigned int buflen, int do_write)
3138{
a1bd9e68
AC		 3139 /* Make the crap hardware pay the costs not the good stuff */
3140 if (unlikely(ap->flags & ATA_FLAG_IRQ_MASK)) {
3141 unsigned long flags;
3142 local_irq_save(flags);
3143 if (ap->flags & ATA_FLAG_MMIO)
3144 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3145 else
3146 ata_pio_data_xfer(ap, buf, buflen, do_write);
3147 local_irq_restore(flags);
3148 } else {
3149 if (ap->flags & ATA_FLAG_MMIO)
3150 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3151 else
3152 ata_pio_data_xfer(ap, buf, buflen, do_write);
3153 }
1da177e4
LT		 3154}
3155
6ae4cfb5
AL		 3156/**
3157 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
3158 * @qc: Command on going
3159 *
3160 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
3161 *
3162 * LOCKING:
3163 * Inherited from caller.
3164 */
3165
1da177e4
LT		 3166static void ata_pio_sector(struct ata_queued_cmd *qc)
3167{
3168 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3169 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3170 struct ata_port *ap = qc->ap;
3171 struct page *page;
3172 unsigned int offset;
3173 unsigned char *buf;
3174
3175 if (qc->cursect == (qc->nsect - 1))
14be71f4 3176 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3177
3178 page = sg[qc->cursg].page;
3179 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
3180
3181 /* get the current page and offset */
3182 page = nth_page(page, (offset >> PAGE_SHIFT));
3183 offset %= PAGE_SIZE;
3184
1da177e4
LT		 3185 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3186
91b8b313
AL		 3187 if (PageHighMem(page)) {
3188 unsigned long flags;
3189
3190 local_irq_save(flags);
3191 buf = kmap_atomic(page, KM_IRQ0);
083958d3 3192
91b8b313
AL		 3193 /* do the actual data transfer */
3194 ata_data_xfer(ap, buf + offset, ATA_SECT_SIZE, do_write);
1da177e4 3195
91b8b313
AL		 3196 kunmap_atomic(buf, KM_IRQ0);
3197 local_irq_restore(flags);
3198 } else {
3199 buf = page_address(page);
3200 ata_data_xfer(ap, buf + offset, ATA_SECT_SIZE, do_write);
3201 }
7282aa4b
AL		 3202
3203 qc->cursect++;
3204 qc->cursg_ofs++;
3205
3206 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
3207 qc->cursg++;
3208 qc->cursg_ofs = 0;
3209 }
1da177e4
LT		 3210}
3211
07f6f7d0
AL		 3212/**
3213 * ata_pio_sectors - Transfer one or many 512-byte sectors.
3214 * @qc: Command on going
3215 *
3216 * Transfer one or many ATA_SECT_SIZE of data from/to the
3217 * ATA device for the DRQ request.
3218 *
3219 * LOCKING:
3220 * Inherited from caller.
3221 */
3222
3223static void ata_pio_sectors(struct ata_queued_cmd *qc)
3224{
3225 if (is_multi_taskfile(&qc->tf)) {
3226 /* READ/WRITE MULTIPLE */
3227 unsigned int nsect;
3228
3229 assert(qc->dev->multi_count);
3230
3231 nsect = min(qc->nsect - qc->cursect, qc->dev->multi_count);
3232 while (nsect--)
3233 ata_pio_sector(qc);
3234 } else
3235 ata_pio_sector(qc);
3236}
3237
c71c1857
AL		 3238/**
3239 * atapi_send_cdb - Write CDB bytes to hardware
3240 * @ap: Port to which ATAPI device is attached.
3241 * @qc: Taskfile currently active
3242 *
3243 * When device has indicated its readiness to accept
3244 * a CDB, this function is called. Send the CDB.
3245 *
3246 * LOCKING:
3247 * caller.
3248 */
3249
3250static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
3251{
3252 /* send SCSI cdb */
3253 DPRINTK("send cdb\n");
3254 assert(ap->cdb_len >= 12);
3255
3256 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
3257 ata_altstatus(ap); /* flush */
3258
3259 switch (qc->tf.protocol) {
3260 case ATA_PROT_ATAPI:
3261 ap->hsm_task_state = HSM_ST;
3262 break;
3263 case ATA_PROT_ATAPI_NODATA:
3264 ap->hsm_task_state = HSM_ST_LAST;
3265 break;
3266 case ATA_PROT_ATAPI_DMA:
3267 ap->hsm_task_state = HSM_ST_LAST;
3268 /* initiate bmdma */
3269 ap->ops->bmdma_start(qc);
3270 break;
3271 }
3272}
3273
3274/**
e27486db
AL		 3275 * ata_pio_first_block - Write first data block to hardware
3276 * @ap: Port to which ATA/ATAPI device is attached.
c71c1857
AL		 3277 *
3278 * When device has indicated its readiness to accept
3279 * the data, this function sends out the CDB or
3280 * the first data block by PIO.
3281 * After this,
3282 * - If polling, ata_pio_task() handles the rest.
3283 * - Otherwise, interrupt handler takes over.
3284 *
3285 * LOCKING:
3286 * Kernel thread context (may sleep)
fbcdd80b
AL		 3287 *
3288 * RETURNS:
3289 * Zero if irq handler takes over
3290 * Non-zero if has next (polling).
c71c1857
AL		 3291 */
3292
fbcdd80b 3293static int ata_pio_first_block(struct ata_port *ap)
c71c1857 3294{
c71c1857
AL		 3295 struct ata_queued_cmd *qc;
3296 u8 status;
3297 unsigned long flags;
fbcdd80b 3298 int has_next;
c71c1857
AL		 3299
3300 qc = ata_qc_from_tag(ap, ap->active_tag);
3301 assert(qc != NULL);
3302 assert(qc->flags & ATA_QCFLAG_ACTIVE);
3303
fbcdd80b
AL		 3304 /* if polling, we will stay in the work queue after sending the data.
3305 * otherwise, interrupt handler takes over after sending the data.
3306 */
3307 has_next = (qc->tf.flags & ATA_TFLAG_POLLING);
3308
c71c1857
AL		 3309 /* sleep-wait for BSY to clear */
3310 DPRINTK("busy wait\n");
fbcdd80b 3311 if (ata_busy_sleep(ap, ATA_TMOUT_DATAOUT_QUICK, ATA_TMOUT_DATAOUT)) {
555a8965 3312 qc->err_mask |= AC_ERR_TIMEOUT;
fbcdd80b 3313 ap->hsm_task_state = HSM_ST_TMOUT;
c71c1857 3314 goto err_out;
fbcdd80b 3315 }
c71c1857
AL		 3316
3317 /* make sure DRQ is set */
3318 status = ata_chk_status(ap);
fbcdd80b
AL		 3319 if ((status & (ATA_BUSY | ATA_DRQ)) != ATA_DRQ) {
3320 /* device status error */
555a8965 3321 qc->err_mask |= AC_ERR_HSM;
fbcdd80b 3322 ap->hsm_task_state = HSM_ST_ERR;
c71c1857 3323 goto err_out;
fbcdd80b 3324 }
c71c1857
AL		 3325
3326 /* Send the CDB (atapi) or the first data block (ata pio out).
3327 * During the state transition, interrupt handler shouldn't
3328 * be invoked before the data transfer is complete and
3329 * hsm_task_state is changed. Hence, the following locking.
3330 */
3331 spin_lock_irqsave(&ap->host_set->lock, flags);
3332
3333 if (qc->tf.protocol == ATA_PROT_PIO) {
3334 /* PIO data out protocol.
3335 * send first data block.
3336 */
3337
07f6f7d0
AL		 3338 /* ata_pio_sectors() might change the state to HSM_ST_LAST.
3339 * so, the state is changed here before ata_pio_sectors().
c71c1857
AL		 3340 */
3341 ap->hsm_task_state = HSM_ST;
07f6f7d0 3342 ata_pio_sectors(qc);
c71c1857
AL		 3343 ata_altstatus(ap); /* flush */
3344 } else
3345 /* send CDB */
3346 atapi_send_cdb(ap, qc);
3347
fbcdd80b
AL		 3348 spin_unlock_irqrestore(&ap->host_set->lock, flags);
3349
c71c1857
AL		 3350 /* if polling, ata_pio_task() handles the rest.
3351 * otherwise, interrupt handler takes over from here.
3352 */
fbcdd80b 3353 return has_next;
c71c1857
AL		 3354
3355err_out:
fbcdd80b 3356 return 1; /* has next */
c71c1857
AL		 3357}
3358
6ae4cfb5
AL		 3359/**
3360 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3361 * @qc: Command on going
3362 * @bytes: number of bytes
3363 *
3364 * Transfer Transfer data from/to the ATAPI device.
3365 *
3366 * LOCKING:
3367 * Inherited from caller.
3368 *
3369 */
3370
1da177e4
LT		 3371static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3372{
3373 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3374 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3375 struct ata_port *ap = qc->ap;
3376 struct page *page;
3377 unsigned char *buf;
3378 unsigned int offset, count;
3379
563a6e1f 3380 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3381 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3382
3383next_sg:
563a6e1f 3384 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3385 /*
563a6e1f
AL		 3386 * The end of qc->sg is reached and the device expects
3387 * more data to transfer. In order not to overrun qc->sg
3388 * and fulfill length specified in the byte count register,
3389 * - for read case, discard trailing data from the device
3390 * - for write case, padding zero data to the device
3391 */
3392 u16 pad_buf[1] = { 0 };
3393 unsigned int words = bytes >> 1;
3394 unsigned int i;
3395
3396 if (words) /* warning if bytes > 1 */
7fb6ec28 3397 printk(KERN_WARNING "ata%u: %u bytes trailing data\n",
563a6e1f
AL		 3398 ap->id, bytes);
3399
3400 for (i = 0; i < words; i++)
3401 ata_data_xfer(ap, (unsigned char*)pad_buf, 2, do_write);
3402
14be71f4 3403 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL		 3404 return;
3405 }
3406
cedc9a47 3407 sg = &qc->__sg[qc->cursg];
1da177e4 3408
1da177e4
LT		 3409 page = sg->page;
3410 offset = sg->offset + qc->cursg_ofs;
3411
3412 /* get the current page and offset */
3413 page = nth_page(page, (offset >> PAGE_SHIFT));
3414 offset %= PAGE_SIZE;
3415
6952df03 3416 /* don't overrun current sg */
32529e01 3417 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT		 3418
3419 /* don't cross page boundaries */
3420 count = min(count, (unsigned int)PAGE_SIZE - offset);
3421
7282aa4b
AL		 3422 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3423
91b8b313
AL		 3424 if (PageHighMem(page)) {
3425 unsigned long flags;
3426
3427 local_irq_save(flags);
3428 buf = kmap_atomic(page, KM_IRQ0);
083958d3 3429
91b8b313
AL		 3430 /* do the actual data transfer */
3431 ata_data_xfer(ap, buf + offset, count, do_write);
7282aa4b 3432
91b8b313
AL		 3433 kunmap_atomic(buf, KM_IRQ0);
3434 local_irq_restore(flags);
3435 } else {
3436 buf = page_address(page);
3437 ata_data_xfer(ap, buf + offset, count, do_write);
3438 }
7282aa4b 3439
1da177e4
LT		 3440 bytes -= count;
3441 qc->curbytes += count;
3442 qc->cursg_ofs += count;
3443
32529e01 3444 if (qc->cursg_ofs == sg->length) {
1da177e4
LT		 3445 qc->cursg++;
3446 qc->cursg_ofs = 0;
3447 }
3448
563a6e1f 3449 if (bytes)
1da177e4 3450 goto next_sg;
1da177e4
LT		 3451}
3452
6ae4cfb5
AL		 3453/**
3454 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
3455 * @qc: Command on going
3456 *
3457 * Transfer Transfer data from/to the ATAPI device.
3458 *
3459 * LOCKING:
3460 * Inherited from caller.
6ae4cfb5
AL		 3461 */
3462
1da177e4
LT		 3463static void atapi_pio_bytes(struct ata_queued_cmd *qc)
3464{
3465 struct ata_port *ap = qc->ap;
3466 struct ata_device *dev = qc->dev;
3467 unsigned int ireason, bc_lo, bc_hi, bytes;
3468 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
3469
3470 ap->ops->tf_read(ap, &qc->tf);
3471 ireason = qc->tf.nsect;
3472 bc_lo = qc->tf.lbam;
3473 bc_hi = qc->tf.lbah;
3474 bytes = (bc_hi << 8) | bc_lo;
3475
3476 /* shall be cleared to zero, indicating xfer of data */
3477 if (ireason & (1 << 0))
3478 goto err_out;
3479
3480 /* make sure transfer direction matches expected */
3481 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
3482 if (do_write != i_write)
3483 goto err_out;
3484
312f7da2
AL		 3485 VPRINTK("ata%u: xfering %d bytes\n", ap->id, bytes);
3486
1da177e4
LT		 3487 __atapi_pio_bytes(qc, bytes);
3488
3489 return;
3490
3491err_out:
3492 printk(KERN_INFO "ata%u: dev %u: ATAPI check failed\n",
3493 ap->id, dev->devno);
11a56d24 3494 qc->err_mask |= AC_ERR_HSM;
14be71f4 3495 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3496}
3497
3498/**
6f0ef4fa
RD		 3499 * ata_pio_block - start PIO on a block
3500 * @ap: the target ata_port
1da177e4
LT		 3501 *
3502 * LOCKING:
0cba632b 3503 * None. (executing in kernel thread context)
1da177e4
LT		 3504 */
3505
3506static void ata_pio_block(struct ata_port *ap)
3507{
3508 struct ata_queued_cmd *qc;
3509 u8 status;
3510
3511 /*
6f0ef4fa 3512 * This is purely heuristic. This is a fast path.
1da177e4
LT		 3513 * Sometimes when we enter, BSY will be cleared in
3514 * a chk-status or two. If not, the drive is probably seeking
3515 * or something. Snooze for a couple msecs, then
3516 * chk-status again. If still busy, fall back to
14be71f4 3517 * HSM_ST_POLL state.
1da177e4
LT		 3518 */
3519 status = ata_busy_wait(ap, ATA_BUSY, 5);
3520 if (status & ATA_BUSY) {
3521 msleep(2);
3522 status = ata_busy_wait(ap, ATA_BUSY, 10);
3523 if (status & ATA_BUSY) {
14be71f4 3524 ap->hsm_task_state = HSM_ST_POLL;
1da177e4
LT		 3525 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
3526 return;
3527 }
3528 }
3529
3530 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 3531 WARN_ON(qc == NULL);
1da177e4 3532
fe79e683
AL		 3533 /* check error */
3534 if (status & (ATA_ERR | ATA_DF)) {
3535 qc->err_mask |= AC_ERR_DEV;
3536 ap->hsm_task_state = HSM_ST_ERR;
3537 return;
3538 }
3539
3540 /* transfer data if any */
1da177e4 3541 if (is_atapi_taskfile(&qc->tf)) {
fe79e683 3542 /* DRQ=0 means no more data to transfer */
1da177e4 3543 if ((status & ATA_DRQ) == 0) {
14be71f4 3544 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3545 return;
3546 }
3547
3548 atapi_pio_bytes(qc);
3549 } else {
3550 /* handle BSY=0, DRQ=0 as error */
3551 if ((status & ATA_DRQ) == 0) {
11a56d24 3552 qc->err_mask |= AC_ERR_HSM;
14be71f4 3553 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3554 return;
3555 }
3556
07f6f7d0 3557 ata_pio_sectors(qc);
1da177e4 3558 }
467b16d4
AL		 3559
3560 ata_altstatus(ap); /* flush */
1da177e4
LT		 3561}
3562
3563static void ata_pio_error(struct ata_port *ap)
3564{
3565 struct ata_queued_cmd *qc;
a7dac447 3566
1da177e4 3567 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 3568 WARN_ON(qc == NULL);
1da177e4 3569
000080c3
AL		 3570 if (qc->tf.command != ATA_CMD_PACKET)
3571 printk(KERN_WARNING "ata%u: PIO error\n", ap->id);
3572
1c848984
AL		 3573 /* make sure qc->err_mask is available to
3574 * know what's wrong and recover
3575 */
a4631474 3576 WARN_ON(qc->err_mask == 0);
1c848984 3577
14be71f4 3578 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3579
a22e2eb0 3580 ata_poll_qc_complete(qc);
1da177e4
LT		 3581}
3582
3583static void ata_pio_task(void *_data)
3584{
3585 struct ata_port *ap = _data;
7fb6ec28 3586 unsigned long timeout;
fbcdd80b 3587 int has_next;
7fb6ec28
JG		 3588
3589fsm_start:
3590 timeout = 0;
fbcdd80b 3591 has_next = 1;
1da177e4 3592
14be71f4 3593 switch (ap->hsm_task_state) {
e27486db 3594 case HSM_ST_FIRST:
fbcdd80b
AL		 3595 has_next = ata_pio_first_block(ap);
3596 break;
e27486db 3597
14be71f4 3598 case HSM_ST:
1da177e4
LT		 3599 ata_pio_block(ap);
3600 break;
3601
14be71f4 3602 case HSM_ST_LAST:
fbcdd80b 3603 has_next = ata_pio_complete(ap);
1da177e4
LT		 3604 break;
3605
14be71f4
AL		 3606 case HSM_ST_POLL:
3607 case HSM_ST_LAST_POLL:
1da177e4
LT		 3608 timeout = ata_pio_poll(ap);
3609 break;
3610
14be71f4
AL		 3611 case HSM_ST_TMOUT:
3612 case HSM_ST_ERR:
1da177e4
LT		 3613 ata_pio_error(ap);
3614 return;
467b16d4
AL		 3615
3616 default:
3617 BUG();
3618 return;
1da177e4
LT		 3619 }
3620
3621 if (timeout)
95064379 3622 ata_queue_delayed_pio_task(ap, timeout);
fbcdd80b 3623 else if (has_next)
7fb6ec28 3624 goto fsm_start;
1da177e4
LT		 3625}
3626
1da177e4
LT		 3627/**
3628 * ata_qc_timeout - Handle timeout of queued command
3629 * @qc: Command that timed out
3630 *
3631 * Some part of the kernel (currently, only the SCSI layer)
3632 * has noticed that the active command on port @ap has not
3633 * completed after a specified length of time. Handle this
3634 * condition by disabling DMA (if necessary) and completing
3635 * transactions, with error if necessary.
3636 *
3637 * This also handles the case of the "lost interrupt", where
3638 * for some reason (possibly hardware bug, possibly driver bug)
3639 * an interrupt was not delivered to the driver, even though the
3640 * transaction completed successfully.
3641 *
3642 * LOCKING:
0cba632b 3643 * Inherited from SCSI layer (none, can sleep)
1da177e4
LT		 3644 */
3645
3646static void ata_qc_timeout(struct ata_queued_cmd *qc)
3647{
3648 struct ata_port *ap = qc->ap;
b8f6153e 3649 struct ata_host_set *host_set = ap->host_set;
1da177e4 3650 u8 host_stat = 0, drv_stat;
b8f6153e 3651 unsigned long flags;
1da177e4
LT		 3652
3653 DPRINTK("ENTER\n");
3654
c18d06f8
TH		 3655 ata_flush_pio_tasks(ap);
3656 ap->hsm_task_state = HSM_ST_IDLE;
3657
b8f6153e
JG		 3658 spin_lock_irqsave(&host_set->lock, flags);
3659
1da177e4
LT		 3660 switch (qc->tf.protocol) {
3661
3662 case ATA_PROT_DMA:
3663 case ATA_PROT_ATAPI_DMA:
3664 host_stat = ap->ops->bmdma_status(ap);
3665
3666 /* before we do anything else, clear DMA-Start bit */
b73fc89f 3667 ap->ops->bmdma_stop(qc);
1da177e4
LT		 3668
3669 /* fall through */
3670
3671 default:
3672 ata_altstatus(ap);
3673 drv_stat = ata_chk_status(ap);
3674
3675 /* ack bmdma irq events */
3676 ap->ops->irq_clear(ap);
3677
3678 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x host_stat 0x%x\n",
3679 ap->id, qc->tf.command, drv_stat, host_stat);
3680
312f7da2
AL		 3681 ap->hsm_task_state = HSM_ST_IDLE;
3682
1da177e4 3683 /* complete taskfile transaction */
555a8965 3684 qc->err_mask |= AC_ERR_TIMEOUT;
1da177e4
LT		 3685 break;
3686 }
b8f6153e
JG		 3687
3688 spin_unlock_irqrestore(&host_set->lock, flags);
3689
a72ec4ce
TH		 3690 ata_eh_qc_complete(qc);
3691
1da177e4
LT		 3692 DPRINTK("EXIT\n");
3693}
3694
3695/**
3696 * ata_eng_timeout - Handle timeout of queued command
3697 * @ap: Port on which timed-out command is active
3698 *
3699 * Some part of the kernel (currently, only the SCSI layer)
3700 * has noticed that the active command on port @ap has not
3701 * completed after a specified length of time. Handle this
3702 * condition by disabling DMA (if necessary) and completing
3703 * transactions, with error if necessary.
3704 *
3705 * This also handles the case of the "lost interrupt", where
3706 * for some reason (possibly hardware bug, possibly driver bug)
3707 * an interrupt was not delivered to the driver, even though the
3708 * transaction completed successfully.
3709 *
3710 * LOCKING:
3711 * Inherited from SCSI layer (none, can sleep)
3712 */
3713
3714void ata_eng_timeout(struct ata_port *ap)
3715{
1da177e4
LT		 3716 DPRINTK("ENTER\n");
3717
f6379020 3718 ata_qc_timeout(ata_qc_from_tag(ap, ap->active_tag));
1da177e4 3719
1da177e4
LT		 3720 DPRINTK("EXIT\n");
3721}
3722
3723/**
3724 * ata_qc_new - Request an available ATA command, for queueing
3725 * @ap: Port associated with device @dev
3726 * @dev: Device from whom we request an available command structure
3727 *
3728 * LOCKING:
0cba632b 3729 * None.
1da177e4
LT		 3730 */
3731
3732static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
3733{
3734 struct ata_queued_cmd *qc = NULL;
3735 unsigned int i;
3736
3737 for (i = 0; i < ATA_MAX_QUEUE; i++)
3738 if (!test_and_set_bit(i, &ap->qactive)) {
3739 qc = ata_qc_from_tag(ap, i);
3740 break;
3741 }
3742
3743 if (qc)
3744 qc->tag = i;
3745
3746 return qc;
3747}
3748
3749/**
3750 * ata_qc_new_init - Request an available ATA command, and initialize it
3751 * @ap: Port associated with device @dev
3752 * @dev: Device from whom we request an available command structure
3753 *
3754 * LOCKING:
0cba632b 3755 * None.
1da177e4
LT		 3756 */
3757
3758struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap,
3759 struct ata_device *dev)
3760{
3761 struct ata_queued_cmd *qc;
3762
3763 qc = ata_qc_new(ap);
3764 if (qc) {
1da177e4
LT		 3765 qc->scsicmd = NULL;
3766 qc->ap = ap;
3767 qc->dev = dev;
1da177e4 3768
2c13b7ce 3769 ata_qc_reinit(qc);
1da177e4
LT		 3770 }
3771
3772 return qc;
3773}
3774
1da177e4
LT		 3775/**
3776 * ata_qc_free - free unused ata_queued_cmd
3777 * @qc: Command to complete
3778 *
3779 * Designed to free unused ata_queued_cmd object
3780 * in case something prevents using it.
3781 *
3782 * LOCKING:
0cba632b 3783 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3784 */
3785void ata_qc_free(struct ata_queued_cmd *qc)
3786{
4ba946e9
TH		 3787 struct ata_port *ap = qc->ap;
3788 unsigned int tag;
3789
a4631474 3790 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
1da177e4 3791
4ba946e9
TH		 3792 qc->flags = 0;
3793 tag = qc->tag;
3794 if (likely(ata_tag_valid(tag))) {
3795 if (tag == ap->active_tag)
3796 ap->active_tag = ATA_TAG_POISON;
3797 qc->tag = ATA_TAG_POISON;
3798 clear_bit(tag, &ap->qactive);
3799 }
1da177e4
LT		 3800}
3801
76014427 3802void __ata_qc_complete(struct ata_queued_cmd *qc)
1da177e4 3803{
a4631474
TH		 3804 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
3805 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
1da177e4
LT		 3806
3807 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
3808 ata_sg_clean(qc);
3809
3f3791d3
AL		 3810 /* atapi: mark qc as inactive to prevent the interrupt handler
3811 * from completing the command twice later, before the error handler
3812 * is called. (when rc != 0 and atapi request sense is needed)
3813 */
3814 qc->flags &= ~ATA_QCFLAG_ACTIVE;
3815
1da177e4 3816 /* call completion callback */
77853bf2 3817 qc->complete_fn(qc);
1da177e4
LT		 3818}
3819
3820static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
3821{
3822 struct ata_port *ap = qc->ap;
3823
3824 switch (qc->tf.protocol) {
3825 case ATA_PROT_DMA:
3826 case ATA_PROT_ATAPI_DMA:
3827 return 1;
3828
3829 case ATA_PROT_ATAPI:
3830 case ATA_PROT_PIO:
3831 case ATA_PROT_PIO_MULT:
3832 if (ap->flags & ATA_FLAG_PIO_DMA)
3833 return 1;
3834
3835 /* fall through */
3836
3837 default:
3838 return 0;
3839 }
3840
3841 /* never reached */
3842}
3843
3844/**
3845 * ata_qc_issue - issue taskfile to device
3846 * @qc: command to issue to device
3847 *
3848 * Prepare an ATA command to submission to device.
3849 * This includes mapping the data into a DMA-able
3850 * area, filling in the S/G table, and finally
3851 * writing the taskfile to hardware, starting the command.
3852 *
3853 * LOCKING:
3854 * spin_lock_irqsave(host_set lock)
3855 *
3856 * RETURNS:
9a3d9eb0 3857 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT		 3858 */
3859
9a3d9eb0 3860unsigned int ata_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 3861{
3862 struct ata_port *ap = qc->ap;
3863
3864 if (ata_should_dma_map(qc)) {
3865 if (qc->flags & ATA_QCFLAG_SG) {
3866 if (ata_sg_setup(qc))
8e436af9 3867 goto sg_err;
1da177e4
LT		 3868 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
3869 if (ata_sg_setup_one(qc))
8e436af9 3870 goto sg_err;
1da177e4
LT		 3871 }
3872 } else {
3873 qc->flags &= ~ATA_QCFLAG_DMAMAP;
3874 }
3875
3876 ap->ops->qc_prep(qc);
3877
3878 qc->ap->active_tag = qc->tag;
3879 qc->flags |= ATA_QCFLAG_ACTIVE;
3880
3881 return ap->ops->qc_issue(qc);
3882
8e436af9
TH		 3883sg_err:
3884 qc->flags &= ~ATA_QCFLAG_DMAMAP;
9a3d9eb0 3885 return AC_ERR_SYSTEM;
1da177e4
LT		 3886}
3887
0baab86b 3888
1da177e4
LT		 3889/**
3890 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
3891 * @qc: command to issue to device
3892 *
3893 * Using various libata functions and hooks, this function
3894 * starts an ATA command. ATA commands are grouped into
3895 * classes called "protocols", and issuing each type of protocol
3896 * is slightly different.
3897 *
0baab86b
EF		 3898 * May be used as the qc_issue() entry in ata_port_operations.
3899 *
1da177e4
LT		 3900 * LOCKING:
3901 * spin_lock_irqsave(host_set lock)
3902 *
3903 * RETURNS:
9a3d9eb0 3904 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT		 3905 */
3906
9a3d9eb0 3907unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
1da177e4
LT		 3908{
3909 struct ata_port *ap = qc->ap;
3910
e50362ec
AL		 3911 /* Use polling pio if the LLD doesn't handle
3912 * interrupt driven pio and atapi CDB interrupt.
3913 */
3914 if (ap->flags & ATA_FLAG_PIO_POLLING) {
3915 switch (qc->tf.protocol) {
3916 case ATA_PROT_PIO:
3917 case ATA_PROT_ATAPI:
3918 case ATA_PROT_ATAPI_NODATA:
3919 qc->tf.flags |= ATA_TFLAG_POLLING;
3920 break;
3921 case ATA_PROT_ATAPI_DMA:
3922 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
3923 BUG();
3924 break;
3925 default:
3926 break;
3927 }
3928 }
3929
312f7da2 3930 /* select the device */
1da177e4
LT		 3931 ata_dev_select(ap, qc->dev->devno, 1, 0);
3932
312f7da2 3933 /* start the command */
1da177e4
LT		 3934 switch (qc->tf.protocol) {
3935 case ATA_PROT_NODATA:
312f7da2
AL		 3936 if (qc->tf.flags & ATA_TFLAG_POLLING)
3937 ata_qc_set_polling(qc);
3938
e5338254 3939 ata_tf_to_host(ap, &qc->tf);
312f7da2
AL		 3940 ap->hsm_task_state = HSM_ST_LAST;
3941
3942 if (qc->tf.flags & ATA_TFLAG_POLLING)
20ea079e 3943 ata_queue_pio_task(ap);
312f7da2 3944
1da177e4
LT		 3945 break;
3946
3947 case ATA_PROT_DMA:
312f7da2
AL		 3948 assert(!(qc->tf.flags & ATA_TFLAG_POLLING));
3949
1da177e4
LT		 3950 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3951 ap->ops->bmdma_setup(qc); /* set up bmdma */
3952 ap->ops->bmdma_start(qc); /* initiate bmdma */
312f7da2 3953 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3954 break;
3955
312f7da2
AL		 3956 case ATA_PROT_PIO:
3957 if (qc->tf.flags & ATA_TFLAG_POLLING)
3958 ata_qc_set_polling(qc);
3959
e5338254 3960 ata_tf_to_host(ap, &qc->tf);
312f7da2 3961
54f00389
AL		 3962 if (qc->tf.flags & ATA_TFLAG_WRITE) {
3963 /* PIO data out protocol */
3964 ap->hsm_task_state = HSM_ST_FIRST;
f6ef65e6 3965 ata_queue_pio_task(ap);
54f00389
AL		 3966
3967 /* always send first data block using
e27486db 3968 * the ata_pio_task() codepath.
54f00389 3969 */
312f7da2 3970 } else {
54f00389
AL		 3971 /* PIO data in protocol */
3972 ap->hsm_task_state = HSM_ST;
3973
3974 if (qc->tf.flags & ATA_TFLAG_POLLING)
f6ef65e6 3975 ata_queue_pio_task(ap);
54f00389
AL		 3976
3977 /* if polling, ata_pio_task() handles the rest.
3978 * otherwise, interrupt handler takes over from here.
3979 */
312f7da2
AL		 3980 }
3981
1da177e4
LT		 3982 break;
3983
3984 case ATA_PROT_ATAPI:
1da177e4 3985 case ATA_PROT_ATAPI_NODATA:
312f7da2
AL		 3986 if (qc->tf.flags & ATA_TFLAG_POLLING)
3987 ata_qc_set_polling(qc);
3988
e5338254 3989 ata_tf_to_host(ap, &qc->tf);
f6ef65e6 3990
312f7da2
AL		 3991 ap->hsm_task_state = HSM_ST_FIRST;
3992
3993 /* send cdb by polling if no cdb interrupt */
3994 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
3995 (qc->tf.flags & ATA_TFLAG_POLLING))
20ea079e 3996 ata_queue_pio_task(ap);
1da177e4
LT		 3997 break;
3998
3999 case ATA_PROT_ATAPI_DMA:
312f7da2
AL		 4000 assert(!(qc->tf.flags & ATA_TFLAG_POLLING));
4001
1da177e4
LT		 4002 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
4003 ap->ops->bmdma_setup(qc); /* set up bmdma */
312f7da2
AL		 4004 ap->hsm_task_state = HSM_ST_FIRST;
4005
4006 /* send cdb by polling if no cdb interrupt */
4007 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
20ea079e 4008 ata_queue_pio_task(ap);
1da177e4
LT		 4009 break;
4010
4011 default:
4012 WARN_ON(1);
9a3d9eb0 4013 return AC_ERR_SYSTEM;
1da177e4
LT		 4014 }
4015
4016 return 0;
4017}
4018
4019/**
0baab86b 4020 * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
1da177e4
LT		 4021 * @qc: Info associated with this ATA transaction.
4022 *
4023 * LOCKING:
4024 * spin_lock_irqsave(host_set lock)
4025 */
4026
4027static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc)
4028{
4029 struct ata_port *ap = qc->ap;
4030 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
4031 u8 dmactl;
4032 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4033
4034 /* load PRD table addr. */
4035 mb(); /* make sure PRD table writes are visible to controller */
4036 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
4037
4038 /* specify data direction, triple-check start bit is clear */
4039 dmactl = readb(mmio + ATA_DMA_CMD);
4040 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
4041 if (!rw)
4042 dmactl |= ATA_DMA_WR;
4043 writeb(dmactl, mmio + ATA_DMA_CMD);
4044
4045 /* issue r/w command */
4046 ap->ops->exec_command(ap, &qc->tf);
4047}
4048
4049/**
b73fc89f 4050 * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction
1da177e4
LT		 4051 * @qc: Info associated with this ATA transaction.
4052 *
4053 * LOCKING:
4054 * spin_lock_irqsave(host_set lock)
4055 */
4056
4057static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc)
4058{
4059 struct ata_port *ap = qc->ap;
4060 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4061 u8 dmactl;
4062
4063 /* start host DMA transaction */
4064 dmactl = readb(mmio + ATA_DMA_CMD);
4065 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
4066
4067 /* Strictly, one may wish to issue a readb() here, to
4068 * flush the mmio write. However, control also passes
4069 * to the hardware at this point, and it will interrupt
4070 * us when we are to resume control. So, in effect,
4071 * we don't care when the mmio write flushes.
4072 * Further, a read of the DMA status register _immediately_
4073 * following the write may not be what certain flaky hardware
4074 * is expected, so I think it is best to not add a readb()
4075 * without first all the MMIO ATA cards/mobos.
4076 * Or maybe I'm just being paranoid.
4077 */
4078}
4079
4080/**
4081 * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO)
4082 * @qc: Info associated with this ATA transaction.
4083 *
4084 * LOCKING:
4085 * spin_lock_irqsave(host_set lock)
4086 */
4087
4088static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc)
4089{
4090 struct ata_port *ap = qc->ap;
4091 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
4092 u8 dmactl;
4093
4094 /* load PRD table addr. */
4095 outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
4096
4097 /* specify data direction, triple-check start bit is clear */
4098 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4099 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
4100 if (!rw)
4101 dmactl |= ATA_DMA_WR;
4102 outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4103
4104 /* issue r/w command */
4105 ap->ops->exec_command(ap, &qc->tf);
4106}
4107
4108/**
4109 * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO)
4110 * @qc: Info associated with this ATA transaction.
4111 *
4112 * LOCKING:
4113 * spin_lock_irqsave(host_set lock)
4114 */
4115
4116static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
4117{
4118 struct ata_port *ap = qc->ap;
4119 u8 dmactl;
4120
4121 /* start host DMA transaction */
4122 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4123 outb(dmactl | ATA_DMA_START,
4124 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4125}
4126
0baab86b
EF		 4127
4128/**
4129 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
4130 * @qc: Info associated with this ATA transaction.
4131 *
4132 * Writes the ATA_DMA_START flag to the DMA command register.
4133 *
4134 * May be used as the bmdma_start() entry in ata_port_operations.
4135 *
4136 * LOCKING:
4137 * spin_lock_irqsave(host_set lock)
4138 */
1da177e4
LT		 4139void ata_bmdma_start(struct ata_queued_cmd *qc)
4140{
4141 if (qc->ap->flags & ATA_FLAG_MMIO)
4142 ata_bmdma_start_mmio(qc);
4143 else
4144 ata_bmdma_start_pio(qc);
4145}
4146
0baab86b
EF		 4147
4148/**
4149 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
4150 * @qc: Info associated with this ATA transaction.
4151 *
4152 * Writes address of PRD table to device's PRD Table Address
4153 * register, sets the DMA control register, and calls
4154 * ops->exec_command() to start the transfer.
4155 *
4156 * May be used as the bmdma_setup() entry in ata_port_operations.
4157 *
4158 * LOCKING:
4159 * spin_lock_irqsave(host_set lock)
4160 */
1da177e4
LT		 4161void ata_bmdma_setup(struct ata_queued_cmd *qc)
4162{
4163 if (qc->ap->flags & ATA_FLAG_MMIO)
4164 ata_bmdma_setup_mmio(qc);
4165 else
4166 ata_bmdma_setup_pio(qc);
4167}
4168
0baab86b
EF		 4169
4170/**
4171 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
decc6d0b 4172 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 4173 *
4174 * Clear interrupt and error flags in DMA status register.
4175 *
4176 * May be used as the irq_clear() entry in ata_port_operations.
4177 *
4178 * LOCKING:
4179 * spin_lock_irqsave(host_set lock)
4180 */
4181
1da177e4
LT		 4182void ata_bmdma_irq_clear(struct ata_port *ap)
4183{
4184 if (ap->flags & ATA_FLAG_MMIO) {
4185 void __iomem *mmio = ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS;
4186 writeb(readb(mmio), mmio);
4187 } else {
4188 unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
4189 outb(inb(addr), addr);
4190 }
4191
4192}
4193
0baab86b
EF		 4194
4195/**
4196 * ata_bmdma_status - Read PCI IDE BMDMA status
decc6d0b 4197 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 4198 *
4199 * Read and return BMDMA status register.
4200 *
4201 * May be used as the bmdma_status() entry in ata_port_operations.
4202 *
4203 * LOCKING:
4204 * spin_lock_irqsave(host_set lock)
4205 */
4206
1da177e4
LT		 4207u8 ata_bmdma_status(struct ata_port *ap)
4208{
4209 u8 host_stat;
4210 if (ap->flags & ATA_FLAG_MMIO) {
4211 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4212 host_stat = readb(mmio + ATA_DMA_STATUS);
4213 } else
ee500aab 4214 host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
1da177e4
LT		 4215 return host_stat;
4216}
4217
0baab86b
EF		 4218
4219/**
4220 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
b73fc89f 4221 * @qc: Command we are ending DMA for
0baab86b
EF		 4222 *
4223 * Clears the ATA_DMA_START flag in the dma control register
4224 *
4225 * May be used as the bmdma_stop() entry in ata_port_operations.
4226 *
4227 * LOCKING:
4228 * spin_lock_irqsave(host_set lock)
4229 */
4230
b73fc89f 4231void ata_bmdma_stop(struct ata_queued_cmd *qc)
1da177e4 4232{
b73fc89f 4233 struct ata_port *ap = qc->ap;
1da177e4
LT		 4234 if (ap->flags & ATA_FLAG_MMIO) {
4235 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4236
4237 /* clear start/stop bit */
4238 writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
4239 mmio + ATA_DMA_CMD);
4240 } else {
4241 /* clear start/stop bit */
4242 outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
4243 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4244 }
4245
4246 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
4247 ata_altstatus(ap); /* dummy read */
4248}
4249
4250/**
4251 * ata_host_intr - Handle host interrupt for given (port, task)
4252 * @ap: Port on which interrupt arrived (possibly...)
4253 * @qc: Taskfile currently active in engine
4254 *
4255 * Handle host interrupt for given queued command. Currently,
4256 * only DMA interrupts are handled. All other commands are
4257 * handled via polling with interrupts disabled (nIEN bit).
4258 *
4259 * LOCKING:
4260 * spin_lock_irqsave(host_set lock)
4261 *
4262 * RETURNS:
4263 * One if interrupt was handled, zero if not (shared irq).
4264 */
4265
4266inline unsigned int ata_host_intr (struct ata_port *ap,
4267 struct ata_queued_cmd *qc)
4268{
312f7da2 4269 u8 status, host_stat = 0;
1da177e4 4270
312f7da2
AL		 4271 VPRINTK("ata%u: protocol %d task_state %d\n",
4272 ap->id, qc->tf.protocol, ap->hsm_task_state);
1da177e4 4273
312f7da2
AL		 4274 /* Check whether we are expecting interrupt in this state */
4275 switch (ap->hsm_task_state) {
4276 case HSM_ST_FIRST:
4277 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
4278 * The flag was turned on only for atapi devices.
4279 * No need to check is_atapi_taskfile(&qc->tf) again.
4280 */
4281 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1da177e4 4282 goto idle_irq;
312f7da2
AL		 4283 break;
4284 case HSM_ST_LAST:
4285 if (qc->tf.protocol == ATA_PROT_DMA ||
4286 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
4287 /* check status of DMA engine */
4288 host_stat = ap->ops->bmdma_status(ap);
4289 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
4290
4291 /* if it's not our irq... */
4292 if (!(host_stat & ATA_DMA_INTR))
4293 goto idle_irq;
4294
4295 /* before we do anything else, clear DMA-Start bit */
4296 ap->ops->bmdma_stop(qc);
a4f16610
AL		 4297
4298 if (unlikely(host_stat & ATA_DMA_ERR)) {
4299 /* error when transfering data to/from memory */
4300 qc->err_mask |= AC_ERR_HOST_BUS;
4301 ap->hsm_task_state = HSM_ST_ERR;
4302 }
312f7da2
AL		 4303 }
4304 break;
4305 case HSM_ST:
4306 break;
4307 default:
4308 goto idle_irq;
4309 }
1da177e4 4310
312f7da2
AL		 4311 /* check altstatus */
4312 status = ata_altstatus(ap);
4313 if (status & ATA_BUSY)
4314 goto idle_irq;
1da177e4 4315
312f7da2
AL		 4316 /* check main status, clearing INTRQ */
4317 status = ata_chk_status(ap);
4318 if (unlikely(status & ATA_BUSY))
4319 goto idle_irq;
1da177e4 4320
312f7da2
AL		 4321 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
4322 ap->id, qc->tf.protocol, ap->hsm_task_state, status);
1da177e4 4323
312f7da2
AL		 4324 /* ack bmdma irq events */
4325 ap->ops->irq_clear(ap);
1da177e4 4326
312f7da2 4327 /* check error */
a4f16610
AL		 4328 if (unlikely(status & (ATA_ERR | ATA_DF))) {
4329 qc->err_mask |= AC_ERR_DEV;
312f7da2 4330 ap->hsm_task_state = HSM_ST_ERR;
a4f16610 4331 }
312f7da2
AL		 4332
4333fsm_start:
4334 switch (ap->hsm_task_state) {
4335 case HSM_ST_FIRST:
4336 /* Some pre-ATAPI-4 devices assert INTRQ
4337 * at this state when ready to receive CDB.
4338 */
4339
4340 /* check device status */
4341 if (unlikely((status & (ATA_BUSY | ATA_DRQ)) != ATA_DRQ)) {
4342 /* Wrong status. Let EH handle this */
555a8965 4343 qc->err_mask |= AC_ERR_HSM;
312f7da2
AL		 4344 ap->hsm_task_state = HSM_ST_ERR;
4345 goto fsm_start;
4346 }
4347
4348 atapi_send_cdb(ap, qc);
4349
4350 break;
4351
4352 case HSM_ST:
4353 /* complete command or read/write the data register */
4354 if (qc->tf.protocol == ATA_PROT_ATAPI) {
4355 /* ATAPI PIO protocol */
4356 if ((status & ATA_DRQ) == 0) {
4357 /* no more data to transfer */
4358 ap->hsm_task_state = HSM_ST_LAST;
4359 goto fsm_start;
4360 }
4361
4362 atapi_pio_bytes(qc);
4363
4364 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
4365 /* bad ireason reported by device */
4366 goto fsm_start;
4367
4368 } else {
4369 /* ATA PIO protocol */
4370 if (unlikely((status & ATA_DRQ) == 0)) {
4371 /* handle BSY=0, DRQ=0 as error */
555a8965 4372 qc->err_mask |= AC_ERR_HSM;
312f7da2
AL		 4373 ap->hsm_task_state = HSM_ST_ERR;
4374 goto fsm_start;
4375 }
4376
07f6f7d0 4377 ata_pio_sectors(qc);
312f7da2
AL		 4378
4379 if (ap->hsm_task_state == HSM_ST_LAST &&
4380 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
4381 /* all data read */
4382 ata_altstatus(ap);
4383 status = ata_chk_status(ap);
4384 goto fsm_start;
4385 }
4386 }
4387
4388 ata_altstatus(ap); /* flush */
4389 break;
4390
4391 case HSM_ST_LAST:
4392 if (unlikely(status & ATA_DRQ)) {
4393 /* handle DRQ=1 as error */
555a8965 4394 qc->err_mask |= AC_ERR_HSM;
312f7da2
AL		 4395 ap->hsm_task_state = HSM_ST_ERR;
4396 goto fsm_start;
4397 }
4398
4399 /* no more data to transfer */
4400 DPRINTK("ata%u: command complete, drv_stat 0x%x\n",
4401 ap->id, status);
4402
4403 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4
LT		 4404
4405 /* complete taskfile transaction */
a22e2eb0
AL		 4406 qc->err_mask |= ac_err_mask(status);
4407 ata_qc_complete(qc);
1da177e4
LT		 4408 break;
4409
312f7da2 4410 case HSM_ST_ERR:
000080c3
AL		 4411 if (qc->tf.command != ATA_CMD_PACKET)
4412 printk(KERN_ERR "ata%u: command error, drv_stat 0x%x host_stat 0x%x\n",
4413 ap->id, status, host_stat);
312f7da2 4414
a4f16610
AL		 4415 /* make sure qc->err_mask is available to
4416 * know what's wrong and recover
4417 */
4418 assert(qc->err_mask);
4419
312f7da2 4420 ap->hsm_task_state = HSM_ST_IDLE;
278efe95 4421 ata_qc_complete(qc);
312f7da2 4422 break;
1da177e4
LT		 4423 default:
4424 goto idle_irq;
4425 }
4426
4427 return 1; /* irq handled */
4428
4429idle_irq:
4430 ap->stats.idle_irq++;
4431
4432#ifdef ATA_IRQ_TRAP
4433 if ((ap->stats.idle_irq % 1000) == 0) {
4434 handled = 1;
4435 ata_irq_ack(ap, 0); /* debug trap */
4436 printk(KERN_WARNING "ata%d: irq trap\n", ap->id);
4437 }
4438#endif
4439 return 0; /* irq not handled */
4440}
4441
4442/**
4443 * ata_interrupt - Default ATA host interrupt handler
0cba632b
JG		 4444 * @irq: irq line (unused)
4445 * @dev_instance: pointer to our ata_host_set information structure
1da177e4
LT		 4446 * @regs: unused
4447 *
0cba632b
JG		 4448 * Default interrupt handler for PCI IDE devices. Calls
4449 * ata_host_intr() for each port that is not disabled.
4450 *
1da177e4 4451 * LOCKING:
0cba632b 4452 * Obtains host_set lock during operation.
1da177e4
LT		 4453 *
4454 * RETURNS:
0cba632b 4455 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT		 4456 */
4457
4458irqreturn_t ata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
4459{
4460 struct ata_host_set *host_set = dev_instance;
4461 unsigned int i;
4462 unsigned int handled = 0;
4463 unsigned long flags;
4464
4465 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
4466 spin_lock_irqsave(&host_set->lock, flags);
4467
4468 for (i = 0; i < host_set->n_ports; i++) {
4469 struct ata_port *ap;
4470
4471 ap = host_set->ports[i];
c1389503 4472 if (ap &&
312f7da2 4473 !(ap->flags & ATA_FLAG_PORT_DISABLED)) {
1da177e4
LT		 4474 struct ata_queued_cmd *qc;
4475
4476 qc = ata_qc_from_tag(ap, ap->active_tag);
312f7da2 4477 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
21b1ed74 4478 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT		 4479 handled |= ata_host_intr(ap, qc);
4480 }
4481 }
4482
4483 spin_unlock_irqrestore(&host_set->lock, flags);
4484
4485 return IRQ_RETVAL(handled);
4486}
4487
9b847548
JA		 4488/*
4489 * Execute a 'simple' command, that only consists of the opcode 'cmd' itself,
4490 * without filling any other registers
4491 */
4492static int ata_do_simple_cmd(struct ata_port *ap, struct ata_device *dev,
4493 u8 cmd)
4494{
4495 struct ata_taskfile tf;
4496 int err;
4497
4498 ata_tf_init(ap, &tf, dev->devno);
4499
4500 tf.command = cmd;
4501 tf.flags |= ATA_TFLAG_DEVICE;
4502 tf.protocol = ATA_PROT_NODATA;
4503
4504 err = ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0);
4505 if (err)
4506 printk(KERN_ERR "%s: ata command failed: %d\n",
4507 __FUNCTION__, err);
4508
4509 return err;
4510}
4511
4512static int ata_flush_cache(struct ata_port *ap, struct ata_device *dev)
4513{
4514 u8 cmd;
4515
4516 if (!ata_try_flush_cache(dev))
4517 return 0;
4518
4519 if (ata_id_has_flush_ext(dev->id))
4520 cmd = ATA_CMD_FLUSH_EXT;
4521 else
4522 cmd = ATA_CMD_FLUSH;
4523
4524 return ata_do_simple_cmd(ap, dev, cmd);
4525}
4526
4527static int ata_standby_drive(struct ata_port *ap, struct ata_device *dev)
4528{
4529 return ata_do_simple_cmd(ap, dev, ATA_CMD_STANDBYNOW1);
4530}
4531
4532static int ata_start_drive(struct ata_port *ap, struct ata_device *dev)
4533{
4534 return ata_do_simple_cmd(ap, dev, ATA_CMD_IDLEIMMEDIATE);
4535}
4536
4537/**
4538 * ata_device_resume - wakeup a previously suspended devices
c893a3ae
RD		 4539 * @ap: port the device is connected to
4540 * @dev: the device to resume
9b847548
JA		 4541 *
4542 * Kick the drive back into action, by sending it an idle immediate
4543 * command and making sure its transfer mode matches between drive
4544 * and host.
4545 *
4546 */
4547int ata_device_resume(struct ata_port *ap, struct ata_device *dev)
4548{
4549 if (ap->flags & ATA_FLAG_SUSPENDED) {
4550 ap->flags &= ~ATA_FLAG_SUSPENDED;
4551 ata_set_mode(ap);
4552 }
4553 if (!ata_dev_present(dev))
4554 return 0;
4555 if (dev->class == ATA_DEV_ATA)
4556 ata_start_drive(ap, dev);
4557
4558 return 0;
4559}
4560
4561/**
4562 * ata_device_suspend - prepare a device for suspend
c893a3ae
RD		 4563 * @ap: port the device is connected to
4564 * @dev: the device to suspend
9b847548
JA		 4565 *
4566 * Flush the cache on the drive, if appropriate, then issue a
4567 * standbynow command.
9b847548
JA		 4568 */
4569int ata_device_suspend(struct ata_port *ap, struct ata_device *dev)
4570{
4571 if (!ata_dev_present(dev))
4572 return 0;
4573 if (dev->class == ATA_DEV_ATA)
4574 ata_flush_cache(ap, dev);
4575
4576 ata_standby_drive(ap, dev);
4577 ap->flags |= ATA_FLAG_SUSPENDED;
4578 return 0;
4579}
4580
332b5a52
AL		 4581/**
4582 * ata_port_start - Set port up for dma.
4583 * @ap: Port to initialize
4584 *
4585 * Called just after data structures for each port are
4586 * initialized. Allocates space for PRD table.
4587 *
4588 * May be used as the port_start() entry in ata_port_operations.
4589 *
4590 * LOCKING:
4591 * Inherited from caller.
4592 */
4593
1da177e4
LT		 4594int ata_port_start (struct ata_port *ap)
4595{
4596 struct device *dev = ap->host_set->dev;
6037d6bb 4597 int rc;
1da177e4
LT		 4598
4599 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
4600 if (!ap->prd)
4601 return -ENOMEM;
4602
6037d6bb
JG		 4603 rc = ata_pad_alloc(ap, dev);
4604 if (rc) {
cedc9a47 4605 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4606 return rc;
cedc9a47
JG		 4607 }
4608
1da177e4
LT		 4609 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
4610
4611 return 0;
4612}
4613
0baab86b
EF		 4614
4615/**
4616 * ata_port_stop - Undo ata_port_start()
4617 * @ap: Port to shut down
4618 *
4619 * Frees the PRD table.
4620 *
4621 * May be used as the port_stop() entry in ata_port_operations.
4622 *
4623 * LOCKING:
6f0ef4fa 4624 * Inherited from caller.
0baab86b
EF		 4625 */
4626
1da177e4
LT		 4627void ata_port_stop (struct ata_port *ap)
4628{
4629 struct device *dev = ap->host_set->dev;
4630
4631 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4632 ata_pad_free(ap, dev);
1da177e4
LT		 4633}
4634
aa8f0dc6
JG		 4635void ata_host_stop (struct ata_host_set *host_set)
4636{
4637 if (host_set->mmio_base)
4638 iounmap(host_set->mmio_base);
4639}
4640
4641
1da177e4
LT		 4642/**
4643 * ata_host_remove - Unregister SCSI host structure with upper layers
4644 * @ap: Port to unregister
4645 * @do_unregister: 1 if we fully unregister, 0 to just stop the port
4646 *
4647 * LOCKING:
6f0ef4fa 4648 * Inherited from caller.
1da177e4
LT		 4649 */
4650
4651static void ata_host_remove(struct ata_port *ap, unsigned int do_unregister)
4652{
4653 struct Scsi_Host *sh = ap->host;
4654
4655 DPRINTK("ENTER\n");
4656
4657 if (do_unregister)
4658 scsi_remove_host(sh);
4659
4660 ap->ops->port_stop(ap);
4661}
4662
4663/**
4664 * ata_host_init - Initialize an ata_port structure
4665 * @ap: Structure to initialize
4666 * @host: associated SCSI mid-layer structure
4667 * @host_set: Collection of hosts to which @ap belongs
4668 * @ent: Probe information provided by low-level driver
4669 * @port_no: Port number associated with this ata_port
4670 *
0cba632b
JG		 4671 * Initialize a new ata_port structure, and its associated
4672 * scsi_host.
4673 *
1da177e4 4674 * LOCKING:
0cba632b 4675 * Inherited from caller.
1da177e4
LT		 4676 */
4677
4678static void ata_host_init(struct ata_port *ap, struct Scsi_Host *host,
4679 struct ata_host_set *host_set,
057ace5e 4680 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT		 4681{
4682 unsigned int i;
4683
4684 host->max_id = 16;
4685 host->max_lun = 1;
4686 host->max_channel = 1;
4687 host->unique_id = ata_unique_id++;
4688 host->max_cmd_len = 12;
12413197 4689
1da177e4
LT		 4690 ap->flags = ATA_FLAG_PORT_DISABLED;
4691 ap->id = host->unique_id;
4692 ap->host = host;
4693 ap->ctl = ATA_DEVCTL_OBS;
4694 ap->host_set = host_set;
4695 ap->port_no = port_no;
4696 ap->hard_port_no =
4697 ent->legacy_mode ? ent->hard_port_no : port_no;
4698 ap->pio_mask = ent->pio_mask;
4699 ap->mwdma_mask = ent->mwdma_mask;
4700 ap->udma_mask = ent->udma_mask;
4701 ap->flags |= ent->host_flags;
4702 ap->ops = ent->port_ops;
4703 ap->cbl = ATA_CBL_NONE;
4704 ap->active_tag = ATA_TAG_POISON;
4705 ap->last_ctl = 0xFF;
4706
1da177e4 4707 INIT_WORK(&ap->pio_task, ata_pio_task, ap);
a72ec4ce 4708 INIT_LIST_HEAD(&ap->eh_done_q);
1da177e4
LT		 4709
4710 for (i = 0; i < ATA_MAX_DEVICES; i++)
4711 ap->device[i].devno = i;
4712
4713#ifdef ATA_IRQ_TRAP
4714 ap->stats.unhandled_irq = 1;
4715 ap->stats.idle_irq = 1;
4716#endif
4717
4718 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
4719}
4720
4721/**
4722 * ata_host_add - Attach low-level ATA driver to system
4723 * @ent: Information provided by low-level driver
4724 * @host_set: Collections of ports to which we add
4725 * @port_no: Port number associated with this host
4726 *
0cba632b
JG		 4727 * Attach low-level ATA driver to system.
4728 *
1da177e4 4729 * LOCKING:
0cba632b 4730 * PCI/etc. bus probe sem.
1da177e4
LT		 4731 *
4732 * RETURNS:
0cba632b 4733 * New ata_port on success, for NULL on error.
1da177e4
LT		 4734 */
4735
057ace5e 4736static struct ata_port * ata_host_add(const struct ata_probe_ent *ent,
1da177e4
LT		 4737 struct ata_host_set *host_set,
4738 unsigned int port_no)
4739{
4740 struct Scsi_Host *host;
4741 struct ata_port *ap;
4742 int rc;
4743
4744 DPRINTK("ENTER\n");
4745 host = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
4746 if (!host)
4747 return NULL;
4748
4749 ap = (struct ata_port *) &host->hostdata[0];
4750
4751 ata_host_init(ap, host, host_set, ent, port_no);
4752
4753 rc = ap->ops->port_start(ap);
4754 if (rc)
4755 goto err_out;
4756
4757 return ap;
4758
4759err_out:
4760 scsi_host_put(host);
4761 return NULL;
4762}
4763
4764/**
0cba632b
JG		 4765 * ata_device_add - Register hardware device with ATA and SCSI layers
4766 * @ent: Probe information describing hardware device to be registered
4767 *
4768 * This function processes the information provided in the probe
4769 * information struct @ent, allocates the necessary ATA and SCSI
4770 * host information structures, initializes them, and registers
4771 * everything with requisite kernel subsystems.
4772 *
4773 * This function requests irqs, probes the ATA bus, and probes
4774 * the SCSI bus.
1da177e4
LT		 4775 *
4776 * LOCKING:
0cba632b 4777 * PCI/etc. bus probe sem.
1da177e4
LT		 4778 *
4779 * RETURNS:
0cba632b 4780 * Number of ports registered. Zero on error (no ports registered).
1da177e4
LT		 4781 */
4782
057ace5e 4783int ata_device_add(const struct ata_probe_ent *ent)
1da177e4
LT		 4784{
4785 unsigned int count = 0, i;
4786 struct device *dev = ent->dev;
4787 struct ata_host_set *host_set;
4788
4789 DPRINTK("ENTER\n");
4790 /* alloc a container for our list of ATA ports (buses) */
57f3bda8 4791 host_set = kzalloc(sizeof(struct ata_host_set) +
1da177e4
LT		 4792 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
4793 if (!host_set)
4794 return 0;
1da177e4
LT		 4795 spin_lock_init(&host_set->lock);
4796
4797 host_set->dev = dev;
4798 host_set->n_ports = ent->n_ports;
4799 host_set->irq = ent->irq;
4800 host_set->mmio_base = ent->mmio_base;
4801 host_set->private_data = ent->private_data;
4802 host_set->ops = ent->port_ops;
4803
4804 /* register each port bound to this device */
4805 for (i = 0; i < ent->n_ports; i++) {
4806 struct ata_port *ap;
4807 unsigned long xfer_mode_mask;
4808
4809 ap = ata_host_add(ent, host_set, i);
4810 if (!ap)
4811 goto err_out;
4812
4813 host_set->ports[i] = ap;
4814 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
4815 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
4816 (ap->pio_mask << ATA_SHIFT_PIO);
4817
4818 /* print per-port info to dmesg */
4819 printk(KERN_INFO "ata%u: %cATA max %s cmd 0x%lX ctl 0x%lX "
4820 "bmdma 0x%lX irq %lu\n",
4821 ap->id,
4822 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
4823 ata_mode_string(xfer_mode_mask),
4824 ap->ioaddr.cmd_addr,
4825 ap->ioaddr.ctl_addr,
4826 ap->ioaddr.bmdma_addr,
4827 ent->irq);
4828
4829 ata_chk_status(ap);
4830 host_set->ops->irq_clear(ap);
4831 count++;
4832 }
4833
57f3bda8
RD		 4834 if (!count)
4835 goto err_free_ret;
1da177e4
LT		 4836
4837 /* obtain irq, that is shared between channels */
4838 if (request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
4839 DRV_NAME, host_set))
4840 goto err_out;
4841
4842 /* perform each probe synchronously */
4843 DPRINTK("probe begin\n");
4844 for (i = 0; i < count; i++) {
4845 struct ata_port *ap;
4846 int rc;
4847
4848 ap = host_set->ports[i];
4849
c893a3ae 4850 DPRINTK("ata%u: bus probe begin\n", ap->id);
1da177e4 4851 rc = ata_bus_probe(ap);
c893a3ae 4852 DPRINTK("ata%u: bus probe end\n", ap->id);
1da177e4
LT		 4853
4854 if (rc) {
4855 /* FIXME: do something useful here?
4856 * Current libata behavior will
4857 * tear down everything when
4858 * the module is removed
4859 * or the h/w is unplugged.
4860 */
4861 }
4862
4863 rc = scsi_add_host(ap->host, dev);
4864 if (rc) {
4865 printk(KERN_ERR "ata%u: scsi_add_host failed\n",
4866 ap->id);
4867 /* FIXME: do something useful here */
4868 /* FIXME: handle unconditional calls to
4869 * scsi_scan_host and ata_host_remove, below,
4870 * at the very least
4871 */
4872 }
4873 }
4874
4875 /* probes are done, now scan each port's disk(s) */
c893a3ae 4876 DPRINTK("host probe begin\n");
1da177e4
LT		 4877 for (i = 0; i < count; i++) {
4878 struct ata_port *ap = host_set->ports[i];
4879
644dd0cc 4880 ata_scsi_scan_host(ap);
1da177e4
LT		 4881 }
4882
4883 dev_set_drvdata(dev, host_set);
4884
4885 VPRINTK("EXIT, returning %u\n", ent->n_ports);
4886 return ent->n_ports; /* success */
4887
4888err_out:
4889 for (i = 0; i < count; i++) {
4890 ata_host_remove(host_set->ports[i], 1);
4891 scsi_host_put(host_set->ports[i]->host);
4892 }
57f3bda8 4893err_free_ret:
1da177e4
LT		 4894 kfree(host_set);
4895 VPRINTK("EXIT, returning 0\n");
4896 return 0;
4897}
4898
17b14451
AC		 4899/**
4900 * ata_host_set_remove - PCI layer callback for device removal
4901 * @host_set: ATA host set that was removed
4902 *
4903 * Unregister all objects associated with this host set. Free those
4904 * objects.
4905 *
4906 * LOCKING:
4907 * Inherited from calling layer (may sleep).
4908 */
4909
17b14451
AC		 4910void ata_host_set_remove(struct ata_host_set *host_set)
4911{
4912 struct ata_port *ap;
4913 unsigned int i;
4914
4915 for (i = 0; i < host_set->n_ports; i++) {
4916 ap = host_set->ports[i];
4917 scsi_remove_host(ap->host);
4918 }
4919
4920 free_irq(host_set->irq, host_set);
4921
4922 for (i = 0; i < host_set->n_ports; i++) {
4923 ap = host_set->ports[i];
4924
4925 ata_scsi_release(ap->host);
4926
4927 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
4928 struct ata_ioports *ioaddr = &ap->ioaddr;
4929
4930 if (ioaddr->cmd_addr == 0x1f0)
4931 release_region(0x1f0, 8);
4932 else if (ioaddr->cmd_addr == 0x170)
4933 release_region(0x170, 8);
4934 }
4935
4936 scsi_host_put(ap->host);
4937 }
4938
4939 if (host_set->ops->host_stop)
4940 host_set->ops->host_stop(host_set);
4941
4942 kfree(host_set);
4943}
4944
1da177e4
LT		 4945/**
4946 * ata_scsi_release - SCSI layer callback hook for host unload
4947 * @host: libata host to be unloaded
4948 *
4949 * Performs all duties necessary to shut down a libata port...
4950 * Kill port kthread, disable port, and release resources.
4951 *
4952 * LOCKING:
4953 * Inherited from SCSI layer.
4954 *
4955 * RETURNS:
4956 * One.
4957 */
4958
4959int ata_scsi_release(struct Scsi_Host *host)
4960{
4961 struct ata_port *ap = (struct ata_port *) &host->hostdata[0];
4962
4963 DPRINTK("ENTER\n");
4964
4965 ap->ops->port_disable(ap);
4966 ata_host_remove(ap, 0);
4967
4968 DPRINTK("EXIT\n");
4969 return 1;
4970}
4971
4972/**
4973 * ata_std_ports - initialize ioaddr with standard port offsets.
4974 * @ioaddr: IO address structure to be initialized
0baab86b
EF		 4975 *
4976 * Utility function which initializes data_addr, error_addr,
4977 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
4978 * device_addr, status_addr, and command_addr to standard offsets
4979 * relative to cmd_addr.
4980 *
4981 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 4982 */
0baab86b 4983
1da177e4
LT		 4984void ata_std_ports(struct ata_ioports *ioaddr)
4985{
4986 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
4987 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
4988 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
4989 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
4990 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
4991 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
4992 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
4993 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
4994 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
4995 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
4996}
4997
0baab86b 4998
374b1873
JG		 4999#ifdef CONFIG_PCI
5000
5001void ata_pci_host_stop (struct ata_host_set *host_set)
5002{
5003 struct pci_dev *pdev = to_pci_dev(host_set->dev);
5004
5005 pci_iounmap(pdev, host_set->mmio_base);
5006}
5007
1da177e4
LT		 5008/**
5009 * ata_pci_remove_one - PCI layer callback for device removal
5010 * @pdev: PCI device that was removed
5011 *
5012 * PCI layer indicates to libata via this hook that
6f0ef4fa 5013 * hot-unplug or module unload event has occurred.
1da177e4
LT		 5014 * Handle this by unregistering all objects associated
5015 * with this PCI device. Free those objects. Then finally
5016 * release PCI resources and disable device.
5017 *
5018 * LOCKING:
5019 * Inherited from PCI layer (may sleep).
5020 */
5021
5022void ata_pci_remove_one (struct pci_dev *pdev)
5023{
5024 struct device *dev = pci_dev_to_dev(pdev);
5025 struct ata_host_set *host_set = dev_get_drvdata(dev);
1da177e4 5026
17b14451 5027 ata_host_set_remove(host_set);
1da177e4
LT		 5028 pci_release_regions(pdev);
5029 pci_disable_device(pdev);
5030 dev_set_drvdata(dev, NULL);
5031}
5032
5033/* move to PCI subsystem */
057ace5e 5034int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT		 5035{
5036 unsigned long tmp = 0;
5037
5038 switch (bits->width) {
5039 case 1: {
5040 u8 tmp8 = 0;
5041 pci_read_config_byte(pdev, bits->reg, &tmp8);
5042 tmp = tmp8;
5043 break;
5044 }
5045 case 2: {
5046 u16 tmp16 = 0;
5047 pci_read_config_word(pdev, bits->reg, &tmp16);
5048 tmp = tmp16;
5049 break;
5050 }
5051 case 4: {
5052 u32 tmp32 = 0;
5053 pci_read_config_dword(pdev, bits->reg, &tmp32);
5054 tmp = tmp32;
5055 break;
5056 }
5057
5058 default:
5059 return -EINVAL;
5060 }
5061
5062 tmp &= bits->mask;
5063
5064 return (tmp == bits->val) ? 1 : 0;
5065}
9b847548
JA		 5066
5067int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t state)
5068{
5069 pci_save_state(pdev);
5070 pci_disable_device(pdev);
5071 pci_set_power_state(pdev, PCI_D3hot);
5072 return 0;
5073}
5074
5075int ata_pci_device_resume(struct pci_dev *pdev)
5076{
5077 pci_set_power_state(pdev, PCI_D0);
5078 pci_restore_state(pdev);
5079 pci_enable_device(pdev);
5080 pci_set_master(pdev);
5081 return 0;
5082}
1da177e4
LT		 5083#endif /* CONFIG_PCI */
5084
5085
1da177e4
LT		 5086static int __init ata_init(void)
5087{
5088 ata_wq = create_workqueue("ata");
5089 if (!ata_wq)
5090 return -ENOMEM;
5091
5092 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
5093 return 0;
5094}
5095
5096static void __exit ata_exit(void)
5097{
5098 destroy_workqueue(ata_wq);
5099}
5100
5101module_init(ata_init);
5102module_exit(ata_exit);
5103
67846b30
JG		 5104static unsigned long ratelimit_time;
5105static spinlock_t ata_ratelimit_lock = SPIN_LOCK_UNLOCKED;
5106
5107int ata_ratelimit(void)
5108{
5109 int rc;
5110 unsigned long flags;
5111
5112 spin_lock_irqsave(&ata_ratelimit_lock, flags);
5113
5114 if (time_after(jiffies, ratelimit_time)) {
5115 rc = 1;
5116 ratelimit_time = jiffies + (HZ/5);
5117 } else
5118 rc = 0;
5119
5120 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
5121
5122 return rc;
5123}
5124
1da177e4
LT		 5125/*
5126 * libata is essentially a library of internal helper functions for
5127 * low-level ATA host controller drivers. As such, the API/ABI is
5128 * likely to change as new drivers are added and updated.
5129 * Do not depend on ABI/API stability.
5130 */
5131
5132EXPORT_SYMBOL_GPL(ata_std_bios_param);
5133EXPORT_SYMBOL_GPL(ata_std_ports);
5134EXPORT_SYMBOL_GPL(ata_device_add);
17b14451 5135EXPORT_SYMBOL_GPL(ata_host_set_remove);
1da177e4
LT		 5136EXPORT_SYMBOL_GPL(ata_sg_init);
5137EXPORT_SYMBOL_GPL(ata_sg_init_one);
76014427 5138EXPORT_SYMBOL_GPL(__ata_qc_complete);
1da177e4
LT		 5139EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
5140EXPORT_SYMBOL_GPL(ata_eng_timeout);
5141EXPORT_SYMBOL_GPL(ata_tf_load);
5142EXPORT_SYMBOL_GPL(ata_tf_read);
5143EXPORT_SYMBOL_GPL(ata_noop_dev_select);
5144EXPORT_SYMBOL_GPL(ata_std_dev_select);
5145EXPORT_SYMBOL_GPL(ata_tf_to_fis);
5146EXPORT_SYMBOL_GPL(ata_tf_from_fis);
5147EXPORT_SYMBOL_GPL(ata_check_status);
5148EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT		 5149EXPORT_SYMBOL_GPL(ata_exec_command);
5150EXPORT_SYMBOL_GPL(ata_port_start);
5151EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 5152EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4
LT		 5153EXPORT_SYMBOL_GPL(ata_interrupt);
5154EXPORT_SYMBOL_GPL(ata_qc_prep);
5155EXPORT_SYMBOL_GPL(ata_bmdma_setup);
5156EXPORT_SYMBOL_GPL(ata_bmdma_start);
5157EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
5158EXPORT_SYMBOL_GPL(ata_bmdma_status);
5159EXPORT_SYMBOL_GPL(ata_bmdma_stop);
5160EXPORT_SYMBOL_GPL(ata_port_probe);
5161EXPORT_SYMBOL_GPL(sata_phy_reset);
5162EXPORT_SYMBOL_GPL(__sata_phy_reset);
5163EXPORT_SYMBOL_GPL(ata_bus_reset);
8a19ac89 5164EXPORT_SYMBOL_GPL(ata_std_probeinit);
c2bd5804
TH		 5165EXPORT_SYMBOL_GPL(ata_std_softreset);
5166EXPORT_SYMBOL_GPL(sata_std_hardreset);
5167EXPORT_SYMBOL_GPL(ata_std_postreset);
5168EXPORT_SYMBOL_GPL(ata_std_probe_reset);
a62c0fc5 5169EXPORT_SYMBOL_GPL(ata_drive_probe_reset);
1da177e4 5170EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 5171EXPORT_SYMBOL_GPL(ata_ratelimit);
6f8b9958 5172EXPORT_SYMBOL_GPL(ata_busy_sleep);
1da177e4
LT		 5173EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
5174EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
f29841e0 5175EXPORT_SYMBOL_GPL(ata_scsi_timed_out);
1da177e4
LT		 5176EXPORT_SYMBOL_GPL(ata_scsi_error);
5177EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
5178EXPORT_SYMBOL_GPL(ata_scsi_release);
5179EXPORT_SYMBOL_GPL(ata_host_intr);
5180EXPORT_SYMBOL_GPL(ata_dev_classify);
5181EXPORT_SYMBOL_GPL(ata_dev_id_string);
6f2f3812 5182EXPORT_SYMBOL_GPL(ata_dev_config);
1da177e4 5183EXPORT_SYMBOL_GPL(ata_scsi_simulate);
a72ec4ce
TH		 5184EXPORT_SYMBOL_GPL(ata_eh_qc_complete);
5185EXPORT_SYMBOL_GPL(ata_eh_qc_retry);
1da177e4 5186
1bc4ccff 5187EXPORT_SYMBOL_GPL(ata_pio_need_iordy);
452503f9
AC		 5188EXPORT_SYMBOL_GPL(ata_timing_compute);
5189EXPORT_SYMBOL_GPL(ata_timing_merge);
5190
1da177e4
LT		 5191#ifdef CONFIG_PCI
5192EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 5193EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT		 5194EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
5195EXPORT_SYMBOL_GPL(ata_pci_init_one);
5196EXPORT_SYMBOL_GPL(ata_pci_remove_one);
9b847548
JA		 5197EXPORT_SYMBOL_GPL(ata_pci_device_suspend);
5198EXPORT_SYMBOL_GPL(ata_pci_device_resume);
1da177e4 5199#endif /* CONFIG_PCI */
9b847548
JA		 5200
5201EXPORT_SYMBOL_GPL(ata_device_suspend);
5202EXPORT_SYMBOL_GPL(ata_device_resume);
5203EXPORT_SYMBOL_GPL(ata_scsi_device_suspend);
5204EXPORT_SYMBOL_GPL(ata_scsi_device_resume);
Linux kernel - Deliverables
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