[PATCH] libata: add probeinit component operation to ata_drive_probe_reset()
[deliverable/linux.git] / drivers / scsi / libata-core.c
CommitLineData
1da177e4 1/*
af36d7f0
JG
2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT
33 */
34
35#include <linux/config.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/list.h>
41#include <linux/mm.h>
42#include <linux/highmem.h>
43#include <linux/spinlock.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/timer.h>
47#include <linux/interrupt.h>
48#include <linux/completion.h>
49#include <linux/suspend.h>
50#include <linux/workqueue.h>
67846b30 51#include <linux/jiffies.h>
378f058c 52#include <linux/scatterlist.h>
1da177e4 53#include <scsi/scsi.h>
1da177e4 54#include "scsi_priv.h"
193515d5 55#include <scsi/scsi_cmnd.h>
1da177e4
LT
56#include <scsi/scsi_host.h>
57#include <linux/libata.h>
58#include <asm/io.h>
59#include <asm/semaphore.h>
60#include <asm/byteorder.h>
61
62#include "libata.h"
63
59a10b17 64static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev);
8bf62ece 65static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev);
1da177e4
LT
66static void ata_set_mode(struct ata_port *ap);
67static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev);
057ace5e 68static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift);
1da177e4 69static int fgb(u32 bitmap);
057ace5e 70static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT
71 u8 *xfer_mode_out,
72 unsigned int *xfer_shift_out);
1da177e4
LT
73
74static unsigned int ata_unique_id = 1;
75static struct workqueue_struct *ata_wq;
76
1623c81e
JG
77int atapi_enabled = 0;
78module_param(atapi_enabled, int, 0444);
79MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
80
1da177e4
LT
81MODULE_AUTHOR("Jeff Garzik");
82MODULE_DESCRIPTION("Library module for ATA devices");
83MODULE_LICENSE("GPL");
84MODULE_VERSION(DRV_VERSION);
85
86/**
6f0ef4fa 87 * ata_tf_load_pio - send taskfile registers to host controller
1da177e4
LT
88 * @ap: Port to which output is sent
89 * @tf: ATA taskfile register set
90 *
91 * Outputs ATA taskfile to standard ATA host controller.
92 *
93 * LOCKING:
94 * Inherited from caller.
95 */
96
057ace5e 97static void ata_tf_load_pio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT
98{
99 struct ata_ioports *ioaddr = &ap->ioaddr;
100 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
101
102 if (tf->ctl != ap->last_ctl) {
103 outb(tf->ctl, ioaddr->ctl_addr);
104 ap->last_ctl = tf->ctl;
105 ata_wait_idle(ap);
106 }
107
108 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
109 outb(tf->hob_feature, ioaddr->feature_addr);
110 outb(tf->hob_nsect, ioaddr->nsect_addr);
111 outb(tf->hob_lbal, ioaddr->lbal_addr);
112 outb(tf->hob_lbam, ioaddr->lbam_addr);
113 outb(tf->hob_lbah, ioaddr->lbah_addr);
114 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
115 tf->hob_feature,
116 tf->hob_nsect,
117 tf->hob_lbal,
118 tf->hob_lbam,
119 tf->hob_lbah);
120 }
121
122 if (is_addr) {
123 outb(tf->feature, ioaddr->feature_addr);
124 outb(tf->nsect, ioaddr->nsect_addr);
125 outb(tf->lbal, ioaddr->lbal_addr);
126 outb(tf->lbam, ioaddr->lbam_addr);
127 outb(tf->lbah, ioaddr->lbah_addr);
128 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
129 tf->feature,
130 tf->nsect,
131 tf->lbal,
132 tf->lbam,
133 tf->lbah);
134 }
135
136 if (tf->flags & ATA_TFLAG_DEVICE) {
137 outb(tf->device, ioaddr->device_addr);
138 VPRINTK("device 0x%X\n", tf->device);
139 }
140
141 ata_wait_idle(ap);
142}
143
144/**
145 * ata_tf_load_mmio - send taskfile registers to host controller
146 * @ap: Port to which output is sent
147 * @tf: ATA taskfile register set
148 *
149 * Outputs ATA taskfile to standard ATA host controller using MMIO.
150 *
151 * LOCKING:
152 * Inherited from caller.
153 */
154
057ace5e 155static void ata_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT
156{
157 struct ata_ioports *ioaddr = &ap->ioaddr;
158 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
159
160 if (tf->ctl != ap->last_ctl) {
161 writeb(tf->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
162 ap->last_ctl = tf->ctl;
163 ata_wait_idle(ap);
164 }
165
166 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
167 writeb(tf->hob_feature, (void __iomem *) ioaddr->feature_addr);
168 writeb(tf->hob_nsect, (void __iomem *) ioaddr->nsect_addr);
169 writeb(tf->hob_lbal, (void __iomem *) ioaddr->lbal_addr);
170 writeb(tf->hob_lbam, (void __iomem *) ioaddr->lbam_addr);
171 writeb(tf->hob_lbah, (void __iomem *) ioaddr->lbah_addr);
172 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
173 tf->hob_feature,
174 tf->hob_nsect,
175 tf->hob_lbal,
176 tf->hob_lbam,
177 tf->hob_lbah);
178 }
179
180 if (is_addr) {
181 writeb(tf->feature, (void __iomem *) ioaddr->feature_addr);
182 writeb(tf->nsect, (void __iomem *) ioaddr->nsect_addr);
183 writeb(tf->lbal, (void __iomem *) ioaddr->lbal_addr);
184 writeb(tf->lbam, (void __iomem *) ioaddr->lbam_addr);
185 writeb(tf->lbah, (void __iomem *) ioaddr->lbah_addr);
186 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
187 tf->feature,
188 tf->nsect,
189 tf->lbal,
190 tf->lbam,
191 tf->lbah);
192 }
193
194 if (tf->flags & ATA_TFLAG_DEVICE) {
195 writeb(tf->device, (void __iomem *) ioaddr->device_addr);
196 VPRINTK("device 0x%X\n", tf->device);
197 }
198
199 ata_wait_idle(ap);
200}
201
0baab86b
EF
202
203/**
204 * ata_tf_load - send taskfile registers to host controller
205 * @ap: Port to which output is sent
206 * @tf: ATA taskfile register set
207 *
208 * Outputs ATA taskfile to standard ATA host controller using MMIO
209 * or PIO as indicated by the ATA_FLAG_MMIO flag.
210 * Writes the control, feature, nsect, lbal, lbam, and lbah registers.
211 * Optionally (ATA_TFLAG_LBA48) writes hob_feature, hob_nsect,
212 * hob_lbal, hob_lbam, and hob_lbah.
213 *
214 * This function waits for idle (!BUSY and !DRQ) after writing
215 * registers. If the control register has a new value, this
216 * function also waits for idle after writing control and before
217 * writing the remaining registers.
218 *
219 * May be used as the tf_load() entry in ata_port_operations.
220 *
221 * LOCKING:
222 * Inherited from caller.
223 */
057ace5e 224void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT
225{
226 if (ap->flags & ATA_FLAG_MMIO)
227 ata_tf_load_mmio(ap, tf);
228 else
229 ata_tf_load_pio(ap, tf);
230}
231
232/**
0baab86b 233 * ata_exec_command_pio - issue ATA command to host controller
1da177e4
LT
234 * @ap: port to which command is being issued
235 * @tf: ATA taskfile register set
236 *
0baab86b 237 * Issues PIO write to ATA command register, with proper
1da177e4
LT
238 * synchronization with interrupt handler / other threads.
239 *
240 * LOCKING:
241 * spin_lock_irqsave(host_set lock)
242 */
243
057ace5e 244static void ata_exec_command_pio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT
245{
246 DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command);
247
248 outb(tf->command, ap->ioaddr.command_addr);
249 ata_pause(ap);
250}
251
252
253/**
254 * ata_exec_command_mmio - issue ATA command to host controller
255 * @ap: port to which command is being issued
256 * @tf: ATA taskfile register set
257 *
258 * Issues MMIO write to ATA command register, with proper
259 * synchronization with interrupt handler / other threads.
260 *
261 * LOCKING:
262 * spin_lock_irqsave(host_set lock)
263 */
264
057ace5e 265static void ata_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT
266{
267 DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command);
268
269 writeb(tf->command, (void __iomem *) ap->ioaddr.command_addr);
270 ata_pause(ap);
271}
272
0baab86b
EF
273
274/**
275 * ata_exec_command - issue ATA command to host controller
276 * @ap: port to which command is being issued
277 * @tf: ATA taskfile register set
278 *
279 * Issues PIO/MMIO write to ATA command register, with proper
280 * synchronization with interrupt handler / other threads.
281 *
282 * LOCKING:
283 * spin_lock_irqsave(host_set lock)
284 */
057ace5e 285void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT
286{
287 if (ap->flags & ATA_FLAG_MMIO)
288 ata_exec_command_mmio(ap, tf);
289 else
290 ata_exec_command_pio(ap, tf);
291}
292
1da177e4
LT
293/**
294 * ata_tf_to_host - issue ATA taskfile to host controller
295 * @ap: port to which command is being issued
296 * @tf: ATA taskfile register set
297 *
298 * Issues ATA taskfile register set to ATA host controller,
299 * with proper synchronization with interrupt handler and
300 * other threads.
301 *
302 * LOCKING:
1da177e4
LT
303 * spin_lock_irqsave(host_set lock)
304 */
305
e5338254
JG
306static inline void ata_tf_to_host(struct ata_port *ap,
307 const struct ata_taskfile *tf)
1da177e4
LT
308{
309 ap->ops->tf_load(ap, tf);
310 ap->ops->exec_command(ap, tf);
311}
312
313/**
0baab86b 314 * ata_tf_read_pio - input device's ATA taskfile shadow registers
1da177e4
LT
315 * @ap: Port from which input is read
316 * @tf: ATA taskfile register set for storing input
317 *
318 * Reads ATA taskfile registers for currently-selected device
319 * into @tf.
320 *
321 * LOCKING:
322 * Inherited from caller.
323 */
324
325static void ata_tf_read_pio(struct ata_port *ap, struct ata_taskfile *tf)
326{
327 struct ata_ioports *ioaddr = &ap->ioaddr;
328
ac19bff2 329 tf->command = ata_check_status(ap);
0169e284 330 tf->feature = inb(ioaddr->error_addr);
1da177e4
LT
331 tf->nsect = inb(ioaddr->nsect_addr);
332 tf->lbal = inb(ioaddr->lbal_addr);
333 tf->lbam = inb(ioaddr->lbam_addr);
334 tf->lbah = inb(ioaddr->lbah_addr);
335 tf->device = inb(ioaddr->device_addr);
336
337 if (tf->flags & ATA_TFLAG_LBA48) {
338 outb(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
339 tf->hob_feature = inb(ioaddr->error_addr);
340 tf->hob_nsect = inb(ioaddr->nsect_addr);
341 tf->hob_lbal = inb(ioaddr->lbal_addr);
342 tf->hob_lbam = inb(ioaddr->lbam_addr);
343 tf->hob_lbah = inb(ioaddr->lbah_addr);
344 }
345}
346
347/**
348 * ata_tf_read_mmio - input device's ATA taskfile shadow registers
349 * @ap: Port from which input is read
350 * @tf: ATA taskfile register set for storing input
351 *
352 * Reads ATA taskfile registers for currently-selected device
353 * into @tf via MMIO.
354 *
355 * LOCKING:
356 * Inherited from caller.
357 */
358
359static void ata_tf_read_mmio(struct ata_port *ap, struct ata_taskfile *tf)
360{
361 struct ata_ioports *ioaddr = &ap->ioaddr;
362
ac19bff2 363 tf->command = ata_check_status(ap);
0169e284 364 tf->feature = readb((void __iomem *)ioaddr->error_addr);
1da177e4
LT
365 tf->nsect = readb((void __iomem *)ioaddr->nsect_addr);
366 tf->lbal = readb((void __iomem *)ioaddr->lbal_addr);
367 tf->lbam = readb((void __iomem *)ioaddr->lbam_addr);
368 tf->lbah = readb((void __iomem *)ioaddr->lbah_addr);
369 tf->device = readb((void __iomem *)ioaddr->device_addr);
370
371 if (tf->flags & ATA_TFLAG_LBA48) {
372 writeb(tf->ctl | ATA_HOB, (void __iomem *) ap->ioaddr.ctl_addr);
373 tf->hob_feature = readb((void __iomem *)ioaddr->error_addr);
374 tf->hob_nsect = readb((void __iomem *)ioaddr->nsect_addr);
375 tf->hob_lbal = readb((void __iomem *)ioaddr->lbal_addr);
376 tf->hob_lbam = readb((void __iomem *)ioaddr->lbam_addr);
377 tf->hob_lbah = readb((void __iomem *)ioaddr->lbah_addr);
378 }
379}
380
0baab86b
EF
381
382/**
383 * ata_tf_read - input device's ATA taskfile shadow registers
384 * @ap: Port from which input is read
385 * @tf: ATA taskfile register set for storing input
386 *
387 * Reads ATA taskfile registers for currently-selected device
388 * into @tf.
389 *
390 * Reads nsect, lbal, lbam, lbah, and device. If ATA_TFLAG_LBA48
391 * is set, also reads the hob registers.
392 *
393 * May be used as the tf_read() entry in ata_port_operations.
394 *
395 * LOCKING:
396 * Inherited from caller.
397 */
1da177e4
LT
398void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
399{
400 if (ap->flags & ATA_FLAG_MMIO)
401 ata_tf_read_mmio(ap, tf);
402 else
403 ata_tf_read_pio(ap, tf);
404}
405
406/**
407 * ata_check_status_pio - Read device status reg & clear interrupt
408 * @ap: port where the device is
409 *
410 * Reads ATA taskfile status register for currently-selected device
0baab86b 411 * and return its value. This also clears pending interrupts
1da177e4
LT
412 * from this device
413 *
414 * LOCKING:
415 * Inherited from caller.
416 */
417static u8 ata_check_status_pio(struct ata_port *ap)
418{
419 return inb(ap->ioaddr.status_addr);
420}
421
422/**
423 * ata_check_status_mmio - Read device status reg & clear interrupt
424 * @ap: port where the device is
425 *
426 * Reads ATA taskfile status register for currently-selected device
0baab86b 427 * via MMIO and return its value. This also clears pending interrupts
1da177e4
LT
428 * from this device
429 *
430 * LOCKING:
431 * Inherited from caller.
432 */
433static u8 ata_check_status_mmio(struct ata_port *ap)
434{
435 return readb((void __iomem *) ap->ioaddr.status_addr);
436}
437
0baab86b
EF
438
439/**
440 * ata_check_status - Read device status reg & clear interrupt
441 * @ap: port where the device is
442 *
443 * Reads ATA taskfile status register for currently-selected device
444 * and return its value. This also clears pending interrupts
445 * from this device
446 *
447 * May be used as the check_status() entry in ata_port_operations.
448 *
449 * LOCKING:
450 * Inherited from caller.
451 */
1da177e4
LT
452u8 ata_check_status(struct ata_port *ap)
453{
454 if (ap->flags & ATA_FLAG_MMIO)
455 return ata_check_status_mmio(ap);
456 return ata_check_status_pio(ap);
457}
458
0baab86b
EF
459
460/**
461 * ata_altstatus - Read device alternate status reg
462 * @ap: port where the device is
463 *
464 * Reads ATA taskfile alternate status register for
465 * currently-selected device and return its value.
466 *
467 * Note: may NOT be used as the check_altstatus() entry in
468 * ata_port_operations.
469 *
470 * LOCKING:
471 * Inherited from caller.
472 */
1da177e4
LT
473u8 ata_altstatus(struct ata_port *ap)
474{
475 if (ap->ops->check_altstatus)
476 return ap->ops->check_altstatus(ap);
477
478 if (ap->flags & ATA_FLAG_MMIO)
479 return readb((void __iomem *)ap->ioaddr.altstatus_addr);
480 return inb(ap->ioaddr.altstatus_addr);
481}
482
0baab86b 483
1da177e4
LT
484/**
485 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
486 * @tf: Taskfile to convert
487 * @fis: Buffer into which data will output
488 * @pmp: Port multiplier port
489 *
490 * Converts a standard ATA taskfile to a Serial ATA
491 * FIS structure (Register - Host to Device).
492 *
493 * LOCKING:
494 * Inherited from caller.
495 */
496
057ace5e 497void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT
498{
499 fis[0] = 0x27; /* Register - Host to Device FIS */
500 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
501 bit 7 indicates Command FIS */
502 fis[2] = tf->command;
503 fis[3] = tf->feature;
504
505 fis[4] = tf->lbal;
506 fis[5] = tf->lbam;
507 fis[6] = tf->lbah;
508 fis[7] = tf->device;
509
510 fis[8] = tf->hob_lbal;
511 fis[9] = tf->hob_lbam;
512 fis[10] = tf->hob_lbah;
513 fis[11] = tf->hob_feature;
514
515 fis[12] = tf->nsect;
516 fis[13] = tf->hob_nsect;
517 fis[14] = 0;
518 fis[15] = tf->ctl;
519
520 fis[16] = 0;
521 fis[17] = 0;
522 fis[18] = 0;
523 fis[19] = 0;
524}
525
526/**
527 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
528 * @fis: Buffer from which data will be input
529 * @tf: Taskfile to output
530 *
e12a1be6 531 * Converts a serial ATA FIS structure to a standard ATA taskfile.
1da177e4
LT
532 *
533 * LOCKING:
534 * Inherited from caller.
535 */
536
057ace5e 537void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT
538{
539 tf->command = fis[2]; /* status */
540 tf->feature = fis[3]; /* error */
541
542 tf->lbal = fis[4];
543 tf->lbam = fis[5];
544 tf->lbah = fis[6];
545 tf->device = fis[7];
546
547 tf->hob_lbal = fis[8];
548 tf->hob_lbam = fis[9];
549 tf->hob_lbah = fis[10];
550
551 tf->nsect = fis[12];
552 tf->hob_nsect = fis[13];
553}
554
8cbd6df1
AL
555static const u8 ata_rw_cmds[] = {
556 /* pio multi */
557 ATA_CMD_READ_MULTI,
558 ATA_CMD_WRITE_MULTI,
559 ATA_CMD_READ_MULTI_EXT,
560 ATA_CMD_WRITE_MULTI_EXT,
9a3dccc4
TH
561 0,
562 0,
563 0,
564 ATA_CMD_WRITE_MULTI_FUA_EXT,
8cbd6df1
AL
565 /* pio */
566 ATA_CMD_PIO_READ,
567 ATA_CMD_PIO_WRITE,
568 ATA_CMD_PIO_READ_EXT,
569 ATA_CMD_PIO_WRITE_EXT,
9a3dccc4
TH
570 0,
571 0,
572 0,
573 0,
8cbd6df1
AL
574 /* dma */
575 ATA_CMD_READ,
576 ATA_CMD_WRITE,
577 ATA_CMD_READ_EXT,
9a3dccc4
TH
578 ATA_CMD_WRITE_EXT,
579 0,
580 0,
581 0,
582 ATA_CMD_WRITE_FUA_EXT
8cbd6df1 583};
1da177e4
LT
584
585/**
8cbd6df1
AL
586 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
587 * @qc: command to examine and configure
1da177e4 588 *
8cbd6df1
AL
589 * Examine the device configuration and tf->flags to calculate
590 * the proper read/write commands and protocol to use.
1da177e4
LT
591 *
592 * LOCKING:
593 * caller.
594 */
9a3dccc4 595int ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 596{
8cbd6df1
AL
597 struct ata_taskfile *tf = &qc->tf;
598 struct ata_device *dev = qc->dev;
9a3dccc4 599 u8 cmd;
1da177e4 600
9a3dccc4 601 int index, fua, lba48, write;
8cbd6df1 602
9a3dccc4 603 fua = (tf->flags & ATA_TFLAG_FUA) ? 4 : 0;
8cbd6df1
AL
604 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
605 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 606
8cbd6df1
AL
607 if (dev->flags & ATA_DFLAG_PIO) {
608 tf->protocol = ATA_PROT_PIO;
9a3dccc4 609 index = dev->multi_count ? 0 : 8;
8d238e01
AC
610 } else if (lba48 && (qc->ap->flags & ATA_FLAG_PIO_LBA48)) {
611 /* Unable to use DMA due to host limitation */
612 tf->protocol = ATA_PROT_PIO;
613 index = dev->multi_count ? 0 : 4;
8cbd6df1
AL
614 } else {
615 tf->protocol = ATA_PROT_DMA;
9a3dccc4 616 index = 16;
8cbd6df1 617 }
1da177e4 618
9a3dccc4
TH
619 cmd = ata_rw_cmds[index + fua + lba48 + write];
620 if (cmd) {
621 tf->command = cmd;
622 return 0;
623 }
624 return -1;
1da177e4
LT
625}
626
98ac62de 627static const char * const xfer_mode_str[] = {
1da177e4
LT
628 "UDMA/16",
629 "UDMA/25",
630 "UDMA/33",
631 "UDMA/44",
632 "UDMA/66",
633 "UDMA/100",
634 "UDMA/133",
635 "UDMA7",
636 "MWDMA0",
637 "MWDMA1",
638 "MWDMA2",
639 "PIO0",
640 "PIO1",
641 "PIO2",
642 "PIO3",
643 "PIO4",
644};
645
646/**
647 * ata_udma_string - convert UDMA bit offset to string
648 * @mask: mask of bits supported; only highest bit counts.
649 *
650 * Determine string which represents the highest speed
651 * (highest bit in @udma_mask).
652 *
653 * LOCKING:
654 * None.
655 *
656 * RETURNS:
657 * Constant C string representing highest speed listed in
658 * @udma_mask, or the constant C string "<n/a>".
659 */
660
661static const char *ata_mode_string(unsigned int mask)
662{
663 int i;
664
665 for (i = 7; i >= 0; i--)
666 if (mask & (1 << i))
667 goto out;
668 for (i = ATA_SHIFT_MWDMA + 2; i >= ATA_SHIFT_MWDMA; i--)
669 if (mask & (1 << i))
670 goto out;
671 for (i = ATA_SHIFT_PIO + 4; i >= ATA_SHIFT_PIO; i--)
672 if (mask & (1 << i))
673 goto out;
674
675 return "<n/a>";
676
677out:
678 return xfer_mode_str[i];
679}
680
681/**
682 * ata_pio_devchk - PATA device presence detection
683 * @ap: ATA channel to examine
684 * @device: Device to examine (starting at zero)
685 *
686 * This technique was originally described in
687 * Hale Landis's ATADRVR (www.ata-atapi.com), and
688 * later found its way into the ATA/ATAPI spec.
689 *
690 * Write a pattern to the ATA shadow registers,
691 * and if a device is present, it will respond by
692 * correctly storing and echoing back the
693 * ATA shadow register contents.
694 *
695 * LOCKING:
696 * caller.
697 */
698
699static unsigned int ata_pio_devchk(struct ata_port *ap,
700 unsigned int device)
701{
702 struct ata_ioports *ioaddr = &ap->ioaddr;
703 u8 nsect, lbal;
704
705 ap->ops->dev_select(ap, device);
706
707 outb(0x55, ioaddr->nsect_addr);
708 outb(0xaa, ioaddr->lbal_addr);
709
710 outb(0xaa, ioaddr->nsect_addr);
711 outb(0x55, ioaddr->lbal_addr);
712
713 outb(0x55, ioaddr->nsect_addr);
714 outb(0xaa, ioaddr->lbal_addr);
715
716 nsect = inb(ioaddr->nsect_addr);
717 lbal = inb(ioaddr->lbal_addr);
718
719 if ((nsect == 0x55) && (lbal == 0xaa))
720 return 1; /* we found a device */
721
722 return 0; /* nothing found */
723}
724
725/**
726 * ata_mmio_devchk - PATA device presence detection
727 * @ap: ATA channel to examine
728 * @device: Device to examine (starting at zero)
729 *
730 * This technique was originally described in
731 * Hale Landis's ATADRVR (www.ata-atapi.com), and
732 * later found its way into the ATA/ATAPI spec.
733 *
734 * Write a pattern to the ATA shadow registers,
735 * and if a device is present, it will respond by
736 * correctly storing and echoing back the
737 * ATA shadow register contents.
738 *
739 * LOCKING:
740 * caller.
741 */
742
743static unsigned int ata_mmio_devchk(struct ata_port *ap,
744 unsigned int device)
745{
746 struct ata_ioports *ioaddr = &ap->ioaddr;
747 u8 nsect, lbal;
748
749 ap->ops->dev_select(ap, device);
750
751 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
752 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
753
754 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
755 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
756
757 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
758 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
759
760 nsect = readb((void __iomem *) ioaddr->nsect_addr);
761 lbal = readb((void __iomem *) ioaddr->lbal_addr);
762
763 if ((nsect == 0x55) && (lbal == 0xaa))
764 return 1; /* we found a device */
765
766 return 0; /* nothing found */
767}
768
769/**
770 * ata_devchk - PATA device presence detection
771 * @ap: ATA channel to examine
772 * @device: Device to examine (starting at zero)
773 *
774 * Dispatch ATA device presence detection, depending
775 * on whether we are using PIO or MMIO to talk to the
776 * ATA shadow registers.
777 *
778 * LOCKING:
779 * caller.
780 */
781
782static unsigned int ata_devchk(struct ata_port *ap,
783 unsigned int device)
784{
785 if (ap->flags & ATA_FLAG_MMIO)
786 return ata_mmio_devchk(ap, device);
787 return ata_pio_devchk(ap, device);
788}
789
790/**
791 * ata_dev_classify - determine device type based on ATA-spec signature
792 * @tf: ATA taskfile register set for device to be identified
793 *
794 * Determine from taskfile register contents whether a device is
795 * ATA or ATAPI, as per "Signature and persistence" section
796 * of ATA/PI spec (volume 1, sect 5.14).
797 *
798 * LOCKING:
799 * None.
800 *
801 * RETURNS:
802 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
803 * the event of failure.
804 */
805
057ace5e 806unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT
807{
808 /* Apple's open source Darwin code hints that some devices only
809 * put a proper signature into the LBA mid/high registers,
810 * So, we only check those. It's sufficient for uniqueness.
811 */
812
813 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
814 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
815 DPRINTK("found ATA device by sig\n");
816 return ATA_DEV_ATA;
817 }
818
819 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
820 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
821 DPRINTK("found ATAPI device by sig\n");
822 return ATA_DEV_ATAPI;
823 }
824
825 DPRINTK("unknown device\n");
826 return ATA_DEV_UNKNOWN;
827}
828
829/**
830 * ata_dev_try_classify - Parse returned ATA device signature
831 * @ap: ATA channel to examine
832 * @device: Device to examine (starting at zero)
b4dc7623 833 * @r_err: Value of error register on completion
1da177e4
LT
834 *
835 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
836 * an ATA/ATAPI-defined set of values is placed in the ATA
837 * shadow registers, indicating the results of device detection
838 * and diagnostics.
839 *
840 * Select the ATA device, and read the values from the ATA shadow
841 * registers. Then parse according to the Error register value,
842 * and the spec-defined values examined by ata_dev_classify().
843 *
844 * LOCKING:
845 * caller.
b4dc7623
TH
846 *
847 * RETURNS:
848 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1da177e4
LT
849 */
850
b4dc7623
TH
851static unsigned int
852ata_dev_try_classify(struct ata_port *ap, unsigned int device, u8 *r_err)
1da177e4 853{
1da177e4
LT
854 struct ata_taskfile tf;
855 unsigned int class;
856 u8 err;
857
858 ap->ops->dev_select(ap, device);
859
860 memset(&tf, 0, sizeof(tf));
861
1da177e4 862 ap->ops->tf_read(ap, &tf);
0169e284 863 err = tf.feature;
b4dc7623
TH
864 if (r_err)
865 *r_err = err;
1da177e4
LT
866
867 /* see if device passed diags */
868 if (err == 1)
869 /* do nothing */ ;
870 else if ((device == 0) && (err == 0x81))
871 /* do nothing */ ;
872 else
b4dc7623 873 return ATA_DEV_NONE;
1da177e4 874
b4dc7623 875 /* determine if device is ATA or ATAPI */
1da177e4 876 class = ata_dev_classify(&tf);
b4dc7623 877
1da177e4 878 if (class == ATA_DEV_UNKNOWN)
b4dc7623 879 return ATA_DEV_NONE;
1da177e4 880 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
b4dc7623
TH
881 return ATA_DEV_NONE;
882 return class;
1da177e4
LT
883}
884
885/**
886 * ata_dev_id_string - Convert IDENTIFY DEVICE page into string
887 * @id: IDENTIFY DEVICE results we will examine
888 * @s: string into which data is output
889 * @ofs: offset into identify device page
890 * @len: length of string to return. must be an even number.
891 *
892 * The strings in the IDENTIFY DEVICE page are broken up into
893 * 16-bit chunks. Run through the string, and output each
894 * 8-bit chunk linearly, regardless of platform.
895 *
896 * LOCKING:
897 * caller.
898 */
899
057ace5e 900void ata_dev_id_string(const u16 *id, unsigned char *s,
1da177e4
LT
901 unsigned int ofs, unsigned int len)
902{
903 unsigned int c;
904
905 while (len > 0) {
906 c = id[ofs] >> 8;
907 *s = c;
908 s++;
909
910 c = id[ofs] & 0xff;
911 *s = c;
912 s++;
913
914 ofs++;
915 len -= 2;
916 }
917}
918
0baab86b
EF
919
920/**
921 * ata_noop_dev_select - Select device 0/1 on ATA bus
922 * @ap: ATA channel to manipulate
923 * @device: ATA device (numbered from zero) to select
924 *
925 * This function performs no actual function.
926 *
927 * May be used as the dev_select() entry in ata_port_operations.
928 *
929 * LOCKING:
930 * caller.
931 */
1da177e4
LT
932void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
933{
934}
935
0baab86b 936
1da177e4
LT
937/**
938 * ata_std_dev_select - Select device 0/1 on ATA bus
939 * @ap: ATA channel to manipulate
940 * @device: ATA device (numbered from zero) to select
941 *
942 * Use the method defined in the ATA specification to
943 * make either device 0, or device 1, active on the
0baab86b
EF
944 * ATA channel. Works with both PIO and MMIO.
945 *
946 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT
947 *
948 * LOCKING:
949 * caller.
950 */
951
952void ata_std_dev_select (struct ata_port *ap, unsigned int device)
953{
954 u8 tmp;
955
956 if (device == 0)
957 tmp = ATA_DEVICE_OBS;
958 else
959 tmp = ATA_DEVICE_OBS | ATA_DEV1;
960
961 if (ap->flags & ATA_FLAG_MMIO) {
962 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
963 } else {
964 outb(tmp, ap->ioaddr.device_addr);
965 }
966 ata_pause(ap); /* needed; also flushes, for mmio */
967}
968
969/**
970 * ata_dev_select - Select device 0/1 on ATA bus
971 * @ap: ATA channel to manipulate
972 * @device: ATA device (numbered from zero) to select
973 * @wait: non-zero to wait for Status register BSY bit to clear
974 * @can_sleep: non-zero if context allows sleeping
975 *
976 * Use the method defined in the ATA specification to
977 * make either device 0, or device 1, active on the
978 * ATA channel.
979 *
980 * This is a high-level version of ata_std_dev_select(),
981 * which additionally provides the services of inserting
982 * the proper pauses and status polling, where needed.
983 *
984 * LOCKING:
985 * caller.
986 */
987
988void ata_dev_select(struct ata_port *ap, unsigned int device,
989 unsigned int wait, unsigned int can_sleep)
990{
991 VPRINTK("ENTER, ata%u: device %u, wait %u\n",
992 ap->id, device, wait);
993
994 if (wait)
995 ata_wait_idle(ap);
996
997 ap->ops->dev_select(ap, device);
998
999 if (wait) {
1000 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
1001 msleep(150);
1002 ata_wait_idle(ap);
1003 }
1004}
1005
1006/**
1007 * ata_dump_id - IDENTIFY DEVICE info debugging output
1008 * @dev: Device whose IDENTIFY DEVICE page we will dump
1009 *
1010 * Dump selected 16-bit words from a detected device's
1011 * IDENTIFY PAGE page.
1012 *
1013 * LOCKING:
1014 * caller.
1015 */
1016
057ace5e 1017static inline void ata_dump_id(const struct ata_device *dev)
1da177e4
LT
1018{
1019 DPRINTK("49==0x%04x "
1020 "53==0x%04x "
1021 "63==0x%04x "
1022 "64==0x%04x "
1023 "75==0x%04x \n",
1024 dev->id[49],
1025 dev->id[53],
1026 dev->id[63],
1027 dev->id[64],
1028 dev->id[75]);
1029 DPRINTK("80==0x%04x "
1030 "81==0x%04x "
1031 "82==0x%04x "
1032 "83==0x%04x "
1033 "84==0x%04x \n",
1034 dev->id[80],
1035 dev->id[81],
1036 dev->id[82],
1037 dev->id[83],
1038 dev->id[84]);
1039 DPRINTK("88==0x%04x "
1040 "93==0x%04x\n",
1041 dev->id[88],
1042 dev->id[93]);
1043}
1044
11e29e21
AC
1045/*
1046 * Compute the PIO modes available for this device. This is not as
1047 * trivial as it seems if we must consider early devices correctly.
1048 *
1049 * FIXME: pre IDE drive timing (do we care ?).
1050 */
1051
057ace5e 1052static unsigned int ata_pio_modes(const struct ata_device *adev)
11e29e21
AC
1053{
1054 u16 modes;
1055
ffa29456
AC
1056 /* Usual case. Word 53 indicates word 64 is valid */
1057 if (adev->id[ATA_ID_FIELD_VALID] & (1 << 1)) {
11e29e21
AC
1058 modes = adev->id[ATA_ID_PIO_MODES] & 0x03;
1059 modes <<= 3;
1060 modes |= 0x7;
1061 return modes;
1062 }
1063
ffa29456
AC
1064 /* If word 64 isn't valid then Word 51 high byte holds the PIO timing
1065 number for the maximum. Turn it into a mask and return it */
1066 modes = (2 << ((adev->id[ATA_ID_OLD_PIO_MODES] >> 8) & 0xFF)) - 1 ;
11e29e21 1067 return modes;
ffa29456
AC
1068 /* But wait.. there's more. Design your standards by committee and
1069 you too can get a free iordy field to process. However its the
1070 speeds not the modes that are supported... Note drivers using the
1071 timing API will get this right anyway */
11e29e21
AC
1072}
1073
95064379
TH
1074static inline void
1075ata_queue_packet_task(struct ata_port *ap)
1076{
c18d06f8
TH
1077 if (!(ap->flags & ATA_FLAG_FLUSH_PIO_TASK))
1078 queue_work(ata_wq, &ap->packet_task);
95064379
TH
1079}
1080
1081static inline void
1082ata_queue_pio_task(struct ata_port *ap)
1083{
c18d06f8
TH
1084 if (!(ap->flags & ATA_FLAG_FLUSH_PIO_TASK))
1085 queue_work(ata_wq, &ap->pio_task);
95064379
TH
1086}
1087
1088static inline void
1089ata_queue_delayed_pio_task(struct ata_port *ap, unsigned long delay)
1090{
c18d06f8
TH
1091 if (!(ap->flags & ATA_FLAG_FLUSH_PIO_TASK))
1092 queue_delayed_work(ata_wq, &ap->pio_task, delay);
1093}
1094
1095/**
1096 * ata_flush_pio_tasks - Flush pio_task and packet_task
1097 * @ap: the target ata_port
1098 *
1099 * After this function completes, pio_task and packet_task are
1100 * guranteed not to be running or scheduled.
1101 *
1102 * LOCKING:
1103 * Kernel thread context (may sleep)
1104 */
1105
1106static void ata_flush_pio_tasks(struct ata_port *ap)
1107{
1108 int tmp = 0;
1109 unsigned long flags;
1110
1111 DPRINTK("ENTER\n");
1112
1113 spin_lock_irqsave(&ap->host_set->lock, flags);
1114 ap->flags |= ATA_FLAG_FLUSH_PIO_TASK;
1115 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1116
1117 DPRINTK("flush #1\n");
1118 flush_workqueue(ata_wq);
1119
1120 /*
1121 * At this point, if a task is running, it's guaranteed to see
1122 * the FLUSH flag; thus, it will never queue pio tasks again.
1123 * Cancel and flush.
1124 */
1125 tmp |= cancel_delayed_work(&ap->pio_task);
1126 tmp |= cancel_delayed_work(&ap->packet_task);
1127 if (!tmp) {
1128 DPRINTK("flush #2\n");
1129 flush_workqueue(ata_wq);
1130 }
1131
1132 spin_lock_irqsave(&ap->host_set->lock, flags);
1133 ap->flags &= ~ATA_FLAG_FLUSH_PIO_TASK;
1134 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1135
1136 DPRINTK("EXIT\n");
95064379
TH
1137}
1138
77853bf2 1139void ata_qc_complete_internal(struct ata_queued_cmd *qc)
a2a7a662 1140{
77853bf2 1141 struct completion *waiting = qc->private_data;
a2a7a662 1142
77853bf2 1143 qc->ap->ops->tf_read(qc->ap, &qc->tf);
a2a7a662 1144 complete(waiting);
a2a7a662
TH
1145}
1146
1147/**
1148 * ata_exec_internal - execute libata internal command
1149 * @ap: Port to which the command is sent
1150 * @dev: Device to which the command is sent
1151 * @tf: Taskfile registers for the command and the result
1152 * @dma_dir: Data tranfer direction of the command
1153 * @buf: Data buffer of the command
1154 * @buflen: Length of data buffer
1155 *
1156 * Executes libata internal command with timeout. @tf contains
1157 * command on entry and result on return. Timeout and error
1158 * conditions are reported via return value. No recovery action
1159 * is taken after a command times out. It's caller's duty to
1160 * clean up after timeout.
1161 *
1162 * LOCKING:
1163 * None. Should be called with kernel context, might sleep.
1164 */
1165
1166static unsigned
1167ata_exec_internal(struct ata_port *ap, struct ata_device *dev,
1168 struct ata_taskfile *tf,
1169 int dma_dir, void *buf, unsigned int buflen)
1170{
1171 u8 command = tf->command;
1172 struct ata_queued_cmd *qc;
1173 DECLARE_COMPLETION(wait);
1174 unsigned long flags;
77853bf2 1175 unsigned int err_mask;
a2a7a662
TH
1176
1177 spin_lock_irqsave(&ap->host_set->lock, flags);
1178
1179 qc = ata_qc_new_init(ap, dev);
1180 BUG_ON(qc == NULL);
1181
1182 qc->tf = *tf;
1183 qc->dma_dir = dma_dir;
1184 if (dma_dir != DMA_NONE) {
1185 ata_sg_init_one(qc, buf, buflen);
1186 qc->nsect = buflen / ATA_SECT_SIZE;
1187 }
1188
77853bf2 1189 qc->private_data = &wait;
a2a7a662
TH
1190 qc->complete_fn = ata_qc_complete_internal;
1191
9a3d9eb0
TH
1192 qc->err_mask = ata_qc_issue(qc);
1193 if (qc->err_mask)
8e436af9 1194 ata_qc_complete(qc);
a2a7a662
TH
1195
1196 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1197
1198 if (!wait_for_completion_timeout(&wait, ATA_TMOUT_INTERNAL)) {
1199 spin_lock_irqsave(&ap->host_set->lock, flags);
1200
1201 /* We're racing with irq here. If we lose, the
1202 * following test prevents us from completing the qc
1203 * again. If completion irq occurs after here but
1204 * before the caller cleans up, it will result in a
1205 * spurious interrupt. We can live with that.
1206 */
77853bf2 1207 if (qc->flags & ATA_QCFLAG_ACTIVE) {
11a56d24 1208 qc->err_mask = AC_ERR_TIMEOUT;
a2a7a662
TH
1209 ata_qc_complete(qc);
1210 printk(KERN_WARNING "ata%u: qc timeout (cmd 0x%x)\n",
1211 ap->id, command);
1212 }
1213
1214 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1215 }
1216
77853bf2
TH
1217 *tf = qc->tf;
1218 err_mask = qc->err_mask;
1219
1220 ata_qc_free(qc);
1221
1222 return err_mask;
a2a7a662
TH
1223}
1224
1bc4ccff
AC
1225/**
1226 * ata_pio_need_iordy - check if iordy needed
1227 * @adev: ATA device
1228 *
1229 * Check if the current speed of the device requires IORDY. Used
1230 * by various controllers for chip configuration.
1231 */
1232
1233unsigned int ata_pio_need_iordy(const struct ata_device *adev)
1234{
1235 int pio;
1236 int speed = adev->pio_mode - XFER_PIO_0;
1237
1238 if (speed < 2)
1239 return 0;
1240 if (speed > 2)
1241 return 1;
1242
1243 /* If we have no drive specific rule, then PIO 2 is non IORDY */
1244
1245 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE */
1246 pio = adev->id[ATA_ID_EIDE_PIO];
1247 /* Is the speed faster than the drive allows non IORDY ? */
1248 if (pio) {
1249 /* This is cycle times not frequency - watch the logic! */
1250 if (pio > 240) /* PIO2 is 240nS per cycle */
1251 return 1;
1252 return 0;
1253 }
1254 }
1255 return 0;
1256}
1257
1da177e4
LT
1258/**
1259 * ata_dev_identify - obtain IDENTIFY x DEVICE page
1260 * @ap: port on which device we wish to probe resides
1261 * @device: device bus address, starting at zero
1262 *
1263 * Following bus reset, we issue the IDENTIFY [PACKET] DEVICE
1264 * command, and read back the 512-byte device information page.
1265 * The device information page is fed to us via the standard
1266 * PIO-IN protocol, but we hand-code it here. (TODO: investigate
1267 * using standard PIO-IN paths)
1268 *
1269 * After reading the device information page, we use several
1270 * bits of information from it to initialize data structures
1271 * that will be used during the lifetime of the ata_device.
1272 * Other data from the info page is used to disqualify certain
1273 * older ATA devices we do not wish to support.
1274 *
1275 * LOCKING:
1276 * Inherited from caller. Some functions called by this function
1277 * obtain the host_set lock.
1278 */
1279
1280static void ata_dev_identify(struct ata_port *ap, unsigned int device)
1281{
1282 struct ata_device *dev = &ap->device[device];
8bf62ece 1283 unsigned int major_version;
1da177e4
LT
1284 u16 tmp;
1285 unsigned long xfer_modes;
1da177e4 1286 unsigned int using_edd;
a0123703
TH
1287 struct ata_taskfile tf;
1288 unsigned int err_mask;
1da177e4
LT
1289 int rc;
1290
1291 if (!ata_dev_present(dev)) {
1292 DPRINTK("ENTER/EXIT (host %u, dev %u) -- nodev\n",
1293 ap->id, device);
1294 return;
1295 }
1296
1297 if (ap->flags & (ATA_FLAG_SRST | ATA_FLAG_SATA_RESET))
1298 using_edd = 0;
1299 else
1300 using_edd = 1;
1301
1302 DPRINTK("ENTER, host %u, dev %u\n", ap->id, device);
1303
1304 assert (dev->class == ATA_DEV_ATA || dev->class == ATA_DEV_ATAPI ||
1305 dev->class == ATA_DEV_NONE);
1306
1307 ata_dev_select(ap, device, 1, 1); /* select device 0/1 */
1308
1da177e4 1309retry:
a0123703
TH
1310 ata_tf_init(ap, &tf, device);
1311
1da177e4 1312 if (dev->class == ATA_DEV_ATA) {
a0123703 1313 tf.command = ATA_CMD_ID_ATA;
1da177e4
LT
1314 DPRINTK("do ATA identify\n");
1315 } else {
a0123703 1316 tf.command = ATA_CMD_ID_ATAPI;
1da177e4
LT
1317 DPRINTK("do ATAPI identify\n");
1318 }
1319
a0123703 1320 tf.protocol = ATA_PROT_PIO;
1da177e4 1321
a0123703
TH
1322 err_mask = ata_exec_internal(ap, dev, &tf, DMA_FROM_DEVICE,
1323 dev->id, sizeof(dev->id));
1da177e4 1324
a0123703
TH
1325 if (err_mask) {
1326 if (err_mask & ~AC_ERR_DEV)
1327 goto err_out;
0169e284 1328
1da177e4
LT
1329 /*
1330 * arg! EDD works for all test cases, but seems to return
1331 * the ATA signature for some ATAPI devices. Until the
1332 * reason for this is found and fixed, we fix up the mess
1333 * here. If IDENTIFY DEVICE returns command aborted
1334 * (as ATAPI devices do), then we issue an
1335 * IDENTIFY PACKET DEVICE.
1336 *
1337 * ATA software reset (SRST, the default) does not appear
1338 * to have this problem.
1339 */
7c398335 1340 if ((using_edd) && (dev->class == ATA_DEV_ATA)) {
a0123703 1341 u8 err = tf.feature;
1da177e4
LT
1342 if (err & ATA_ABORTED) {
1343 dev->class = ATA_DEV_ATAPI;
1da177e4
LT
1344 goto retry;
1345 }
1346 }
1347 goto err_out;
1348 }
1349
1350 swap_buf_le16(dev->id, ATA_ID_WORDS);
1351
1352 /* print device capabilities */
1353 printk(KERN_DEBUG "ata%u: dev %u cfg "
1354 "49:%04x 82:%04x 83:%04x 84:%04x 85:%04x 86:%04x 87:%04x 88:%04x\n",
1355 ap->id, device, dev->id[49],
1356 dev->id[82], dev->id[83], dev->id[84],
1357 dev->id[85], dev->id[86], dev->id[87],
1358 dev->id[88]);
1359
1360 /*
1361 * common ATA, ATAPI feature tests
1362 */
1363
8bf62ece
AL
1364 /* we require DMA support (bits 8 of word 49) */
1365 if (!ata_id_has_dma(dev->id)) {
1366 printk(KERN_DEBUG "ata%u: no dma\n", ap->id);
1da177e4
LT
1367 goto err_out_nosup;
1368 }
1369
1370 /* quick-n-dirty find max transfer mode; for printk only */
1371 xfer_modes = dev->id[ATA_ID_UDMA_MODES];
1372 if (!xfer_modes)
1373 xfer_modes = (dev->id[ATA_ID_MWDMA_MODES]) << ATA_SHIFT_MWDMA;
11e29e21
AC
1374 if (!xfer_modes)
1375 xfer_modes = ata_pio_modes(dev);
1da177e4
LT
1376
1377 ata_dump_id(dev);
1378
1379 /* ATA-specific feature tests */
1380 if (dev->class == ATA_DEV_ATA) {
1381 if (!ata_id_is_ata(dev->id)) /* sanity check */
1382 goto err_out_nosup;
1383
8bf62ece 1384 /* get major version */
1da177e4 1385 tmp = dev->id[ATA_ID_MAJOR_VER];
8bf62ece
AL
1386 for (major_version = 14; major_version >= 1; major_version--)
1387 if (tmp & (1 << major_version))
1da177e4
LT
1388 break;
1389
8bf62ece
AL
1390 /*
1391 * The exact sequence expected by certain pre-ATA4 drives is:
1392 * SRST RESET
1393 * IDENTIFY
1394 * INITIALIZE DEVICE PARAMETERS
1395 * anything else..
1396 * Some drives were very specific about that exact sequence.
1397 */
59a10b17 1398 if (major_version < 4 || (!ata_id_has_lba(dev->id))) {
8bf62ece
AL
1399 ata_dev_init_params(ap, dev);
1400
59a10b17
AL
1401 /* current CHS translation info (id[53-58]) might be
1402 * changed. reread the identify device info.
1403 */
1404 ata_dev_reread_id(ap, dev);
1405 }
1406
8bf62ece
AL
1407 if (ata_id_has_lba(dev->id)) {
1408 dev->flags |= ATA_DFLAG_LBA;
1409
1410 if (ata_id_has_lba48(dev->id)) {
1411 dev->flags |= ATA_DFLAG_LBA48;
1412 dev->n_sectors = ata_id_u64(dev->id, 100);
1413 } else {
1414 dev->n_sectors = ata_id_u32(dev->id, 60);
1415 }
1416
1417 /* print device info to dmesg */
1418 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors:%s\n",
1419 ap->id, device,
1420 major_version,
1421 ata_mode_string(xfer_modes),
1422 (unsigned long long)dev->n_sectors,
1423 dev->flags & ATA_DFLAG_LBA48 ? " LBA48" : " LBA");
1424 } else {
1425 /* CHS */
1426
1427 /* Default translation */
1428 dev->cylinders = dev->id[1];
1429 dev->heads = dev->id[3];
1430 dev->sectors = dev->id[6];
1431 dev->n_sectors = dev->cylinders * dev->heads * dev->sectors;
1432
1433 if (ata_id_current_chs_valid(dev->id)) {
1434 /* Current CHS translation is valid. */
1435 dev->cylinders = dev->id[54];
1436 dev->heads = dev->id[55];
1437 dev->sectors = dev->id[56];
1438
1439 dev->n_sectors = ata_id_u32(dev->id, 57);
1440 }
1441
1442 /* print device info to dmesg */
1443 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors: CHS %d/%d/%d\n",
1444 ap->id, device,
1445 major_version,
1446 ata_mode_string(xfer_modes),
1447 (unsigned long long)dev->n_sectors,
1448 (int)dev->cylinders, (int)dev->heads, (int)dev->sectors);
1da177e4 1449
1da177e4
LT
1450 }
1451
1452 ap->host->max_cmd_len = 16;
1da177e4
LT
1453 }
1454
1455 /* ATAPI-specific feature tests */
2c13b7ce 1456 else if (dev->class == ATA_DEV_ATAPI) {
1da177e4
LT
1457 if (ata_id_is_ata(dev->id)) /* sanity check */
1458 goto err_out_nosup;
1459
1460 rc = atapi_cdb_len(dev->id);
1461 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
1462 printk(KERN_WARNING "ata%u: unsupported CDB len\n", ap->id);
1463 goto err_out_nosup;
1464 }
1465 ap->cdb_len = (unsigned int) rc;
1466 ap->host->max_cmd_len = (unsigned char) ap->cdb_len;
1467
1468 /* print device info to dmesg */
1469 printk(KERN_INFO "ata%u: dev %u ATAPI, max %s\n",
1470 ap->id, device,
1471 ata_mode_string(xfer_modes));
1472 }
1473
1474 DPRINTK("EXIT, drv_stat = 0x%x\n", ata_chk_status(ap));
1475 return;
1476
1477err_out_nosup:
1478 printk(KERN_WARNING "ata%u: dev %u not supported, ignoring\n",
1479 ap->id, device);
1480err_out:
1481 dev->class++; /* converts ATA_DEV_xxx into ATA_DEV_xxx_UNSUP */
1482 DPRINTK("EXIT, err\n");
1483}
1484
6f2f3812 1485
057ace5e 1486static inline u8 ata_dev_knobble(const struct ata_port *ap)
6f2f3812
BC
1487{
1488 return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ap->device->id)));
1489}
1490
1491/**
c893a3ae
RD
1492 * ata_dev_config - Run device specific handlers & check for SATA->PATA bridges
1493 * @ap: Bus
1494 * @i: Device
6f2f3812 1495 *
c893a3ae 1496 * LOCKING:
6f2f3812 1497 */
8a60a071 1498
6f2f3812
BC
1499void ata_dev_config(struct ata_port *ap, unsigned int i)
1500{
1501 /* limit bridge transfers to udma5, 200 sectors */
1502 if (ata_dev_knobble(ap)) {
1503 printk(KERN_INFO "ata%u(%u): applying bridge limits\n",
1504 ap->id, ap->device->devno);
1505 ap->udma_mask &= ATA_UDMA5;
1506 ap->host->max_sectors = ATA_MAX_SECTORS;
1507 ap->host->hostt->max_sectors = ATA_MAX_SECTORS;
9d824d07 1508 ap->device[i].flags |= ATA_DFLAG_LOCK_SECTORS;
6f2f3812
BC
1509 }
1510
1511 if (ap->ops->dev_config)
1512 ap->ops->dev_config(ap, &ap->device[i]);
1513}
1514
1da177e4
LT
1515/**
1516 * ata_bus_probe - Reset and probe ATA bus
1517 * @ap: Bus to probe
1518 *
0cba632b
JG
1519 * Master ATA bus probing function. Initiates a hardware-dependent
1520 * bus reset, then attempts to identify any devices found on
1521 * the bus.
1522 *
1da177e4 1523 * LOCKING:
0cba632b 1524 * PCI/etc. bus probe sem.
1da177e4
LT
1525 *
1526 * RETURNS:
1527 * Zero on success, non-zero on error.
1528 */
1529
1530static int ata_bus_probe(struct ata_port *ap)
1531{
1532 unsigned int i, found = 0;
1533
c19ba8af
TH
1534 if (ap->ops->probe_reset) {
1535 unsigned int classes[ATA_MAX_DEVICES];
1536 int rc;
1537
1538 ata_port_probe(ap);
1539
1540 rc = ap->ops->probe_reset(ap, classes);
1541 if (rc == 0) {
1542 for (i = 0; i < ATA_MAX_DEVICES; i++)
1543 ap->device[i].class = classes[i];
1544 } else {
1545 printk(KERN_ERR "ata%u: probe reset failed, "
1546 "disabling port\n", ap->id);
1547 ata_port_disable(ap);
1548 }
1549 } else
1550 ap->ops->phy_reset(ap);
1551
1da177e4
LT
1552 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1553 goto err_out;
1554
1555 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1556 ata_dev_identify(ap, i);
1557 if (ata_dev_present(&ap->device[i])) {
1558 found = 1;
6f2f3812 1559 ata_dev_config(ap,i);
1da177e4
LT
1560 }
1561 }
1562
1563 if ((!found) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1564 goto err_out_disable;
1565
1566 ata_set_mode(ap);
1567 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1568 goto err_out_disable;
1569
1570 return 0;
1571
1572err_out_disable:
1573 ap->ops->port_disable(ap);
1574err_out:
1575 return -1;
1576}
1577
1578/**
0cba632b
JG
1579 * ata_port_probe - Mark port as enabled
1580 * @ap: Port for which we indicate enablement
1da177e4 1581 *
0cba632b
JG
1582 * Modify @ap data structure such that the system
1583 * thinks that the entire port is enabled.
1584 *
1585 * LOCKING: host_set lock, or some other form of
1586 * serialization.
1da177e4
LT
1587 */
1588
1589void ata_port_probe(struct ata_port *ap)
1590{
1591 ap->flags &= ~ATA_FLAG_PORT_DISABLED;
1592}
1593
3be680b7
TH
1594/**
1595 * sata_print_link_status - Print SATA link status
1596 * @ap: SATA port to printk link status about
1597 *
1598 * This function prints link speed and status of a SATA link.
1599 *
1600 * LOCKING:
1601 * None.
1602 */
1603static void sata_print_link_status(struct ata_port *ap)
1604{
1605 u32 sstatus, tmp;
1606 const char *speed;
1607
1608 if (!ap->ops->scr_read)
1609 return;
1610
1611 sstatus = scr_read(ap, SCR_STATUS);
1612
1613 if (sata_dev_present(ap)) {
1614 tmp = (sstatus >> 4) & 0xf;
1615 if (tmp & (1 << 0))
1616 speed = "1.5";
1617 else if (tmp & (1 << 1))
1618 speed = "3.0";
1619 else
1620 speed = "<unknown>";
1621 printk(KERN_INFO "ata%u: SATA link up %s Gbps (SStatus %X)\n",
1622 ap->id, speed, sstatus);
1623 } else {
1624 printk(KERN_INFO "ata%u: SATA link down (SStatus %X)\n",
1625 ap->id, sstatus);
1626 }
1627}
1628
1da177e4 1629/**
780a87f7
JG
1630 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1631 * @ap: SATA port associated with target SATA PHY.
1da177e4 1632 *
780a87f7
JG
1633 * This function issues commands to standard SATA Sxxx
1634 * PHY registers, to wake up the phy (and device), and
1635 * clear any reset condition.
1da177e4
LT
1636 *
1637 * LOCKING:
0cba632b 1638 * PCI/etc. bus probe sem.
1da177e4
LT
1639 *
1640 */
1641void __sata_phy_reset(struct ata_port *ap)
1642{
1643 u32 sstatus;
1644 unsigned long timeout = jiffies + (HZ * 5);
1645
1646 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e
BR
1647 /* issue phy wake/reset */
1648 scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH
1649 /* Couldn't find anything in SATA I/II specs, but
1650 * AHCI-1.1 10.4.2 says at least 1 ms. */
1651 mdelay(1);
1da177e4 1652 }
cdcca89e 1653 scr_write_flush(ap, SCR_CONTROL, 0x300); /* phy wake/clear reset */
1da177e4
LT
1654
1655 /* wait for phy to become ready, if necessary */
1656 do {
1657 msleep(200);
1658 sstatus = scr_read(ap, SCR_STATUS);
1659 if ((sstatus & 0xf) != 1)
1660 break;
1661 } while (time_before(jiffies, timeout));
1662
3be680b7
TH
1663 /* print link status */
1664 sata_print_link_status(ap);
656563e3 1665
3be680b7
TH
1666 /* TODO: phy layer with polling, timeouts, etc. */
1667 if (sata_dev_present(ap))
1da177e4 1668 ata_port_probe(ap);
3be680b7 1669 else
1da177e4 1670 ata_port_disable(ap);
1da177e4
LT
1671
1672 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1673 return;
1674
1675 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1676 ata_port_disable(ap);
1677 return;
1678 }
1679
1680 ap->cbl = ATA_CBL_SATA;
1681}
1682
1683/**
780a87f7
JG
1684 * sata_phy_reset - Reset SATA bus.
1685 * @ap: SATA port associated with target SATA PHY.
1da177e4 1686 *
780a87f7
JG
1687 * This function resets the SATA bus, and then probes
1688 * the bus for devices.
1da177e4
LT
1689 *
1690 * LOCKING:
0cba632b 1691 * PCI/etc. bus probe sem.
1da177e4
LT
1692 *
1693 */
1694void sata_phy_reset(struct ata_port *ap)
1695{
1696 __sata_phy_reset(ap);
1697 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1698 return;
1699 ata_bus_reset(ap);
1700}
1701
1702/**
780a87f7
JG
1703 * ata_port_disable - Disable port.
1704 * @ap: Port to be disabled.
1da177e4 1705 *
780a87f7
JG
1706 * Modify @ap data structure such that the system
1707 * thinks that the entire port is disabled, and should
1708 * never attempt to probe or communicate with devices
1709 * on this port.
1710 *
1711 * LOCKING: host_set lock, or some other form of
1712 * serialization.
1da177e4
LT
1713 */
1714
1715void ata_port_disable(struct ata_port *ap)
1716{
1717 ap->device[0].class = ATA_DEV_NONE;
1718 ap->device[1].class = ATA_DEV_NONE;
1719 ap->flags |= ATA_FLAG_PORT_DISABLED;
1720}
1721
452503f9
AC
1722/*
1723 * This mode timing computation functionality is ported over from
1724 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1725 */
1726/*
1727 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
1728 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
1729 * for PIO 5, which is a nonstandard extension and UDMA6, which
1730 * is currently supported only by Maxtor drives.
1731 */
1732
1733static const struct ata_timing ata_timing[] = {
1734
1735 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1736 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1737 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1738 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1739
1740 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1741 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1742 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1743
1744/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
1745
1746 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1747 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1748 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
1749
1750 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
1751 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
1752 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
1753
1754/* { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, */
1755 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
1756 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
1757
1758 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
1759 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
1760 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
1761
1762/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
1763
1764 { 0xFF }
1765};
1766
1767#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
1768#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
1769
1770static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
1771{
1772 q->setup = EZ(t->setup * 1000, T);
1773 q->act8b = EZ(t->act8b * 1000, T);
1774 q->rec8b = EZ(t->rec8b * 1000, T);
1775 q->cyc8b = EZ(t->cyc8b * 1000, T);
1776 q->active = EZ(t->active * 1000, T);
1777 q->recover = EZ(t->recover * 1000, T);
1778 q->cycle = EZ(t->cycle * 1000, T);
1779 q->udma = EZ(t->udma * 1000, UT);
1780}
1781
1782void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
1783 struct ata_timing *m, unsigned int what)
1784{
1785 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
1786 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
1787 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
1788 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
1789 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
1790 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
1791 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
1792 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
1793}
1794
1795static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
1796{
1797 const struct ata_timing *t;
1798
1799 for (t = ata_timing; t->mode != speed; t++)
91190758 1800 if (t->mode == 0xFF)
452503f9
AC
1801 return NULL;
1802 return t;
1803}
1804
1805int ata_timing_compute(struct ata_device *adev, unsigned short speed,
1806 struct ata_timing *t, int T, int UT)
1807{
1808 const struct ata_timing *s;
1809 struct ata_timing p;
1810
1811 /*
1812 * Find the mode.
75b1f2f8 1813 */
452503f9
AC
1814
1815 if (!(s = ata_timing_find_mode(speed)))
1816 return -EINVAL;
1817
75b1f2f8
AL
1818 memcpy(t, s, sizeof(*s));
1819
452503f9
AC
1820 /*
1821 * If the drive is an EIDE drive, it can tell us it needs extended
1822 * PIO/MW_DMA cycle timing.
1823 */
1824
1825 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
1826 memset(&p, 0, sizeof(p));
1827 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
1828 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
1829 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
1830 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
1831 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
1832 }
1833 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
1834 }
1835
1836 /*
1837 * Convert the timing to bus clock counts.
1838 */
1839
75b1f2f8 1840 ata_timing_quantize(t, t, T, UT);
452503f9
AC
1841
1842 /*
c893a3ae
RD
1843 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
1844 * S.M.A.R.T * and some other commands. We have to ensure that the
1845 * DMA cycle timing is slower/equal than the fastest PIO timing.
452503f9
AC
1846 */
1847
1848 if (speed > XFER_PIO_4) {
1849 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
1850 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
1851 }
1852
1853 /*
c893a3ae 1854 * Lengthen active & recovery time so that cycle time is correct.
452503f9
AC
1855 */
1856
1857 if (t->act8b + t->rec8b < t->cyc8b) {
1858 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
1859 t->rec8b = t->cyc8b - t->act8b;
1860 }
1861
1862 if (t->active + t->recover < t->cycle) {
1863 t->active += (t->cycle - (t->active + t->recover)) / 2;
1864 t->recover = t->cycle - t->active;
1865 }
1866
1867 return 0;
1868}
1869
057ace5e 1870static const struct {
1da177e4
LT
1871 unsigned int shift;
1872 u8 base;
1873} xfer_mode_classes[] = {
1874 { ATA_SHIFT_UDMA, XFER_UDMA_0 },
1875 { ATA_SHIFT_MWDMA, XFER_MW_DMA_0 },
1876 { ATA_SHIFT_PIO, XFER_PIO_0 },
1877};
1878
858119e1 1879static u8 base_from_shift(unsigned int shift)
1da177e4
LT
1880{
1881 int i;
1882
1883 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++)
1884 if (xfer_mode_classes[i].shift == shift)
1885 return xfer_mode_classes[i].base;
1886
1887 return 0xff;
1888}
1889
1890static void ata_dev_set_mode(struct ata_port *ap, struct ata_device *dev)
1891{
1892 int ofs, idx;
1893 u8 base;
1894
1895 if (!ata_dev_present(dev) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1896 return;
1897
1898 if (dev->xfer_shift == ATA_SHIFT_PIO)
1899 dev->flags |= ATA_DFLAG_PIO;
1900
1901 ata_dev_set_xfermode(ap, dev);
1902
1903 base = base_from_shift(dev->xfer_shift);
1904 ofs = dev->xfer_mode - base;
1905 idx = ofs + dev->xfer_shift;
1906 WARN_ON(idx >= ARRAY_SIZE(xfer_mode_str));
1907
1908 DPRINTK("idx=%d xfer_shift=%u, xfer_mode=0x%x, base=0x%x, offset=%d\n",
1909 idx, dev->xfer_shift, (int)dev->xfer_mode, (int)base, ofs);
1910
1911 printk(KERN_INFO "ata%u: dev %u configured for %s\n",
1912 ap->id, dev->devno, xfer_mode_str[idx]);
1913}
1914
1915static int ata_host_set_pio(struct ata_port *ap)
1916{
1917 unsigned int mask;
1918 int x, i;
1919 u8 base, xfer_mode;
1920
1921 mask = ata_get_mode_mask(ap, ATA_SHIFT_PIO);
1922 x = fgb(mask);
1923 if (x < 0) {
1924 printk(KERN_WARNING "ata%u: no PIO support\n", ap->id);
1925 return -1;
1926 }
1927
1928 base = base_from_shift(ATA_SHIFT_PIO);
1929 xfer_mode = base + x;
1930
1931 DPRINTK("base 0x%x xfer_mode 0x%x mask 0x%x x %d\n",
1932 (int)base, (int)xfer_mode, mask, x);
1933
1934 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1935 struct ata_device *dev = &ap->device[i];
1936 if (ata_dev_present(dev)) {
1937 dev->pio_mode = xfer_mode;
1938 dev->xfer_mode = xfer_mode;
1939 dev->xfer_shift = ATA_SHIFT_PIO;
1940 if (ap->ops->set_piomode)
1941 ap->ops->set_piomode(ap, dev);
1942 }
1943 }
1944
1945 return 0;
1946}
1947
1948static void ata_host_set_dma(struct ata_port *ap, u8 xfer_mode,
1949 unsigned int xfer_shift)
1950{
1951 int i;
1952
1953 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1954 struct ata_device *dev = &ap->device[i];
1955 if (ata_dev_present(dev)) {
1956 dev->dma_mode = xfer_mode;
1957 dev->xfer_mode = xfer_mode;
1958 dev->xfer_shift = xfer_shift;
1959 if (ap->ops->set_dmamode)
1960 ap->ops->set_dmamode(ap, dev);
1961 }
1962 }
1963}
1964
1965/**
1966 * ata_set_mode - Program timings and issue SET FEATURES - XFER
1967 * @ap: port on which timings will be programmed
1968 *
780a87f7
JG
1969 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.).
1970 *
1da177e4 1971 * LOCKING:
0cba632b 1972 * PCI/etc. bus probe sem.
1da177e4
LT
1973 */
1974static void ata_set_mode(struct ata_port *ap)
1975{
8cbd6df1 1976 unsigned int xfer_shift;
1da177e4
LT
1977 u8 xfer_mode;
1978 int rc;
1979
1980 /* step 1: always set host PIO timings */
1981 rc = ata_host_set_pio(ap);
1982 if (rc)
1983 goto err_out;
1984
1985 /* step 2: choose the best data xfer mode */
1986 xfer_mode = xfer_shift = 0;
1987 rc = ata_choose_xfer_mode(ap, &xfer_mode, &xfer_shift);
1988 if (rc)
1989 goto err_out;
1990
1991 /* step 3: if that xfer mode isn't PIO, set host DMA timings */
1992 if (xfer_shift != ATA_SHIFT_PIO)
1993 ata_host_set_dma(ap, xfer_mode, xfer_shift);
1994
1995 /* step 4: update devices' xfer mode */
1996 ata_dev_set_mode(ap, &ap->device[0]);
1997 ata_dev_set_mode(ap, &ap->device[1]);
1998
1999 if (ap->flags & ATA_FLAG_PORT_DISABLED)
2000 return;
2001
2002 if (ap->ops->post_set_mode)
2003 ap->ops->post_set_mode(ap);
2004
1da177e4
LT
2005 return;
2006
2007err_out:
2008 ata_port_disable(ap);
2009}
2010
2011/**
2012 * ata_busy_sleep - sleep until BSY clears, or timeout
2013 * @ap: port containing status register to be polled
2014 * @tmout_pat: impatience timeout
2015 * @tmout: overall timeout
2016 *
780a87f7
JG
2017 * Sleep until ATA Status register bit BSY clears,
2018 * or a timeout occurs.
2019 *
2020 * LOCKING: None.
1da177e4
LT
2021 */
2022
6f8b9958
TH
2023unsigned int ata_busy_sleep (struct ata_port *ap,
2024 unsigned long tmout_pat, unsigned long tmout)
1da177e4
LT
2025{
2026 unsigned long timer_start, timeout;
2027 u8 status;
2028
2029 status = ata_busy_wait(ap, ATA_BUSY, 300);
2030 timer_start = jiffies;
2031 timeout = timer_start + tmout_pat;
2032 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
2033 msleep(50);
2034 status = ata_busy_wait(ap, ATA_BUSY, 3);
2035 }
2036
2037 if (status & ATA_BUSY)
2038 printk(KERN_WARNING "ata%u is slow to respond, "
2039 "please be patient\n", ap->id);
2040
2041 timeout = timer_start + tmout;
2042 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
2043 msleep(50);
2044 status = ata_chk_status(ap);
2045 }
2046
2047 if (status & ATA_BUSY) {
2048 printk(KERN_ERR "ata%u failed to respond (%lu secs)\n",
2049 ap->id, tmout / HZ);
2050 return 1;
2051 }
2052
2053 return 0;
2054}
2055
2056static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
2057{
2058 struct ata_ioports *ioaddr = &ap->ioaddr;
2059 unsigned int dev0 = devmask & (1 << 0);
2060 unsigned int dev1 = devmask & (1 << 1);
2061 unsigned long timeout;
2062
2063 /* if device 0 was found in ata_devchk, wait for its
2064 * BSY bit to clear
2065 */
2066 if (dev0)
2067 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2068
2069 /* if device 1 was found in ata_devchk, wait for
2070 * register access, then wait for BSY to clear
2071 */
2072 timeout = jiffies + ATA_TMOUT_BOOT;
2073 while (dev1) {
2074 u8 nsect, lbal;
2075
2076 ap->ops->dev_select(ap, 1);
2077 if (ap->flags & ATA_FLAG_MMIO) {
2078 nsect = readb((void __iomem *) ioaddr->nsect_addr);
2079 lbal = readb((void __iomem *) ioaddr->lbal_addr);
2080 } else {
2081 nsect = inb(ioaddr->nsect_addr);
2082 lbal = inb(ioaddr->lbal_addr);
2083 }
2084 if ((nsect == 1) && (lbal == 1))
2085 break;
2086 if (time_after(jiffies, timeout)) {
2087 dev1 = 0;
2088 break;
2089 }
2090 msleep(50); /* give drive a breather */
2091 }
2092 if (dev1)
2093 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2094
2095 /* is all this really necessary? */
2096 ap->ops->dev_select(ap, 0);
2097 if (dev1)
2098 ap->ops->dev_select(ap, 1);
2099 if (dev0)
2100 ap->ops->dev_select(ap, 0);
2101}
2102
2103/**
0cba632b
JG
2104 * ata_bus_edd - Issue EXECUTE DEVICE DIAGNOSTIC command.
2105 * @ap: Port to reset and probe
2106 *
2107 * Use the EXECUTE DEVICE DIAGNOSTIC command to reset and
2108 * probe the bus. Not often used these days.
1da177e4
LT
2109 *
2110 * LOCKING:
0cba632b 2111 * PCI/etc. bus probe sem.
e5338254 2112 * Obtains host_set lock.
1da177e4
LT
2113 *
2114 */
2115
2116static unsigned int ata_bus_edd(struct ata_port *ap)
2117{
2118 struct ata_taskfile tf;
e5338254 2119 unsigned long flags;
1da177e4
LT
2120
2121 /* set up execute-device-diag (bus reset) taskfile */
2122 /* also, take interrupts to a known state (disabled) */
2123 DPRINTK("execute-device-diag\n");
2124 ata_tf_init(ap, &tf, 0);
2125 tf.ctl |= ATA_NIEN;
2126 tf.command = ATA_CMD_EDD;
2127 tf.protocol = ATA_PROT_NODATA;
2128
2129 /* do bus reset */
e5338254 2130 spin_lock_irqsave(&ap->host_set->lock, flags);
1da177e4 2131 ata_tf_to_host(ap, &tf);
e5338254 2132 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1da177e4
LT
2133
2134 /* spec says at least 2ms. but who knows with those
2135 * crazy ATAPI devices...
2136 */
2137 msleep(150);
2138
2139 return ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2140}
2141
2142static unsigned int ata_bus_softreset(struct ata_port *ap,
2143 unsigned int devmask)
2144{
2145 struct ata_ioports *ioaddr = &ap->ioaddr;
2146
2147 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
2148
2149 /* software reset. causes dev0 to be selected */
2150 if (ap->flags & ATA_FLAG_MMIO) {
2151 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2152 udelay(20); /* FIXME: flush */
2153 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
2154 udelay(20); /* FIXME: flush */
2155 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2156 } else {
2157 outb(ap->ctl, ioaddr->ctl_addr);
2158 udelay(10);
2159 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2160 udelay(10);
2161 outb(ap->ctl, ioaddr->ctl_addr);
2162 }
2163
2164 /* spec mandates ">= 2ms" before checking status.
2165 * We wait 150ms, because that was the magic delay used for
2166 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
2167 * between when the ATA command register is written, and then
2168 * status is checked. Because waiting for "a while" before
2169 * checking status is fine, post SRST, we perform this magic
2170 * delay here as well.
2171 */
2172 msleep(150);
2173
2174 ata_bus_post_reset(ap, devmask);
2175
2176 return 0;
2177}
2178
2179/**
2180 * ata_bus_reset - reset host port and associated ATA channel
2181 * @ap: port to reset
2182 *
2183 * This is typically the first time we actually start issuing
2184 * commands to the ATA channel. We wait for BSY to clear, then
2185 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2186 * result. Determine what devices, if any, are on the channel
2187 * by looking at the device 0/1 error register. Look at the signature
2188 * stored in each device's taskfile registers, to determine if
2189 * the device is ATA or ATAPI.
2190 *
2191 * LOCKING:
0cba632b
JG
2192 * PCI/etc. bus probe sem.
2193 * Obtains host_set lock.
1da177e4
LT
2194 *
2195 * SIDE EFFECTS:
2196 * Sets ATA_FLAG_PORT_DISABLED if bus reset fails.
2197 */
2198
2199void ata_bus_reset(struct ata_port *ap)
2200{
2201 struct ata_ioports *ioaddr = &ap->ioaddr;
2202 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2203 u8 err;
2204 unsigned int dev0, dev1 = 0, rc = 0, devmask = 0;
2205
2206 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
2207
2208 /* determine if device 0/1 are present */
2209 if (ap->flags & ATA_FLAG_SATA_RESET)
2210 dev0 = 1;
2211 else {
2212 dev0 = ata_devchk(ap, 0);
2213 if (slave_possible)
2214 dev1 = ata_devchk(ap, 1);
2215 }
2216
2217 if (dev0)
2218 devmask |= (1 << 0);
2219 if (dev1)
2220 devmask |= (1 << 1);
2221
2222 /* select device 0 again */
2223 ap->ops->dev_select(ap, 0);
2224
2225 /* issue bus reset */
2226 if (ap->flags & ATA_FLAG_SRST)
2227 rc = ata_bus_softreset(ap, devmask);
2228 else if ((ap->flags & ATA_FLAG_SATA_RESET) == 0) {
2229 /* set up device control */
2230 if (ap->flags & ATA_FLAG_MMIO)
2231 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2232 else
2233 outb(ap->ctl, ioaddr->ctl_addr);
2234 rc = ata_bus_edd(ap);
2235 }
2236
2237 if (rc)
2238 goto err_out;
2239
2240 /*
2241 * determine by signature whether we have ATA or ATAPI devices
2242 */
b4dc7623 2243 ap->device[0].class = ata_dev_try_classify(ap, 0, &err);
1da177e4 2244 if ((slave_possible) && (err != 0x81))
b4dc7623 2245 ap->device[1].class = ata_dev_try_classify(ap, 1, &err);
1da177e4
LT
2246
2247 /* re-enable interrupts */
2248 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2249 ata_irq_on(ap);
2250
2251 /* is double-select really necessary? */
2252 if (ap->device[1].class != ATA_DEV_NONE)
2253 ap->ops->dev_select(ap, 1);
2254 if (ap->device[0].class != ATA_DEV_NONE)
2255 ap->ops->dev_select(ap, 0);
2256
2257 /* if no devices were detected, disable this port */
2258 if ((ap->device[0].class == ATA_DEV_NONE) &&
2259 (ap->device[1].class == ATA_DEV_NONE))
2260 goto err_out;
2261
2262 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2263 /* set up device control for ATA_FLAG_SATA_RESET */
2264 if (ap->flags & ATA_FLAG_MMIO)
2265 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2266 else
2267 outb(ap->ctl, ioaddr->ctl_addr);
2268 }
2269
2270 DPRINTK("EXIT\n");
2271 return;
2272
2273err_out:
2274 printk(KERN_ERR "ata%u: disabling port\n", ap->id);
2275 ap->ops->port_disable(ap);
2276
2277 DPRINTK("EXIT\n");
2278}
2279
7a7921e8
TH
2280static int sata_phy_resume(struct ata_port *ap)
2281{
2282 unsigned long timeout = jiffies + (HZ * 5);
2283 u32 sstatus;
2284
2285 scr_write_flush(ap, SCR_CONTROL, 0x300);
2286
2287 /* Wait for phy to become ready, if necessary. */
2288 do {
2289 msleep(200);
2290 sstatus = scr_read(ap, SCR_STATUS);
2291 if ((sstatus & 0xf) != 1)
2292 return 0;
2293 } while (time_before(jiffies, timeout));
2294
2295 return -1;
2296}
2297
c2bd5804
TH
2298/**
2299 * ata_std_softreset - reset host port via ATA SRST
2300 * @ap: port to reset
2301 * @verbose: fail verbosely
2302 * @classes: resulting classes of attached devices
2303 *
2304 * Reset host port using ATA SRST. This function is to be used
2305 * as standard callback for ata_drive_*_reset() functions.
2306 *
2307 * LOCKING:
2308 * Kernel thread context (may sleep)
2309 *
2310 * RETURNS:
2311 * 0 on success, -errno otherwise.
2312 */
2313int ata_std_softreset(struct ata_port *ap, int verbose, unsigned int *classes)
2314{
2315 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2316 unsigned int devmask = 0, err_mask;
2317 u8 err;
2318
2319 DPRINTK("ENTER\n");
2320
2321 /* determine if device 0/1 are present */
2322 if (ata_devchk(ap, 0))
2323 devmask |= (1 << 0);
2324 if (slave_possible && ata_devchk(ap, 1))
2325 devmask |= (1 << 1);
2326
2327 /* devchk reports device presence without actual device on
2328 * most SATA controllers. Check SStatus and turn devmask off
2329 * if link is offline. Note that we should continue resetting
2330 * even when it seems like there's no device.
2331 */
2332 if (ap->ops->scr_read && !sata_dev_present(ap))
2333 devmask = 0;
2334
2335 /* select device 0 again */
2336 ap->ops->dev_select(ap, 0);
2337
2338 /* issue bus reset */
2339 DPRINTK("about to softreset, devmask=%x\n", devmask);
2340 err_mask = ata_bus_softreset(ap, devmask);
2341 if (err_mask) {
2342 if (verbose)
2343 printk(KERN_ERR "ata%u: SRST failed (err_mask=0x%x)\n",
2344 ap->id, err_mask);
2345 else
2346 DPRINTK("EXIT, softreset failed (err_mask=0x%x)\n",
2347 err_mask);
2348 return -EIO;
2349 }
2350
2351 /* determine by signature whether we have ATA or ATAPI devices */
2352 classes[0] = ata_dev_try_classify(ap, 0, &err);
2353 if (slave_possible && err != 0x81)
2354 classes[1] = ata_dev_try_classify(ap, 1, &err);
2355
2356 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2357 return 0;
2358}
2359
2360/**
2361 * sata_std_hardreset - reset host port via SATA phy reset
2362 * @ap: port to reset
2363 * @verbose: fail verbosely
2364 * @class: resulting class of attached device
2365 *
2366 * SATA phy-reset host port using DET bits of SControl register.
2367 * This function is to be used as standard callback for
2368 * ata_drive_*_reset().
2369 *
2370 * LOCKING:
2371 * Kernel thread context (may sleep)
2372 *
2373 * RETURNS:
2374 * 0 on success, -errno otherwise.
2375 */
2376int sata_std_hardreset(struct ata_port *ap, int verbose, unsigned int *class)
2377{
7a7921e8 2378 u32 serror;
c2bd5804
TH
2379
2380 DPRINTK("ENTER\n");
2381
2382 /* Issue phy wake/reset */
2383 scr_write_flush(ap, SCR_CONTROL, 0x301);
2384
2385 /*
2386 * Couldn't find anything in SATA I/II specs, but AHCI-1.1
2387 * 10.4.2 says at least 1 ms.
2388 */
2389 msleep(1);
2390
7a7921e8
TH
2391 /* Bring phy back */
2392 sata_phy_resume(ap);
c2bd5804
TH
2393
2394 /* Clear SError */
2395 serror = scr_read(ap, SCR_ERROR);
2396 scr_write(ap, SCR_ERROR, serror);
2397
2398 /* TODO: phy layer with polling, timeouts, etc. */
2399 if (!sata_dev_present(ap)) {
2400 *class = ATA_DEV_NONE;
2401 DPRINTK("EXIT, link offline\n");
2402 return 0;
2403 }
2404
2405 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
2406 if (verbose)
2407 printk(KERN_ERR "ata%u: COMRESET failed "
2408 "(device not ready)\n", ap->id);
2409 else
2410 DPRINTK("EXIT, device not ready\n");
2411 return -EIO;
2412 }
2413
2414 *class = ata_dev_try_classify(ap, 0, NULL);
2415
2416 DPRINTK("EXIT, class=%u\n", *class);
2417 return 0;
2418}
2419
2420/**
2421 * ata_std_postreset - standard postreset callback
2422 * @ap: the target ata_port
2423 * @classes: classes of attached devices
2424 *
2425 * This function is invoked after a successful reset. Note that
2426 * the device might have been reset more than once using
2427 * different reset methods before postreset is invoked.
2428 * postreset is also reponsible for setting cable type.
2429 *
2430 * This function is to be used as standard callback for
2431 * ata_drive_*_reset().
2432 *
2433 * LOCKING:
2434 * Kernel thread context (may sleep)
2435 */
2436void ata_std_postreset(struct ata_port *ap, unsigned int *classes)
2437{
2438 DPRINTK("ENTER\n");
2439
2440 /* set cable type */
2441 if (ap->cbl == ATA_CBL_NONE && ap->flags & ATA_FLAG_SATA)
2442 ap->cbl = ATA_CBL_SATA;
2443
2444 /* print link status */
2445 if (ap->cbl == ATA_CBL_SATA)
2446 sata_print_link_status(ap);
2447
2448 /* bail out if no device is present */
2449 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2450 DPRINTK("EXIT, no device\n");
2451 return;
2452 }
2453
2454 /* is double-select really necessary? */
2455 if (classes[0] != ATA_DEV_NONE)
2456 ap->ops->dev_select(ap, 1);
2457 if (classes[1] != ATA_DEV_NONE)
2458 ap->ops->dev_select(ap, 0);
2459
2460 /* re-enable interrupts & set up device control */
2461 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2462 ata_irq_on(ap);
2463
2464 DPRINTK("EXIT\n");
2465}
2466
2467/**
2468 * ata_std_probe_reset - standard probe reset method
2469 * @ap: prot to perform probe-reset
2470 * @classes: resulting classes of attached devices
2471 *
2472 * The stock off-the-shelf ->probe_reset method.
2473 *
2474 * LOCKING:
2475 * Kernel thread context (may sleep)
2476 *
2477 * RETURNS:
2478 * 0 on success, -errno otherwise.
2479 */
2480int ata_std_probe_reset(struct ata_port *ap, unsigned int *classes)
2481{
2482 ata_reset_fn_t hardreset;
2483
2484 hardreset = NULL;
b911fc3a 2485 if (ap->flags & ATA_FLAG_SATA && ap->ops->scr_read)
c2bd5804
TH
2486 hardreset = sata_std_hardreset;
2487
7944ea95
TH
2488 return ata_drive_probe_reset(ap, NULL,
2489 ata_std_softreset, hardreset,
c2bd5804
TH
2490 ata_std_postreset, classes);
2491}
2492
a62c0fc5
TH
2493static int do_probe_reset(struct ata_port *ap, ata_reset_fn_t reset,
2494 ata_postreset_fn_t postreset,
2495 unsigned int *classes)
2496{
2497 int i, rc;
2498
2499 for (i = 0; i < ATA_MAX_DEVICES; i++)
2500 classes[i] = ATA_DEV_UNKNOWN;
2501
2502 rc = reset(ap, 0, classes);
2503 if (rc)
2504 return rc;
2505
2506 /* If any class isn't ATA_DEV_UNKNOWN, consider classification
2507 * is complete and convert all ATA_DEV_UNKNOWN to
2508 * ATA_DEV_NONE.
2509 */
2510 for (i = 0; i < ATA_MAX_DEVICES; i++)
2511 if (classes[i] != ATA_DEV_UNKNOWN)
2512 break;
2513
2514 if (i < ATA_MAX_DEVICES)
2515 for (i = 0; i < ATA_MAX_DEVICES; i++)
2516 if (classes[i] == ATA_DEV_UNKNOWN)
2517 classes[i] = ATA_DEV_NONE;
2518
2519 if (postreset)
2520 postreset(ap, classes);
2521
2522 return classes[0] != ATA_DEV_UNKNOWN ? 0 : -ENODEV;
2523}
2524
2525/**
2526 * ata_drive_probe_reset - Perform probe reset with given methods
2527 * @ap: port to reset
7944ea95 2528 * @probeinit: probeinit method (can be NULL)
a62c0fc5
TH
2529 * @softreset: softreset method (can be NULL)
2530 * @hardreset: hardreset method (can be NULL)
2531 * @postreset: postreset method (can be NULL)
2532 * @classes: resulting classes of attached devices
2533 *
2534 * Reset the specified port and classify attached devices using
2535 * given methods. This function prefers softreset but tries all
2536 * possible reset sequences to reset and classify devices. This
2537 * function is intended to be used for constructing ->probe_reset
2538 * callback by low level drivers.
2539 *
2540 * Reset methods should follow the following rules.
2541 *
2542 * - Return 0 on sucess, -errno on failure.
2543 * - If classification is supported, fill classes[] with
2544 * recognized class codes.
2545 * - If classification is not supported, leave classes[] alone.
2546 * - If verbose is non-zero, print error message on failure;
2547 * otherwise, shut up.
2548 *
2549 * LOCKING:
2550 * Kernel thread context (may sleep)
2551 *
2552 * RETURNS:
2553 * 0 on success, -EINVAL if no reset method is avaliable, -ENODEV
2554 * if classification fails, and any error code from reset
2555 * methods.
2556 */
7944ea95 2557int ata_drive_probe_reset(struct ata_port *ap, ata_probeinit_fn_t probeinit,
a62c0fc5
TH
2558 ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
2559 ata_postreset_fn_t postreset, unsigned int *classes)
2560{
2561 int rc = -EINVAL;
2562
7944ea95
TH
2563 if (probeinit)
2564 probeinit(ap);
2565
a62c0fc5
TH
2566 if (softreset) {
2567 rc = do_probe_reset(ap, softreset, postreset, classes);
2568 if (rc == 0)
2569 return 0;
2570 }
2571
2572 if (!hardreset)
2573 return rc;
2574
2575 rc = do_probe_reset(ap, hardreset, postreset, classes);
2576 if (rc == 0 || rc != -ENODEV)
2577 return rc;
2578
2579 if (softreset)
2580 rc = do_probe_reset(ap, softreset, postreset, classes);
2581
2582 return rc;
2583}
2584
057ace5e
JG
2585static void ata_pr_blacklisted(const struct ata_port *ap,
2586 const struct ata_device *dev)
1da177e4
LT
2587{
2588 printk(KERN_WARNING "ata%u: dev %u is on DMA blacklist, disabling DMA\n",
2589 ap->id, dev->devno);
2590}
2591
98ac62de 2592static const char * const ata_dma_blacklist [] = {
1da177e4
LT
2593 "WDC AC11000H",
2594 "WDC AC22100H",
2595 "WDC AC32500H",
2596 "WDC AC33100H",
2597 "WDC AC31600H",
2598 "WDC AC32100H",
2599 "WDC AC23200L",
2600 "Compaq CRD-8241B",
2601 "CRD-8400B",
2602 "CRD-8480B",
2603 "CRD-8482B",
2604 "CRD-84",
2605 "SanDisk SDP3B",
2606 "SanDisk SDP3B-64",
2607 "SANYO CD-ROM CRD",
2608 "HITACHI CDR-8",
2609 "HITACHI CDR-8335",
2610 "HITACHI CDR-8435",
2611 "Toshiba CD-ROM XM-6202B",
e922256a 2612 "TOSHIBA CD-ROM XM-1702BC",
1da177e4
LT
2613 "CD-532E-A",
2614 "E-IDE CD-ROM CR-840",
2615 "CD-ROM Drive/F5A",
2616 "WPI CDD-820",
2617 "SAMSUNG CD-ROM SC-148C",
2618 "SAMSUNG CD-ROM SC",
2619 "SanDisk SDP3B-64",
1da177e4
LT
2620 "ATAPI CD-ROM DRIVE 40X MAXIMUM",
2621 "_NEC DV5800A",
2622};
2623
057ace5e 2624static int ata_dma_blacklisted(const struct ata_device *dev)
1da177e4
LT
2625{
2626 unsigned char model_num[40];
2627 char *s;
2628 unsigned int len;
2629 int i;
2630
2631 ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
2632 sizeof(model_num));
2633 s = &model_num[0];
2634 len = strnlen(s, sizeof(model_num));
2635
2636 /* ATAPI specifies that empty space is blank-filled; remove blanks */
2637 while ((len > 0) && (s[len - 1] == ' ')) {
2638 len--;
2639 s[len] = 0;
2640 }
2641
2642 for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i++)
2643 if (!strncmp(ata_dma_blacklist[i], s, len))
2644 return 1;
2645
2646 return 0;
2647}
2648
057ace5e 2649static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift)
1da177e4 2650{
057ace5e 2651 const struct ata_device *master, *slave;
1da177e4
LT
2652 unsigned int mask;
2653
2654 master = &ap->device[0];
2655 slave = &ap->device[1];
2656
2657 assert (ata_dev_present(master) || ata_dev_present(slave));
2658
2659 if (shift == ATA_SHIFT_UDMA) {
2660 mask = ap->udma_mask;
2661 if (ata_dev_present(master)) {
2662 mask &= (master->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2663 if (ata_dma_blacklisted(master)) {
1da177e4
LT
2664 mask = 0;
2665 ata_pr_blacklisted(ap, master);
2666 }
2667 }
2668 if (ata_dev_present(slave)) {
2669 mask &= (slave->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2670 if (ata_dma_blacklisted(slave)) {
1da177e4
LT
2671 mask = 0;
2672 ata_pr_blacklisted(ap, slave);
2673 }
2674 }
2675 }
2676 else if (shift == ATA_SHIFT_MWDMA) {
2677 mask = ap->mwdma_mask;
2678 if (ata_dev_present(master)) {
2679 mask &= (master->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2680 if (ata_dma_blacklisted(master)) {
1da177e4
LT
2681 mask = 0;
2682 ata_pr_blacklisted(ap, master);
2683 }
2684 }
2685 if (ata_dev_present(slave)) {
2686 mask &= (slave->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2687 if (ata_dma_blacklisted(slave)) {
1da177e4
LT
2688 mask = 0;
2689 ata_pr_blacklisted(ap, slave);
2690 }
2691 }
2692 }
2693 else if (shift == ATA_SHIFT_PIO) {
2694 mask = ap->pio_mask;
2695 if (ata_dev_present(master)) {
2696 /* spec doesn't return explicit support for
2697 * PIO0-2, so we fake it
2698 */
2699 u16 tmp_mode = master->id[ATA_ID_PIO_MODES] & 0x03;
2700 tmp_mode <<= 3;
2701 tmp_mode |= 0x7;
2702 mask &= tmp_mode;
2703 }
2704 if (ata_dev_present(slave)) {
2705 /* spec doesn't return explicit support for
2706 * PIO0-2, so we fake it
2707 */
2708 u16 tmp_mode = slave->id[ATA_ID_PIO_MODES] & 0x03;
2709 tmp_mode <<= 3;
2710 tmp_mode |= 0x7;
2711 mask &= tmp_mode;
2712 }
2713 }
2714 else {
2715 mask = 0xffffffff; /* shut up compiler warning */
2716 BUG();
2717 }
2718
2719 return mask;
2720}
2721
2722/* find greatest bit */
2723static int fgb(u32 bitmap)
2724{
2725 unsigned int i;
2726 int x = -1;
2727
2728 for (i = 0; i < 32; i++)
2729 if (bitmap & (1 << i))
2730 x = i;
2731
2732 return x;
2733}
2734
2735/**
2736 * ata_choose_xfer_mode - attempt to find best transfer mode
2737 * @ap: Port for which an xfer mode will be selected
2738 * @xfer_mode_out: (output) SET FEATURES - XFER MODE code
2739 * @xfer_shift_out: (output) bit shift that selects this mode
2740 *
0cba632b
JG
2741 * Based on host and device capabilities, determine the
2742 * maximum transfer mode that is amenable to all.
2743 *
1da177e4 2744 * LOCKING:
0cba632b 2745 * PCI/etc. bus probe sem.
1da177e4
LT
2746 *
2747 * RETURNS:
2748 * Zero on success, negative on error.
2749 */
2750
057ace5e 2751static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT
2752 u8 *xfer_mode_out,
2753 unsigned int *xfer_shift_out)
2754{
2755 unsigned int mask, shift;
2756 int x, i;
2757
2758 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++) {
2759 shift = xfer_mode_classes[i].shift;
2760 mask = ata_get_mode_mask(ap, shift);
2761
2762 x = fgb(mask);
2763 if (x >= 0) {
2764 *xfer_mode_out = xfer_mode_classes[i].base + x;
2765 *xfer_shift_out = shift;
2766 return 0;
2767 }
2768 }
2769
2770 return -1;
2771}
2772
2773/**
2774 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
2775 * @ap: Port associated with device @dev
2776 * @dev: Device to which command will be sent
2777 *
780a87f7
JG
2778 * Issue SET FEATURES - XFER MODE command to device @dev
2779 * on port @ap.
2780 *
1da177e4 2781 * LOCKING:
0cba632b 2782 * PCI/etc. bus probe sem.
1da177e4
LT
2783 */
2784
2785static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev)
2786{
a0123703 2787 struct ata_taskfile tf;
1da177e4
LT
2788
2789 /* set up set-features taskfile */
2790 DPRINTK("set features - xfer mode\n");
2791
a0123703
TH
2792 ata_tf_init(ap, &tf, dev->devno);
2793 tf.command = ATA_CMD_SET_FEATURES;
2794 tf.feature = SETFEATURES_XFER;
2795 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2796 tf.protocol = ATA_PROT_NODATA;
2797 tf.nsect = dev->xfer_mode;
1da177e4 2798
a0123703
TH
2799 if (ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0)) {
2800 printk(KERN_ERR "ata%u: failed to set xfermode, disabled\n",
2801 ap->id);
1da177e4 2802 ata_port_disable(ap);
a0123703 2803 }
1da177e4
LT
2804
2805 DPRINTK("EXIT\n");
2806}
2807
59a10b17
AL
2808/**
2809 * ata_dev_reread_id - Reread the device identify device info
2810 * @ap: port where the device is
2811 * @dev: device to reread the identify device info
2812 *
2813 * LOCKING:
2814 */
2815
2816static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev)
2817{
a0123703 2818 struct ata_taskfile tf;
59a10b17 2819
a0123703 2820 ata_tf_init(ap, &tf, dev->devno);
59a10b17
AL
2821
2822 if (dev->class == ATA_DEV_ATA) {
a0123703 2823 tf.command = ATA_CMD_ID_ATA;
59a10b17
AL
2824 DPRINTK("do ATA identify\n");
2825 } else {
a0123703 2826 tf.command = ATA_CMD_ID_ATAPI;
59a10b17
AL
2827 DPRINTK("do ATAPI identify\n");
2828 }
2829
a0123703
TH
2830 tf.flags |= ATA_TFLAG_DEVICE;
2831 tf.protocol = ATA_PROT_PIO;
59a10b17 2832
a0123703
TH
2833 if (ata_exec_internal(ap, dev, &tf, DMA_FROM_DEVICE,
2834 dev->id, sizeof(dev->id)))
59a10b17
AL
2835 goto err_out;
2836
59a10b17
AL
2837 swap_buf_le16(dev->id, ATA_ID_WORDS);
2838
2839 ata_dump_id(dev);
2840
2841 DPRINTK("EXIT\n");
2842
2843 return;
2844err_out:
a0123703 2845 printk(KERN_ERR "ata%u: failed to reread ID, disabled\n", ap->id);
59a10b17
AL
2846 ata_port_disable(ap);
2847}
2848
8bf62ece
AL
2849/**
2850 * ata_dev_init_params - Issue INIT DEV PARAMS command
2851 * @ap: Port associated with device @dev
2852 * @dev: Device to which command will be sent
2853 *
2854 * LOCKING:
2855 */
2856
2857static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev)
2858{
a0123703 2859 struct ata_taskfile tf;
8bf62ece
AL
2860 u16 sectors = dev->id[6];
2861 u16 heads = dev->id[3];
2862
2863 /* Number of sectors per track 1-255. Number of heads 1-16 */
2864 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
2865 return;
2866
2867 /* set up init dev params taskfile */
2868 DPRINTK("init dev params \n");
2869
a0123703
TH
2870 ata_tf_init(ap, &tf, dev->devno);
2871 tf.command = ATA_CMD_INIT_DEV_PARAMS;
2872 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2873 tf.protocol = ATA_PROT_NODATA;
2874 tf.nsect = sectors;
2875 tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
8bf62ece 2876
a0123703
TH
2877 if (ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0)) {
2878 printk(KERN_ERR "ata%u: failed to init parameters, disabled\n",
2879 ap->id);
8bf62ece 2880 ata_port_disable(ap);
a0123703 2881 }
8bf62ece
AL
2882
2883 DPRINTK("EXIT\n");
2884}
2885
1da177e4 2886/**
0cba632b
JG
2887 * ata_sg_clean - Unmap DMA memory associated with command
2888 * @qc: Command containing DMA memory to be released
2889 *
2890 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT
2891 *
2892 * LOCKING:
0cba632b 2893 * spin_lock_irqsave(host_set lock)
1da177e4
LT
2894 */
2895
2896static void ata_sg_clean(struct ata_queued_cmd *qc)
2897{
2898 struct ata_port *ap = qc->ap;
cedc9a47 2899 struct scatterlist *sg = qc->__sg;
1da177e4 2900 int dir = qc->dma_dir;
cedc9a47 2901 void *pad_buf = NULL;
1da177e4
LT
2902
2903 assert(qc->flags & ATA_QCFLAG_DMAMAP);
2904 assert(sg != NULL);
2905
2906 if (qc->flags & ATA_QCFLAG_SINGLE)
2907 assert(qc->n_elem == 1);
2908
2c13b7ce 2909 VPRINTK("unmapping %u sg elements\n", qc->n_elem);
1da177e4 2910
cedc9a47
JG
2911 /* if we padded the buffer out to 32-bit bound, and data
2912 * xfer direction is from-device, we must copy from the
2913 * pad buffer back into the supplied buffer
2914 */
2915 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
2916 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2917
2918 if (qc->flags & ATA_QCFLAG_SG) {
e1410f2d
JG
2919 if (qc->n_elem)
2920 dma_unmap_sg(ap->host_set->dev, sg, qc->n_elem, dir);
cedc9a47
JG
2921 /* restore last sg */
2922 sg[qc->orig_n_elem - 1].length += qc->pad_len;
2923 if (pad_buf) {
2924 struct scatterlist *psg = &qc->pad_sgent;
2925 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2926 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
dfa15988 2927 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG
2928 }
2929 } else {
e1410f2d
JG
2930 if (sg_dma_len(&sg[0]) > 0)
2931 dma_unmap_single(ap->host_set->dev,
2932 sg_dma_address(&sg[0]), sg_dma_len(&sg[0]),
2933 dir);
cedc9a47
JG
2934 /* restore sg */
2935 sg->length += qc->pad_len;
2936 if (pad_buf)
2937 memcpy(qc->buf_virt + sg->length - qc->pad_len,
2938 pad_buf, qc->pad_len);
2939 }
1da177e4
LT
2940
2941 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 2942 qc->__sg = NULL;
1da177e4
LT
2943}
2944
2945/**
2946 * ata_fill_sg - Fill PCI IDE PRD table
2947 * @qc: Metadata associated with taskfile to be transferred
2948 *
780a87f7
JG
2949 * Fill PCI IDE PRD (scatter-gather) table with segments
2950 * associated with the current disk command.
2951 *
1da177e4 2952 * LOCKING:
780a87f7 2953 * spin_lock_irqsave(host_set lock)
1da177e4
LT
2954 *
2955 */
2956static void ata_fill_sg(struct ata_queued_cmd *qc)
2957{
1da177e4 2958 struct ata_port *ap = qc->ap;
cedc9a47
JG
2959 struct scatterlist *sg;
2960 unsigned int idx;
1da177e4 2961
cedc9a47 2962 assert(qc->__sg != NULL);
1da177e4
LT
2963 assert(qc->n_elem > 0);
2964
2965 idx = 0;
cedc9a47 2966 ata_for_each_sg(sg, qc) {
1da177e4
LT
2967 u32 addr, offset;
2968 u32 sg_len, len;
2969
2970 /* determine if physical DMA addr spans 64K boundary.
2971 * Note h/w doesn't support 64-bit, so we unconditionally
2972 * truncate dma_addr_t to u32.
2973 */
2974 addr = (u32) sg_dma_address(sg);
2975 sg_len = sg_dma_len(sg);
2976
2977 while (sg_len) {
2978 offset = addr & 0xffff;
2979 len = sg_len;
2980 if ((offset + sg_len) > 0x10000)
2981 len = 0x10000 - offset;
2982
2983 ap->prd[idx].addr = cpu_to_le32(addr);
2984 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
2985 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
2986
2987 idx++;
2988 sg_len -= len;
2989 addr += len;
2990 }
2991 }
2992
2993 if (idx)
2994 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2995}
2996/**
2997 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
2998 * @qc: Metadata associated with taskfile to check
2999 *
780a87f7
JG
3000 * Allow low-level driver to filter ATA PACKET commands, returning
3001 * a status indicating whether or not it is OK to use DMA for the
3002 * supplied PACKET command.
3003 *
1da177e4 3004 * LOCKING:
0cba632b
JG
3005 * spin_lock_irqsave(host_set lock)
3006 *
1da177e4
LT
3007 * RETURNS: 0 when ATAPI DMA can be used
3008 * nonzero otherwise
3009 */
3010int ata_check_atapi_dma(struct ata_queued_cmd *qc)
3011{
3012 struct ata_port *ap = qc->ap;
3013 int rc = 0; /* Assume ATAPI DMA is OK by default */
3014
3015 if (ap->ops->check_atapi_dma)
3016 rc = ap->ops->check_atapi_dma(qc);
3017
3018 return rc;
3019}
3020/**
3021 * ata_qc_prep - Prepare taskfile for submission
3022 * @qc: Metadata associated with taskfile to be prepared
3023 *
780a87f7
JG
3024 * Prepare ATA taskfile for submission.
3025 *
1da177e4
LT
3026 * LOCKING:
3027 * spin_lock_irqsave(host_set lock)
3028 */
3029void ata_qc_prep(struct ata_queued_cmd *qc)
3030{
3031 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
3032 return;
3033
3034 ata_fill_sg(qc);
3035}
3036
0cba632b
JG
3037/**
3038 * ata_sg_init_one - Associate command with memory buffer
3039 * @qc: Command to be associated
3040 * @buf: Memory buffer
3041 * @buflen: Length of memory buffer, in bytes.
3042 *
3043 * Initialize the data-related elements of queued_cmd @qc
3044 * to point to a single memory buffer, @buf of byte length @buflen.
3045 *
3046 * LOCKING:
3047 * spin_lock_irqsave(host_set lock)
3048 */
3049
1da177e4
LT
3050void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
3051{
3052 struct scatterlist *sg;
3053
3054 qc->flags |= ATA_QCFLAG_SINGLE;
3055
3056 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 3057 qc->__sg = &qc->sgent;
1da177e4 3058 qc->n_elem = 1;
cedc9a47 3059 qc->orig_n_elem = 1;
1da177e4
LT
3060 qc->buf_virt = buf;
3061
cedc9a47 3062 sg = qc->__sg;
f0612bbc 3063 sg_init_one(sg, buf, buflen);
1da177e4
LT
3064}
3065
0cba632b
JG
3066/**
3067 * ata_sg_init - Associate command with scatter-gather table.
3068 * @qc: Command to be associated
3069 * @sg: Scatter-gather table.
3070 * @n_elem: Number of elements in s/g table.
3071 *
3072 * Initialize the data-related elements of queued_cmd @qc
3073 * to point to a scatter-gather table @sg, containing @n_elem
3074 * elements.
3075 *
3076 * LOCKING:
3077 * spin_lock_irqsave(host_set lock)
3078 */
3079
1da177e4
LT
3080void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
3081 unsigned int n_elem)
3082{
3083 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 3084 qc->__sg = sg;
1da177e4 3085 qc->n_elem = n_elem;
cedc9a47 3086 qc->orig_n_elem = n_elem;
1da177e4
LT
3087}
3088
3089/**
0cba632b
JG
3090 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
3091 * @qc: Command with memory buffer to be mapped.
3092 *
3093 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT
3094 *
3095 * LOCKING:
3096 * spin_lock_irqsave(host_set lock)
3097 *
3098 * RETURNS:
0cba632b 3099 * Zero on success, negative on error.
1da177e4
LT
3100 */
3101
3102static int ata_sg_setup_one(struct ata_queued_cmd *qc)
3103{
3104 struct ata_port *ap = qc->ap;
3105 int dir = qc->dma_dir;
cedc9a47 3106 struct scatterlist *sg = qc->__sg;
1da177e4
LT
3107 dma_addr_t dma_address;
3108
cedc9a47
JG
3109 /* we must lengthen transfers to end on a 32-bit boundary */
3110 qc->pad_len = sg->length & 3;
3111 if (qc->pad_len) {
3112 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3113 struct scatterlist *psg = &qc->pad_sgent;
3114
3115 assert(qc->dev->class == ATA_DEV_ATAPI);
3116
3117 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
3118
3119 if (qc->tf.flags & ATA_TFLAG_WRITE)
3120 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
3121 qc->pad_len);
3122
3123 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
3124 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
3125 /* trim sg */
3126 sg->length -= qc->pad_len;
3127
3128 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
3129 sg->length, qc->pad_len);
3130 }
3131
e1410f2d
JG
3132 if (!sg->length) {
3133 sg_dma_address(sg) = 0;
3134 goto skip_map;
3135 }
3136
1da177e4 3137 dma_address = dma_map_single(ap->host_set->dev, qc->buf_virt,
32529e01 3138 sg->length, dir);
537a95d9
TH
3139 if (dma_mapping_error(dma_address)) {
3140 /* restore sg */
3141 sg->length += qc->pad_len;
1da177e4 3142 return -1;
537a95d9 3143 }
1da177e4
LT
3144
3145 sg_dma_address(sg) = dma_address;
e1410f2d 3146skip_map:
32529e01 3147 sg_dma_len(sg) = sg->length;
1da177e4
LT
3148
3149 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
3150 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3151
3152 return 0;
3153}
3154
3155/**
0cba632b
JG
3156 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
3157 * @qc: Command with scatter-gather table to be mapped.
3158 *
3159 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT
3160 *
3161 * LOCKING:
3162 * spin_lock_irqsave(host_set lock)
3163 *
3164 * RETURNS:
0cba632b 3165 * Zero on success, negative on error.
1da177e4
LT
3166 *
3167 */
3168
3169static int ata_sg_setup(struct ata_queued_cmd *qc)
3170{
3171 struct ata_port *ap = qc->ap;
cedc9a47
JG
3172 struct scatterlist *sg = qc->__sg;
3173 struct scatterlist *lsg = &sg[qc->n_elem - 1];
e1410f2d 3174 int n_elem, pre_n_elem, dir, trim_sg = 0;
1da177e4
LT
3175
3176 VPRINTK("ENTER, ata%u\n", ap->id);
3177 assert(qc->flags & ATA_QCFLAG_SG);
3178
cedc9a47
JG
3179 /* we must lengthen transfers to end on a 32-bit boundary */
3180 qc->pad_len = lsg->length & 3;
3181 if (qc->pad_len) {
3182 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3183 struct scatterlist *psg = &qc->pad_sgent;
3184 unsigned int offset;
3185
3186 assert(qc->dev->class == ATA_DEV_ATAPI);
3187
3188 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
3189
3190 /*
3191 * psg->page/offset are used to copy to-be-written
3192 * data in this function or read data in ata_sg_clean.
3193 */
3194 offset = lsg->offset + lsg->length - qc->pad_len;
3195 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
3196 psg->offset = offset_in_page(offset);
3197
3198 if (qc->tf.flags & ATA_TFLAG_WRITE) {
3199 void *addr = kmap_atomic(psg->page, KM_IRQ0);
3200 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
dfa15988 3201 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG
3202 }
3203
3204 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
3205 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
3206 /* trim last sg */
3207 lsg->length -= qc->pad_len;
e1410f2d
JG
3208 if (lsg->length == 0)
3209 trim_sg = 1;
cedc9a47
JG
3210
3211 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
3212 qc->n_elem - 1, lsg->length, qc->pad_len);
3213 }
3214
e1410f2d
JG
3215 pre_n_elem = qc->n_elem;
3216 if (trim_sg && pre_n_elem)
3217 pre_n_elem--;
3218
3219 if (!pre_n_elem) {
3220 n_elem = 0;
3221 goto skip_map;
3222 }
3223
1da177e4 3224 dir = qc->dma_dir;
e1410f2d 3225 n_elem = dma_map_sg(ap->host_set->dev, sg, pre_n_elem, dir);
537a95d9
TH
3226 if (n_elem < 1) {
3227 /* restore last sg */
3228 lsg->length += qc->pad_len;
1da177e4 3229 return -1;
537a95d9 3230 }
1da177e4
LT
3231
3232 DPRINTK("%d sg elements mapped\n", n_elem);
3233
e1410f2d 3234skip_map:
1da177e4
LT
3235 qc->n_elem = n_elem;
3236
3237 return 0;
3238}
3239
40e8c82c
TH
3240/**
3241 * ata_poll_qc_complete - turn irq back on and finish qc
3242 * @qc: Command to complete
8e8b77dd 3243 * @err_mask: ATA status register content
40e8c82c
TH
3244 *
3245 * LOCKING:
3246 * None. (grabs host lock)
3247 */
3248
a22e2eb0 3249void ata_poll_qc_complete(struct ata_queued_cmd *qc)
40e8c82c
TH
3250{
3251 struct ata_port *ap = qc->ap;
b8f6153e 3252 unsigned long flags;
40e8c82c 3253
b8f6153e 3254 spin_lock_irqsave(&ap->host_set->lock, flags);
40e8c82c
TH
3255 ap->flags &= ~ATA_FLAG_NOINTR;
3256 ata_irq_on(ap);
a22e2eb0 3257 ata_qc_complete(qc);
b8f6153e 3258 spin_unlock_irqrestore(&ap->host_set->lock, flags);
40e8c82c
TH
3259}
3260
1da177e4 3261/**
c893a3ae 3262 * ata_pio_poll - poll using PIO, depending on current state
6f0ef4fa 3263 * @ap: the target ata_port
1da177e4
LT
3264 *
3265 * LOCKING:
0cba632b 3266 * None. (executing in kernel thread context)
1da177e4
LT
3267 *
3268 * RETURNS:
6f0ef4fa 3269 * timeout value to use
1da177e4
LT
3270 */
3271
3272static unsigned long ata_pio_poll(struct ata_port *ap)
3273{
c14b8331 3274 struct ata_queued_cmd *qc;
1da177e4 3275 u8 status;
14be71f4
AL
3276 unsigned int poll_state = HSM_ST_UNKNOWN;
3277 unsigned int reg_state = HSM_ST_UNKNOWN;
14be71f4 3278
c14b8331
AL
3279 qc = ata_qc_from_tag(ap, ap->active_tag);
3280 assert(qc != NULL);
3281
14be71f4
AL
3282 switch (ap->hsm_task_state) {
3283 case HSM_ST:
3284 case HSM_ST_POLL:
3285 poll_state = HSM_ST_POLL;
3286 reg_state = HSM_ST;
1da177e4 3287 break;
14be71f4
AL
3288 case HSM_ST_LAST:
3289 case HSM_ST_LAST_POLL:
3290 poll_state = HSM_ST_LAST_POLL;
3291 reg_state = HSM_ST_LAST;
1da177e4
LT
3292 break;
3293 default:
3294 BUG();
3295 break;
3296 }
3297
3298 status = ata_chk_status(ap);
3299 if (status & ATA_BUSY) {
3300 if (time_after(jiffies, ap->pio_task_timeout)) {
11a56d24 3301 qc->err_mask |= AC_ERR_TIMEOUT;
7c398335 3302 ap->hsm_task_state = HSM_ST_TMOUT;
1da177e4
LT
3303 return 0;
3304 }
14be71f4 3305 ap->hsm_task_state = poll_state;
1da177e4
LT
3306 return ATA_SHORT_PAUSE;
3307 }
3308
14be71f4 3309 ap->hsm_task_state = reg_state;
1da177e4
LT
3310 return 0;
3311}
3312
3313/**
6f0ef4fa
RD
3314 * ata_pio_complete - check if drive is busy or idle
3315 * @ap: the target ata_port
1da177e4
LT
3316 *
3317 * LOCKING:
0cba632b 3318 * None. (executing in kernel thread context)
7fb6ec28
JG
3319 *
3320 * RETURNS:
3321 * Non-zero if qc completed, zero otherwise.
1da177e4
LT
3322 */
3323
7fb6ec28 3324static int ata_pio_complete (struct ata_port *ap)
1da177e4
LT
3325{
3326 struct ata_queued_cmd *qc;
3327 u8 drv_stat;
3328
3329 /*
31433ea3
AC
3330 * This is purely heuristic. This is a fast path. Sometimes when
3331 * we enter, BSY will be cleared in a chk-status or two. If not,
3332 * the drive is probably seeking or something. Snooze for a couple
3333 * msecs, then chk-status again. If still busy, fall back to
14be71f4 3334 * HSM_ST_POLL state.
1da177e4 3335 */
fe79e683
AL
3336 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
3337 if (drv_stat & ATA_BUSY) {
1da177e4 3338 msleep(2);
fe79e683
AL
3339 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
3340 if (drv_stat & ATA_BUSY) {
14be71f4 3341 ap->hsm_task_state = HSM_ST_LAST_POLL;
1da177e4 3342 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
7fb6ec28 3343 return 0;
1da177e4
LT
3344 }
3345 }
3346
c14b8331
AL
3347 qc = ata_qc_from_tag(ap, ap->active_tag);
3348 assert(qc != NULL);
3349
1da177e4
LT
3350 drv_stat = ata_wait_idle(ap);
3351 if (!ata_ok(drv_stat)) {
1c848984 3352 qc->err_mask |= __ac_err_mask(drv_stat);
14be71f4 3353 ap->hsm_task_state = HSM_ST_ERR;
7fb6ec28 3354 return 0;
1da177e4
LT
3355 }
3356
14be71f4 3357 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3358
a22e2eb0
AL
3359 assert(qc->err_mask == 0);
3360 ata_poll_qc_complete(qc);
7fb6ec28
JG
3361
3362 /* another command may start at this point */
3363
3364 return 1;
1da177e4
LT
3365}
3366
0baab86b
EF
3367
3368/**
c893a3ae 3369 * swap_buf_le16 - swap halves of 16-bit words in place
0baab86b
EF
3370 * @buf: Buffer to swap
3371 * @buf_words: Number of 16-bit words in buffer.
3372 *
3373 * Swap halves of 16-bit words if needed to convert from
3374 * little-endian byte order to native cpu byte order, or
3375 * vice-versa.
3376 *
3377 * LOCKING:
6f0ef4fa 3378 * Inherited from caller.
0baab86b 3379 */
1da177e4
LT
3380void swap_buf_le16(u16 *buf, unsigned int buf_words)
3381{
3382#ifdef __BIG_ENDIAN
3383 unsigned int i;
3384
3385 for (i = 0; i < buf_words; i++)
3386 buf[i] = le16_to_cpu(buf[i]);
3387#endif /* __BIG_ENDIAN */
3388}
3389
6ae4cfb5
AL
3390/**
3391 * ata_mmio_data_xfer - Transfer data by MMIO
3392 * @ap: port to read/write
3393 * @buf: data buffer
3394 * @buflen: buffer length
344babaa 3395 * @write_data: read/write
6ae4cfb5
AL
3396 *
3397 * Transfer data from/to the device data register by MMIO.
3398 *
3399 * LOCKING:
3400 * Inherited from caller.
6ae4cfb5
AL
3401 */
3402
1da177e4
LT
3403static void ata_mmio_data_xfer(struct ata_port *ap, unsigned char *buf,
3404 unsigned int buflen, int write_data)
3405{
3406 unsigned int i;
3407 unsigned int words = buflen >> 1;
3408 u16 *buf16 = (u16 *) buf;
3409 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
3410
6ae4cfb5 3411 /* Transfer multiple of 2 bytes */
1da177e4
LT
3412 if (write_data) {
3413 for (i = 0; i < words; i++)
3414 writew(le16_to_cpu(buf16[i]), mmio);
3415 } else {
3416 for (i = 0; i < words; i++)
3417 buf16[i] = cpu_to_le16(readw(mmio));
3418 }
6ae4cfb5
AL
3419
3420 /* Transfer trailing 1 byte, if any. */
3421 if (unlikely(buflen & 0x01)) {
3422 u16 align_buf[1] = { 0 };
3423 unsigned char *trailing_buf = buf + buflen - 1;
3424
3425 if (write_data) {
3426 memcpy(align_buf, trailing_buf, 1);
3427 writew(le16_to_cpu(align_buf[0]), mmio);
3428 } else {
3429 align_buf[0] = cpu_to_le16(readw(mmio));
3430 memcpy(trailing_buf, align_buf, 1);
3431 }
3432 }
1da177e4
LT
3433}
3434
6ae4cfb5
AL
3435/**
3436 * ata_pio_data_xfer - Transfer data by PIO
3437 * @ap: port to read/write
3438 * @buf: data buffer
3439 * @buflen: buffer length
344babaa 3440 * @write_data: read/write
6ae4cfb5
AL
3441 *
3442 * Transfer data from/to the device data register by PIO.
3443 *
3444 * LOCKING:
3445 * Inherited from caller.
6ae4cfb5
AL
3446 */
3447
1da177e4
LT
3448static void ata_pio_data_xfer(struct ata_port *ap, unsigned char *buf,
3449 unsigned int buflen, int write_data)
3450{
6ae4cfb5 3451 unsigned int words = buflen >> 1;
1da177e4 3452
6ae4cfb5 3453 /* Transfer multiple of 2 bytes */
1da177e4 3454 if (write_data)
6ae4cfb5 3455 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 3456 else
6ae4cfb5
AL
3457 insw(ap->ioaddr.data_addr, buf, words);
3458
3459 /* Transfer trailing 1 byte, if any. */
3460 if (unlikely(buflen & 0x01)) {
3461 u16 align_buf[1] = { 0 };
3462 unsigned char *trailing_buf = buf + buflen - 1;
3463
3464 if (write_data) {
3465 memcpy(align_buf, trailing_buf, 1);
3466 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
3467 } else {
3468 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
3469 memcpy(trailing_buf, align_buf, 1);
3470 }
3471 }
1da177e4
LT
3472}
3473
6ae4cfb5
AL
3474/**
3475 * ata_data_xfer - Transfer data from/to the data register.
3476 * @ap: port to read/write
3477 * @buf: data buffer
3478 * @buflen: buffer length
3479 * @do_write: read/write
3480 *
3481 * Transfer data from/to the device data register.
3482 *
3483 * LOCKING:
3484 * Inherited from caller.
6ae4cfb5
AL
3485 */
3486
1da177e4
LT
3487static void ata_data_xfer(struct ata_port *ap, unsigned char *buf,
3488 unsigned int buflen, int do_write)
3489{
a1bd9e68
AC
3490 /* Make the crap hardware pay the costs not the good stuff */
3491 if (unlikely(ap->flags & ATA_FLAG_IRQ_MASK)) {
3492 unsigned long flags;
3493 local_irq_save(flags);
3494 if (ap->flags & ATA_FLAG_MMIO)
3495 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3496 else
3497 ata_pio_data_xfer(ap, buf, buflen, do_write);
3498 local_irq_restore(flags);
3499 } else {
3500 if (ap->flags & ATA_FLAG_MMIO)
3501 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3502 else
3503 ata_pio_data_xfer(ap, buf, buflen, do_write);
3504 }
1da177e4
LT
3505}
3506
6ae4cfb5
AL
3507/**
3508 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
3509 * @qc: Command on going
3510 *
3511 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
3512 *
3513 * LOCKING:
3514 * Inherited from caller.
3515 */
3516
1da177e4
LT
3517static void ata_pio_sector(struct ata_queued_cmd *qc)
3518{
3519 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3520 struct scatterlist *sg = qc->__sg;
1da177e4
LT
3521 struct ata_port *ap = qc->ap;
3522 struct page *page;
3523 unsigned int offset;
3524 unsigned char *buf;
3525
3526 if (qc->cursect == (qc->nsect - 1))
14be71f4 3527 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT
3528
3529 page = sg[qc->cursg].page;
3530 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
3531
3532 /* get the current page and offset */
3533 page = nth_page(page, (offset >> PAGE_SHIFT));
3534 offset %= PAGE_SIZE;
3535
3536 buf = kmap(page) + offset;
3537
3538 qc->cursect++;
3539 qc->cursg_ofs++;
3540
32529e01 3541 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
1da177e4
LT
3542 qc->cursg++;
3543 qc->cursg_ofs = 0;
3544 }
3545
3546 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3547
3548 /* do the actual data transfer */
3549 do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
3550 ata_data_xfer(ap, buf, ATA_SECT_SIZE, do_write);
3551
3552 kunmap(page);
3553}
3554
6ae4cfb5
AL
3555/**
3556 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3557 * @qc: Command on going
3558 * @bytes: number of bytes
3559 *
3560 * Transfer Transfer data from/to the ATAPI device.
3561 *
3562 * LOCKING:
3563 * Inherited from caller.
3564 *
3565 */
3566
1da177e4
LT
3567static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3568{
3569 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3570 struct scatterlist *sg = qc->__sg;
1da177e4
LT
3571 struct ata_port *ap = qc->ap;
3572 struct page *page;
3573 unsigned char *buf;
3574 unsigned int offset, count;
3575
563a6e1f 3576 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3577 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT
3578
3579next_sg:
563a6e1f 3580 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3581 /*
563a6e1f
AL
3582 * The end of qc->sg is reached and the device expects
3583 * more data to transfer. In order not to overrun qc->sg
3584 * and fulfill length specified in the byte count register,
3585 * - for read case, discard trailing data from the device
3586 * - for write case, padding zero data to the device
3587 */
3588 u16 pad_buf[1] = { 0 };
3589 unsigned int words = bytes >> 1;
3590 unsigned int i;
3591
3592 if (words) /* warning if bytes > 1 */
7fb6ec28 3593 printk(KERN_WARNING "ata%u: %u bytes trailing data\n",
563a6e1f
AL
3594 ap->id, bytes);
3595
3596 for (i = 0; i < words; i++)
3597 ata_data_xfer(ap, (unsigned char*)pad_buf, 2, do_write);
3598
14be71f4 3599 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL
3600 return;
3601 }
3602
cedc9a47 3603 sg = &qc->__sg[qc->cursg];
1da177e4 3604
1da177e4
LT
3605 page = sg->page;
3606 offset = sg->offset + qc->cursg_ofs;
3607
3608 /* get the current page and offset */
3609 page = nth_page(page, (offset >> PAGE_SHIFT));
3610 offset %= PAGE_SIZE;
3611
6952df03 3612 /* don't overrun current sg */
32529e01 3613 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT
3614
3615 /* don't cross page boundaries */
3616 count = min(count, (unsigned int)PAGE_SIZE - offset);
3617
3618 buf = kmap(page) + offset;
3619
3620 bytes -= count;
3621 qc->curbytes += count;
3622 qc->cursg_ofs += count;
3623
32529e01 3624 if (qc->cursg_ofs == sg->length) {
1da177e4
LT
3625 qc->cursg++;
3626 qc->cursg_ofs = 0;
3627 }
3628
3629 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3630
3631 /* do the actual data transfer */
3632 ata_data_xfer(ap, buf, count, do_write);
3633
3634 kunmap(page);
3635
563a6e1f 3636 if (bytes)
1da177e4 3637 goto next_sg;
1da177e4
LT
3638}
3639
6ae4cfb5
AL
3640/**
3641 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
3642 * @qc: Command on going
3643 *
3644 * Transfer Transfer data from/to the ATAPI device.
3645 *
3646 * LOCKING:
3647 * Inherited from caller.
6ae4cfb5
AL
3648 */
3649
1da177e4
LT
3650static void atapi_pio_bytes(struct ata_queued_cmd *qc)
3651{
3652 struct ata_port *ap = qc->ap;
3653 struct ata_device *dev = qc->dev;
3654 unsigned int ireason, bc_lo, bc_hi, bytes;
3655 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
3656
3657 ap->ops->tf_read(ap, &qc->tf);
3658 ireason = qc->tf.nsect;
3659 bc_lo = qc->tf.lbam;
3660 bc_hi = qc->tf.lbah;
3661 bytes = (bc_hi << 8) | bc_lo;
3662
3663 /* shall be cleared to zero, indicating xfer of data */
3664 if (ireason & (1 << 0))
3665 goto err_out;
3666
3667 /* make sure transfer direction matches expected */
3668 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
3669 if (do_write != i_write)
3670 goto err_out;
3671
3672 __atapi_pio_bytes(qc, bytes);
3673
3674 return;
3675
3676err_out:
3677 printk(KERN_INFO "ata%u: dev %u: ATAPI check failed\n",
3678 ap->id, dev->devno);
11a56d24 3679 qc->err_mask |= AC_ERR_HSM;
14be71f4 3680 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT
3681}
3682
3683/**
6f0ef4fa
RD
3684 * ata_pio_block - start PIO on a block
3685 * @ap: the target ata_port
1da177e4
LT
3686 *
3687 * LOCKING:
0cba632b 3688 * None. (executing in kernel thread context)
1da177e4
LT
3689 */
3690
3691static void ata_pio_block(struct ata_port *ap)
3692{
3693 struct ata_queued_cmd *qc;
3694 u8 status;
3695
3696 /*
6f0ef4fa 3697 * This is purely heuristic. This is a fast path.
1da177e4
LT
3698 * Sometimes when we enter, BSY will be cleared in
3699 * a chk-status or two. If not, the drive is probably seeking
3700 * or something. Snooze for a couple msecs, then
3701 * chk-status again. If still busy, fall back to
14be71f4 3702 * HSM_ST_POLL state.
1da177e4
LT
3703 */
3704 status = ata_busy_wait(ap, ATA_BUSY, 5);
3705 if (status & ATA_BUSY) {
3706 msleep(2);
3707 status = ata_busy_wait(ap, ATA_BUSY, 10);
3708 if (status & ATA_BUSY) {
14be71f4 3709 ap->hsm_task_state = HSM_ST_POLL;
1da177e4
LT
3710 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
3711 return;
3712 }
3713 }
3714
3715 qc = ata_qc_from_tag(ap, ap->active_tag);
3716 assert(qc != NULL);
3717
fe79e683
AL
3718 /* check error */
3719 if (status & (ATA_ERR | ATA_DF)) {
3720 qc->err_mask |= AC_ERR_DEV;
3721 ap->hsm_task_state = HSM_ST_ERR;
3722 return;
3723 }
3724
3725 /* transfer data if any */
1da177e4 3726 if (is_atapi_taskfile(&qc->tf)) {
fe79e683 3727 /* DRQ=0 means no more data to transfer */
1da177e4 3728 if ((status & ATA_DRQ) == 0) {
14be71f4 3729 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT
3730 return;
3731 }
3732
3733 atapi_pio_bytes(qc);
3734 } else {
3735 /* handle BSY=0, DRQ=0 as error */
3736 if ((status & ATA_DRQ) == 0) {
11a56d24 3737 qc->err_mask |= AC_ERR_HSM;
14be71f4 3738 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT
3739 return;
3740 }
3741
3742 ata_pio_sector(qc);
3743 }
3744}
3745
3746static void ata_pio_error(struct ata_port *ap)
3747{
3748 struct ata_queued_cmd *qc;
a7dac447
JG
3749
3750 printk(KERN_WARNING "ata%u: PIO error\n", ap->id);
1da177e4
LT
3751
3752 qc = ata_qc_from_tag(ap, ap->active_tag);
3753 assert(qc != NULL);
3754
1c848984
AL
3755 /* make sure qc->err_mask is available to
3756 * know what's wrong and recover
3757 */
3758 assert(qc->err_mask);
3759
14be71f4 3760 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3761
a22e2eb0 3762 ata_poll_qc_complete(qc);
1da177e4
LT
3763}
3764
3765static void ata_pio_task(void *_data)
3766{
3767 struct ata_port *ap = _data;
7fb6ec28
JG
3768 unsigned long timeout;
3769 int qc_completed;
3770
3771fsm_start:
3772 timeout = 0;
3773 qc_completed = 0;
1da177e4 3774
14be71f4
AL
3775 switch (ap->hsm_task_state) {
3776 case HSM_ST_IDLE:
1da177e4
LT
3777 return;
3778
14be71f4 3779 case HSM_ST:
1da177e4
LT
3780 ata_pio_block(ap);
3781 break;
3782
14be71f4 3783 case HSM_ST_LAST:
7fb6ec28 3784 qc_completed = ata_pio_complete(ap);
1da177e4
LT
3785 break;
3786
14be71f4
AL
3787 case HSM_ST_POLL:
3788 case HSM_ST_LAST_POLL:
1da177e4
LT
3789 timeout = ata_pio_poll(ap);
3790 break;
3791
14be71f4
AL
3792 case HSM_ST_TMOUT:
3793 case HSM_ST_ERR:
1da177e4
LT
3794 ata_pio_error(ap);
3795 return;
3796 }
3797
3798 if (timeout)
95064379 3799 ata_queue_delayed_pio_task(ap, timeout);
7fb6ec28
JG
3800 else if (!qc_completed)
3801 goto fsm_start;
1da177e4
LT
3802}
3803
1da177e4
LT
3804/**
3805 * ata_qc_timeout - Handle timeout of queued command
3806 * @qc: Command that timed out
3807 *
3808 * Some part of the kernel (currently, only the SCSI layer)
3809 * has noticed that the active command on port @ap has not
3810 * completed after a specified length of time. Handle this
3811 * condition by disabling DMA (if necessary) and completing
3812 * transactions, with error if necessary.
3813 *
3814 * This also handles the case of the "lost interrupt", where
3815 * for some reason (possibly hardware bug, possibly driver bug)
3816 * an interrupt was not delivered to the driver, even though the
3817 * transaction completed successfully.
3818 *
3819 * LOCKING:
0cba632b 3820 * Inherited from SCSI layer (none, can sleep)
1da177e4
LT
3821 */
3822
3823static void ata_qc_timeout(struct ata_queued_cmd *qc)
3824{
3825 struct ata_port *ap = qc->ap;
b8f6153e 3826 struct ata_host_set *host_set = ap->host_set;
1da177e4 3827 u8 host_stat = 0, drv_stat;
b8f6153e 3828 unsigned long flags;
1da177e4
LT
3829
3830 DPRINTK("ENTER\n");
3831
c18d06f8
TH
3832 ata_flush_pio_tasks(ap);
3833 ap->hsm_task_state = HSM_ST_IDLE;
3834
b8f6153e
JG
3835 spin_lock_irqsave(&host_set->lock, flags);
3836
1da177e4
LT
3837 switch (qc->tf.protocol) {
3838
3839 case ATA_PROT_DMA:
3840 case ATA_PROT_ATAPI_DMA:
3841 host_stat = ap->ops->bmdma_status(ap);
3842
3843 /* before we do anything else, clear DMA-Start bit */
b73fc89f 3844 ap->ops->bmdma_stop(qc);
1da177e4
LT
3845
3846 /* fall through */
3847
3848 default:
3849 ata_altstatus(ap);
3850 drv_stat = ata_chk_status(ap);
3851
3852 /* ack bmdma irq events */
3853 ap->ops->irq_clear(ap);
3854
3855 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x host_stat 0x%x\n",
3856 ap->id, qc->tf.command, drv_stat, host_stat);
3857
3858 /* complete taskfile transaction */
a22e2eb0 3859 qc->err_mask |= ac_err_mask(drv_stat);
1da177e4
LT
3860 break;
3861 }
b8f6153e
JG
3862
3863 spin_unlock_irqrestore(&host_set->lock, flags);
3864
a72ec4ce
TH
3865 ata_eh_qc_complete(qc);
3866
1da177e4
LT
3867 DPRINTK("EXIT\n");
3868}
3869
3870/**
3871 * ata_eng_timeout - Handle timeout of queued command
3872 * @ap: Port on which timed-out command is active
3873 *
3874 * Some part of the kernel (currently, only the SCSI layer)
3875 * has noticed that the active command on port @ap has not
3876 * completed after a specified length of time. Handle this
3877 * condition by disabling DMA (if necessary) and completing
3878 * transactions, with error if necessary.
3879 *
3880 * This also handles the case of the "lost interrupt", where
3881 * for some reason (possibly hardware bug, possibly driver bug)
3882 * an interrupt was not delivered to the driver, even though the
3883 * transaction completed successfully.
3884 *
3885 * LOCKING:
3886 * Inherited from SCSI layer (none, can sleep)
3887 */
3888
3889void ata_eng_timeout(struct ata_port *ap)
3890{
3891 struct ata_queued_cmd *qc;
3892
3893 DPRINTK("ENTER\n");
3894
3895 qc = ata_qc_from_tag(ap, ap->active_tag);
e12669e7
JG
3896 if (qc)
3897 ata_qc_timeout(qc);
3898 else {
1da177e4
LT
3899 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
3900 ap->id);
3901 goto out;
3902 }
3903
1da177e4
LT
3904out:
3905 DPRINTK("EXIT\n");
3906}
3907
3908/**
3909 * ata_qc_new - Request an available ATA command, for queueing
3910 * @ap: Port associated with device @dev
3911 * @dev: Device from whom we request an available command structure
3912 *
3913 * LOCKING:
0cba632b 3914 * None.
1da177e4
LT
3915 */
3916
3917static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
3918{
3919 struct ata_queued_cmd *qc = NULL;
3920 unsigned int i;
3921
3922 for (i = 0; i < ATA_MAX_QUEUE; i++)
3923 if (!test_and_set_bit(i, &ap->qactive)) {
3924 qc = ata_qc_from_tag(ap, i);
3925 break;
3926 }
3927
3928 if (qc)
3929 qc->tag = i;
3930
3931 return qc;
3932}
3933
3934/**
3935 * ata_qc_new_init - Request an available ATA command, and initialize it
3936 * @ap: Port associated with device @dev
3937 * @dev: Device from whom we request an available command structure
3938 *
3939 * LOCKING:
0cba632b 3940 * None.
1da177e4
LT
3941 */
3942
3943struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap,
3944 struct ata_device *dev)
3945{
3946 struct ata_queued_cmd *qc;
3947
3948 qc = ata_qc_new(ap);
3949 if (qc) {
1da177e4
LT
3950 qc->scsicmd = NULL;
3951 qc->ap = ap;
3952 qc->dev = dev;
1da177e4 3953
2c13b7ce 3954 ata_qc_reinit(qc);
1da177e4
LT
3955 }
3956
3957 return qc;
3958}
3959
1da177e4
LT
3960/**
3961 * ata_qc_free - free unused ata_queued_cmd
3962 * @qc: Command to complete
3963 *
3964 * Designed to free unused ata_queued_cmd object
3965 * in case something prevents using it.
3966 *
3967 * LOCKING:
0cba632b 3968 * spin_lock_irqsave(host_set lock)
1da177e4
LT
3969 */
3970void ata_qc_free(struct ata_queued_cmd *qc)
3971{
4ba946e9
TH
3972 struct ata_port *ap = qc->ap;
3973 unsigned int tag;
3974
1da177e4 3975 assert(qc != NULL); /* ata_qc_from_tag _might_ return NULL */
1da177e4 3976
4ba946e9
TH
3977 qc->flags = 0;
3978 tag = qc->tag;
3979 if (likely(ata_tag_valid(tag))) {
3980 if (tag == ap->active_tag)
3981 ap->active_tag = ATA_TAG_POISON;
3982 qc->tag = ATA_TAG_POISON;
3983 clear_bit(tag, &ap->qactive);
3984 }
1da177e4
LT
3985}
3986
3987/**
3988 * ata_qc_complete - Complete an active ATA command
3989 * @qc: Command to complete
8e8b77dd 3990 * @err_mask: ATA Status register contents
0cba632b
JG
3991 *
3992 * Indicate to the mid and upper layers that an ATA
3993 * command has completed, with either an ok or not-ok status.
1da177e4
LT
3994 *
3995 * LOCKING:
0cba632b 3996 * spin_lock_irqsave(host_set lock)
1da177e4
LT
3997 */
3998
a22e2eb0 3999void ata_qc_complete(struct ata_queued_cmd *qc)
1da177e4 4000{
1da177e4
LT
4001 assert(qc != NULL); /* ata_qc_from_tag _might_ return NULL */
4002 assert(qc->flags & ATA_QCFLAG_ACTIVE);
4003
4004 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
4005 ata_sg_clean(qc);
4006
3f3791d3
AL
4007 /* atapi: mark qc as inactive to prevent the interrupt handler
4008 * from completing the command twice later, before the error handler
4009 * is called. (when rc != 0 and atapi request sense is needed)
4010 */
4011 qc->flags &= ~ATA_QCFLAG_ACTIVE;
4012
1da177e4 4013 /* call completion callback */
77853bf2 4014 qc->complete_fn(qc);
1da177e4
LT
4015}
4016
4017static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
4018{
4019 struct ata_port *ap = qc->ap;
4020
4021 switch (qc->tf.protocol) {
4022 case ATA_PROT_DMA:
4023 case ATA_PROT_ATAPI_DMA:
4024 return 1;
4025
4026 case ATA_PROT_ATAPI:
4027 case ATA_PROT_PIO:
4028 case ATA_PROT_PIO_MULT:
4029 if (ap->flags & ATA_FLAG_PIO_DMA)
4030 return 1;
4031
4032 /* fall through */
4033
4034 default:
4035 return 0;
4036 }
4037
4038 /* never reached */
4039}
4040
4041/**
4042 * ata_qc_issue - issue taskfile to device
4043 * @qc: command to issue to device
4044 *
4045 * Prepare an ATA command to submission to device.
4046 * This includes mapping the data into a DMA-able
4047 * area, filling in the S/G table, and finally
4048 * writing the taskfile to hardware, starting the command.
4049 *
4050 * LOCKING:
4051 * spin_lock_irqsave(host_set lock)
4052 *
4053 * RETURNS:
9a3d9eb0 4054 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT
4055 */
4056
9a3d9eb0 4057unsigned int ata_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT
4058{
4059 struct ata_port *ap = qc->ap;
4060
4061 if (ata_should_dma_map(qc)) {
4062 if (qc->flags & ATA_QCFLAG_SG) {
4063 if (ata_sg_setup(qc))
8e436af9 4064 goto sg_err;
1da177e4
LT
4065 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
4066 if (ata_sg_setup_one(qc))
8e436af9 4067 goto sg_err;
1da177e4
LT
4068 }
4069 } else {
4070 qc->flags &= ~ATA_QCFLAG_DMAMAP;
4071 }
4072
4073 ap->ops->qc_prep(qc);
4074
4075 qc->ap->active_tag = qc->tag;
4076 qc->flags |= ATA_QCFLAG_ACTIVE;
4077
4078 return ap->ops->qc_issue(qc);
4079
8e436af9
TH
4080sg_err:
4081 qc->flags &= ~ATA_QCFLAG_DMAMAP;
9a3d9eb0 4082 return AC_ERR_SYSTEM;
1da177e4
LT
4083}
4084
0baab86b 4085
1da177e4
LT
4086/**
4087 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
4088 * @qc: command to issue to device
4089 *
4090 * Using various libata functions and hooks, this function
4091 * starts an ATA command. ATA commands are grouped into
4092 * classes called "protocols", and issuing each type of protocol
4093 * is slightly different.
4094 *
0baab86b
EF
4095 * May be used as the qc_issue() entry in ata_port_operations.
4096 *
1da177e4
LT
4097 * LOCKING:
4098 * spin_lock_irqsave(host_set lock)
4099 *
4100 * RETURNS:
9a3d9eb0 4101 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT
4102 */
4103
9a3d9eb0 4104unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
1da177e4
LT
4105{
4106 struct ata_port *ap = qc->ap;
4107
4108 ata_dev_select(ap, qc->dev->devno, 1, 0);
4109
4110 switch (qc->tf.protocol) {
4111 case ATA_PROT_NODATA:
e5338254 4112 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT
4113 break;
4114
4115 case ATA_PROT_DMA:
4116 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
4117 ap->ops->bmdma_setup(qc); /* set up bmdma */
4118 ap->ops->bmdma_start(qc); /* initiate bmdma */
4119 break;
4120
4121 case ATA_PROT_PIO: /* load tf registers, initiate polling pio */
4122 ata_qc_set_polling(qc);
e5338254 4123 ata_tf_to_host(ap, &qc->tf);
14be71f4 4124 ap->hsm_task_state = HSM_ST;
95064379 4125 ata_queue_pio_task(ap);
1da177e4
LT
4126 break;
4127
4128 case ATA_PROT_ATAPI:
4129 ata_qc_set_polling(qc);
e5338254 4130 ata_tf_to_host(ap, &qc->tf);
95064379 4131 ata_queue_packet_task(ap);
1da177e4
LT
4132 break;
4133
4134 case ATA_PROT_ATAPI_NODATA:
c1389503 4135 ap->flags |= ATA_FLAG_NOINTR;
e5338254 4136 ata_tf_to_host(ap, &qc->tf);
95064379 4137 ata_queue_packet_task(ap);
1da177e4
LT
4138 break;
4139
4140 case ATA_PROT_ATAPI_DMA:
c1389503 4141 ap->flags |= ATA_FLAG_NOINTR;
1da177e4
LT
4142 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
4143 ap->ops->bmdma_setup(qc); /* set up bmdma */
95064379 4144 ata_queue_packet_task(ap);
1da177e4
LT
4145 break;
4146
4147 default:
4148 WARN_ON(1);
9a3d9eb0 4149 return AC_ERR_SYSTEM;
1da177e4
LT
4150 }
4151
4152 return 0;
4153}
4154
4155/**
0baab86b 4156 * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
1da177e4
LT
4157 * @qc: Info associated with this ATA transaction.
4158 *
4159 * LOCKING:
4160 * spin_lock_irqsave(host_set lock)
4161 */
4162
4163static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc)
4164{
4165 struct ata_port *ap = qc->ap;
4166 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
4167 u8 dmactl;
4168 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4169
4170 /* load PRD table addr. */
4171 mb(); /* make sure PRD table writes are visible to controller */
4172 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
4173
4174 /* specify data direction, triple-check start bit is clear */
4175 dmactl = readb(mmio + ATA_DMA_CMD);
4176 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
4177 if (!rw)
4178 dmactl |= ATA_DMA_WR;
4179 writeb(dmactl, mmio + ATA_DMA_CMD);
4180
4181 /* issue r/w command */
4182 ap->ops->exec_command(ap, &qc->tf);
4183}
4184
4185/**
b73fc89f 4186 * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction
1da177e4
LT
4187 * @qc: Info associated with this ATA transaction.
4188 *
4189 * LOCKING:
4190 * spin_lock_irqsave(host_set lock)
4191 */
4192
4193static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc)
4194{
4195 struct ata_port *ap = qc->ap;
4196 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4197 u8 dmactl;
4198
4199 /* start host DMA transaction */
4200 dmactl = readb(mmio + ATA_DMA_CMD);
4201 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
4202
4203 /* Strictly, one may wish to issue a readb() here, to
4204 * flush the mmio write. However, control also passes
4205 * to the hardware at this point, and it will interrupt
4206 * us when we are to resume control. So, in effect,
4207 * we don't care when the mmio write flushes.
4208 * Further, a read of the DMA status register _immediately_
4209 * following the write may not be what certain flaky hardware
4210 * is expected, so I think it is best to not add a readb()
4211 * without first all the MMIO ATA cards/mobos.
4212 * Or maybe I'm just being paranoid.
4213 */
4214}
4215
4216/**
4217 * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO)
4218 * @qc: Info associated with this ATA transaction.
4219 *
4220 * LOCKING:
4221 * spin_lock_irqsave(host_set lock)
4222 */
4223
4224static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc)
4225{
4226 struct ata_port *ap = qc->ap;
4227 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
4228 u8 dmactl;
4229
4230 /* load PRD table addr. */
4231 outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
4232
4233 /* specify data direction, triple-check start bit is clear */
4234 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4235 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
4236 if (!rw)
4237 dmactl |= ATA_DMA_WR;
4238 outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4239
4240 /* issue r/w command */
4241 ap->ops->exec_command(ap, &qc->tf);
4242}
4243
4244/**
4245 * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO)
4246 * @qc: Info associated with this ATA transaction.
4247 *
4248 * LOCKING:
4249 * spin_lock_irqsave(host_set lock)
4250 */
4251
4252static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
4253{
4254 struct ata_port *ap = qc->ap;
4255 u8 dmactl;
4256
4257 /* start host DMA transaction */
4258 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4259 outb(dmactl | ATA_DMA_START,
4260 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4261}
4262
0baab86b
EF
4263
4264/**
4265 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
4266 * @qc: Info associated with this ATA transaction.
4267 *
4268 * Writes the ATA_DMA_START flag to the DMA command register.
4269 *
4270 * May be used as the bmdma_start() entry in ata_port_operations.
4271 *
4272 * LOCKING:
4273 * spin_lock_irqsave(host_set lock)
4274 */
1da177e4
LT
4275void ata_bmdma_start(struct ata_queued_cmd *qc)
4276{
4277 if (qc->ap->flags & ATA_FLAG_MMIO)
4278 ata_bmdma_start_mmio(qc);
4279 else
4280 ata_bmdma_start_pio(qc);
4281}
4282
0baab86b
EF
4283
4284/**
4285 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
4286 * @qc: Info associated with this ATA transaction.
4287 *
4288 * Writes address of PRD table to device's PRD Table Address
4289 * register, sets the DMA control register, and calls
4290 * ops->exec_command() to start the transfer.
4291 *
4292 * May be used as the bmdma_setup() entry in ata_port_operations.
4293 *
4294 * LOCKING:
4295 * spin_lock_irqsave(host_set lock)
4296 */
1da177e4
LT
4297void ata_bmdma_setup(struct ata_queued_cmd *qc)
4298{
4299 if (qc->ap->flags & ATA_FLAG_MMIO)
4300 ata_bmdma_setup_mmio(qc);
4301 else
4302 ata_bmdma_setup_pio(qc);
4303}
4304
0baab86b
EF
4305
4306/**
4307 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
decc6d0b 4308 * @ap: Port associated with this ATA transaction.
0baab86b
EF
4309 *
4310 * Clear interrupt and error flags in DMA status register.
4311 *
4312 * May be used as the irq_clear() entry in ata_port_operations.
4313 *
4314 * LOCKING:
4315 * spin_lock_irqsave(host_set lock)
4316 */
4317
1da177e4
LT
4318void ata_bmdma_irq_clear(struct ata_port *ap)
4319{
4320 if (ap->flags & ATA_FLAG_MMIO) {
4321 void __iomem *mmio = ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS;
4322 writeb(readb(mmio), mmio);
4323 } else {
4324 unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
4325 outb(inb(addr), addr);
4326 }
4327
4328}
4329
0baab86b
EF
4330
4331/**
4332 * ata_bmdma_status - Read PCI IDE BMDMA status
decc6d0b 4333 * @ap: Port associated with this ATA transaction.
0baab86b
EF
4334 *
4335 * Read and return BMDMA status register.
4336 *
4337 * May be used as the bmdma_status() entry in ata_port_operations.
4338 *
4339 * LOCKING:
4340 * spin_lock_irqsave(host_set lock)
4341 */
4342
1da177e4
LT
4343u8 ata_bmdma_status(struct ata_port *ap)
4344{
4345 u8 host_stat;
4346 if (ap->flags & ATA_FLAG_MMIO) {
4347 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4348 host_stat = readb(mmio + ATA_DMA_STATUS);
4349 } else
ee500aab 4350 host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
1da177e4
LT
4351 return host_stat;
4352}
4353
0baab86b
EF
4354
4355/**
4356 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
b73fc89f 4357 * @qc: Command we are ending DMA for
0baab86b
EF
4358 *
4359 * Clears the ATA_DMA_START flag in the dma control register
4360 *
4361 * May be used as the bmdma_stop() entry in ata_port_operations.
4362 *
4363 * LOCKING:
4364 * spin_lock_irqsave(host_set lock)
4365 */
4366
b73fc89f 4367void ata_bmdma_stop(struct ata_queued_cmd *qc)
1da177e4 4368{
b73fc89f 4369 struct ata_port *ap = qc->ap;
1da177e4
LT
4370 if (ap->flags & ATA_FLAG_MMIO) {
4371 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4372
4373 /* clear start/stop bit */
4374 writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
4375 mmio + ATA_DMA_CMD);
4376 } else {
4377 /* clear start/stop bit */
4378 outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
4379 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4380 }
4381
4382 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
4383 ata_altstatus(ap); /* dummy read */
4384}
4385
4386/**
4387 * ata_host_intr - Handle host interrupt for given (port, task)
4388 * @ap: Port on which interrupt arrived (possibly...)
4389 * @qc: Taskfile currently active in engine
4390 *
4391 * Handle host interrupt for given queued command. Currently,
4392 * only DMA interrupts are handled. All other commands are
4393 * handled via polling with interrupts disabled (nIEN bit).
4394 *
4395 * LOCKING:
4396 * spin_lock_irqsave(host_set lock)
4397 *
4398 * RETURNS:
4399 * One if interrupt was handled, zero if not (shared irq).
4400 */
4401
4402inline unsigned int ata_host_intr (struct ata_port *ap,
4403 struct ata_queued_cmd *qc)
4404{
4405 u8 status, host_stat;
4406
4407 switch (qc->tf.protocol) {
4408
4409 case ATA_PROT_DMA:
4410 case ATA_PROT_ATAPI_DMA:
4411 case ATA_PROT_ATAPI:
4412 /* check status of DMA engine */
4413 host_stat = ap->ops->bmdma_status(ap);
4414 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
4415
4416 /* if it's not our irq... */
4417 if (!(host_stat & ATA_DMA_INTR))
4418 goto idle_irq;
4419
4420 /* before we do anything else, clear DMA-Start bit */
b73fc89f 4421 ap->ops->bmdma_stop(qc);
1da177e4
LT
4422
4423 /* fall through */
4424
4425 case ATA_PROT_ATAPI_NODATA:
4426 case ATA_PROT_NODATA:
4427 /* check altstatus */
4428 status = ata_altstatus(ap);
4429 if (status & ATA_BUSY)
4430 goto idle_irq;
4431
4432 /* check main status, clearing INTRQ */
4433 status = ata_chk_status(ap);
4434 if (unlikely(status & ATA_BUSY))
4435 goto idle_irq;
4436 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
4437 ap->id, qc->tf.protocol, status);
4438
4439 /* ack bmdma irq events */
4440 ap->ops->irq_clear(ap);
4441
4442 /* complete taskfile transaction */
a22e2eb0
AL
4443 qc->err_mask |= ac_err_mask(status);
4444 ata_qc_complete(qc);
1da177e4
LT
4445 break;
4446
4447 default:
4448 goto idle_irq;
4449 }
4450
4451 return 1; /* irq handled */
4452
4453idle_irq:
4454 ap->stats.idle_irq++;
4455
4456#ifdef ATA_IRQ_TRAP
4457 if ((ap->stats.idle_irq % 1000) == 0) {
4458 handled = 1;
4459 ata_irq_ack(ap, 0); /* debug trap */
4460 printk(KERN_WARNING "ata%d: irq trap\n", ap->id);
4461 }
4462#endif
4463 return 0; /* irq not handled */
4464}
4465
4466/**
4467 * ata_interrupt - Default ATA host interrupt handler
0cba632b
JG
4468 * @irq: irq line (unused)
4469 * @dev_instance: pointer to our ata_host_set information structure
1da177e4
LT
4470 * @regs: unused
4471 *
0cba632b
JG
4472 * Default interrupt handler for PCI IDE devices. Calls
4473 * ata_host_intr() for each port that is not disabled.
4474 *
1da177e4 4475 * LOCKING:
0cba632b 4476 * Obtains host_set lock during operation.
1da177e4
LT
4477 *
4478 * RETURNS:
0cba632b 4479 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT
4480 */
4481
4482irqreturn_t ata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
4483{
4484 struct ata_host_set *host_set = dev_instance;
4485 unsigned int i;
4486 unsigned int handled = 0;
4487 unsigned long flags;
4488
4489 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
4490 spin_lock_irqsave(&host_set->lock, flags);
4491
4492 for (i = 0; i < host_set->n_ports; i++) {
4493 struct ata_port *ap;
4494
4495 ap = host_set->ports[i];
c1389503
TH
4496 if (ap &&
4497 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
1da177e4
LT
4498 struct ata_queued_cmd *qc;
4499
4500 qc = ata_qc_from_tag(ap, ap->active_tag);
21b1ed74
AL
4501 if (qc && (!(qc->tf.ctl & ATA_NIEN)) &&
4502 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT
4503 handled |= ata_host_intr(ap, qc);
4504 }
4505 }
4506
4507 spin_unlock_irqrestore(&host_set->lock, flags);
4508
4509 return IRQ_RETVAL(handled);
4510}
4511
4512/**
4513 * atapi_packet_task - Write CDB bytes to hardware
4514 * @_data: Port to which ATAPI device is attached.
4515 *
4516 * When device has indicated its readiness to accept
4517 * a CDB, this function is called. Send the CDB.
4518 * If DMA is to be performed, exit immediately.
4519 * Otherwise, we are in polling mode, so poll
4520 * status under operation succeeds or fails.
4521 *
4522 * LOCKING:
4523 * Kernel thread context (may sleep)
4524 */
4525
4526static void atapi_packet_task(void *_data)
4527{
4528 struct ata_port *ap = _data;
4529 struct ata_queued_cmd *qc;
4530 u8 status;
4531
4532 qc = ata_qc_from_tag(ap, ap->active_tag);
4533 assert(qc != NULL);
4534 assert(qc->flags & ATA_QCFLAG_ACTIVE);
4535
4536 /* sleep-wait for BSY to clear */
4537 DPRINTK("busy wait\n");
d8fe452b 4538 if (ata_busy_sleep(ap, ATA_TMOUT_CDB_QUICK, ATA_TMOUT_CDB)) {
11a56d24 4539 qc->err_mask |= AC_ERR_TIMEOUT;
d8fe452b
AL
4540 goto err_out;
4541 }
1da177e4
LT
4542
4543 /* make sure DRQ is set */
4544 status = ata_chk_status(ap);
d8fe452b 4545 if ((status & (ATA_BUSY | ATA_DRQ)) != ATA_DRQ) {
11a56d24 4546 qc->err_mask |= AC_ERR_HSM;
1da177e4 4547 goto err_out;
d8fe452b 4548 }
1da177e4
LT
4549
4550 /* send SCSI cdb */
4551 DPRINTK("send cdb\n");
4552 assert(ap->cdb_len >= 12);
1da177e4 4553
c1389503
TH
4554 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA ||
4555 qc->tf.protocol == ATA_PROT_ATAPI_NODATA) {
4556 unsigned long flags;
1da177e4 4557
c1389503
TH
4558 /* Once we're done issuing command and kicking bmdma,
4559 * irq handler takes over. To not lose irq, we need
4560 * to clear NOINTR flag before sending cdb, but
4561 * interrupt handler shouldn't be invoked before we're
4562 * finished. Hence, the following locking.
4563 */
4564 spin_lock_irqsave(&ap->host_set->lock, flags);
4565 ap->flags &= ~ATA_FLAG_NOINTR;
4566 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
4567 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA)
4568 ap->ops->bmdma_start(qc); /* initiate bmdma */
4569 spin_unlock_irqrestore(&ap->host_set->lock, flags);
4570 } else {
4571 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
1da177e4 4572
c1389503 4573 /* PIO commands are handled by polling */
14be71f4 4574 ap->hsm_task_state = HSM_ST;
95064379 4575 ata_queue_pio_task(ap);
1da177e4
LT
4576 }
4577
4578 return;
4579
4580err_out:
a22e2eb0 4581 ata_poll_qc_complete(qc);
1da177e4
LT
4582}
4583
0baab86b 4584
9b847548
JA
4585/*
4586 * Execute a 'simple' command, that only consists of the opcode 'cmd' itself,
4587 * without filling any other registers
4588 */
4589static int ata_do_simple_cmd(struct ata_port *ap, struct ata_device *dev,
4590 u8 cmd)
4591{
4592 struct ata_taskfile tf;
4593 int err;
4594
4595 ata_tf_init(ap, &tf, dev->devno);
4596
4597 tf.command = cmd;
4598 tf.flags |= ATA_TFLAG_DEVICE;
4599 tf.protocol = ATA_PROT_NODATA;
4600
4601 err = ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0);
4602 if (err)
4603 printk(KERN_ERR "%s: ata command failed: %d\n",
4604 __FUNCTION__, err);
4605
4606 return err;
4607}
4608
4609static int ata_flush_cache(struct ata_port *ap, struct ata_device *dev)
4610{
4611 u8 cmd;
4612
4613 if (!ata_try_flush_cache(dev))
4614 return 0;
4615
4616 if (ata_id_has_flush_ext(dev->id))
4617 cmd = ATA_CMD_FLUSH_EXT;
4618 else
4619 cmd = ATA_CMD_FLUSH;
4620
4621 return ata_do_simple_cmd(ap, dev, cmd);
4622}
4623
4624static int ata_standby_drive(struct ata_port *ap, struct ata_device *dev)
4625{
4626 return ata_do_simple_cmd(ap, dev, ATA_CMD_STANDBYNOW1);
4627}
4628
4629static int ata_start_drive(struct ata_port *ap, struct ata_device *dev)
4630{
4631 return ata_do_simple_cmd(ap, dev, ATA_CMD_IDLEIMMEDIATE);
4632}
4633
4634/**
4635 * ata_device_resume - wakeup a previously suspended devices
c893a3ae
RD
4636 * @ap: port the device is connected to
4637 * @dev: the device to resume
9b847548
JA
4638 *
4639 * Kick the drive back into action, by sending it an idle immediate
4640 * command and making sure its transfer mode matches between drive
4641 * and host.
4642 *
4643 */
4644int ata_device_resume(struct ata_port *ap, struct ata_device *dev)
4645{
4646 if (ap->flags & ATA_FLAG_SUSPENDED) {
4647 ap->flags &= ~ATA_FLAG_SUSPENDED;
4648 ata_set_mode(ap);
4649 }
4650 if (!ata_dev_present(dev))
4651 return 0;
4652 if (dev->class == ATA_DEV_ATA)
4653 ata_start_drive(ap, dev);
4654
4655 return 0;
4656}
4657
4658/**
4659 * ata_device_suspend - prepare a device for suspend
c893a3ae
RD
4660 * @ap: port the device is connected to
4661 * @dev: the device to suspend
9b847548
JA
4662 *
4663 * Flush the cache on the drive, if appropriate, then issue a
4664 * standbynow command.
9b847548
JA
4665 */
4666int ata_device_suspend(struct ata_port *ap, struct ata_device *dev)
4667{
4668 if (!ata_dev_present(dev))
4669 return 0;
4670 if (dev->class == ATA_DEV_ATA)
4671 ata_flush_cache(ap, dev);
4672
4673 ata_standby_drive(ap, dev);
4674 ap->flags |= ATA_FLAG_SUSPENDED;
4675 return 0;
4676}
4677
c893a3ae
RD
4678/**
4679 * ata_port_start - Set port up for dma.
4680 * @ap: Port to initialize
4681 *
4682 * Called just after data structures for each port are
4683 * initialized. Allocates space for PRD table.
4684 *
4685 * May be used as the port_start() entry in ata_port_operations.
4686 *
4687 * LOCKING:
4688 * Inherited from caller.
4689 */
4690
1da177e4
LT
4691int ata_port_start (struct ata_port *ap)
4692{
4693 struct device *dev = ap->host_set->dev;
6037d6bb 4694 int rc;
1da177e4
LT
4695
4696 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
4697 if (!ap->prd)
4698 return -ENOMEM;
4699
6037d6bb
JG
4700 rc = ata_pad_alloc(ap, dev);
4701 if (rc) {
cedc9a47 4702 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4703 return rc;
cedc9a47
JG
4704 }
4705
1da177e4
LT
4706 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
4707
4708 return 0;
4709}
4710
0baab86b
EF
4711
4712/**
4713 * ata_port_stop - Undo ata_port_start()
4714 * @ap: Port to shut down
4715 *
4716 * Frees the PRD table.
4717 *
4718 * May be used as the port_stop() entry in ata_port_operations.
4719 *
4720 * LOCKING:
6f0ef4fa 4721 * Inherited from caller.
0baab86b
EF
4722 */
4723
1da177e4
LT
4724void ata_port_stop (struct ata_port *ap)
4725{
4726 struct device *dev = ap->host_set->dev;
4727
4728 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4729 ata_pad_free(ap, dev);
1da177e4
LT
4730}
4731
aa8f0dc6
JG
4732void ata_host_stop (struct ata_host_set *host_set)
4733{
4734 if (host_set->mmio_base)
4735 iounmap(host_set->mmio_base);
4736}
4737
4738
1da177e4
LT
4739/**
4740 * ata_host_remove - Unregister SCSI host structure with upper layers
4741 * @ap: Port to unregister
4742 * @do_unregister: 1 if we fully unregister, 0 to just stop the port
4743 *
4744 * LOCKING:
6f0ef4fa 4745 * Inherited from caller.
1da177e4
LT
4746 */
4747
4748static void ata_host_remove(struct ata_port *ap, unsigned int do_unregister)
4749{
4750 struct Scsi_Host *sh = ap->host;
4751
4752 DPRINTK("ENTER\n");
4753
4754 if (do_unregister)
4755 scsi_remove_host(sh);
4756
4757 ap->ops->port_stop(ap);
4758}
4759
4760/**
4761 * ata_host_init - Initialize an ata_port structure
4762 * @ap: Structure to initialize
4763 * @host: associated SCSI mid-layer structure
4764 * @host_set: Collection of hosts to which @ap belongs
4765 * @ent: Probe information provided by low-level driver
4766 * @port_no: Port number associated with this ata_port
4767 *
0cba632b
JG
4768 * Initialize a new ata_port structure, and its associated
4769 * scsi_host.
4770 *
1da177e4 4771 * LOCKING:
0cba632b 4772 * Inherited from caller.
1da177e4
LT
4773 */
4774
4775static void ata_host_init(struct ata_port *ap, struct Scsi_Host *host,
4776 struct ata_host_set *host_set,
057ace5e 4777 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT
4778{
4779 unsigned int i;
4780
4781 host->max_id = 16;
4782 host->max_lun = 1;
4783 host->max_channel = 1;
4784 host->unique_id = ata_unique_id++;
4785 host->max_cmd_len = 12;
12413197 4786
1da177e4
LT
4787 ap->flags = ATA_FLAG_PORT_DISABLED;
4788 ap->id = host->unique_id;
4789 ap->host = host;
4790 ap->ctl = ATA_DEVCTL_OBS;
4791 ap->host_set = host_set;
4792 ap->port_no = port_no;
4793 ap->hard_port_no =
4794 ent->legacy_mode ? ent->hard_port_no : port_no;
4795 ap->pio_mask = ent->pio_mask;
4796 ap->mwdma_mask = ent->mwdma_mask;
4797 ap->udma_mask = ent->udma_mask;
4798 ap->flags |= ent->host_flags;
4799 ap->ops = ent->port_ops;
4800 ap->cbl = ATA_CBL_NONE;
4801 ap->active_tag = ATA_TAG_POISON;
4802 ap->last_ctl = 0xFF;
4803
4804 INIT_WORK(&ap->packet_task, atapi_packet_task, ap);
4805 INIT_WORK(&ap->pio_task, ata_pio_task, ap);
a72ec4ce 4806 INIT_LIST_HEAD(&ap->eh_done_q);
1da177e4
LT
4807
4808 for (i = 0; i < ATA_MAX_DEVICES; i++)
4809 ap->device[i].devno = i;
4810
4811#ifdef ATA_IRQ_TRAP
4812 ap->stats.unhandled_irq = 1;
4813 ap->stats.idle_irq = 1;
4814#endif
4815
4816 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
4817}
4818
4819/**
4820 * ata_host_add - Attach low-level ATA driver to system
4821 * @ent: Information provided by low-level driver
4822 * @host_set: Collections of ports to which we add
4823 * @port_no: Port number associated with this host
4824 *
0cba632b
JG
4825 * Attach low-level ATA driver to system.
4826 *
1da177e4 4827 * LOCKING:
0cba632b 4828 * PCI/etc. bus probe sem.
1da177e4
LT
4829 *
4830 * RETURNS:
0cba632b 4831 * New ata_port on success, for NULL on error.
1da177e4
LT
4832 */
4833
057ace5e 4834static struct ata_port * ata_host_add(const struct ata_probe_ent *ent,
1da177e4
LT
4835 struct ata_host_set *host_set,
4836 unsigned int port_no)
4837{
4838 struct Scsi_Host *host;
4839 struct ata_port *ap;
4840 int rc;
4841
4842 DPRINTK("ENTER\n");
4843 host = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
4844 if (!host)
4845 return NULL;
4846
4847 ap = (struct ata_port *) &host->hostdata[0];
4848
4849 ata_host_init(ap, host, host_set, ent, port_no);
4850
4851 rc = ap->ops->port_start(ap);
4852 if (rc)
4853 goto err_out;
4854
4855 return ap;
4856
4857err_out:
4858 scsi_host_put(host);
4859 return NULL;
4860}
4861
4862/**
0cba632b
JG
4863 * ata_device_add - Register hardware device with ATA and SCSI layers
4864 * @ent: Probe information describing hardware device to be registered
4865 *
4866 * This function processes the information provided in the probe
4867 * information struct @ent, allocates the necessary ATA and SCSI
4868 * host information structures, initializes them, and registers
4869 * everything with requisite kernel subsystems.
4870 *
4871 * This function requests irqs, probes the ATA bus, and probes
4872 * the SCSI bus.
1da177e4
LT
4873 *
4874 * LOCKING:
0cba632b 4875 * PCI/etc. bus probe sem.
1da177e4
LT
4876 *
4877 * RETURNS:
0cba632b 4878 * Number of ports registered. Zero on error (no ports registered).
1da177e4
LT
4879 */
4880
057ace5e 4881int ata_device_add(const struct ata_probe_ent *ent)
1da177e4
LT
4882{
4883 unsigned int count = 0, i;
4884 struct device *dev = ent->dev;
4885 struct ata_host_set *host_set;
4886
4887 DPRINTK("ENTER\n");
4888 /* alloc a container for our list of ATA ports (buses) */
57f3bda8 4889 host_set = kzalloc(sizeof(struct ata_host_set) +
1da177e4
LT
4890 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
4891 if (!host_set)
4892 return 0;
1da177e4
LT
4893 spin_lock_init(&host_set->lock);
4894
4895 host_set->dev = dev;
4896 host_set->n_ports = ent->n_ports;
4897 host_set->irq = ent->irq;
4898 host_set->mmio_base = ent->mmio_base;
4899 host_set->private_data = ent->private_data;
4900 host_set->ops = ent->port_ops;
4901
4902 /* register each port bound to this device */
4903 for (i = 0; i < ent->n_ports; i++) {
4904 struct ata_port *ap;
4905 unsigned long xfer_mode_mask;
4906
4907 ap = ata_host_add(ent, host_set, i);
4908 if (!ap)
4909 goto err_out;
4910
4911 host_set->ports[i] = ap;
4912 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
4913 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
4914 (ap->pio_mask << ATA_SHIFT_PIO);
4915
4916 /* print per-port info to dmesg */
4917 printk(KERN_INFO "ata%u: %cATA max %s cmd 0x%lX ctl 0x%lX "
4918 "bmdma 0x%lX irq %lu\n",
4919 ap->id,
4920 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
4921 ata_mode_string(xfer_mode_mask),
4922 ap->ioaddr.cmd_addr,
4923 ap->ioaddr.ctl_addr,
4924 ap->ioaddr.bmdma_addr,
4925 ent->irq);
4926
4927 ata_chk_status(ap);
4928 host_set->ops->irq_clear(ap);
4929 count++;
4930 }
4931
57f3bda8
RD
4932 if (!count)
4933 goto err_free_ret;
1da177e4
LT
4934
4935 /* obtain irq, that is shared between channels */
4936 if (request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
4937 DRV_NAME, host_set))
4938 goto err_out;
4939
4940 /* perform each probe synchronously */
4941 DPRINTK("probe begin\n");
4942 for (i = 0; i < count; i++) {
4943 struct ata_port *ap;
4944 int rc;
4945
4946 ap = host_set->ports[i];
4947
c893a3ae 4948 DPRINTK("ata%u: bus probe begin\n", ap->id);
1da177e4 4949 rc = ata_bus_probe(ap);
c893a3ae 4950 DPRINTK("ata%u: bus probe end\n", ap->id);
1da177e4
LT
4951
4952 if (rc) {
4953 /* FIXME: do something useful here?
4954 * Current libata behavior will
4955 * tear down everything when
4956 * the module is removed
4957 * or the h/w is unplugged.
4958 */
4959 }
4960
4961 rc = scsi_add_host(ap->host, dev);
4962 if (rc) {
4963 printk(KERN_ERR "ata%u: scsi_add_host failed\n",
4964 ap->id);
4965 /* FIXME: do something useful here */
4966 /* FIXME: handle unconditional calls to
4967 * scsi_scan_host and ata_host_remove, below,
4968 * at the very least
4969 */
4970 }
4971 }
4972
4973 /* probes are done, now scan each port's disk(s) */
c893a3ae 4974 DPRINTK("host probe begin\n");
1da177e4
LT
4975 for (i = 0; i < count; i++) {
4976 struct ata_port *ap = host_set->ports[i];
4977
644dd0cc 4978 ata_scsi_scan_host(ap);
1da177e4
LT
4979 }
4980
4981 dev_set_drvdata(dev, host_set);
4982
4983 VPRINTK("EXIT, returning %u\n", ent->n_ports);
4984 return ent->n_ports; /* success */
4985
4986err_out:
4987 for (i = 0; i < count; i++) {
4988 ata_host_remove(host_set->ports[i], 1);
4989 scsi_host_put(host_set->ports[i]->host);
4990 }
57f3bda8 4991err_free_ret:
1da177e4
LT
4992 kfree(host_set);
4993 VPRINTK("EXIT, returning 0\n");
4994 return 0;
4995}
4996
17b14451
AC
4997/**
4998 * ata_host_set_remove - PCI layer callback for device removal
4999 * @host_set: ATA host set that was removed
5000 *
5001 * Unregister all objects associated with this host set. Free those
5002 * objects.
5003 *
5004 * LOCKING:
5005 * Inherited from calling layer (may sleep).
5006 */
5007
17b14451
AC
5008void ata_host_set_remove(struct ata_host_set *host_set)
5009{
5010 struct ata_port *ap;
5011 unsigned int i;
5012
5013 for (i = 0; i < host_set->n_ports; i++) {
5014 ap = host_set->ports[i];
5015 scsi_remove_host(ap->host);
5016 }
5017
5018 free_irq(host_set->irq, host_set);
5019
5020 for (i = 0; i < host_set->n_ports; i++) {
5021 ap = host_set->ports[i];
5022
5023 ata_scsi_release(ap->host);
5024
5025 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
5026 struct ata_ioports *ioaddr = &ap->ioaddr;
5027
5028 if (ioaddr->cmd_addr == 0x1f0)
5029 release_region(0x1f0, 8);
5030 else if (ioaddr->cmd_addr == 0x170)
5031 release_region(0x170, 8);
5032 }
5033
5034 scsi_host_put(ap->host);
5035 }
5036
5037 if (host_set->ops->host_stop)
5038 host_set->ops->host_stop(host_set);
5039
5040 kfree(host_set);
5041}
5042
1da177e4
LT
5043/**
5044 * ata_scsi_release - SCSI layer callback hook for host unload
5045 * @host: libata host to be unloaded
5046 *
5047 * Performs all duties necessary to shut down a libata port...
5048 * Kill port kthread, disable port, and release resources.
5049 *
5050 * LOCKING:
5051 * Inherited from SCSI layer.
5052 *
5053 * RETURNS:
5054 * One.
5055 */
5056
5057int ata_scsi_release(struct Scsi_Host *host)
5058{
5059 struct ata_port *ap = (struct ata_port *) &host->hostdata[0];
5060
5061 DPRINTK("ENTER\n");
5062
5063 ap->ops->port_disable(ap);
5064 ata_host_remove(ap, 0);
5065
5066 DPRINTK("EXIT\n");
5067 return 1;
5068}
5069
5070/**
5071 * ata_std_ports - initialize ioaddr with standard port offsets.
5072 * @ioaddr: IO address structure to be initialized
0baab86b
EF
5073 *
5074 * Utility function which initializes data_addr, error_addr,
5075 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
5076 * device_addr, status_addr, and command_addr to standard offsets
5077 * relative to cmd_addr.
5078 *
5079 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 5080 */
0baab86b 5081
1da177e4
LT
5082void ata_std_ports(struct ata_ioports *ioaddr)
5083{
5084 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
5085 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
5086 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
5087 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
5088 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
5089 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
5090 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
5091 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
5092 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
5093 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
5094}
5095
5096static struct ata_probe_ent *
057ace5e 5097ata_probe_ent_alloc(struct device *dev, const struct ata_port_info *port)
1da177e4
LT
5098{
5099 struct ata_probe_ent *probe_ent;
5100
57f3bda8 5101 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
1da177e4
LT
5102 if (!probe_ent) {
5103 printk(KERN_ERR DRV_NAME "(%s): out of memory\n",
5104 kobject_name(&(dev->kobj)));
5105 return NULL;
5106 }
5107
1da177e4
LT
5108 INIT_LIST_HEAD(&probe_ent->node);
5109 probe_ent->dev = dev;
5110
5111 probe_ent->sht = port->sht;
5112 probe_ent->host_flags = port->host_flags;
5113 probe_ent->pio_mask = port->pio_mask;
5114 probe_ent->mwdma_mask = port->mwdma_mask;
5115 probe_ent->udma_mask = port->udma_mask;
5116 probe_ent->port_ops = port->port_ops;
5117
5118 return probe_ent;
5119}
5120
0baab86b
EF
5121
5122
374b1873
JG
5123#ifdef CONFIG_PCI
5124
5125void ata_pci_host_stop (struct ata_host_set *host_set)
5126{
5127 struct pci_dev *pdev = to_pci_dev(host_set->dev);
5128
5129 pci_iounmap(pdev, host_set->mmio_base);
5130}
5131
0baab86b
EF
5132/**
5133 * ata_pci_init_native_mode - Initialize native-mode driver
5134 * @pdev: pci device to be initialized
5135 * @port: array[2] of pointers to port info structures.
47a86593 5136 * @ports: bitmap of ports present
0baab86b
EF
5137 *
5138 * Utility function which allocates and initializes an
5139 * ata_probe_ent structure for a standard dual-port
5140 * PIO-based IDE controller. The returned ata_probe_ent
5141 * structure can be passed to ata_device_add(). The returned
5142 * ata_probe_ent structure should then be freed with kfree().
47a86593
AC
5143 *
5144 * The caller need only pass the address of the primary port, the
5145 * secondary will be deduced automatically. If the device has non
5146 * standard secondary port mappings this function can be called twice,
5147 * once for each interface.
0baab86b
EF
5148 */
5149
1da177e4 5150struct ata_probe_ent *
47a86593 5151ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports)
1da177e4
LT
5152{
5153 struct ata_probe_ent *probe_ent =
5154 ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]);
47a86593
AC
5155 int p = 0;
5156
1da177e4
LT
5157 if (!probe_ent)
5158 return NULL;
5159
1da177e4
LT
5160 probe_ent->irq = pdev->irq;
5161 probe_ent->irq_flags = SA_SHIRQ;
e99f8b5e 5162 probe_ent->private_data = port[0]->private_data;
1da177e4 5163
47a86593
AC
5164 if (ports & ATA_PORT_PRIMARY) {
5165 probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 0);
5166 probe_ent->port[p].altstatus_addr =
5167 probe_ent->port[p].ctl_addr =
5168 pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS;
5169 probe_ent->port[p].bmdma_addr = pci_resource_start(pdev, 4);
5170 ata_std_ports(&probe_ent->port[p]);
5171 p++;
5172 }
1da177e4 5173
47a86593
AC
5174 if (ports & ATA_PORT_SECONDARY) {
5175 probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 2);
5176 probe_ent->port[p].altstatus_addr =
5177 probe_ent->port[p].ctl_addr =
5178 pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS;
5179 probe_ent->port[p].bmdma_addr = pci_resource_start(pdev, 4) + 8;
5180 ata_std_ports(&probe_ent->port[p]);
5181 p++;
5182 }
1da177e4 5183
47a86593 5184 probe_ent->n_ports = p;
1da177e4
LT
5185 return probe_ent;
5186}
5187
0f0d5192 5188static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, struct ata_port_info *port, int port_num)
1da177e4 5189{
47a86593 5190 struct ata_probe_ent *probe_ent;
1da177e4 5191
0f0d5192 5192 probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port);
1da177e4
LT
5193 if (!probe_ent)
5194 return NULL;
1da177e4 5195
1da177e4 5196 probe_ent->legacy_mode = 1;
47a86593
AC
5197 probe_ent->n_ports = 1;
5198 probe_ent->hard_port_no = port_num;
e99f8b5e 5199 probe_ent->private_data = port->private_data;
47a86593
AC
5200
5201 switch(port_num)
5202 {
5203 case 0:
5204 probe_ent->irq = 14;
5205 probe_ent->port[0].cmd_addr = 0x1f0;
5206 probe_ent->port[0].altstatus_addr =
5207 probe_ent->port[0].ctl_addr = 0x3f6;
5208 break;
5209 case 1:
5210 probe_ent->irq = 15;
5211 probe_ent->port[0].cmd_addr = 0x170;
5212 probe_ent->port[0].altstatus_addr =
5213 probe_ent->port[0].ctl_addr = 0x376;
5214 break;
5215 }
5216 probe_ent->port[0].bmdma_addr = pci_resource_start(pdev, 4) + 8 * port_num;
1da177e4 5217 ata_std_ports(&probe_ent->port[0]);
1da177e4
LT
5218 return probe_ent;
5219}
5220
5221/**
5222 * ata_pci_init_one - Initialize/register PCI IDE host controller
5223 * @pdev: Controller to be initialized
5224 * @port_info: Information from low-level host driver
5225 * @n_ports: Number of ports attached to host controller
5226 *
0baab86b
EF
5227 * This is a helper function which can be called from a driver's
5228 * xxx_init_one() probe function if the hardware uses traditional
5229 * IDE taskfile registers.
5230 *
5231 * This function calls pci_enable_device(), reserves its register
5232 * regions, sets the dma mask, enables bus master mode, and calls
5233 * ata_device_add()
5234 *
1da177e4
LT
5235 * LOCKING:
5236 * Inherited from PCI layer (may sleep).
5237 *
5238 * RETURNS:
0cba632b 5239 * Zero on success, negative on errno-based value on error.
1da177e4
LT
5240 */
5241
5242int ata_pci_init_one (struct pci_dev *pdev, struct ata_port_info **port_info,
5243 unsigned int n_ports)
5244{
47a86593 5245 struct ata_probe_ent *probe_ent = NULL, *probe_ent2 = NULL;
1da177e4
LT
5246 struct ata_port_info *port[2];
5247 u8 tmp8, mask;
5248 unsigned int legacy_mode = 0;
5249 int disable_dev_on_err = 1;
5250 int rc;
5251
5252 DPRINTK("ENTER\n");
5253
5254 port[0] = port_info[0];
5255 if (n_ports > 1)
5256 port[1] = port_info[1];
5257 else
5258 port[1] = port[0];
5259
5260 if ((port[0]->host_flags & ATA_FLAG_NO_LEGACY) == 0
5261 && (pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
47a86593 5262 /* TODO: What if one channel is in native mode ... */
1da177e4
LT
5263 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
5264 mask = (1 << 2) | (1 << 0);
5265 if ((tmp8 & mask) != mask)
5266 legacy_mode = (1 << 3);
5267 }
5268
5269 /* FIXME... */
47a86593
AC
5270 if ((!legacy_mode) && (n_ports > 2)) {
5271 printk(KERN_ERR "ata: BUG: native mode, n_ports > 2\n");
5272 n_ports = 2;
5273 /* For now */
1da177e4
LT
5274 }
5275
47a86593
AC
5276 /* FIXME: Really for ATA it isn't safe because the device may be
5277 multi-purpose and we want to leave it alone if it was already
5278 enabled. Secondly for shared use as Arjan says we want refcounting
5279
5280 Checking dev->is_enabled is insufficient as this is not set at
5281 boot for the primary video which is BIOS enabled
5282 */
5283
1da177e4
LT
5284 rc = pci_enable_device(pdev);
5285 if (rc)
5286 return rc;
5287
5288 rc = pci_request_regions(pdev, DRV_NAME);
5289 if (rc) {
5290 disable_dev_on_err = 0;
5291 goto err_out;
5292 }
5293
47a86593 5294 /* FIXME: Should use platform specific mappers for legacy port ranges */
1da177e4
LT
5295 if (legacy_mode) {
5296 if (!request_region(0x1f0, 8, "libata")) {
5297 struct resource *conflict, res;
5298 res.start = 0x1f0;
5299 res.end = 0x1f0 + 8 - 1;
5300 conflict = ____request_resource(&ioport_resource, &res);
5301 if (!strcmp(conflict->name, "libata"))
5302 legacy_mode |= (1 << 0);
5303 else {
5304 disable_dev_on_err = 0;
5305 printk(KERN_WARNING "ata: 0x1f0 IDE port busy\n");
5306 }
5307 } else
5308 legacy_mode |= (1 << 0);
5309
5310 if (!request_region(0x170, 8, "libata")) {
5311 struct resource *conflict, res;
5312 res.start = 0x170;
5313 res.end = 0x170 + 8 - 1;
5314 conflict = ____request_resource(&ioport_resource, &res);
5315 if (!strcmp(conflict->name, "libata"))
5316 legacy_mode |= (1 << 1);
5317 else {
5318 disable_dev_on_err = 0;
5319 printk(KERN_WARNING "ata: 0x170 IDE port busy\n");
5320 }
5321 } else
5322 legacy_mode |= (1 << 1);
5323 }
5324
5325 /* we have legacy mode, but all ports are unavailable */
5326 if (legacy_mode == (1 << 3)) {
5327 rc = -EBUSY;
5328 goto err_out_regions;
5329 }
5330
5331 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
5332 if (rc)
5333 goto err_out_regions;
5334 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
5335 if (rc)
5336 goto err_out_regions;
5337
5338 if (legacy_mode) {
47a86593 5339 if (legacy_mode & (1 << 0))
0f0d5192 5340 probe_ent = ata_pci_init_legacy_port(pdev, port[0], 0);
47a86593 5341 if (legacy_mode & (1 << 1))
0f0d5192 5342 probe_ent2 = ata_pci_init_legacy_port(pdev, port[1], 1);
47a86593
AC
5343 } else {
5344 if (n_ports == 2)
5345 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
5346 else
5347 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY);
5348 }
5349 if (!probe_ent && !probe_ent2) {
1da177e4
LT
5350 rc = -ENOMEM;
5351 goto err_out_regions;
5352 }
5353
5354 pci_set_master(pdev);
5355
5356 /* FIXME: check ata_device_add return */
5357 if (legacy_mode) {
5358 if (legacy_mode & (1 << 0))
5359 ata_device_add(probe_ent);
5360 if (legacy_mode & (1 << 1))
5361 ata_device_add(probe_ent2);
5362 } else
5363 ata_device_add(probe_ent);
5364
5365 kfree(probe_ent);
5366 kfree(probe_ent2);
5367
5368 return 0;
5369
5370err_out_regions:
5371 if (legacy_mode & (1 << 0))
5372 release_region(0x1f0, 8);
5373 if (legacy_mode & (1 << 1))
5374 release_region(0x170, 8);
5375 pci_release_regions(pdev);
5376err_out:
5377 if (disable_dev_on_err)
5378 pci_disable_device(pdev);
5379 return rc;
5380}
5381
5382/**
5383 * ata_pci_remove_one - PCI layer callback for device removal
5384 * @pdev: PCI device that was removed
5385 *
5386 * PCI layer indicates to libata via this hook that
6f0ef4fa 5387 * hot-unplug or module unload event has occurred.
1da177e4
LT
5388 * Handle this by unregistering all objects associated
5389 * with this PCI device. Free those objects. Then finally
5390 * release PCI resources and disable device.
5391 *
5392 * LOCKING:
5393 * Inherited from PCI layer (may sleep).
5394 */
5395
5396void ata_pci_remove_one (struct pci_dev *pdev)
5397{
5398 struct device *dev = pci_dev_to_dev(pdev);
5399 struct ata_host_set *host_set = dev_get_drvdata(dev);
1da177e4 5400
17b14451 5401 ata_host_set_remove(host_set);
1da177e4
LT
5402 pci_release_regions(pdev);
5403 pci_disable_device(pdev);
5404 dev_set_drvdata(dev, NULL);
5405}
5406
5407/* move to PCI subsystem */
057ace5e 5408int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT
5409{
5410 unsigned long tmp = 0;
5411
5412 switch (bits->width) {
5413 case 1: {
5414 u8 tmp8 = 0;
5415 pci_read_config_byte(pdev, bits->reg, &tmp8);
5416 tmp = tmp8;
5417 break;
5418 }
5419 case 2: {
5420 u16 tmp16 = 0;
5421 pci_read_config_word(pdev, bits->reg, &tmp16);
5422 tmp = tmp16;
5423 break;
5424 }
5425 case 4: {
5426 u32 tmp32 = 0;
5427 pci_read_config_dword(pdev, bits->reg, &tmp32);
5428 tmp = tmp32;
5429 break;
5430 }
5431
5432 default:
5433 return -EINVAL;
5434 }
5435
5436 tmp &= bits->mask;
5437
5438 return (tmp == bits->val) ? 1 : 0;
5439}
9b847548
JA
5440
5441int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t state)
5442{
5443 pci_save_state(pdev);
5444 pci_disable_device(pdev);
5445 pci_set_power_state(pdev, PCI_D3hot);
5446 return 0;
5447}
5448
5449int ata_pci_device_resume(struct pci_dev *pdev)
5450{
5451 pci_set_power_state(pdev, PCI_D0);
5452 pci_restore_state(pdev);
5453 pci_enable_device(pdev);
5454 pci_set_master(pdev);
5455 return 0;
5456}
1da177e4
LT
5457#endif /* CONFIG_PCI */
5458
5459
1da177e4
LT
5460static int __init ata_init(void)
5461{
5462 ata_wq = create_workqueue("ata");
5463 if (!ata_wq)
5464 return -ENOMEM;
5465
5466 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
5467 return 0;
5468}
5469
5470static void __exit ata_exit(void)
5471{
5472 destroy_workqueue(ata_wq);
5473}
5474
5475module_init(ata_init);
5476module_exit(ata_exit);
5477
67846b30
JG
5478static unsigned long ratelimit_time;
5479static spinlock_t ata_ratelimit_lock = SPIN_LOCK_UNLOCKED;
5480
5481int ata_ratelimit(void)
5482{
5483 int rc;
5484 unsigned long flags;
5485
5486 spin_lock_irqsave(&ata_ratelimit_lock, flags);
5487
5488 if (time_after(jiffies, ratelimit_time)) {
5489 rc = 1;
5490 ratelimit_time = jiffies + (HZ/5);
5491 } else
5492 rc = 0;
5493
5494 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
5495
5496 return rc;
5497}
5498
1da177e4
LT
5499/*
5500 * libata is essentially a library of internal helper functions for
5501 * low-level ATA host controller drivers. As such, the API/ABI is
5502 * likely to change as new drivers are added and updated.
5503 * Do not depend on ABI/API stability.
5504 */
5505
5506EXPORT_SYMBOL_GPL(ata_std_bios_param);
5507EXPORT_SYMBOL_GPL(ata_std_ports);
5508EXPORT_SYMBOL_GPL(ata_device_add);
17b14451 5509EXPORT_SYMBOL_GPL(ata_host_set_remove);
1da177e4
LT
5510EXPORT_SYMBOL_GPL(ata_sg_init);
5511EXPORT_SYMBOL_GPL(ata_sg_init_one);
5512EXPORT_SYMBOL_GPL(ata_qc_complete);
5513EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
5514EXPORT_SYMBOL_GPL(ata_eng_timeout);
5515EXPORT_SYMBOL_GPL(ata_tf_load);
5516EXPORT_SYMBOL_GPL(ata_tf_read);
5517EXPORT_SYMBOL_GPL(ata_noop_dev_select);
5518EXPORT_SYMBOL_GPL(ata_std_dev_select);
5519EXPORT_SYMBOL_GPL(ata_tf_to_fis);
5520EXPORT_SYMBOL_GPL(ata_tf_from_fis);
5521EXPORT_SYMBOL_GPL(ata_check_status);
5522EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT
5523EXPORT_SYMBOL_GPL(ata_exec_command);
5524EXPORT_SYMBOL_GPL(ata_port_start);
5525EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 5526EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4
LT
5527EXPORT_SYMBOL_GPL(ata_interrupt);
5528EXPORT_SYMBOL_GPL(ata_qc_prep);
5529EXPORT_SYMBOL_GPL(ata_bmdma_setup);
5530EXPORT_SYMBOL_GPL(ata_bmdma_start);
5531EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
5532EXPORT_SYMBOL_GPL(ata_bmdma_status);
5533EXPORT_SYMBOL_GPL(ata_bmdma_stop);
5534EXPORT_SYMBOL_GPL(ata_port_probe);
5535EXPORT_SYMBOL_GPL(sata_phy_reset);
5536EXPORT_SYMBOL_GPL(__sata_phy_reset);
5537EXPORT_SYMBOL_GPL(ata_bus_reset);
c2bd5804
TH
5538EXPORT_SYMBOL_GPL(ata_std_softreset);
5539EXPORT_SYMBOL_GPL(sata_std_hardreset);
5540EXPORT_SYMBOL_GPL(ata_std_postreset);
5541EXPORT_SYMBOL_GPL(ata_std_probe_reset);
a62c0fc5 5542EXPORT_SYMBOL_GPL(ata_drive_probe_reset);
1da177e4 5543EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 5544EXPORT_SYMBOL_GPL(ata_ratelimit);
6f8b9958 5545EXPORT_SYMBOL_GPL(ata_busy_sleep);
1da177e4
LT
5546EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
5547EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
5548EXPORT_SYMBOL_GPL(ata_scsi_error);
5549EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
5550EXPORT_SYMBOL_GPL(ata_scsi_release);
5551EXPORT_SYMBOL_GPL(ata_host_intr);
5552EXPORT_SYMBOL_GPL(ata_dev_classify);
5553EXPORT_SYMBOL_GPL(ata_dev_id_string);
6f2f3812 5554EXPORT_SYMBOL_GPL(ata_dev_config);
1da177e4 5555EXPORT_SYMBOL_GPL(ata_scsi_simulate);
a72ec4ce
TH
5556EXPORT_SYMBOL_GPL(ata_eh_qc_complete);
5557EXPORT_SYMBOL_GPL(ata_eh_qc_retry);
1da177e4 5558
1bc4ccff 5559EXPORT_SYMBOL_GPL(ata_pio_need_iordy);
452503f9
AC
5560EXPORT_SYMBOL_GPL(ata_timing_compute);
5561EXPORT_SYMBOL_GPL(ata_timing_merge);
5562
1da177e4
LT
5563#ifdef CONFIG_PCI
5564EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 5565EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT
5566EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
5567EXPORT_SYMBOL_GPL(ata_pci_init_one);
5568EXPORT_SYMBOL_GPL(ata_pci_remove_one);
9b847548
JA
5569EXPORT_SYMBOL_GPL(ata_pci_device_suspend);
5570EXPORT_SYMBOL_GPL(ata_pci_device_resume);
1da177e4 5571#endif /* CONFIG_PCI */
9b847548
JA
5572
5573EXPORT_SYMBOL_GPL(ata_device_suspend);
5574EXPORT_SYMBOL_GPL(ata_device_resume);
5575EXPORT_SYMBOL_GPL(ata_scsi_device_suspend);
5576EXPORT_SYMBOL_GPL(ata_scsi_device_resume);
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