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[deliverable/linux.git] / drivers / scsi / libata-core.c
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1da177e4 1/*
af36d7f0
JG		 2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT		 33 */
34
35#include <linux/config.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/list.h>
41#include <linux/mm.h>
42#include <linux/highmem.h>
43#include <linux/spinlock.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/timer.h>
47#include <linux/interrupt.h>
48#include <linux/completion.h>
49#include <linux/suspend.h>
50#include <linux/workqueue.h>
67846b30 51#include <linux/jiffies.h>
378f058c 52#include <linux/scatterlist.h>
1da177e4
LT		 53#include <scsi/scsi.h>
54#include "scsi.h"
55#include "scsi_priv.h"
56#include <scsi/scsi_host.h>
57#include <linux/libata.h>
58#include <asm/io.h>
59#include <asm/semaphore.h>
60#include <asm/byteorder.h>
61
62#include "libata.h"
63
64static unsigned int ata_busy_sleep (struct ata_port *ap,
65 unsigned long tmout_pat,
66 unsigned long tmout);
59a10b17 67static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev);
8bf62ece 68static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev);
1da177e4
LT		 69static void ata_set_mode(struct ata_port *ap);
70static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev);
057ace5e 71static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift);
1da177e4 72static int fgb(u32 bitmap);
057ace5e 73static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 74 u8 *xfer_mode_out,
75 unsigned int *xfer_shift_out);
1da177e4
LT		 76static void __ata_qc_complete(struct ata_queued_cmd *qc);
77
78static unsigned int ata_unique_id = 1;
79static struct workqueue_struct *ata_wq;
80
1623c81e
JG		 81int atapi_enabled = 0;
82module_param(atapi_enabled, int, 0444);
83MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
84
1da177e4
LT		 85MODULE_AUTHOR("Jeff Garzik");
86MODULE_DESCRIPTION("Library module for ATA devices");
87MODULE_LICENSE("GPL");
88MODULE_VERSION(DRV_VERSION);
89
90/**
6f0ef4fa 91 * ata_tf_load_pio - send taskfile registers to host controller
1da177e4
LT		 92 * @ap: Port to which output is sent
93 * @tf: ATA taskfile register set
94 *
95 * Outputs ATA taskfile to standard ATA host controller.
96 *
97 * LOCKING:
98 * Inherited from caller.
99 */
100
057ace5e 101static void ata_tf_load_pio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 102{
103 struct ata_ioports *ioaddr = &ap->ioaddr;
104 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
105
106 if (tf->ctl != ap->last_ctl) {
107 outb(tf->ctl, ioaddr->ctl_addr);
108 ap->last_ctl = tf->ctl;
109 ata_wait_idle(ap);
110 }
111
112 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
113 outb(tf->hob_feature, ioaddr->feature_addr);
114 outb(tf->hob_nsect, ioaddr->nsect_addr);
115 outb(tf->hob_lbal, ioaddr->lbal_addr);
116 outb(tf->hob_lbam, ioaddr->lbam_addr);
117 outb(tf->hob_lbah, ioaddr->lbah_addr);
118 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
119 tf->hob_feature,
120 tf->hob_nsect,
121 tf->hob_lbal,
122 tf->hob_lbam,
123 tf->hob_lbah);
124 }
125
126 if (is_addr) {
127 outb(tf->feature, ioaddr->feature_addr);
128 outb(tf->nsect, ioaddr->nsect_addr);
129 outb(tf->lbal, ioaddr->lbal_addr);
130 outb(tf->lbam, ioaddr->lbam_addr);
131 outb(tf->lbah, ioaddr->lbah_addr);
132 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
133 tf->feature,
134 tf->nsect,
135 tf->lbal,
136 tf->lbam,
137 tf->lbah);
138 }
139
140 if (tf->flags & ATA_TFLAG_DEVICE) {
141 outb(tf->device, ioaddr->device_addr);
142 VPRINTK("device 0x%X\n", tf->device);
143 }
144
145 ata_wait_idle(ap);
146}
147
148/**
149 * ata_tf_load_mmio - send taskfile registers to host controller
150 * @ap: Port to which output is sent
151 * @tf: ATA taskfile register set
152 *
153 * Outputs ATA taskfile to standard ATA host controller using MMIO.
154 *
155 * LOCKING:
156 * Inherited from caller.
157 */
158
057ace5e 159static void ata_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 160{
161 struct ata_ioports *ioaddr = &ap->ioaddr;
162 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
163
164 if (tf->ctl != ap->last_ctl) {
165 writeb(tf->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
166 ap->last_ctl = tf->ctl;
167 ata_wait_idle(ap);
168 }
169
170 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
171 writeb(tf->hob_feature, (void __iomem *) ioaddr->feature_addr);
172 writeb(tf->hob_nsect, (void __iomem *) ioaddr->nsect_addr);
173 writeb(tf->hob_lbal, (void __iomem *) ioaddr->lbal_addr);
174 writeb(tf->hob_lbam, (void __iomem *) ioaddr->lbam_addr);
175 writeb(tf->hob_lbah, (void __iomem *) ioaddr->lbah_addr);
176 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
177 tf->hob_feature,
178 tf->hob_nsect,
179 tf->hob_lbal,
180 tf->hob_lbam,
181 tf->hob_lbah);
182 }
183
184 if (is_addr) {
185 writeb(tf->feature, (void __iomem *) ioaddr->feature_addr);
186 writeb(tf->nsect, (void __iomem *) ioaddr->nsect_addr);
187 writeb(tf->lbal, (void __iomem *) ioaddr->lbal_addr);
188 writeb(tf->lbam, (void __iomem *) ioaddr->lbam_addr);
189 writeb(tf->lbah, (void __iomem *) ioaddr->lbah_addr);
190 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
191 tf->feature,
192 tf->nsect,
193 tf->lbal,
194 tf->lbam,
195 tf->lbah);
196 }
197
198 if (tf->flags & ATA_TFLAG_DEVICE) {
199 writeb(tf->device, (void __iomem *) ioaddr->device_addr);
200 VPRINTK("device 0x%X\n", tf->device);
201 }
202
203 ata_wait_idle(ap);
204}
205
0baab86b
EF		 206
207/**
208 * ata_tf_load - send taskfile registers to host controller
209 * @ap: Port to which output is sent
210 * @tf: ATA taskfile register set
211 *
212 * Outputs ATA taskfile to standard ATA host controller using MMIO
213 * or PIO as indicated by the ATA_FLAG_MMIO flag.
214 * Writes the control, feature, nsect, lbal, lbam, and lbah registers.
215 * Optionally (ATA_TFLAG_LBA48) writes hob_feature, hob_nsect,
216 * hob_lbal, hob_lbam, and hob_lbah.
217 *
218 * This function waits for idle (!BUSY and !DRQ) after writing
219 * registers. If the control register has a new value, this
220 * function also waits for idle after writing control and before
221 * writing the remaining registers.
222 *
223 * May be used as the tf_load() entry in ata_port_operations.
224 *
225 * LOCKING:
226 * Inherited from caller.
227 */
057ace5e 228void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 229{
230 if (ap->flags & ATA_FLAG_MMIO)
231 ata_tf_load_mmio(ap, tf);
232 else
233 ata_tf_load_pio(ap, tf);
234}
235
236/**
0baab86b 237 * ata_exec_command_pio - issue ATA command to host controller
1da177e4
LT		 238 * @ap: port to which command is being issued
239 * @tf: ATA taskfile register set
240 *
0baab86b 241 * Issues PIO write to ATA command register, with proper
1da177e4
LT		 242 * synchronization with interrupt handler / other threads.
243 *
244 * LOCKING:
245 * spin_lock_irqsave(host_set lock)
246 */
247
057ace5e 248static void ata_exec_command_pio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 249{
250 DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command);
251
252 outb(tf->command, ap->ioaddr.command_addr);
253 ata_pause(ap);
254}
255
256
257/**
258 * ata_exec_command_mmio - issue ATA command to host controller
259 * @ap: port to which command is being issued
260 * @tf: ATA taskfile register set
261 *
262 * Issues MMIO write to ATA command register, with proper
263 * synchronization with interrupt handler / other threads.
264 *
265 * LOCKING:
266 * spin_lock_irqsave(host_set lock)
267 */
268
057ace5e 269static void ata_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 270{
271 DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command);
272
273 writeb(tf->command, (void __iomem *) ap->ioaddr.command_addr);
274 ata_pause(ap);
275}
276
0baab86b
EF		 277
278/**
279 * ata_exec_command - issue ATA command to host controller
280 * @ap: port to which command is being issued
281 * @tf: ATA taskfile register set
282 *
283 * Issues PIO/MMIO write to ATA command register, with proper
284 * synchronization with interrupt handler / other threads.
285 *
286 * LOCKING:
287 * spin_lock_irqsave(host_set lock)
288 */
057ace5e 289void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 290{
291 if (ap->flags & ATA_FLAG_MMIO)
292 ata_exec_command_mmio(ap, tf);
293 else
294 ata_exec_command_pio(ap, tf);
295}
296
1da177e4
LT		 297/**
298 * ata_tf_to_host - issue ATA taskfile to host controller
299 * @ap: port to which command is being issued
300 * @tf: ATA taskfile register set
301 *
302 * Issues ATA taskfile register set to ATA host controller,
303 * with proper synchronization with interrupt handler and
304 * other threads.
305 *
306 * LOCKING:
1da177e4
LT		 307 * spin_lock_irqsave(host_set lock)
308 */
309
e5338254
JG		 310static inline void ata_tf_to_host(struct ata_port *ap,
311 const struct ata_taskfile *tf)
1da177e4
LT		 312{
313 ap->ops->tf_load(ap, tf);
314 ap->ops->exec_command(ap, tf);
315}
316
317/**
0baab86b 318 * ata_tf_read_pio - input device's ATA taskfile shadow registers
1da177e4
LT		 319 * @ap: Port from which input is read
320 * @tf: ATA taskfile register set for storing input
321 *
322 * Reads ATA taskfile registers for currently-selected device
323 * into @tf.
324 *
325 * LOCKING:
326 * Inherited from caller.
327 */
328
329static void ata_tf_read_pio(struct ata_port *ap, struct ata_taskfile *tf)
330{
331 struct ata_ioports *ioaddr = &ap->ioaddr;
332
ac19bff2 333 tf->command = ata_check_status(ap);
0169e284 334 tf->feature = inb(ioaddr->error_addr);
1da177e4
LT		 335 tf->nsect = inb(ioaddr->nsect_addr);
336 tf->lbal = inb(ioaddr->lbal_addr);
337 tf->lbam = inb(ioaddr->lbam_addr);
338 tf->lbah = inb(ioaddr->lbah_addr);
339 tf->device = inb(ioaddr->device_addr);
340
341 if (tf->flags & ATA_TFLAG_LBA48) {
342 outb(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
343 tf->hob_feature = inb(ioaddr->error_addr);
344 tf->hob_nsect = inb(ioaddr->nsect_addr);
345 tf->hob_lbal = inb(ioaddr->lbal_addr);
346 tf->hob_lbam = inb(ioaddr->lbam_addr);
347 tf->hob_lbah = inb(ioaddr->lbah_addr);
348 }
349}
350
351/**
352 * ata_tf_read_mmio - input device's ATA taskfile shadow registers
353 * @ap: Port from which input is read
354 * @tf: ATA taskfile register set for storing input
355 *
356 * Reads ATA taskfile registers for currently-selected device
357 * into @tf via MMIO.
358 *
359 * LOCKING:
360 * Inherited from caller.
361 */
362
363static void ata_tf_read_mmio(struct ata_port *ap, struct ata_taskfile *tf)
364{
365 struct ata_ioports *ioaddr = &ap->ioaddr;
366
ac19bff2 367 tf->command = ata_check_status(ap);
0169e284 368 tf->feature = readb((void __iomem *)ioaddr->error_addr);
1da177e4
LT		 369 tf->nsect = readb((void __iomem *)ioaddr->nsect_addr);
370 tf->lbal = readb((void __iomem *)ioaddr->lbal_addr);
371 tf->lbam = readb((void __iomem *)ioaddr->lbam_addr);
372 tf->lbah = readb((void __iomem *)ioaddr->lbah_addr);
373 tf->device = readb((void __iomem *)ioaddr->device_addr);
374
375 if (tf->flags & ATA_TFLAG_LBA48) {
376 writeb(tf->ctl | ATA_HOB, (void __iomem *) ap->ioaddr.ctl_addr);
377 tf->hob_feature = readb((void __iomem *)ioaddr->error_addr);
378 tf->hob_nsect = readb((void __iomem *)ioaddr->nsect_addr);
379 tf->hob_lbal = readb((void __iomem *)ioaddr->lbal_addr);
380 tf->hob_lbam = readb((void __iomem *)ioaddr->lbam_addr);
381 tf->hob_lbah = readb((void __iomem *)ioaddr->lbah_addr);
382 }
383}
384
0baab86b
EF		 385
386/**
387 * ata_tf_read - input device's ATA taskfile shadow registers
388 * @ap: Port from which input is read
389 * @tf: ATA taskfile register set for storing input
390 *
391 * Reads ATA taskfile registers for currently-selected device
392 * into @tf.
393 *
394 * Reads nsect, lbal, lbam, lbah, and device. If ATA_TFLAG_LBA48
395 * is set, also reads the hob registers.
396 *
397 * May be used as the tf_read() entry in ata_port_operations.
398 *
399 * LOCKING:
400 * Inherited from caller.
401 */
1da177e4
LT		 402void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
403{
404 if (ap->flags & ATA_FLAG_MMIO)
405 ata_tf_read_mmio(ap, tf);
406 else
407 ata_tf_read_pio(ap, tf);
408}
409
410/**
411 * ata_check_status_pio - Read device status reg & clear interrupt
412 * @ap: port where the device is
413 *
414 * Reads ATA taskfile status register for currently-selected device
0baab86b 415 * and return its value. This also clears pending interrupts
1da177e4
LT		 416 * from this device
417 *
418 * LOCKING:
419 * Inherited from caller.
420 */
421static u8 ata_check_status_pio(struct ata_port *ap)
422{
423 return inb(ap->ioaddr.status_addr);
424}
425
426/**
427 * ata_check_status_mmio - Read device status reg & clear interrupt
428 * @ap: port where the device is
429 *
430 * Reads ATA taskfile status register for currently-selected device
0baab86b 431 * via MMIO and return its value. This also clears pending interrupts
1da177e4
LT		 432 * from this device
433 *
434 * LOCKING:
435 * Inherited from caller.
436 */
437static u8 ata_check_status_mmio(struct ata_port *ap)
438{
439 return readb((void __iomem *) ap->ioaddr.status_addr);
440}
441
0baab86b
EF		 442
443/**
444 * ata_check_status - Read device status reg & clear interrupt
445 * @ap: port where the device is
446 *
447 * Reads ATA taskfile status register for currently-selected device
448 * and return its value. This also clears pending interrupts
449 * from this device
450 *
451 * May be used as the check_status() entry in ata_port_operations.
452 *
453 * LOCKING:
454 * Inherited from caller.
455 */
1da177e4
LT		 456u8 ata_check_status(struct ata_port *ap)
457{
458 if (ap->flags & ATA_FLAG_MMIO)
459 return ata_check_status_mmio(ap);
460 return ata_check_status_pio(ap);
461}
462
0baab86b
EF		 463
464/**
465 * ata_altstatus - Read device alternate status reg
466 * @ap: port where the device is
467 *
468 * Reads ATA taskfile alternate status register for
469 * currently-selected device and return its value.
470 *
471 * Note: may NOT be used as the check_altstatus() entry in
472 * ata_port_operations.
473 *
474 * LOCKING:
475 * Inherited from caller.
476 */
1da177e4
LT		 477u8 ata_altstatus(struct ata_port *ap)
478{
479 if (ap->ops->check_altstatus)
480 return ap->ops->check_altstatus(ap);
481
482 if (ap->flags & ATA_FLAG_MMIO)
483 return readb((void __iomem *)ap->ioaddr.altstatus_addr);
484 return inb(ap->ioaddr.altstatus_addr);
485}
486
0baab86b 487
1da177e4
LT		 488/**
489 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
490 * @tf: Taskfile to convert
491 * @fis: Buffer into which data will output
492 * @pmp: Port multiplier port
493 *
494 * Converts a standard ATA taskfile to a Serial ATA
495 * FIS structure (Register - Host to Device).
496 *
497 * LOCKING:
498 * Inherited from caller.
499 */
500
057ace5e 501void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT		 502{
503 fis[0] = 0x27; /* Register - Host to Device FIS */
504 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
505 bit 7 indicates Command FIS */
506 fis[2] = tf->command;
507 fis[3] = tf->feature;
508
509 fis[4] = tf->lbal;
510 fis[5] = tf->lbam;
511 fis[6] = tf->lbah;
512 fis[7] = tf->device;
513
514 fis[8] = tf->hob_lbal;
515 fis[9] = tf->hob_lbam;
516 fis[10] = tf->hob_lbah;
517 fis[11] = tf->hob_feature;
518
519 fis[12] = tf->nsect;
520 fis[13] = tf->hob_nsect;
521 fis[14] = 0;
522 fis[15] = tf->ctl;
523
524 fis[16] = 0;
525 fis[17] = 0;
526 fis[18] = 0;
527 fis[19] = 0;
528}
529
530/**
531 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
532 * @fis: Buffer from which data will be input
533 * @tf: Taskfile to output
534 *
535 * Converts a standard ATA taskfile to a Serial ATA
536 * FIS structure (Register - Host to Device).
537 *
538 * LOCKING:
539 * Inherited from caller.
540 */
541
057ace5e 542void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT		 543{
544 tf->command = fis[2]; /* status */
545 tf->feature = fis[3]; /* error */
546
547 tf->lbal = fis[4];
548 tf->lbam = fis[5];
549 tf->lbah = fis[6];
550 tf->device = fis[7];
551
552 tf->hob_lbal = fis[8];
553 tf->hob_lbam = fis[9];
554 tf->hob_lbah = fis[10];
555
556 tf->nsect = fis[12];
557 tf->hob_nsect = fis[13];
558}
559
8cbd6df1
AL		 560static const u8 ata_rw_cmds[] = {
561 /* pio multi */
562 ATA_CMD_READ_MULTI,
563 ATA_CMD_WRITE_MULTI,
564 ATA_CMD_READ_MULTI_EXT,
565 ATA_CMD_WRITE_MULTI_EXT,
566 /* pio */
567 ATA_CMD_PIO_READ,
568 ATA_CMD_PIO_WRITE,
569 ATA_CMD_PIO_READ_EXT,
570 ATA_CMD_PIO_WRITE_EXT,
571 /* dma */
572 ATA_CMD_READ,
573 ATA_CMD_WRITE,
574 ATA_CMD_READ_EXT,
575 ATA_CMD_WRITE_EXT
576};
1da177e4
LT		 577
578/**
8cbd6df1
AL		 579 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
580 * @qc: command to examine and configure
1da177e4 581 *
8cbd6df1
AL		 582 * Examine the device configuration and tf->flags to calculate
583 * the proper read/write commands and protocol to use.
1da177e4
LT		 584 *
585 * LOCKING:
586 * caller.
587 */
8cbd6df1 588void ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 589{
8cbd6df1
AL		 590 struct ata_taskfile *tf = &qc->tf;
591 struct ata_device *dev = qc->dev;
1da177e4 592
8cbd6df1
AL		 593 int index, lba48, write;
594
595 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
596 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 597
8cbd6df1
AL		 598 if (dev->flags & ATA_DFLAG_PIO) {
599 tf->protocol = ATA_PROT_PIO;
600 index = dev->multi_count ? 0 : 4;
601 } else {
602 tf->protocol = ATA_PROT_DMA;
603 index = 8;
604 }
1da177e4 605
8cbd6df1 606 tf->command = ata_rw_cmds[index + lba48 + write];
1da177e4
LT		 607}
608
609static const char * xfer_mode_str[] = {
610 "UDMA/16",
611 "UDMA/25",
612 "UDMA/33",
613 "UDMA/44",
614 "UDMA/66",
615 "UDMA/100",
616 "UDMA/133",
617 "UDMA7",
618 "MWDMA0",
619 "MWDMA1",
620 "MWDMA2",
621 "PIO0",
622 "PIO1",
623 "PIO2",
624 "PIO3",
625 "PIO4",
626};
627
628/**
629 * ata_udma_string - convert UDMA bit offset to string
630 * @mask: mask of bits supported; only highest bit counts.
631 *
632 * Determine string which represents the highest speed
633 * (highest bit in @udma_mask).
634 *
635 * LOCKING:
636 * None.
637 *
638 * RETURNS:
639 * Constant C string representing highest speed listed in
640 * @udma_mask, or the constant C string "<n/a>".
641 */
642
643static const char *ata_mode_string(unsigned int mask)
644{
645 int i;
646
647 for (i = 7; i >= 0; i--)
648 if (mask & (1 << i))
649 goto out;
650 for (i = ATA_SHIFT_MWDMA + 2; i >= ATA_SHIFT_MWDMA; i--)
651 if (mask & (1 << i))
652 goto out;
653 for (i = ATA_SHIFT_PIO + 4; i >= ATA_SHIFT_PIO; i--)
654 if (mask & (1 << i))
655 goto out;
656
657 return "<n/a>";
658
659out:
660 return xfer_mode_str[i];
661}
662
663/**
664 * ata_pio_devchk - PATA device presence detection
665 * @ap: ATA channel to examine
666 * @device: Device to examine (starting at zero)
667 *
668 * This technique was originally described in
669 * Hale Landis's ATADRVR (www.ata-atapi.com), and
670 * later found its way into the ATA/ATAPI spec.
671 *
672 * Write a pattern to the ATA shadow registers,
673 * and if a device is present, it will respond by
674 * correctly storing and echoing back the
675 * ATA shadow register contents.
676 *
677 * LOCKING:
678 * caller.
679 */
680
681static unsigned int ata_pio_devchk(struct ata_port *ap,
682 unsigned int device)
683{
684 struct ata_ioports *ioaddr = &ap->ioaddr;
685 u8 nsect, lbal;
686
687 ap->ops->dev_select(ap, device);
688
689 outb(0x55, ioaddr->nsect_addr);
690 outb(0xaa, ioaddr->lbal_addr);
691
692 outb(0xaa, ioaddr->nsect_addr);
693 outb(0x55, ioaddr->lbal_addr);
694
695 outb(0x55, ioaddr->nsect_addr);
696 outb(0xaa, ioaddr->lbal_addr);
697
698 nsect = inb(ioaddr->nsect_addr);
699 lbal = inb(ioaddr->lbal_addr);
700
701 if ((nsect == 0x55) && (lbal == 0xaa))
702 return 1; /* we found a device */
703
704 return 0; /* nothing found */
705}
706
707/**
708 * ata_mmio_devchk - PATA device presence detection
709 * @ap: ATA channel to examine
710 * @device: Device to examine (starting at zero)
711 *
712 * This technique was originally described in
713 * Hale Landis's ATADRVR (www.ata-atapi.com), and
714 * later found its way into the ATA/ATAPI spec.
715 *
716 * Write a pattern to the ATA shadow registers,
717 * and if a device is present, it will respond by
718 * correctly storing and echoing back the
719 * ATA shadow register contents.
720 *
721 * LOCKING:
722 * caller.
723 */
724
725static unsigned int ata_mmio_devchk(struct ata_port *ap,
726 unsigned int device)
727{
728 struct ata_ioports *ioaddr = &ap->ioaddr;
729 u8 nsect, lbal;
730
731 ap->ops->dev_select(ap, device);
732
733 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
734 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
735
736 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
737 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
738
739 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
740 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
741
742 nsect = readb((void __iomem *) ioaddr->nsect_addr);
743 lbal = readb((void __iomem *) ioaddr->lbal_addr);
744
745 if ((nsect == 0x55) && (lbal == 0xaa))
746 return 1; /* we found a device */
747
748 return 0; /* nothing found */
749}
750
751/**
752 * ata_devchk - PATA device presence detection
753 * @ap: ATA channel to examine
754 * @device: Device to examine (starting at zero)
755 *
756 * Dispatch ATA device presence detection, depending
757 * on whether we are using PIO or MMIO to talk to the
758 * ATA shadow registers.
759 *
760 * LOCKING:
761 * caller.
762 */
763
764static unsigned int ata_devchk(struct ata_port *ap,
765 unsigned int device)
766{
767 if (ap->flags & ATA_FLAG_MMIO)
768 return ata_mmio_devchk(ap, device);
769 return ata_pio_devchk(ap, device);
770}
771
772/**
773 * ata_dev_classify - determine device type based on ATA-spec signature
774 * @tf: ATA taskfile register set for device to be identified
775 *
776 * Determine from taskfile register contents whether a device is
777 * ATA or ATAPI, as per "Signature and persistence" section
778 * of ATA/PI spec (volume 1, sect 5.14).
779 *
780 * LOCKING:
781 * None.
782 *
783 * RETURNS:
784 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
785 * the event of failure.
786 */
787
057ace5e 788unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT		 789{
790 /* Apple's open source Darwin code hints that some devices only
791 * put a proper signature into the LBA mid/high registers,
792 * So, we only check those. It's sufficient for uniqueness.
793 */
794
795 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
796 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
797 DPRINTK("found ATA device by sig\n");
798 return ATA_DEV_ATA;
799 }
800
801 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
802 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
803 DPRINTK("found ATAPI device by sig\n");
804 return ATA_DEV_ATAPI;
805 }
806
807 DPRINTK("unknown device\n");
808 return ATA_DEV_UNKNOWN;
809}
810
811/**
812 * ata_dev_try_classify - Parse returned ATA device signature
813 * @ap: ATA channel to examine
814 * @device: Device to examine (starting at zero)
815 *
816 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
817 * an ATA/ATAPI-defined set of values is placed in the ATA
818 * shadow registers, indicating the results of device detection
819 * and diagnostics.
820 *
821 * Select the ATA device, and read the values from the ATA shadow
822 * registers. Then parse according to the Error register value,
823 * and the spec-defined values examined by ata_dev_classify().
824 *
825 * LOCKING:
826 * caller.
827 */
828
829static u8 ata_dev_try_classify(struct ata_port *ap, unsigned int device)
830{
831 struct ata_device *dev = &ap->device[device];
832 struct ata_taskfile tf;
833 unsigned int class;
834 u8 err;
835
836 ap->ops->dev_select(ap, device);
837
838 memset(&tf, 0, sizeof(tf));
839
1da177e4 840 ap->ops->tf_read(ap, &tf);
0169e284 841 err = tf.feature;
1da177e4
LT		 842
843 dev->class = ATA_DEV_NONE;
844
845 /* see if device passed diags */
846 if (err == 1)
847 /* do nothing */ ;
848 else if ((device == 0) && (err == 0x81))
849 /* do nothing */ ;
850 else
851 return err;
852
853 /* determine if device if ATA or ATAPI */
854 class = ata_dev_classify(&tf);
855 if (class == ATA_DEV_UNKNOWN)
856 return err;
857 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
858 return err;
859
860 dev->class = class;
861
862 return err;
863}
864
865/**
866 * ata_dev_id_string - Convert IDENTIFY DEVICE page into string
867 * @id: IDENTIFY DEVICE results we will examine
868 * @s: string into which data is output
869 * @ofs: offset into identify device page
870 * @len: length of string to return. must be an even number.
871 *
872 * The strings in the IDENTIFY DEVICE page are broken up into
873 * 16-bit chunks. Run through the string, and output each
874 * 8-bit chunk linearly, regardless of platform.
875 *
876 * LOCKING:
877 * caller.
878 */
879
057ace5e 880void ata_dev_id_string(const u16 *id, unsigned char *s,
1da177e4
LT		 881 unsigned int ofs, unsigned int len)
882{
883 unsigned int c;
884
885 while (len > 0) {
886 c = id[ofs] >> 8;
887 *s = c;
888 s++;
889
890 c = id[ofs] & 0xff;
891 *s = c;
892 s++;
893
894 ofs++;
895 len -= 2;
896 }
897}
898
0baab86b
EF		 899
900/**
901 * ata_noop_dev_select - Select device 0/1 on ATA bus
902 * @ap: ATA channel to manipulate
903 * @device: ATA device (numbered from zero) to select
904 *
905 * This function performs no actual function.
906 *
907 * May be used as the dev_select() entry in ata_port_operations.
908 *
909 * LOCKING:
910 * caller.
911 */
1da177e4
LT		 912void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
913{
914}
915
0baab86b 916
1da177e4
LT		 917/**
918 * ata_std_dev_select - Select device 0/1 on ATA bus
919 * @ap: ATA channel to manipulate
920 * @device: ATA device (numbered from zero) to select
921 *
922 * Use the method defined in the ATA specification to
923 * make either device 0, or device 1, active on the
0baab86b
EF		 924 * ATA channel. Works with both PIO and MMIO.
925 *
926 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT		 927 *
928 * LOCKING:
929 * caller.
930 */
931
932void ata_std_dev_select (struct ata_port *ap, unsigned int device)
933{
934 u8 tmp;
935
936 if (device == 0)
937 tmp = ATA_DEVICE_OBS;
938 else
939 tmp = ATA_DEVICE_OBS | ATA_DEV1;
940
941 if (ap->flags & ATA_FLAG_MMIO) {
942 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
943 } else {
944 outb(tmp, ap->ioaddr.device_addr);
945 }
946 ata_pause(ap); /* needed; also flushes, for mmio */
947}
948
949/**
950 * ata_dev_select - Select device 0/1 on ATA bus
951 * @ap: ATA channel to manipulate
952 * @device: ATA device (numbered from zero) to select
953 * @wait: non-zero to wait for Status register BSY bit to clear
954 * @can_sleep: non-zero if context allows sleeping
955 *
956 * Use the method defined in the ATA specification to
957 * make either device 0, or device 1, active on the
958 * ATA channel.
959 *
960 * This is a high-level version of ata_std_dev_select(),
961 * which additionally provides the services of inserting
962 * the proper pauses and status polling, where needed.
963 *
964 * LOCKING:
965 * caller.
966 */
967
968void ata_dev_select(struct ata_port *ap, unsigned int device,
969 unsigned int wait, unsigned int can_sleep)
970{
971 VPRINTK("ENTER, ata%u: device %u, wait %u\n",
972 ap->id, device, wait);
973
974 if (wait)
975 ata_wait_idle(ap);
976
977 ap->ops->dev_select(ap, device);
978
979 if (wait) {
980 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
981 msleep(150);
982 ata_wait_idle(ap);
983 }
984}
985
986/**
987 * ata_dump_id - IDENTIFY DEVICE info debugging output
988 * @dev: Device whose IDENTIFY DEVICE page we will dump
989 *
990 * Dump selected 16-bit words from a detected device's
991 * IDENTIFY PAGE page.
992 *
993 * LOCKING:
994 * caller.
995 */
996
057ace5e 997static inline void ata_dump_id(const struct ata_device *dev)
1da177e4
LT		 998{
999 DPRINTK("49==0x%04x "
1000 "53==0x%04x "
1001 "63==0x%04x "
1002 "64==0x%04x "
1003 "75==0x%04x \n",
1004 dev->id[49],
1005 dev->id[53],
1006 dev->id[63],
1007 dev->id[64],
1008 dev->id[75]);
1009 DPRINTK("80==0x%04x "
1010 "81==0x%04x "
1011 "82==0x%04x "
1012 "83==0x%04x "
1013 "84==0x%04x \n",
1014 dev->id[80],
1015 dev->id[81],
1016 dev->id[82],
1017 dev->id[83],
1018 dev->id[84]);
1019 DPRINTK("88==0x%04x "
1020 "93==0x%04x\n",
1021 dev->id[88],
1022 dev->id[93]);
1023}
1024
11e29e21
AC		 1025/*
1026 * Compute the PIO modes available for this device. This is not as
1027 * trivial as it seems if we must consider early devices correctly.
1028 *
1029 * FIXME: pre IDE drive timing (do we care ?).
1030 */
1031
057ace5e 1032static unsigned int ata_pio_modes(const struct ata_device *adev)
11e29e21
AC		 1033{
1034 u16 modes;
1035
1036 /* Usual case. Word 53 indicates word 88 is valid */
1037 if (adev->id[ATA_ID_FIELD_VALID] & (1 << 2)) {
1038 modes = adev->id[ATA_ID_PIO_MODES] & 0x03;
1039 modes <<= 3;
1040 modes |= 0x7;
1041 return modes;
1042 }
1043
1044 /* If word 88 isn't valid then Word 51 holds the PIO timing number
1045 for the maximum. Turn it into a mask and return it */
1046 modes = (2 << (adev->id[ATA_ID_OLD_PIO_MODES] & 0xFF)) - 1 ;
1047 return modes;
1048}
1049
1da177e4
LT		 1050/**
1051 * ata_dev_identify - obtain IDENTIFY x DEVICE page
1052 * @ap: port on which device we wish to probe resides
1053 * @device: device bus address, starting at zero
1054 *
1055 * Following bus reset, we issue the IDENTIFY [PACKET] DEVICE
1056 * command, and read back the 512-byte device information page.
1057 * The device information page is fed to us via the standard
1058 * PIO-IN protocol, but we hand-code it here. (TODO: investigate
1059 * using standard PIO-IN paths)
1060 *
1061 * After reading the device information page, we use several
1062 * bits of information from it to initialize data structures
1063 * that will be used during the lifetime of the ata_device.
1064 * Other data from the info page is used to disqualify certain
1065 * older ATA devices we do not wish to support.
1066 *
1067 * LOCKING:
1068 * Inherited from caller. Some functions called by this function
1069 * obtain the host_set lock.
1070 */
1071
1072static void ata_dev_identify(struct ata_port *ap, unsigned int device)
1073{
1074 struct ata_device *dev = &ap->device[device];
8bf62ece 1075 unsigned int major_version;
1da177e4
LT		 1076 u16 tmp;
1077 unsigned long xfer_modes;
1da177e4
LT		 1078 unsigned int using_edd;
1079 DECLARE_COMPLETION(wait);
1080 struct ata_queued_cmd *qc;
1081 unsigned long flags;
1082 int rc;
1083
1084 if (!ata_dev_present(dev)) {
1085 DPRINTK("ENTER/EXIT (host %u, dev %u) -- nodev\n",
1086 ap->id, device);
1087 return;
1088 }
1089
1090 if (ap->flags & (ATA_FLAG_SRST | ATA_FLAG_SATA_RESET))
1091 using_edd = 0;
1092 else
1093 using_edd = 1;
1094
1095 DPRINTK("ENTER, host %u, dev %u\n", ap->id, device);
1096
1097 assert (dev->class == ATA_DEV_ATA || dev->class == ATA_DEV_ATAPI ||
1098 dev->class == ATA_DEV_NONE);
1099
1100 ata_dev_select(ap, device, 1, 1); /* select device 0/1 */
1101
1102 qc = ata_qc_new_init(ap, dev);
1103 BUG_ON(qc == NULL);
1104
1105 ata_sg_init_one(qc, dev->id, sizeof(dev->id));
1106 qc->dma_dir = DMA_FROM_DEVICE;
1107 qc->tf.protocol = ATA_PROT_PIO;
1108 qc->nsect = 1;
1109
1110retry:
1111 if (dev->class == ATA_DEV_ATA) {
1112 qc->tf.command = ATA_CMD_ID_ATA;
1113 DPRINTK("do ATA identify\n");
1114 } else {
1115 qc->tf.command = ATA_CMD_ID_ATAPI;
1116 DPRINTK("do ATAPI identify\n");
1117 }
1118
1119 qc->waiting = &wait;
1120 qc->complete_fn = ata_qc_complete_noop;
1121
1122 spin_lock_irqsave(&ap->host_set->lock, flags);
1123 rc = ata_qc_issue(qc);
1124 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1125
1126 if (rc)
1127 goto err_out;
1128 else
1129 wait_for_completion(&wait);
1130
0169e284
JG		 1131 spin_lock_irqsave(&ap->host_set->lock, flags);
1132 ap->ops->tf_read(ap, &qc->tf);
1133 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1134
1135 if (qc->tf.command & ATA_ERR) {
1da177e4
LT		 1136 /*
1137 * arg! EDD works for all test cases, but seems to return
1138 * the ATA signature for some ATAPI devices. Until the
1139 * reason for this is found and fixed, we fix up the mess
1140 * here. If IDENTIFY DEVICE returns command aborted
1141 * (as ATAPI devices do), then we issue an
1142 * IDENTIFY PACKET DEVICE.
1143 *
1144 * ATA software reset (SRST, the default) does not appear
1145 * to have this problem.
1146 */
1147 if ((using_edd) && (qc->tf.command == ATA_CMD_ID_ATA)) {
0169e284 1148 u8 err = qc->tf.feature;
1da177e4
LT		 1149 if (err & ATA_ABORTED) {
1150 dev->class = ATA_DEV_ATAPI;
1151 qc->cursg = 0;
1152 qc->cursg_ofs = 0;
1153 qc->cursect = 0;
1154 qc->nsect = 1;
1155 goto retry;
1156 }
1157 }
1158 goto err_out;
1159 }
1160
1161 swap_buf_le16(dev->id, ATA_ID_WORDS);
1162
1163 /* print device capabilities */
1164 printk(KERN_DEBUG "ata%u: dev %u cfg "
1165 "49:%04x 82:%04x 83:%04x 84:%04x 85:%04x 86:%04x 87:%04x 88:%04x\n",
1166 ap->id, device, dev->id[49],
1167 dev->id[82], dev->id[83], dev->id[84],
1168 dev->id[85], dev->id[86], dev->id[87],
1169 dev->id[88]);
1170
1171 /*
1172 * common ATA, ATAPI feature tests
1173 */
1174
8bf62ece
AL		 1175 /* we require DMA support (bits 8 of word 49) */
1176 if (!ata_id_has_dma(dev->id)) {
1177 printk(KERN_DEBUG "ata%u: no dma\n", ap->id);
1da177e4
LT		 1178 goto err_out_nosup;
1179 }
1180
1181 /* quick-n-dirty find max transfer mode; for printk only */
1182 xfer_modes = dev->id[ATA_ID_UDMA_MODES];
1183 if (!xfer_modes)
1184 xfer_modes = (dev->id[ATA_ID_MWDMA_MODES]) << ATA_SHIFT_MWDMA;
11e29e21
AC		 1185 if (!xfer_modes)
1186 xfer_modes = ata_pio_modes(dev);
1da177e4
LT		 1187
1188 ata_dump_id(dev);
1189
1190 /* ATA-specific feature tests */
1191 if (dev->class == ATA_DEV_ATA) {
1192 if (!ata_id_is_ata(dev->id)) /* sanity check */
1193 goto err_out_nosup;
1194
8bf62ece 1195 /* get major version */
1da177e4 1196 tmp = dev->id[ATA_ID_MAJOR_VER];
8bf62ece
AL		 1197 for (major_version = 14; major_version >= 1; major_version--)
1198 if (tmp & (1 << major_version))
1da177e4
LT		 1199 break;
1200
8bf62ece
AL		 1201 /*
1202 * The exact sequence expected by certain pre-ATA4 drives is:
1203 * SRST RESET
1204 * IDENTIFY
1205 * INITIALIZE DEVICE PARAMETERS
1206 * anything else..
1207 * Some drives were very specific about that exact sequence.
1208 */
59a10b17 1209 if (major_version < 4 || (!ata_id_has_lba(dev->id))) {
8bf62ece
AL		 1210 ata_dev_init_params(ap, dev);
1211
59a10b17
AL		 1212 /* current CHS translation info (id[53-58]) might be
1213 * changed. reread the identify device info.
1214 */
1215 ata_dev_reread_id(ap, dev);
1216 }
1217
8bf62ece
AL		 1218 if (ata_id_has_lba(dev->id)) {
1219 dev->flags |= ATA_DFLAG_LBA;
1220
1221 if (ata_id_has_lba48(dev->id)) {
1222 dev->flags |= ATA_DFLAG_LBA48;
1223 dev->n_sectors = ata_id_u64(dev->id, 100);
1224 } else {
1225 dev->n_sectors = ata_id_u32(dev->id, 60);
1226 }
1227
1228 /* print device info to dmesg */
1229 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors:%s\n",
1230 ap->id, device,
1231 major_version,
1232 ata_mode_string(xfer_modes),
1233 (unsigned long long)dev->n_sectors,
1234 dev->flags & ATA_DFLAG_LBA48 ? " LBA48" : " LBA");
1235 } else {
1236 /* CHS */
1237
1238 /* Default translation */
1239 dev->cylinders = dev->id[1];
1240 dev->heads = dev->id[3];
1241 dev->sectors = dev->id[6];
1242 dev->n_sectors = dev->cylinders * dev->heads * dev->sectors;
1243
1244 if (ata_id_current_chs_valid(dev->id)) {
1245 /* Current CHS translation is valid. */
1246 dev->cylinders = dev->id[54];
1247 dev->heads = dev->id[55];
1248 dev->sectors = dev->id[56];
1249
1250 dev->n_sectors = ata_id_u32(dev->id, 57);
1251 }
1252
1253 /* print device info to dmesg */
1254 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors: CHS %d/%d/%d\n",
1255 ap->id, device,
1256 major_version,
1257 ata_mode_string(xfer_modes),
1258 (unsigned long long)dev->n_sectors,
1259 (int)dev->cylinders, (int)dev->heads, (int)dev->sectors);
1da177e4 1260
1da177e4
LT		 1261 }
1262
1263 ap->host->max_cmd_len = 16;
1da177e4
LT		 1264 }
1265
1266 /* ATAPI-specific feature tests */
1267 else {
1268 if (ata_id_is_ata(dev->id)) /* sanity check */
1269 goto err_out_nosup;
1270
1271 rc = atapi_cdb_len(dev->id);
1272 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
1273 printk(KERN_WARNING "ata%u: unsupported CDB len\n", ap->id);
1274 goto err_out_nosup;
1275 }
1276 ap->cdb_len = (unsigned int) rc;
1277 ap->host->max_cmd_len = (unsigned char) ap->cdb_len;
1278
1279 /* print device info to dmesg */
1280 printk(KERN_INFO "ata%u: dev %u ATAPI, max %s\n",
1281 ap->id, device,
1282 ata_mode_string(xfer_modes));
1283 }
1284
1285 DPRINTK("EXIT, drv_stat = 0x%x\n", ata_chk_status(ap));
1286 return;
1287
1288err_out_nosup:
1289 printk(KERN_WARNING "ata%u: dev %u not supported, ignoring\n",
1290 ap->id, device);
1291err_out:
1292 dev->class++; /* converts ATA_DEV_xxx into ATA_DEV_xxx_UNSUP */
1293 DPRINTK("EXIT, err\n");
1294}
1295
6f2f3812 1296
057ace5e 1297static inline u8 ata_dev_knobble(const struct ata_port *ap)
6f2f3812
BC		 1298{
1299 return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ap->device->id)));
1300}
1301
1302/**
1303 * ata_dev_config - Run device specific handlers and check for
1304 * SATA->PATA bridges
8a60a071 1305 * @ap: Bus
6f2f3812
BC		 1306 * @i: Device
1307 *
1308 * LOCKING:
1309 */
8a60a071 1310
6f2f3812
BC		 1311void ata_dev_config(struct ata_port *ap, unsigned int i)
1312{
1313 /* limit bridge transfers to udma5, 200 sectors */
1314 if (ata_dev_knobble(ap)) {
1315 printk(KERN_INFO "ata%u(%u): applying bridge limits\n",
1316 ap->id, ap->device->devno);
1317 ap->udma_mask &= ATA_UDMA5;
1318 ap->host->max_sectors = ATA_MAX_SECTORS;
1319 ap->host->hostt->max_sectors = ATA_MAX_SECTORS;
1320 ap->device->flags |= ATA_DFLAG_LOCK_SECTORS;
1321 }
1322
1323 if (ap->ops->dev_config)
1324 ap->ops->dev_config(ap, &ap->device[i]);
1325}
1326
1da177e4
LT		 1327/**
1328 * ata_bus_probe - Reset and probe ATA bus
1329 * @ap: Bus to probe
1330 *
0cba632b
JG		 1331 * Master ATA bus probing function. Initiates a hardware-dependent
1332 * bus reset, then attempts to identify any devices found on
1333 * the bus.
1334 *
1da177e4 1335 * LOCKING:
0cba632b 1336 * PCI/etc. bus probe sem.
1da177e4
LT		 1337 *
1338 * RETURNS:
1339 * Zero on success, non-zero on error.
1340 */
1341
1342static int ata_bus_probe(struct ata_port *ap)
1343{
1344 unsigned int i, found = 0;
1345
1346 ap->ops->phy_reset(ap);
1347 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1348 goto err_out;
1349
1350 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1351 ata_dev_identify(ap, i);
1352 if (ata_dev_present(&ap->device[i])) {
1353 found = 1;
6f2f3812 1354 ata_dev_config(ap,i);
1da177e4
LT		 1355 }
1356 }
1357
1358 if ((!found) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1359 goto err_out_disable;
1360
1361 ata_set_mode(ap);
1362 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1363 goto err_out_disable;
1364
1365 return 0;
1366
1367err_out_disable:
1368 ap->ops->port_disable(ap);
1369err_out:
1370 return -1;
1371}
1372
1373/**
0cba632b
JG		 1374 * ata_port_probe - Mark port as enabled
1375 * @ap: Port for which we indicate enablement
1da177e4 1376 *
0cba632b
JG		 1377 * Modify @ap data structure such that the system
1378 * thinks that the entire port is enabled.
1379 *
1380 * LOCKING: host_set lock, or some other form of
1381 * serialization.
1da177e4
LT		 1382 */
1383
1384void ata_port_probe(struct ata_port *ap)
1385{
1386 ap->flags &= ~ATA_FLAG_PORT_DISABLED;
1387}
1388
1389/**
780a87f7
JG		 1390 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1391 * @ap: SATA port associated with target SATA PHY.
1da177e4 1392 *
780a87f7
JG		 1393 * This function issues commands to standard SATA Sxxx
1394 * PHY registers, to wake up the phy (and device), and
1395 * clear any reset condition.
1da177e4
LT		 1396 *
1397 * LOCKING:
0cba632b 1398 * PCI/etc. bus probe sem.
1da177e4
LT		 1399 *
1400 */
1401void __sata_phy_reset(struct ata_port *ap)
1402{
1403 u32 sstatus;
1404 unsigned long timeout = jiffies + (HZ * 5);
1405
1406 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e
BR		 1407 /* issue phy wake/reset */
1408 scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH		 1409 /* Couldn't find anything in SATA I/II specs, but
1410 * AHCI-1.1 10.4.2 says at least 1 ms. */
1411 mdelay(1);
1da177e4 1412 }
cdcca89e 1413 scr_write_flush(ap, SCR_CONTROL, 0x300); /* phy wake/clear reset */
1da177e4
LT		 1414
1415 /* wait for phy to become ready, if necessary */
1416 do {
1417 msleep(200);
1418 sstatus = scr_read(ap, SCR_STATUS);
1419 if ((sstatus & 0xf) != 1)
1420 break;
1421 } while (time_before(jiffies, timeout));
1422
1423 /* TODO: phy layer with polling, timeouts, etc. */
1424 if (sata_dev_present(ap))
1425 ata_port_probe(ap);
1426 else {
1427 sstatus = scr_read(ap, SCR_STATUS);
1428 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1429 ap->id, sstatus);
1430 ata_port_disable(ap);
1431 }
1432
1433 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1434 return;
1435
1436 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1437 ata_port_disable(ap);
1438 return;
1439 }
1440
1441 ap->cbl = ATA_CBL_SATA;
1442}
1443
1444/**
780a87f7
JG		 1445 * sata_phy_reset - Reset SATA bus.
1446 * @ap: SATA port associated with target SATA PHY.
1da177e4 1447 *
780a87f7
JG		 1448 * This function resets the SATA bus, and then probes
1449 * the bus for devices.
1da177e4
LT		 1450 *
1451 * LOCKING:
0cba632b 1452 * PCI/etc. bus probe sem.
1da177e4
LT		 1453 *
1454 */
1455void sata_phy_reset(struct ata_port *ap)
1456{
1457 __sata_phy_reset(ap);
1458 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1459 return;
1460 ata_bus_reset(ap);
1461}
1462
1463/**
780a87f7
JG		 1464 * ata_port_disable - Disable port.
1465 * @ap: Port to be disabled.
1da177e4 1466 *
780a87f7
JG		 1467 * Modify @ap data structure such that the system
1468 * thinks that the entire port is disabled, and should
1469 * never attempt to probe or communicate with devices
1470 * on this port.
1471 *
1472 * LOCKING: host_set lock, or some other form of
1473 * serialization.
1da177e4
LT		 1474 */
1475
1476void ata_port_disable(struct ata_port *ap)
1477{
1478 ap->device[0].class = ATA_DEV_NONE;
1479 ap->device[1].class = ATA_DEV_NONE;
1480 ap->flags |= ATA_FLAG_PORT_DISABLED;
1481}
1482
452503f9
AC		 1483/*
1484 * This mode timing computation functionality is ported over from
1485 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1486 */
1487/*
1488 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
1489 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
1490 * for PIO 5, which is a nonstandard extension and UDMA6, which
1491 * is currently supported only by Maxtor drives.
1492 */
1493
1494static const struct ata_timing ata_timing[] = {
1495
1496 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1497 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1498 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1499 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1500
1501 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1502 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1503 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1504
1505/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
1506
1507 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1508 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1509 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
1510
1511 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
1512 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
1513 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
1514
1515/* { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, */
1516 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
1517 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
1518
1519 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
1520 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
1521 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
1522
1523/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
1524
1525 { 0xFF }
1526};
1527
1528#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
1529#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
1530
1531static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
1532{
1533 q->setup = EZ(t->setup * 1000, T);
1534 q->act8b = EZ(t->act8b * 1000, T);
1535 q->rec8b = EZ(t->rec8b * 1000, T);
1536 q->cyc8b = EZ(t->cyc8b * 1000, T);
1537 q->active = EZ(t->active * 1000, T);
1538 q->recover = EZ(t->recover * 1000, T);
1539 q->cycle = EZ(t->cycle * 1000, T);
1540 q->udma = EZ(t->udma * 1000, UT);
1541}
1542
1543void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
1544 struct ata_timing *m, unsigned int what)
1545{
1546 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
1547 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
1548 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
1549 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
1550 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
1551 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
1552 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
1553 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
1554}
1555
1556static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
1557{
1558 const struct ata_timing *t;
1559
1560 for (t = ata_timing; t->mode != speed; t++)
91190758 1561 if (t->mode == 0xFF)
452503f9
AC		 1562 return NULL;
1563 return t;
1564}
1565
1566int ata_timing_compute(struct ata_device *adev, unsigned short speed,
1567 struct ata_timing *t, int T, int UT)
1568{
1569 const struct ata_timing *s;
1570 struct ata_timing p;
1571
1572 /*
1573 * Find the mode.
1574 */
1575
1576 if (!(s = ata_timing_find_mode(speed)))
1577 return -EINVAL;
1578
1579 /*
1580 * If the drive is an EIDE drive, it can tell us it needs extended
1581 * PIO/MW_DMA cycle timing.
1582 */
1583
1584 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
1585 memset(&p, 0, sizeof(p));
1586 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
1587 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
1588 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
1589 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
1590 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
1591 }
1592 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
1593 }
1594
1595 /*
1596 * Convert the timing to bus clock counts.
1597 */
1598
1599 ata_timing_quantize(s, t, T, UT);
1600
1601 /*
1602 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T
1603 * and some other commands. We have to ensure that the DMA cycle timing is
1604 * slower/equal than the fastest PIO timing.
1605 */
1606
1607 if (speed > XFER_PIO_4) {
1608 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
1609 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
1610 }
1611
1612 /*
1613 * Lenghten active & recovery time so that cycle time is correct.
1614 */
1615
1616 if (t->act8b + t->rec8b < t->cyc8b) {
1617 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
1618 t->rec8b = t->cyc8b - t->act8b;
1619 }
1620
1621 if (t->active + t->recover < t->cycle) {
1622 t->active += (t->cycle - (t->active + t->recover)) / 2;
1623 t->recover = t->cycle - t->active;
1624 }
1625
1626 return 0;
1627}
1628
057ace5e 1629static const struct {
1da177e4
LT		 1630 unsigned int shift;
1631 u8 base;
1632} xfer_mode_classes[] = {
1633 { ATA_SHIFT_UDMA, XFER_UDMA_0 },
1634 { ATA_SHIFT_MWDMA, XFER_MW_DMA_0 },
1635 { ATA_SHIFT_PIO, XFER_PIO_0 },
1636};
1637
1638static inline u8 base_from_shift(unsigned int shift)
1639{
1640 int i;
1641
1642 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++)
1643 if (xfer_mode_classes[i].shift == shift)
1644 return xfer_mode_classes[i].base;
1645
1646 return 0xff;
1647}
1648
1649static void ata_dev_set_mode(struct ata_port *ap, struct ata_device *dev)
1650{
1651 int ofs, idx;
1652 u8 base;
1653
1654 if (!ata_dev_present(dev) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1655 return;
1656
1657 if (dev->xfer_shift == ATA_SHIFT_PIO)
1658 dev->flags |= ATA_DFLAG_PIO;
1659
1660 ata_dev_set_xfermode(ap, dev);
1661
1662 base = base_from_shift(dev->xfer_shift);
1663 ofs = dev->xfer_mode - base;
1664 idx = ofs + dev->xfer_shift;
1665 WARN_ON(idx >= ARRAY_SIZE(xfer_mode_str));
1666
1667 DPRINTK("idx=%d xfer_shift=%u, xfer_mode=0x%x, base=0x%x, offset=%d\n",
1668 idx, dev->xfer_shift, (int)dev->xfer_mode, (int)base, ofs);
1669
1670 printk(KERN_INFO "ata%u: dev %u configured for %s\n",
1671 ap->id, dev->devno, xfer_mode_str[idx]);
1672}
1673
1674static int ata_host_set_pio(struct ata_port *ap)
1675{
1676 unsigned int mask;
1677 int x, i;
1678 u8 base, xfer_mode;
1679
1680 mask = ata_get_mode_mask(ap, ATA_SHIFT_PIO);
1681 x = fgb(mask);
1682 if (x < 0) {
1683 printk(KERN_WARNING "ata%u: no PIO support\n", ap->id);
1684 return -1;
1685 }
1686
1687 base = base_from_shift(ATA_SHIFT_PIO);
1688 xfer_mode = base + x;
1689
1690 DPRINTK("base 0x%x xfer_mode 0x%x mask 0x%x x %d\n",
1691 (int)base, (int)xfer_mode, mask, x);
1692
1693 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1694 struct ata_device *dev = &ap->device[i];
1695 if (ata_dev_present(dev)) {
1696 dev->pio_mode = xfer_mode;
1697 dev->xfer_mode = xfer_mode;
1698 dev->xfer_shift = ATA_SHIFT_PIO;
1699 if (ap->ops->set_piomode)
1700 ap->ops->set_piomode(ap, dev);
1701 }
1702 }
1703
1704 return 0;
1705}
1706
1707static void ata_host_set_dma(struct ata_port *ap, u8 xfer_mode,
1708 unsigned int xfer_shift)
1709{
1710 int i;
1711
1712 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1713 struct ata_device *dev = &ap->device[i];
1714 if (ata_dev_present(dev)) {
1715 dev->dma_mode = xfer_mode;
1716 dev->xfer_mode = xfer_mode;
1717 dev->xfer_shift = xfer_shift;
1718 if (ap->ops->set_dmamode)
1719 ap->ops->set_dmamode(ap, dev);
1720 }
1721 }
1722}
1723
1724/**
1725 * ata_set_mode - Program timings and issue SET FEATURES - XFER
1726 * @ap: port on which timings will be programmed
1727 *
780a87f7
JG		 1728 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.).
1729 *
1da177e4 1730 * LOCKING:
0cba632b 1731 * PCI/etc. bus probe sem.
1da177e4
LT		 1732 *
1733 */
1734static void ata_set_mode(struct ata_port *ap)
1735{
8cbd6df1 1736 unsigned int xfer_shift;
1da177e4
LT		 1737 u8 xfer_mode;
1738 int rc;
1739
1740 /* step 1: always set host PIO timings */
1741 rc = ata_host_set_pio(ap);
1742 if (rc)
1743 goto err_out;
1744
1745 /* step 2: choose the best data xfer mode */
1746 xfer_mode = xfer_shift = 0;
1747 rc = ata_choose_xfer_mode(ap, &xfer_mode, &xfer_shift);
1748 if (rc)
1749 goto err_out;
1750
1751 /* step 3: if that xfer mode isn't PIO, set host DMA timings */
1752 if (xfer_shift != ATA_SHIFT_PIO)
1753 ata_host_set_dma(ap, xfer_mode, xfer_shift);
1754
1755 /* step 4: update devices' xfer mode */
1756 ata_dev_set_mode(ap, &ap->device[0]);
1757 ata_dev_set_mode(ap, &ap->device[1]);
1758
1759 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1760 return;
1761
1762 if (ap->ops->post_set_mode)
1763 ap->ops->post_set_mode(ap);
1764
1da177e4
LT		 1765 return;
1766
1767err_out:
1768 ata_port_disable(ap);
1769}
1770
1771/**
1772 * ata_busy_sleep - sleep until BSY clears, or timeout
1773 * @ap: port containing status register to be polled
1774 * @tmout_pat: impatience timeout
1775 * @tmout: overall timeout
1776 *
780a87f7
JG		 1777 * Sleep until ATA Status register bit BSY clears,
1778 * or a timeout occurs.
1779 *
1780 * LOCKING: None.
1da177e4
LT		 1781 *
1782 */
1783
1784static unsigned int ata_busy_sleep (struct ata_port *ap,
1785 unsigned long tmout_pat,
1786 unsigned long tmout)
1787{
1788 unsigned long timer_start, timeout;
1789 u8 status;
1790
1791 status = ata_busy_wait(ap, ATA_BUSY, 300);
1792 timer_start = jiffies;
1793 timeout = timer_start + tmout_pat;
1794 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1795 msleep(50);
1796 status = ata_busy_wait(ap, ATA_BUSY, 3);
1797 }
1798
1799 if (status & ATA_BUSY)
1800 printk(KERN_WARNING "ata%u is slow to respond, "
1801 "please be patient\n", ap->id);
1802
1803 timeout = timer_start + tmout;
1804 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1805 msleep(50);
1806 status = ata_chk_status(ap);
1807 }
1808
1809 if (status & ATA_BUSY) {
1810 printk(KERN_ERR "ata%u failed to respond (%lu secs)\n",
1811 ap->id, tmout / HZ);
1812 return 1;
1813 }
1814
1815 return 0;
1816}
1817
1818static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
1819{
1820 struct ata_ioports *ioaddr = &ap->ioaddr;
1821 unsigned int dev0 = devmask & (1 << 0);
1822 unsigned int dev1 = devmask & (1 << 1);
1823 unsigned long timeout;
1824
1825 /* if device 0 was found in ata_devchk, wait for its
1826 * BSY bit to clear
1827 */
1828 if (dev0)
1829 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1830
1831 /* if device 1 was found in ata_devchk, wait for
1832 * register access, then wait for BSY to clear
1833 */
1834 timeout = jiffies + ATA_TMOUT_BOOT;
1835 while (dev1) {
1836 u8 nsect, lbal;
1837
1838 ap->ops->dev_select(ap, 1);
1839 if (ap->flags & ATA_FLAG_MMIO) {
1840 nsect = readb((void __iomem *) ioaddr->nsect_addr);
1841 lbal = readb((void __iomem *) ioaddr->lbal_addr);
1842 } else {
1843 nsect = inb(ioaddr->nsect_addr);
1844 lbal = inb(ioaddr->lbal_addr);
1845 }
1846 if ((nsect == 1) && (lbal == 1))
1847 break;
1848 if (time_after(jiffies, timeout)) {
1849 dev1 = 0;
1850 break;
1851 }
1852 msleep(50); /* give drive a breather */
1853 }
1854 if (dev1)
1855 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1856
1857 /* is all this really necessary? */
1858 ap->ops->dev_select(ap, 0);
1859 if (dev1)
1860 ap->ops->dev_select(ap, 1);
1861 if (dev0)
1862 ap->ops->dev_select(ap, 0);
1863}
1864
1865/**
0cba632b
JG		 1866 * ata_bus_edd - Issue EXECUTE DEVICE DIAGNOSTIC command.
1867 * @ap: Port to reset and probe
1868 *
1869 * Use the EXECUTE DEVICE DIAGNOSTIC command to reset and
1870 * probe the bus. Not often used these days.
1da177e4
LT		 1871 *
1872 * LOCKING:
0cba632b 1873 * PCI/etc. bus probe sem.
e5338254 1874 * Obtains host_set lock.
1da177e4
LT		 1875 *
1876 */
1877
1878static unsigned int ata_bus_edd(struct ata_port *ap)
1879{
1880 struct ata_taskfile tf;
e5338254 1881 unsigned long flags;
1da177e4
LT		 1882
1883 /* set up execute-device-diag (bus reset) taskfile */
1884 /* also, take interrupts to a known state (disabled) */
1885 DPRINTK("execute-device-diag\n");
1886 ata_tf_init(ap, &tf, 0);
1887 tf.ctl |= ATA_NIEN;
1888 tf.command = ATA_CMD_EDD;
1889 tf.protocol = ATA_PROT_NODATA;
1890
1891 /* do bus reset */
e5338254 1892 spin_lock_irqsave(&ap->host_set->lock, flags);
1da177e4 1893 ata_tf_to_host(ap, &tf);
e5338254 1894 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1da177e4
LT		 1895
1896 /* spec says at least 2ms. but who knows with those
1897 * crazy ATAPI devices...
1898 */
1899 msleep(150);
1900
1901 return ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1902}
1903
1904static unsigned int ata_bus_softreset(struct ata_port *ap,
1905 unsigned int devmask)
1906{
1907 struct ata_ioports *ioaddr = &ap->ioaddr;
1908
1909 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
1910
1911 /* software reset. causes dev0 to be selected */
1912 if (ap->flags & ATA_FLAG_MMIO) {
1913 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1914 udelay(20); /* FIXME: flush */
1915 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
1916 udelay(20); /* FIXME: flush */
1917 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1918 } else {
1919 outb(ap->ctl, ioaddr->ctl_addr);
1920 udelay(10);
1921 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1922 udelay(10);
1923 outb(ap->ctl, ioaddr->ctl_addr);
1924 }
1925
1926 /* spec mandates ">= 2ms" before checking status.
1927 * We wait 150ms, because that was the magic delay used for
1928 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1929 * between when the ATA command register is written, and then
1930 * status is checked. Because waiting for "a while" before
1931 * checking status is fine, post SRST, we perform this magic
1932 * delay here as well.
1933 */
1934 msleep(150);
1935
1936 ata_bus_post_reset(ap, devmask);
1937
1938 return 0;
1939}
1940
1941/**
1942 * ata_bus_reset - reset host port and associated ATA channel
1943 * @ap: port to reset
1944 *
1945 * This is typically the first time we actually start issuing
1946 * commands to the ATA channel. We wait for BSY to clear, then
1947 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
1948 * result. Determine what devices, if any, are on the channel
1949 * by looking at the device 0/1 error register. Look at the signature
1950 * stored in each device's taskfile registers, to determine if
1951 * the device is ATA or ATAPI.
1952 *
1953 * LOCKING:
0cba632b
JG		 1954 * PCI/etc. bus probe sem.
1955 * Obtains host_set lock.
1da177e4
LT		 1956 *
1957 * SIDE EFFECTS:
1958 * Sets ATA_FLAG_PORT_DISABLED if bus reset fails.
1959 */
1960
1961void ata_bus_reset(struct ata_port *ap)
1962{
1963 struct ata_ioports *ioaddr = &ap->ioaddr;
1964 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1965 u8 err;
1966 unsigned int dev0, dev1 = 0, rc = 0, devmask = 0;
1967
1968 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
1969
1970 /* determine if device 0/1 are present */
1971 if (ap->flags & ATA_FLAG_SATA_RESET)
1972 dev0 = 1;
1973 else {
1974 dev0 = ata_devchk(ap, 0);
1975 if (slave_possible)
1976 dev1 = ata_devchk(ap, 1);
1977 }
1978
1979 if (dev0)
1980 devmask |= (1 << 0);
1981 if (dev1)
1982 devmask |= (1 << 1);
1983
1984 /* select device 0 again */
1985 ap->ops->dev_select(ap, 0);
1986
1987 /* issue bus reset */
1988 if (ap->flags & ATA_FLAG_SRST)
1989 rc = ata_bus_softreset(ap, devmask);
1990 else if ((ap->flags & ATA_FLAG_SATA_RESET) == 0) {
1991 /* set up device control */
1992 if (ap->flags & ATA_FLAG_MMIO)
1993 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1994 else
1995 outb(ap->ctl, ioaddr->ctl_addr);
1996 rc = ata_bus_edd(ap);
1997 }
1998
1999 if (rc)
2000 goto err_out;
2001
2002 /*
2003 * determine by signature whether we have ATA or ATAPI devices
2004 */
2005 err = ata_dev_try_classify(ap, 0);
2006 if ((slave_possible) && (err != 0x81))
2007 ata_dev_try_classify(ap, 1);
2008
2009 /* re-enable interrupts */
2010 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2011 ata_irq_on(ap);
2012
2013 /* is double-select really necessary? */
2014 if (ap->device[1].class != ATA_DEV_NONE)
2015 ap->ops->dev_select(ap, 1);
2016 if (ap->device[0].class != ATA_DEV_NONE)
2017 ap->ops->dev_select(ap, 0);
2018
2019 /* if no devices were detected, disable this port */
2020 if ((ap->device[0].class == ATA_DEV_NONE) &&
2021 (ap->device[1].class == ATA_DEV_NONE))
2022 goto err_out;
2023
2024 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2025 /* set up device control for ATA_FLAG_SATA_RESET */
2026 if (ap->flags & ATA_FLAG_MMIO)
2027 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2028 else
2029 outb(ap->ctl, ioaddr->ctl_addr);
2030 }
2031
2032 DPRINTK("EXIT\n");
2033 return;
2034
2035err_out:
2036 printk(KERN_ERR "ata%u: disabling port\n", ap->id);
2037 ap->ops->port_disable(ap);
2038
2039 DPRINTK("EXIT\n");
2040}
2041
057ace5e
JG		 2042static void ata_pr_blacklisted(const struct ata_port *ap,
2043 const struct ata_device *dev)
1da177e4
LT		 2044{
2045 printk(KERN_WARNING "ata%u: dev %u is on DMA blacklist, disabling DMA\n",
2046 ap->id, dev->devno);
2047}
2048
2049static const char * ata_dma_blacklist [] = {
2050 "WDC AC11000H",
2051 "WDC AC22100H",
2052 "WDC AC32500H",
2053 "WDC AC33100H",
2054 "WDC AC31600H",
2055 "WDC AC32100H",
2056 "WDC AC23200L",
2057 "Compaq CRD-8241B",
2058 "CRD-8400B",
2059 "CRD-8480B",
2060 "CRD-8482B",
2061 "CRD-84",
2062 "SanDisk SDP3B",
2063 "SanDisk SDP3B-64",
2064 "SANYO CD-ROM CRD",
2065 "HITACHI CDR-8",
2066 "HITACHI CDR-8335",
2067 "HITACHI CDR-8435",
2068 "Toshiba CD-ROM XM-6202B",
e922256a 2069 "TOSHIBA CD-ROM XM-1702BC",
1da177e4
LT		 2070 "CD-532E-A",
2071 "E-IDE CD-ROM CR-840",
2072 "CD-ROM Drive/F5A",
2073 "WPI CDD-820",
2074 "SAMSUNG CD-ROM SC-148C",
2075 "SAMSUNG CD-ROM SC",
2076 "SanDisk SDP3B-64",
1da177e4
LT		 2077 "ATAPI CD-ROM DRIVE 40X MAXIMUM",
2078 "_NEC DV5800A",
2079};
2080
057ace5e 2081static int ata_dma_blacklisted(const struct ata_device *dev)
1da177e4
LT		 2082{
2083 unsigned char model_num[40];
2084 char *s;
2085 unsigned int len;
2086 int i;
2087
2088 ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
2089 sizeof(model_num));
2090 s = &model_num[0];
2091 len = strnlen(s, sizeof(model_num));
2092
2093 /* ATAPI specifies that empty space is blank-filled; remove blanks */
2094 while ((len > 0) && (s[len - 1] == ' ')) {
2095 len--;
2096 s[len] = 0;
2097 }
2098
2099 for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i++)
2100 if (!strncmp(ata_dma_blacklist[i], s, len))
2101 return 1;
2102
2103 return 0;
2104}
2105
057ace5e 2106static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift)
1da177e4 2107{
057ace5e 2108 const struct ata_device *master, *slave;
1da177e4
LT		 2109 unsigned int mask;
2110
2111 master = &ap->device[0];
2112 slave = &ap->device[1];
2113
2114 assert (ata_dev_present(master) || ata_dev_present(slave));
2115
2116 if (shift == ATA_SHIFT_UDMA) {
2117 mask = ap->udma_mask;
2118 if (ata_dev_present(master)) {
2119 mask &= (master->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2120 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2121 mask = 0;
2122 ata_pr_blacklisted(ap, master);
2123 }
2124 }
2125 if (ata_dev_present(slave)) {
2126 mask &= (slave->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2127 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2128 mask = 0;
2129 ata_pr_blacklisted(ap, slave);
2130 }
2131 }
2132 }
2133 else if (shift == ATA_SHIFT_MWDMA) {
2134 mask = ap->mwdma_mask;
2135 if (ata_dev_present(master)) {
2136 mask &= (master->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2137 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2138 mask = 0;
2139 ata_pr_blacklisted(ap, master);
2140 }
2141 }
2142 if (ata_dev_present(slave)) {
2143 mask &= (slave->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2144 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2145 mask = 0;
2146 ata_pr_blacklisted(ap, slave);
2147 }
2148 }
2149 }
2150 else if (shift == ATA_SHIFT_PIO) {
2151 mask = ap->pio_mask;
2152 if (ata_dev_present(master)) {
2153 /* spec doesn't return explicit support for
2154 * PIO0-2, so we fake it
2155 */
2156 u16 tmp_mode = master->id[ATA_ID_PIO_MODES] & 0x03;
2157 tmp_mode <<= 3;
2158 tmp_mode |= 0x7;
2159 mask &= tmp_mode;
2160 }
2161 if (ata_dev_present(slave)) {
2162 /* spec doesn't return explicit support for
2163 * PIO0-2, so we fake it
2164 */
2165 u16 tmp_mode = slave->id[ATA_ID_PIO_MODES] & 0x03;
2166 tmp_mode <<= 3;
2167 tmp_mode |= 0x7;
2168 mask &= tmp_mode;
2169 }
2170 }
2171 else {
2172 mask = 0xffffffff; /* shut up compiler warning */
2173 BUG();
2174 }
2175
2176 return mask;
2177}
2178
2179/* find greatest bit */
2180static int fgb(u32 bitmap)
2181{
2182 unsigned int i;
2183 int x = -1;
2184
2185 for (i = 0; i < 32; i++)
2186 if (bitmap & (1 << i))
2187 x = i;
2188
2189 return x;
2190}
2191
2192/**
2193 * ata_choose_xfer_mode - attempt to find best transfer mode
2194 * @ap: Port for which an xfer mode will be selected
2195 * @xfer_mode_out: (output) SET FEATURES - XFER MODE code
2196 * @xfer_shift_out: (output) bit shift that selects this mode
2197 *
0cba632b
JG		 2198 * Based on host and device capabilities, determine the
2199 * maximum transfer mode that is amenable to all.
2200 *
1da177e4 2201 * LOCKING:
0cba632b 2202 * PCI/etc. bus probe sem.
1da177e4
LT		 2203 *
2204 * RETURNS:
2205 * Zero on success, negative on error.
2206 */
2207
057ace5e 2208static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 2209 u8 *xfer_mode_out,
2210 unsigned int *xfer_shift_out)
2211{
2212 unsigned int mask, shift;
2213 int x, i;
2214
2215 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++) {
2216 shift = xfer_mode_classes[i].shift;
2217 mask = ata_get_mode_mask(ap, shift);
2218
2219 x = fgb(mask);
2220 if (x >= 0) {
2221 *xfer_mode_out = xfer_mode_classes[i].base + x;
2222 *xfer_shift_out = shift;
2223 return 0;
2224 }
2225 }
2226
2227 return -1;
2228}
2229
2230/**
2231 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
2232 * @ap: Port associated with device @dev
2233 * @dev: Device to which command will be sent
2234 *
780a87f7
JG		 2235 * Issue SET FEATURES - XFER MODE command to device @dev
2236 * on port @ap.
2237 *
1da177e4 2238 * LOCKING:
0cba632b 2239 * PCI/etc. bus probe sem.
1da177e4
LT		 2240 */
2241
2242static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev)
2243{
2244 DECLARE_COMPLETION(wait);
2245 struct ata_queued_cmd *qc;
2246 int rc;
2247 unsigned long flags;
2248
2249 /* set up set-features taskfile */
2250 DPRINTK("set features - xfer mode\n");
2251
2252 qc = ata_qc_new_init(ap, dev);
2253 BUG_ON(qc == NULL);
2254
2255 qc->tf.command = ATA_CMD_SET_FEATURES;
2256 qc->tf.feature = SETFEATURES_XFER;
2257 qc->tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2258 qc->tf.protocol = ATA_PROT_NODATA;
2259 qc->tf.nsect = dev->xfer_mode;
2260
2261 qc->waiting = &wait;
2262 qc->complete_fn = ata_qc_complete_noop;
2263
2264 spin_lock_irqsave(&ap->host_set->lock, flags);
2265 rc = ata_qc_issue(qc);
2266 spin_unlock_irqrestore(&ap->host_set->lock, flags);
2267
2268 if (rc)
2269 ata_port_disable(ap);
2270 else
2271 wait_for_completion(&wait);
2272
2273 DPRINTK("EXIT\n");
2274}
2275
59a10b17
AL		 2276/**
2277 * ata_dev_reread_id - Reread the device identify device info
2278 * @ap: port where the device is
2279 * @dev: device to reread the identify device info
2280 *
2281 * LOCKING:
2282 */
2283
2284static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev)
2285{
2286 DECLARE_COMPLETION(wait);
2287 struct ata_queued_cmd *qc;
2288 unsigned long flags;
2289 int rc;
2290
2291 qc = ata_qc_new_init(ap, dev);
2292 BUG_ON(qc == NULL);
2293
2294 ata_sg_init_one(qc, dev->id, sizeof(dev->id));
2295 qc->dma_dir = DMA_FROM_DEVICE;
2296
2297 if (dev->class == ATA_DEV_ATA) {
2298 qc->tf.command = ATA_CMD_ID_ATA;
2299 DPRINTK("do ATA identify\n");
2300 } else {
2301 qc->tf.command = ATA_CMD_ID_ATAPI;
2302 DPRINTK("do ATAPI identify\n");
2303 }
2304
2305 qc->tf.flags |= ATA_TFLAG_DEVICE;
2306 qc->tf.protocol = ATA_PROT_PIO;
2307 qc->nsect = 1;
2308
2309 qc->waiting = &wait;
2310 qc->complete_fn = ata_qc_complete_noop;
2311
2312 spin_lock_irqsave(&ap->host_set->lock, flags);
2313 rc = ata_qc_issue(qc);
2314 spin_unlock_irqrestore(&ap->host_set->lock, flags);
2315
2316 if (rc)
2317 goto err_out;
2318
2319 wait_for_completion(&wait);
2320
2321 swap_buf_le16(dev->id, ATA_ID_WORDS);
2322
2323 ata_dump_id(dev);
2324
2325 DPRINTK("EXIT\n");
2326
2327 return;
2328err_out:
2329 ata_port_disable(ap);
2330}
2331
8bf62ece
AL		 2332/**
2333 * ata_dev_init_params - Issue INIT DEV PARAMS command
2334 * @ap: Port associated with device @dev
2335 * @dev: Device to which command will be sent
2336 *
2337 * LOCKING:
2338 */
2339
2340static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev)
2341{
2342 DECLARE_COMPLETION(wait);
2343 struct ata_queued_cmd *qc;
2344 int rc;
2345 unsigned long flags;
2346 u16 sectors = dev->id[6];
2347 u16 heads = dev->id[3];
2348
2349 /* Number of sectors per track 1-255. Number of heads 1-16 */
2350 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
2351 return;
2352
2353 /* set up init dev params taskfile */
2354 DPRINTK("init dev params \n");
2355
2356 qc = ata_qc_new_init(ap, dev);
2357 BUG_ON(qc == NULL);
2358
2359 qc->tf.command = ATA_CMD_INIT_DEV_PARAMS;
2360 qc->tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2361 qc->tf.protocol = ATA_PROT_NODATA;
2362 qc->tf.nsect = sectors;
2363 qc->tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
2364
2365 qc->waiting = &wait;
2366 qc->complete_fn = ata_qc_complete_noop;
2367
2368 spin_lock_irqsave(&ap->host_set->lock, flags);
2369 rc = ata_qc_issue(qc);
2370 spin_unlock_irqrestore(&ap->host_set->lock, flags);
2371
2372 if (rc)
2373 ata_port_disable(ap);
2374 else
2375 wait_for_completion(&wait);
2376
2377 DPRINTK("EXIT\n");
2378}
2379
1da177e4 2380/**
0cba632b
JG		 2381 * ata_sg_clean - Unmap DMA memory associated with command
2382 * @qc: Command containing DMA memory to be released
2383 *
2384 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT		 2385 *
2386 * LOCKING:
0cba632b 2387 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2388 */
2389
2390static void ata_sg_clean(struct ata_queued_cmd *qc)
2391{
2392 struct ata_port *ap = qc->ap;
cedc9a47 2393 struct scatterlist *sg = qc->__sg;
1da177e4 2394 int dir = qc->dma_dir;
cedc9a47 2395 void *pad_buf = NULL;
1da177e4
LT		 2396
2397 assert(qc->flags & ATA_QCFLAG_DMAMAP);
2398 assert(sg != NULL);
2399
2400 if (qc->flags & ATA_QCFLAG_SINGLE)
2401 assert(qc->n_elem == 1);
2402
2403 DPRINTK("unmapping %u sg elements\n", qc->n_elem);
2404
cedc9a47
JG		 2405 /* if we padded the buffer out to 32-bit bound, and data
2406 * xfer direction is from-device, we must copy from the
2407 * pad buffer back into the supplied buffer
2408 */
2409 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
2410 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2411
2412 if (qc->flags & ATA_QCFLAG_SG) {
1da177e4 2413 dma_unmap_sg(ap->host_set->dev, sg, qc->n_elem, dir);
cedc9a47
JG		 2414 /* restore last sg */
2415 sg[qc->orig_n_elem - 1].length += qc->pad_len;
2416 if (pad_buf) {
2417 struct scatterlist *psg = &qc->pad_sgent;
2418 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2419 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
2420 kunmap_atomic(psg->page, KM_IRQ0);
2421 }
2422 } else {
1da177e4
LT		 2423 dma_unmap_single(ap->host_set->dev, sg_dma_address(&sg[0]),
2424 sg_dma_len(&sg[0]), dir);
cedc9a47
JG		 2425 /* restore sg */
2426 sg->length += qc->pad_len;
2427 if (pad_buf)
2428 memcpy(qc->buf_virt + sg->length - qc->pad_len,
2429 pad_buf, qc->pad_len);
2430 }
1da177e4
LT		 2431
2432 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 2433 qc->__sg = NULL;
1da177e4
LT		 2434}
2435
2436/**
2437 * ata_fill_sg - Fill PCI IDE PRD table
2438 * @qc: Metadata associated with taskfile to be transferred
2439 *
780a87f7
JG		 2440 * Fill PCI IDE PRD (scatter-gather) table with segments
2441 * associated with the current disk command.
2442 *
1da177e4 2443 * LOCKING:
780a87f7 2444 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2445 *
2446 */
2447static void ata_fill_sg(struct ata_queued_cmd *qc)
2448{
1da177e4 2449 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2450 struct scatterlist *sg;
2451 unsigned int idx;
1da177e4 2452
cedc9a47 2453 assert(qc->__sg != NULL);
1da177e4
LT		 2454 assert(qc->n_elem > 0);
2455
2456 idx = 0;
cedc9a47 2457 ata_for_each_sg(sg, qc) {
1da177e4
LT		 2458 u32 addr, offset;
2459 u32 sg_len, len;
2460
2461 /* determine if physical DMA addr spans 64K boundary.
2462 * Note h/w doesn't support 64-bit, so we unconditionally
2463 * truncate dma_addr_t to u32.
2464 */
2465 addr = (u32) sg_dma_address(sg);
2466 sg_len = sg_dma_len(sg);
2467
2468 while (sg_len) {
2469 offset = addr & 0xffff;
2470 len = sg_len;
2471 if ((offset + sg_len) > 0x10000)
2472 len = 0x10000 - offset;
2473
2474 ap->prd[idx].addr = cpu_to_le32(addr);
2475 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
2476 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
2477
2478 idx++;
2479 sg_len -= len;
2480 addr += len;
2481 }
2482 }
2483
2484 if (idx)
2485 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2486}
2487/**
2488 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
2489 * @qc: Metadata associated with taskfile to check
2490 *
780a87f7
JG		 2491 * Allow low-level driver to filter ATA PACKET commands, returning
2492 * a status indicating whether or not it is OK to use DMA for the
2493 * supplied PACKET command.
2494 *
1da177e4 2495 * LOCKING:
0cba632b
JG		 2496 * spin_lock_irqsave(host_set lock)
2497 *
1da177e4
LT		 2498 * RETURNS: 0 when ATAPI DMA can be used
2499 * nonzero otherwise
2500 */
2501int ata_check_atapi_dma(struct ata_queued_cmd *qc)
2502{
2503 struct ata_port *ap = qc->ap;
2504 int rc = 0; /* Assume ATAPI DMA is OK by default */
2505
2506 if (ap->ops->check_atapi_dma)
2507 rc = ap->ops->check_atapi_dma(qc);
2508
2509 return rc;
2510}
2511/**
2512 * ata_qc_prep - Prepare taskfile for submission
2513 * @qc: Metadata associated with taskfile to be prepared
2514 *
780a87f7
JG		 2515 * Prepare ATA taskfile for submission.
2516 *
1da177e4
LT		 2517 * LOCKING:
2518 * spin_lock_irqsave(host_set lock)
2519 */
2520void ata_qc_prep(struct ata_queued_cmd *qc)
2521{
2522 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2523 return;
2524
2525 ata_fill_sg(qc);
2526}
2527
0cba632b
JG		 2528/**
2529 * ata_sg_init_one - Associate command with memory buffer
2530 * @qc: Command to be associated
2531 * @buf: Memory buffer
2532 * @buflen: Length of memory buffer, in bytes.
2533 *
2534 * Initialize the data-related elements of queued_cmd @qc
2535 * to point to a single memory buffer, @buf of byte length @buflen.
2536 *
2537 * LOCKING:
2538 * spin_lock_irqsave(host_set lock)
2539 */
2540
1da177e4
LT		 2541void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
2542{
2543 struct scatterlist *sg;
2544
2545 qc->flags |= ATA_QCFLAG_SINGLE;
2546
2547 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 2548 qc->__sg = &qc->sgent;
1da177e4 2549 qc->n_elem = 1;
cedc9a47 2550 qc->orig_n_elem = 1;
1da177e4
LT		 2551 qc->buf_virt = buf;
2552
cedc9a47 2553 sg = qc->__sg;
f0612bbc 2554 sg_init_one(sg, buf, buflen);
1da177e4
LT		 2555}
2556
0cba632b
JG		 2557/**
2558 * ata_sg_init - Associate command with scatter-gather table.
2559 * @qc: Command to be associated
2560 * @sg: Scatter-gather table.
2561 * @n_elem: Number of elements in s/g table.
2562 *
2563 * Initialize the data-related elements of queued_cmd @qc
2564 * to point to a scatter-gather table @sg, containing @n_elem
2565 * elements.
2566 *
2567 * LOCKING:
2568 * spin_lock_irqsave(host_set lock)
2569 */
2570
1da177e4
LT		 2571void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
2572 unsigned int n_elem)
2573{
2574 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 2575 qc->__sg = sg;
1da177e4 2576 qc->n_elem = n_elem;
cedc9a47 2577 qc->orig_n_elem = n_elem;
1da177e4
LT		 2578}
2579
2580/**
0cba632b
JG		 2581 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
2582 * @qc: Command with memory buffer to be mapped.
2583 *
2584 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT		 2585 *
2586 * LOCKING:
2587 * spin_lock_irqsave(host_set lock)
2588 *
2589 * RETURNS:
0cba632b 2590 * Zero on success, negative on error.
1da177e4
LT		 2591 */
2592
2593static int ata_sg_setup_one(struct ata_queued_cmd *qc)
2594{
2595 struct ata_port *ap = qc->ap;
2596 int dir = qc->dma_dir;
cedc9a47 2597 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 2598 dma_addr_t dma_address;
2599
cedc9a47
JG		 2600 /* we must lengthen transfers to end on a 32-bit boundary */
2601 qc->pad_len = sg->length & 3;
2602 if (qc->pad_len) {
2603 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2604 struct scatterlist *psg = &qc->pad_sgent;
2605
2606 assert(qc->dev->class == ATA_DEV_ATAPI);
2607
2608 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2609
2610 if (qc->tf.flags & ATA_TFLAG_WRITE)
2611 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
2612 qc->pad_len);
2613
2614 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2615 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2616 /* trim sg */
2617 sg->length -= qc->pad_len;
2618
2619 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
2620 sg->length, qc->pad_len);
2621 }
2622
1da177e4 2623 dma_address = dma_map_single(ap->host_set->dev, qc->buf_virt,
32529e01 2624 sg->length, dir);
1da177e4
LT		 2625 if (dma_mapping_error(dma_address))
2626 return -1;
2627
2628 sg_dma_address(sg) = dma_address;
32529e01 2629 sg_dma_len(sg) = sg->length;
1da177e4
LT		 2630
2631 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
2632 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
2633
2634 return 0;
2635}
2636
2637/**
0cba632b
JG		 2638 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
2639 * @qc: Command with scatter-gather table to be mapped.
2640 *
2641 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT		 2642 *
2643 * LOCKING:
2644 * spin_lock_irqsave(host_set lock)
2645 *
2646 * RETURNS:
0cba632b 2647 * Zero on success, negative on error.
1da177e4
LT		 2648 *
2649 */
2650
2651static int ata_sg_setup(struct ata_queued_cmd *qc)
2652{
2653 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2654 struct scatterlist *sg = qc->__sg;
2655 struct scatterlist *lsg = &sg[qc->n_elem - 1];
1da177e4
LT		 2656 int n_elem, dir;
2657
2658 VPRINTK("ENTER, ata%u\n", ap->id);
2659 assert(qc->flags & ATA_QCFLAG_SG);
2660
cedc9a47
JG		 2661 /* we must lengthen transfers to end on a 32-bit boundary */
2662 qc->pad_len = lsg->length & 3;
2663 if (qc->pad_len) {
2664 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2665 struct scatterlist *psg = &qc->pad_sgent;
2666 unsigned int offset;
2667
2668 assert(qc->dev->class == ATA_DEV_ATAPI);
2669
2670 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2671
2672 /*
2673 * psg->page/offset are used to copy to-be-written
2674 * data in this function or read data in ata_sg_clean.
2675 */
2676 offset = lsg->offset + lsg->length - qc->pad_len;
2677 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
2678 psg->offset = offset_in_page(offset);
2679
2680 if (qc->tf.flags & ATA_TFLAG_WRITE) {
2681 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2682 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
2683 kunmap_atomic(psg->page, KM_IRQ0);
2684 }
2685
2686 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2687 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2688 /* trim last sg */
2689 lsg->length -= qc->pad_len;
2690
2691 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
2692 qc->n_elem - 1, lsg->length, qc->pad_len);
2693 }
2694
1da177e4
LT		 2695 dir = qc->dma_dir;
2696 n_elem = dma_map_sg(ap->host_set->dev, sg, qc->n_elem, dir);
2697 if (n_elem < 1)
2698 return -1;
2699
2700 DPRINTK("%d sg elements mapped\n", n_elem);
2701
2702 qc->n_elem = n_elem;
2703
2704 return 0;
2705}
2706
40e8c82c
TH		 2707/**
2708 * ata_poll_qc_complete - turn irq back on and finish qc
2709 * @qc: Command to complete
2710 * @drv_stat: ATA status register content
2711 *
2712 * LOCKING:
2713 * None. (grabs host lock)
2714 */
2715
a7dac447 2716void ata_poll_qc_complete(struct ata_queued_cmd *qc, unsigned int err_mask)
40e8c82c
TH		 2717{
2718 struct ata_port *ap = qc->ap;
b8f6153e 2719 unsigned long flags;
40e8c82c 2720
b8f6153e 2721 spin_lock_irqsave(&ap->host_set->lock, flags);
40e8c82c
TH		 2722 ap->flags &= ~ATA_FLAG_NOINTR;
2723 ata_irq_on(ap);
a7dac447 2724 ata_qc_complete(qc, err_mask);
b8f6153e 2725 spin_unlock_irqrestore(&ap->host_set->lock, flags);
40e8c82c
TH		 2726}
2727
1da177e4
LT		 2728/**
2729 * ata_pio_poll -
6f0ef4fa 2730 * @ap: the target ata_port
1da177e4
LT		 2731 *
2732 * LOCKING:
0cba632b 2733 * None. (executing in kernel thread context)
1da177e4
LT		 2734 *
2735 * RETURNS:
6f0ef4fa 2736 * timeout value to use
1da177e4
LT		 2737 */
2738
2739static unsigned long ata_pio_poll(struct ata_port *ap)
2740{
2741 u8 status;
14be71f4
AL		 2742 unsigned int poll_state = HSM_ST_UNKNOWN;
2743 unsigned int reg_state = HSM_ST_UNKNOWN;
2744 const unsigned int tmout_state = HSM_ST_TMOUT;
2745
2746 switch (ap->hsm_task_state) {
2747 case HSM_ST:
2748 case HSM_ST_POLL:
2749 poll_state = HSM_ST_POLL;
2750 reg_state = HSM_ST;
1da177e4 2751 break;
14be71f4
AL		 2752 case HSM_ST_LAST:
2753 case HSM_ST_LAST_POLL:
2754 poll_state = HSM_ST_LAST_POLL;
2755 reg_state = HSM_ST_LAST;
1da177e4
LT		 2756 break;
2757 default:
2758 BUG();
2759 break;
2760 }
2761
2762 status = ata_chk_status(ap);
2763 if (status & ATA_BUSY) {
2764 if (time_after(jiffies, ap->pio_task_timeout)) {
14be71f4 2765 ap->hsm_task_state = tmout_state;
1da177e4
LT		 2766 return 0;
2767 }
14be71f4 2768 ap->hsm_task_state = poll_state;
1da177e4
LT		 2769 return ATA_SHORT_PAUSE;
2770 }
2771
14be71f4 2772 ap->hsm_task_state = reg_state;
1da177e4
LT		 2773 return 0;
2774}
2775
2776/**
6f0ef4fa
RD		 2777 * ata_pio_complete - check if drive is busy or idle
2778 * @ap: the target ata_port
1da177e4
LT		 2779 *
2780 * LOCKING:
0cba632b 2781 * None. (executing in kernel thread context)
7fb6ec28
JG		 2782 *
2783 * RETURNS:
2784 * Non-zero if qc completed, zero otherwise.
1da177e4
LT		 2785 */
2786
7fb6ec28 2787static int ata_pio_complete (struct ata_port *ap)
1da177e4
LT		 2788{
2789 struct ata_queued_cmd *qc;
2790 u8 drv_stat;
2791
2792 /*
31433ea3
AC		 2793 * This is purely heuristic. This is a fast path. Sometimes when
2794 * we enter, BSY will be cleared in a chk-status or two. If not,
2795 * the drive is probably seeking or something. Snooze for a couple
2796 * msecs, then chk-status again. If still busy, fall back to
14be71f4 2797 * HSM_ST_POLL state.
1da177e4
LT		 2798 */
2799 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 10);
2800 if (drv_stat & (ATA_BUSY | ATA_DRQ)) {
2801 msleep(2);
2802 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 10);
2803 if (drv_stat & (ATA_BUSY | ATA_DRQ)) {
14be71f4 2804 ap->hsm_task_state = HSM_ST_LAST_POLL;
1da177e4 2805 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
7fb6ec28 2806 return 0;
1da177e4
LT		 2807 }
2808 }
2809
2810 drv_stat = ata_wait_idle(ap);
2811 if (!ata_ok(drv_stat)) {
14be71f4 2812 ap->hsm_task_state = HSM_ST_ERR;
7fb6ec28 2813 return 0;
1da177e4
LT		 2814 }
2815
2816 qc = ata_qc_from_tag(ap, ap->active_tag);
2817 assert(qc != NULL);
2818
14be71f4 2819 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 2820
a7dac447 2821 ata_poll_qc_complete(qc, 0);
7fb6ec28
JG		 2822
2823 /* another command may start at this point */
2824
2825 return 1;
1da177e4
LT		 2826}
2827
0baab86b
EF		 2828
2829/**
6f0ef4fa 2830 * swap_buf_le16 - swap halves of 16-words in place
0baab86b
EF		 2831 * @buf: Buffer to swap
2832 * @buf_words: Number of 16-bit words in buffer.
2833 *
2834 * Swap halves of 16-bit words if needed to convert from
2835 * little-endian byte order to native cpu byte order, or
2836 * vice-versa.
2837 *
2838 * LOCKING:
6f0ef4fa 2839 * Inherited from caller.
0baab86b 2840 */
1da177e4
LT		 2841void swap_buf_le16(u16 *buf, unsigned int buf_words)
2842{
2843#ifdef __BIG_ENDIAN
2844 unsigned int i;
2845
2846 for (i = 0; i < buf_words; i++)
2847 buf[i] = le16_to_cpu(buf[i]);
2848#endif /* __BIG_ENDIAN */
2849}
2850
6ae4cfb5
AL		 2851/**
2852 * ata_mmio_data_xfer - Transfer data by MMIO
2853 * @ap: port to read/write
2854 * @buf: data buffer
2855 * @buflen: buffer length
344babaa 2856 * @write_data: read/write
6ae4cfb5
AL		 2857 *
2858 * Transfer data from/to the device data register by MMIO.
2859 *
2860 * LOCKING:
2861 * Inherited from caller.
6ae4cfb5
AL		 2862 */
2863
1da177e4
LT		 2864static void ata_mmio_data_xfer(struct ata_port *ap, unsigned char *buf,
2865 unsigned int buflen, int write_data)
2866{
2867 unsigned int i;
2868 unsigned int words = buflen >> 1;
2869 u16 *buf16 = (u16 *) buf;
2870 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
2871
6ae4cfb5 2872 /* Transfer multiple of 2 bytes */
1da177e4
LT		 2873 if (write_data) {
2874 for (i = 0; i < words; i++)
2875 writew(le16_to_cpu(buf16[i]), mmio);
2876 } else {
2877 for (i = 0; i < words; i++)
2878 buf16[i] = cpu_to_le16(readw(mmio));
2879 }
6ae4cfb5
AL		 2880
2881 /* Transfer trailing 1 byte, if any. */
2882 if (unlikely(buflen & 0x01)) {
2883 u16 align_buf[1] = { 0 };
2884 unsigned char *trailing_buf = buf + buflen - 1;
2885
2886 if (write_data) {
2887 memcpy(align_buf, trailing_buf, 1);
2888 writew(le16_to_cpu(align_buf[0]), mmio);
2889 } else {
2890 align_buf[0] = cpu_to_le16(readw(mmio));
2891 memcpy(trailing_buf, align_buf, 1);
2892 }
2893 }
1da177e4
LT		 2894}
2895
6ae4cfb5
AL		 2896/**
2897 * ata_pio_data_xfer - Transfer data by PIO
2898 * @ap: port to read/write
2899 * @buf: data buffer
2900 * @buflen: buffer length
344babaa 2901 * @write_data: read/write
6ae4cfb5
AL		 2902 *
2903 * Transfer data from/to the device data register by PIO.
2904 *
2905 * LOCKING:
2906 * Inherited from caller.
6ae4cfb5
AL		 2907 */
2908
1da177e4
LT		 2909static void ata_pio_data_xfer(struct ata_port *ap, unsigned char *buf,
2910 unsigned int buflen, int write_data)
2911{
6ae4cfb5 2912 unsigned int words = buflen >> 1;
1da177e4 2913
6ae4cfb5 2914 /* Transfer multiple of 2 bytes */
1da177e4 2915 if (write_data)
6ae4cfb5 2916 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 2917 else
6ae4cfb5
AL		 2918 insw(ap->ioaddr.data_addr, buf, words);
2919
2920 /* Transfer trailing 1 byte, if any. */
2921 if (unlikely(buflen & 0x01)) {
2922 u16 align_buf[1] = { 0 };
2923 unsigned char *trailing_buf = buf + buflen - 1;
2924
2925 if (write_data) {
2926 memcpy(align_buf, trailing_buf, 1);
2927 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
2928 } else {
2929 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
2930 memcpy(trailing_buf, align_buf, 1);
2931 }
2932 }
1da177e4
LT		 2933}
2934
6ae4cfb5
AL		 2935/**
2936 * ata_data_xfer - Transfer data from/to the data register.
2937 * @ap: port to read/write
2938 * @buf: data buffer
2939 * @buflen: buffer length
2940 * @do_write: read/write
2941 *
2942 * Transfer data from/to the device data register.
2943 *
2944 * LOCKING:
2945 * Inherited from caller.
6ae4cfb5
AL		 2946 */
2947
1da177e4
LT		 2948static void ata_data_xfer(struct ata_port *ap, unsigned char *buf,
2949 unsigned int buflen, int do_write)
2950{
2951 if (ap->flags & ATA_FLAG_MMIO)
2952 ata_mmio_data_xfer(ap, buf, buflen, do_write);
2953 else
2954 ata_pio_data_xfer(ap, buf, buflen, do_write);
2955}
2956
6ae4cfb5
AL		 2957/**
2958 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
2959 * @qc: Command on going
2960 *
2961 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
2962 *
2963 * LOCKING:
2964 * Inherited from caller.
2965 */
2966
1da177e4
LT		 2967static void ata_pio_sector(struct ata_queued_cmd *qc)
2968{
2969 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 2970 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 2971 struct ata_port *ap = qc->ap;
2972 struct page *page;
2973 unsigned int offset;
2974 unsigned char *buf;
2975
2976 if (qc->cursect == (qc->nsect - 1))
14be71f4 2977 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 2978
2979 page = sg[qc->cursg].page;
2980 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
2981
2982 /* get the current page and offset */
2983 page = nth_page(page, (offset >> PAGE_SHIFT));
2984 offset %= PAGE_SIZE;
2985
2986 buf = kmap(page) + offset;
2987
2988 qc->cursect++;
2989 qc->cursg_ofs++;
2990
32529e01 2991 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
1da177e4
LT		 2992 qc->cursg++;
2993 qc->cursg_ofs = 0;
2994 }
2995
2996 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
2997
2998 /* do the actual data transfer */
2999 do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
3000 ata_data_xfer(ap, buf, ATA_SECT_SIZE, do_write);
3001
3002 kunmap(page);
3003}
3004
6ae4cfb5
AL		 3005/**
3006 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3007 * @qc: Command on going
3008 * @bytes: number of bytes
3009 *
3010 * Transfer Transfer data from/to the ATAPI device.
3011 *
3012 * LOCKING:
3013 * Inherited from caller.
3014 *
3015 */
3016
1da177e4
LT		 3017static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3018{
3019 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3020 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3021 struct ata_port *ap = qc->ap;
3022 struct page *page;
3023 unsigned char *buf;
3024 unsigned int offset, count;
3025
563a6e1f 3026 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3027 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3028
3029next_sg:
563a6e1f 3030 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3031 /*
563a6e1f
AL		 3032 * The end of qc->sg is reached and the device expects
3033 * more data to transfer. In order not to overrun qc->sg
3034 * and fulfill length specified in the byte count register,
3035 * - for read case, discard trailing data from the device
3036 * - for write case, padding zero data to the device
3037 */
3038 u16 pad_buf[1] = { 0 };
3039 unsigned int words = bytes >> 1;
3040 unsigned int i;
3041
3042 if (words) /* warning if bytes > 1 */
7fb6ec28 3043 printk(KERN_WARNING "ata%u: %u bytes trailing data\n",
563a6e1f
AL		 3044 ap->id, bytes);
3045
3046 for (i = 0; i < words; i++)
3047 ata_data_xfer(ap, (unsigned char*)pad_buf, 2, do_write);
3048
14be71f4 3049 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL		 3050 return;
3051 }
3052
cedc9a47 3053 sg = &qc->__sg[qc->cursg];
1da177e4 3054
1da177e4
LT		 3055 page = sg->page;
3056 offset = sg->offset + qc->cursg_ofs;
3057
3058 /* get the current page and offset */
3059 page = nth_page(page, (offset >> PAGE_SHIFT));
3060 offset %= PAGE_SIZE;
3061
6952df03 3062 /* don't overrun current sg */
32529e01 3063 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT		 3064
3065 /* don't cross page boundaries */
3066 count = min(count, (unsigned int)PAGE_SIZE - offset);
3067
3068 buf = kmap(page) + offset;
3069
3070 bytes -= count;
3071 qc->curbytes += count;
3072 qc->cursg_ofs += count;
3073
32529e01 3074 if (qc->cursg_ofs == sg->length) {
1da177e4
LT		 3075 qc->cursg++;
3076 qc->cursg_ofs = 0;
3077 }
3078
3079 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3080
3081 /* do the actual data transfer */
3082 ata_data_xfer(ap, buf, count, do_write);
3083
3084 kunmap(page);
3085
563a6e1f 3086 if (bytes)
1da177e4 3087 goto next_sg;
1da177e4
LT		 3088}
3089
6ae4cfb5
AL		 3090/**
3091 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
3092 * @qc: Command on going
3093 *
3094 * Transfer Transfer data from/to the ATAPI device.
3095 *
3096 * LOCKING:
3097 * Inherited from caller.
6ae4cfb5
AL		 3098 */
3099
1da177e4
LT		 3100static void atapi_pio_bytes(struct ata_queued_cmd *qc)
3101{
3102 struct ata_port *ap = qc->ap;
3103 struct ata_device *dev = qc->dev;
3104 unsigned int ireason, bc_lo, bc_hi, bytes;
3105 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
3106
3107 ap->ops->tf_read(ap, &qc->tf);
3108 ireason = qc->tf.nsect;
3109 bc_lo = qc->tf.lbam;
3110 bc_hi = qc->tf.lbah;
3111 bytes = (bc_hi << 8) | bc_lo;
3112
3113 /* shall be cleared to zero, indicating xfer of data */
3114 if (ireason & (1 << 0))
3115 goto err_out;
3116
3117 /* make sure transfer direction matches expected */
3118 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
3119 if (do_write != i_write)
3120 goto err_out;
3121
3122 __atapi_pio_bytes(qc, bytes);
3123
3124 return;
3125
3126err_out:
3127 printk(KERN_INFO "ata%u: dev %u: ATAPI check failed\n",
3128 ap->id, dev->devno);
14be71f4 3129 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3130}
3131
3132/**
6f0ef4fa
RD		 3133 * ata_pio_block - start PIO on a block
3134 * @ap: the target ata_port
1da177e4
LT		 3135 *
3136 * LOCKING:
0cba632b 3137 * None. (executing in kernel thread context)
1da177e4
LT		 3138 */
3139
3140static void ata_pio_block(struct ata_port *ap)
3141{
3142 struct ata_queued_cmd *qc;
3143 u8 status;
3144
3145 /*
6f0ef4fa 3146 * This is purely heuristic. This is a fast path.
1da177e4
LT		 3147 * Sometimes when we enter, BSY will be cleared in
3148 * a chk-status or two. If not, the drive is probably seeking
3149 * or something. Snooze for a couple msecs, then
3150 * chk-status again. If still busy, fall back to
14be71f4 3151 * HSM_ST_POLL state.
1da177e4
LT		 3152 */
3153 status = ata_busy_wait(ap, ATA_BUSY, 5);
3154 if (status & ATA_BUSY) {
3155 msleep(2);
3156 status = ata_busy_wait(ap, ATA_BUSY, 10);
3157 if (status & ATA_BUSY) {
14be71f4 3158 ap->hsm_task_state = HSM_ST_POLL;
1da177e4
LT		 3159 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
3160 return;
3161 }
3162 }
3163
3164 qc = ata_qc_from_tag(ap, ap->active_tag);
3165 assert(qc != NULL);
3166
3167 if (is_atapi_taskfile(&qc->tf)) {
3168 /* no more data to transfer or unsupported ATAPI command */
3169 if ((status & ATA_DRQ) == 0) {
14be71f4 3170 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3171 return;
3172 }
3173
3174 atapi_pio_bytes(qc);
3175 } else {
3176 /* handle BSY=0, DRQ=0 as error */
3177 if ((status & ATA_DRQ) == 0) {
14be71f4 3178 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3179 return;
3180 }
3181
3182 ata_pio_sector(qc);
3183 }
3184}
3185
3186static void ata_pio_error(struct ata_port *ap)
3187{
3188 struct ata_queued_cmd *qc;
a7dac447
JG		 3189
3190 printk(KERN_WARNING "ata%u: PIO error\n", ap->id);
1da177e4
LT		 3191
3192 qc = ata_qc_from_tag(ap, ap->active_tag);
3193 assert(qc != NULL);
3194
14be71f4 3195 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3196
a7dac447 3197 ata_poll_qc_complete(qc, AC_ERR_ATA_BUS);
1da177e4
LT		 3198}
3199
3200static void ata_pio_task(void *_data)
3201{
3202 struct ata_port *ap = _data;
7fb6ec28
JG		 3203 unsigned long timeout;
3204 int qc_completed;
3205
3206fsm_start:
3207 timeout = 0;
3208 qc_completed = 0;
1da177e4 3209
14be71f4
AL		 3210 switch (ap->hsm_task_state) {
3211 case HSM_ST_IDLE:
1da177e4
LT		 3212 return;
3213
14be71f4 3214 case HSM_ST:
1da177e4
LT		 3215 ata_pio_block(ap);
3216 break;
3217
14be71f4 3218 case HSM_ST_LAST:
7fb6ec28 3219 qc_completed = ata_pio_complete(ap);
1da177e4
LT		 3220 break;
3221
14be71f4
AL		 3222 case HSM_ST_POLL:
3223 case HSM_ST_LAST_POLL:
1da177e4
LT		 3224 timeout = ata_pio_poll(ap);
3225 break;
3226
14be71f4
AL		 3227 case HSM_ST_TMOUT:
3228 case HSM_ST_ERR:
1da177e4
LT		 3229 ata_pio_error(ap);
3230 return;
3231 }
3232
3233 if (timeout)
7fb6ec28
JG		 3234 queue_delayed_work(ata_wq, &ap->pio_task, timeout);
3235 else if (!qc_completed)
3236 goto fsm_start;
1da177e4
LT		 3237}
3238
1da177e4
LT		 3239/**
3240 * ata_qc_timeout - Handle timeout of queued command
3241 * @qc: Command that timed out
3242 *
3243 * Some part of the kernel (currently, only the SCSI layer)
3244 * has noticed that the active command on port @ap has not
3245 * completed after a specified length of time. Handle this
3246 * condition by disabling DMA (if necessary) and completing
3247 * transactions, with error if necessary.
3248 *
3249 * This also handles the case of the "lost interrupt", where
3250 * for some reason (possibly hardware bug, possibly driver bug)
3251 * an interrupt was not delivered to the driver, even though the
3252 * transaction completed successfully.
3253 *
3254 * LOCKING:
0cba632b 3255 * Inherited from SCSI layer (none, can sleep)
1da177e4
LT		 3256 */
3257
3258static void ata_qc_timeout(struct ata_queued_cmd *qc)
3259{
3260 struct ata_port *ap = qc->ap;
b8f6153e 3261 struct ata_host_set *host_set = ap->host_set;
1da177e4
LT		 3262 struct ata_device *dev = qc->dev;
3263 u8 host_stat = 0, drv_stat;
b8f6153e 3264 unsigned long flags;
1da177e4
LT		 3265
3266 DPRINTK("ENTER\n");
3267
3268 /* FIXME: doesn't this conflict with timeout handling? */
3269 if (qc->dev->class == ATA_DEV_ATAPI && qc->scsicmd) {
3270 struct scsi_cmnd *cmd = qc->scsicmd;
3271
3111b0d1 3272 if (!(cmd->eh_eflags & SCSI_EH_CANCEL_CMD)) {
1da177e4
LT		 3273
3274 /* finish completing original command */
b8f6153e 3275 spin_lock_irqsave(&host_set->lock, flags);
1da177e4 3276 __ata_qc_complete(qc);
b8f6153e 3277 spin_unlock_irqrestore(&host_set->lock, flags);
1da177e4
LT		 3278
3279 atapi_request_sense(ap, dev, cmd);
3280
3281 cmd->result = (CHECK_CONDITION << 1) | (DID_OK << 16);
3282 scsi_finish_command(cmd);
3283
3284 goto out;
3285 }
3286 }
3287
b8f6153e
JG		 3288 spin_lock_irqsave(&host_set->lock, flags);
3289
1da177e4
LT		 3290 /* hack alert! We cannot use the supplied completion
3291 * function from inside the ->eh_strategy_handler() thread.
3292 * libata is the only user of ->eh_strategy_handler() in
3293 * any kernel, so the default scsi_done() assumes it is
3294 * not being called from the SCSI EH.
3295 */
3296 qc->scsidone = scsi_finish_command;
3297
3298 switch (qc->tf.protocol) {
3299
3300 case ATA_PROT_DMA:
3301 case ATA_PROT_ATAPI_DMA:
3302 host_stat = ap->ops->bmdma_status(ap);
3303
3304 /* before we do anything else, clear DMA-Start bit */
b73fc89f 3305 ap->ops->bmdma_stop(qc);
1da177e4
LT		 3306
3307 /* fall through */
3308
3309 default:
3310 ata_altstatus(ap);
3311 drv_stat = ata_chk_status(ap);
3312
3313 /* ack bmdma irq events */
3314 ap->ops->irq_clear(ap);
3315
3316 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x host_stat 0x%x\n",
3317 ap->id, qc->tf.command, drv_stat, host_stat);
3318
3319 /* complete taskfile transaction */
a7dac447 3320 ata_qc_complete(qc, ac_err_mask(drv_stat));
1da177e4
LT		 3321 break;
3322 }
b8f6153e
JG		 3323
3324 spin_unlock_irqrestore(&host_set->lock, flags);
3325
1da177e4
LT		 3326out:
3327 DPRINTK("EXIT\n");
3328}
3329
3330/**
3331 * ata_eng_timeout - Handle timeout of queued command
3332 * @ap: Port on which timed-out command is active
3333 *
3334 * Some part of the kernel (currently, only the SCSI layer)
3335 * has noticed that the active command on port @ap has not
3336 * completed after a specified length of time. Handle this
3337 * condition by disabling DMA (if necessary) and completing
3338 * transactions, with error if necessary.
3339 *
3340 * This also handles the case of the "lost interrupt", where
3341 * for some reason (possibly hardware bug, possibly driver bug)
3342 * an interrupt was not delivered to the driver, even though the
3343 * transaction completed successfully.
3344 *
3345 * LOCKING:
3346 * Inherited from SCSI layer (none, can sleep)
3347 */
3348
3349void ata_eng_timeout(struct ata_port *ap)
3350{
3351 struct ata_queued_cmd *qc;
3352
3353 DPRINTK("ENTER\n");
3354
3355 qc = ata_qc_from_tag(ap, ap->active_tag);
e12669e7
JG		 3356 if (qc)
3357 ata_qc_timeout(qc);
3358 else {
1da177e4
LT		 3359 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
3360 ap->id);
3361 goto out;
3362 }
3363
1da177e4
LT		 3364out:
3365 DPRINTK("EXIT\n");
3366}
3367
3368/**
3369 * ata_qc_new - Request an available ATA command, for queueing
3370 * @ap: Port associated with device @dev
3371 * @dev: Device from whom we request an available command structure
3372 *
3373 * LOCKING:
0cba632b 3374 * None.
1da177e4
LT		 3375 */
3376
3377static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
3378{
3379 struct ata_queued_cmd *qc = NULL;
3380 unsigned int i;
3381
3382 for (i = 0; i < ATA_MAX_QUEUE; i++)
3383 if (!test_and_set_bit(i, &ap->qactive)) {
3384 qc = ata_qc_from_tag(ap, i);
3385 break;
3386 }
3387
3388 if (qc)
3389 qc->tag = i;
3390
3391 return qc;
3392}
3393
3394/**
3395 * ata_qc_new_init - Request an available ATA command, and initialize it
3396 * @ap: Port associated with device @dev
3397 * @dev: Device from whom we request an available command structure
3398 *
3399 * LOCKING:
0cba632b 3400 * None.
1da177e4
LT		 3401 */
3402
3403struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap,
3404 struct ata_device *dev)
3405{
3406 struct ata_queued_cmd *qc;
3407
3408 qc = ata_qc_new(ap);
3409 if (qc) {
cedc9a47 3410 qc->__sg = NULL;
1da177e4
LT		 3411 qc->flags = 0;
3412 qc->scsicmd = NULL;
3413 qc->ap = ap;
3414 qc->dev = dev;
3415 qc->cursect = qc->cursg = qc->cursg_ofs = 0;
3416 qc->nsect = 0;
3417 qc->nbytes = qc->curbytes = 0;
3418
3419 ata_tf_init(ap, &qc->tf, dev->devno);
1da177e4
LT		 3420 }
3421
3422 return qc;
3423}
3424
a7dac447 3425int ata_qc_complete_noop(struct ata_queued_cmd *qc, unsigned int err_mask)
1da177e4
LT		 3426{
3427 return 0;
3428}
3429
3430static void __ata_qc_complete(struct ata_queued_cmd *qc)
3431{
3432 struct ata_port *ap = qc->ap;
3433 unsigned int tag, do_clear = 0;
3434
3435 qc->flags = 0;
3436 tag = qc->tag;
3437 if (likely(ata_tag_valid(tag))) {
3438 if (tag == ap->active_tag)
3439 ap->active_tag = ATA_TAG_POISON;
3440 qc->tag = ATA_TAG_POISON;
3441 do_clear = 1;
3442 }
3443
3444 if (qc->waiting) {
3445 struct completion *waiting = qc->waiting;
3446 qc->waiting = NULL;
3447 complete(waiting);
3448 }
3449
3450 if (likely(do_clear))
3451 clear_bit(tag, &ap->qactive);
3452}
3453
3454/**
3455 * ata_qc_free - free unused ata_queued_cmd
3456 * @qc: Command to complete
3457 *
3458 * Designed to free unused ata_queued_cmd object
3459 * in case something prevents using it.
3460 *
3461 * LOCKING:
0cba632b 3462 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3463 */
3464void ata_qc_free(struct ata_queued_cmd *qc)
3465{
3466 assert(qc != NULL); /* ata_qc_from_tag _might_ return NULL */
3467 assert(qc->waiting == NULL); /* nothing should be waiting */
3468
3469 __ata_qc_complete(qc);
3470}
3471
3472/**
3473 * ata_qc_complete - Complete an active ATA command
3474 * @qc: Command to complete
0cba632b
JG		 3475 * @drv_stat: ATA Status register contents
3476 *
3477 * Indicate to the mid and upper layers that an ATA
3478 * command has completed, with either an ok or not-ok status.
1da177e4
LT		 3479 *
3480 * LOCKING:
0cba632b 3481 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3482 */
3483
a7dac447 3484void ata_qc_complete(struct ata_queued_cmd *qc, unsigned int err_mask)
1da177e4
LT		 3485{
3486 int rc;
3487
3488 assert(qc != NULL); /* ata_qc_from_tag _might_ return NULL */
3489 assert(qc->flags & ATA_QCFLAG_ACTIVE);
3490
3491 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
3492 ata_sg_clean(qc);
3493
3f3791d3
AL		 3494 /* atapi: mark qc as inactive to prevent the interrupt handler
3495 * from completing the command twice later, before the error handler
3496 * is called. (when rc != 0 and atapi request sense is needed)
3497 */
3498 qc->flags &= ~ATA_QCFLAG_ACTIVE;
3499
1da177e4 3500 /* call completion callback */
a7dac447 3501 rc = qc->complete_fn(qc, err_mask);
1da177e4
LT		 3502
3503 /* if callback indicates not to complete command (non-zero),
3504 * return immediately
3505 */
3506 if (rc != 0)
3507 return;
3508
3509 __ata_qc_complete(qc);
3510
3511 VPRINTK("EXIT\n");
3512}
3513
3514static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
3515{
3516 struct ata_port *ap = qc->ap;
3517
3518 switch (qc->tf.protocol) {
3519 case ATA_PROT_DMA:
3520 case ATA_PROT_ATAPI_DMA:
3521 return 1;
3522
3523 case ATA_PROT_ATAPI:
3524 case ATA_PROT_PIO:
3525 case ATA_PROT_PIO_MULT:
3526 if (ap->flags & ATA_FLAG_PIO_DMA)
3527 return 1;
3528
3529 /* fall through */
3530
3531 default:
3532 return 0;
3533 }
3534
3535 /* never reached */
3536}
3537
3538/**
3539 * ata_qc_issue - issue taskfile to device
3540 * @qc: command to issue to device
3541 *
3542 * Prepare an ATA command to submission to device.
3543 * This includes mapping the data into a DMA-able
3544 * area, filling in the S/G table, and finally
3545 * writing the taskfile to hardware, starting the command.
3546 *
3547 * LOCKING:
3548 * spin_lock_irqsave(host_set lock)
3549 *
3550 * RETURNS:
3551 * Zero on success, negative on error.
3552 */
3553
3554int ata_qc_issue(struct ata_queued_cmd *qc)
3555{
3556 struct ata_port *ap = qc->ap;
3557
3558 if (ata_should_dma_map(qc)) {
3559 if (qc->flags & ATA_QCFLAG_SG) {
3560 if (ata_sg_setup(qc))
3561 goto err_out;
3562 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
3563 if (ata_sg_setup_one(qc))
3564 goto err_out;
3565 }
3566 } else {
3567 qc->flags &= ~ATA_QCFLAG_DMAMAP;
3568 }
3569
3570 ap->ops->qc_prep(qc);
3571
3572 qc->ap->active_tag = qc->tag;
3573 qc->flags |= ATA_QCFLAG_ACTIVE;
3574
3575 return ap->ops->qc_issue(qc);
3576
3577err_out:
3578 return -1;
3579}
3580
0baab86b 3581
1da177e4
LT		 3582/**
3583 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
3584 * @qc: command to issue to device
3585 *
3586 * Using various libata functions and hooks, this function
3587 * starts an ATA command. ATA commands are grouped into
3588 * classes called "protocols", and issuing each type of protocol
3589 * is slightly different.
3590 *
0baab86b
EF		 3591 * May be used as the qc_issue() entry in ata_port_operations.
3592 *
1da177e4
LT		 3593 * LOCKING:
3594 * spin_lock_irqsave(host_set lock)
3595 *
3596 * RETURNS:
3597 * Zero on success, negative on error.
3598 */
3599
3600int ata_qc_issue_prot(struct ata_queued_cmd *qc)
3601{
3602 struct ata_port *ap = qc->ap;
3603
3604 ata_dev_select(ap, qc->dev->devno, 1, 0);
3605
3606 switch (qc->tf.protocol) {
3607 case ATA_PROT_NODATA:
e5338254 3608 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3609 break;
3610
3611 case ATA_PROT_DMA:
3612 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3613 ap->ops->bmdma_setup(qc); /* set up bmdma */
3614 ap->ops->bmdma_start(qc); /* initiate bmdma */
3615 break;
3616
3617 case ATA_PROT_PIO: /* load tf registers, initiate polling pio */
3618 ata_qc_set_polling(qc);
e5338254 3619 ata_tf_to_host(ap, &qc->tf);
14be71f4 3620 ap->hsm_task_state = HSM_ST;
1da177e4
LT		 3621 queue_work(ata_wq, &ap->pio_task);
3622 break;
3623
3624 case ATA_PROT_ATAPI:
3625 ata_qc_set_polling(qc);
e5338254 3626 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3627 queue_work(ata_wq, &ap->packet_task);
3628 break;
3629
3630 case ATA_PROT_ATAPI_NODATA:
c1389503 3631 ap->flags |= ATA_FLAG_NOINTR;
e5338254 3632 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3633 queue_work(ata_wq, &ap->packet_task);
3634 break;
3635
3636 case ATA_PROT_ATAPI_DMA:
c1389503 3637 ap->flags |= ATA_FLAG_NOINTR;
1da177e4
LT		 3638 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3639 ap->ops->bmdma_setup(qc); /* set up bmdma */
3640 queue_work(ata_wq, &ap->packet_task);
3641 break;
3642
3643 default:
3644 WARN_ON(1);
3645 return -1;
3646 }
3647
3648 return 0;
3649}
3650
3651/**
0baab86b 3652 * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
1da177e4
LT		 3653 * @qc: Info associated with this ATA transaction.
3654 *
3655 * LOCKING:
3656 * spin_lock_irqsave(host_set lock)
3657 */
3658
3659static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc)
3660{
3661 struct ata_port *ap = qc->ap;
3662 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3663 u8 dmactl;
3664 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3665
3666 /* load PRD table addr. */
3667 mb(); /* make sure PRD table writes are visible to controller */
3668 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
3669
3670 /* specify data direction, triple-check start bit is clear */
3671 dmactl = readb(mmio + ATA_DMA_CMD);
3672 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3673 if (!rw)
3674 dmactl |= ATA_DMA_WR;
3675 writeb(dmactl, mmio + ATA_DMA_CMD);
3676
3677 /* issue r/w command */
3678 ap->ops->exec_command(ap, &qc->tf);
3679}
3680
3681/**
b73fc89f 3682 * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction
1da177e4
LT		 3683 * @qc: Info associated with this ATA transaction.
3684 *
3685 * LOCKING:
3686 * spin_lock_irqsave(host_set lock)
3687 */
3688
3689static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc)
3690{
3691 struct ata_port *ap = qc->ap;
3692 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3693 u8 dmactl;
3694
3695 /* start host DMA transaction */
3696 dmactl = readb(mmio + ATA_DMA_CMD);
3697 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
3698
3699 /* Strictly, one may wish to issue a readb() here, to
3700 * flush the mmio write. However, control also passes
3701 * to the hardware at this point, and it will interrupt
3702 * us when we are to resume control. So, in effect,
3703 * we don't care when the mmio write flushes.
3704 * Further, a read of the DMA status register _immediately_
3705 * following the write may not be what certain flaky hardware
3706 * is expected, so I think it is best to not add a readb()
3707 * without first all the MMIO ATA cards/mobos.
3708 * Or maybe I'm just being paranoid.
3709 */
3710}
3711
3712/**
3713 * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO)
3714 * @qc: Info associated with this ATA transaction.
3715 *
3716 * LOCKING:
3717 * spin_lock_irqsave(host_set lock)
3718 */
3719
3720static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc)
3721{
3722 struct ata_port *ap = qc->ap;
3723 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3724 u8 dmactl;
3725
3726 /* load PRD table addr. */
3727 outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
3728
3729 /* specify data direction, triple-check start bit is clear */
3730 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3731 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3732 if (!rw)
3733 dmactl |= ATA_DMA_WR;
3734 outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3735
3736 /* issue r/w command */
3737 ap->ops->exec_command(ap, &qc->tf);
3738}
3739
3740/**
3741 * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO)
3742 * @qc: Info associated with this ATA transaction.
3743 *
3744 * LOCKING:
3745 * spin_lock_irqsave(host_set lock)
3746 */
3747
3748static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
3749{
3750 struct ata_port *ap = qc->ap;
3751 u8 dmactl;
3752
3753 /* start host DMA transaction */
3754 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3755 outb(dmactl | ATA_DMA_START,
3756 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3757}
3758
0baab86b
EF		 3759
3760/**
3761 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
3762 * @qc: Info associated with this ATA transaction.
3763 *
3764 * Writes the ATA_DMA_START flag to the DMA command register.
3765 *
3766 * May be used as the bmdma_start() entry in ata_port_operations.
3767 *
3768 * LOCKING:
3769 * spin_lock_irqsave(host_set lock)
3770 */
1da177e4
LT		 3771void ata_bmdma_start(struct ata_queued_cmd *qc)
3772{
3773 if (qc->ap->flags & ATA_FLAG_MMIO)
3774 ata_bmdma_start_mmio(qc);
3775 else
3776 ata_bmdma_start_pio(qc);
3777}
3778
0baab86b
EF		 3779
3780/**
3781 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
3782 * @qc: Info associated with this ATA transaction.
3783 *
3784 * Writes address of PRD table to device's PRD Table Address
3785 * register, sets the DMA control register, and calls
3786 * ops->exec_command() to start the transfer.
3787 *
3788 * May be used as the bmdma_setup() entry in ata_port_operations.
3789 *
3790 * LOCKING:
3791 * spin_lock_irqsave(host_set lock)
3792 */
1da177e4
LT		 3793void ata_bmdma_setup(struct ata_queued_cmd *qc)
3794{
3795 if (qc->ap->flags & ATA_FLAG_MMIO)
3796 ata_bmdma_setup_mmio(qc);
3797 else
3798 ata_bmdma_setup_pio(qc);
3799}
3800
0baab86b
EF		 3801
3802/**
3803 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
decc6d0b 3804 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3805 *
3806 * Clear interrupt and error flags in DMA status register.
3807 *
3808 * May be used as the irq_clear() entry in ata_port_operations.
3809 *
3810 * LOCKING:
3811 * spin_lock_irqsave(host_set lock)
3812 */
3813
1da177e4
LT		 3814void ata_bmdma_irq_clear(struct ata_port *ap)
3815{
3816 if (ap->flags & ATA_FLAG_MMIO) {
3817 void __iomem *mmio = ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS;
3818 writeb(readb(mmio), mmio);
3819 } else {
3820 unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
3821 outb(inb(addr), addr);
3822 }
3823
3824}
3825
0baab86b
EF		 3826
3827/**
3828 * ata_bmdma_status - Read PCI IDE BMDMA status
decc6d0b 3829 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3830 *
3831 * Read and return BMDMA status register.
3832 *
3833 * May be used as the bmdma_status() entry in ata_port_operations.
3834 *
3835 * LOCKING:
3836 * spin_lock_irqsave(host_set lock)
3837 */
3838
1da177e4
LT		 3839u8 ata_bmdma_status(struct ata_port *ap)
3840{
3841 u8 host_stat;
3842 if (ap->flags & ATA_FLAG_MMIO) {
3843 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3844 host_stat = readb(mmio + ATA_DMA_STATUS);
3845 } else
ee500aab 3846 host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
1da177e4
LT		 3847 return host_stat;
3848}
3849
0baab86b
EF		 3850
3851/**
3852 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
b73fc89f 3853 * @qc: Command we are ending DMA for
0baab86b
EF		 3854 *
3855 * Clears the ATA_DMA_START flag in the dma control register
3856 *
3857 * May be used as the bmdma_stop() entry in ata_port_operations.
3858 *
3859 * LOCKING:
3860 * spin_lock_irqsave(host_set lock)
3861 */
3862
b73fc89f 3863void ata_bmdma_stop(struct ata_queued_cmd *qc)
1da177e4 3864{
b73fc89f 3865 struct ata_port *ap = qc->ap;
1da177e4
LT		 3866 if (ap->flags & ATA_FLAG_MMIO) {
3867 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3868
3869 /* clear start/stop bit */
3870 writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
3871 mmio + ATA_DMA_CMD);
3872 } else {
3873 /* clear start/stop bit */
3874 outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
3875 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3876 }
3877
3878 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
3879 ata_altstatus(ap); /* dummy read */
3880}
3881
3882/**
3883 * ata_host_intr - Handle host interrupt for given (port, task)
3884 * @ap: Port on which interrupt arrived (possibly...)
3885 * @qc: Taskfile currently active in engine
3886 *
3887 * Handle host interrupt for given queued command. Currently,
3888 * only DMA interrupts are handled. All other commands are
3889 * handled via polling with interrupts disabled (nIEN bit).
3890 *
3891 * LOCKING:
3892 * spin_lock_irqsave(host_set lock)
3893 *
3894 * RETURNS:
3895 * One if interrupt was handled, zero if not (shared irq).
3896 */
3897
3898inline unsigned int ata_host_intr (struct ata_port *ap,
3899 struct ata_queued_cmd *qc)
3900{
3901 u8 status, host_stat;
3902
3903 switch (qc->tf.protocol) {
3904
3905 case ATA_PROT_DMA:
3906 case ATA_PROT_ATAPI_DMA:
3907 case ATA_PROT_ATAPI:
3908 /* check status of DMA engine */
3909 host_stat = ap->ops->bmdma_status(ap);
3910 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
3911
3912 /* if it's not our irq... */
3913 if (!(host_stat & ATA_DMA_INTR))
3914 goto idle_irq;
3915
3916 /* before we do anything else, clear DMA-Start bit */
b73fc89f 3917 ap->ops->bmdma_stop(qc);
1da177e4
LT		 3918
3919 /* fall through */
3920
3921 case ATA_PROT_ATAPI_NODATA:
3922 case ATA_PROT_NODATA:
3923 /* check altstatus */
3924 status = ata_altstatus(ap);
3925 if (status & ATA_BUSY)
3926 goto idle_irq;
3927
3928 /* check main status, clearing INTRQ */
3929 status = ata_chk_status(ap);
3930 if (unlikely(status & ATA_BUSY))
3931 goto idle_irq;
3932 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
3933 ap->id, qc->tf.protocol, status);
3934
3935 /* ack bmdma irq events */
3936 ap->ops->irq_clear(ap);
3937
3938 /* complete taskfile transaction */
a7dac447 3939 ata_qc_complete(qc, ac_err_mask(status));
1da177e4
LT		 3940 break;
3941
3942 default:
3943 goto idle_irq;
3944 }
3945
3946 return 1; /* irq handled */
3947
3948idle_irq:
3949 ap->stats.idle_irq++;
3950
3951#ifdef ATA_IRQ_TRAP
3952 if ((ap->stats.idle_irq % 1000) == 0) {
3953 handled = 1;
3954 ata_irq_ack(ap, 0); /* debug trap */
3955 printk(KERN_WARNING "ata%d: irq trap\n", ap->id);
3956 }
3957#endif
3958 return 0; /* irq not handled */
3959}
3960
3961/**
3962 * ata_interrupt - Default ATA host interrupt handler
0cba632b
JG		 3963 * @irq: irq line (unused)
3964 * @dev_instance: pointer to our ata_host_set information structure
1da177e4
LT		 3965 * @regs: unused
3966 *
0cba632b
JG		 3967 * Default interrupt handler for PCI IDE devices. Calls
3968 * ata_host_intr() for each port that is not disabled.
3969 *
1da177e4 3970 * LOCKING:
0cba632b 3971 * Obtains host_set lock during operation.
1da177e4
LT		 3972 *
3973 * RETURNS:
0cba632b 3974 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT		 3975 */
3976
3977irqreturn_t ata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
3978{
3979 struct ata_host_set *host_set = dev_instance;
3980 unsigned int i;
3981 unsigned int handled = 0;
3982 unsigned long flags;
3983
3984 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
3985 spin_lock_irqsave(&host_set->lock, flags);
3986
3987 for (i = 0; i < host_set->n_ports; i++) {
3988 struct ata_port *ap;
3989
3990 ap = host_set->ports[i];
c1389503
TH		 3991 if (ap &&
3992 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
1da177e4
LT		 3993 struct ata_queued_cmd *qc;
3994
3995 qc = ata_qc_from_tag(ap, ap->active_tag);
21b1ed74
AL		 3996 if (qc && (!(qc->tf.ctl & ATA_NIEN)) &&
3997 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT		 3998 handled |= ata_host_intr(ap, qc);
3999 }
4000 }
4001
4002 spin_unlock_irqrestore(&host_set->lock, flags);
4003
4004 return IRQ_RETVAL(handled);
4005}
4006
4007/**
4008 * atapi_packet_task - Write CDB bytes to hardware
4009 * @_data: Port to which ATAPI device is attached.
4010 *
4011 * When device has indicated its readiness to accept
4012 * a CDB, this function is called. Send the CDB.
4013 * If DMA is to be performed, exit immediately.
4014 * Otherwise, we are in polling mode, so poll
4015 * status under operation succeeds or fails.
4016 *
4017 * LOCKING:
4018 * Kernel thread context (may sleep)
4019 */
4020
4021static void atapi_packet_task(void *_data)
4022{
4023 struct ata_port *ap = _data;
4024 struct ata_queued_cmd *qc;
4025 u8 status;
4026
4027 qc = ata_qc_from_tag(ap, ap->active_tag);
4028 assert(qc != NULL);
4029 assert(qc->flags & ATA_QCFLAG_ACTIVE);
4030
4031 /* sleep-wait for BSY to clear */
4032 DPRINTK("busy wait\n");
4033 if (ata_busy_sleep(ap, ATA_TMOUT_CDB_QUICK, ATA_TMOUT_CDB))
a7dac447 4034 goto err_out_status;
1da177e4
LT		 4035
4036 /* make sure DRQ is set */
4037 status = ata_chk_status(ap);
4038 if ((status & (ATA_BUSY | ATA_DRQ)) != ATA_DRQ)
4039 goto err_out;
4040
4041 /* send SCSI cdb */
4042 DPRINTK("send cdb\n");
4043 assert(ap->cdb_len >= 12);
1da177e4 4044
c1389503
TH		 4045 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA ||
4046 qc->tf.protocol == ATA_PROT_ATAPI_NODATA) {
4047 unsigned long flags;
1da177e4 4048
c1389503
TH		 4049 /* Once we're done issuing command and kicking bmdma,
4050 * irq handler takes over. To not lose irq, we need
4051 * to clear NOINTR flag before sending cdb, but
4052 * interrupt handler shouldn't be invoked before we're
4053 * finished. Hence, the following locking.
4054 */
4055 spin_lock_irqsave(&ap->host_set->lock, flags);
4056 ap->flags &= ~ATA_FLAG_NOINTR;
4057 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
4058 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA)
4059 ap->ops->bmdma_start(qc); /* initiate bmdma */
4060 spin_unlock_irqrestore(&ap->host_set->lock, flags);
4061 } else {
4062 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
1da177e4 4063
c1389503 4064 /* PIO commands are handled by polling */
14be71f4 4065 ap->hsm_task_state = HSM_ST;
1da177e4
LT		 4066 queue_work(ata_wq, &ap->pio_task);
4067 }
4068
4069 return;
4070
a7dac447
JG		 4071err_out_status:
4072 status = ata_chk_status(ap);
1da177e4 4073err_out:
a7dac447 4074 ata_poll_qc_complete(qc, __ac_err_mask(status));
1da177e4
LT		 4075}
4076
0baab86b
EF		 4077
4078/**
4079 * ata_port_start - Set port up for dma.
4080 * @ap: Port to initialize
4081 *
4082 * Called just after data structures for each port are
4083 * initialized. Allocates space for PRD table.
4084 *
4085 * May be used as the port_start() entry in ata_port_operations.
4086 *
4087 * LOCKING:
6f0ef4fa 4088 * Inherited from caller.
0baab86b
EF		 4089 */
4090
1da177e4
LT		 4091int ata_port_start (struct ata_port *ap)
4092{
4093 struct device *dev = ap->host_set->dev;
4094
4095 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
4096 if (!ap->prd)
4097 return -ENOMEM;
4098
cedc9a47
JG		 4099 ap->pad = dma_alloc_coherent(dev, ATA_DMA_PAD_BUF_SZ, &ap->pad_dma, GFP_KERNEL);
4100 if (!ap->pad) {
4101 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
4102 return -ENOMEM;
4103 }
4104
1da177e4
LT		 4105 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
4106
4107 return 0;
4108}
4109
0baab86b
EF		 4110
4111/**
4112 * ata_port_stop - Undo ata_port_start()
4113 * @ap: Port to shut down
4114 *
4115 * Frees the PRD table.
4116 *
4117 * May be used as the port_stop() entry in ata_port_operations.
4118 *
4119 * LOCKING:
6f0ef4fa 4120 * Inherited from caller.
0baab86b
EF		 4121 */
4122
1da177e4
LT		 4123void ata_port_stop (struct ata_port *ap)
4124{
4125 struct device *dev = ap->host_set->dev;
4126
4127 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
cedc9a47 4128 dma_free_coherent(dev, ATA_DMA_PAD_BUF_SZ, ap->pad, ap->pad_dma);
1da177e4
LT		 4129}
4130
aa8f0dc6
JG		 4131void ata_host_stop (struct ata_host_set *host_set)
4132{
4133 if (host_set->mmio_base)
4134 iounmap(host_set->mmio_base);
4135}
4136
4137
1da177e4
LT		 4138/**
4139 * ata_host_remove - Unregister SCSI host structure with upper layers
4140 * @ap: Port to unregister
4141 * @do_unregister: 1 if we fully unregister, 0 to just stop the port
4142 *
4143 * LOCKING:
6f0ef4fa 4144 * Inherited from caller.
1da177e4
LT		 4145 */
4146
4147static void ata_host_remove(struct ata_port *ap, unsigned int do_unregister)
4148{
4149 struct Scsi_Host *sh = ap->host;
4150
4151 DPRINTK("ENTER\n");
4152
4153 if (do_unregister)
4154 scsi_remove_host(sh);
4155
4156 ap->ops->port_stop(ap);
4157}
4158
4159/**
4160 * ata_host_init - Initialize an ata_port structure
4161 * @ap: Structure to initialize
4162 * @host: associated SCSI mid-layer structure
4163 * @host_set: Collection of hosts to which @ap belongs
4164 * @ent: Probe information provided by low-level driver
4165 * @port_no: Port number associated with this ata_port
4166 *
0cba632b
JG		 4167 * Initialize a new ata_port structure, and its associated
4168 * scsi_host.
4169 *
1da177e4 4170 * LOCKING:
0cba632b 4171 * Inherited from caller.
1da177e4
LT		 4172 */
4173
4174static void ata_host_init(struct ata_port *ap, struct Scsi_Host *host,
4175 struct ata_host_set *host_set,
057ace5e 4176 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT		 4177{
4178 unsigned int i;
4179
4180 host->max_id = 16;
4181 host->max_lun = 1;
4182 host->max_channel = 1;
4183 host->unique_id = ata_unique_id++;
4184 host->max_cmd_len = 12;
12413197 4185
1da177e4
LT		 4186 ap->flags = ATA_FLAG_PORT_DISABLED;
4187 ap->id = host->unique_id;
4188 ap->host = host;
4189 ap->ctl = ATA_DEVCTL_OBS;
4190 ap->host_set = host_set;
4191 ap->port_no = port_no;
4192 ap->hard_port_no =
4193 ent->legacy_mode ? ent->hard_port_no : port_no;
4194 ap->pio_mask = ent->pio_mask;
4195 ap->mwdma_mask = ent->mwdma_mask;
4196 ap->udma_mask = ent->udma_mask;
4197 ap->flags |= ent->host_flags;
4198 ap->ops = ent->port_ops;
4199 ap->cbl = ATA_CBL_NONE;
4200 ap->active_tag = ATA_TAG_POISON;
4201 ap->last_ctl = 0xFF;
4202
4203 INIT_WORK(&ap->packet_task, atapi_packet_task, ap);
4204 INIT_WORK(&ap->pio_task, ata_pio_task, ap);
4205
4206 for (i = 0; i < ATA_MAX_DEVICES; i++)
4207 ap->device[i].devno = i;
4208
4209#ifdef ATA_IRQ_TRAP
4210 ap->stats.unhandled_irq = 1;
4211 ap->stats.idle_irq = 1;
4212#endif
4213
4214 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
4215}
4216
4217/**
4218 * ata_host_add - Attach low-level ATA driver to system
4219 * @ent: Information provided by low-level driver
4220 * @host_set: Collections of ports to which we add
4221 * @port_no: Port number associated with this host
4222 *
0cba632b
JG		 4223 * Attach low-level ATA driver to system.
4224 *
1da177e4 4225 * LOCKING:
0cba632b 4226 * PCI/etc. bus probe sem.
1da177e4
LT		 4227 *
4228 * RETURNS:
0cba632b 4229 * New ata_port on success, for NULL on error.
1da177e4
LT		 4230 */
4231
057ace5e 4232static struct ata_port * ata_host_add(const struct ata_probe_ent *ent,
1da177e4
LT		 4233 struct ata_host_set *host_set,
4234 unsigned int port_no)
4235{
4236 struct Scsi_Host *host;
4237 struct ata_port *ap;
4238 int rc;
4239
4240 DPRINTK("ENTER\n");
4241 host = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
4242 if (!host)
4243 return NULL;
4244
4245 ap = (struct ata_port *) &host->hostdata[0];
4246
4247 ata_host_init(ap, host, host_set, ent, port_no);
4248
4249 rc = ap->ops->port_start(ap);
4250 if (rc)
4251 goto err_out;
4252
4253 return ap;
4254
4255err_out:
4256 scsi_host_put(host);
4257 return NULL;
4258}
4259
4260/**
0cba632b
JG		 4261 * ata_device_add - Register hardware device with ATA and SCSI layers
4262 * @ent: Probe information describing hardware device to be registered
4263 *
4264 * This function processes the information provided in the probe
4265 * information struct @ent, allocates the necessary ATA and SCSI
4266 * host information structures, initializes them, and registers
4267 * everything with requisite kernel subsystems.
4268 *
4269 * This function requests irqs, probes the ATA bus, and probes
4270 * the SCSI bus.
1da177e4
LT		 4271 *
4272 * LOCKING:
0cba632b 4273 * PCI/etc. bus probe sem.
1da177e4
LT		 4274 *
4275 * RETURNS:
0cba632b 4276 * Number of ports registered. Zero on error (no ports registered).
1da177e4
LT		 4277 */
4278
057ace5e 4279int ata_device_add(const struct ata_probe_ent *ent)
1da177e4
LT		 4280{
4281 unsigned int count = 0, i;
4282 struct device *dev = ent->dev;
4283 struct ata_host_set *host_set;
4284
4285 DPRINTK("ENTER\n");
4286 /* alloc a container for our list of ATA ports (buses) */
57f3bda8 4287 host_set = kzalloc(sizeof(struct ata_host_set) +
1da177e4
LT		 4288 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
4289 if (!host_set)
4290 return 0;
1da177e4
LT		 4291 spin_lock_init(&host_set->lock);
4292
4293 host_set->dev = dev;
4294 host_set->n_ports = ent->n_ports;
4295 host_set->irq = ent->irq;
4296 host_set->mmio_base = ent->mmio_base;
4297 host_set->private_data = ent->private_data;
4298 host_set->ops = ent->port_ops;
4299
4300 /* register each port bound to this device */
4301 for (i = 0; i < ent->n_ports; i++) {
4302 struct ata_port *ap;
4303 unsigned long xfer_mode_mask;
4304
4305 ap = ata_host_add(ent, host_set, i);
4306 if (!ap)
4307 goto err_out;
4308
4309 host_set->ports[i] = ap;
4310 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
4311 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
4312 (ap->pio_mask << ATA_SHIFT_PIO);
4313
4314 /* print per-port info to dmesg */
4315 printk(KERN_INFO "ata%u: %cATA max %s cmd 0x%lX ctl 0x%lX "
4316 "bmdma 0x%lX irq %lu\n",
4317 ap->id,
4318 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
4319 ata_mode_string(xfer_mode_mask),
4320 ap->ioaddr.cmd_addr,
4321 ap->ioaddr.ctl_addr,
4322 ap->ioaddr.bmdma_addr,
4323 ent->irq);
4324
4325 ata_chk_status(ap);
4326 host_set->ops->irq_clear(ap);
4327 count++;
4328 }
4329
57f3bda8
RD		 4330 if (!count)
4331 goto err_free_ret;
1da177e4
LT		 4332
4333 /* obtain irq, that is shared between channels */
4334 if (request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
4335 DRV_NAME, host_set))
4336 goto err_out;
4337
4338 /* perform each probe synchronously */
4339 DPRINTK("probe begin\n");
4340 for (i = 0; i < count; i++) {
4341 struct ata_port *ap;
4342 int rc;
4343
4344 ap = host_set->ports[i];
4345
4346 DPRINTK("ata%u: probe begin\n", ap->id);
4347 rc = ata_bus_probe(ap);
4348 DPRINTK("ata%u: probe end\n", ap->id);
4349
4350 if (rc) {
4351 /* FIXME: do something useful here?
4352 * Current libata behavior will
4353 * tear down everything when
4354 * the module is removed
4355 * or the h/w is unplugged.
4356 */
4357 }
4358
4359 rc = scsi_add_host(ap->host, dev);
4360 if (rc) {
4361 printk(KERN_ERR "ata%u: scsi_add_host failed\n",
4362 ap->id);
4363 /* FIXME: do something useful here */
4364 /* FIXME: handle unconditional calls to
4365 * scsi_scan_host and ata_host_remove, below,
4366 * at the very least
4367 */
4368 }
4369 }
4370
4371 /* probes are done, now scan each port's disk(s) */
4372 DPRINTK("probe begin\n");
4373 for (i = 0; i < count; i++) {
4374 struct ata_port *ap = host_set->ports[i];
4375
644dd0cc 4376 ata_scsi_scan_host(ap);
1da177e4
LT		 4377 }
4378
4379 dev_set_drvdata(dev, host_set);
4380
4381 VPRINTK("EXIT, returning %u\n", ent->n_ports);
4382 return ent->n_ports; /* success */
4383
4384err_out:
4385 for (i = 0; i < count; i++) {
4386 ata_host_remove(host_set->ports[i], 1);
4387 scsi_host_put(host_set->ports[i]->host);
4388 }
57f3bda8 4389err_free_ret:
1da177e4
LT		 4390 kfree(host_set);
4391 VPRINTK("EXIT, returning 0\n");
4392 return 0;
4393}
4394
17b14451
AC		 4395/**
4396 * ata_host_set_remove - PCI layer callback for device removal
4397 * @host_set: ATA host set that was removed
4398 *
4399 * Unregister all objects associated with this host set. Free those
4400 * objects.
4401 *
4402 * LOCKING:
4403 * Inherited from calling layer (may sleep).
4404 */
4405
17b14451
AC		 4406void ata_host_set_remove(struct ata_host_set *host_set)
4407{
4408 struct ata_port *ap;
4409 unsigned int i;
4410
4411 for (i = 0; i < host_set->n_ports; i++) {
4412 ap = host_set->ports[i];
4413 scsi_remove_host(ap->host);
4414 }
4415
4416 free_irq(host_set->irq, host_set);
4417
4418 for (i = 0; i < host_set->n_ports; i++) {
4419 ap = host_set->ports[i];
4420
4421 ata_scsi_release(ap->host);
4422
4423 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
4424 struct ata_ioports *ioaddr = &ap->ioaddr;
4425
4426 if (ioaddr->cmd_addr == 0x1f0)
4427 release_region(0x1f0, 8);
4428 else if (ioaddr->cmd_addr == 0x170)
4429 release_region(0x170, 8);
4430 }
4431
4432 scsi_host_put(ap->host);
4433 }
4434
4435 if (host_set->ops->host_stop)
4436 host_set->ops->host_stop(host_set);
4437
4438 kfree(host_set);
4439}
4440
1da177e4
LT		 4441/**
4442 * ata_scsi_release - SCSI layer callback hook for host unload
4443 * @host: libata host to be unloaded
4444 *
4445 * Performs all duties necessary to shut down a libata port...
4446 * Kill port kthread, disable port, and release resources.
4447 *
4448 * LOCKING:
4449 * Inherited from SCSI layer.
4450 *
4451 * RETURNS:
4452 * One.
4453 */
4454
4455int ata_scsi_release(struct Scsi_Host *host)
4456{
4457 struct ata_port *ap = (struct ata_port *) &host->hostdata[0];
4458
4459 DPRINTK("ENTER\n");
4460
4461 ap->ops->port_disable(ap);
4462 ata_host_remove(ap, 0);
4463
4464 DPRINTK("EXIT\n");
4465 return 1;
4466}
4467
4468/**
4469 * ata_std_ports - initialize ioaddr with standard port offsets.
4470 * @ioaddr: IO address structure to be initialized
0baab86b
EF		 4471 *
4472 * Utility function which initializes data_addr, error_addr,
4473 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
4474 * device_addr, status_addr, and command_addr to standard offsets
4475 * relative to cmd_addr.
4476 *
4477 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 4478 */
0baab86b 4479
1da177e4
LT		 4480void ata_std_ports(struct ata_ioports *ioaddr)
4481{
4482 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
4483 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
4484 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
4485 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
4486 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
4487 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
4488 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
4489 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
4490 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
4491 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
4492}
4493
4494static struct ata_probe_ent *
057ace5e 4495ata_probe_ent_alloc(struct device *dev, const struct ata_port_info *port)
1da177e4
LT		 4496{
4497 struct ata_probe_ent *probe_ent;
4498
57f3bda8 4499 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
1da177e4
LT		 4500 if (!probe_ent) {
4501 printk(KERN_ERR DRV_NAME "(%s): out of memory\n",
4502 kobject_name(&(dev->kobj)));
4503 return NULL;
4504 }
4505
1da177e4
LT		 4506 INIT_LIST_HEAD(&probe_ent->node);
4507 probe_ent->dev = dev;
4508
4509 probe_ent->sht = port->sht;
4510 probe_ent->host_flags = port->host_flags;
4511 probe_ent->pio_mask = port->pio_mask;
4512 probe_ent->mwdma_mask = port->mwdma_mask;
4513 probe_ent->udma_mask = port->udma_mask;
4514 probe_ent->port_ops = port->port_ops;
4515
4516 return probe_ent;
4517}
4518
0baab86b
EF		 4519
4520
374b1873
JG		 4521#ifdef CONFIG_PCI
4522
4523void ata_pci_host_stop (struct ata_host_set *host_set)
4524{
4525 struct pci_dev *pdev = to_pci_dev(host_set->dev);
4526
4527 pci_iounmap(pdev, host_set->mmio_base);
4528}
4529
0baab86b
EF		 4530/**
4531 * ata_pci_init_native_mode - Initialize native-mode driver
4532 * @pdev: pci device to be initialized
4533 * @port: array[2] of pointers to port info structures.
47a86593 4534 * @ports: bitmap of ports present
0baab86b
EF		 4535 *
4536 * Utility function which allocates and initializes an
4537 * ata_probe_ent structure for a standard dual-port
4538 * PIO-based IDE controller. The returned ata_probe_ent
4539 * structure can be passed to ata_device_add(). The returned
4540 * ata_probe_ent structure should then be freed with kfree().
47a86593
AC		 4541 *
4542 * The caller need only pass the address of the primary port, the
4543 * secondary will be deduced automatically. If the device has non
4544 * standard secondary port mappings this function can be called twice,
4545 * once for each interface.
0baab86b
EF		 4546 */
4547
1da177e4 4548struct ata_probe_ent *
47a86593 4549ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports)
1da177e4
LT		 4550{
4551 struct ata_probe_ent *probe_ent =
4552 ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]);
47a86593
AC		 4553 int p = 0;
4554
1da177e4
LT		 4555 if (!probe_ent)
4556 return NULL;
4557
1da177e4
LT		 4558 probe_ent->irq = pdev->irq;
4559 probe_ent->irq_flags = SA_SHIRQ;
4560
47a86593
AC		 4561 if (ports & ATA_PORT_PRIMARY) {
4562 probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 0);
4563 probe_ent->port[p].altstatus_addr =
4564 probe_ent->port[p].ctl_addr =
4565 pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS;
4566 probe_ent->port[p].bmdma_addr = pci_resource_start(pdev, 4);
4567 ata_std_ports(&probe_ent->port[p]);
4568 p++;
4569 }
1da177e4 4570
47a86593
AC		 4571 if (ports & ATA_PORT_SECONDARY) {
4572 probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 2);
4573 probe_ent->port[p].altstatus_addr =
4574 probe_ent->port[p].ctl_addr =
4575 pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS;
4576 probe_ent->port[p].bmdma_addr = pci_resource_start(pdev, 4) + 8;
4577 ata_std_ports(&probe_ent->port[p]);
4578 p++;
4579 }
1da177e4 4580
47a86593 4581 probe_ent->n_ports = p;
1da177e4
LT		 4582 return probe_ent;
4583}
4584
0f0d5192 4585static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, struct ata_port_info *port, int port_num)
1da177e4 4586{
47a86593 4587 struct ata_probe_ent *probe_ent;
1da177e4 4588
0f0d5192 4589 probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port);
1da177e4
LT		 4590 if (!probe_ent)
4591 return NULL;
1da177e4 4592
1da177e4 4593 probe_ent->legacy_mode = 1;
47a86593
AC		 4594 probe_ent->n_ports = 1;
4595 probe_ent->hard_port_no = port_num;
4596
4597 switch(port_num)
4598 {
4599 case 0:
4600 probe_ent->irq = 14;
4601 probe_ent->port[0].cmd_addr = 0x1f0;
4602 probe_ent->port[0].altstatus_addr =
4603 probe_ent->port[0].ctl_addr = 0x3f6;
4604 break;
4605 case 1:
4606 probe_ent->irq = 15;
4607 probe_ent->port[0].cmd_addr = 0x170;
4608 probe_ent->port[0].altstatus_addr =
4609 probe_ent->port[0].ctl_addr = 0x376;
4610 break;
4611 }
4612 probe_ent->port[0].bmdma_addr = pci_resource_start(pdev, 4) + 8 * port_num;
1da177e4 4613 ata_std_ports(&probe_ent->port[0]);
1da177e4
LT		 4614 return probe_ent;
4615}
4616
4617/**
4618 * ata_pci_init_one - Initialize/register PCI IDE host controller
4619 * @pdev: Controller to be initialized
4620 * @port_info: Information from low-level host driver
4621 * @n_ports: Number of ports attached to host controller
4622 *
0baab86b
EF		 4623 * This is a helper function which can be called from a driver's
4624 * xxx_init_one() probe function if the hardware uses traditional
4625 * IDE taskfile registers.
4626 *
4627 * This function calls pci_enable_device(), reserves its register
4628 * regions, sets the dma mask, enables bus master mode, and calls
4629 * ata_device_add()
4630 *
1da177e4
LT		 4631 * LOCKING:
4632 * Inherited from PCI layer (may sleep).
4633 *
4634 * RETURNS:
0cba632b 4635 * Zero on success, negative on errno-based value on error.
1da177e4
LT		 4636 */
4637
4638int ata_pci_init_one (struct pci_dev *pdev, struct ata_port_info **port_info,
4639 unsigned int n_ports)
4640{
47a86593 4641 struct ata_probe_ent *probe_ent = NULL, *probe_ent2 = NULL;
1da177e4
LT		 4642 struct ata_port_info *port[2];
4643 u8 tmp8, mask;
4644 unsigned int legacy_mode = 0;
4645 int disable_dev_on_err = 1;
4646 int rc;
4647
4648 DPRINTK("ENTER\n");
4649
4650 port[0] = port_info[0];
4651 if (n_ports > 1)
4652 port[1] = port_info[1];
4653 else
4654 port[1] = port[0];
4655
4656 if ((port[0]->host_flags & ATA_FLAG_NO_LEGACY) == 0
4657 && (pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
47a86593 4658 /* TODO: What if one channel is in native mode ... */
1da177e4
LT		 4659 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
4660 mask = (1 << 2) | (1 << 0);
4661 if ((tmp8 & mask) != mask)
4662 legacy_mode = (1 << 3);
4663 }
4664
4665 /* FIXME... */
47a86593
AC		 4666 if ((!legacy_mode) && (n_ports > 2)) {
4667 printk(KERN_ERR "ata: BUG: native mode, n_ports > 2\n");
4668 n_ports = 2;
4669 /* For now */
1da177e4
LT		 4670 }
4671
47a86593
AC		 4672 /* FIXME: Really for ATA it isn't safe because the device may be
4673 multi-purpose and we want to leave it alone if it was already
4674 enabled. Secondly for shared use as Arjan says we want refcounting
4675
4676 Checking dev->is_enabled is insufficient as this is not set at
4677 boot for the primary video which is BIOS enabled
4678 */
4679
1da177e4
LT		 4680 rc = pci_enable_device(pdev);
4681 if (rc)
4682 return rc;
4683
4684 rc = pci_request_regions(pdev, DRV_NAME);
4685 if (rc) {
4686 disable_dev_on_err = 0;
4687 goto err_out;
4688 }
4689
47a86593 4690 /* FIXME: Should use platform specific mappers for legacy port ranges */
1da177e4
LT		 4691 if (legacy_mode) {
4692 if (!request_region(0x1f0, 8, "libata")) {
4693 struct resource *conflict, res;
4694 res.start = 0x1f0;
4695 res.end = 0x1f0 + 8 - 1;
4696 conflict = ____request_resource(&ioport_resource, &res);
4697 if (!strcmp(conflict->name, "libata"))
4698 legacy_mode |= (1 << 0);
4699 else {
4700 disable_dev_on_err = 0;
4701 printk(KERN_WARNING "ata: 0x1f0 IDE port busy\n");
4702 }
4703 } else
4704 legacy_mode |= (1 << 0);
4705
4706 if (!request_region(0x170, 8, "libata")) {
4707 struct resource *conflict, res;
4708 res.start = 0x170;
4709 res.end = 0x170 + 8 - 1;
4710 conflict = ____request_resource(&ioport_resource, &res);
4711 if (!strcmp(conflict->name, "libata"))
4712 legacy_mode |= (1 << 1);
4713 else {
4714 disable_dev_on_err = 0;
4715 printk(KERN_WARNING "ata: 0x170 IDE port busy\n");
4716 }
4717 } else
4718 legacy_mode |= (1 << 1);
4719 }
4720
4721 /* we have legacy mode, but all ports are unavailable */
4722 if (legacy_mode == (1 << 3)) {
4723 rc = -EBUSY;
4724 goto err_out_regions;
4725 }
4726
4727 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
4728 if (rc)
4729 goto err_out_regions;
4730 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
4731 if (rc)
4732 goto err_out_regions;
4733
4734 if (legacy_mode) {
47a86593 4735 if (legacy_mode & (1 << 0))
0f0d5192 4736 probe_ent = ata_pci_init_legacy_port(pdev, port[0], 0);
47a86593 4737 if (legacy_mode & (1 << 1))
0f0d5192 4738 probe_ent2 = ata_pci_init_legacy_port(pdev, port[1], 1);
47a86593
AC		 4739 } else {
4740 if (n_ports == 2)
4741 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
4742 else
4743 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY);
4744 }
4745 if (!probe_ent && !probe_ent2) {
1da177e4
LT		 4746 rc = -ENOMEM;
4747 goto err_out_regions;
4748 }
4749
4750 pci_set_master(pdev);
4751
4752 /* FIXME: check ata_device_add return */
4753 if (legacy_mode) {
4754 if (legacy_mode & (1 << 0))
4755 ata_device_add(probe_ent);
4756 if (legacy_mode & (1 << 1))
4757 ata_device_add(probe_ent2);
4758 } else
4759 ata_device_add(probe_ent);
4760
4761 kfree(probe_ent);
4762 kfree(probe_ent2);
4763
4764 return 0;
4765
4766err_out_regions:
4767 if (legacy_mode & (1 << 0))
4768 release_region(0x1f0, 8);
4769 if (legacy_mode & (1 << 1))
4770 release_region(0x170, 8);
4771 pci_release_regions(pdev);
4772err_out:
4773 if (disable_dev_on_err)
4774 pci_disable_device(pdev);
4775 return rc;
4776}
4777
4778/**
4779 * ata_pci_remove_one - PCI layer callback for device removal
4780 * @pdev: PCI device that was removed
4781 *
4782 * PCI layer indicates to libata via this hook that
6f0ef4fa 4783 * hot-unplug or module unload event has occurred.
1da177e4
LT		 4784 * Handle this by unregistering all objects associated
4785 * with this PCI device. Free those objects. Then finally
4786 * release PCI resources and disable device.
4787 *
4788 * LOCKING:
4789 * Inherited from PCI layer (may sleep).
4790 */
4791
4792void ata_pci_remove_one (struct pci_dev *pdev)
4793{
4794 struct device *dev = pci_dev_to_dev(pdev);
4795 struct ata_host_set *host_set = dev_get_drvdata(dev);
1da177e4 4796
17b14451 4797 ata_host_set_remove(host_set);
1da177e4
LT		 4798 pci_release_regions(pdev);
4799 pci_disable_device(pdev);
4800 dev_set_drvdata(dev, NULL);
4801}
4802
4803/* move to PCI subsystem */
057ace5e 4804int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT		 4805{
4806 unsigned long tmp = 0;
4807
4808 switch (bits->width) {
4809 case 1: {
4810 u8 tmp8 = 0;
4811 pci_read_config_byte(pdev, bits->reg, &tmp8);
4812 tmp = tmp8;
4813 break;
4814 }
4815 case 2: {
4816 u16 tmp16 = 0;
4817 pci_read_config_word(pdev, bits->reg, &tmp16);
4818 tmp = tmp16;
4819 break;
4820 }
4821 case 4: {
4822 u32 tmp32 = 0;
4823 pci_read_config_dword(pdev, bits->reg, &tmp32);
4824 tmp = tmp32;
4825 break;
4826 }
4827
4828 default:
4829 return -EINVAL;
4830 }
4831
4832 tmp &= bits->mask;
4833
4834 return (tmp == bits->val) ? 1 : 0;
4835}
4836#endif /* CONFIG_PCI */
4837
4838
1da177e4
LT		 4839static int __init ata_init(void)
4840{
4841 ata_wq = create_workqueue("ata");
4842 if (!ata_wq)
4843 return -ENOMEM;
4844
4845 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
4846 return 0;
4847}
4848
4849static void __exit ata_exit(void)
4850{
4851 destroy_workqueue(ata_wq);
4852}
4853
4854module_init(ata_init);
4855module_exit(ata_exit);
4856
67846b30
JG		 4857static unsigned long ratelimit_time;
4858static spinlock_t ata_ratelimit_lock = SPIN_LOCK_UNLOCKED;
4859
4860int ata_ratelimit(void)
4861{
4862 int rc;
4863 unsigned long flags;
4864
4865 spin_lock_irqsave(&ata_ratelimit_lock, flags);
4866
4867 if (time_after(jiffies, ratelimit_time)) {
4868 rc = 1;
4869 ratelimit_time = jiffies + (HZ/5);
4870 } else
4871 rc = 0;
4872
4873 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
4874
4875 return rc;
4876}
4877
1da177e4
LT		 4878/*
4879 * libata is essentially a library of internal helper functions for
4880 * low-level ATA host controller drivers. As such, the API/ABI is
4881 * likely to change as new drivers are added and updated.
4882 * Do not depend on ABI/API stability.
4883 */
4884
4885EXPORT_SYMBOL_GPL(ata_std_bios_param);
4886EXPORT_SYMBOL_GPL(ata_std_ports);
4887EXPORT_SYMBOL_GPL(ata_device_add);
17b14451 4888EXPORT_SYMBOL_GPL(ata_host_set_remove);
1da177e4
LT		 4889EXPORT_SYMBOL_GPL(ata_sg_init);
4890EXPORT_SYMBOL_GPL(ata_sg_init_one);
4891EXPORT_SYMBOL_GPL(ata_qc_complete);
4892EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
4893EXPORT_SYMBOL_GPL(ata_eng_timeout);
4894EXPORT_SYMBOL_GPL(ata_tf_load);
4895EXPORT_SYMBOL_GPL(ata_tf_read);
4896EXPORT_SYMBOL_GPL(ata_noop_dev_select);
4897EXPORT_SYMBOL_GPL(ata_std_dev_select);
4898EXPORT_SYMBOL_GPL(ata_tf_to_fis);
4899EXPORT_SYMBOL_GPL(ata_tf_from_fis);
4900EXPORT_SYMBOL_GPL(ata_check_status);
4901EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT		 4902EXPORT_SYMBOL_GPL(ata_exec_command);
4903EXPORT_SYMBOL_GPL(ata_port_start);
4904EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 4905EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4
LT		 4906EXPORT_SYMBOL_GPL(ata_interrupt);
4907EXPORT_SYMBOL_GPL(ata_qc_prep);
4908EXPORT_SYMBOL_GPL(ata_bmdma_setup);
4909EXPORT_SYMBOL_GPL(ata_bmdma_start);
4910EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
4911EXPORT_SYMBOL_GPL(ata_bmdma_status);
4912EXPORT_SYMBOL_GPL(ata_bmdma_stop);
4913EXPORT_SYMBOL_GPL(ata_port_probe);
4914EXPORT_SYMBOL_GPL(sata_phy_reset);
4915EXPORT_SYMBOL_GPL(__sata_phy_reset);
4916EXPORT_SYMBOL_GPL(ata_bus_reset);
4917EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 4918EXPORT_SYMBOL_GPL(ata_ratelimit);
1da177e4
LT		 4919EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
4920EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
4921EXPORT_SYMBOL_GPL(ata_scsi_error);
4922EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
4923EXPORT_SYMBOL_GPL(ata_scsi_release);
4924EXPORT_SYMBOL_GPL(ata_host_intr);
4925EXPORT_SYMBOL_GPL(ata_dev_classify);
4926EXPORT_SYMBOL_GPL(ata_dev_id_string);
6f2f3812 4927EXPORT_SYMBOL_GPL(ata_dev_config);
1da177e4
LT		 4928EXPORT_SYMBOL_GPL(ata_scsi_simulate);
4929
452503f9
AC		 4930EXPORT_SYMBOL_GPL(ata_timing_compute);
4931EXPORT_SYMBOL_GPL(ata_timing_merge);
4932
1da177e4
LT		 4933#ifdef CONFIG_PCI
4934EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 4935EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT		 4936EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
4937EXPORT_SYMBOL_GPL(ata_pci_init_one);
4938EXPORT_SYMBOL_GPL(ata_pci_remove_one);
4939#endif /* CONFIG_PCI */
Linux kernel - Deliverables
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