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[PATCH] libata-ncq: implement ap->qc_active, ap->sactive and complete helper
[deliverable/linux.git] / drivers / scsi / libata-core.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT		 33 */
34
35#include <linux/config.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/list.h>
41#include <linux/mm.h>
42#include <linux/highmem.h>
43#include <linux/spinlock.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/timer.h>
47#include <linux/interrupt.h>
48#include <linux/completion.h>
49#include <linux/suspend.h>
50#include <linux/workqueue.h>
67846b30 51#include <linux/jiffies.h>
378f058c 52#include <linux/scatterlist.h>
1da177e4 53#include <scsi/scsi.h>
1da177e4 54#include "scsi_priv.h"
193515d5 55#include <scsi/scsi_cmnd.h>
1da177e4
LT		 56#include <scsi/scsi_host.h>
57#include <linux/libata.h>
58#include <asm/io.h>
59#include <asm/semaphore.h>
60#include <asm/byteorder.h>
61
62#include "libata.h"
63
3373efd8
TH		 64static unsigned int ata_dev_init_params(struct ata_device *dev,
65 u16 heads, u16 sectors);
66static unsigned int ata_dev_set_xfermode(struct ata_device *dev);
67static void ata_dev_xfermask(struct ata_device *dev);
1da177e4
LT		 68
69static unsigned int ata_unique_id = 1;
70static struct workqueue_struct *ata_wq;
71
418dc1f5 72int atapi_enabled = 1;
1623c81e
JG		 73module_param(atapi_enabled, int, 0444);
74MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
75
95de719a
AL		 76int atapi_dmadir = 0;
77module_param(atapi_dmadir, int, 0444);
78MODULE_PARM_DESC(atapi_dmadir, "Enable ATAPI DMADIR bridge support (0=off, 1=on)");
79
c3c013a2
JG		 80int libata_fua = 0;
81module_param_named(fua, libata_fua, int, 0444);
82MODULE_PARM_DESC(fua, "FUA support (0=off, 1=on)");
83
1da177e4
LT		 84MODULE_AUTHOR("Jeff Garzik");
85MODULE_DESCRIPTION("Library module for ATA devices");
86MODULE_LICENSE("GPL");
87MODULE_VERSION(DRV_VERSION);
88
0baab86b 89
1da177e4
LT		 90/**
91 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
92 * @tf: Taskfile to convert
93 * @fis: Buffer into which data will output
94 * @pmp: Port multiplier port
95 *
96 * Converts a standard ATA taskfile to a Serial ATA
97 * FIS structure (Register - Host to Device).
98 *
99 * LOCKING:
100 * Inherited from caller.
101 */
102
057ace5e 103void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT		 104{
105 fis[0] = 0x27; /* Register - Host to Device FIS */
106 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
107 bit 7 indicates Command FIS */
108 fis[2] = tf->command;
109 fis[3] = tf->feature;
110
111 fis[4] = tf->lbal;
112 fis[5] = tf->lbam;
113 fis[6] = tf->lbah;
114 fis[7] = tf->device;
115
116 fis[8] = tf->hob_lbal;
117 fis[9] = tf->hob_lbam;
118 fis[10] = tf->hob_lbah;
119 fis[11] = tf->hob_feature;
120
121 fis[12] = tf->nsect;
122 fis[13] = tf->hob_nsect;
123 fis[14] = 0;
124 fis[15] = tf->ctl;
125
126 fis[16] = 0;
127 fis[17] = 0;
128 fis[18] = 0;
129 fis[19] = 0;
130}
131
132/**
133 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
134 * @fis: Buffer from which data will be input
135 * @tf: Taskfile to output
136 *
e12a1be6 137 * Converts a serial ATA FIS structure to a standard ATA taskfile.
1da177e4
LT		 138 *
139 * LOCKING:
140 * Inherited from caller.
141 */
142
057ace5e 143void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT		 144{
145 tf->command = fis[2]; /* status */
146 tf->feature = fis[3]; /* error */
147
148 tf->lbal = fis[4];
149 tf->lbam = fis[5];
150 tf->lbah = fis[6];
151 tf->device = fis[7];
152
153 tf->hob_lbal = fis[8];
154 tf->hob_lbam = fis[9];
155 tf->hob_lbah = fis[10];
156
157 tf->nsect = fis[12];
158 tf->hob_nsect = fis[13];
159}
160
8cbd6df1
AL		 161static const u8 ata_rw_cmds[] = {
162 /* pio multi */
163 ATA_CMD_READ_MULTI,
164 ATA_CMD_WRITE_MULTI,
165 ATA_CMD_READ_MULTI_EXT,
166 ATA_CMD_WRITE_MULTI_EXT,
9a3dccc4
TH		 167 0,
168 0,
169 0,
170 ATA_CMD_WRITE_MULTI_FUA_EXT,
8cbd6df1
AL		 171 /* pio */
172 ATA_CMD_PIO_READ,
173 ATA_CMD_PIO_WRITE,
174 ATA_CMD_PIO_READ_EXT,
175 ATA_CMD_PIO_WRITE_EXT,
9a3dccc4
TH		 176 0,
177 0,
178 0,
179 0,
8cbd6df1
AL		 180 /* dma */
181 ATA_CMD_READ,
182 ATA_CMD_WRITE,
183 ATA_CMD_READ_EXT,
9a3dccc4
TH		 184 ATA_CMD_WRITE_EXT,
185 0,
186 0,
187 0,
188 ATA_CMD_WRITE_FUA_EXT
8cbd6df1 189};
1da177e4
LT		 190
191/**
8cbd6df1
AL		 192 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
193 * @qc: command to examine and configure
1da177e4 194 *
2e9edbf8 195 * Examine the device configuration and tf->flags to calculate
8cbd6df1 196 * the proper read/write commands and protocol to use.
1da177e4
LT		 197 *
198 * LOCKING:
199 * caller.
200 */
9a3dccc4 201int ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 202{
8cbd6df1
AL		 203 struct ata_taskfile *tf = &qc->tf;
204 struct ata_device *dev = qc->dev;
9a3dccc4 205 u8 cmd;
1da177e4 206
9a3dccc4 207 int index, fua, lba48, write;
2e9edbf8 208
9a3dccc4 209 fua = (tf->flags & ATA_TFLAG_FUA) ? 4 : 0;
8cbd6df1
AL		 210 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
211 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 212
8cbd6df1
AL		 213 if (dev->flags & ATA_DFLAG_PIO) {
214 tf->protocol = ATA_PROT_PIO;
9a3dccc4 215 index = dev->multi_count ? 0 : 8;
8d238e01
AC		 216 } else if (lba48 && (qc->ap->flags & ATA_FLAG_PIO_LBA48)) {
217 /* Unable to use DMA due to host limitation */
218 tf->protocol = ATA_PROT_PIO;
0565c26d 219 index = dev->multi_count ? 0 : 8;
8cbd6df1
AL		 220 } else {
221 tf->protocol = ATA_PROT_DMA;
9a3dccc4 222 index = 16;
8cbd6df1 223 }
1da177e4 224
9a3dccc4
TH		 225 cmd = ata_rw_cmds[index + fua + lba48 + write];
226 if (cmd) {
227 tf->command = cmd;
228 return 0;
229 }
230 return -1;
1da177e4
LT		 231}
232
cb95d562
TH		 233/**
234 * ata_pack_xfermask - Pack pio, mwdma and udma masks into xfer_mask
235 * @pio_mask: pio_mask
236 * @mwdma_mask: mwdma_mask
237 * @udma_mask: udma_mask
238 *
239 * Pack @pio_mask, @mwdma_mask and @udma_mask into a single
240 * unsigned int xfer_mask.
241 *
242 * LOCKING:
243 * None.
244 *
245 * RETURNS:
246 * Packed xfer_mask.
247 */
248static unsigned int ata_pack_xfermask(unsigned int pio_mask,
249 unsigned int mwdma_mask,
250 unsigned int udma_mask)
251{
252 return ((pio_mask << ATA_SHIFT_PIO) & ATA_MASK_PIO) |
253 ((mwdma_mask << ATA_SHIFT_MWDMA) & ATA_MASK_MWDMA) |
254 ((udma_mask << ATA_SHIFT_UDMA) & ATA_MASK_UDMA);
255}
256
c0489e4e
TH		 257/**
258 * ata_unpack_xfermask - Unpack xfer_mask into pio, mwdma and udma masks
259 * @xfer_mask: xfer_mask to unpack
260 * @pio_mask: resulting pio_mask
261 * @mwdma_mask: resulting mwdma_mask
262 * @udma_mask: resulting udma_mask
263 *
264 * Unpack @xfer_mask into @pio_mask, @mwdma_mask and @udma_mask.
265 * Any NULL distination masks will be ignored.
266 */
267static void ata_unpack_xfermask(unsigned int xfer_mask,
268 unsigned int *pio_mask,
269 unsigned int *mwdma_mask,
270 unsigned int *udma_mask)
271{
272 if (pio_mask)
273 *pio_mask = (xfer_mask & ATA_MASK_PIO) >> ATA_SHIFT_PIO;
274 if (mwdma_mask)
275 *mwdma_mask = (xfer_mask & ATA_MASK_MWDMA) >> ATA_SHIFT_MWDMA;
276 if (udma_mask)
277 *udma_mask = (xfer_mask & ATA_MASK_UDMA) >> ATA_SHIFT_UDMA;
278}
279
cb95d562 280static const struct ata_xfer_ent {
be9a50c8 281 int shift, bits;
cb95d562
TH		 282 u8 base;
283} ata_xfer_tbl[] = {
284 { ATA_SHIFT_PIO, ATA_BITS_PIO, XFER_PIO_0 },
285 { ATA_SHIFT_MWDMA, ATA_BITS_MWDMA, XFER_MW_DMA_0 },
286 { ATA_SHIFT_UDMA, ATA_BITS_UDMA, XFER_UDMA_0 },
287 { -1, },
288};
289
290/**
291 * ata_xfer_mask2mode - Find matching XFER_* for the given xfer_mask
292 * @xfer_mask: xfer_mask of interest
293 *
294 * Return matching XFER_* value for @xfer_mask. Only the highest
295 * bit of @xfer_mask is considered.
296 *
297 * LOCKING:
298 * None.
299 *
300 * RETURNS:
301 * Matching XFER_* value, 0 if no match found.
302 */
303static u8 ata_xfer_mask2mode(unsigned int xfer_mask)
304{
305 int highbit = fls(xfer_mask) - 1;
306 const struct ata_xfer_ent *ent;
307
308 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
309 if (highbit >= ent->shift && highbit < ent->shift + ent->bits)
310 return ent->base + highbit - ent->shift;
311 return 0;
312}
313
314/**
315 * ata_xfer_mode2mask - Find matching xfer_mask for XFER_*
316 * @xfer_mode: XFER_* of interest
317 *
318 * Return matching xfer_mask for @xfer_mode.
319 *
320 * LOCKING:
321 * None.
322 *
323 * RETURNS:
324 * Matching xfer_mask, 0 if no match found.
325 */
326static unsigned int ata_xfer_mode2mask(u8 xfer_mode)
327{
328 const struct ata_xfer_ent *ent;
329
330 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
331 if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits)
332 return 1 << (ent->shift + xfer_mode - ent->base);
333 return 0;
334}
335
336/**
337 * ata_xfer_mode2shift - Find matching xfer_shift for XFER_*
338 * @xfer_mode: XFER_* of interest
339 *
340 * Return matching xfer_shift for @xfer_mode.
341 *
342 * LOCKING:
343 * None.
344 *
345 * RETURNS:
346 * Matching xfer_shift, -1 if no match found.
347 */
348static int ata_xfer_mode2shift(unsigned int xfer_mode)
349{
350 const struct ata_xfer_ent *ent;
351
352 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
353 if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits)
354 return ent->shift;
355 return -1;
356}
357
1da177e4 358/**
1da7b0d0
TH		 359 * ata_mode_string - convert xfer_mask to string
360 * @xfer_mask: mask of bits supported; only highest bit counts.
1da177e4
LT		 361 *
362 * Determine string which represents the highest speed
1da7b0d0 363 * (highest bit in @modemask).
1da177e4
LT		 364 *
365 * LOCKING:
366 * None.
367 *
368 * RETURNS:
369 * Constant C string representing highest speed listed in
1da7b0d0 370 * @mode_mask, or the constant C string "<n/a>".
1da177e4 371 */
1da7b0d0 372static const char *ata_mode_string(unsigned int xfer_mask)
1da177e4 373{
75f554bc
TH		 374 static const char * const xfer_mode_str[] = {
375 "PIO0",
376 "PIO1",
377 "PIO2",
378 "PIO3",
379 "PIO4",
380 "MWDMA0",
381 "MWDMA1",
382 "MWDMA2",
383 "UDMA/16",
384 "UDMA/25",
385 "UDMA/33",
386 "UDMA/44",
387 "UDMA/66",
388 "UDMA/100",
389 "UDMA/133",
390 "UDMA7",
391 };
1da7b0d0 392 int highbit;
1da177e4 393
1da7b0d0
TH		 394 highbit = fls(xfer_mask) - 1;
395 if (highbit >= 0 && highbit < ARRAY_SIZE(xfer_mode_str))
396 return xfer_mode_str[highbit];
1da177e4 397 return "<n/a>";
1da177e4
LT		 398}
399
4c360c81
TH		 400static const char *sata_spd_string(unsigned int spd)
401{
402 static const char * const spd_str[] = {
403 "1.5 Gbps",
404 "3.0 Gbps",
405 };
406
407 if (spd == 0 || (spd - 1) >= ARRAY_SIZE(spd_str))
408 return "<unknown>";
409 return spd_str[spd - 1];
410}
411
3373efd8 412void ata_dev_disable(struct ata_device *dev)
0b8efb0a 413{
e1211e3f 414 if (ata_dev_enabled(dev)) {
f15a1daf 415 ata_dev_printk(dev, KERN_WARNING, "disabled\n");
0b8efb0a
TH		 416 dev->class++;
417 }
418}
419
1da177e4
LT		 420/**
421 * ata_pio_devchk - PATA device presence detection
422 * @ap: ATA channel to examine
423 * @device: Device to examine (starting at zero)
424 *
425 * This technique was originally described in
426 * Hale Landis's ATADRVR (www.ata-atapi.com), and
427 * later found its way into the ATA/ATAPI spec.
428 *
429 * Write a pattern to the ATA shadow registers,
430 * and if a device is present, it will respond by
431 * correctly storing and echoing back the
432 * ATA shadow register contents.
433 *
434 * LOCKING:
435 * caller.
436 */
437
438static unsigned int ata_pio_devchk(struct ata_port *ap,
439 unsigned int device)
440{
441 struct ata_ioports *ioaddr = &ap->ioaddr;
442 u8 nsect, lbal;
443
444 ap->ops->dev_select(ap, device);
445
446 outb(0x55, ioaddr->nsect_addr);
447 outb(0xaa, ioaddr->lbal_addr);
448
449 outb(0xaa, ioaddr->nsect_addr);
450 outb(0x55, ioaddr->lbal_addr);
451
452 outb(0x55, ioaddr->nsect_addr);
453 outb(0xaa, ioaddr->lbal_addr);
454
455 nsect = inb(ioaddr->nsect_addr);
456 lbal = inb(ioaddr->lbal_addr);
457
458 if ((nsect == 0x55) && (lbal == 0xaa))
459 return 1; /* we found a device */
460
461 return 0; /* nothing found */
462}
463
464/**
465 * ata_mmio_devchk - PATA device presence detection
466 * @ap: ATA channel to examine
467 * @device: Device to examine (starting at zero)
468 *
469 * This technique was originally described in
470 * Hale Landis's ATADRVR (www.ata-atapi.com), and
471 * later found its way into the ATA/ATAPI spec.
472 *
473 * Write a pattern to the ATA shadow registers,
474 * and if a device is present, it will respond by
475 * correctly storing and echoing back the
476 * ATA shadow register contents.
477 *
478 * LOCKING:
479 * caller.
480 */
481
482static unsigned int ata_mmio_devchk(struct ata_port *ap,
483 unsigned int device)
484{
485 struct ata_ioports *ioaddr = &ap->ioaddr;
486 u8 nsect, lbal;
487
488 ap->ops->dev_select(ap, device);
489
490 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
491 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
492
493 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
494 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
495
496 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
497 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
498
499 nsect = readb((void __iomem *) ioaddr->nsect_addr);
500 lbal = readb((void __iomem *) ioaddr->lbal_addr);
501
502 if ((nsect == 0x55) && (lbal == 0xaa))
503 return 1; /* we found a device */
504
505 return 0; /* nothing found */
506}
507
508/**
509 * ata_devchk - PATA device presence detection
510 * @ap: ATA channel to examine
511 * @device: Device to examine (starting at zero)
512 *
513 * Dispatch ATA device presence detection, depending
514 * on whether we are using PIO or MMIO to talk to the
515 * ATA shadow registers.
516 *
517 * LOCKING:
518 * caller.
519 */
520
521static unsigned int ata_devchk(struct ata_port *ap,
522 unsigned int device)
523{
524 if (ap->flags & ATA_FLAG_MMIO)
525 return ata_mmio_devchk(ap, device);
526 return ata_pio_devchk(ap, device);
527}
528
529/**
530 * ata_dev_classify - determine device type based on ATA-spec signature
531 * @tf: ATA taskfile register set for device to be identified
532 *
533 * Determine from taskfile register contents whether a device is
534 * ATA or ATAPI, as per "Signature and persistence" section
535 * of ATA/PI spec (volume 1, sect 5.14).
536 *
537 * LOCKING:
538 * None.
539 *
540 * RETURNS:
541 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
542 * the event of failure.
543 */
544
057ace5e 545unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT		 546{
547 /* Apple's open source Darwin code hints that some devices only
548 * put a proper signature into the LBA mid/high registers,
549 * So, we only check those. It's sufficient for uniqueness.
550 */
551
552 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
553 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
554 DPRINTK("found ATA device by sig\n");
555 return ATA_DEV_ATA;
556 }
557
558 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
559 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
560 DPRINTK("found ATAPI device by sig\n");
561 return ATA_DEV_ATAPI;
562 }
563
564 DPRINTK("unknown device\n");
565 return ATA_DEV_UNKNOWN;
566}
567
568/**
569 * ata_dev_try_classify - Parse returned ATA device signature
570 * @ap: ATA channel to examine
571 * @device: Device to examine (starting at zero)
b4dc7623 572 * @r_err: Value of error register on completion
1da177e4
LT		 573 *
574 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
575 * an ATA/ATAPI-defined set of values is placed in the ATA
576 * shadow registers, indicating the results of device detection
577 * and diagnostics.
578 *
579 * Select the ATA device, and read the values from the ATA shadow
580 * registers. Then parse according to the Error register value,
581 * and the spec-defined values examined by ata_dev_classify().
582 *
583 * LOCKING:
584 * caller.
b4dc7623
TH		 585 *
586 * RETURNS:
587 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1da177e4
LT		 588 */
589
b4dc7623
TH		 590static unsigned int
591ata_dev_try_classify(struct ata_port *ap, unsigned int device, u8 *r_err)
1da177e4 592{
1da177e4
LT		 593 struct ata_taskfile tf;
594 unsigned int class;
595 u8 err;
596
597 ap->ops->dev_select(ap, device);
598
599 memset(&tf, 0, sizeof(tf));
600
1da177e4 601 ap->ops->tf_read(ap, &tf);
0169e284 602 err = tf.feature;
b4dc7623
TH		 603 if (r_err)
604 *r_err = err;
1da177e4
LT		 605
606 /* see if device passed diags */
607 if (err == 1)
608 /* do nothing */ ;
609 else if ((device == 0) && (err == 0x81))
610 /* do nothing */ ;
611 else
b4dc7623 612 return ATA_DEV_NONE;
1da177e4 613
b4dc7623 614 /* determine if device is ATA or ATAPI */
1da177e4 615 class = ata_dev_classify(&tf);
b4dc7623 616
1da177e4 617 if (class == ATA_DEV_UNKNOWN)
b4dc7623 618 return ATA_DEV_NONE;
1da177e4 619 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
b4dc7623
TH		 620 return ATA_DEV_NONE;
621 return class;
1da177e4
LT		 622}
623
624/**
6a62a04d 625 * ata_id_string - Convert IDENTIFY DEVICE page into string
1da177e4
LT		 626 * @id: IDENTIFY DEVICE results we will examine
627 * @s: string into which data is output
628 * @ofs: offset into identify device page
629 * @len: length of string to return. must be an even number.
630 *
631 * The strings in the IDENTIFY DEVICE page are broken up into
632 * 16-bit chunks. Run through the string, and output each
633 * 8-bit chunk linearly, regardless of platform.
634 *
635 * LOCKING:
636 * caller.
637 */
638
6a62a04d
TH		 639void ata_id_string(const u16 *id, unsigned char *s,
640 unsigned int ofs, unsigned int len)
1da177e4
LT		 641{
642 unsigned int c;
643
644 while (len > 0) {
645 c = id[ofs] >> 8;
646 *s = c;
647 s++;
648
649 c = id[ofs] & 0xff;
650 *s = c;
651 s++;
652
653 ofs++;
654 len -= 2;
655 }
656}
657
0e949ff3 658/**
6a62a04d 659 * ata_id_c_string - Convert IDENTIFY DEVICE page into C string
0e949ff3
TH		 660 * @id: IDENTIFY DEVICE results we will examine
661 * @s: string into which data is output
662 * @ofs: offset into identify device page
663 * @len: length of string to return. must be an odd number.
664 *
6a62a04d 665 * This function is identical to ata_id_string except that it
0e949ff3
TH		 666 * trims trailing spaces and terminates the resulting string with
667 * null. @len must be actual maximum length (even number) + 1.
668 *
669 * LOCKING:
670 * caller.
671 */
6a62a04d
TH		 672void ata_id_c_string(const u16 *id, unsigned char *s,
673 unsigned int ofs, unsigned int len)
0e949ff3
TH		 674{
675 unsigned char *p;
676
677 WARN_ON(!(len & 1));
678
6a62a04d 679 ata_id_string(id, s, ofs, len - 1);
0e949ff3
TH		 680
681 p = s + strnlen(s, len - 1);
682 while (p > s && p[-1] == ' ')
683 p--;
684 *p = '\0';
685}
0baab86b 686
2940740b
TH		 687static u64 ata_id_n_sectors(const u16 *id)
688{
689 if (ata_id_has_lba(id)) {
690 if (ata_id_has_lba48(id))
691 return ata_id_u64(id, 100);
692 else
693 return ata_id_u32(id, 60);
694 } else {
695 if (ata_id_current_chs_valid(id))
696 return ata_id_u32(id, 57);
697 else
698 return id[1] * id[3] * id[6];
699 }
700}
701
0baab86b
EF		 702/**
703 * ata_noop_dev_select - Select device 0/1 on ATA bus
704 * @ap: ATA channel to manipulate
705 * @device: ATA device (numbered from zero) to select
706 *
707 * This function performs no actual function.
708 *
709 * May be used as the dev_select() entry in ata_port_operations.
710 *
711 * LOCKING:
712 * caller.
713 */
1da177e4
LT		 714void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
715{
716}
717
0baab86b 718
1da177e4
LT		 719/**
720 * ata_std_dev_select - Select device 0/1 on ATA bus
721 * @ap: ATA channel to manipulate
722 * @device: ATA device (numbered from zero) to select
723 *
724 * Use the method defined in the ATA specification to
725 * make either device 0, or device 1, active on the
0baab86b
EF		 726 * ATA channel. Works with both PIO and MMIO.
727 *
728 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT		 729 *
730 * LOCKING:
731 * caller.
732 */
733
734void ata_std_dev_select (struct ata_port *ap, unsigned int device)
735{
736 u8 tmp;
737
738 if (device == 0)
739 tmp = ATA_DEVICE_OBS;
740 else
741 tmp = ATA_DEVICE_OBS | ATA_DEV1;
742
743 if (ap->flags & ATA_FLAG_MMIO) {
744 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
745 } else {
746 outb(tmp, ap->ioaddr.device_addr);
747 }
748 ata_pause(ap); /* needed; also flushes, for mmio */
749}
750
751/**
752 * ata_dev_select - Select device 0/1 on ATA bus
753 * @ap: ATA channel to manipulate
754 * @device: ATA device (numbered from zero) to select
755 * @wait: non-zero to wait for Status register BSY bit to clear
756 * @can_sleep: non-zero if context allows sleeping
757 *
758 * Use the method defined in the ATA specification to
759 * make either device 0, or device 1, active on the
760 * ATA channel.
761 *
762 * This is a high-level version of ata_std_dev_select(),
763 * which additionally provides the services of inserting
764 * the proper pauses and status polling, where needed.
765 *
766 * LOCKING:
767 * caller.
768 */
769
770void ata_dev_select(struct ata_port *ap, unsigned int device,
771 unsigned int wait, unsigned int can_sleep)
772{
773 VPRINTK("ENTER, ata%u: device %u, wait %u\n",
774 ap->id, device, wait);
775
776 if (wait)
777 ata_wait_idle(ap);
778
779 ap->ops->dev_select(ap, device);
780
781 if (wait) {
782 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
783 msleep(150);
784 ata_wait_idle(ap);
785 }
786}
787
788/**
789 * ata_dump_id - IDENTIFY DEVICE info debugging output
0bd3300a 790 * @id: IDENTIFY DEVICE page to dump
1da177e4 791 *
0bd3300a
TH		 792 * Dump selected 16-bit words from the given IDENTIFY DEVICE
793 * page.
1da177e4
LT		 794 *
795 * LOCKING:
796 * caller.
797 */
798
0bd3300a 799static inline void ata_dump_id(const u16 *id)
1da177e4
LT		 800{
801 DPRINTK("49==0x%04x "
802 "53==0x%04x "
803 "63==0x%04x "
804 "64==0x%04x "
805 "75==0x%04x \n",
0bd3300a
TH		 806 id[49],
807 id[53],
808 id[63],
809 id[64],
810 id[75]);
1da177e4
LT		 811 DPRINTK("80==0x%04x "
812 "81==0x%04x "
813 "82==0x%04x "
814 "83==0x%04x "
815 "84==0x%04x \n",
0bd3300a
TH		 816 id[80],
817 id[81],
818 id[82],
819 id[83],
820 id[84]);
1da177e4
LT		 821 DPRINTK("88==0x%04x "
822 "93==0x%04x\n",
0bd3300a
TH		 823 id[88],
824 id[93]);
1da177e4
LT		 825}
826
cb95d562
TH		 827/**
828 * ata_id_xfermask - Compute xfermask from the given IDENTIFY data
829 * @id: IDENTIFY data to compute xfer mask from
830 *
831 * Compute the xfermask for this device. This is not as trivial
832 * as it seems if we must consider early devices correctly.
833 *
834 * FIXME: pre IDE drive timing (do we care ?).
835 *
836 * LOCKING:
837 * None.
838 *
839 * RETURNS:
840 * Computed xfermask
841 */
842static unsigned int ata_id_xfermask(const u16 *id)
843{
844 unsigned int pio_mask, mwdma_mask, udma_mask;
845
846 /* Usual case. Word 53 indicates word 64 is valid */
847 if (id[ATA_ID_FIELD_VALID] & (1 << 1)) {
848 pio_mask = id[ATA_ID_PIO_MODES] & 0x03;
849 pio_mask <<= 3;
850 pio_mask |= 0x7;
851 } else {
852 /* If word 64 isn't valid then Word 51 high byte holds
853 * the PIO timing number for the maximum. Turn it into
854 * a mask.
855 */
856 pio_mask = (2 << (id[ATA_ID_OLD_PIO_MODES] & 0xFF)) - 1 ;
857
858 /* But wait.. there's more. Design your standards by
859 * committee and you too can get a free iordy field to
860 * process. However its the speeds not the modes that
861 * are supported... Note drivers using the timing API
862 * will get this right anyway
863 */
864 }
865
866 mwdma_mask = id[ATA_ID_MWDMA_MODES] & 0x07;
fb21f0d0
TH		 867
868 udma_mask = 0;
869 if (id[ATA_ID_FIELD_VALID] & (1 << 2))
870 udma_mask = id[ATA_ID_UDMA_MODES] & 0xff;
cb95d562
TH		 871
872 return ata_pack_xfermask(pio_mask, mwdma_mask, udma_mask);
873}
874
86e45b6b
TH		 875/**
876 * ata_port_queue_task - Queue port_task
877 * @ap: The ata_port to queue port_task for
878 *
879 * Schedule @fn(@data) for execution after @delay jiffies using
880 * port_task. There is one port_task per port and it's the
881 * user(low level driver)'s responsibility to make sure that only
882 * one task is active at any given time.
883 *
884 * libata core layer takes care of synchronization between
885 * port_task and EH. ata_port_queue_task() may be ignored for EH
886 * synchronization.
887 *
888 * LOCKING:
889 * Inherited from caller.
890 */
891void ata_port_queue_task(struct ata_port *ap, void (*fn)(void *), void *data,
892 unsigned long delay)
893{
894 int rc;
895
2e755f68 896 if (ap->flags & ATA_FLAG_FLUSH_PORT_TASK)
86e45b6b
TH		 897 return;
898
899 PREPARE_WORK(&ap->port_task, fn, data);
900
901 if (!delay)
902 rc = queue_work(ata_wq, &ap->port_task);
903 else
904 rc = queue_delayed_work(ata_wq, &ap->port_task, delay);
905
906 /* rc == 0 means that another user is using port task */
907 WARN_ON(rc == 0);
908}
909
910/**
911 * ata_port_flush_task - Flush port_task
912 * @ap: The ata_port to flush port_task for
913 *
914 * After this function completes, port_task is guranteed not to
915 * be running or scheduled.
916 *
917 * LOCKING:
918 * Kernel thread context (may sleep)
919 */
920void ata_port_flush_task(struct ata_port *ap)
921{
922 unsigned long flags;
923
924 DPRINTK("ENTER\n");
925
926 spin_lock_irqsave(&ap->host_set->lock, flags);
2e755f68 927 ap->flags |= ATA_FLAG_FLUSH_PORT_TASK;
86e45b6b
TH		 928 spin_unlock_irqrestore(&ap->host_set->lock, flags);
929
930 DPRINTK("flush #1\n");
931 flush_workqueue(ata_wq);
932
933 /*
934 * At this point, if a task is running, it's guaranteed to see
935 * the FLUSH flag; thus, it will never queue pio tasks again.
936 * Cancel and flush.
937 */
938 if (!cancel_delayed_work(&ap->port_task)) {
939 DPRINTK("flush #2\n");
940 flush_workqueue(ata_wq);
941 }
942
943 spin_lock_irqsave(&ap->host_set->lock, flags);
2e755f68 944 ap->flags &= ~ATA_FLAG_FLUSH_PORT_TASK;
86e45b6b
TH		 945 spin_unlock_irqrestore(&ap->host_set->lock, flags);
946
947 DPRINTK("EXIT\n");
948}
949
77853bf2 950void ata_qc_complete_internal(struct ata_queued_cmd *qc)
a2a7a662 951{
77853bf2 952 struct completion *waiting = qc->private_data;
a2a7a662 953
a2a7a662 954 complete(waiting);
a2a7a662
TH		 955}
956
957/**
958 * ata_exec_internal - execute libata internal command
a2a7a662
TH		 959 * @dev: Device to which the command is sent
960 * @tf: Taskfile registers for the command and the result
d69cf37d 961 * @cdb: CDB for packet command
a2a7a662
TH		 962 * @dma_dir: Data tranfer direction of the command
963 * @buf: Data buffer of the command
964 * @buflen: Length of data buffer
965 *
966 * Executes libata internal command with timeout. @tf contains
967 * command on entry and result on return. Timeout and error
968 * conditions are reported via return value. No recovery action
969 * is taken after a command times out. It's caller's duty to
970 * clean up after timeout.
971 *
972 * LOCKING:
973 * None. Should be called with kernel context, might sleep.
974 */
975
3373efd8 976unsigned ata_exec_internal(struct ata_device *dev,
1ad8e7f9
TH		 977 struct ata_taskfile *tf, const u8 *cdb,
978 int dma_dir, void *buf, unsigned int buflen)
a2a7a662 979{
3373efd8 980 struct ata_port *ap = dev->ap;
a2a7a662
TH		 981 u8 command = tf->command;
982 struct ata_queued_cmd *qc;
2ab7db1f 983 unsigned int tag, preempted_tag;
dedaf2b0 984 u32 preempted_sactive, preempted_qc_active;
a2a7a662
TH		 985 DECLARE_COMPLETION(wait);
986 unsigned long flags;
77853bf2 987 unsigned int err_mask;
d95a717f 988 int rc;
a2a7a662
TH		 989
990 spin_lock_irqsave(&ap->host_set->lock, flags);
991
e3180499
TH		 992 /* no internal command while frozen */
993 if (ap->flags & ATA_FLAG_FROZEN) {
994 spin_unlock_irqrestore(&ap->host_set->lock, flags);
995 return AC_ERR_SYSTEM;
996 }
997
2ab7db1f 998 /* initialize internal qc */
a2a7a662 999
2ab7db1f
TH		 1000 /* XXX: Tag 0 is used for drivers with legacy EH as some
1001 * drivers choke if any other tag is given. This breaks
1002 * ata_tag_internal() test for those drivers. Don't use new
1003 * EH stuff without converting to it.
1004 */
1005 if (ap->ops->error_handler)
1006 tag = ATA_TAG_INTERNAL;
1007 else
1008 tag = 0;
1009
6cec4a39 1010 if (test_and_set_bit(tag, &ap->qc_allocated))
2ab7db1f 1011 BUG();
f69499f4 1012 qc = __ata_qc_from_tag(ap, tag);
2ab7db1f
TH		 1013
1014 qc->tag = tag;
1015 qc->scsicmd = NULL;
1016 qc->ap = ap;
1017 qc->dev = dev;
1018 ata_qc_reinit(qc);
1019
1020 preempted_tag = ap->active_tag;
dedaf2b0
TH		 1021 preempted_sactive = ap->sactive;
1022 preempted_qc_active = ap->qc_active;
2ab7db1f 1023 ap->active_tag = ATA_TAG_POISON;
dedaf2b0
TH		 1024 ap->sactive = 0;
1025 ap->qc_active = 0;
2ab7db1f
TH		 1026
1027 /* prepare & issue qc */
a2a7a662 1028 qc->tf = *tf;
d69cf37d
TH		 1029 if (cdb)
1030 memcpy(qc->cdb, cdb, ATAPI_CDB_LEN);
e61e0672 1031 qc->flags |= ATA_QCFLAG_RESULT_TF;
a2a7a662
TH		 1032 qc->dma_dir = dma_dir;
1033 if (dma_dir != DMA_NONE) {
1034 ata_sg_init_one(qc, buf, buflen);
1035 qc->nsect = buflen / ATA_SECT_SIZE;
1036 }
1037
77853bf2 1038 qc->private_data = &wait;
a2a7a662
TH		 1039 qc->complete_fn = ata_qc_complete_internal;
1040
8e0e694a 1041 ata_qc_issue(qc);
a2a7a662
TH		 1042
1043 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1044
d95a717f
TH		 1045 rc = wait_for_completion_timeout(&wait, ATA_TMOUT_INTERNAL);
1046
1047 ata_port_flush_task(ap);
41ade50c 1048
d95a717f 1049 if (!rc) {
a2a7a662
TH		 1050 spin_lock_irqsave(&ap->host_set->lock, flags);
1051
1052 /* We're racing with irq here. If we lose, the
1053 * following test prevents us from completing the qc
d95a717f
TH		 1054 * twice. If we win, the port is frozen and will be
1055 * cleaned up by ->post_internal_cmd().
a2a7a662 1056 */
77853bf2 1057 if (qc->flags & ATA_QCFLAG_ACTIVE) {
d95a717f
TH		 1058 qc->err_mask |= AC_ERR_TIMEOUT;
1059
1060 if (ap->ops->error_handler)
1061 ata_port_freeze(ap);
1062 else
1063 ata_qc_complete(qc);
f15a1daf
TH		 1064
1065 ata_dev_printk(dev, KERN_WARNING,
1066 "qc timeout (cmd 0x%x)\n", command);
a2a7a662
TH		 1067 }
1068
1069 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1070 }
1071
d95a717f
TH		 1072 /* do post_internal_cmd */
1073 if (ap->ops->post_internal_cmd)
1074 ap->ops->post_internal_cmd(qc);
1075
1076 if (qc->flags & ATA_QCFLAG_FAILED && !qc->err_mask) {
1077 ata_dev_printk(dev, KERN_WARNING, "zero err_mask for failed "
1078 "internal command, assuming AC_ERR_OTHER\n");
1079 qc->err_mask |= AC_ERR_OTHER;
1080 }
1081
15869303
TH		 1082 /* finish up */
1083 spin_lock_irqsave(&ap->host_set->lock, flags);
1084
e61e0672 1085 *tf = qc->result_tf;
77853bf2
TH		 1086 err_mask = qc->err_mask;
1087
1088 ata_qc_free(qc);
2ab7db1f 1089 ap->active_tag = preempted_tag;
dedaf2b0
TH		 1090 ap->sactive = preempted_sactive;
1091 ap->qc_active = preempted_qc_active;
77853bf2 1092
1f7dd3e9
TH		 1093 /* XXX - Some LLDDs (sata_mv) disable port on command failure.
1094 * Until those drivers are fixed, we detect the condition
1095 * here, fail the command with AC_ERR_SYSTEM and reenable the
1096 * port.
1097 *
1098 * Note that this doesn't change any behavior as internal
1099 * command failure results in disabling the device in the
1100 * higher layer for LLDDs without new reset/EH callbacks.
1101 *
1102 * Kill the following code as soon as those drivers are fixed.
1103 */
198e0fed 1104 if (ap->flags & ATA_FLAG_DISABLED) {
1f7dd3e9
TH		 1105 err_mask |= AC_ERR_SYSTEM;
1106 ata_port_probe(ap);
1107 }
1108
15869303
TH		 1109 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1110
77853bf2 1111 return err_mask;
a2a7a662
TH		 1112}
1113
1bc4ccff
AC		 1114/**
1115 * ata_pio_need_iordy - check if iordy needed
1116 * @adev: ATA device
1117 *
1118 * Check if the current speed of the device requires IORDY. Used
1119 * by various controllers for chip configuration.
1120 */
1121
1122unsigned int ata_pio_need_iordy(const struct ata_device *adev)
1123{
1124 int pio;
1125 int speed = adev->pio_mode - XFER_PIO_0;
1126
1127 if (speed < 2)
1128 return 0;
1129 if (speed > 2)
1130 return 1;
2e9edbf8 1131
1bc4ccff
AC		 1132 /* If we have no drive specific rule, then PIO 2 is non IORDY */
1133
1134 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE */
1135 pio = adev->id[ATA_ID_EIDE_PIO];
1136 /* Is the speed faster than the drive allows non IORDY ? */
1137 if (pio) {
1138 /* This is cycle times not frequency - watch the logic! */
1139 if (pio > 240) /* PIO2 is 240nS per cycle */
1140 return 1;
1141 return 0;
1142 }
1143 }
1144 return 0;
1145}
1146
1da177e4 1147/**
49016aca 1148 * ata_dev_read_id - Read ID data from the specified device
49016aca
TH		 1149 * @dev: target device
1150 * @p_class: pointer to class of the target device (may be changed)
1151 * @post_reset: is this read ID post-reset?
fe635c7e 1152 * @id: buffer to read IDENTIFY data into
1da177e4 1153 *
49016aca
TH		 1154 * Read ID data from the specified device. ATA_CMD_ID_ATA is
1155 * performed on ATA devices and ATA_CMD_ID_ATAPI on ATAPI
aec5c3c1
TH		 1156 * devices. This function also issues ATA_CMD_INIT_DEV_PARAMS
1157 * for pre-ATA4 drives.
1da177e4
LT		 1158 *
1159 * LOCKING:
49016aca
TH		 1160 * Kernel thread context (may sleep)
1161 *
1162 * RETURNS:
1163 * 0 on success, -errno otherwise.
1da177e4 1164 */
3373efd8
TH		 1165static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
1166 int post_reset, u16 *id)
1da177e4 1167{
3373efd8 1168 struct ata_port *ap = dev->ap;
49016aca 1169 unsigned int class = *p_class;
a0123703 1170 struct ata_taskfile tf;
49016aca
TH		 1171 unsigned int err_mask = 0;
1172 const char *reason;
1173 int rc;
1da177e4 1174
49016aca 1175 DPRINTK("ENTER, host %u, dev %u\n", ap->id, dev->devno);
1da177e4 1176
49016aca 1177 ata_dev_select(ap, dev->devno, 1, 1); /* select device 0/1 */
1da177e4 1178
49016aca 1179 retry:
3373efd8 1180 ata_tf_init(dev, &tf);
a0123703 1181
49016aca
TH		 1182 switch (class) {
1183 case ATA_DEV_ATA:
a0123703 1184 tf.command = ATA_CMD_ID_ATA;
49016aca
TH		 1185 break;
1186 case ATA_DEV_ATAPI:
a0123703 1187 tf.command = ATA_CMD_ID_ATAPI;
49016aca
TH		 1188 break;
1189 default:
1190 rc = -ENODEV;
1191 reason = "unsupported class";
1192 goto err_out;
1da177e4
LT		 1193 }
1194
a0123703 1195 tf.protocol = ATA_PROT_PIO;
1da177e4 1196
3373efd8 1197 err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE,
49016aca 1198 id, sizeof(id[0]) * ATA_ID_WORDS);
a0123703 1199 if (err_mask) {
49016aca
TH		 1200 rc = -EIO;
1201 reason = "I/O error";
1da177e4
LT		 1202 goto err_out;
1203 }
1204
49016aca 1205 swap_buf_le16(id, ATA_ID_WORDS);
1da177e4 1206
49016aca 1207 /* sanity check */
692785e7 1208 if ((class == ATA_DEV_ATA) != (ata_id_is_ata(id) | ata_id_is_cfa(id))) {
49016aca
TH		 1209 rc = -EINVAL;
1210 reason = "device reports illegal type";
1211 goto err_out;
1212 }
1213
1214 if (post_reset && class == ATA_DEV_ATA) {
1215 /*
1216 * The exact sequence expected by certain pre-ATA4 drives is:
1217 * SRST RESET
1218 * IDENTIFY
1219 * INITIALIZE DEVICE PARAMETERS
1220 * anything else..
1221 * Some drives were very specific about that exact sequence.
1222 */
1223 if (ata_id_major_version(id) < 4 || !ata_id_has_lba(id)) {
3373efd8 1224 err_mask = ata_dev_init_params(dev, id[3], id[6]);
49016aca
TH		 1225 if (err_mask) {
1226 rc = -EIO;
1227 reason = "INIT_DEV_PARAMS failed";
1228 goto err_out;
1229 }
1230
1231 /* current CHS translation info (id[53-58]) might be
1232 * changed. reread the identify device info.
1233 */
1234 post_reset = 0;
1235 goto retry;
1236 }
1237 }
1238
1239 *p_class = class;
fe635c7e 1240
49016aca
TH		 1241 return 0;
1242
1243 err_out:
f15a1daf
TH		 1244 ata_dev_printk(dev, KERN_WARNING, "failed to IDENTIFY "
1245 "(%s, err_mask=0x%x)\n", reason, err_mask);
49016aca
TH		 1246 return rc;
1247}
1248
3373efd8 1249static inline u8 ata_dev_knobble(struct ata_device *dev)
4b2f3ede 1250{
3373efd8 1251 return ((dev->ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(dev->id)));
4b2f3ede
TH		 1252}
1253
49016aca 1254/**
ffeae418 1255 * ata_dev_configure - Configure the specified ATA/ATAPI device
ffeae418 1256 * @dev: Target device to configure
4c2d721a 1257 * @print_info: Enable device info printout
ffeae418
TH		 1258 *
1259 * Configure @dev according to @dev->id. Generic and low-level
1260 * driver specific fixups are also applied.
49016aca
TH		 1261 *
1262 * LOCKING:
ffeae418
TH		 1263 * Kernel thread context (may sleep)
1264 *
1265 * RETURNS:
1266 * 0 on success, -errno otherwise
49016aca 1267 */
3373efd8 1268static int ata_dev_configure(struct ata_device *dev, int print_info)
49016aca 1269{
3373efd8 1270 struct ata_port *ap = dev->ap;
1148c3a7 1271 const u16 *id = dev->id;
ff8854b2 1272 unsigned int xfer_mask;
49016aca
TH		 1273 int i, rc;
1274
e1211e3f 1275 if (!ata_dev_enabled(dev)) {
49016aca 1276 DPRINTK("ENTER/EXIT (host %u, dev %u) -- nodev\n",
ffeae418
TH		 1277 ap->id, dev->devno);
1278 return 0;
49016aca
TH		 1279 }
1280
ffeae418 1281 DPRINTK("ENTER, host %u, dev %u\n", ap->id, dev->devno);
1da177e4 1282
c39f5ebe
TH		 1283 /* print device capabilities */
1284 if (print_info)
f15a1daf
TH		 1285 ata_dev_printk(dev, KERN_DEBUG, "cfg 49:%04x 82:%04x 83:%04x "
1286 "84:%04x 85:%04x 86:%04x 87:%04x 88:%04x\n",
1287 id[49], id[82], id[83], id[84],
1288 id[85], id[86], id[87], id[88]);
c39f5ebe 1289
208a9933 1290 /* initialize to-be-configured parameters */
ea1dd4e1 1291 dev->flags &= ~ATA_DFLAG_CFG_MASK;
208a9933
TH		 1292 dev->max_sectors = 0;
1293 dev->cdb_len = 0;
1294 dev->n_sectors = 0;
1295 dev->cylinders = 0;
1296 dev->heads = 0;
1297 dev->sectors = 0;
1298
1da177e4
LT		 1299 /*
1300 * common ATA, ATAPI feature tests
1301 */
1302
ff8854b2 1303 /* find max transfer mode; for printk only */
1148c3a7 1304 xfer_mask = ata_id_xfermask(id);
1da177e4 1305
1148c3a7 1306 ata_dump_id(id);
1da177e4
LT		 1307
1308 /* ATA-specific feature tests */
1309 if (dev->class == ATA_DEV_ATA) {
1148c3a7 1310 dev->n_sectors = ata_id_n_sectors(id);
2940740b 1311
1148c3a7 1312 if (ata_id_has_lba(id)) {
4c2d721a 1313 const char *lba_desc;
8bf62ece 1314
4c2d721a
TH		 1315 lba_desc = "LBA";
1316 dev->flags |= ATA_DFLAG_LBA;
1148c3a7 1317 if (ata_id_has_lba48(id)) {
8bf62ece 1318 dev->flags |= ATA_DFLAG_LBA48;
4c2d721a
TH		 1319 lba_desc = "LBA48";
1320 }
8bf62ece
AL		 1321
1322 /* print device info to dmesg */
4c2d721a 1323 if (print_info)
f15a1daf
TH		 1324 ata_dev_printk(dev, KERN_INFO, "ATA-%d, "
1325 "max %s, %Lu sectors: %s\n",
1326 ata_id_major_version(id),
1327 ata_mode_string(xfer_mask),
1328 (unsigned long long)dev->n_sectors,
1329 lba_desc);
ffeae418 1330 } else {
8bf62ece
AL		 1331 /* CHS */
1332
1333 /* Default translation */
1148c3a7
TH		 1334 dev->cylinders = id[1];
1335 dev->heads = id[3];
1336 dev->sectors = id[6];
8bf62ece 1337
1148c3a7 1338 if (ata_id_current_chs_valid(id)) {
8bf62ece 1339 /* Current CHS translation is valid. */
1148c3a7
TH		 1340 dev->cylinders = id[54];
1341 dev->heads = id[55];
1342 dev->sectors = id[56];
8bf62ece
AL		 1343 }
1344
1345 /* print device info to dmesg */
4c2d721a 1346 if (print_info)
f15a1daf
TH		 1347 ata_dev_printk(dev, KERN_INFO, "ATA-%d, "
1348 "max %s, %Lu sectors: CHS %u/%u/%u\n",
1349 ata_id_major_version(id),
1350 ata_mode_string(xfer_mask),
1351 (unsigned long long)dev->n_sectors,
1352 dev->cylinders, dev->heads, dev->sectors);
1da177e4
LT		 1353 }
1354
07f6f7d0
AL		 1355 if (dev->id[59] & 0x100) {
1356 dev->multi_count = dev->id[59] & 0xff;
1357 DPRINTK("ata%u: dev %u multi count %u\n",
999bb6f4 1358 ap->id, dev->devno, dev->multi_count);
07f6f7d0
AL		 1359 }
1360
6e7846e9 1361 dev->cdb_len = 16;
1da177e4
LT		 1362 }
1363
1364 /* ATAPI-specific feature tests */
2c13b7ce 1365 else if (dev->class == ATA_DEV_ATAPI) {
08a556db
AL		 1366 char *cdb_intr_string = "";
1367
1148c3a7 1368 rc = atapi_cdb_len(id);
1da177e4 1369 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
f15a1daf
TH		 1370 ata_dev_printk(dev, KERN_WARNING,
1371 "unsupported CDB len\n");
ffeae418 1372 rc = -EINVAL;
1da177e4
LT		 1373 goto err_out_nosup;
1374 }
6e7846e9 1375 dev->cdb_len = (unsigned int) rc;
1da177e4 1376
08a556db 1377 if (ata_id_cdb_intr(dev->id)) {
312f7da2 1378 dev->flags |= ATA_DFLAG_CDB_INTR;
08a556db
AL		 1379 cdb_intr_string = ", CDB intr";
1380 }
312f7da2 1381
1da177e4 1382 /* print device info to dmesg */
4c2d721a 1383 if (print_info)
12436c30
TH		 1384 ata_dev_printk(dev, KERN_INFO, "ATAPI, max %s%s\n",
1385 ata_mode_string(xfer_mask),
1386 cdb_intr_string);
1da177e4
LT		 1387 }
1388
6e7846e9
TH		 1389 ap->host->max_cmd_len = 0;
1390 for (i = 0; i < ATA_MAX_DEVICES; i++)
1391 ap->host->max_cmd_len = max_t(unsigned int,
1392 ap->host->max_cmd_len,
1393 ap->device[i].cdb_len);
1394
4b2f3ede 1395 /* limit bridge transfers to udma5, 200 sectors */
3373efd8 1396 if (ata_dev_knobble(dev)) {
4c2d721a 1397 if (print_info)
f15a1daf
TH		 1398 ata_dev_printk(dev, KERN_INFO,
1399 "applying bridge limits\n");
5a529139 1400 dev->udma_mask &= ATA_UDMA5;
4b2f3ede
TH		 1401 dev->max_sectors = ATA_MAX_SECTORS;
1402 }
1403
1404 if (ap->ops->dev_config)
1405 ap->ops->dev_config(ap, dev);
1406
1da177e4 1407 DPRINTK("EXIT, drv_stat = 0x%x\n", ata_chk_status(ap));
ffeae418 1408 return 0;
1da177e4
LT		 1409
1410err_out_nosup:
1da177e4 1411 DPRINTK("EXIT, err\n");
ffeae418 1412 return rc;
1da177e4
LT		 1413}
1414
1415/**
1416 * ata_bus_probe - Reset and probe ATA bus
1417 * @ap: Bus to probe
1418 *
0cba632b
JG		 1419 * Master ATA bus probing function. Initiates a hardware-dependent
1420 * bus reset, then attempts to identify any devices found on
1421 * the bus.
1422 *
1da177e4 1423 * LOCKING:
0cba632b 1424 * PCI/etc. bus probe sem.
1da177e4
LT		 1425 *
1426 * RETURNS:
96072e69 1427 * Zero on success, negative errno otherwise.
1da177e4
LT		 1428 */
1429
1430static int ata_bus_probe(struct ata_port *ap)
1431{
28ca5c57 1432 unsigned int classes[ATA_MAX_DEVICES];
14d2bac1
TH		 1433 int tries[ATA_MAX_DEVICES];
1434 int i, rc, down_xfermask;
e82cbdb9 1435 struct ata_device *dev;
1da177e4 1436
28ca5c57 1437 ata_port_probe(ap);
c19ba8af 1438
14d2bac1
TH		 1439 for (i = 0; i < ATA_MAX_DEVICES; i++)
1440 tries[i] = ATA_PROBE_MAX_TRIES;
1441
1442 retry:
1443 down_xfermask = 0;
1444
2044470c
TH		 1445 /* reset and determine device classes */
1446 for (i = 0; i < ATA_MAX_DEVICES; i++)
1447 classes[i] = ATA_DEV_UNKNOWN;
2061a47a 1448
2044470c 1449 if (ap->ops->probe_reset) {
c19ba8af 1450 rc = ap->ops->probe_reset(ap, classes);
28ca5c57 1451 if (rc) {
f15a1daf
TH		 1452 ata_port_printk(ap, KERN_ERR,
1453 "reset failed (errno=%d)\n", rc);
28ca5c57 1454 return rc;
c19ba8af 1455 }
28ca5c57 1456 } else {
c19ba8af
TH		 1457 ap->ops->phy_reset(ap);
1458
f8c2c420
TH		 1459 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1460 if (!(ap->flags & ATA_FLAG_DISABLED))
28ca5c57 1461 classes[i] = ap->device[i].class;
f8c2c420
TH		 1462 ap->device[i].class = ATA_DEV_UNKNOWN;
1463 }
2044470c 1464
28ca5c57
TH		 1465 ata_port_probe(ap);
1466 }
1da177e4 1467
2044470c
TH		 1468 for (i = 0; i < ATA_MAX_DEVICES; i++)
1469 if (classes[i] == ATA_DEV_UNKNOWN)
1470 classes[i] = ATA_DEV_NONE;
1471
28ca5c57 1472 /* read IDENTIFY page and configure devices */
1da177e4 1473 for (i = 0; i < ATA_MAX_DEVICES; i++) {
e82cbdb9 1474 dev = &ap->device[i];
28ca5c57 1475
ec573755
TH		 1476 if (tries[i])
1477 dev->class = classes[i];
ffeae418 1478
14d2bac1 1479 if (!ata_dev_enabled(dev))
ffeae418 1480 continue;
ffeae418 1481
3373efd8 1482 rc = ata_dev_read_id(dev, &dev->class, 1, dev->id);
14d2bac1
TH		 1483 if (rc)
1484 goto fail;
1485
3373efd8 1486 rc = ata_dev_configure(dev, 1);
14d2bac1
TH		 1487 if (rc)
1488 goto fail;
1da177e4
LT		 1489 }
1490
e82cbdb9 1491 /* configure transfer mode */
3adcebb2 1492 rc = ata_set_mode(ap, &dev);
51713d35
TH		 1493 if (rc) {
1494 down_xfermask = 1;
1495 goto fail;
e82cbdb9 1496 }
1da177e4 1497
e82cbdb9
TH		 1498 for (i = 0; i < ATA_MAX_DEVICES; i++)
1499 if (ata_dev_enabled(&ap->device[i]))
1500 return 0;
1da177e4 1501
e82cbdb9
TH		 1502 /* no device present, disable port */
1503 ata_port_disable(ap);
1da177e4 1504 ap->ops->port_disable(ap);
96072e69 1505 return -ENODEV;
14d2bac1
TH		 1506
1507 fail:
1508 switch (rc) {
1509 case -EINVAL:
1510 case -ENODEV:
1511 tries[dev->devno] = 0;
1512 break;
1513 case -EIO:
3c567b7d 1514 sata_down_spd_limit(ap);
14d2bac1
TH		 1515 /* fall through */
1516 default:
1517 tries[dev->devno]--;
1518 if (down_xfermask &&
3373efd8 1519 ata_down_xfermask_limit(dev, tries[dev->devno] == 1))
14d2bac1
TH		 1520 tries[dev->devno] = 0;
1521 }
1522
ec573755 1523 if (!tries[dev->devno]) {
3373efd8
TH		 1524 ata_down_xfermask_limit(dev, 1);
1525 ata_dev_disable(dev);
ec573755
TH		 1526 }
1527
14d2bac1 1528 goto retry;
1da177e4
LT		 1529}
1530
1531/**
0cba632b
JG		 1532 * ata_port_probe - Mark port as enabled
1533 * @ap: Port for which we indicate enablement
1da177e4 1534 *
0cba632b
JG		 1535 * Modify @ap data structure such that the system
1536 * thinks that the entire port is enabled.
1537 *
1538 * LOCKING: host_set lock, or some other form of
1539 * serialization.
1da177e4
LT		 1540 */
1541
1542void ata_port_probe(struct ata_port *ap)
1543{
198e0fed 1544 ap->flags &= ~ATA_FLAG_DISABLED;
1da177e4
LT		 1545}
1546
3be680b7
TH		 1547/**
1548 * sata_print_link_status - Print SATA link status
1549 * @ap: SATA port to printk link status about
1550 *
1551 * This function prints link speed and status of a SATA link.
1552 *
1553 * LOCKING:
1554 * None.
1555 */
1556static void sata_print_link_status(struct ata_port *ap)
1557{
6d5f9732 1558 u32 sstatus, scontrol, tmp;
3be680b7 1559
81952c54 1560 if (sata_scr_read(ap, SCR_STATUS, &sstatus))
3be680b7 1561 return;
81952c54 1562 sata_scr_read(ap, SCR_CONTROL, &scontrol);
3be680b7 1563
81952c54 1564 if (ata_port_online(ap)) {
3be680b7 1565 tmp = (sstatus >> 4) & 0xf;
f15a1daf
TH		 1566 ata_port_printk(ap, KERN_INFO,
1567 "SATA link up %s (SStatus %X SControl %X)\n",
1568 sata_spd_string(tmp), sstatus, scontrol);
3be680b7 1569 } else {
f15a1daf
TH		 1570 ata_port_printk(ap, KERN_INFO,
1571 "SATA link down (SStatus %X SControl %X)\n",
1572 sstatus, scontrol);
3be680b7
TH		 1573 }
1574}
1575
1da177e4 1576/**
780a87f7
JG		 1577 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1578 * @ap: SATA port associated with target SATA PHY.
1da177e4 1579 *
780a87f7
JG		 1580 * This function issues commands to standard SATA Sxxx
1581 * PHY registers, to wake up the phy (and device), and
1582 * clear any reset condition.
1da177e4
LT		 1583 *
1584 * LOCKING:
0cba632b 1585 * PCI/etc. bus probe sem.
1da177e4
LT		 1586 *
1587 */
1588void __sata_phy_reset(struct ata_port *ap)
1589{
1590 u32 sstatus;
1591 unsigned long timeout = jiffies + (HZ * 5);
1592
1593 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e 1594 /* issue phy wake/reset */
81952c54 1595 sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH		 1596 /* Couldn't find anything in SATA I/II specs, but
1597 * AHCI-1.1 10.4.2 says at least 1 ms. */
1598 mdelay(1);
1da177e4 1599 }
81952c54
TH		 1600 /* phy wake/clear reset */
1601 sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
1da177e4
LT		 1602
1603 /* wait for phy to become ready, if necessary */
1604 do {
1605 msleep(200);
81952c54 1606 sata_scr_read(ap, SCR_STATUS, &sstatus);
1da177e4
LT		 1607 if ((sstatus & 0xf) != 1)
1608 break;
1609 } while (time_before(jiffies, timeout));
1610
3be680b7
TH		 1611 /* print link status */
1612 sata_print_link_status(ap);
656563e3 1613
3be680b7 1614 /* TODO: phy layer with polling, timeouts, etc. */
81952c54 1615 if (!ata_port_offline(ap))
1da177e4 1616 ata_port_probe(ap);
3be680b7 1617 else
1da177e4 1618 ata_port_disable(ap);
1da177e4 1619
198e0fed 1620 if (ap->flags & ATA_FLAG_DISABLED)
1da177e4
LT		 1621 return;
1622
1623 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1624 ata_port_disable(ap);
1625 return;
1626 }
1627
1628 ap->cbl = ATA_CBL_SATA;
1629}
1630
1631/**
780a87f7
JG		 1632 * sata_phy_reset - Reset SATA bus.
1633 * @ap: SATA port associated with target SATA PHY.
1da177e4 1634 *
780a87f7
JG		 1635 * This function resets the SATA bus, and then probes
1636 * the bus for devices.
1da177e4
LT		 1637 *
1638 * LOCKING:
0cba632b 1639 * PCI/etc. bus probe sem.
1da177e4
LT		 1640 *
1641 */
1642void sata_phy_reset(struct ata_port *ap)
1643{
1644 __sata_phy_reset(ap);
198e0fed 1645 if (ap->flags & ATA_FLAG_DISABLED)
1da177e4
LT		 1646 return;
1647 ata_bus_reset(ap);
1648}
1649
ebdfca6e
AC		 1650/**
1651 * ata_dev_pair - return other device on cable
ebdfca6e
AC		 1652 * @adev: device
1653 *
1654 * Obtain the other device on the same cable, or if none is
1655 * present NULL is returned
1656 */
2e9edbf8 1657
3373efd8 1658struct ata_device *ata_dev_pair(struct ata_device *adev)
ebdfca6e 1659{
3373efd8 1660 struct ata_port *ap = adev->ap;
ebdfca6e 1661 struct ata_device *pair = &ap->device[1 - adev->devno];
e1211e3f 1662 if (!ata_dev_enabled(pair))
ebdfca6e
AC		 1663 return NULL;
1664 return pair;
1665}
1666
1da177e4 1667/**
780a87f7
JG		 1668 * ata_port_disable - Disable port.
1669 * @ap: Port to be disabled.
1da177e4 1670 *
780a87f7
JG		 1671 * Modify @ap data structure such that the system
1672 * thinks that the entire port is disabled, and should
1673 * never attempt to probe or communicate with devices
1674 * on this port.
1675 *
1676 * LOCKING: host_set lock, or some other form of
1677 * serialization.
1da177e4
LT		 1678 */
1679
1680void ata_port_disable(struct ata_port *ap)
1681{
1682 ap->device[0].class = ATA_DEV_NONE;
1683 ap->device[1].class = ATA_DEV_NONE;
198e0fed 1684 ap->flags |= ATA_FLAG_DISABLED;
1da177e4
LT		 1685}
1686
1c3fae4d 1687/**
3c567b7d 1688 * sata_down_spd_limit - adjust SATA spd limit downward
1c3fae4d
TH		 1689 * @ap: Port to adjust SATA spd limit for
1690 *
1691 * Adjust SATA spd limit of @ap downward. Note that this
1692 * function only adjusts the limit. The change must be applied
3c567b7d 1693 * using sata_set_spd().
1c3fae4d
TH		 1694 *
1695 * LOCKING:
1696 * Inherited from caller.
1697 *
1698 * RETURNS:
1699 * 0 on success, negative errno on failure
1700 */
3c567b7d 1701int sata_down_spd_limit(struct ata_port *ap)
1c3fae4d 1702{
81952c54
TH		 1703 u32 sstatus, spd, mask;
1704 int rc, highbit;
1c3fae4d 1705
81952c54
TH		 1706 rc = sata_scr_read(ap, SCR_STATUS, &sstatus);
1707 if (rc)
1708 return rc;
1c3fae4d
TH		 1709
1710 mask = ap->sata_spd_limit;
1711 if (mask <= 1)
1712 return -EINVAL;
1713 highbit = fls(mask) - 1;
1714 mask &= ~(1 << highbit);
1715
81952c54 1716 spd = (sstatus >> 4) & 0xf;
1c3fae4d
TH		 1717 if (spd <= 1)
1718 return -EINVAL;
1719 spd--;
1720 mask &= (1 << spd) - 1;
1721 if (!mask)
1722 return -EINVAL;
1723
1724 ap->sata_spd_limit = mask;
1725
f15a1daf
TH		 1726 ata_port_printk(ap, KERN_WARNING, "limiting SATA link speed to %s\n",
1727 sata_spd_string(fls(mask)));
1c3fae4d
TH		 1728
1729 return 0;
1730}
1731
3c567b7d 1732static int __sata_set_spd_needed(struct ata_port *ap, u32 *scontrol)
1c3fae4d
TH		 1733{
1734 u32 spd, limit;
1735
1736 if (ap->sata_spd_limit == UINT_MAX)
1737 limit = 0;
1738 else
1739 limit = fls(ap->sata_spd_limit);
1740
1741 spd = (*scontrol >> 4) & 0xf;
1742 *scontrol = (*scontrol & ~0xf0) | ((limit & 0xf) << 4);
1743
1744 return spd != limit;
1745}
1746
1747/**
3c567b7d 1748 * sata_set_spd_needed - is SATA spd configuration needed
1c3fae4d
TH		 1749 * @ap: Port in question
1750 *
1751 * Test whether the spd limit in SControl matches
1752 * @ap->sata_spd_limit. This function is used to determine
1753 * whether hardreset is necessary to apply SATA spd
1754 * configuration.
1755 *
1756 * LOCKING:
1757 * Inherited from caller.
1758 *
1759 * RETURNS:
1760 * 1 if SATA spd configuration is needed, 0 otherwise.
1761 */
3c567b7d 1762int sata_set_spd_needed(struct ata_port *ap)
1c3fae4d
TH		 1763{
1764 u32 scontrol;
1765
81952c54 1766 if (sata_scr_read(ap, SCR_CONTROL, &scontrol))
1c3fae4d
TH		 1767 return 0;
1768
3c567b7d 1769 return __sata_set_spd_needed(ap, &scontrol);
1c3fae4d
TH		 1770}
1771
1772/**
3c567b7d 1773 * sata_set_spd - set SATA spd according to spd limit
1c3fae4d
TH		 1774 * @ap: Port to set SATA spd for
1775 *
1776 * Set SATA spd of @ap according to sata_spd_limit.
1777 *
1778 * LOCKING:
1779 * Inherited from caller.
1780 *
1781 * RETURNS:
1782 * 0 if spd doesn't need to be changed, 1 if spd has been
81952c54 1783 * changed. Negative errno if SCR registers are inaccessible.
1c3fae4d 1784 */
3c567b7d 1785int sata_set_spd(struct ata_port *ap)
1c3fae4d
TH		 1786{
1787 u32 scontrol;
81952c54 1788 int rc;
1c3fae4d 1789
81952c54
TH		 1790 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
1791 return rc;
1c3fae4d 1792
3c567b7d 1793 if (!__sata_set_spd_needed(ap, &scontrol))
1c3fae4d
TH		 1794 return 0;
1795
81952c54
TH		 1796 if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
1797 return rc;
1798
1c3fae4d
TH		 1799 return 1;
1800}
1801
452503f9
AC		 1802/*
1803 * This mode timing computation functionality is ported over from
1804 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1805 */
1806/*
1807 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
1808 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
1809 * for PIO 5, which is a nonstandard extension and UDMA6, which
2e9edbf8 1810 * is currently supported only by Maxtor drives.
452503f9
AC		 1811 */
1812
1813static const struct ata_timing ata_timing[] = {
1814
1815 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1816 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1817 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1818 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1819
1820 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1821 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1822 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1823
1824/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
2e9edbf8 1825
452503f9
AC		 1826 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1827 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1828 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
2e9edbf8 1829
452503f9
AC		 1830 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
1831 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
1832 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
1833
1834/* { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, */
1835 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
1836 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
1837
1838 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
1839 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
1840 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
1841
1842/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
1843
1844 { 0xFF }
1845};
1846
1847#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
1848#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
1849
1850static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
1851{
1852 q->setup = EZ(t->setup * 1000, T);
1853 q->act8b = EZ(t->act8b * 1000, T);
1854 q->rec8b = EZ(t->rec8b * 1000, T);
1855 q->cyc8b = EZ(t->cyc8b * 1000, T);
1856 q->active = EZ(t->active * 1000, T);
1857 q->recover = EZ(t->recover * 1000, T);
1858 q->cycle = EZ(t->cycle * 1000, T);
1859 q->udma = EZ(t->udma * 1000, UT);
1860}
1861
1862void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
1863 struct ata_timing *m, unsigned int what)
1864{
1865 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
1866 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
1867 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
1868 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
1869 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
1870 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
1871 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
1872 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
1873}
1874
1875static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
1876{
1877 const struct ata_timing *t;
1878
1879 for (t = ata_timing; t->mode != speed; t++)
91190758 1880 if (t->mode == 0xFF)
452503f9 1881 return NULL;
2e9edbf8 1882 return t;
452503f9
AC		 1883}
1884
1885int ata_timing_compute(struct ata_device *adev, unsigned short speed,
1886 struct ata_timing *t, int T, int UT)
1887{
1888 const struct ata_timing *s;
1889 struct ata_timing p;
1890
1891 /*
2e9edbf8 1892 * Find the mode.
75b1f2f8 1893 */
452503f9
AC		 1894
1895 if (!(s = ata_timing_find_mode(speed)))
1896 return -EINVAL;
1897
75b1f2f8
AL		 1898 memcpy(t, s, sizeof(*s));
1899
452503f9
AC		 1900 /*
1901 * If the drive is an EIDE drive, it can tell us it needs extended
1902 * PIO/MW_DMA cycle timing.
1903 */
1904
1905 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
1906 memset(&p, 0, sizeof(p));
1907 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
1908 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
1909 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
1910 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
1911 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
1912 }
1913 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
1914 }
1915
1916 /*
1917 * Convert the timing to bus clock counts.
1918 */
1919
75b1f2f8 1920 ata_timing_quantize(t, t, T, UT);
452503f9
AC		 1921
1922 /*
c893a3ae
RD		 1923 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
1924 * S.M.A.R.T * and some other commands. We have to ensure that the
1925 * DMA cycle timing is slower/equal than the fastest PIO timing.
452503f9
AC		 1926 */
1927
1928 if (speed > XFER_PIO_4) {
1929 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
1930 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
1931 }
1932
1933 /*
c893a3ae 1934 * Lengthen active & recovery time so that cycle time is correct.
452503f9
AC		 1935 */
1936
1937 if (t->act8b + t->rec8b < t->cyc8b) {
1938 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
1939 t->rec8b = t->cyc8b - t->act8b;
1940 }
1941
1942 if (t->active + t->recover < t->cycle) {
1943 t->active += (t->cycle - (t->active + t->recover)) / 2;
1944 t->recover = t->cycle - t->active;
1945 }
1946
1947 return 0;
1948}
1949
cf176e1a
TH		 1950/**
1951 * ata_down_xfermask_limit - adjust dev xfer masks downward
cf176e1a
TH		 1952 * @dev: Device to adjust xfer masks
1953 * @force_pio0: Force PIO0
1954 *
1955 * Adjust xfer masks of @dev downward. Note that this function
1956 * does not apply the change. Invoking ata_set_mode() afterwards
1957 * will apply the limit.
1958 *
1959 * LOCKING:
1960 * Inherited from caller.
1961 *
1962 * RETURNS:
1963 * 0 on success, negative errno on failure
1964 */
3373efd8 1965int ata_down_xfermask_limit(struct ata_device *dev, int force_pio0)
cf176e1a
TH		 1966{
1967 unsigned long xfer_mask;
1968 int highbit;
1969
1970 xfer_mask = ata_pack_xfermask(dev->pio_mask, dev->mwdma_mask,
1971 dev->udma_mask);
1972
1973 if (!xfer_mask)
1974 goto fail;
1975 /* don't gear down to MWDMA from UDMA, go directly to PIO */
1976 if (xfer_mask & ATA_MASK_UDMA)
1977 xfer_mask &= ~ATA_MASK_MWDMA;
1978
1979 highbit = fls(xfer_mask) - 1;
1980 xfer_mask &= ~(1 << highbit);
1981 if (force_pio0)
1982 xfer_mask &= 1 << ATA_SHIFT_PIO;
1983 if (!xfer_mask)
1984 goto fail;
1985
1986 ata_unpack_xfermask(xfer_mask, &dev->pio_mask, &dev->mwdma_mask,
1987 &dev->udma_mask);
1988
f15a1daf
TH		 1989 ata_dev_printk(dev, KERN_WARNING, "limiting speed to %s\n",
1990 ata_mode_string(xfer_mask));
cf176e1a
TH		 1991
1992 return 0;
1993
1994 fail:
1995 return -EINVAL;
1996}
1997
3373efd8 1998static int ata_dev_set_mode(struct ata_device *dev)
1da177e4 1999{
83206a29
TH		 2000 unsigned int err_mask;
2001 int rc;
1da177e4 2002
e8384607 2003 dev->flags &= ~ATA_DFLAG_PIO;
1da177e4
LT		 2004 if (dev->xfer_shift == ATA_SHIFT_PIO)
2005 dev->flags |= ATA_DFLAG_PIO;
2006
3373efd8 2007 err_mask = ata_dev_set_xfermode(dev);
83206a29 2008 if (err_mask) {
f15a1daf
TH		 2009 ata_dev_printk(dev, KERN_ERR, "failed to set xfermode "
2010 "(err_mask=0x%x)\n", err_mask);
83206a29
TH		 2011 return -EIO;
2012 }
1da177e4 2013
3373efd8 2014 rc = ata_dev_revalidate(dev, 0);
5eb45c02 2015 if (rc)
83206a29 2016 return rc;
48a8a14f 2017
23e71c3d
TH		 2018 DPRINTK("xfer_shift=%u, xfer_mode=0x%x\n",
2019 dev->xfer_shift, (int)dev->xfer_mode);
1da177e4 2020
f15a1daf
TH		 2021 ata_dev_printk(dev, KERN_INFO, "configured for %s\n",
2022 ata_mode_string(ata_xfer_mode2mask(dev->xfer_mode)));
83206a29 2023 return 0;
1da177e4
LT		 2024}
2025
1da177e4
LT		 2026/**
2027 * ata_set_mode - Program timings and issue SET FEATURES - XFER
2028 * @ap: port on which timings will be programmed
e82cbdb9 2029 * @r_failed_dev: out paramter for failed device
1da177e4 2030 *
e82cbdb9
TH		 2031 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.). If
2032 * ata_set_mode() fails, pointer to the failing device is
2033 * returned in @r_failed_dev.
780a87f7 2034 *
1da177e4 2035 * LOCKING:
0cba632b 2036 * PCI/etc. bus probe sem.
e82cbdb9
TH		 2037 *
2038 * RETURNS:
2039 * 0 on success, negative errno otherwise
1da177e4 2040 */
1ad8e7f9 2041int ata_set_mode(struct ata_port *ap, struct ata_device **r_failed_dev)
1da177e4 2042{
e8e0619f 2043 struct ata_device *dev;
e82cbdb9 2044 int i, rc = 0, used_dma = 0, found = 0;
1da177e4 2045
3adcebb2
TH		 2046 /* has private set_mode? */
2047 if (ap->ops->set_mode) {
2048 /* FIXME: make ->set_mode handle no device case and
2049 * return error code and failing device on failure.
2050 */
2051 for (i = 0; i < ATA_MAX_DEVICES; i++) {
2052 if (ata_dev_enabled(&ap->device[i])) {
2053 ap->ops->set_mode(ap);
2054 break;
2055 }
2056 }
2057 return 0;
2058 }
2059
a6d5a51c
TH		 2060 /* step 1: calculate xfer_mask */
2061 for (i = 0; i < ATA_MAX_DEVICES; i++) {
acf356b1 2062 unsigned int pio_mask, dma_mask;
a6d5a51c 2063
e8e0619f
TH		 2064 dev = &ap->device[i];
2065
e1211e3f 2066 if (!ata_dev_enabled(dev))
a6d5a51c
TH		 2067 continue;
2068
3373efd8 2069 ata_dev_xfermask(dev);
1da177e4 2070
acf356b1
TH		 2071 pio_mask = ata_pack_xfermask(dev->pio_mask, 0, 0);
2072 dma_mask = ata_pack_xfermask(0, dev->mwdma_mask, dev->udma_mask);
2073 dev->pio_mode = ata_xfer_mask2mode(pio_mask);
2074 dev->dma_mode = ata_xfer_mask2mode(dma_mask);
5444a6f4 2075
4f65977d 2076 found = 1;
5444a6f4
AC		 2077 if (dev->dma_mode)
2078 used_dma = 1;
a6d5a51c 2079 }
4f65977d 2080 if (!found)
e82cbdb9 2081 goto out;
a6d5a51c
TH		 2082
2083 /* step 2: always set host PIO timings */
e8e0619f
TH		 2084 for (i = 0; i < ATA_MAX_DEVICES; i++) {
2085 dev = &ap->device[i];
2086 if (!ata_dev_enabled(dev))
2087 continue;
2088
2089 if (!dev->pio_mode) {
f15a1daf 2090 ata_dev_printk(dev, KERN_WARNING, "no PIO support\n");
e8e0619f 2091 rc = -EINVAL;
e82cbdb9 2092 goto out;
e8e0619f
TH		 2093 }
2094
2095 dev->xfer_mode = dev->pio_mode;
2096 dev->xfer_shift = ATA_SHIFT_PIO;
2097 if (ap->ops->set_piomode)
2098 ap->ops->set_piomode(ap, dev);
2099 }
1da177e4 2100
a6d5a51c 2101 /* step 3: set host DMA timings */
e8e0619f
TH		 2102 for (i = 0; i < ATA_MAX_DEVICES; i++) {
2103 dev = &ap->device[i];
2104
2105 if (!ata_dev_enabled(dev) || !dev->dma_mode)
2106 continue;
2107
2108 dev->xfer_mode = dev->dma_mode;
2109 dev->xfer_shift = ata_xfer_mode2shift(dev->dma_mode);
2110 if (ap->ops->set_dmamode)
2111 ap->ops->set_dmamode(ap, dev);
2112 }
1da177e4
LT		 2113
2114 /* step 4: update devices' xfer mode */
83206a29 2115 for (i = 0; i < ATA_MAX_DEVICES; i++) {
e8e0619f 2116 dev = &ap->device[i];
1da177e4 2117
e1211e3f 2118 if (!ata_dev_enabled(dev))
83206a29
TH		 2119 continue;
2120
3373efd8 2121 rc = ata_dev_set_mode(dev);
5bbc53f4 2122 if (rc)
e82cbdb9 2123 goto out;
83206a29 2124 }
1da177e4 2125
e8e0619f
TH		 2126 /* Record simplex status. If we selected DMA then the other
2127 * host channels are not permitted to do so.
5444a6f4 2128 */
5444a6f4
AC		 2129 if (used_dma && (ap->host_set->flags & ATA_HOST_SIMPLEX))
2130 ap->host_set->simplex_claimed = 1;
2131
e8e0619f 2132 /* step5: chip specific finalisation */
1da177e4
LT		 2133 if (ap->ops->post_set_mode)
2134 ap->ops->post_set_mode(ap);
2135
e82cbdb9
TH		 2136 out:
2137 if (rc)
2138 *r_failed_dev = dev;
2139 return rc;
1da177e4
LT		 2140}
2141
1fdffbce
JG		 2142/**
2143 * ata_tf_to_host - issue ATA taskfile to host controller
2144 * @ap: port to which command is being issued
2145 * @tf: ATA taskfile register set
2146 *
2147 * Issues ATA taskfile register set to ATA host controller,
2148 * with proper synchronization with interrupt handler and
2149 * other threads.
2150 *
2151 * LOCKING:
2152 * spin_lock_irqsave(host_set lock)
2153 */
2154
2155static inline void ata_tf_to_host(struct ata_port *ap,
2156 const struct ata_taskfile *tf)
2157{
2158 ap->ops->tf_load(ap, tf);
2159 ap->ops->exec_command(ap, tf);
2160}
2161
1da177e4
LT		 2162/**
2163 * ata_busy_sleep - sleep until BSY clears, or timeout
2164 * @ap: port containing status register to be polled
2165 * @tmout_pat: impatience timeout
2166 * @tmout: overall timeout
2167 *
780a87f7
JG		 2168 * Sleep until ATA Status register bit BSY clears,
2169 * or a timeout occurs.
2170 *
2171 * LOCKING: None.
1da177e4
LT		 2172 */
2173
6f8b9958
TH		 2174unsigned int ata_busy_sleep (struct ata_port *ap,
2175 unsigned long tmout_pat, unsigned long tmout)
1da177e4
LT		 2176{
2177 unsigned long timer_start, timeout;
2178 u8 status;
2179
2180 status = ata_busy_wait(ap, ATA_BUSY, 300);
2181 timer_start = jiffies;
2182 timeout = timer_start + tmout_pat;
2183 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
2184 msleep(50);
2185 status = ata_busy_wait(ap, ATA_BUSY, 3);
2186 }
2187
2188 if (status & ATA_BUSY)
f15a1daf
TH		 2189 ata_port_printk(ap, KERN_WARNING,
2190 "port is slow to respond, please be patient\n");
1da177e4
LT		 2191
2192 timeout = timer_start + tmout;
2193 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
2194 msleep(50);
2195 status = ata_chk_status(ap);
2196 }
2197
2198 if (status & ATA_BUSY) {
f15a1daf
TH		 2199 ata_port_printk(ap, KERN_ERR, "port failed to respond "
2200 "(%lu secs)\n", tmout / HZ);
1da177e4
LT		 2201 return 1;
2202 }
2203
2204 return 0;
2205}
2206
2207static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
2208{
2209 struct ata_ioports *ioaddr = &ap->ioaddr;
2210 unsigned int dev0 = devmask & (1 << 0);
2211 unsigned int dev1 = devmask & (1 << 1);
2212 unsigned long timeout;
2213
2214 /* if device 0 was found in ata_devchk, wait for its
2215 * BSY bit to clear
2216 */
2217 if (dev0)
2218 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2219
2220 /* if device 1 was found in ata_devchk, wait for
2221 * register access, then wait for BSY to clear
2222 */
2223 timeout = jiffies + ATA_TMOUT_BOOT;
2224 while (dev1) {
2225 u8 nsect, lbal;
2226
2227 ap->ops->dev_select(ap, 1);
2228 if (ap->flags & ATA_FLAG_MMIO) {
2229 nsect = readb((void __iomem *) ioaddr->nsect_addr);
2230 lbal = readb((void __iomem *) ioaddr->lbal_addr);
2231 } else {
2232 nsect = inb(ioaddr->nsect_addr);
2233 lbal = inb(ioaddr->lbal_addr);
2234 }
2235 if ((nsect == 1) && (lbal == 1))
2236 break;
2237 if (time_after(jiffies, timeout)) {
2238 dev1 = 0;
2239 break;
2240 }
2241 msleep(50); /* give drive a breather */
2242 }
2243 if (dev1)
2244 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2245
2246 /* is all this really necessary? */
2247 ap->ops->dev_select(ap, 0);
2248 if (dev1)
2249 ap->ops->dev_select(ap, 1);
2250 if (dev0)
2251 ap->ops->dev_select(ap, 0);
2252}
2253
1da177e4
LT		 2254static unsigned int ata_bus_softreset(struct ata_port *ap,
2255 unsigned int devmask)
2256{
2257 struct ata_ioports *ioaddr = &ap->ioaddr;
2258
2259 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
2260
2261 /* software reset. causes dev0 to be selected */
2262 if (ap->flags & ATA_FLAG_MMIO) {
2263 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2264 udelay(20); /* FIXME: flush */
2265 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
2266 udelay(20); /* FIXME: flush */
2267 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2268 } else {
2269 outb(ap->ctl, ioaddr->ctl_addr);
2270 udelay(10);
2271 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2272 udelay(10);
2273 outb(ap->ctl, ioaddr->ctl_addr);
2274 }
2275
2276 /* spec mandates ">= 2ms" before checking status.
2277 * We wait 150ms, because that was the magic delay used for
2278 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
2279 * between when the ATA command register is written, and then
2280 * status is checked. Because waiting for "a while" before
2281 * checking status is fine, post SRST, we perform this magic
2282 * delay here as well.
09c7ad79
AC		 2283 *
2284 * Old drivers/ide uses the 2mS rule and then waits for ready
1da177e4
LT		 2285 */
2286 msleep(150);
2287
2e9edbf8 2288 /* Before we perform post reset processing we want to see if
298a41ca
TH		 2289 * the bus shows 0xFF because the odd clown forgets the D7
2290 * pulldown resistor.
2291 */
987d2f05 2292 if (ata_check_status(ap) == 0xFF) {
f15a1daf 2293 ata_port_printk(ap, KERN_ERR, "SRST failed (status 0xFF)\n");
298a41ca 2294 return AC_ERR_OTHER;
987d2f05 2295 }
09c7ad79 2296
1da177e4
LT		 2297 ata_bus_post_reset(ap, devmask);
2298
2299 return 0;
2300}
2301
2302/**
2303 * ata_bus_reset - reset host port and associated ATA channel
2304 * @ap: port to reset
2305 *
2306 * This is typically the first time we actually start issuing
2307 * commands to the ATA channel. We wait for BSY to clear, then
2308 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2309 * result. Determine what devices, if any, are on the channel
2310 * by looking at the device 0/1 error register. Look at the signature
2311 * stored in each device's taskfile registers, to determine if
2312 * the device is ATA or ATAPI.
2313 *
2314 * LOCKING:
0cba632b
JG		 2315 * PCI/etc. bus probe sem.
2316 * Obtains host_set lock.
1da177e4
LT		 2317 *
2318 * SIDE EFFECTS:
198e0fed 2319 * Sets ATA_FLAG_DISABLED if bus reset fails.
1da177e4
LT		 2320 */
2321
2322void ata_bus_reset(struct ata_port *ap)
2323{
2324 struct ata_ioports *ioaddr = &ap->ioaddr;
2325 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2326 u8 err;
aec5c3c1 2327 unsigned int dev0, dev1 = 0, devmask = 0;
1da177e4
LT		 2328
2329 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
2330
2331 /* determine if device 0/1 are present */
2332 if (ap->flags & ATA_FLAG_SATA_RESET)
2333 dev0 = 1;
2334 else {
2335 dev0 = ata_devchk(ap, 0);
2336 if (slave_possible)
2337 dev1 = ata_devchk(ap, 1);
2338 }
2339
2340 if (dev0)
2341 devmask |= (1 << 0);
2342 if (dev1)
2343 devmask |= (1 << 1);
2344
2345 /* select device 0 again */
2346 ap->ops->dev_select(ap, 0);
2347
2348 /* issue bus reset */
2349 if (ap->flags & ATA_FLAG_SRST)
aec5c3c1
TH		 2350 if (ata_bus_softreset(ap, devmask))
2351 goto err_out;
1da177e4
LT		 2352
2353 /*
2354 * determine by signature whether we have ATA or ATAPI devices
2355 */
b4dc7623 2356 ap->device[0].class = ata_dev_try_classify(ap, 0, &err);
1da177e4 2357 if ((slave_possible) && (err != 0x81))
b4dc7623 2358 ap->device[1].class = ata_dev_try_classify(ap, 1, &err);
1da177e4
LT		 2359
2360 /* re-enable interrupts */
2361 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2362 ata_irq_on(ap);
2363
2364 /* is double-select really necessary? */
2365 if (ap->device[1].class != ATA_DEV_NONE)
2366 ap->ops->dev_select(ap, 1);
2367 if (ap->device[0].class != ATA_DEV_NONE)
2368 ap->ops->dev_select(ap, 0);
2369
2370 /* if no devices were detected, disable this port */
2371 if ((ap->device[0].class == ATA_DEV_NONE) &&
2372 (ap->device[1].class == ATA_DEV_NONE))
2373 goto err_out;
2374
2375 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2376 /* set up device control for ATA_FLAG_SATA_RESET */
2377 if (ap->flags & ATA_FLAG_MMIO)
2378 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2379 else
2380 outb(ap->ctl, ioaddr->ctl_addr);
2381 }
2382
2383 DPRINTK("EXIT\n");
2384 return;
2385
2386err_out:
f15a1daf 2387 ata_port_printk(ap, KERN_ERR, "disabling port\n");
1da177e4
LT		 2388 ap->ops->port_disable(ap);
2389
2390 DPRINTK("EXIT\n");
2391}
2392
7a7921e8
TH		 2393static int sata_phy_resume(struct ata_port *ap)
2394{
2395 unsigned long timeout = jiffies + (HZ * 5);
852ee16a 2396 u32 scontrol, sstatus;
81952c54
TH		 2397 int rc;
2398
2399 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
2400 return rc;
7a7921e8 2401
852ee16a 2402 scontrol = (scontrol & 0x0f0) | 0x300;
81952c54
TH		 2403
2404 if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
2405 return rc;
7a7921e8
TH		 2406
2407 /* Wait for phy to become ready, if necessary. */
2408 do {
2409 msleep(200);
81952c54
TH		 2410 if ((rc = sata_scr_read(ap, SCR_STATUS, &sstatus)))
2411 return rc;
7a7921e8
TH		 2412 if ((sstatus & 0xf) != 1)
2413 return 0;
2414 } while (time_before(jiffies, timeout));
2415
81952c54 2416 return -EBUSY;
7a7921e8
TH		 2417}
2418
8a19ac89
TH		 2419/**
2420 * ata_std_probeinit - initialize probing
2421 * @ap: port to be probed
2422 *
2423 * @ap is about to be probed. Initialize it. This function is
2424 * to be used as standard callback for ata_drive_probe_reset().
3a39746a
TH		 2425 *
2426 * NOTE!!! Do not use this function as probeinit if a low level
2427 * driver implements only hardreset. Just pass NULL as probeinit
2428 * in that case. Using this function is probably okay but doing
2429 * so makes reset sequence different from the original
2430 * ->phy_reset implementation and Jeff nervous. :-P
8a19ac89 2431 */
17efc5f7 2432void ata_std_probeinit(struct ata_port *ap)
8a19ac89 2433{
81952c54 2434 u32 scontrol;
1c3fae4d 2435
81952c54
TH		 2436 /* resume link */
2437 sata_phy_resume(ap);
1c3fae4d 2438
81952c54
TH		 2439 /* init sata_spd_limit to the current value */
2440 if (sata_scr_read(ap, SCR_CONTROL, &scontrol) == 0) {
2441 int spd = (scontrol >> 4) & 0xf;
2442 ap->sata_spd_limit &= (1 << spd) - 1;
3a39746a 2443 }
81952c54
TH		 2444
2445 /* wait for device */
2446 if (ata_port_online(ap))
2447 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
8a19ac89
TH		 2448}
2449
c2bd5804
TH		 2450/**
2451 * ata_std_softreset - reset host port via ATA SRST
2452 * @ap: port to reset
c2bd5804
TH		 2453 * @classes: resulting classes of attached devices
2454 *
2455 * Reset host port using ATA SRST. This function is to be used
2456 * as standard callback for ata_drive_*_reset() functions.
2457 *
2458 * LOCKING:
2459 * Kernel thread context (may sleep)
2460 *
2461 * RETURNS:
2462 * 0 on success, -errno otherwise.
2463 */
2bf2cb26 2464int ata_std_softreset(struct ata_port *ap, unsigned int *classes)
c2bd5804
TH		 2465{
2466 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2467 unsigned int devmask = 0, err_mask;
2468 u8 err;
2469
2470 DPRINTK("ENTER\n");
2471
81952c54 2472 if (ata_port_offline(ap)) {
3a39746a
TH		 2473 classes[0] = ATA_DEV_NONE;
2474 goto out;
2475 }
2476
c2bd5804
TH		 2477 /* determine if device 0/1 are present */
2478 if (ata_devchk(ap, 0))
2479 devmask |= (1 << 0);
2480 if (slave_possible && ata_devchk(ap, 1))
2481 devmask |= (1 << 1);
2482
c2bd5804
TH		 2483 /* select device 0 again */
2484 ap->ops->dev_select(ap, 0);
2485
2486 /* issue bus reset */
2487 DPRINTK("about to softreset, devmask=%x\n", devmask);
2488 err_mask = ata_bus_softreset(ap, devmask);
2489 if (err_mask) {
f15a1daf
TH		 2490 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
2491 err_mask);
c2bd5804
TH		 2492 return -EIO;
2493 }
2494
2495 /* determine by signature whether we have ATA or ATAPI devices */
2496 classes[0] = ata_dev_try_classify(ap, 0, &err);
2497 if (slave_possible && err != 0x81)
2498 classes[1] = ata_dev_try_classify(ap, 1, &err);
2499
3a39746a 2500 out:
c2bd5804
TH		 2501 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2502 return 0;
2503}
2504
2505/**
2506 * sata_std_hardreset - reset host port via SATA phy reset
2507 * @ap: port to reset
c2bd5804
TH		 2508 * @class: resulting class of attached device
2509 *
2510 * SATA phy-reset host port using DET bits of SControl register.
2511 * This function is to be used as standard callback for
2512 * ata_drive_*_reset().
2513 *
2514 * LOCKING:
2515 * Kernel thread context (may sleep)
2516 *
2517 * RETURNS:
2518 * 0 on success, -errno otherwise.
2519 */
2bf2cb26 2520int sata_std_hardreset(struct ata_port *ap, unsigned int *class)
c2bd5804 2521{
852ee16a 2522 u32 scontrol;
81952c54 2523 int rc;
852ee16a 2524
c2bd5804
TH		 2525 DPRINTK("ENTER\n");
2526
3c567b7d 2527 if (sata_set_spd_needed(ap)) {
1c3fae4d
TH		 2528 /* SATA spec says nothing about how to reconfigure
2529 * spd. To be on the safe side, turn off phy during
2530 * reconfiguration. This works for at least ICH7 AHCI
2531 * and Sil3124.
2532 */
81952c54
TH		 2533 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
2534 return rc;
2535
1c3fae4d 2536 scontrol = (scontrol & 0x0f0) | 0x302;
81952c54
TH		 2537
2538 if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
2539 return rc;
1c3fae4d 2540
3c567b7d 2541 sata_set_spd(ap);
1c3fae4d
TH		 2542 }
2543
2544 /* issue phy wake/reset */
81952c54
TH		 2545 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
2546 return rc;
2547
852ee16a 2548 scontrol = (scontrol & 0x0f0) | 0x301;
81952c54
TH		 2549
2550 if ((rc = sata_scr_write_flush(ap, SCR_CONTROL, scontrol)))
2551 return rc;
c2bd5804 2552
1c3fae4d 2553 /* Couldn't find anything in SATA I/II specs, but AHCI-1.1
c2bd5804
TH		 2554 * 10.4.2 says at least 1 ms.
2555 */
2556 msleep(1);
2557
1c3fae4d 2558 /* bring phy back */
7a7921e8 2559 sata_phy_resume(ap);
c2bd5804 2560
c2bd5804 2561 /* TODO: phy layer with polling, timeouts, etc. */
81952c54 2562 if (ata_port_offline(ap)) {
c2bd5804
TH		 2563 *class = ATA_DEV_NONE;
2564 DPRINTK("EXIT, link offline\n");
2565 return 0;
2566 }
2567
2568 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
f15a1daf
TH		 2569 ata_port_printk(ap, KERN_ERR,
2570 "COMRESET failed (device not ready)\n");
c2bd5804
TH		 2571 return -EIO;
2572 }
2573
3a39746a
TH		 2574 ap->ops->dev_select(ap, 0); /* probably unnecessary */
2575
c2bd5804
TH		 2576 *class = ata_dev_try_classify(ap, 0, NULL);
2577
2578 DPRINTK("EXIT, class=%u\n", *class);
2579 return 0;
2580}
2581
2582/**
2583 * ata_std_postreset - standard postreset callback
2584 * @ap: the target ata_port
2585 * @classes: classes of attached devices
2586 *
2587 * This function is invoked after a successful reset. Note that
2588 * the device might have been reset more than once using
2589 * different reset methods before postreset is invoked.
c2bd5804
TH		 2590 *
2591 * This function is to be used as standard callback for
2592 * ata_drive_*_reset().
2593 *
2594 * LOCKING:
2595 * Kernel thread context (may sleep)
2596 */
2597void ata_std_postreset(struct ata_port *ap, unsigned int *classes)
2598{
dc2b3515
TH		 2599 u32 serror;
2600
c2bd5804
TH		 2601 DPRINTK("ENTER\n");
2602
c2bd5804 2603 /* print link status */
81952c54 2604 sata_print_link_status(ap);
c2bd5804 2605
dc2b3515
TH		 2606 /* clear SError */
2607 if (sata_scr_read(ap, SCR_ERROR, &serror) == 0)
2608 sata_scr_write(ap, SCR_ERROR, serror);
2609
3a39746a 2610 /* re-enable interrupts */
e3180499
TH		 2611 if (!ap->ops->error_handler) {
2612 /* FIXME: hack. create a hook instead */
2613 if (ap->ioaddr.ctl_addr)
2614 ata_irq_on(ap);
2615 }
c2bd5804
TH		 2616
2617 /* is double-select really necessary? */
2618 if (classes[0] != ATA_DEV_NONE)
2619 ap->ops->dev_select(ap, 1);
2620 if (classes[1] != ATA_DEV_NONE)
2621 ap->ops->dev_select(ap, 0);
2622
3a39746a
TH		 2623 /* bail out if no device is present */
2624 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2625 DPRINTK("EXIT, no device\n");
2626 return;
2627 }
2628
2629 /* set up device control */
2630 if (ap->ioaddr.ctl_addr) {
2631 if (ap->flags & ATA_FLAG_MMIO)
2632 writeb(ap->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
2633 else
2634 outb(ap->ctl, ap->ioaddr.ctl_addr);
2635 }
c2bd5804
TH		 2636
2637 DPRINTK("EXIT\n");
2638}
2639
2640/**
2641 * ata_std_probe_reset - standard probe reset method
2642 * @ap: prot to perform probe-reset
2643 * @classes: resulting classes of attached devices
2644 *
2645 * The stock off-the-shelf ->probe_reset method.
2646 *
2647 * LOCKING:
2648 * Kernel thread context (may sleep)
2649 *
2650 * RETURNS:
2651 * 0 on success, -errno otherwise.
2652 */
2653int ata_std_probe_reset(struct ata_port *ap, unsigned int *classes)
2654{
2655 ata_reset_fn_t hardreset;
2656
2657 hardreset = NULL;
81952c54 2658 if (sata_scr_valid(ap))
c2bd5804
TH		 2659 hardreset = sata_std_hardreset;
2660
8a19ac89 2661 return ata_drive_probe_reset(ap, ata_std_probeinit,
7944ea95 2662 ata_std_softreset, hardreset,
c2bd5804
TH		 2663 ata_std_postreset, classes);
2664}
2665
2bf2cb26 2666int ata_do_reset(struct ata_port *ap, ata_reset_fn_t reset,
96bd39ec 2667 unsigned int *classes)
a62c0fc5
TH		 2668{
2669 int i, rc;
2670
2671 for (i = 0; i < ATA_MAX_DEVICES; i++)
2672 classes[i] = ATA_DEV_UNKNOWN;
2673
2bf2cb26 2674 rc = reset(ap, classes);
a62c0fc5
TH		 2675 if (rc)
2676 return rc;
2677
2678 /* If any class isn't ATA_DEV_UNKNOWN, consider classification
2679 * is complete and convert all ATA_DEV_UNKNOWN to
2680 * ATA_DEV_NONE.
2681 */
2682 for (i = 0; i < ATA_MAX_DEVICES; i++)
2683 if (classes[i] != ATA_DEV_UNKNOWN)
2684 break;
2685
2686 if (i < ATA_MAX_DEVICES)
2687 for (i = 0; i < ATA_MAX_DEVICES; i++)
2688 if (classes[i] == ATA_DEV_UNKNOWN)
2689 classes[i] = ATA_DEV_NONE;
2690
9974e7cc 2691 return 0;
a62c0fc5
TH		 2692}
2693
2694/**
2695 * ata_drive_probe_reset - Perform probe reset with given methods
2696 * @ap: port to reset
7944ea95 2697 * @probeinit: probeinit method (can be NULL)
a62c0fc5
TH		 2698 * @softreset: softreset method (can be NULL)
2699 * @hardreset: hardreset method (can be NULL)
2700 * @postreset: postreset method (can be NULL)
2701 * @classes: resulting classes of attached devices
2702 *
2703 * Reset the specified port and classify attached devices using
2704 * given methods. This function prefers softreset but tries all
2705 * possible reset sequences to reset and classify devices. This
2706 * function is intended to be used for constructing ->probe_reset
2707 * callback by low level drivers.
2708 *
2709 * Reset methods should follow the following rules.
2710 *
2711 * - Return 0 on sucess, -errno on failure.
2712 * - If classification is supported, fill classes[] with
2713 * recognized class codes.
2714 * - If classification is not supported, leave classes[] alone.
a62c0fc5
TH		 2715 *
2716 * LOCKING:
2717 * Kernel thread context (may sleep)
2718 *
2719 * RETURNS:
2720 * 0 on success, -EINVAL if no reset method is avaliable, -ENODEV
2721 * if classification fails, and any error code from reset
2722 * methods.
2723 */
7944ea95 2724int ata_drive_probe_reset(struct ata_port *ap, ata_probeinit_fn_t probeinit,
a62c0fc5
TH		 2725 ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
2726 ata_postreset_fn_t postreset, unsigned int *classes)
2727{
2728 int rc = -EINVAL;
2729
e3180499
TH		 2730 ata_eh_freeze_port(ap);
2731
7944ea95
TH		 2732 if (probeinit)
2733 probeinit(ap);
2734
3c567b7d 2735 if (softreset && !sata_set_spd_needed(ap)) {
96bd39ec 2736 rc = ata_do_reset(ap, softreset, classes);
9974e7cc
TH		 2737 if (rc == 0 && classes[0] != ATA_DEV_UNKNOWN)
2738 goto done;
f15a1daf
TH		 2739 ata_port_printk(ap, KERN_INFO, "softreset failed, "
2740 "will try hardreset in 5 secs\n");
edbabd86 2741 ssleep(5);
a62c0fc5
TH		 2742 }
2743
2744 if (!hardreset)
9974e7cc 2745 goto done;
a62c0fc5 2746
90dac02c 2747 while (1) {
96bd39ec 2748 rc = ata_do_reset(ap, hardreset, classes);
90dac02c
TH		 2749 if (rc == 0) {
2750 if (classes[0] != ATA_DEV_UNKNOWN)
2751 goto done;
2752 break;
2753 }
2754
3c567b7d 2755 if (sata_down_spd_limit(ap))
90dac02c 2756 goto done;
edbabd86 2757
f15a1daf
TH		 2758 ata_port_printk(ap, KERN_INFO, "hardreset failed, "
2759 "will retry in 5 secs\n");
edbabd86 2760 ssleep(5);
90dac02c 2761 }
a62c0fc5 2762
edbabd86 2763 if (softreset) {
f15a1daf
TH		 2764 ata_port_printk(ap, KERN_INFO,
2765 "hardreset succeeded without classification, "
2766 "will retry softreset in 5 secs\n");
edbabd86
TH		 2767 ssleep(5);
2768
96bd39ec 2769 rc = ata_do_reset(ap, softreset, classes);
edbabd86 2770 }
a62c0fc5 2771
9974e7cc 2772 done:
96bd39ec
TH		 2773 if (rc == 0) {
2774 if (postreset)
2775 postreset(ap, classes);
e3180499
TH		 2776
2777 ata_eh_thaw_port(ap);
2778
96bd39ec
TH		 2779 if (classes[0] == ATA_DEV_UNKNOWN)
2780 rc = -ENODEV;
2781 }
a62c0fc5
TH		 2782 return rc;
2783}
2784
623a3128
TH		 2785/**
2786 * ata_dev_same_device - Determine whether new ID matches configured device
623a3128
TH		 2787 * @dev: device to compare against
2788 * @new_class: class of the new device
2789 * @new_id: IDENTIFY page of the new device
2790 *
2791 * Compare @new_class and @new_id against @dev and determine
2792 * whether @dev is the device indicated by @new_class and
2793 * @new_id.
2794 *
2795 * LOCKING:
2796 * None.
2797 *
2798 * RETURNS:
2799 * 1 if @dev matches @new_class and @new_id, 0 otherwise.
2800 */
3373efd8
TH		 2801static int ata_dev_same_device(struct ata_device *dev, unsigned int new_class,
2802 const u16 *new_id)
623a3128
TH		 2803{
2804 const u16 *old_id = dev->id;
2805 unsigned char model[2][41], serial[2][21];
2806 u64 new_n_sectors;
2807
2808 if (dev->class != new_class) {
f15a1daf
TH		 2809 ata_dev_printk(dev, KERN_INFO, "class mismatch %d != %d\n",
2810 dev->class, new_class);
623a3128
TH		 2811 return 0;
2812 }
2813
2814 ata_id_c_string(old_id, model[0], ATA_ID_PROD_OFS, sizeof(model[0]));
2815 ata_id_c_string(new_id, model[1], ATA_ID_PROD_OFS, sizeof(model[1]));
2816 ata_id_c_string(old_id, serial[0], ATA_ID_SERNO_OFS, sizeof(serial[0]));
2817 ata_id_c_string(new_id, serial[1], ATA_ID_SERNO_OFS, sizeof(serial[1]));
2818 new_n_sectors = ata_id_n_sectors(new_id);
2819
2820 if (strcmp(model[0], model[1])) {
f15a1daf
TH		 2821 ata_dev_printk(dev, KERN_INFO, "model number mismatch "
2822 "'%s' != '%s'\n", model[0], model[1]);
623a3128
TH		 2823 return 0;
2824 }
2825
2826 if (strcmp(serial[0], serial[1])) {
f15a1daf
TH		 2827 ata_dev_printk(dev, KERN_INFO, "serial number mismatch "
2828 "'%s' != '%s'\n", serial[0], serial[1]);
623a3128
TH		 2829 return 0;
2830 }
2831
2832 if (dev->class == ATA_DEV_ATA && dev->n_sectors != new_n_sectors) {
f15a1daf
TH		 2833 ata_dev_printk(dev, KERN_INFO, "n_sectors mismatch "
2834 "%llu != %llu\n",
2835 (unsigned long long)dev->n_sectors,
2836 (unsigned long long)new_n_sectors);
623a3128
TH		 2837 return 0;
2838 }
2839
2840 return 1;
2841}
2842
2843/**
2844 * ata_dev_revalidate - Revalidate ATA device
623a3128
TH		 2845 * @dev: device to revalidate
2846 * @post_reset: is this revalidation after reset?
2847 *
2848 * Re-read IDENTIFY page and make sure @dev is still attached to
2849 * the port.
2850 *
2851 * LOCKING:
2852 * Kernel thread context (may sleep)
2853 *
2854 * RETURNS:
2855 * 0 on success, negative errno otherwise
2856 */
3373efd8 2857int ata_dev_revalidate(struct ata_device *dev, int post_reset)
623a3128 2858{
5eb45c02 2859 unsigned int class = dev->class;
f15a1daf 2860 u16 *id = (void *)dev->ap->sector_buf;
623a3128
TH		 2861 int rc;
2862
5eb45c02
TH		 2863 if (!ata_dev_enabled(dev)) {
2864 rc = -ENODEV;
2865 goto fail;
2866 }
623a3128 2867
fe635c7e 2868 /* read ID data */
3373efd8 2869 rc = ata_dev_read_id(dev, &class, post_reset, id);
623a3128
TH		 2870 if (rc)
2871 goto fail;
2872
2873 /* is the device still there? */
3373efd8 2874 if (!ata_dev_same_device(dev, class, id)) {
623a3128
TH		 2875 rc = -ENODEV;
2876 goto fail;
2877 }
2878
fe635c7e 2879 memcpy(dev->id, id, sizeof(id[0]) * ATA_ID_WORDS);
623a3128
TH		 2880
2881 /* configure device according to the new ID */
3373efd8 2882 rc = ata_dev_configure(dev, 0);
5eb45c02
TH		 2883 if (rc == 0)
2884 return 0;
623a3128
TH		 2885
2886 fail:
f15a1daf 2887 ata_dev_printk(dev, KERN_ERR, "revalidation failed (errno=%d)\n", rc);
623a3128
TH		 2888 return rc;
2889}
2890
98ac62de 2891static const char * const ata_dma_blacklist [] = {
f4b15fef
AC		 2892 "WDC AC11000H", NULL,
2893 "WDC AC22100H", NULL,
2894 "WDC AC32500H", NULL,
2895 "WDC AC33100H", NULL,
2896 "WDC AC31600H", NULL,
2897 "WDC AC32100H", "24.09P07",
2898 "WDC AC23200L", "21.10N21",
2899 "Compaq CRD-8241B", NULL,
2900 "CRD-8400B", NULL,
2901 "CRD-8480B", NULL,
2902 "CRD-8482B", NULL,
2903 "CRD-84", NULL,
2904 "SanDisk SDP3B", NULL,
2905 "SanDisk SDP3B-64", NULL,
2906 "SANYO CD-ROM CRD", NULL,
2907 "HITACHI CDR-8", NULL,
2e9edbf8 2908 "HITACHI CDR-8335", NULL,
f4b15fef 2909 "HITACHI CDR-8435", NULL,
2e9edbf8
JG		 2910 "Toshiba CD-ROM XM-6202B", NULL,
2911 "TOSHIBA CD-ROM XM-1702BC", NULL,
2912 "CD-532E-A", NULL,
2913 "E-IDE CD-ROM CR-840", NULL,
2914 "CD-ROM Drive/F5A", NULL,
2915 "WPI CDD-820", NULL,
f4b15fef 2916 "SAMSUNG CD-ROM SC-148C", NULL,
2e9edbf8 2917 "SAMSUNG CD-ROM SC", NULL,
f4b15fef
AC		 2918 "SanDisk SDP3B-64", NULL,
2919 "ATAPI CD-ROM DRIVE 40X MAXIMUM",NULL,
2920 "_NEC DV5800A", NULL,
2921 "SAMSUNG CD-ROM SN-124", "N001"
1da177e4 2922};
2e9edbf8 2923
f4b15fef
AC		 2924static int ata_strim(char *s, size_t len)
2925{
2926 len = strnlen(s, len);
2927
2928 /* ATAPI specifies that empty space is blank-filled; remove blanks */
2929 while ((len > 0) && (s[len - 1] == ' ')) {
2930 len--;
2931 s[len] = 0;
2932 }
2933 return len;
2934}
1da177e4 2935
057ace5e 2936static int ata_dma_blacklisted(const struct ata_device *dev)
1da177e4 2937{
f4b15fef
AC		 2938 unsigned char model_num[40];
2939 unsigned char model_rev[16];
2940 unsigned int nlen, rlen;
1da177e4
LT		 2941 int i;
2942
f4b15fef
AC		 2943 ata_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
2944 sizeof(model_num));
2945 ata_id_string(dev->id, model_rev, ATA_ID_FW_REV_OFS,
2946 sizeof(model_rev));
2947 nlen = ata_strim(model_num, sizeof(model_num));
2948 rlen = ata_strim(model_rev, sizeof(model_rev));
1da177e4 2949
f4b15fef
AC		 2950 for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i += 2) {
2951 if (!strncmp(ata_dma_blacklist[i], model_num, nlen)) {
2952 if (ata_dma_blacklist[i+1] == NULL)
2953 return 1;
2954 if (!strncmp(ata_dma_blacklist[i], model_rev, rlen))
2955 return 1;
2956 }
2957 }
1da177e4
LT		 2958 return 0;
2959}
2960
a6d5a51c
TH		 2961/**
2962 * ata_dev_xfermask - Compute supported xfermask of the given device
a6d5a51c
TH		 2963 * @dev: Device to compute xfermask for
2964 *
acf356b1
TH		 2965 * Compute supported xfermask of @dev and store it in
2966 * dev->*_mask. This function is responsible for applying all
2967 * known limits including host controller limits, device
2968 * blacklist, etc...
a6d5a51c 2969 *
600511e8
TH		 2970 * FIXME: The current implementation limits all transfer modes to
2971 * the fastest of the lowested device on the port. This is not
05c8e0ac 2972 * required on most controllers.
600511e8 2973 *
a6d5a51c
TH		 2974 * LOCKING:
2975 * None.
a6d5a51c 2976 */
3373efd8 2977static void ata_dev_xfermask(struct ata_device *dev)
1da177e4 2978{
3373efd8 2979 struct ata_port *ap = dev->ap;
5444a6f4 2980 struct ata_host_set *hs = ap->host_set;
a6d5a51c
TH		 2981 unsigned long xfer_mask;
2982 int i;
1da177e4 2983
565083e1
TH		 2984 xfer_mask = ata_pack_xfermask(ap->pio_mask,
2985 ap->mwdma_mask, ap->udma_mask);
2986
2987 /* Apply cable rule here. Don't apply it early because when
2988 * we handle hot plug the cable type can itself change.
2989 */
2990 if (ap->cbl == ATA_CBL_PATA40)
2991 xfer_mask &= ~(0xF8 << ATA_SHIFT_UDMA);
1da177e4 2992
5444a6f4 2993 /* FIXME: Use port-wide xfermask for now */
a6d5a51c
TH		 2994 for (i = 0; i < ATA_MAX_DEVICES; i++) {
2995 struct ata_device *d = &ap->device[i];
565083e1
TH		 2996
2997 if (ata_dev_absent(d))
2998 continue;
2999
3000 if (ata_dev_disabled(d)) {
3001 /* to avoid violating device selection timing */
3002 xfer_mask &= ata_pack_xfermask(d->pio_mask,
3003 UINT_MAX, UINT_MAX);
a6d5a51c 3004 continue;
565083e1
TH		 3005 }
3006
3007 xfer_mask &= ata_pack_xfermask(d->pio_mask,
3008 d->mwdma_mask, d->udma_mask);
a6d5a51c
TH		 3009 xfer_mask &= ata_id_xfermask(d->id);
3010 if (ata_dma_blacklisted(d))
3011 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
1da177e4
LT		 3012 }
3013
a6d5a51c 3014 if (ata_dma_blacklisted(dev))
f15a1daf
TH		 3015 ata_dev_printk(dev, KERN_WARNING,
3016 "device is on DMA blacklist, disabling DMA\n");
a6d5a51c 3017
5444a6f4
AC		 3018 if (hs->flags & ATA_HOST_SIMPLEX) {
3019 if (hs->simplex_claimed)
3020 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
3021 }
565083e1 3022
5444a6f4
AC		 3023 if (ap->ops->mode_filter)
3024 xfer_mask = ap->ops->mode_filter(ap, dev, xfer_mask);
3025
565083e1
TH		 3026 ata_unpack_xfermask(xfer_mask, &dev->pio_mask,
3027 &dev->mwdma_mask, &dev->udma_mask);
1da177e4
LT		 3028}
3029
1da177e4
LT		 3030/**
3031 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
1da177e4
LT		 3032 * @dev: Device to which command will be sent
3033 *
780a87f7
JG		 3034 * Issue SET FEATURES - XFER MODE command to device @dev
3035 * on port @ap.
3036 *
1da177e4 3037 * LOCKING:
0cba632b 3038 * PCI/etc. bus probe sem.
83206a29
TH		 3039 *
3040 * RETURNS:
3041 * 0 on success, AC_ERR_* mask otherwise.
1da177e4
LT		 3042 */
3043
3373efd8 3044static unsigned int ata_dev_set_xfermode(struct ata_device *dev)
1da177e4 3045{
a0123703 3046 struct ata_taskfile tf;
83206a29 3047 unsigned int err_mask;
1da177e4
LT		 3048
3049 /* set up set-features taskfile */
3050 DPRINTK("set features - xfer mode\n");
3051
3373efd8 3052 ata_tf_init(dev, &tf);
a0123703
TH		 3053 tf.command = ATA_CMD_SET_FEATURES;
3054 tf.feature = SETFEATURES_XFER;
3055 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
3056 tf.protocol = ATA_PROT_NODATA;
3057 tf.nsect = dev->xfer_mode;
1da177e4 3058
3373efd8 3059 err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0);
1da177e4 3060
83206a29
TH		 3061 DPRINTK("EXIT, err_mask=%x\n", err_mask);
3062 return err_mask;
1da177e4
LT		 3063}
3064
8bf62ece
AL		 3065/**
3066 * ata_dev_init_params - Issue INIT DEV PARAMS command
8bf62ece 3067 * @dev: Device to which command will be sent
3373efd8
TH		 3068 * @heads: Number of heads
3069 * @sectors: Number of sectors
8bf62ece
AL		 3070 *
3071 * LOCKING:
6aff8f1f
TH		 3072 * Kernel thread context (may sleep)
3073 *
3074 * RETURNS:
3075 * 0 on success, AC_ERR_* mask otherwise.
8bf62ece 3076 */
3373efd8
TH		 3077static unsigned int ata_dev_init_params(struct ata_device *dev,
3078 u16 heads, u16 sectors)
8bf62ece 3079{
a0123703 3080 struct ata_taskfile tf;
6aff8f1f 3081 unsigned int err_mask;
8bf62ece
AL		 3082
3083 /* Number of sectors per track 1-255. Number of heads 1-16 */
3084 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
00b6f5e9 3085 return AC_ERR_INVALID;
8bf62ece
AL		 3086
3087 /* set up init dev params taskfile */
3088 DPRINTK("init dev params \n");
3089
3373efd8 3090 ata_tf_init(dev, &tf);
a0123703
TH		 3091 tf.command = ATA_CMD_INIT_DEV_PARAMS;
3092 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
3093 tf.protocol = ATA_PROT_NODATA;
3094 tf.nsect = sectors;
3095 tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
8bf62ece 3096
3373efd8 3097 err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0);
8bf62ece 3098
6aff8f1f
TH		 3099 DPRINTK("EXIT, err_mask=%x\n", err_mask);
3100 return err_mask;
8bf62ece
AL		 3101}
3102
1da177e4 3103/**
0cba632b
JG		 3104 * ata_sg_clean - Unmap DMA memory associated with command
3105 * @qc: Command containing DMA memory to be released
3106 *
3107 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT		 3108 *
3109 * LOCKING:
0cba632b 3110 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3111 */
3112
3113static void ata_sg_clean(struct ata_queued_cmd *qc)
3114{
3115 struct ata_port *ap = qc->ap;
cedc9a47 3116 struct scatterlist *sg = qc->__sg;
1da177e4 3117 int dir = qc->dma_dir;
cedc9a47 3118 void *pad_buf = NULL;
1da177e4 3119
a4631474
TH		 3120 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
3121 WARN_ON(sg == NULL);
1da177e4
LT		 3122
3123 if (qc->flags & ATA_QCFLAG_SINGLE)
f131883e 3124 WARN_ON(qc->n_elem > 1);
1da177e4 3125
2c13b7ce 3126 VPRINTK("unmapping %u sg elements\n", qc->n_elem);
1da177e4 3127
cedc9a47
JG		 3128 /* if we padded the buffer out to 32-bit bound, and data
3129 * xfer direction is from-device, we must copy from the
3130 * pad buffer back into the supplied buffer
3131 */
3132 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
3133 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3134
3135 if (qc->flags & ATA_QCFLAG_SG) {
e1410f2d 3136 if (qc->n_elem)
2f1f610b 3137 dma_unmap_sg(ap->dev, sg, qc->n_elem, dir);
cedc9a47
JG		 3138 /* restore last sg */
3139 sg[qc->orig_n_elem - 1].length += qc->pad_len;
3140 if (pad_buf) {
3141 struct scatterlist *psg = &qc->pad_sgent;
3142 void *addr = kmap_atomic(psg->page, KM_IRQ0);
3143 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
dfa15988 3144 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 3145 }
3146 } else {
2e242fa9 3147 if (qc->n_elem)
2f1f610b 3148 dma_unmap_single(ap->dev,
e1410f2d
JG		 3149 sg_dma_address(&sg[0]), sg_dma_len(&sg[0]),
3150 dir);
cedc9a47
JG		 3151 /* restore sg */
3152 sg->length += qc->pad_len;
3153 if (pad_buf)
3154 memcpy(qc->buf_virt + sg->length - qc->pad_len,
3155 pad_buf, qc->pad_len);
3156 }
1da177e4
LT		 3157
3158 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 3159 qc->__sg = NULL;
1da177e4
LT		 3160}
3161
3162/**
3163 * ata_fill_sg - Fill PCI IDE PRD table
3164 * @qc: Metadata associated with taskfile to be transferred
3165 *
780a87f7
JG		 3166 * Fill PCI IDE PRD (scatter-gather) table with segments
3167 * associated with the current disk command.
3168 *
1da177e4 3169 * LOCKING:
780a87f7 3170 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3171 *
3172 */
3173static void ata_fill_sg(struct ata_queued_cmd *qc)
3174{
1da177e4 3175 struct ata_port *ap = qc->ap;
cedc9a47
JG		 3176 struct scatterlist *sg;
3177 unsigned int idx;
1da177e4 3178
a4631474 3179 WARN_ON(qc->__sg == NULL);
f131883e 3180 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
1da177e4
LT		 3181
3182 idx = 0;
cedc9a47 3183 ata_for_each_sg(sg, qc) {
1da177e4
LT		 3184 u32 addr, offset;
3185 u32 sg_len, len;
3186
3187 /* determine if physical DMA addr spans 64K boundary.
3188 * Note h/w doesn't support 64-bit, so we unconditionally
3189 * truncate dma_addr_t to u32.
3190 */
3191 addr = (u32) sg_dma_address(sg);
3192 sg_len = sg_dma_len(sg);
3193
3194 while (sg_len) {
3195 offset = addr & 0xffff;
3196 len = sg_len;
3197 if ((offset + sg_len) > 0x10000)
3198 len = 0x10000 - offset;
3199
3200 ap->prd[idx].addr = cpu_to_le32(addr);
3201 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
3202 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
3203
3204 idx++;
3205 sg_len -= len;
3206 addr += len;
3207 }
3208 }
3209
3210 if (idx)
3211 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
3212}
3213/**
3214 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
3215 * @qc: Metadata associated with taskfile to check
3216 *
780a87f7
JG		 3217 * Allow low-level driver to filter ATA PACKET commands, returning
3218 * a status indicating whether or not it is OK to use DMA for the
3219 * supplied PACKET command.
3220 *
1da177e4 3221 * LOCKING:
0cba632b
JG		 3222 * spin_lock_irqsave(host_set lock)
3223 *
1da177e4
LT		 3224 * RETURNS: 0 when ATAPI DMA can be used
3225 * nonzero otherwise
3226 */
3227int ata_check_atapi_dma(struct ata_queued_cmd *qc)
3228{
3229 struct ata_port *ap = qc->ap;
3230 int rc = 0; /* Assume ATAPI DMA is OK by default */
3231
3232 if (ap->ops->check_atapi_dma)
3233 rc = ap->ops->check_atapi_dma(qc);
3234
c2bbc551
AL		 3235 /* We don't support polling DMA.
3236 * Use PIO if the LLDD handles only interrupts in
3237 * the HSM_ST_LAST state and the ATAPI device
3238 * generates CDB interrupts.
3239 */
3240 if ((ap->flags & ATA_FLAG_PIO_POLLING) &&
3241 (qc->dev->flags & ATA_DFLAG_CDB_INTR))
3242 rc = 1;
3243
1da177e4
LT		 3244 return rc;
3245}
3246/**
3247 * ata_qc_prep - Prepare taskfile for submission
3248 * @qc: Metadata associated with taskfile to be prepared
3249 *
780a87f7
JG		 3250 * Prepare ATA taskfile for submission.
3251 *
1da177e4
LT		 3252 * LOCKING:
3253 * spin_lock_irqsave(host_set lock)
3254 */
3255void ata_qc_prep(struct ata_queued_cmd *qc)
3256{
3257 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
3258 return;
3259
3260 ata_fill_sg(qc);
3261}
3262
e46834cd
BK		 3263void ata_noop_qc_prep(struct ata_queued_cmd *qc) { }
3264
0cba632b
JG		 3265/**
3266 * ata_sg_init_one - Associate command with memory buffer
3267 * @qc: Command to be associated
3268 * @buf: Memory buffer
3269 * @buflen: Length of memory buffer, in bytes.
3270 *
3271 * Initialize the data-related elements of queued_cmd @qc
3272 * to point to a single memory buffer, @buf of byte length @buflen.
3273 *
3274 * LOCKING:
3275 * spin_lock_irqsave(host_set lock)
3276 */
3277
1da177e4
LT		 3278void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
3279{
3280 struct scatterlist *sg;
3281
3282 qc->flags |= ATA_QCFLAG_SINGLE;
3283
3284 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 3285 qc->__sg = &qc->sgent;
1da177e4 3286 qc->n_elem = 1;
cedc9a47 3287 qc->orig_n_elem = 1;
1da177e4
LT		 3288 qc->buf_virt = buf;
3289
cedc9a47 3290 sg = qc->__sg;
f0612bbc 3291 sg_init_one(sg, buf, buflen);
1da177e4
LT		 3292}
3293
0cba632b
JG		 3294/**
3295 * ata_sg_init - Associate command with scatter-gather table.
3296 * @qc: Command to be associated
3297 * @sg: Scatter-gather table.
3298 * @n_elem: Number of elements in s/g table.
3299 *
3300 * Initialize the data-related elements of queued_cmd @qc
3301 * to point to a scatter-gather table @sg, containing @n_elem
3302 * elements.
3303 *
3304 * LOCKING:
3305 * spin_lock_irqsave(host_set lock)
3306 */
3307
1da177e4
LT		 3308void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
3309 unsigned int n_elem)
3310{
3311 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 3312 qc->__sg = sg;
1da177e4 3313 qc->n_elem = n_elem;
cedc9a47 3314 qc->orig_n_elem = n_elem;
1da177e4
LT		 3315}
3316
3317/**
0cba632b
JG		 3318 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
3319 * @qc: Command with memory buffer to be mapped.
3320 *
3321 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT		 3322 *
3323 * LOCKING:
3324 * spin_lock_irqsave(host_set lock)
3325 *
3326 * RETURNS:
0cba632b 3327 * Zero on success, negative on error.
1da177e4
LT		 3328 */
3329
3330static int ata_sg_setup_one(struct ata_queued_cmd *qc)
3331{
3332 struct ata_port *ap = qc->ap;
3333 int dir = qc->dma_dir;
cedc9a47 3334 struct scatterlist *sg = qc->__sg;
1da177e4 3335 dma_addr_t dma_address;
2e242fa9 3336 int trim_sg = 0;
1da177e4 3337
cedc9a47
JG		 3338 /* we must lengthen transfers to end on a 32-bit boundary */
3339 qc->pad_len = sg->length & 3;
3340 if (qc->pad_len) {
3341 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3342 struct scatterlist *psg = &qc->pad_sgent;
3343
a4631474 3344 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 3345
3346 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
3347
3348 if (qc->tf.flags & ATA_TFLAG_WRITE)
3349 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
3350 qc->pad_len);
3351
3352 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
3353 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
3354 /* trim sg */
3355 sg->length -= qc->pad_len;
2e242fa9
TH		 3356 if (sg->length == 0)
3357 trim_sg = 1;
cedc9a47
JG		 3358
3359 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
3360 sg->length, qc->pad_len);
3361 }
3362
2e242fa9
TH		 3363 if (trim_sg) {
3364 qc->n_elem--;
e1410f2d
JG		 3365 goto skip_map;
3366 }
3367
2f1f610b 3368 dma_address = dma_map_single(ap->dev, qc->buf_virt,
32529e01 3369 sg->length, dir);
537a95d9
TH		 3370 if (dma_mapping_error(dma_address)) {
3371 /* restore sg */
3372 sg->length += qc->pad_len;
1da177e4 3373 return -1;
537a95d9 3374 }
1da177e4
LT		 3375
3376 sg_dma_address(sg) = dma_address;
32529e01 3377 sg_dma_len(sg) = sg->length;
1da177e4 3378
2e242fa9 3379skip_map:
1da177e4
LT		 3380 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
3381 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3382
3383 return 0;
3384}
3385
3386/**
0cba632b
JG		 3387 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
3388 * @qc: Command with scatter-gather table to be mapped.
3389 *
3390 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT		 3391 *
3392 * LOCKING:
3393 * spin_lock_irqsave(host_set lock)
3394 *
3395 * RETURNS:
0cba632b 3396 * Zero on success, negative on error.
1da177e4
LT		 3397 *
3398 */
3399
3400static int ata_sg_setup(struct ata_queued_cmd *qc)
3401{
3402 struct ata_port *ap = qc->ap;
cedc9a47
JG		 3403 struct scatterlist *sg = qc->__sg;
3404 struct scatterlist *lsg = &sg[qc->n_elem - 1];
e1410f2d 3405 int n_elem, pre_n_elem, dir, trim_sg = 0;
1da177e4
LT		 3406
3407 VPRINTK("ENTER, ata%u\n", ap->id);
a4631474 3408 WARN_ON(!(qc->flags & ATA_QCFLAG_SG));
1da177e4 3409
cedc9a47
JG		 3410 /* we must lengthen transfers to end on a 32-bit boundary */
3411 qc->pad_len = lsg->length & 3;
3412 if (qc->pad_len) {
3413 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3414 struct scatterlist *psg = &qc->pad_sgent;
3415 unsigned int offset;
3416
a4631474 3417 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 3418
3419 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
3420
3421 /*
3422 * psg->page/offset are used to copy to-be-written
3423 * data in this function or read data in ata_sg_clean.
3424 */
3425 offset = lsg->offset + lsg->length - qc->pad_len;
3426 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
3427 psg->offset = offset_in_page(offset);
3428
3429 if (qc->tf.flags & ATA_TFLAG_WRITE) {
3430 void *addr = kmap_atomic(psg->page, KM_IRQ0);
3431 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
dfa15988 3432 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 3433 }
3434
3435 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
3436 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
3437 /* trim last sg */
3438 lsg->length -= qc->pad_len;
e1410f2d
JG		 3439 if (lsg->length == 0)
3440 trim_sg = 1;
cedc9a47
JG		 3441
3442 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
3443 qc->n_elem - 1, lsg->length, qc->pad_len);
3444 }
3445
e1410f2d
JG		 3446 pre_n_elem = qc->n_elem;
3447 if (trim_sg && pre_n_elem)
3448 pre_n_elem--;
3449
3450 if (!pre_n_elem) {
3451 n_elem = 0;
3452 goto skip_map;
3453 }
3454
1da177e4 3455 dir = qc->dma_dir;
2f1f610b 3456 n_elem = dma_map_sg(ap->dev, sg, pre_n_elem, dir);
537a95d9
TH		 3457 if (n_elem < 1) {
3458 /* restore last sg */
3459 lsg->length += qc->pad_len;
1da177e4 3460 return -1;
537a95d9 3461 }
1da177e4
LT		 3462
3463 DPRINTK("%d sg elements mapped\n", n_elem);
3464
e1410f2d 3465skip_map:
1da177e4
LT		 3466 qc->n_elem = n_elem;
3467
3468 return 0;
3469}
3470
0baab86b 3471/**
c893a3ae 3472 * swap_buf_le16 - swap halves of 16-bit words in place
0baab86b
EF		 3473 * @buf: Buffer to swap
3474 * @buf_words: Number of 16-bit words in buffer.
3475 *
3476 * Swap halves of 16-bit words if needed to convert from
3477 * little-endian byte order to native cpu byte order, or
3478 * vice-versa.
3479 *
3480 * LOCKING:
6f0ef4fa 3481 * Inherited from caller.
0baab86b 3482 */
1da177e4
LT		 3483void swap_buf_le16(u16 *buf, unsigned int buf_words)
3484{
3485#ifdef __BIG_ENDIAN
3486 unsigned int i;
3487
3488 for (i = 0; i < buf_words; i++)
3489 buf[i] = le16_to_cpu(buf[i]);
3490#endif /* __BIG_ENDIAN */
3491}
3492
6ae4cfb5
AL		 3493/**
3494 * ata_mmio_data_xfer - Transfer data by MMIO
3495 * @ap: port to read/write
3496 * @buf: data buffer
3497 * @buflen: buffer length
344babaa 3498 * @write_data: read/write
6ae4cfb5
AL		 3499 *
3500 * Transfer data from/to the device data register by MMIO.
3501 *
3502 * LOCKING:
3503 * Inherited from caller.
6ae4cfb5
AL		 3504 */
3505
1da177e4
LT		 3506static void ata_mmio_data_xfer(struct ata_port *ap, unsigned char *buf,
3507 unsigned int buflen, int write_data)
3508{
3509 unsigned int i;
3510 unsigned int words = buflen >> 1;
3511 u16 *buf16 = (u16 *) buf;
3512 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
3513
6ae4cfb5 3514 /* Transfer multiple of 2 bytes */
1da177e4
LT		 3515 if (write_data) {
3516 for (i = 0; i < words; i++)
3517 writew(le16_to_cpu(buf16[i]), mmio);
3518 } else {
3519 for (i = 0; i < words; i++)
3520 buf16[i] = cpu_to_le16(readw(mmio));
3521 }
6ae4cfb5
AL		 3522
3523 /* Transfer trailing 1 byte, if any. */
3524 if (unlikely(buflen & 0x01)) {
3525 u16 align_buf[1] = { 0 };
3526 unsigned char *trailing_buf = buf + buflen - 1;
3527
3528 if (write_data) {
3529 memcpy(align_buf, trailing_buf, 1);
3530 writew(le16_to_cpu(align_buf[0]), mmio);
3531 } else {
3532 align_buf[0] = cpu_to_le16(readw(mmio));
3533 memcpy(trailing_buf, align_buf, 1);
3534 }
3535 }
1da177e4
LT		 3536}
3537
6ae4cfb5
AL		 3538/**
3539 * ata_pio_data_xfer - Transfer data by PIO
3540 * @ap: port to read/write
3541 * @buf: data buffer
3542 * @buflen: buffer length
344babaa 3543 * @write_data: read/write
6ae4cfb5
AL		 3544 *
3545 * Transfer data from/to the device data register by PIO.
3546 *
3547 * LOCKING:
3548 * Inherited from caller.
6ae4cfb5
AL		 3549 */
3550
1da177e4
LT		 3551static void ata_pio_data_xfer(struct ata_port *ap, unsigned char *buf,
3552 unsigned int buflen, int write_data)
3553{
6ae4cfb5 3554 unsigned int words = buflen >> 1;
1da177e4 3555
6ae4cfb5 3556 /* Transfer multiple of 2 bytes */
1da177e4 3557 if (write_data)
6ae4cfb5 3558 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 3559 else
6ae4cfb5
AL		 3560 insw(ap->ioaddr.data_addr, buf, words);
3561
3562 /* Transfer trailing 1 byte, if any. */
3563 if (unlikely(buflen & 0x01)) {
3564 u16 align_buf[1] = { 0 };
3565 unsigned char *trailing_buf = buf + buflen - 1;
3566
3567 if (write_data) {
3568 memcpy(align_buf, trailing_buf, 1);
3569 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
3570 } else {
3571 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
3572 memcpy(trailing_buf, align_buf, 1);
3573 }
3574 }
1da177e4
LT		 3575}
3576
6ae4cfb5
AL		 3577/**
3578 * ata_data_xfer - Transfer data from/to the data register.
3579 * @ap: port to read/write
3580 * @buf: data buffer
3581 * @buflen: buffer length
3582 * @do_write: read/write
3583 *
3584 * Transfer data from/to the device data register.
3585 *
3586 * LOCKING:
3587 * Inherited from caller.
6ae4cfb5
AL		 3588 */
3589
1da177e4
LT		 3590static void ata_data_xfer(struct ata_port *ap, unsigned char *buf,
3591 unsigned int buflen, int do_write)
3592{
a1bd9e68
AC		 3593 /* Make the crap hardware pay the costs not the good stuff */
3594 if (unlikely(ap->flags & ATA_FLAG_IRQ_MASK)) {
3595 unsigned long flags;
3596 local_irq_save(flags);
3597 if (ap->flags & ATA_FLAG_MMIO)
3598 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3599 else
3600 ata_pio_data_xfer(ap, buf, buflen, do_write);
3601 local_irq_restore(flags);
3602 } else {
3603 if (ap->flags & ATA_FLAG_MMIO)
3604 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3605 else
3606 ata_pio_data_xfer(ap, buf, buflen, do_write);
3607 }
1da177e4
LT		 3608}
3609
6ae4cfb5
AL		 3610/**
3611 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
3612 * @qc: Command on going
3613 *
3614 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
3615 *
3616 * LOCKING:
3617 * Inherited from caller.
3618 */
3619
1da177e4
LT		 3620static void ata_pio_sector(struct ata_queued_cmd *qc)
3621{
3622 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3623 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3624 struct ata_port *ap = qc->ap;
3625 struct page *page;
3626 unsigned int offset;
3627 unsigned char *buf;
3628
3629 if (qc->cursect == (qc->nsect - 1))
14be71f4 3630 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3631
3632 page = sg[qc->cursg].page;
3633 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
3634
3635 /* get the current page and offset */
3636 page = nth_page(page, (offset >> PAGE_SHIFT));
3637 offset %= PAGE_SIZE;
3638
1da177e4
LT		 3639 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3640
91b8b313
AL		 3641 if (PageHighMem(page)) {
3642 unsigned long flags;
3643
3644 local_irq_save(flags);
3645 buf = kmap_atomic(page, KM_IRQ0);
083958d3 3646
91b8b313
AL		 3647 /* do the actual data transfer */
3648 ata_data_xfer(ap, buf + offset, ATA_SECT_SIZE, do_write);
1da177e4 3649
91b8b313
AL		 3650 kunmap_atomic(buf, KM_IRQ0);
3651 local_irq_restore(flags);
3652 } else {
3653 buf = page_address(page);
3654 ata_data_xfer(ap, buf + offset, ATA_SECT_SIZE, do_write);
3655 }
1da177e4
LT		 3656
3657 qc->cursect++;
3658 qc->cursg_ofs++;
3659
32529e01 3660 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
1da177e4
LT		 3661 qc->cursg++;
3662 qc->cursg_ofs = 0;
3663 }
1da177e4 3664}
1da177e4 3665
07f6f7d0
AL		 3666/**
3667 * ata_pio_sectors - Transfer one or many 512-byte sectors.
3668 * @qc: Command on going
3669 *
3670 * Transfer one or many ATA_SECT_SIZE of data from/to the
3671 * ATA device for the DRQ request.
3672 *
3673 * LOCKING:
3674 * Inherited from caller.
3675 */
1da177e4 3676
07f6f7d0
AL		 3677static void ata_pio_sectors(struct ata_queued_cmd *qc)
3678{
3679 if (is_multi_taskfile(&qc->tf)) {
3680 /* READ/WRITE MULTIPLE */
3681 unsigned int nsect;
3682
587005de 3683 WARN_ON(qc->dev->multi_count == 0);
1da177e4 3684
07f6f7d0
AL		 3685 nsect = min(qc->nsect - qc->cursect, qc->dev->multi_count);
3686 while (nsect--)
3687 ata_pio_sector(qc);
3688 } else
3689 ata_pio_sector(qc);
3690}
3691
c71c1857
AL		 3692/**
3693 * atapi_send_cdb - Write CDB bytes to hardware
3694 * @ap: Port to which ATAPI device is attached.
3695 * @qc: Taskfile currently active
3696 *
3697 * When device has indicated its readiness to accept
3698 * a CDB, this function is called. Send the CDB.
3699 *
3700 * LOCKING:
3701 * caller.
3702 */
3703
3704static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
3705{
3706 /* send SCSI cdb */
3707 DPRINTK("send cdb\n");
db024d53 3708 WARN_ON(qc->dev->cdb_len < 12);
c71c1857 3709
db024d53 3710 ata_data_xfer(ap, qc->cdb, qc->dev->cdb_len, 1);
c71c1857
AL		 3711 ata_altstatus(ap); /* flush */
3712
3713 switch (qc->tf.protocol) {
3714 case ATA_PROT_ATAPI:
3715 ap->hsm_task_state = HSM_ST;
3716 break;
3717 case ATA_PROT_ATAPI_NODATA:
3718 ap->hsm_task_state = HSM_ST_LAST;
3719 break;
3720 case ATA_PROT_ATAPI_DMA:
3721 ap->hsm_task_state = HSM_ST_LAST;
3722 /* initiate bmdma */
3723 ap->ops->bmdma_start(qc);
3724 break;
3725 }
1da177e4
LT		 3726}
3727
6ae4cfb5
AL		 3728/**
3729 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3730 * @qc: Command on going
3731 * @bytes: number of bytes
3732 *
3733 * Transfer Transfer data from/to the ATAPI device.
3734 *
3735 * LOCKING:
3736 * Inherited from caller.
3737 *
3738 */
3739
1da177e4
LT		 3740static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3741{
3742 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3743 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3744 struct ata_port *ap = qc->ap;
3745 struct page *page;
3746 unsigned char *buf;
3747 unsigned int offset, count;
3748
563a6e1f 3749 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3750 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3751
3752next_sg:
563a6e1f 3753 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3754 /*
563a6e1f
AL		 3755 * The end of qc->sg is reached and the device expects
3756 * more data to transfer. In order not to overrun qc->sg
3757 * and fulfill length specified in the byte count register,
3758 * - for read case, discard trailing data from the device
3759 * - for write case, padding zero data to the device
3760 */
3761 u16 pad_buf[1] = { 0 };
3762 unsigned int words = bytes >> 1;
3763 unsigned int i;
3764
3765 if (words) /* warning if bytes > 1 */
f15a1daf
TH		 3766 ata_dev_printk(qc->dev, KERN_WARNING,
3767 "%u bytes trailing data\n", bytes);
563a6e1f
AL		 3768
3769 for (i = 0; i < words; i++)
3770 ata_data_xfer(ap, (unsigned char*)pad_buf, 2, do_write);
3771
14be71f4 3772 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL		 3773 return;
3774 }
3775
cedc9a47 3776 sg = &qc->__sg[qc->cursg];
1da177e4 3777
1da177e4
LT		 3778 page = sg->page;
3779 offset = sg->offset + qc->cursg_ofs;
3780
3781 /* get the current page and offset */
3782 page = nth_page(page, (offset >> PAGE_SHIFT));
3783 offset %= PAGE_SIZE;
3784
6952df03 3785 /* don't overrun current sg */
32529e01 3786 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT		 3787
3788 /* don't cross page boundaries */
3789 count = min(count, (unsigned int)PAGE_SIZE - offset);
3790
7282aa4b
AL		 3791 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3792
91b8b313
AL		 3793 if (PageHighMem(page)) {
3794 unsigned long flags;
3795
3796 local_irq_save(flags);
3797 buf = kmap_atomic(page, KM_IRQ0);
083958d3 3798
91b8b313
AL		 3799 /* do the actual data transfer */
3800 ata_data_xfer(ap, buf + offset, count, do_write);
7282aa4b 3801
91b8b313
AL		 3802 kunmap_atomic(buf, KM_IRQ0);
3803 local_irq_restore(flags);
3804 } else {
3805 buf = page_address(page);
3806 ata_data_xfer(ap, buf + offset, count, do_write);
3807 }
1da177e4
LT		 3808
3809 bytes -= count;
3810 qc->curbytes += count;
3811 qc->cursg_ofs += count;
3812
32529e01 3813 if (qc->cursg_ofs == sg->length) {
1da177e4
LT		 3814 qc->cursg++;
3815 qc->cursg_ofs = 0;
3816 }
3817
563a6e1f 3818 if (bytes)
1da177e4 3819 goto next_sg;
1da177e4
LT		 3820}
3821
6ae4cfb5
AL		 3822/**
3823 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
3824 * @qc: Command on going
3825 *
3826 * Transfer Transfer data from/to the ATAPI device.
3827 *
3828 * LOCKING:
3829 * Inherited from caller.
6ae4cfb5
AL		 3830 */
3831
1da177e4
LT		 3832static void atapi_pio_bytes(struct ata_queued_cmd *qc)
3833{
3834 struct ata_port *ap = qc->ap;
3835 struct ata_device *dev = qc->dev;
3836 unsigned int ireason, bc_lo, bc_hi, bytes;
3837 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
3838
3839 ap->ops->tf_read(ap, &qc->tf);
3840 ireason = qc->tf.nsect;
3841 bc_lo = qc->tf.lbam;
3842 bc_hi = qc->tf.lbah;
3843 bytes = (bc_hi << 8) | bc_lo;
3844
3845 /* shall be cleared to zero, indicating xfer of data */
3846 if (ireason & (1 << 0))
3847 goto err_out;
3848
3849 /* make sure transfer direction matches expected */
3850 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
3851 if (do_write != i_write)
3852 goto err_out;
3853
312f7da2
AL		 3854 VPRINTK("ata%u: xfering %d bytes\n", ap->id, bytes);
3855
1da177e4
LT		 3856 __atapi_pio_bytes(qc, bytes);
3857
3858 return;
3859
3860err_out:
f15a1daf 3861 ata_dev_printk(dev, KERN_INFO, "ATAPI check failed\n");
11a56d24 3862 qc->err_mask |= AC_ERR_HSM;
14be71f4 3863 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3864}
3865
3866/**
c234fb00
AL		 3867 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
3868 * @ap: the target ata_port
3869 * @qc: qc on going
1da177e4 3870 *
c234fb00
AL		 3871 * RETURNS:
3872 * 1 if ok in workqueue, 0 otherwise.
1da177e4 3873 */
c234fb00
AL		 3874
3875static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc)
1da177e4 3876{
c234fb00
AL		 3877 if (qc->tf.flags & ATA_TFLAG_POLLING)
3878 return 1;
1da177e4 3879
c234fb00
AL		 3880 if (ap->hsm_task_state == HSM_ST_FIRST) {
3881 if (qc->tf.protocol == ATA_PROT_PIO &&
3882 (qc->tf.flags & ATA_TFLAG_WRITE))
3883 return 1;
1da177e4 3884
c234fb00
AL		 3885 if (is_atapi_taskfile(&qc->tf) &&
3886 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
3887 return 1;
fe79e683
AL		 3888 }
3889
c234fb00
AL		 3890 return 0;
3891}
1da177e4 3892
c17ea20d
TH		 3893/**
3894 * ata_hsm_qc_complete - finish a qc running on standard HSM
3895 * @qc: Command to complete
3896 * @in_wq: 1 if called from workqueue, 0 otherwise
3897 *
3898 * Finish @qc which is running on standard HSM.
3899 *
3900 * LOCKING:
3901 * If @in_wq is zero, spin_lock_irqsave(host_set lock).
3902 * Otherwise, none on entry and grabs host lock.
3903 */
3904static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
3905{
3906 struct ata_port *ap = qc->ap;
3907 unsigned long flags;
3908
3909 if (ap->ops->error_handler) {
3910 if (in_wq) {
3911 spin_lock_irqsave(&ap->host_set->lock, flags);
3912
3913 /* EH might have kicked in while host_set lock
3914 * is released.
3915 */
3916 qc = ata_qc_from_tag(ap, qc->tag);
3917 if (qc) {
3918 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
3919 ata_irq_on(ap);
3920 ata_qc_complete(qc);
3921 } else
3922 ata_port_freeze(ap);
3923 }
3924
3925 spin_unlock_irqrestore(&ap->host_set->lock, flags);
3926 } else {
3927 if (likely(!(qc->err_mask & AC_ERR_HSM)))
3928 ata_qc_complete(qc);
3929 else
3930 ata_port_freeze(ap);
3931 }
3932 } else {
3933 if (in_wq) {
3934 spin_lock_irqsave(&ap->host_set->lock, flags);
3935 ata_irq_on(ap);
3936 ata_qc_complete(qc);
3937 spin_unlock_irqrestore(&ap->host_set->lock, flags);
3938 } else
3939 ata_qc_complete(qc);
3940 }
3941}
3942
bb5cb290
AL		 3943/**
3944 * ata_hsm_move - move the HSM to the next state.
3945 * @ap: the target ata_port
3946 * @qc: qc on going
3947 * @status: current device status
3948 * @in_wq: 1 if called from workqueue, 0 otherwise
3949 *
3950 * RETURNS:
3951 * 1 when poll next status needed, 0 otherwise.
3952 */
3953
3954static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
3955 u8 status, int in_wq)
e2cec771 3956{
bb5cb290
AL		 3957 unsigned long flags = 0;
3958 int poll_next;
3959
6912ccd5
AL		 3960 WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
3961
bb5cb290
AL		 3962 /* Make sure ata_qc_issue_prot() does not throw things
3963 * like DMA polling into the workqueue. Notice that
3964 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
3965 */
c234fb00 3966 WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc));
bb5cb290 3967
e2cec771 3968fsm_start:
999bb6f4
AL		 3969 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
3970 ap->id, qc->tf.protocol, ap->hsm_task_state, status);
3971
e2cec771
AL		 3972 switch (ap->hsm_task_state) {
3973 case HSM_ST_FIRST:
bb5cb290
AL		 3974 /* Send first data block or PACKET CDB */
3975
3976 /* If polling, we will stay in the work queue after
3977 * sending the data. Otherwise, interrupt handler
3978 * takes over after sending the data.
3979 */
3980 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
3981
e2cec771
AL		 3982 /* check device status */
3983 if (unlikely((status & (ATA_BUSY | ATA_DRQ)) != ATA_DRQ)) {
3984 /* Wrong status. Let EH handle this */
11a56d24 3985 qc->err_mask |= AC_ERR_HSM;
14be71f4 3986 ap->hsm_task_state = HSM_ST_ERR;
e2cec771 3987 goto fsm_start;
1da177e4
LT		 3988 }
3989
71601958
AL		 3990 /* Device should not ask for data transfer (DRQ=1)
3991 * when it finds something wrong.
eee6c32f
AL		 3992 * We ignore DRQ here and stop the HSM by
3993 * changing hsm_task_state to HSM_ST_ERR and
3994 * let the EH abort the command or reset the device.
71601958
AL		 3995 */
3996 if (unlikely(status & (ATA_ERR | ATA_DF))) {
3997 printk(KERN_WARNING "ata%d: DRQ=1 with device error, dev_stat 0x%X\n",
3998 ap->id, status);
3999 qc->err_mask |= AC_ERR_DEV;
eee6c32f
AL		 4000 ap->hsm_task_state = HSM_ST_ERR;
4001 goto fsm_start;
71601958 4002 }
1da177e4 4003
bb5cb290
AL		 4004 /* Send the CDB (atapi) or the first data block (ata pio out).
4005 * During the state transition, interrupt handler shouldn't
4006 * be invoked before the data transfer is complete and
4007 * hsm_task_state is changed. Hence, the following locking.
4008 */
4009 if (in_wq)
4010 spin_lock_irqsave(&ap->host_set->lock, flags);
1da177e4 4011
bb5cb290
AL		 4012 if (qc->tf.protocol == ATA_PROT_PIO) {
4013 /* PIO data out protocol.
4014 * send first data block.
4015 */
0565c26d 4016
bb5cb290
AL		 4017 /* ata_pio_sectors() might change the state
4018 * to HSM_ST_LAST. so, the state is changed here
4019 * before ata_pio_sectors().
4020 */
4021 ap->hsm_task_state = HSM_ST;
4022 ata_pio_sectors(qc);
4023 ata_altstatus(ap); /* flush */
4024 } else
4025 /* send CDB */
4026 atapi_send_cdb(ap, qc);
4027
4028 if (in_wq)
4029 spin_unlock_irqrestore(&ap->host_set->lock, flags);
4030
4031 /* if polling, ata_pio_task() handles the rest.
4032 * otherwise, interrupt handler takes over from here.
4033 */
e2cec771 4034 break;
1c848984 4035
e2cec771
AL		 4036 case HSM_ST:
4037 /* complete command or read/write the data register */
4038 if (qc->tf.protocol == ATA_PROT_ATAPI) {
4039 /* ATAPI PIO protocol */
4040 if ((status & ATA_DRQ) == 0) {
4041 /* no more data to transfer */
4042 ap->hsm_task_state = HSM_ST_LAST;
4043 goto fsm_start;
4044 }
1da177e4 4045
71601958
AL		 4046 /* Device should not ask for data transfer (DRQ=1)
4047 * when it finds something wrong.
eee6c32f
AL		 4048 * We ignore DRQ here and stop the HSM by
4049 * changing hsm_task_state to HSM_ST_ERR and
4050 * let the EH abort the command or reset the device.
71601958
AL		 4051 */
4052 if (unlikely(status & (ATA_ERR | ATA_DF))) {
4053 printk(KERN_WARNING "ata%d: DRQ=1 with device error, dev_stat 0x%X\n",
4054 ap->id, status);
4055 qc->err_mask |= AC_ERR_DEV;
eee6c32f
AL		 4056 ap->hsm_task_state = HSM_ST_ERR;
4057 goto fsm_start;
71601958 4058 }
1da177e4 4059
e2cec771 4060 atapi_pio_bytes(qc);
7fb6ec28 4061
e2cec771
AL		 4062 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
4063 /* bad ireason reported by device */
4064 goto fsm_start;
1da177e4 4065
e2cec771
AL		 4066 } else {
4067 /* ATA PIO protocol */
4068 if (unlikely((status & ATA_DRQ) == 0)) {
4069 /* handle BSY=0, DRQ=0 as error */
4070 qc->err_mask |= AC_ERR_HSM;
4071 ap->hsm_task_state = HSM_ST_ERR;
4072 goto fsm_start;
4073 }
1da177e4 4074
eee6c32f
AL		 4075 /* For PIO reads, some devices may ask for
4076 * data transfer (DRQ=1) alone with ERR=1.
4077 * We respect DRQ here and transfer one
4078 * block of junk data before changing the
4079 * hsm_task_state to HSM_ST_ERR.
4080 *
4081 * For PIO writes, ERR=1 DRQ=1 doesn't make
4082 * sense since the data block has been
4083 * transferred to the device.
71601958
AL		 4084 */
4085 if (unlikely(status & (ATA_ERR | ATA_DF))) {
71601958
AL		 4086 /* data might be corrputed */
4087 qc->err_mask |= AC_ERR_DEV;
eee6c32f
AL		 4088
4089 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
4090 ata_pio_sectors(qc);
4091 ata_altstatus(ap);
4092 status = ata_wait_idle(ap);
4093 }
4094
4095 /* ata_pio_sectors() might change the
4096 * state to HSM_ST_LAST. so, the state
4097 * is changed after ata_pio_sectors().
4098 */
4099 ap->hsm_task_state = HSM_ST_ERR;
4100 goto fsm_start;
71601958
AL		 4101 }
4102
e2cec771
AL		 4103 ata_pio_sectors(qc);
4104
4105 if (ap->hsm_task_state == HSM_ST_LAST &&
4106 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
4107 /* all data read */
4108 ata_altstatus(ap);
52a32205 4109 status = ata_wait_idle(ap);
e2cec771
AL		 4110 goto fsm_start;
4111 }
4112 }
4113
4114 ata_altstatus(ap); /* flush */
bb5cb290 4115 poll_next = 1;
1da177e4
LT		 4116 break;
4117
14be71f4 4118 case HSM_ST_LAST:
6912ccd5
AL		 4119 if (unlikely(!ata_ok(status))) {
4120 qc->err_mask |= __ac_err_mask(status);
e2cec771
AL		 4121 ap->hsm_task_state = HSM_ST_ERR;
4122 goto fsm_start;
4123 }
4124
4125 /* no more data to transfer */
4332a771
AL		 4126 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
4127 ap->id, qc->dev->devno, status);
e2cec771 4128
6912ccd5
AL		 4129 WARN_ON(qc->err_mask);
4130
e2cec771 4131 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 4132
e2cec771 4133 /* complete taskfile transaction */
c17ea20d 4134 ata_hsm_qc_complete(qc, in_wq);
bb5cb290
AL		 4135
4136 poll_next = 0;
1da177e4
LT		 4137 break;
4138
14be71f4 4139 case HSM_ST_ERR:
e2cec771
AL		 4140 /* make sure qc->err_mask is available to
4141 * know what's wrong and recover
4142 */
4143 WARN_ON(qc->err_mask == 0);
4144
4145 ap->hsm_task_state = HSM_ST_IDLE;
bb5cb290 4146
999bb6f4 4147 /* complete taskfile transaction */
c17ea20d 4148 ata_hsm_qc_complete(qc, in_wq);
bb5cb290
AL		 4149
4150 poll_next = 0;
e2cec771
AL		 4151 break;
4152 default:
bb5cb290 4153 poll_next = 0;
6912ccd5 4154 BUG();
1da177e4
LT		 4155 }
4156
bb5cb290 4157 return poll_next;
1da177e4
LT		 4158}
4159
1da177e4 4160static void ata_pio_task(void *_data)
8061f5f0 4161{
c91af2c8
TH		 4162 struct ata_queued_cmd *qc = _data;
4163 struct ata_port *ap = qc->ap;
8061f5f0 4164 u8 status;
a1af3734 4165 int poll_next;
8061f5f0 4166
7fb6ec28 4167fsm_start:
a1af3734 4168 WARN_ON(ap->hsm_task_state == HSM_ST_IDLE);
8061f5f0 4169
a1af3734
AL		 4170 /*
4171 * This is purely heuristic. This is a fast path.
4172 * Sometimes when we enter, BSY will be cleared in
4173 * a chk-status or two. If not, the drive is probably seeking
4174 * or something. Snooze for a couple msecs, then
4175 * chk-status again. If still busy, queue delayed work.
4176 */
4177 status = ata_busy_wait(ap, ATA_BUSY, 5);
4178 if (status & ATA_BUSY) {
4179 msleep(2);
4180 status = ata_busy_wait(ap, ATA_BUSY, 10);
4181 if (status & ATA_BUSY) {
31ce6dae 4182 ata_port_queue_task(ap, ata_pio_task, qc, ATA_SHORT_PAUSE);
a1af3734
AL		 4183 return;
4184 }
8061f5f0
TH		 4185 }
4186
a1af3734
AL		 4187 /* move the HSM */
4188 poll_next = ata_hsm_move(ap, qc, status, 1);
8061f5f0 4189
a1af3734
AL		 4190 /* another command or interrupt handler
4191 * may be running at this point.
4192 */
4193 if (poll_next)
7fb6ec28 4194 goto fsm_start;
8061f5f0
TH		 4195}
4196
1da177e4
LT		 4197/**
4198 * ata_qc_new - Request an available ATA command, for queueing
4199 * @ap: Port associated with device @dev
4200 * @dev: Device from whom we request an available command structure
4201 *
4202 * LOCKING:
0cba632b 4203 * None.
1da177e4
LT		 4204 */
4205
4206static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
4207{
4208 struct ata_queued_cmd *qc = NULL;
4209 unsigned int i;
4210
e3180499
TH		 4211 /* no command while frozen */
4212 if (unlikely(ap->flags & ATA_FLAG_FROZEN))
4213 return NULL;
4214
2ab7db1f
TH		 4215 /* the last tag is reserved for internal command. */
4216 for (i = 0; i < ATA_MAX_QUEUE - 1; i++)
6cec4a39 4217 if (!test_and_set_bit(i, &ap->qc_allocated)) {
f69499f4 4218 qc = __ata_qc_from_tag(ap, i);
1da177e4
LT		 4219 break;
4220 }
4221
4222 if (qc)
4223 qc->tag = i;
4224
4225 return qc;
4226}
4227
4228/**
4229 * ata_qc_new_init - Request an available ATA command, and initialize it
1da177e4
LT		 4230 * @dev: Device from whom we request an available command structure
4231 *
4232 * LOCKING:
0cba632b 4233 * None.
1da177e4
LT		 4234 */
4235
3373efd8 4236struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev)
1da177e4 4237{
3373efd8 4238 struct ata_port *ap = dev->ap;
1da177e4
LT		 4239 struct ata_queued_cmd *qc;
4240
4241 qc = ata_qc_new(ap);
4242 if (qc) {
1da177e4
LT		 4243 qc->scsicmd = NULL;
4244 qc->ap = ap;
4245 qc->dev = dev;
1da177e4 4246
2c13b7ce 4247 ata_qc_reinit(qc);
1da177e4
LT		 4248 }
4249
4250 return qc;
4251}
4252
1da177e4
LT		 4253/**
4254 * ata_qc_free - free unused ata_queued_cmd
4255 * @qc: Command to complete
4256 *
4257 * Designed to free unused ata_queued_cmd object
4258 * in case something prevents using it.
4259 *
4260 * LOCKING:
0cba632b 4261 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 4262 */
4263void ata_qc_free(struct ata_queued_cmd *qc)
4264{
4ba946e9
TH		 4265 struct ata_port *ap = qc->ap;
4266 unsigned int tag;
4267
a4631474 4268 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
1da177e4 4269
4ba946e9
TH		 4270 qc->flags = 0;
4271 tag = qc->tag;
4272 if (likely(ata_tag_valid(tag))) {
4ba946e9 4273 qc->tag = ATA_TAG_POISON;
6cec4a39 4274 clear_bit(tag, &ap->qc_allocated);
4ba946e9 4275 }
1da177e4
LT		 4276}
4277
76014427 4278void __ata_qc_complete(struct ata_queued_cmd *qc)
1da177e4 4279{
dedaf2b0
TH		 4280 struct ata_port *ap = qc->ap;
4281
a4631474
TH		 4282 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
4283 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
1da177e4
LT		 4284
4285 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
4286 ata_sg_clean(qc);
4287
7401abf2 4288 /* command should be marked inactive atomically with qc completion */
dedaf2b0
TH		 4289 if (qc->tf.protocol == ATA_PROT_NCQ)
4290 ap->sactive &= ~(1 << qc->tag);
4291 else
4292 ap->active_tag = ATA_TAG_POISON;
7401abf2 4293
3f3791d3
AL		 4294 /* atapi: mark qc as inactive to prevent the interrupt handler
4295 * from completing the command twice later, before the error handler
4296 * is called. (when rc != 0 and atapi request sense is needed)
4297 */
4298 qc->flags &= ~ATA_QCFLAG_ACTIVE;
dedaf2b0 4299 ap->qc_active &= ~(1 << qc->tag);
3f3791d3 4300
1da177e4 4301 /* call completion callback */
77853bf2 4302 qc->complete_fn(qc);
1da177e4
LT		 4303}
4304
f686bcb8
TH		 4305/**
4306 * ata_qc_complete - Complete an active ATA command
4307 * @qc: Command to complete
4308 * @err_mask: ATA Status register contents
4309 *
4310 * Indicate to the mid and upper layers that an ATA
4311 * command has completed, with either an ok or not-ok status.
4312 *
4313 * LOCKING:
4314 * spin_lock_irqsave(host_set lock)
4315 */
4316void ata_qc_complete(struct ata_queued_cmd *qc)
4317{
4318 struct ata_port *ap = qc->ap;
4319
4320 /* XXX: New EH and old EH use different mechanisms to
4321 * synchronize EH with regular execution path.
4322 *
4323 * In new EH, a failed qc is marked with ATA_QCFLAG_FAILED.
4324 * Normal execution path is responsible for not accessing a
4325 * failed qc. libata core enforces the rule by returning NULL
4326 * from ata_qc_from_tag() for failed qcs.
4327 *
4328 * Old EH depends on ata_qc_complete() nullifying completion
4329 * requests if ATA_QCFLAG_EH_SCHEDULED is set. Old EH does
4330 * not synchronize with interrupt handler. Only PIO task is
4331 * taken care of.
4332 */
4333 if (ap->ops->error_handler) {
4334 WARN_ON(ap->flags & ATA_FLAG_FROZEN);
4335
4336 if (unlikely(qc->err_mask))
4337 qc->flags |= ATA_QCFLAG_FAILED;
4338
4339 if (unlikely(qc->flags & ATA_QCFLAG_FAILED)) {
4340 if (!ata_tag_internal(qc->tag)) {
4341 /* always fill result TF for failed qc */
4342 ap->ops->tf_read(ap, &qc->result_tf);
4343 ata_qc_schedule_eh(qc);
4344 return;
4345 }
4346 }
4347
4348 /* read result TF if requested */
4349 if (qc->flags & ATA_QCFLAG_RESULT_TF)
4350 ap->ops->tf_read(ap, &qc->result_tf);
4351
4352 __ata_qc_complete(qc);
4353 } else {
4354 if (qc->flags & ATA_QCFLAG_EH_SCHEDULED)
4355 return;
4356
4357 /* read result TF if failed or requested */
4358 if (qc->err_mask || qc->flags & ATA_QCFLAG_RESULT_TF)
4359 ap->ops->tf_read(ap, &qc->result_tf);
4360
4361 __ata_qc_complete(qc);
4362 }
4363}
4364
dedaf2b0
TH		 4365/**
4366 * ata_qc_complete_multiple - Complete multiple qcs successfully
4367 * @ap: port in question
4368 * @qc_active: new qc_active mask
4369 * @finish_qc: LLDD callback invoked before completing a qc
4370 *
4371 * Complete in-flight commands. This functions is meant to be
4372 * called from low-level driver's interrupt routine to complete
4373 * requests normally. ap->qc_active and @qc_active is compared
4374 * and commands are completed accordingly.
4375 *
4376 * LOCKING:
4377 * spin_lock_irqsave(host_set lock)
4378 *
4379 * RETURNS:
4380 * Number of completed commands on success, -errno otherwise.
4381 */
4382int ata_qc_complete_multiple(struct ata_port *ap, u32 qc_active,
4383 void (*finish_qc)(struct ata_queued_cmd *))
4384{
4385 int nr_done = 0;
4386 u32 done_mask;
4387 int i;
4388
4389 done_mask = ap->qc_active ^ qc_active;
4390
4391 if (unlikely(done_mask & qc_active)) {
4392 ata_port_printk(ap, KERN_ERR, "illegal qc_active transition "
4393 "(%08x->%08x)\n", ap->qc_active, qc_active);
4394 return -EINVAL;
4395 }
4396
4397 for (i = 0; i < ATA_MAX_QUEUE; i++) {
4398 struct ata_queued_cmd *qc;
4399
4400 if (!(done_mask & (1 << i)))
4401 continue;
4402
4403 if ((qc = ata_qc_from_tag(ap, i))) {
4404 if (finish_qc)
4405 finish_qc(qc);
4406 ata_qc_complete(qc);
4407 nr_done++;
4408 }
4409 }
4410
4411 return nr_done;
4412}
4413
1da177e4
LT		 4414static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
4415{
4416 struct ata_port *ap = qc->ap;
4417
4418 switch (qc->tf.protocol) {
4419 case ATA_PROT_DMA:
4420 case ATA_PROT_ATAPI_DMA:
4421 return 1;
4422
4423 case ATA_PROT_ATAPI:
4424 case ATA_PROT_PIO:
1da177e4
LT		 4425 if (ap->flags & ATA_FLAG_PIO_DMA)
4426 return 1;
4427
4428 /* fall through */
4429
4430 default:
4431 return 0;
4432 }
4433
4434 /* never reached */
4435}
4436
4437/**
4438 * ata_qc_issue - issue taskfile to device
4439 * @qc: command to issue to device
4440 *
4441 * Prepare an ATA command to submission to device.
4442 * This includes mapping the data into a DMA-able
4443 * area, filling in the S/G table, and finally
4444 * writing the taskfile to hardware, starting the command.
4445 *
4446 * LOCKING:
4447 * spin_lock_irqsave(host_set lock)
1da177e4 4448 */
8e0e694a 4449void ata_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 4450{
4451 struct ata_port *ap = qc->ap;
4452
dedaf2b0
TH		 4453 /* Make sure only one non-NCQ command is outstanding. The
4454 * check is skipped for old EH because it reuses active qc to
4455 * request ATAPI sense.
4456 */
4457 WARN_ON(ap->ops->error_handler && ata_tag_valid(ap->active_tag));
4458
4459 if (qc->tf.protocol == ATA_PROT_NCQ) {
4460 WARN_ON(ap->sactive & (1 << qc->tag));
4461 ap->sactive |= 1 << qc->tag;
4462 } else {
4463 WARN_ON(ap->sactive);
4464 ap->active_tag = qc->tag;
4465 }
4466
e4a70e76 4467 qc->flags |= ATA_QCFLAG_ACTIVE;
dedaf2b0 4468 ap->qc_active |= 1 << qc->tag;
e4a70e76 4469
1da177e4
LT		 4470 if (ata_should_dma_map(qc)) {
4471 if (qc->flags & ATA_QCFLAG_SG) {
4472 if (ata_sg_setup(qc))
8e436af9 4473 goto sg_err;
1da177e4
LT		 4474 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
4475 if (ata_sg_setup_one(qc))
8e436af9 4476 goto sg_err;
1da177e4
LT		 4477 }
4478 } else {
4479 qc->flags &= ~ATA_QCFLAG_DMAMAP;
4480 }
4481
4482 ap->ops->qc_prep(qc);
4483
8e0e694a
TH		 4484 qc->err_mask |= ap->ops->qc_issue(qc);
4485 if (unlikely(qc->err_mask))
4486 goto err;
4487 return;
1da177e4 4488
8e436af9
TH		 4489sg_err:
4490 qc->flags &= ~ATA_QCFLAG_DMAMAP;
8e0e694a
TH		 4491 qc->err_mask |= AC_ERR_SYSTEM;
4492err:
4493 ata_qc_complete(qc);
1da177e4
LT		 4494}
4495
4496/**
4497 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
4498 * @qc: command to issue to device
4499 *
4500 * Using various libata functions and hooks, this function
4501 * starts an ATA command. ATA commands are grouped into
4502 * classes called "protocols", and issuing each type of protocol
4503 * is slightly different.
4504 *
0baab86b
EF		 4505 * May be used as the qc_issue() entry in ata_port_operations.
4506 *
1da177e4
LT		 4507 * LOCKING:
4508 * spin_lock_irqsave(host_set lock)
4509 *
4510 * RETURNS:
9a3d9eb0 4511 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT		 4512 */
4513
9a3d9eb0 4514unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
1da177e4
LT		 4515{
4516 struct ata_port *ap = qc->ap;
4517
e50362ec
AL		 4518 /* Use polling pio if the LLD doesn't handle
4519 * interrupt driven pio and atapi CDB interrupt.
4520 */
4521 if (ap->flags & ATA_FLAG_PIO_POLLING) {
4522 switch (qc->tf.protocol) {
4523 case ATA_PROT_PIO:
4524 case ATA_PROT_ATAPI:
4525 case ATA_PROT_ATAPI_NODATA:
4526 qc->tf.flags |= ATA_TFLAG_POLLING;
4527 break;
4528 case ATA_PROT_ATAPI_DMA:
4529 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
c2bbc551 4530 /* see ata_check_atapi_dma() */
e50362ec
AL		 4531 BUG();
4532 break;
4533 default:
4534 break;
4535 }
4536 }
4537
312f7da2 4538 /* select the device */
1da177e4
LT		 4539 ata_dev_select(ap, qc->dev->devno, 1, 0);
4540
312f7da2 4541 /* start the command */
1da177e4
LT		 4542 switch (qc->tf.protocol) {
4543 case ATA_PROT_NODATA:
312f7da2
AL		 4544 if (qc->tf.flags & ATA_TFLAG_POLLING)
4545 ata_qc_set_polling(qc);
4546
e5338254 4547 ata_tf_to_host(ap, &qc->tf);
312f7da2
AL		 4548 ap->hsm_task_state = HSM_ST_LAST;
4549
4550 if (qc->tf.flags & ATA_TFLAG_POLLING)
31ce6dae 4551 ata_port_queue_task(ap, ata_pio_task, qc, 0);
312f7da2 4552
1da177e4
LT		 4553 break;
4554
4555 case ATA_PROT_DMA:
587005de 4556 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
312f7da2 4557
1da177e4
LT		 4558 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
4559 ap->ops->bmdma_setup(qc); /* set up bmdma */
4560 ap->ops->bmdma_start(qc); /* initiate bmdma */
312f7da2 4561 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 4562 break;
4563
312f7da2
AL		 4564 case ATA_PROT_PIO:
4565 if (qc->tf.flags & ATA_TFLAG_POLLING)
4566 ata_qc_set_polling(qc);
1da177e4 4567
e5338254 4568 ata_tf_to_host(ap, &qc->tf);
312f7da2 4569
54f00389
AL		 4570 if (qc->tf.flags & ATA_TFLAG_WRITE) {
4571 /* PIO data out protocol */
4572 ap->hsm_task_state = HSM_ST_FIRST;
31ce6dae 4573 ata_port_queue_task(ap, ata_pio_task, qc, 0);
54f00389
AL		 4574
4575 /* always send first data block using
e27486db 4576 * the ata_pio_task() codepath.
54f00389 4577 */
312f7da2 4578 } else {
54f00389
AL		 4579 /* PIO data in protocol */
4580 ap->hsm_task_state = HSM_ST;
4581
4582 if (qc->tf.flags & ATA_TFLAG_POLLING)
31ce6dae 4583 ata_port_queue_task(ap, ata_pio_task, qc, 0);
54f00389
AL		 4584
4585 /* if polling, ata_pio_task() handles the rest.
4586 * otherwise, interrupt handler takes over from here.
4587 */
312f7da2
AL		 4588 }
4589
1da177e4
LT		 4590 break;
4591
1da177e4 4592 case ATA_PROT_ATAPI:
1da177e4 4593 case ATA_PROT_ATAPI_NODATA:
312f7da2
AL		 4594 if (qc->tf.flags & ATA_TFLAG_POLLING)
4595 ata_qc_set_polling(qc);
4596
e5338254 4597 ata_tf_to_host(ap, &qc->tf);
f6ef65e6 4598
312f7da2
AL		 4599 ap->hsm_task_state = HSM_ST_FIRST;
4600
4601 /* send cdb by polling if no cdb interrupt */
4602 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
4603 (qc->tf.flags & ATA_TFLAG_POLLING))
31ce6dae 4604 ata_port_queue_task(ap, ata_pio_task, qc, 0);
1da177e4
LT		 4605 break;
4606
4607 case ATA_PROT_ATAPI_DMA:
587005de 4608 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
312f7da2 4609
1da177e4
LT		 4610 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
4611 ap->ops->bmdma_setup(qc); /* set up bmdma */
312f7da2
AL		 4612 ap->hsm_task_state = HSM_ST_FIRST;
4613
4614 /* send cdb by polling if no cdb interrupt */
4615 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
31ce6dae 4616 ata_port_queue_task(ap, ata_pio_task, qc, 0);
1da177e4
LT		 4617 break;
4618
4619 default:
4620 WARN_ON(1);
9a3d9eb0 4621 return AC_ERR_SYSTEM;
1da177e4
LT		 4622 }
4623
4624 return 0;
4625}
4626
1da177e4
LT		 4627/**
4628 * ata_host_intr - Handle host interrupt for given (port, task)
4629 * @ap: Port on which interrupt arrived (possibly...)
4630 * @qc: Taskfile currently active in engine
4631 *
4632 * Handle host interrupt for given queued command. Currently,
4633 * only DMA interrupts are handled. All other commands are
4634 * handled via polling with interrupts disabled (nIEN bit).
4635 *
4636 * LOCKING:
4637 * spin_lock_irqsave(host_set lock)
4638 *
4639 * RETURNS:
4640 * One if interrupt was handled, zero if not (shared irq).
4641 */
4642
4643inline unsigned int ata_host_intr (struct ata_port *ap,
4644 struct ata_queued_cmd *qc)
4645{
312f7da2 4646 u8 status, host_stat = 0;
1da177e4 4647
312f7da2
AL		 4648 VPRINTK("ata%u: protocol %d task_state %d\n",
4649 ap->id, qc->tf.protocol, ap->hsm_task_state);
1da177e4 4650
312f7da2
AL		 4651 /* Check whether we are expecting interrupt in this state */
4652 switch (ap->hsm_task_state) {
4653 case HSM_ST_FIRST:
6912ccd5
AL		 4654 /* Some pre-ATAPI-4 devices assert INTRQ
4655 * at this state when ready to receive CDB.
4656 */
1da177e4 4657
312f7da2
AL		 4658 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
4659 * The flag was turned on only for atapi devices.
4660 * No need to check is_atapi_taskfile(&qc->tf) again.
4661 */
4662 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1da177e4 4663 goto idle_irq;
1da177e4 4664 break;
312f7da2
AL		 4665 case HSM_ST_LAST:
4666 if (qc->tf.protocol == ATA_PROT_DMA ||
4667 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
4668 /* check status of DMA engine */
4669 host_stat = ap->ops->bmdma_status(ap);
4670 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
4671
4672 /* if it's not our irq... */
4673 if (!(host_stat & ATA_DMA_INTR))
4674 goto idle_irq;
4675
4676 /* before we do anything else, clear DMA-Start bit */
4677 ap->ops->bmdma_stop(qc);
a4f16610
AL		 4678
4679 if (unlikely(host_stat & ATA_DMA_ERR)) {
4680 /* error when transfering data to/from memory */
4681 qc->err_mask |= AC_ERR_HOST_BUS;
4682 ap->hsm_task_state = HSM_ST_ERR;
4683 }
312f7da2
AL		 4684 }
4685 break;
4686 case HSM_ST:
4687 break;
1da177e4
LT		 4688 default:
4689 goto idle_irq;
4690 }
4691
312f7da2
AL		 4692 /* check altstatus */
4693 status = ata_altstatus(ap);
4694 if (status & ATA_BUSY)
4695 goto idle_irq;
1da177e4 4696
312f7da2
AL		 4697 /* check main status, clearing INTRQ */
4698 status = ata_chk_status(ap);
4699 if (unlikely(status & ATA_BUSY))
4700 goto idle_irq;
1da177e4 4701
312f7da2
AL		 4702 /* ack bmdma irq events */
4703 ap->ops->irq_clear(ap);
1da177e4 4704
bb5cb290 4705 ata_hsm_move(ap, qc, status, 0);
1da177e4
LT		 4706 return 1; /* irq handled */
4707
4708idle_irq:
4709 ap->stats.idle_irq++;
4710
4711#ifdef ATA_IRQ_TRAP
4712 if ((ap->stats.idle_irq % 1000) == 0) {
1da177e4 4713 ata_irq_ack(ap, 0); /* debug trap */
f15a1daf 4714 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
23cfce89 4715 return 1;
1da177e4
LT		 4716 }
4717#endif
4718 return 0; /* irq not handled */
4719}
4720
4721/**
4722 * ata_interrupt - Default ATA host interrupt handler
0cba632b
JG		 4723 * @irq: irq line (unused)
4724 * @dev_instance: pointer to our ata_host_set information structure
1da177e4
LT		 4725 * @regs: unused
4726 *
0cba632b
JG		 4727 * Default interrupt handler for PCI IDE devices. Calls
4728 * ata_host_intr() for each port that is not disabled.
4729 *
1da177e4 4730 * LOCKING:
0cba632b 4731 * Obtains host_set lock during operation.
1da177e4
LT		 4732 *
4733 * RETURNS:
0cba632b 4734 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT		 4735 */
4736
4737irqreturn_t ata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
4738{
4739 struct ata_host_set *host_set = dev_instance;
4740 unsigned int i;
4741 unsigned int handled = 0;
4742 unsigned long flags;
4743
4744 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
4745 spin_lock_irqsave(&host_set->lock, flags);
4746
4747 for (i = 0; i < host_set->n_ports; i++) {
4748 struct ata_port *ap;
4749
4750 ap = host_set->ports[i];
c1389503 4751 if (ap &&
029f5468 4752 !(ap->flags & ATA_FLAG_DISABLED)) {
1da177e4
LT		 4753 struct ata_queued_cmd *qc;
4754
4755 qc = ata_qc_from_tag(ap, ap->active_tag);
312f7da2 4756 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
21b1ed74 4757 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT		 4758 handled |= ata_host_intr(ap, qc);
4759 }
4760 }
4761
4762 spin_unlock_irqrestore(&host_set->lock, flags);
4763
4764 return IRQ_RETVAL(handled);
4765}
4766
34bf2170
TH		 4767/**
4768 * sata_scr_valid - test whether SCRs are accessible
4769 * @ap: ATA port to test SCR accessibility for
4770 *
4771 * Test whether SCRs are accessible for @ap.
4772 *
4773 * LOCKING:
4774 * None.
4775 *
4776 * RETURNS:
4777 * 1 if SCRs are accessible, 0 otherwise.
4778 */
4779int sata_scr_valid(struct ata_port *ap)
4780{
4781 return ap->cbl == ATA_CBL_SATA && ap->ops->scr_read;
4782}
4783
4784/**
4785 * sata_scr_read - read SCR register of the specified port
4786 * @ap: ATA port to read SCR for
4787 * @reg: SCR to read
4788 * @val: Place to store read value
4789 *
4790 * Read SCR register @reg of @ap into *@val. This function is
4791 * guaranteed to succeed if the cable type of the port is SATA
4792 * and the port implements ->scr_read.
4793 *
4794 * LOCKING:
4795 * None.
4796 *
4797 * RETURNS:
4798 * 0 on success, negative errno on failure.
4799 */
4800int sata_scr_read(struct ata_port *ap, int reg, u32 *val)
4801{
4802 if (sata_scr_valid(ap)) {
4803 *val = ap->ops->scr_read(ap, reg);
4804 return 0;
4805 }
4806 return -EOPNOTSUPP;
4807}
4808
4809/**
4810 * sata_scr_write - write SCR register of the specified port
4811 * @ap: ATA port to write SCR for
4812 * @reg: SCR to write
4813 * @val: value to write
4814 *
4815 * Write @val to SCR register @reg of @ap. This function is
4816 * guaranteed to succeed if the cable type of the port is SATA
4817 * and the port implements ->scr_read.
4818 *
4819 * LOCKING:
4820 * None.
4821 *
4822 * RETURNS:
4823 * 0 on success, negative errno on failure.
4824 */
4825int sata_scr_write(struct ata_port *ap, int reg, u32 val)
4826{
4827 if (sata_scr_valid(ap)) {
4828 ap->ops->scr_write(ap, reg, val);
4829 return 0;
4830 }
4831 return -EOPNOTSUPP;
4832}
4833
4834/**
4835 * sata_scr_write_flush - write SCR register of the specified port and flush
4836 * @ap: ATA port to write SCR for
4837 * @reg: SCR to write
4838 * @val: value to write
4839 *
4840 * This function is identical to sata_scr_write() except that this
4841 * function performs flush after writing to the register.
4842 *
4843 * LOCKING:
4844 * None.
4845 *
4846 * RETURNS:
4847 * 0 on success, negative errno on failure.
4848 */
4849int sata_scr_write_flush(struct ata_port *ap, int reg, u32 val)
4850{
4851 if (sata_scr_valid(ap)) {
4852 ap->ops->scr_write(ap, reg, val);
4853 ap->ops->scr_read(ap, reg);
4854 return 0;
4855 }
4856 return -EOPNOTSUPP;
4857}
4858
4859/**
4860 * ata_port_online - test whether the given port is online
4861 * @ap: ATA port to test
4862 *
4863 * Test whether @ap is online. Note that this function returns 0
4864 * if online status of @ap cannot be obtained, so
4865 * ata_port_online(ap) != !ata_port_offline(ap).
4866 *
4867 * LOCKING:
4868 * None.
4869 *
4870 * RETURNS:
4871 * 1 if the port online status is available and online.
4872 */
4873int ata_port_online(struct ata_port *ap)
4874{
4875 u32 sstatus;
4876
4877 if (!sata_scr_read(ap, SCR_STATUS, &sstatus) && (sstatus & 0xf) == 0x3)
4878 return 1;
4879 return 0;
4880}
4881
4882/**
4883 * ata_port_offline - test whether the given port is offline
4884 * @ap: ATA port to test
4885 *
4886 * Test whether @ap is offline. Note that this function returns
4887 * 0 if offline status of @ap cannot be obtained, so
4888 * ata_port_online(ap) != !ata_port_offline(ap).
4889 *
4890 * LOCKING:
4891 * None.
4892 *
4893 * RETURNS:
4894 * 1 if the port offline status is available and offline.
4895 */
4896int ata_port_offline(struct ata_port *ap)
4897{
4898 u32 sstatus;
4899
4900 if (!sata_scr_read(ap, SCR_STATUS, &sstatus) && (sstatus & 0xf) != 0x3)
4901 return 1;
4902 return 0;
4903}
0baab86b 4904
9b847548
JA		 4905/*
4906 * Execute a 'simple' command, that only consists of the opcode 'cmd' itself,
4907 * without filling any other registers
4908 */
3373efd8 4909static int ata_do_simple_cmd(struct ata_device *dev, u8 cmd)
9b847548
JA		 4910{
4911 struct ata_taskfile tf;
4912 int err;
4913
3373efd8 4914 ata_tf_init(dev, &tf);
9b847548
JA		 4915
4916 tf.command = cmd;
4917 tf.flags |= ATA_TFLAG_DEVICE;
4918 tf.protocol = ATA_PROT_NODATA;
4919
3373efd8 4920 err = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0);
9b847548 4921 if (err)
f15a1daf
TH		 4922 ata_dev_printk(dev, KERN_ERR, "%s: ata command failed: %d\n",
4923 __FUNCTION__, err);
9b847548
JA		 4924
4925 return err;
4926}
4927
3373efd8 4928static int ata_flush_cache(struct ata_device *dev)
9b847548
JA		 4929{
4930 u8 cmd;
4931
4932 if (!ata_try_flush_cache(dev))
4933 return 0;
4934
4935 if (ata_id_has_flush_ext(dev->id))
4936 cmd = ATA_CMD_FLUSH_EXT;
4937 else
4938 cmd = ATA_CMD_FLUSH;
4939
3373efd8 4940 return ata_do_simple_cmd(dev, cmd);
9b847548
JA		 4941}
4942
3373efd8 4943static int ata_standby_drive(struct ata_device *dev)
9b847548 4944{
3373efd8 4945 return ata_do_simple_cmd(dev, ATA_CMD_STANDBYNOW1);
9b847548
JA		 4946}
4947
3373efd8 4948static int ata_start_drive(struct ata_device *dev)
9b847548 4949{
3373efd8 4950 return ata_do_simple_cmd(dev, ATA_CMD_IDLEIMMEDIATE);
9b847548
JA		 4951}
4952
4953/**
4954 * ata_device_resume - wakeup a previously suspended devices
c893a3ae 4955 * @dev: the device to resume
9b847548
JA		 4956 *
4957 * Kick the drive back into action, by sending it an idle immediate
4958 * command and making sure its transfer mode matches between drive
4959 * and host.
4960 *
4961 */
3373efd8 4962int ata_device_resume(struct ata_device *dev)
9b847548 4963{
3373efd8
TH		 4964 struct ata_port *ap = dev->ap;
4965
9b847548 4966 if (ap->flags & ATA_FLAG_SUSPENDED) {
e82cbdb9 4967 struct ata_device *failed_dev;
9b847548 4968 ap->flags &= ~ATA_FLAG_SUSPENDED;
e82cbdb9 4969 while (ata_set_mode(ap, &failed_dev))
3373efd8 4970 ata_dev_disable(failed_dev);
9b847548 4971 }
e1211e3f 4972 if (!ata_dev_enabled(dev))
9b847548
JA		 4973 return 0;
4974 if (dev->class == ATA_DEV_ATA)
3373efd8 4975 ata_start_drive(dev);
9b847548
JA		 4976
4977 return 0;
4978}
4979
4980/**
4981 * ata_device_suspend - prepare a device for suspend
c893a3ae 4982 * @dev: the device to suspend
9b847548
JA		 4983 *
4984 * Flush the cache on the drive, if appropriate, then issue a
4985 * standbynow command.
9b847548 4986 */
3373efd8 4987int ata_device_suspend(struct ata_device *dev, pm_message_t state)
9b847548 4988{
3373efd8
TH		 4989 struct ata_port *ap = dev->ap;
4990
e1211e3f 4991 if (!ata_dev_enabled(dev))
9b847548
JA		 4992 return 0;
4993 if (dev->class == ATA_DEV_ATA)
3373efd8 4994 ata_flush_cache(dev);
9b847548 4995
082776e4 4996 if (state.event != PM_EVENT_FREEZE)
3373efd8 4997 ata_standby_drive(dev);
9b847548
JA		 4998 ap->flags |= ATA_FLAG_SUSPENDED;
4999 return 0;
5000}
5001
c893a3ae
RD		 5002/**
5003 * ata_port_start - Set port up for dma.
5004 * @ap: Port to initialize
5005 *
5006 * Called just after data structures for each port are
5007 * initialized. Allocates space for PRD table.
5008 *
5009 * May be used as the port_start() entry in ata_port_operations.
5010 *
5011 * LOCKING:
5012 * Inherited from caller.
5013 */
5014
1da177e4
LT		 5015int ata_port_start (struct ata_port *ap)
5016{
2f1f610b 5017 struct device *dev = ap->dev;
6037d6bb 5018 int rc;
1da177e4
LT		 5019
5020 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
5021 if (!ap->prd)
5022 return -ENOMEM;
5023
6037d6bb
JG		 5024 rc = ata_pad_alloc(ap, dev);
5025 if (rc) {
cedc9a47 5026 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 5027 return rc;
cedc9a47
JG		 5028 }
5029
1da177e4
LT		 5030 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
5031
5032 return 0;
5033}
5034
0baab86b
EF		 5035
5036/**
5037 * ata_port_stop - Undo ata_port_start()
5038 * @ap: Port to shut down
5039 *
5040 * Frees the PRD table.
5041 *
5042 * May be used as the port_stop() entry in ata_port_operations.
5043 *
5044 * LOCKING:
6f0ef4fa 5045 * Inherited from caller.
0baab86b
EF		 5046 */
5047
1da177e4
LT		 5048void ata_port_stop (struct ata_port *ap)
5049{
2f1f610b 5050 struct device *dev = ap->dev;
1da177e4
LT		 5051
5052 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 5053 ata_pad_free(ap, dev);
1da177e4
LT		 5054}
5055
aa8f0dc6
JG		 5056void ata_host_stop (struct ata_host_set *host_set)
5057{
5058 if (host_set->mmio_base)
5059 iounmap(host_set->mmio_base);
5060}
5061
5062
1da177e4
LT		 5063/**
5064 * ata_host_remove - Unregister SCSI host structure with upper layers
5065 * @ap: Port to unregister
5066 * @do_unregister: 1 if we fully unregister, 0 to just stop the port
5067 *
5068 * LOCKING:
6f0ef4fa 5069 * Inherited from caller.
1da177e4
LT		 5070 */
5071
5072static void ata_host_remove(struct ata_port *ap, unsigned int do_unregister)
5073{
5074 struct Scsi_Host *sh = ap->host;
5075
5076 DPRINTK("ENTER\n");
5077
5078 if (do_unregister)
5079 scsi_remove_host(sh);
5080
5081 ap->ops->port_stop(ap);
5082}
5083
5084/**
5085 * ata_host_init - Initialize an ata_port structure
5086 * @ap: Structure to initialize
5087 * @host: associated SCSI mid-layer structure
5088 * @host_set: Collection of hosts to which @ap belongs
5089 * @ent: Probe information provided by low-level driver
5090 * @port_no: Port number associated with this ata_port
5091 *
0cba632b
JG		 5092 * Initialize a new ata_port structure, and its associated
5093 * scsi_host.
5094 *
1da177e4 5095 * LOCKING:
0cba632b 5096 * Inherited from caller.
1da177e4
LT		 5097 */
5098
5099static void ata_host_init(struct ata_port *ap, struct Scsi_Host *host,
5100 struct ata_host_set *host_set,
057ace5e 5101 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT		 5102{
5103 unsigned int i;
5104
5105 host->max_id = 16;
5106 host->max_lun = 1;
5107 host->max_channel = 1;
5108 host->unique_id = ata_unique_id++;
5109 host->max_cmd_len = 12;
12413197 5110
198e0fed 5111 ap->flags = ATA_FLAG_DISABLED;
1da177e4
LT		 5112 ap->id = host->unique_id;
5113 ap->host = host;
5114 ap->ctl = ATA_DEVCTL_OBS;
5115 ap->host_set = host_set;
2f1f610b 5116 ap->dev = ent->dev;
1da177e4
LT		 5117 ap->port_no = port_no;
5118 ap->hard_port_no =
5119 ent->legacy_mode ? ent->hard_port_no : port_no;
5120 ap->pio_mask = ent->pio_mask;
5121 ap->mwdma_mask = ent->mwdma_mask;
5122 ap->udma_mask = ent->udma_mask;
5123 ap->flags |= ent->host_flags;
5124 ap->ops = ent->port_ops;
1c3fae4d 5125 ap->sata_spd_limit = UINT_MAX;
1da177e4
LT		 5126 ap->active_tag = ATA_TAG_POISON;
5127 ap->last_ctl = 0xFF;
5128
86e45b6b 5129 INIT_WORK(&ap->port_task, NULL, NULL);
a72ec4ce 5130 INIT_LIST_HEAD(&ap->eh_done_q);
1da177e4 5131
838df628
TH		 5132 /* set cable type */
5133 ap->cbl = ATA_CBL_NONE;
5134 if (ap->flags & ATA_FLAG_SATA)
5135 ap->cbl = ATA_CBL_SATA;
5136
acf356b1
TH		 5137 for (i = 0; i < ATA_MAX_DEVICES; i++) {
5138 struct ata_device *dev = &ap->device[i];
38d87234 5139 dev->ap = ap;
acf356b1
TH		 5140 dev->devno = i;
5141 dev->pio_mask = UINT_MAX;
5142 dev->mwdma_mask = UINT_MAX;
5143 dev->udma_mask = UINT_MAX;
5144 }
1da177e4
LT		 5145
5146#ifdef ATA_IRQ_TRAP
5147 ap->stats.unhandled_irq = 1;
5148 ap->stats.idle_irq = 1;
5149#endif
5150
5151 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
5152}
5153
5154/**
5155 * ata_host_add - Attach low-level ATA driver to system
5156 * @ent: Information provided by low-level driver
5157 * @host_set: Collections of ports to which we add
5158 * @port_no: Port number associated with this host
5159 *
0cba632b
JG		 5160 * Attach low-level ATA driver to system.
5161 *
1da177e4 5162 * LOCKING:
0cba632b 5163 * PCI/etc. bus probe sem.
1da177e4
LT		 5164 *
5165 * RETURNS:
0cba632b 5166 * New ata_port on success, for NULL on error.
1da177e4
LT		 5167 */
5168
057ace5e 5169static struct ata_port * ata_host_add(const struct ata_probe_ent *ent,
1da177e4
LT		 5170 struct ata_host_set *host_set,
5171 unsigned int port_no)
5172{
5173 struct Scsi_Host *host;
5174 struct ata_port *ap;
5175 int rc;
5176
5177 DPRINTK("ENTER\n");
aec5c3c1
TH		 5178
5179 if (!ent->port_ops->probe_reset &&
5180 !(ent->host_flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST))) {
5181 printk(KERN_ERR "ata%u: no reset mechanism available\n",
5182 port_no);
5183 return NULL;
5184 }
5185
1da177e4
LT		 5186 host = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
5187 if (!host)
5188 return NULL;
5189
30afc84c
TH		 5190 host->transportt = &ata_scsi_transport_template;
5191
35bb94b1 5192 ap = ata_shost_to_port(host);
1da177e4
LT		 5193
5194 ata_host_init(ap, host, host_set, ent, port_no);
5195
5196 rc = ap->ops->port_start(ap);
5197 if (rc)
5198 goto err_out;
5199
5200 return ap;
5201
5202err_out:
5203 scsi_host_put(host);
5204 return NULL;
5205}
5206
5207/**
0cba632b
JG		 5208 * ata_device_add - Register hardware device with ATA and SCSI layers
5209 * @ent: Probe information describing hardware device to be registered
5210 *
5211 * This function processes the information provided in the probe
5212 * information struct @ent, allocates the necessary ATA and SCSI
5213 * host information structures, initializes them, and registers
5214 * everything with requisite kernel subsystems.
5215 *
5216 * This function requests irqs, probes the ATA bus, and probes
5217 * the SCSI bus.
1da177e4
LT		 5218 *
5219 * LOCKING:
0cba632b 5220 * PCI/etc. bus probe sem.
1da177e4
LT		 5221 *
5222 * RETURNS:
0cba632b 5223 * Number of ports registered. Zero on error (no ports registered).
1da177e4
LT		 5224 */
5225
057ace5e 5226int ata_device_add(const struct ata_probe_ent *ent)
1da177e4
LT		 5227{
5228 unsigned int count = 0, i;
5229 struct device *dev = ent->dev;
5230 struct ata_host_set *host_set;
5231
5232 DPRINTK("ENTER\n");
5233 /* alloc a container for our list of ATA ports (buses) */
57f3bda8 5234 host_set = kzalloc(sizeof(struct ata_host_set) +
1da177e4
LT		 5235 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
5236 if (!host_set)
5237 return 0;
1da177e4
LT		 5238 spin_lock_init(&host_set->lock);
5239
5240 host_set->dev = dev;
5241 host_set->n_ports = ent->n_ports;
5242 host_set->irq = ent->irq;
5243 host_set->mmio_base = ent->mmio_base;
5244 host_set->private_data = ent->private_data;
5245 host_set->ops = ent->port_ops;
5444a6f4 5246 host_set->flags = ent->host_set_flags;
1da177e4
LT		 5247
5248 /* register each port bound to this device */
5249 for (i = 0; i < ent->n_ports; i++) {
5250 struct ata_port *ap;
5251 unsigned long xfer_mode_mask;
5252
5253 ap = ata_host_add(ent, host_set, i);
5254 if (!ap)
5255 goto err_out;
5256
5257 host_set->ports[i] = ap;
5258 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
5259 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
5260 (ap->pio_mask << ATA_SHIFT_PIO);
5261
5262 /* print per-port info to dmesg */
f15a1daf
TH		 5263 ata_port_printk(ap, KERN_INFO, "%cATA max %s cmd 0x%lX "
5264 "ctl 0x%lX bmdma 0x%lX irq %lu\n",
5265 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
5266 ata_mode_string(xfer_mode_mask),
5267 ap->ioaddr.cmd_addr,
5268 ap->ioaddr.ctl_addr,
5269 ap->ioaddr.bmdma_addr,
5270 ent->irq);
1da177e4
LT		 5271
5272 ata_chk_status(ap);
5273 host_set->ops->irq_clear(ap);
e3180499 5274 ata_eh_freeze_port(ap); /* freeze port before requesting IRQ */
1da177e4
LT		 5275 count++;
5276 }
5277
57f3bda8
RD		 5278 if (!count)
5279 goto err_free_ret;
1da177e4
LT		 5280
5281 /* obtain irq, that is shared between channels */
5282 if (request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
5283 DRV_NAME, host_set))
5284 goto err_out;
5285
5286 /* perform each probe synchronously */
5287 DPRINTK("probe begin\n");
5288 for (i = 0; i < count; i++) {
5289 struct ata_port *ap;
5290 int rc;
5291
5292 ap = host_set->ports[i];
5293
c893a3ae 5294 DPRINTK("ata%u: bus probe begin\n", ap->id);
1da177e4 5295 rc = ata_bus_probe(ap);
c893a3ae 5296 DPRINTK("ata%u: bus probe end\n", ap->id);
1da177e4
LT		 5297
5298 if (rc) {
5299 /* FIXME: do something useful here?
5300 * Current libata behavior will
5301 * tear down everything when
5302 * the module is removed
5303 * or the h/w is unplugged.
5304 */
5305 }
5306
5307 rc = scsi_add_host(ap->host, dev);
5308 if (rc) {
f15a1daf 5309 ata_port_printk(ap, KERN_ERR, "scsi_add_host failed\n");
1da177e4
LT		 5310 /* FIXME: do something useful here */
5311 /* FIXME: handle unconditional calls to
5312 * scsi_scan_host and ata_host_remove, below,
5313 * at the very least
5314 */
5315 }
5316 }
5317
5318 /* probes are done, now scan each port's disk(s) */
c893a3ae 5319 DPRINTK("host probe begin\n");
1da177e4
LT		 5320 for (i = 0; i < count; i++) {
5321 struct ata_port *ap = host_set->ports[i];
5322
644dd0cc 5323 ata_scsi_scan_host(ap);
1da177e4
LT		 5324 }
5325
5326 dev_set_drvdata(dev, host_set);
5327
5328 VPRINTK("EXIT, returning %u\n", ent->n_ports);
5329 return ent->n_ports; /* success */
5330
5331err_out:
5332 for (i = 0; i < count; i++) {
5333 ata_host_remove(host_set->ports[i], 1);
5334 scsi_host_put(host_set->ports[i]->host);
5335 }
57f3bda8 5336err_free_ret:
1da177e4
LT		 5337 kfree(host_set);
5338 VPRINTK("EXIT, returning 0\n");
5339 return 0;
5340}
5341
17b14451
AC		 5342/**
5343 * ata_host_set_remove - PCI layer callback for device removal
5344 * @host_set: ATA host set that was removed
5345 *
2e9edbf8 5346 * Unregister all objects associated with this host set. Free those
17b14451
AC		 5347 * objects.
5348 *
5349 * LOCKING:
5350 * Inherited from calling layer (may sleep).
5351 */
5352
17b14451
AC		 5353void ata_host_set_remove(struct ata_host_set *host_set)
5354{
5355 struct ata_port *ap;
5356 unsigned int i;
5357
5358 for (i = 0; i < host_set->n_ports; i++) {
5359 ap = host_set->ports[i];
5360 scsi_remove_host(ap->host);
5361 }
5362
5363 free_irq(host_set->irq, host_set);
5364
5365 for (i = 0; i < host_set->n_ports; i++) {
5366 ap = host_set->ports[i];
5367
5368 ata_scsi_release(ap->host);
5369
5370 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
5371 struct ata_ioports *ioaddr = &ap->ioaddr;
5372
5373 if (ioaddr->cmd_addr == 0x1f0)
5374 release_region(0x1f0, 8);
5375 else if (ioaddr->cmd_addr == 0x170)
5376 release_region(0x170, 8);
5377 }
5378
5379 scsi_host_put(ap->host);
5380 }
5381
5382 if (host_set->ops->host_stop)
5383 host_set->ops->host_stop(host_set);
5384
5385 kfree(host_set);
5386}
5387
1da177e4
LT		 5388/**
5389 * ata_scsi_release - SCSI layer callback hook for host unload
5390 * @host: libata host to be unloaded
5391 *
5392 * Performs all duties necessary to shut down a libata port...
5393 * Kill port kthread, disable port, and release resources.
5394 *
5395 * LOCKING:
5396 * Inherited from SCSI layer.
5397 *
5398 * RETURNS:
5399 * One.
5400 */
5401
5402int ata_scsi_release(struct Scsi_Host *host)
5403{
35bb94b1 5404 struct ata_port *ap = ata_shost_to_port(host);
1da177e4
LT		 5405
5406 DPRINTK("ENTER\n");
5407
5408 ap->ops->port_disable(ap);
5409 ata_host_remove(ap, 0);
5410
5411 DPRINTK("EXIT\n");
5412 return 1;
5413}
5414
5415/**
5416 * ata_std_ports - initialize ioaddr with standard port offsets.
5417 * @ioaddr: IO address structure to be initialized
0baab86b
EF		 5418 *
5419 * Utility function which initializes data_addr, error_addr,
5420 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
5421 * device_addr, status_addr, and command_addr to standard offsets
5422 * relative to cmd_addr.
5423 *
5424 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 5425 */
0baab86b 5426
1da177e4
LT		 5427void ata_std_ports(struct ata_ioports *ioaddr)
5428{
5429 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
5430 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
5431 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
5432 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
5433 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
5434 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
5435 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
5436 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
5437 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
5438 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
5439}
5440
0baab86b 5441
374b1873
JG		 5442#ifdef CONFIG_PCI
5443
5444void ata_pci_host_stop (struct ata_host_set *host_set)
5445{
5446 struct pci_dev *pdev = to_pci_dev(host_set->dev);
5447
5448 pci_iounmap(pdev, host_set->mmio_base);
5449}
5450
1da177e4
LT		 5451/**
5452 * ata_pci_remove_one - PCI layer callback for device removal
5453 * @pdev: PCI device that was removed
5454 *
5455 * PCI layer indicates to libata via this hook that
6f0ef4fa 5456 * hot-unplug or module unload event has occurred.
1da177e4
LT		 5457 * Handle this by unregistering all objects associated
5458 * with this PCI device. Free those objects. Then finally
5459 * release PCI resources and disable device.
5460 *
5461 * LOCKING:
5462 * Inherited from PCI layer (may sleep).
5463 */
5464
5465void ata_pci_remove_one (struct pci_dev *pdev)
5466{
5467 struct device *dev = pci_dev_to_dev(pdev);
5468 struct ata_host_set *host_set = dev_get_drvdata(dev);
1da177e4 5469
17b14451 5470 ata_host_set_remove(host_set);
1da177e4
LT		 5471 pci_release_regions(pdev);
5472 pci_disable_device(pdev);
5473 dev_set_drvdata(dev, NULL);
5474}
5475
5476/* move to PCI subsystem */
057ace5e 5477int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT		 5478{
5479 unsigned long tmp = 0;
5480
5481 switch (bits->width) {
5482 case 1: {
5483 u8 tmp8 = 0;
5484 pci_read_config_byte(pdev, bits->reg, &tmp8);
5485 tmp = tmp8;
5486 break;
5487 }
5488 case 2: {
5489 u16 tmp16 = 0;
5490 pci_read_config_word(pdev, bits->reg, &tmp16);
5491 tmp = tmp16;
5492 break;
5493 }
5494 case 4: {
5495 u32 tmp32 = 0;
5496 pci_read_config_dword(pdev, bits->reg, &tmp32);
5497 tmp = tmp32;
5498 break;
5499 }
5500
5501 default:
5502 return -EINVAL;
5503 }
5504
5505 tmp &= bits->mask;
5506
5507 return (tmp == bits->val) ? 1 : 0;
5508}
9b847548
JA		 5509
5510int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t state)
5511{
5512 pci_save_state(pdev);
5513 pci_disable_device(pdev);
5514 pci_set_power_state(pdev, PCI_D3hot);
5515 return 0;
5516}
5517
5518int ata_pci_device_resume(struct pci_dev *pdev)
5519{
5520 pci_set_power_state(pdev, PCI_D0);
5521 pci_restore_state(pdev);
5522 pci_enable_device(pdev);
5523 pci_set_master(pdev);
5524 return 0;
5525}
1da177e4
LT		 5526#endif /* CONFIG_PCI */
5527
5528
1da177e4
LT		 5529static int __init ata_init(void)
5530{
5531 ata_wq = create_workqueue("ata");
5532 if (!ata_wq)
5533 return -ENOMEM;
5534
5535 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
5536 return 0;
5537}
5538
5539static void __exit ata_exit(void)
5540{
5541 destroy_workqueue(ata_wq);
5542}
5543
5544module_init(ata_init);
5545module_exit(ata_exit);
5546
67846b30
JG		 5547static unsigned long ratelimit_time;
5548static spinlock_t ata_ratelimit_lock = SPIN_LOCK_UNLOCKED;
5549
5550int ata_ratelimit(void)
5551{
5552 int rc;
5553 unsigned long flags;
5554
5555 spin_lock_irqsave(&ata_ratelimit_lock, flags);
5556
5557 if (time_after(jiffies, ratelimit_time)) {
5558 rc = 1;
5559 ratelimit_time = jiffies + (HZ/5);
5560 } else
5561 rc = 0;
5562
5563 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
5564
5565 return rc;
5566}
5567
c22daff4
TH		 5568/**
5569 * ata_wait_register - wait until register value changes
5570 * @reg: IO-mapped register
5571 * @mask: Mask to apply to read register value
5572 * @val: Wait condition
5573 * @interval_msec: polling interval in milliseconds
5574 * @timeout_msec: timeout in milliseconds
5575 *
5576 * Waiting for some bits of register to change is a common
5577 * operation for ATA controllers. This function reads 32bit LE
5578 * IO-mapped register @reg and tests for the following condition.
5579 *
5580 * (*@reg & mask) != val
5581 *
5582 * If the condition is met, it returns; otherwise, the process is
5583 * repeated after @interval_msec until timeout.
5584 *
5585 * LOCKING:
5586 * Kernel thread context (may sleep)
5587 *
5588 * RETURNS:
5589 * The final register value.
5590 */
5591u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val,
5592 unsigned long interval_msec,
5593 unsigned long timeout_msec)
5594{
5595 unsigned long timeout;
5596 u32 tmp;
5597
5598 tmp = ioread32(reg);
5599
5600 /* Calculate timeout _after_ the first read to make sure
5601 * preceding writes reach the controller before starting to
5602 * eat away the timeout.
5603 */
5604 timeout = jiffies + (timeout_msec * HZ) / 1000;
5605
5606 while ((tmp & mask) == val && time_before(jiffies, timeout)) {
5607 msleep(interval_msec);
5608 tmp = ioread32(reg);
5609 }
5610
5611 return tmp;
5612}
5613
1da177e4
LT		 5614/*
5615 * libata is essentially a library of internal helper functions for
5616 * low-level ATA host controller drivers. As such, the API/ABI is
5617 * likely to change as new drivers are added and updated.
5618 * Do not depend on ABI/API stability.
5619 */
5620
5621EXPORT_SYMBOL_GPL(ata_std_bios_param);
5622EXPORT_SYMBOL_GPL(ata_std_ports);
5623EXPORT_SYMBOL_GPL(ata_device_add);
17b14451 5624EXPORT_SYMBOL_GPL(ata_host_set_remove);
1da177e4
LT		 5625EXPORT_SYMBOL_GPL(ata_sg_init);
5626EXPORT_SYMBOL_GPL(ata_sg_init_one);
f686bcb8 5627EXPORT_SYMBOL_GPL(ata_qc_complete);
dedaf2b0 5628EXPORT_SYMBOL_GPL(ata_qc_complete_multiple);
1da177e4 5629EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
1da177e4
LT		 5630EXPORT_SYMBOL_GPL(ata_tf_load);
5631EXPORT_SYMBOL_GPL(ata_tf_read);
5632EXPORT_SYMBOL_GPL(ata_noop_dev_select);
5633EXPORT_SYMBOL_GPL(ata_std_dev_select);
5634EXPORT_SYMBOL_GPL(ata_tf_to_fis);
5635EXPORT_SYMBOL_GPL(ata_tf_from_fis);
5636EXPORT_SYMBOL_GPL(ata_check_status);
5637EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT		 5638EXPORT_SYMBOL_GPL(ata_exec_command);
5639EXPORT_SYMBOL_GPL(ata_port_start);
5640EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 5641EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4
LT		 5642EXPORT_SYMBOL_GPL(ata_interrupt);
5643EXPORT_SYMBOL_GPL(ata_qc_prep);
e46834cd 5644EXPORT_SYMBOL_GPL(ata_noop_qc_prep);
1da177e4
LT		 5645EXPORT_SYMBOL_GPL(ata_bmdma_setup);
5646EXPORT_SYMBOL_GPL(ata_bmdma_start);
5647EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
5648EXPORT_SYMBOL_GPL(ata_bmdma_status);
5649EXPORT_SYMBOL_GPL(ata_bmdma_stop);
6d97dbd7
TH		 5650EXPORT_SYMBOL_GPL(ata_bmdma_freeze);
5651EXPORT_SYMBOL_GPL(ata_bmdma_thaw);
5652EXPORT_SYMBOL_GPL(ata_bmdma_drive_eh);
5653EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
5654EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
1da177e4 5655EXPORT_SYMBOL_GPL(ata_port_probe);
3c567b7d 5656EXPORT_SYMBOL_GPL(sata_set_spd);
1da177e4
LT		 5657EXPORT_SYMBOL_GPL(sata_phy_reset);
5658EXPORT_SYMBOL_GPL(__sata_phy_reset);
5659EXPORT_SYMBOL_GPL(ata_bus_reset);
8a19ac89 5660EXPORT_SYMBOL_GPL(ata_std_probeinit);
c2bd5804
TH		 5661EXPORT_SYMBOL_GPL(ata_std_softreset);
5662EXPORT_SYMBOL_GPL(sata_std_hardreset);
5663EXPORT_SYMBOL_GPL(ata_std_postreset);
5664EXPORT_SYMBOL_GPL(ata_std_probe_reset);
a62c0fc5 5665EXPORT_SYMBOL_GPL(ata_drive_probe_reset);
623a3128 5666EXPORT_SYMBOL_GPL(ata_dev_revalidate);
2e9edbf8
JG		 5667EXPORT_SYMBOL_GPL(ata_dev_classify);
5668EXPORT_SYMBOL_GPL(ata_dev_pair);
1da177e4 5669EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 5670EXPORT_SYMBOL_GPL(ata_ratelimit);
c22daff4 5671EXPORT_SYMBOL_GPL(ata_wait_register);
6f8b9958 5672EXPORT_SYMBOL_GPL(ata_busy_sleep);
86e45b6b 5673EXPORT_SYMBOL_GPL(ata_port_queue_task);
1da177e4
LT		 5674EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
5675EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
1da177e4
LT		 5676EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
5677EXPORT_SYMBOL_GPL(ata_scsi_release);
5678EXPORT_SYMBOL_GPL(ata_host_intr);
34bf2170
TH		 5679EXPORT_SYMBOL_GPL(sata_scr_valid);
5680EXPORT_SYMBOL_GPL(sata_scr_read);
5681EXPORT_SYMBOL_GPL(sata_scr_write);
5682EXPORT_SYMBOL_GPL(sata_scr_write_flush);
5683EXPORT_SYMBOL_GPL(ata_port_online);
5684EXPORT_SYMBOL_GPL(ata_port_offline);
6a62a04d
TH		 5685EXPORT_SYMBOL_GPL(ata_id_string);
5686EXPORT_SYMBOL_GPL(ata_id_c_string);
1da177e4
LT		 5687EXPORT_SYMBOL_GPL(ata_scsi_simulate);
5688
1bc4ccff 5689EXPORT_SYMBOL_GPL(ata_pio_need_iordy);
452503f9
AC		 5690EXPORT_SYMBOL_GPL(ata_timing_compute);
5691EXPORT_SYMBOL_GPL(ata_timing_merge);
5692
1da177e4
LT		 5693#ifdef CONFIG_PCI
5694EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 5695EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT		 5696EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
5697EXPORT_SYMBOL_GPL(ata_pci_init_one);
5698EXPORT_SYMBOL_GPL(ata_pci_remove_one);
9b847548
JA		 5699EXPORT_SYMBOL_GPL(ata_pci_device_suspend);
5700EXPORT_SYMBOL_GPL(ata_pci_device_resume);
67951ade
AC		 5701EXPORT_SYMBOL_GPL(ata_pci_default_filter);
5702EXPORT_SYMBOL_GPL(ata_pci_clear_simplex);
1da177e4 5703#endif /* CONFIG_PCI */
9b847548
JA		 5704
5705EXPORT_SYMBOL_GPL(ata_device_suspend);
5706EXPORT_SYMBOL_GPL(ata_device_resume);
5707EXPORT_SYMBOL_GPL(ata_scsi_device_suspend);
5708EXPORT_SYMBOL_GPL(ata_scsi_device_resume);
ece1d636 5709
ece1d636 5710EXPORT_SYMBOL_GPL(ata_eng_timeout);
7b70fc03
TH		 5711EXPORT_SYMBOL_GPL(ata_port_schedule_eh);
5712EXPORT_SYMBOL_GPL(ata_port_abort);
e3180499
TH		 5713EXPORT_SYMBOL_GPL(ata_port_freeze);
5714EXPORT_SYMBOL_GPL(ata_eh_freeze_port);
5715EXPORT_SYMBOL_GPL(ata_eh_thaw_port);
ece1d636
TH		 5716EXPORT_SYMBOL_GPL(ata_eh_qc_complete);
5717EXPORT_SYMBOL_GPL(ata_eh_qc_retry);
022bdb07 5718EXPORT_SYMBOL_GPL(ata_do_eh);
Linux kernel - Deliverables
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