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[SCSI] lpfc 8.2.2 : Style cleanups
[deliverable/linux.git] / drivers / scsi / lpfc / lpfc_hw.h
CommitLineData
dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
9413afff 4 * Copyright (C) 2004-2007 Emulex. All rights reserved. *
c44ce173 5 * EMULEX and SLI are trademarks of Emulex. *
dea3101e 6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC		 9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
dea3101e 19 *******************************************************************/
20
dea3101e 21#define FDMI_DID 0xfffffaU
22#define NameServer_DID 0xfffffcU
23#define SCR_DID 0xfffffdU
24#define Fabric_DID 0xfffffeU
25#define Bcast_DID 0xffffffU
26#define Mask_DID 0xffffffU
27#define CT_DID_MASK 0xffff00U
28#define Fabric_DID_MASK 0xfff000U
29#define WELL_KNOWN_DID_MASK 0xfffff0U
30
31#define PT2PT_LocalID 1
32#define PT2PT_RemoteID 2
33
34#define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35#define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36#define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */
37#define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
38
39#define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
40 0 */
41
42#define FCELSSIZE 1024 /* maximum ELS transfer size */
43
44#define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
a4bc3379 45#define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
dea3101e 46#define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47#define LPFC_FCP_NEXT_RING 3
48
49#define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
50#define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
a4bc3379
JS		 51#define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
52#define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
dea3101e 53#define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
54#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
55#define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
56#define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
57#define SLI2_IOCB_CMD_R3_ENTRIES 0
58#define SLI2_IOCB_RSP_R3_ENTRIES 0
59#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
61
ed957684
JS		 62#define SLI2_IOCB_CMD_SIZE 32
63#define SLI2_IOCB_RSP_SIZE 32
64#define SLI3_IOCB_CMD_SIZE 128
65#define SLI3_IOCB_RSP_SIZE 64
66
92d7f7b0 67
dea3101e 68/* Common Transport structures and definitions */
69
70union CtRevisionId {
71 /* Structure is in Big Endian format */
72 struct {
73 uint32_t Revision:8;
74 uint32_t InId:24;
75 } bits;
76 uint32_t word;
77};
78
79union CtCommandResponse {
80 /* Structure is in Big Endian format */
81 struct {
82 uint32_t CmdRsp:16;
83 uint32_t Size:16;
84 } bits;
85 uint32_t word;
86};
87
92d7f7b0
JS		 88#define FC4_FEATURE_INIT 0x2
89#define FC4_FEATURE_TARGET 0x1
90
dea3101e 91struct lpfc_sli_ct_request {
92 /* Structure is in Big Endian format */
93 union CtRevisionId RevisionId;
94 uint8_t FsType;
95 uint8_t FsSubType;
96 uint8_t Options;
97 uint8_t Rsrvd1;
98 union CtCommandResponse CommandResponse;
99 uint8_t Rsrvd2;
100 uint8_t ReasonCode;
101 uint8_t Explanation;
102 uint8_t VendorUnique;
103
104 union {
105 uint32_t PortID;
106 struct gid {
107 uint8_t PortType; /* for GID_PT requests */
108 uint8_t DomainScope;
109 uint8_t AreaScope;
110 uint8_t Fc4Type; /* for GID_FT requests */
111 } gid;
112 struct rft {
113 uint32_t PortId; /* For RFT_ID requests */
114
115#ifdef __BIG_ENDIAN_BITFIELD
116 uint32_t rsvd0:16;
117 uint32_t rsvd1:7;
118 uint32_t fcpReg:1; /* Type 8 */
119 uint32_t rsvd2:2;
120 uint32_t ipReg:1; /* Type 5 */
121 uint32_t rsvd3:5;
122#else /* __LITTLE_ENDIAN_BITFIELD */
123 uint32_t rsvd0:16;
124 uint32_t fcpReg:1; /* Type 8 */
125 uint32_t rsvd1:7;
126 uint32_t rsvd3:5;
127 uint32_t ipReg:1; /* Type 5 */
128 uint32_t rsvd2:2;
129#endif
130
131 uint32_t rsvd[7];
132 } rft;
133 struct rnn {
134 uint32_t PortId; /* For RNN_ID requests */
135 uint8_t wwnn[8];
136 } rnn;
137 struct rsnn { /* For RSNN_ID requests */
138 uint8_t wwnn[8];
139 uint8_t len;
140 uint8_t symbname[255];
141 } rsnn;
92d7f7b0
JS		 142 struct rspn { /* For RSPN_ID requests */
143 uint32_t PortId;
144 uint8_t len;
145 uint8_t symbname[255];
146 } rspn;
147 struct gff {
148 uint32_t PortId;
149 } gff;
150 struct gff_acc {
151 uint8_t fbits[128];
152 } gff_acc;
51ef4c26
JS		 153#ifdef __BIG_ENDIAN_BITFIELD
154#define FCP_TYPE_FEATURE_OFFSET 7
155#else /* __LITTLE_ENDIAN_BITFIELD */
92d7f7b0 156#define FCP_TYPE_FEATURE_OFFSET 4
51ef4c26 157#endif
92d7f7b0
JS		 158 struct rff {
159 uint32_t PortId;
160 uint8_t reserved[2];
161 uint8_t fbits;
162 uint8_t type_code; /* type=8 for FCP */
163 } rff;
dea3101e 164 } un;
165};
166
167#define SLI_CT_REVISION 1
92d7f7b0
JS		 168#define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
169 sizeof(struct gid))
170#define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
171 sizeof(struct gff))
172#define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
173 sizeof(struct rft))
174#define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
175 sizeof(struct rff))
176#define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
177 sizeof(struct rnn))
178#define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
179 sizeof(struct rsnn))
180#define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
181 sizeof(struct rspn))
dea3101e 182
183/*
184 * FsType Definitions
185 */
186
187#define SLI_CT_MANAGEMENT_SERVICE 0xFA
188#define SLI_CT_TIME_SERVICE 0xFB
189#define SLI_CT_DIRECTORY_SERVICE 0xFC
190#define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
191
192/*
193 * Directory Service Subtypes
194 */
195
196#define SLI_CT_DIRECTORY_NAME_SERVER 0x02
197
198/*
199 * Response Codes
200 */
201
202#define SLI_CT_RESPONSE_FS_RJT 0x8001
203#define SLI_CT_RESPONSE_FS_ACC 0x8002
204
205/*
206 * Reason Codes
207 */
208
209#define SLI_CT_NO_ADDITIONAL_EXPL 0x0
210#define SLI_CT_INVALID_COMMAND 0x01
211#define SLI_CT_INVALID_VERSION 0x02
212#define SLI_CT_LOGICAL_ERROR 0x03
213#define SLI_CT_INVALID_IU_SIZE 0x04
214#define SLI_CT_LOGICAL_BUSY 0x05
215#define SLI_CT_PROTOCOL_ERROR 0x07
216#define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
217#define SLI_CT_REQ_NOT_SUPPORTED 0x0b
218#define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
219#define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
220#define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
221#define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
222#define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
223#define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
224#define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
225#define SLI_CT_VENDOR_UNIQUE 0xff
226
227/*
228 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
229 */
230
231#define SLI_CT_NO_PORT_ID 0x01
232#define SLI_CT_NO_PORT_NAME 0x02
233#define SLI_CT_NO_NODE_NAME 0x03
234#define SLI_CT_NO_CLASS_OF_SERVICE 0x04
235#define SLI_CT_NO_IP_ADDRESS 0x05
236#define SLI_CT_NO_IPA 0x06
237#define SLI_CT_NO_FC4_TYPES 0x07
238#define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
239#define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
240#define SLI_CT_NO_PORT_TYPE 0x0A
241#define SLI_CT_ACCESS_DENIED 0x10
242#define SLI_CT_INVALID_PORT_ID 0x11
243#define SLI_CT_DATABASE_EMPTY 0x12
244
245/*
246 * Name Server Command Codes
247 */
248
249#define SLI_CTNS_GA_NXT 0x0100
250#define SLI_CTNS_GPN_ID 0x0112
251#define SLI_CTNS_GNN_ID 0x0113
252#define SLI_CTNS_GCS_ID 0x0114
253#define SLI_CTNS_GFT_ID 0x0117
254#define SLI_CTNS_GSPN_ID 0x0118
255#define SLI_CTNS_GPT_ID 0x011A
92d7f7b0 256#define SLI_CTNS_GFF_ID 0x011F
dea3101e 257#define SLI_CTNS_GID_PN 0x0121
258#define SLI_CTNS_GID_NN 0x0131
259#define SLI_CTNS_GIP_NN 0x0135
260#define SLI_CTNS_GIPA_NN 0x0136
261#define SLI_CTNS_GSNN_NN 0x0139
262#define SLI_CTNS_GNN_IP 0x0153
263#define SLI_CTNS_GIPA_IP 0x0156
264#define SLI_CTNS_GID_FT 0x0171
265#define SLI_CTNS_GID_PT 0x01A1
266#define SLI_CTNS_RPN_ID 0x0212
267#define SLI_CTNS_RNN_ID 0x0213
268#define SLI_CTNS_RCS_ID 0x0214
269#define SLI_CTNS_RFT_ID 0x0217
270#define SLI_CTNS_RSPN_ID 0x0218
271#define SLI_CTNS_RPT_ID 0x021A
92d7f7b0 272#define SLI_CTNS_RFF_ID 0x021F
dea3101e 273#define SLI_CTNS_RIP_NN 0x0235
274#define SLI_CTNS_RIPA_NN 0x0236
275#define SLI_CTNS_RSNN_NN 0x0239
276#define SLI_CTNS_DA_ID 0x0300
277
278/*
279 * Port Types
280 */
281
282#define SLI_CTPT_N_PORT 0x01
283#define SLI_CTPT_NL_PORT 0x02
284#define SLI_CTPT_FNL_PORT 0x03
285#define SLI_CTPT_IP 0x04
286#define SLI_CTPT_FCP 0x08
287#define SLI_CTPT_NX_PORT 0x7F
288#define SLI_CTPT_F_PORT 0x81
289#define SLI_CTPT_FL_PORT 0x82
290#define SLI_CTPT_E_PORT 0x84
291
292#define SLI_CT_LAST_ENTRY 0x80000000
293
294/* Fibre Channel Service Parameter definitions */
295
296#define FC_PH_4_0 6 /* FC-PH version 4.0 */
297#define FC_PH_4_1 7 /* FC-PH version 4.1 */
298#define FC_PH_4_2 8 /* FC-PH version 4.2 */
299#define FC_PH_4_3 9 /* FC-PH version 4.3 */
300
301#define FC_PH_LOW 8 /* Lowest supported FC-PH version */
302#define FC_PH_HIGH 9 /* Highest supported FC-PH version */
303#define FC_PH3 0x20 /* FC-PH-3 version */
304
305#define FF_FRAME_SIZE 2048
306
307struct lpfc_name {
f631b4be
AV		 308 union {
309 struct {
dea3101e 310#ifdef __BIG_ENDIAN_BITFIELD
f631b4be 311 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
1de933f3
JSEC		 312 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
313 8:11 of IEEE ext */
dea3101e 314#else /* __LITTLE_ENDIAN_BITFIELD */
1de933f3
JSEC		 315 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
316 8:11 of IEEE ext */
f631b4be 317 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
dea3101e 318#endif
319
320#define NAME_IEEE 0x1 /* IEEE name - nameType */
321#define NAME_IEEE_EXT 0x2 /* IEEE extended name */
322#define NAME_FC_TYPE 0x3 /* FC native name type */
323#define NAME_IP_TYPE 0x4 /* IP address */
324#define NAME_CCITT_TYPE 0xC
325#define NAME_CCITT_GR_TYPE 0xE
1de933f3
JSEC		 326 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
327 extended Lsb */
f631b4be 328 uint8_t IEEE[6]; /* FC IEEE address */
68ce1eb5 329 } s;
f631b4be 330 uint8_t wwn[8];
68ce1eb5 331 } u;
dea3101e 332};
333
334struct csp {
335 uint8_t fcphHigh; /* FC Word 0, byte 0 */
336 uint8_t fcphLow;
337 uint8_t bbCreditMsb;
338 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
339
340#ifdef __BIG_ENDIAN_BITFIELD
92d7f7b0
JS		 341 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
342 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
343 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
dea3101e 344 uint16_t fPort:1; /* FC Word 1, bit 28 */
345 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
346 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
347 uint16_t multicast:1; /* FC Word 1, bit 25 */
348 uint16_t broadcast:1; /* FC Word 1, bit 24 */
349
350 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
351 uint16_t simplex:1; /* FC Word 1, bit 22 */
352 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
353 uint16_t dhd:1; /* FC Word 1, bit 18 */
354 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
355 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
356#else /* __LITTLE_ENDIAN_BITFIELD */
357 uint16_t broadcast:1; /* FC Word 1, bit 24 */
358 uint16_t multicast:1; /* FC Word 1, bit 25 */
359 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
360 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
361 uint16_t fPort:1; /* FC Word 1, bit 28 */
92d7f7b0 362 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
dea3101e 363 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
92d7f7b0 364 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
dea3101e 365
366 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
367 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
368 uint16_t dhd:1; /* FC Word 1, bit 18 */
369 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
370 uint16_t simplex:1; /* FC Word 1, bit 22 */
371 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
372#endif
373
374 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
375 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
376 union {
377 struct {
378 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
379
380 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
381 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
382
383 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
384 } nPort;
385 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
386 } w2;
387
388 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
389};
390
391struct class_parms {
392#ifdef __BIG_ENDIAN_BITFIELD
393 uint8_t classValid:1; /* FC Word 0, bit 31 */
394 uint8_t intermix:1; /* FC Word 0, bit 30 */
395 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
396 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
397 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
398 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
399#else /* __LITTLE_ENDIAN_BITFIELD */
400 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
401 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
402 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
403 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
404 uint8_t intermix:1; /* FC Word 0, bit 30 */
405 uint8_t classValid:1; /* FC Word 0, bit 31 */
406
407#endif
408
409 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
410
411#ifdef __BIG_ENDIAN_BITFIELD
412 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
413 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
414 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
415 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
416 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
417#else /* __LITTLE_ENDIAN_BITFIELD */
418 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
419 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
420 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
421 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
422 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
423#endif
424
425 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
426
427#ifdef __BIG_ENDIAN_BITFIELD
428 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
429 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
430 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
431 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
432 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
433 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
434#else /* __LITTLE_ENDIAN_BITFIELD */
435 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
436 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
437 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
438 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
439 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
440 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
441#endif
442
443 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
444 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
445 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
446
447 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
448 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
449 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
450 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
451
452 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
453 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
454 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
455 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
456};
457
458struct serv_parm { /* Structure is in Big Endian format */
459 struct csp cmn;
460 struct lpfc_name portName;
461 struct lpfc_name nodeName;
462 struct class_parms cls1;
463 struct class_parms cls2;
464 struct class_parms cls3;
465 struct class_parms cls4;
466 uint8_t vendorVersion[16];
467};
468
469/*
470 * Extended Link Service LS_COMMAND codes (Payload Word 0)
471 */
472#ifdef __BIG_ENDIAN_BITFIELD
473#define ELS_CMD_MASK 0xffff0000
474#define ELS_RSP_MASK 0xff000000
475#define ELS_CMD_LS_RJT 0x01000000
476#define ELS_CMD_ACC 0x02000000
477#define ELS_CMD_PLOGI 0x03000000
478#define ELS_CMD_FLOGI 0x04000000
479#define ELS_CMD_LOGO 0x05000000
480#define ELS_CMD_ABTX 0x06000000
481#define ELS_CMD_RCS 0x07000000
482#define ELS_CMD_RES 0x08000000
483#define ELS_CMD_RSS 0x09000000
484#define ELS_CMD_RSI 0x0A000000
485#define ELS_CMD_ESTS 0x0B000000
486#define ELS_CMD_ESTC 0x0C000000
487#define ELS_CMD_ADVC 0x0D000000
488#define ELS_CMD_RTV 0x0E000000
489#define ELS_CMD_RLS 0x0F000000
490#define ELS_CMD_ECHO 0x10000000
491#define ELS_CMD_TEST 0x11000000
492#define ELS_CMD_RRQ 0x12000000
493#define ELS_CMD_PRLI 0x20100014
494#define ELS_CMD_PRLO 0x21100014
82d9a2a2 495#define ELS_CMD_PRLO_ACC 0x02100014
dea3101e 496#define ELS_CMD_PDISC 0x50000000
497#define ELS_CMD_FDISC 0x51000000
498#define ELS_CMD_ADISC 0x52000000
499#define ELS_CMD_FARP 0x54000000
500#define ELS_CMD_FARPR 0x55000000
7bb3b137
JW		 501#define ELS_CMD_RPS 0x56000000
502#define ELS_CMD_RPL 0x57000000
dea3101e 503#define ELS_CMD_FAN 0x60000000
504#define ELS_CMD_RSCN 0x61040000
505#define ELS_CMD_SCR 0x62000000
506#define ELS_CMD_RNID 0x78000000
7bb3b137 507#define ELS_CMD_LIRR 0x7A000000
dea3101e 508#else /* __LITTLE_ENDIAN_BITFIELD */
509#define ELS_CMD_MASK 0xffff
510#define ELS_RSP_MASK 0xff
511#define ELS_CMD_LS_RJT 0x01
512#define ELS_CMD_ACC 0x02
513#define ELS_CMD_PLOGI 0x03
514#define ELS_CMD_FLOGI 0x04
515#define ELS_CMD_LOGO 0x05
516#define ELS_CMD_ABTX 0x06
517#define ELS_CMD_RCS 0x07
518#define ELS_CMD_RES 0x08
519#define ELS_CMD_RSS 0x09
520#define ELS_CMD_RSI 0x0A
521#define ELS_CMD_ESTS 0x0B
522#define ELS_CMD_ESTC 0x0C
523#define ELS_CMD_ADVC 0x0D
524#define ELS_CMD_RTV 0x0E
525#define ELS_CMD_RLS 0x0F
526#define ELS_CMD_ECHO 0x10
527#define ELS_CMD_TEST 0x11
528#define ELS_CMD_RRQ 0x12
529#define ELS_CMD_PRLI 0x14001020
530#define ELS_CMD_PRLO 0x14001021
82d9a2a2 531#define ELS_CMD_PRLO_ACC 0x14001002
dea3101e 532#define ELS_CMD_PDISC 0x50
533#define ELS_CMD_FDISC 0x51
534#define ELS_CMD_ADISC 0x52
535#define ELS_CMD_FARP 0x54
536#define ELS_CMD_FARPR 0x55
7bb3b137
JW		 537#define ELS_CMD_RPS 0x56
538#define ELS_CMD_RPL 0x57
dea3101e 539#define ELS_CMD_FAN 0x60
540#define ELS_CMD_RSCN 0x0461
541#define ELS_CMD_SCR 0x62
542#define ELS_CMD_RNID 0x78
7bb3b137 543#define ELS_CMD_LIRR 0x7A
dea3101e 544#endif
545
546/*
547 * LS_RJT Payload Definition
548 */
549
550struct ls_rjt { /* Structure is in Big Endian format */
551 union {
552 uint32_t lsRjtError;
553 struct {
554 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
555
556 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
557 /* LS_RJT reason codes */
558#define LSRJT_INVALID_CMD 0x01
559#define LSRJT_LOGICAL_ERR 0x03
560#define LSRJT_LOGICAL_BSY 0x05
561#define LSRJT_PROTOCOL_ERR 0x07
562#define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
563#define LSRJT_CMD_UNSUPPORTED 0x0B
564#define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
565
566 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
567 /* LS_RJT reason explanation */
568#define LSEXP_NOTHING_MORE 0x00
569#define LSEXP_SPARM_OPTIONS 0x01
570#define LSEXP_SPARM_ICTL 0x03
571#define LSEXP_SPARM_RCTL 0x05
572#define LSEXP_SPARM_RCV_SIZE 0x07
573#define LSEXP_SPARM_CONCUR_SEQ 0x09
574#define LSEXP_SPARM_CREDIT 0x0B
575#define LSEXP_INVALID_PNAME 0x0D
576#define LSEXP_INVALID_NNAME 0x0E
577#define LSEXP_INVALID_CSP 0x0F
578#define LSEXP_INVALID_ASSOC_HDR 0x11
579#define LSEXP_ASSOC_HDR_REQ 0x13
580#define LSEXP_INVALID_O_SID 0x15
581#define LSEXP_INVALID_OX_RX 0x17
582#define LSEXP_CMD_IN_PROGRESS 0x19
583#define LSEXP_INVALID_NPORT_ID 0x1F
584#define LSEXP_INVALID_SEQ_ID 0x21
585#define LSEXP_INVALID_XCHG 0x23
586#define LSEXP_INACTIVE_XCHG 0x25
587#define LSEXP_RQ_REQUIRED 0x27
588#define LSEXP_OUT_OF_RESOURCE 0x29
589#define LSEXP_CANT_GIVE_DATA 0x2A
590#define LSEXP_REQ_UNSUPPORTED 0x2C
591 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
592 } b;
593 } un;
594};
595
596/*
597 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
598 */
599
600typedef struct _LOGO { /* Structure is in Big Endian format */
601 union {
602 uint32_t nPortId32; /* Access nPortId as a word */
603 struct {
604 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
605 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
606 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
607 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
608 } b;
609 } un;
610 struct lpfc_name portName; /* N_port name field */
611} LOGO;
612
613/*
614 * FCP Login (PRLI Request / ACC) Payload Definition
615 */
616
617#define PRLX_PAGE_LEN 0x10
618#define TPRLO_PAGE_LEN 0x14
619
620typedef struct _PRLI { /* Structure is in Big Endian format */
621 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
622
623#define PRLI_FCP_TYPE 0x08
624 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
625
626#ifdef __BIG_ENDIAN_BITFIELD
627 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
628 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
629 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
630
631 /* ACC = imagePairEstablished */
632 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
633 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
634#else /* __LITTLE_ENDIAN_BITFIELD */
635 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
636 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
637 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
638 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
639 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
640 /* ACC = imagePairEstablished */
641#endif
642
643#define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
644#define PRLI_NO_RESOURCES 0x2
645#define PRLI_INIT_INCOMPLETE 0x3
646#define PRLI_NO_SUCH_PA 0x4
647#define PRLI_PREDEF_CONFIG 0x5
648#define PRLI_PARTIAL_SUCCESS 0x6
649#define PRLI_INVALID_PAGE_CNT 0x7
650 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
651
652 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
653
654 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
655
656 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
657 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
658
659#ifdef __BIG_ENDIAN_BITFIELD
660 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
661 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
662 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
663 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
664 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
665 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
666 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
667 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
668 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
669 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
670 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
671 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
672 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
673 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
674 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
675 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
676#else /* __LITTLE_ENDIAN_BITFIELD */
677 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
678 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
679 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
680 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
681 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
682 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
683 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
684 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
685 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
686 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
687 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
688 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
689 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
690 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
691 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
692 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
693#endif
694} PRLI;
695
696/*
697 * FCP Logout (PRLO Request / ACC) Payload Definition
698 */
699
700typedef struct _PRLO { /* Structure is in Big Endian format */
701 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
702
703#define PRLO_FCP_TYPE 0x08
704 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
705
706#ifdef __BIG_ENDIAN_BITFIELD
707 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
708 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
709 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
710 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
711#else /* __LITTLE_ENDIAN_BITFIELD */
712 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
713 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
714 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
715 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
716#endif
717
718#define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
719#define PRLO_NO_SUCH_IMAGE 0x4
720#define PRLO_INVALID_PAGE_CNT 0x7
721
722 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
723
724 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
725
726 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
727
728 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
729} PRLO;
730
731typedef struct _ADISC { /* Structure is in Big Endian format */
732 uint32_t hardAL_PA;
733 struct lpfc_name portName;
734 struct lpfc_name nodeName;
735 uint32_t DID;
736} ADISC;
737
738typedef struct _FARP { /* Structure is in Big Endian format */
739 uint32_t Mflags:8;
740 uint32_t Odid:24;
741#define FARP_NO_ACTION 0 /* FARP information enclosed, no
742 action */
743#define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
744#define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
745#define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
746#define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
747 supported */
748#define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
749 supported */
750 uint32_t Rflags:8;
751 uint32_t Rdid:24;
752#define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
753#define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
754 struct lpfc_name OportName;
755 struct lpfc_name OnodeName;
756 struct lpfc_name RportName;
757 struct lpfc_name RnodeName;
758 uint8_t Oipaddr[16];
759 uint8_t Ripaddr[16];
760} FARP;
761
762typedef struct _FAN { /* Structure is in Big Endian format */
763 uint32_t Fdid;
764 struct lpfc_name FportName;
765 struct lpfc_name FnodeName;
766} FAN;
767
768typedef struct _SCR { /* Structure is in Big Endian format */
769 uint8_t resvd1;
770 uint8_t resvd2;
771 uint8_t resvd3;
772 uint8_t Function;
773#define SCR_FUNC_FABRIC 0x01
774#define SCR_FUNC_NPORT 0x02
775#define SCR_FUNC_FULL 0x03
776#define SCR_CLEAR 0xff
777} SCR;
778
779typedef struct _RNID_TOP_DISC {
780 struct lpfc_name portName;
781 uint8_t resvd[8];
782 uint32_t unitType;
783#define RNID_HBA 0x7
784#define RNID_HOST 0xa
785#define RNID_DRIVER 0xd
786 uint32_t physPort;
787 uint32_t attachedNodes;
788 uint16_t ipVersion;
789#define RNID_IPV4 0x1
790#define RNID_IPV6 0x2
791 uint16_t UDPport;
792 uint8_t ipAddr[16];
793 uint16_t resvd1;
794 uint16_t flags;
795#define RNID_TD_SUPPORT 0x1
796#define RNID_LP_VALID 0x2
797} RNID_TOP_DISC;
798
799typedef struct _RNID { /* Structure is in Big Endian format */
800 uint8_t Format;
801#define RNID_TOPOLOGY_DISC 0xdf
802 uint8_t CommonLen;
803 uint8_t resvd1;
804 uint8_t SpecificLen;
805 struct lpfc_name portName;
806 struct lpfc_name nodeName;
807 union {
808 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
809 } un;
810} RNID;
811
311464ec 812typedef struct _RPS { /* Structure is in Big Endian format */
7bb3b137
JW		 813 union {
814 uint32_t portNum;
815 struct lpfc_name portName;
816 } un;
817} RPS;
818
819typedef struct _RPS_RSP { /* Structure is in Big Endian format */
820 uint16_t rsvd1;
821 uint16_t portStatus;
822 uint32_t linkFailureCnt;
823 uint32_t lossSyncCnt;
824 uint32_t lossSignalCnt;
825 uint32_t primSeqErrCnt;
826 uint32_t invalidXmitWord;
827 uint32_t crcCnt;
828} RPS_RSP;
829
311464ec 830typedef struct _RPL { /* Structure is in Big Endian format */
7bb3b137
JW		 831 uint32_t maxsize;
832 uint32_t index;
833} RPL;
834
835typedef struct _PORT_NUM_BLK {
836 uint32_t portNum;
837 uint32_t portID;
838 struct lpfc_name portName;
839} PORT_NUM_BLK;
840
311464ec 841typedef struct _RPL_RSP { /* Structure is in Big Endian format */
7bb3b137
JW		 842 uint32_t listLen;
843 uint32_t index;
844 PORT_NUM_BLK port_num_blk;
845} RPL_RSP;
dea3101e 846
847/* This is used for RSCN command */
848typedef struct _D_ID { /* Structure is in Big Endian format */
849 union {
850 uint32_t word;
851 struct {
852#ifdef __BIG_ENDIAN_BITFIELD
853 uint8_t resv;
854 uint8_t domain;
855 uint8_t area;
856 uint8_t id;
857#else /* __LITTLE_ENDIAN_BITFIELD */
858 uint8_t id;
859 uint8_t area;
860 uint8_t domain;
861 uint8_t resv;
862#endif
863 } b;
864 } un;
865} D_ID;
866
867/*
868 * Structure to define all ELS Payload types
869 */
870
871typedef struct _ELS_PKT { /* Structure is in Big Endian format */
872 uint8_t elsCode; /* FC Word 0, bit 24:31 */
873 uint8_t elsByte1;
874 uint8_t elsByte2;
875 uint8_t elsByte3;
876 union {
877 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
878 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
879 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
880 PRLI prli; /* Payload for PRLI/ACC */
881 PRLO prlo; /* Payload for PRLO/ACC */
882 ADISC adisc; /* Payload for ADISC/ACC */
883 FARP farp; /* Payload for FARP/ACC */
884 FAN fan; /* Payload for FAN */
885 SCR scr; /* Payload for SCR/ACC */
dea3101e 886 RNID rnid; /* Payload for RNID */
887 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
888 } un;
889} ELS_PKT;
890
891/*
892 * FDMI
893 * HBA MAnagement Operations Command Codes
894 */
895#define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
896#define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
897#define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
898#define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
899#define SLI_MGMT_RHBA 0x200 /* Register HBA */
900#define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */
901#define SLI_MGMT_RPRT 0x210 /* Register Port */
902#define SLI_MGMT_RPA 0x211 /* Register Port attributes */
903#define SLI_MGMT_DHBA 0x300 /* De-register HBA */
904#define SLI_MGMT_DPRT 0x310 /* De-register Port */
905
906/*
907 * Management Service Subtypes
908 */
909#define SLI_CT_FDMI_Subtypes 0x10
910
911/*
912 * HBA Management Service Reject Code
913 */
914#define REJECT_CODE 0x9 /* Unable to perform command request */
915
916/*
917 * HBA Management Service Reject Reason Code
918 * Please refer to the Reason Codes above
919 */
920
921/*
922 * HBA Attribute Types
923 */
924#define NODE_NAME 0x1
925#define MANUFACTURER 0x2
926#define SERIAL_NUMBER 0x3
927#define MODEL 0x4
928#define MODEL_DESCRIPTION 0x5
929#define HARDWARE_VERSION 0x6
930#define DRIVER_VERSION 0x7
931#define OPTION_ROM_VERSION 0x8
932#define FIRMWARE_VERSION 0x9
933#define OS_NAME_VERSION 0xa
934#define MAX_CT_PAYLOAD_LEN 0xb
935
936/*
937 * Port Attrubute Types
938 */
939#define SUPPORTED_FC4_TYPES 0x1
940#define SUPPORTED_SPEED 0x2
941#define PORT_SPEED 0x3
942#define MAX_FRAME_SIZE 0x4
943#define OS_DEVICE_NAME 0x5
944#define HOST_NAME 0x6
945
946union AttributesDef {
947 /* Structure is in Big Endian format */
948 struct {
949 uint32_t AttrType:16;
950 uint32_t AttrLen:16;
951 } bits;
952 uint32_t word;
953};
954
955
956/*
957 * HBA Attribute Entry (8 - 260 bytes)
958 */
959typedef struct {
960 union AttributesDef ad;
961 union {
962 uint32_t VendorSpecific;
963 uint8_t Manufacturer[64];
964 uint8_t SerialNumber[64];
965 uint8_t Model[256];
966 uint8_t ModelDescription[256];
967 uint8_t HardwareVersion[256];
968 uint8_t DriverVersion[256];
969 uint8_t OptionROMVersion[256];
970 uint8_t FirmwareVersion[256];
971 struct lpfc_name NodeName;
972 uint8_t SupportFC4Types[32];
973 uint32_t SupportSpeed;
974 uint32_t PortSpeed;
975 uint32_t MaxFrameSize;
976 uint8_t OsDeviceName[256];
977 uint8_t OsNameVersion[256];
978 uint32_t MaxCTPayloadLen;
979 uint8_t HostName[256];
980 } un;
981} ATTRIBUTE_ENTRY;
982
983/*
984 * HBA Attribute Block
985 */
986typedef struct {
987 uint32_t EntryCnt; /* Number of HBA attribute entries */
988 ATTRIBUTE_ENTRY Entry; /* Variable-length array */
989} ATTRIBUTE_BLOCK;
990
991/*
992 * Port Entry
993 */
994typedef struct {
995 struct lpfc_name PortName;
996} PORT_ENTRY;
997
998/*
999 * HBA Identifier
1000 */
1001typedef struct {
1002 struct lpfc_name PortName;
1003} HBA_IDENTIFIER;
1004
1005/*
1006 * Registered Port List Format
1007 */
1008typedef struct {
1009 uint32_t EntryCnt;
1010 PORT_ENTRY pe; /* Variable-length array */
1011} REG_PORT_LIST;
1012
1013/*
1014 * Register HBA(RHBA)
1015 */
1016typedef struct {
1017 HBA_IDENTIFIER hi;
1018 REG_PORT_LIST rpl; /* variable-length array */
1019/* ATTRIBUTE_BLOCK ab; */
1020} REG_HBA;
1021
1022/*
1023 * Register HBA Attributes (RHAT)
1024 */
1025typedef struct {
1026 struct lpfc_name HBA_PortName;
1027 ATTRIBUTE_BLOCK ab;
1028} REG_HBA_ATTRIBUTE;
1029
1030/*
1031 * Register Port Attributes (RPA)
1032 */
1033typedef struct {
1034 struct lpfc_name PortName;
1035 ATTRIBUTE_BLOCK ab;
1036} REG_PORT_ATTRIBUTE;
1037
1038/*
1039 * Get Registered HBA List (GRHL) Accept Payload Format
1040 */
1041typedef struct {
1042 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1043 struct lpfc_name HBA_PortName; /* Variable-length array */
1044} GRHL_ACC_PAYLOAD;
1045
1046/*
1047 * Get Registered Port List (GRPL) Accept Payload Format
1048 */
1049typedef struct {
1050 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1051 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */
1052} GRPL_ACC_PAYLOAD;
1053
1054/*
1055 * Get Port Attributes (GPAT) Accept Payload Format
1056 */
1057
1058typedef struct {
1059 ATTRIBUTE_BLOCK pab;
1060} GPAT_ACC_PAYLOAD;
1061
1062
1063/*
1064 * Begin HBA configuration parameters.
1065 * The PCI configuration register BAR assignments are:
1066 * BAR0, offset 0x10 - SLIM base memory address
1067 * BAR1, offset 0x14 - SLIM base memory high address
1068 * BAR2, offset 0x18 - REGISTER base memory address
1069 * BAR3, offset 0x1c - REGISTER base memory high address
1070 * BAR4, offset 0x20 - BIU I/O registers
1071 * BAR5, offset 0x24 - REGISTER base io high address
1072 */
1073
1074/* Number of rings currently used and available. */
1075#define MAX_CONFIGURED_RINGS 3
1076#define MAX_RINGS 4
1077
1078/* IOCB / Mailbox is owned by FireFly */
1079#define OWN_CHIP 1
1080
1081/* IOCB / Mailbox is owned by Host */
1082#define OWN_HOST 0
1083
1084/* Number of 4-byte words in an IOCB. */
1085#define IOCB_WORD_SZ 8
1086
1087/* defines for type field in fc header */
1088#define FC_ELS_DATA 0x1
1089#define FC_LLC_SNAP 0x5
1090#define FC_FCP_DATA 0x8
1091#define FC_COMMON_TRANSPORT_ULP 0x20
1092
1093/* defines for rctl field in fc header */
1094#define FC_DEV_DATA 0x0
1095#define FC_UNSOL_CTL 0x2
1096#define FC_SOL_CTL 0x3
1097#define FC_UNSOL_DATA 0x4
1098#define FC_FCP_CMND 0x6
1099#define FC_ELS_REQ 0x22
1100#define FC_ELS_RSP 0x23
1101
1102/* network headers for Dfctl field */
1103#define FC_NET_HDR 0x20
1104
1105/* Start FireFly Register definitions */
1106#define PCI_VENDOR_ID_EMULEX 0x10df
1107#define PCI_DEVICE_ID_FIREFLY 0x1ae5
b87eab38
JS		 1108#define PCI_DEVICE_ID_SAT_SMB 0xf011
1109#define PCI_DEVICE_ID_SAT_MID 0xf015
dea3101e 1110#define PCI_DEVICE_ID_RFLY 0xf095
1111#define PCI_DEVICE_ID_PFLY 0xf098
e4adb204 1112#define PCI_DEVICE_ID_LP101 0xf0a1
dea3101e 1113#define PCI_DEVICE_ID_TFLY 0xf0a5
e4adb204
JSEC		 1114#define PCI_DEVICE_ID_BSMB 0xf0d1
1115#define PCI_DEVICE_ID_BMID 0xf0d5
1116#define PCI_DEVICE_ID_ZSMB 0xf0e1
1117#define PCI_DEVICE_ID_ZMID 0xf0e5
1118#define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1119#define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1120#define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
b87eab38
JS		 1121#define PCI_DEVICE_ID_SAT 0xf100
1122#define PCI_DEVICE_ID_SAT_SCSP 0xf111
1123#define PCI_DEVICE_ID_SAT_DCSP 0xf112
e4adb204
JSEC		 1124#define PCI_DEVICE_ID_SUPERFLY 0xf700
1125#define PCI_DEVICE_ID_DRAGONFLY 0xf800
dea3101e 1126#define PCI_DEVICE_ID_CENTAUR 0xf900
1127#define PCI_DEVICE_ID_PEGASUS 0xf980
1128#define PCI_DEVICE_ID_THOR 0xfa00
1129#define PCI_DEVICE_ID_VIPER 0xfb00
e4adb204
JSEC		 1130#define PCI_DEVICE_ID_LP10000S 0xfc00
1131#define PCI_DEVICE_ID_LP11000S 0xfc10
1132#define PCI_DEVICE_ID_LPE11000S 0xfc20
b87eab38 1133#define PCI_DEVICE_ID_SAT_S 0xfc40
dea3101e 1134#define PCI_DEVICE_ID_HELIOS 0xfd00
e4adb204
JSEC		 1135#define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1136#define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
dea3101e 1137#define PCI_DEVICE_ID_ZEPHYR 0xfe00
e4adb204
JSEC		 1138#define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1139#define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
dea3101e 1140
1141#define JEDEC_ID_ADDRESS 0x0080001c
1142#define FIREFLY_JEDEC_ID 0x1ACC
1143#define SUPERFLY_JEDEC_ID 0x0020
1144#define DRAGONFLY_JEDEC_ID 0x0021
1145#define DRAGONFLY_V2_JEDEC_ID 0x0025
1146#define CENTAUR_2G_JEDEC_ID 0x0026
1147#define CENTAUR_1G_JEDEC_ID 0x0028
1148#define PEGASUS_ORION_JEDEC_ID 0x0036
1149#define PEGASUS_JEDEC_ID 0x0038
1150#define THOR_JEDEC_ID 0x0012
1151#define HELIOS_JEDEC_ID 0x0364
1152#define ZEPHYR_JEDEC_ID 0x0577
1153#define VIPER_JEDEC_ID 0x4838
b87eab38 1154#define SATURN_JEDEC_ID 0x1004
dea3101e 1155
1156#define JEDEC_ID_MASK 0x0FFFF000
1157#define JEDEC_ID_SHIFT 12
1158#define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1159
1160typedef struct { /* FireFly BIU registers */
1161 uint32_t hostAtt; /* See definitions for Host Attention
1162 register */
1163 uint32_t chipAtt; /* See definitions for Chip Attention
1164 register */
1165 uint32_t hostStatus; /* See definitions for Host Status register */
1166 uint32_t hostControl; /* See definitions for Host Control register */
1167 uint32_t buiConfig; /* See definitions for BIU configuration
1168 register */
1169} FF_REGS;
1170
1171/* IO Register size in bytes */
1172#define FF_REG_AREA_SIZE 256
1173
1174/* Host Attention Register */
1175
1176#define HA_REG_OFFSET 0 /* Byte offset from register base address */
1177
1178#define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1179#define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1180#define HA_R0ATT 0x00000008 /* Bit 3 */
1181#define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1182#define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1183#define HA_R1ATT 0x00000080 /* Bit 7 */
1184#define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1185#define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1186#define HA_R2ATT 0x00000800 /* Bit 11 */
1187#define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1188#define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1189#define HA_R3ATT 0x00008000 /* Bit 15 */
1190#define HA_LATT 0x20000000 /* Bit 29 */
1191#define HA_MBATT 0x40000000 /* Bit 30 */
1192#define HA_ERATT 0x80000000 /* Bit 31 */
1193
1194#define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1195#define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1196#define HA_RXATT 0x00000008 /* Bit 3 */
1197#define HA_RXMASK 0x0000000f
1198
1199/* Chip Attention Register */
1200
1201#define CA_REG_OFFSET 4 /* Byte offset from register base address */
1202
1203#define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1204#define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1205#define CA_R0ATT 0x00000008 /* Bit 3 */
1206#define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1207#define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1208#define CA_R1ATT 0x00000080 /* Bit 7 */
1209#define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1210#define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1211#define CA_R2ATT 0x00000800 /* Bit 11 */
1212#define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1213#define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1214#define CA_R3ATT 0x00008000 /* Bit 15 */
1215#define CA_MBATT 0x40000000 /* Bit 30 */
1216
1217/* Host Status Register */
1218
1219#define HS_REG_OFFSET 8 /* Byte offset from register base address */
1220
1221#define HS_MBRDY 0x00400000 /* Bit 22 */
1222#define HS_FFRDY 0x00800000 /* Bit 23 */
1223#define HS_FFER8 0x01000000 /* Bit 24 */
1224#define HS_FFER7 0x02000000 /* Bit 25 */
1225#define HS_FFER6 0x04000000 /* Bit 26 */
1226#define HS_FFER5 0x08000000 /* Bit 27 */
1227#define HS_FFER4 0x10000000 /* Bit 28 */
1228#define HS_FFER3 0x20000000 /* Bit 29 */
1229#define HS_FFER2 0x40000000 /* Bit 30 */
1230#define HS_FFER1 0x80000000 /* Bit 31 */
1231#define HS_FFERM 0xFF000000 /* Mask for error bits 31:24 */
1232
1233/* Host Control Register */
1234
1235#define HC_REG_OFFSET 12 /* Word offset from register base address */
1236
1237#define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1238#define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1239#define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1240#define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1241#define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1242#define HC_INITHBI 0x02000000 /* Bit 25 */
1243#define HC_INITMB 0x04000000 /* Bit 26 */
1244#define HC_INITFF 0x08000000 /* Bit 27 */
1245#define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1246#define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1247
1248/* Mailbox Commands */
1249#define MBX_SHUTDOWN 0x00 /* terminate testing */
1250#define MBX_LOAD_SM 0x01
1251#define MBX_READ_NV 0x02
1252#define MBX_WRITE_NV 0x03
1253#define MBX_RUN_BIU_DIAG 0x04
1254#define MBX_INIT_LINK 0x05
1255#define MBX_DOWN_LINK 0x06
1256#define MBX_CONFIG_LINK 0x07
1257#define MBX_CONFIG_RING 0x09
1258#define MBX_RESET_RING 0x0A
1259#define MBX_READ_CONFIG 0x0B
1260#define MBX_READ_RCONFIG 0x0C
1261#define MBX_READ_SPARM 0x0D
1262#define MBX_READ_STATUS 0x0E
1263#define MBX_READ_RPI 0x0F
1264#define MBX_READ_XRI 0x10
1265#define MBX_READ_REV 0x11
1266#define MBX_READ_LNK_STAT 0x12
1267#define MBX_REG_LOGIN 0x13
1268#define MBX_UNREG_LOGIN 0x14
1269#define MBX_READ_LA 0x15
1270#define MBX_CLEAR_LA 0x16
1271#define MBX_DUMP_MEMORY 0x17
1272#define MBX_DUMP_CONTEXT 0x18
1273#define MBX_RUN_DIAGS 0x19
1274#define MBX_RESTART 0x1A
1275#define MBX_UPDATE_CFG 0x1B
1276#define MBX_DOWN_LOAD 0x1C
1277#define MBX_DEL_LD_ENTRY 0x1D
1278#define MBX_RUN_PROGRAM 0x1E
1279#define MBX_SET_MASK 0x20
1280#define MBX_SET_SLIM 0x21
1281#define MBX_UNREG_D_ID 0x23
41415862 1282#define MBX_KILL_BOARD 0x24
dea3101e 1283#define MBX_CONFIG_FARP 0x25
41415862 1284#define MBX_BEACON 0x2A
858c9f6c 1285#define MBX_HEARTBEAT 0x31
dea3101e 1286
ed957684 1287#define MBX_CONFIG_HBQ 0x7C
dea3101e 1288#define MBX_LOAD_AREA 0x81
1289#define MBX_RUN_BIU_DIAG64 0x84
1290#define MBX_CONFIG_PORT 0x88
1291#define MBX_READ_SPARM64 0x8D
1292#define MBX_READ_RPI64 0x8F
1293#define MBX_REG_LOGIN64 0x93
1294#define MBX_READ_LA64 0x95
92d7f7b0
JS		 1295#define MBX_REG_VPI 0x96
1296#define MBX_UNREG_VPI 0x97
1297#define MBX_REG_VNPID 0x96
1298#define MBX_UNREG_VNPID 0x97
dea3101e 1299
1300#define MBX_FLASH_WR_ULA 0x98
1301#define MBX_SET_DEBUG 0x99
1302#define MBX_LOAD_EXP_ROM 0x9C
1303
1304#define MBX_MAX_CMDS 0x9D
1305#define MBX_SLI2_CMD_MASK 0x80
1306
1307/* IOCB Commands */
1308
1309#define CMD_RCV_SEQUENCE_CX 0x01
1310#define CMD_XMIT_SEQUENCE_CR 0x02
1311#define CMD_XMIT_SEQUENCE_CX 0x03
1312#define CMD_XMIT_BCAST_CN 0x04
1313#define CMD_XMIT_BCAST_CX 0x05
1314#define CMD_QUE_RING_BUF_CN 0x06
1315#define CMD_QUE_XRI_BUF_CX 0x07
1316#define CMD_IOCB_CONTINUE_CN 0x08
1317#define CMD_RET_XRI_BUF_CX 0x09
1318#define CMD_ELS_REQUEST_CR 0x0A
1319#define CMD_ELS_REQUEST_CX 0x0B
1320#define CMD_RCV_ELS_REQ_CX 0x0D
1321#define CMD_ABORT_XRI_CN 0x0E
1322#define CMD_ABORT_XRI_CX 0x0F
1323#define CMD_CLOSE_XRI_CN 0x10
1324#define CMD_CLOSE_XRI_CX 0x11
1325#define CMD_CREATE_XRI_CR 0x12
1326#define CMD_CREATE_XRI_CX 0x13
1327#define CMD_GET_RPI_CN 0x14
1328#define CMD_XMIT_ELS_RSP_CX 0x15
1329#define CMD_GET_RPI_CR 0x16
1330#define CMD_XRI_ABORTED_CX 0x17
1331#define CMD_FCP_IWRITE_CR 0x18
1332#define CMD_FCP_IWRITE_CX 0x19
1333#define CMD_FCP_IREAD_CR 0x1A
1334#define CMD_FCP_IREAD_CX 0x1B
1335#define CMD_FCP_ICMND_CR 0x1C
1336#define CMD_FCP_ICMND_CX 0x1D
f5603511
JS		 1337#define CMD_FCP_TSEND_CX 0x1F
1338#define CMD_FCP_TRECEIVE_CX 0x21
1339#define CMD_FCP_TRSP_CX 0x23
1340#define CMD_FCP_AUTO_TRSP_CX 0x29
dea3101e 1341
1342#define CMD_ADAPTER_MSG 0x20
1343#define CMD_ADAPTER_DUMP 0x22
1344
1345/* SLI_2 IOCB Command Set */
1346
1347#define CMD_RCV_SEQUENCE64_CX 0x81
1348#define CMD_XMIT_SEQUENCE64_CR 0x82
1349#define CMD_XMIT_SEQUENCE64_CX 0x83
1350#define CMD_XMIT_BCAST64_CN 0x84
1351#define CMD_XMIT_BCAST64_CX 0x85
1352#define CMD_QUE_RING_BUF64_CN 0x86
1353#define CMD_QUE_XRI_BUF64_CX 0x87
1354#define CMD_IOCB_CONTINUE64_CN 0x88
1355#define CMD_RET_XRI_BUF64_CX 0x89
1356#define CMD_ELS_REQUEST64_CR 0x8A
1357#define CMD_ELS_REQUEST64_CX 0x8B
1358#define CMD_ABORT_MXRI64_CN 0x8C
1359#define CMD_RCV_ELS_REQ64_CX 0x8D
1360#define CMD_XMIT_ELS_RSP64_CX 0x95
1361#define CMD_FCP_IWRITE64_CR 0x98
1362#define CMD_FCP_IWRITE64_CX 0x99
1363#define CMD_FCP_IREAD64_CR 0x9A
1364#define CMD_FCP_IREAD64_CX 0x9B
1365#define CMD_FCP_ICMND64_CR 0x9C
1366#define CMD_FCP_ICMND64_CX 0x9D
f5603511
JS		 1367#define CMD_FCP_TSEND64_CX 0x9F
1368#define CMD_FCP_TRECEIVE64_CX 0xA1
1369#define CMD_FCP_TRSP64_CX 0xA3
dea3101e 1370
ed957684
JS		 1371#define CMD_IOCB_RCV_SEQ64_CX 0xB5
1372#define CMD_IOCB_RCV_ELS64_CX 0xB7
1373#define CMD_IOCB_RCV_CONT64_CX 0xBB
1374
dea3101e 1375#define CMD_GEN_REQUEST64_CR 0xC2
1376#define CMD_GEN_REQUEST64_CX 0xC3
1377
1378#define CMD_MAX_IOCB_CMD 0xE6
1379#define CMD_IOCB_MASK 0xff
1380
1381#define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1382 iocb */
1383#define LPFC_MAX_ADPTMSG 32 /* max msg data */
1384/*
1385 * Define Status
1386 */
1387#define MBX_SUCCESS 0
1388#define MBXERR_NUM_RINGS 1
1389#define MBXERR_NUM_IOCBS 2
1390#define MBXERR_IOCBS_EXCEEDED 3
1391#define MBXERR_BAD_RING_NUMBER 4
1392#define MBXERR_MASK_ENTRIES_RANGE 5
1393#define MBXERR_MASKS_EXCEEDED 6
1394#define MBXERR_BAD_PROFILE 7
1395#define MBXERR_BAD_DEF_CLASS 8
1396#define MBXERR_BAD_MAX_RESPONDER 9
1397#define MBXERR_BAD_MAX_ORIGINATOR 10
1398#define MBXERR_RPI_REGISTERED 11
1399#define MBXERR_RPI_FULL 12
1400#define MBXERR_NO_RESOURCES 13
1401#define MBXERR_BAD_RCV_LENGTH 14
1402#define MBXERR_DMA_ERROR 15
1403#define MBXERR_ERROR 16
1404#define MBX_NOT_FINISHED 255
1405
1406#define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1407#define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1408
1409/*
1410 * Begin Structure Definitions for Mailbox Commands
1411 */
1412
1413typedef struct {
1414#ifdef __BIG_ENDIAN_BITFIELD
1415 uint8_t tval;
1416 uint8_t tmask;
1417 uint8_t rval;
1418 uint8_t rmask;
1419#else /* __LITTLE_ENDIAN_BITFIELD */
1420 uint8_t rmask;
1421 uint8_t rval;
1422 uint8_t tmask;
1423 uint8_t tval;
1424#endif
1425} RR_REG;
1426
1427struct ulp_bde {
1428 uint32_t bdeAddress;
1429#ifdef __BIG_ENDIAN_BITFIELD
1430 uint32_t bdeReserved:4;
1431 uint32_t bdeAddrHigh:4;
1432 uint32_t bdeSize:24;
1433#else /* __LITTLE_ENDIAN_BITFIELD */
1434 uint32_t bdeSize:24;
1435 uint32_t bdeAddrHigh:4;
1436 uint32_t bdeReserved:4;
1437#endif
1438};
1439
1440struct ulp_bde64 { /* SLI-2 */
1441 union ULP_BDE_TUS {
1442 uint32_t w;
1443 struct {
1444#ifdef __BIG_ENDIAN_BITFIELD
1445 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1446 VALUE !! */
1447 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1448#else /* __LITTLE_ENDIAN_BITFIELD */
1449 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1450 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1451 VALUE !! */
1452#endif
1453
1454#define BUFF_USE_RSVD 0x01 /* bdeFlags */
1455#define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */
1456#define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */
1457#define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, 0=xmit
1458 buffer */
1459#define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit
1460 addr */
1461#define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */
1462#define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */
1463#define BUFF_TYPE_INVALID 0x80 /* "" "" */
1464 } f;
1465 } tus;
1466 uint32_t addrLow;
1467 uint32_t addrHigh;
1468};
1469#define BDE64_SIZE_WORD 0
1470#define BPL64_SIZE_WORD 0x40
1471
1472typedef struct ULP_BDL { /* SLI-2 */
1473#ifdef __BIG_ENDIAN_BITFIELD
1474 uint32_t bdeFlags:8; /* BDL Flags */
1475 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1476#else /* __LITTLE_ENDIAN_BITFIELD */
1477 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1478 uint32_t bdeFlags:8; /* BDL Flags */
1479#endif
1480
1481 uint32_t addrLow; /* Address 0:31 */
1482 uint32_t addrHigh; /* Address 32:63 */
1483 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1484} ULP_BDL;
1485
1486/* Structure for MB Command LOAD_SM and DOWN_LOAD */
1487
1488typedef struct {
1489#ifdef __BIG_ENDIAN_BITFIELD
1490 uint32_t rsvd2:25;
1491 uint32_t acknowledgment:1;
1492 uint32_t version:1;
1493 uint32_t erase_or_prog:1;
1494 uint32_t update_flash:1;
1495 uint32_t update_ram:1;
1496 uint32_t method:1;
1497 uint32_t load_cmplt:1;
1498#else /* __LITTLE_ENDIAN_BITFIELD */
1499 uint32_t load_cmplt:1;
1500 uint32_t method:1;
1501 uint32_t update_ram:1;
1502 uint32_t update_flash:1;
1503 uint32_t erase_or_prog:1;
1504 uint32_t version:1;
1505 uint32_t acknowledgment:1;
1506 uint32_t rsvd2:25;
1507#endif
1508
1509 uint32_t dl_to_adr_low;
1510 uint32_t dl_to_adr_high;
1511 uint32_t dl_len;
1512 union {
1513 uint32_t dl_from_mbx_offset;
1514 struct ulp_bde dl_from_bde;
1515 struct ulp_bde64 dl_from_bde64;
1516 } un;
1517
1518} LOAD_SM_VAR;
1519
1520/* Structure for MB Command READ_NVPARM (02) */
1521
1522typedef struct {
1523 uint32_t rsvd1[3]; /* Read as all one's */
1524 uint32_t rsvd2; /* Read as all zero's */
1525 uint32_t portname[2]; /* N_PORT name */
1526 uint32_t nodename[2]; /* NODE name */
1527
1528#ifdef __BIG_ENDIAN_BITFIELD
1529 uint32_t pref_DID:24;
1530 uint32_t hardAL_PA:8;
1531#else /* __LITTLE_ENDIAN_BITFIELD */
1532 uint32_t hardAL_PA:8;
1533 uint32_t pref_DID:24;
1534#endif
1535
1536 uint32_t rsvd3[21]; /* Read as all one's */
1537} READ_NV_VAR;
1538
1539/* Structure for MB Command WRITE_NVPARMS (03) */
1540
1541typedef struct {
1542 uint32_t rsvd1[3]; /* Must be all one's */
1543 uint32_t rsvd2; /* Must be all zero's */
1544 uint32_t portname[2]; /* N_PORT name */
1545 uint32_t nodename[2]; /* NODE name */
1546
1547#ifdef __BIG_ENDIAN_BITFIELD
1548 uint32_t pref_DID:24;
1549 uint32_t hardAL_PA:8;
1550#else /* __LITTLE_ENDIAN_BITFIELD */
1551 uint32_t hardAL_PA:8;
1552 uint32_t pref_DID:24;
1553#endif
1554
1555 uint32_t rsvd3[21]; /* Must be all one's */
1556} WRITE_NV_VAR;
1557
1558/* Structure for MB Command RUN_BIU_DIAG (04) */
1559/* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1560
1561typedef struct {
1562 uint32_t rsvd1;
1563 union {
1564 struct {
1565 struct ulp_bde xmit_bde;
1566 struct ulp_bde rcv_bde;
1567 } s1;
1568 struct {
1569 struct ulp_bde64 xmit_bde64;
1570 struct ulp_bde64 rcv_bde64;
1571 } s2;
1572 } un;
1573} BIU_DIAG_VAR;
1574
1575/* Structure for MB Command INIT_LINK (05) */
1576
1577typedef struct {
1578#ifdef __BIG_ENDIAN_BITFIELD
1579 uint32_t rsvd1:24;
1580 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1581#else /* __LITTLE_ENDIAN_BITFIELD */
1582 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1583 uint32_t rsvd1:24;
1584#endif
1585
1586#ifdef __BIG_ENDIAN_BITFIELD
1587 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1588 uint8_t rsvd2;
1589 uint16_t link_flags;
1590#else /* __LITTLE_ENDIAN_BITFIELD */
1591 uint16_t link_flags;
1592 uint8_t rsvd2;
1593 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1594#endif
1595
1596#define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1597#define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1598#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1599#define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1600#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
92d7f7b0 1601#define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
dea3101e 1602#define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1603
1604#define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1605#define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
4b0b91d4 1606#define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
dea3101e 1607
1608 uint32_t link_speed;
1609#define LINK_SPEED_AUTO 0 /* Auto selection */
1610#define LINK_SPEED_1G 1 /* 1 Gigabaud */
1611#define LINK_SPEED_2G 2 /* 2 Gigabaud */
1612#define LINK_SPEED_4G 4 /* 4 Gigabaud */
b87eab38 1613#define LINK_SPEED_8G 8 /* 8 Gigabaud */
dea3101e 1614#define LINK_SPEED_10G 16 /* 10 Gigabaud */
1615
1616} INIT_LINK_VAR;
1617
1618/* Structure for MB Command DOWN_LINK (06) */
1619
1620typedef struct {
1621 uint32_t rsvd1;
1622} DOWN_LINK_VAR;
1623
1624/* Structure for MB Command CONFIG_LINK (07) */
1625
1626typedef struct {
1627#ifdef __BIG_ENDIAN_BITFIELD
1628 uint32_t cr:1;
1629 uint32_t ci:1;
1630 uint32_t cr_delay:6;
1631 uint32_t cr_count:8;
1632 uint32_t rsvd1:8;
1633 uint32_t MaxBBC:8;
1634#else /* __LITTLE_ENDIAN_BITFIELD */
1635 uint32_t MaxBBC:8;
1636 uint32_t rsvd1:8;
1637 uint32_t cr_count:8;
1638 uint32_t cr_delay:6;
1639 uint32_t ci:1;
1640 uint32_t cr:1;
1641#endif
1642
1643 uint32_t myId;
1644 uint32_t rsvd2;
1645 uint32_t edtov;
1646 uint32_t arbtov;
1647 uint32_t ratov;
1648 uint32_t rttov;
1649 uint32_t altov;
1650 uint32_t crtov;
1651 uint32_t citov;
1652#ifdef __BIG_ENDIAN_BITFIELD
1653 uint32_t rrq_enable:1;
1654 uint32_t rrq_immed:1;
1655 uint32_t rsvd4:29;
1656 uint32_t ack0_enable:1;
1657#else /* __LITTLE_ENDIAN_BITFIELD */
1658 uint32_t ack0_enable:1;
1659 uint32_t rsvd4:29;
1660 uint32_t rrq_immed:1;
1661 uint32_t rrq_enable:1;
1662#endif
1663} CONFIG_LINK;
1664
1665/* Structure for MB Command PART_SLIM (08)
1666 * will be removed since SLI1 is no longer supported!
1667 */
1668typedef struct {
1669#ifdef __BIG_ENDIAN_BITFIELD
1670 uint16_t offCiocb;
1671 uint16_t numCiocb;
1672 uint16_t offRiocb;
1673 uint16_t numRiocb;
1674#else /* __LITTLE_ENDIAN_BITFIELD */
1675 uint16_t numCiocb;
1676 uint16_t offCiocb;
1677 uint16_t numRiocb;
1678 uint16_t offRiocb;
1679#endif
1680} RING_DEF;
1681
1682typedef struct {
1683#ifdef __BIG_ENDIAN_BITFIELD
1684 uint32_t unused1:24;
1685 uint32_t numRing:8;
1686#else /* __LITTLE_ENDIAN_BITFIELD */
1687 uint32_t numRing:8;
1688 uint32_t unused1:24;
1689#endif
1690
1691 RING_DEF ringdef[4];
1692 uint32_t hbainit;
1693} PART_SLIM_VAR;
1694
1695/* Structure for MB Command CONFIG_RING (09) */
1696
1697typedef struct {
1698#ifdef __BIG_ENDIAN_BITFIELD
1699 uint32_t unused2:6;
1700 uint32_t recvSeq:1;
1701 uint32_t recvNotify:1;
1702 uint32_t numMask:8;
1703 uint32_t profile:8;
1704 uint32_t unused1:4;
1705 uint32_t ring:4;
1706#else /* __LITTLE_ENDIAN_BITFIELD */
1707 uint32_t ring:4;
1708 uint32_t unused1:4;
1709 uint32_t profile:8;
1710 uint32_t numMask:8;
1711 uint32_t recvNotify:1;
1712 uint32_t recvSeq:1;
1713 uint32_t unused2:6;
1714#endif
1715
1716#ifdef __BIG_ENDIAN_BITFIELD
1717 uint16_t maxRespXchg;
1718 uint16_t maxOrigXchg;
1719#else /* __LITTLE_ENDIAN_BITFIELD */
1720 uint16_t maxOrigXchg;
1721 uint16_t maxRespXchg;
1722#endif
1723
1724 RR_REG rrRegs[6];
1725} CONFIG_RING_VAR;
1726
1727/* Structure for MB Command RESET_RING (10) */
1728
1729typedef struct {
1730 uint32_t ring_no;
1731} RESET_RING_VAR;
1732
1733/* Structure for MB Command READ_CONFIG (11) */
1734
1735typedef struct {
1736#ifdef __BIG_ENDIAN_BITFIELD
1737 uint32_t cr:1;
1738 uint32_t ci:1;
1739 uint32_t cr_delay:6;
1740 uint32_t cr_count:8;
1741 uint32_t InitBBC:8;
1742 uint32_t MaxBBC:8;
1743#else /* __LITTLE_ENDIAN_BITFIELD */
1744 uint32_t MaxBBC:8;
1745 uint32_t InitBBC:8;
1746 uint32_t cr_count:8;
1747 uint32_t cr_delay:6;
1748 uint32_t ci:1;
1749 uint32_t cr:1;
1750#endif
1751
1752#ifdef __BIG_ENDIAN_BITFIELD
1753 uint32_t topology:8;
1754 uint32_t myDid:24;
1755#else /* __LITTLE_ENDIAN_BITFIELD */
1756 uint32_t myDid:24;
1757 uint32_t topology:8;
1758#endif
1759
1760 /* Defines for topology (defined previously) */
1761#ifdef __BIG_ENDIAN_BITFIELD
1762 uint32_t AR:1;
1763 uint32_t IR:1;
1764 uint32_t rsvd1:29;
1765 uint32_t ack0:1;
1766#else /* __LITTLE_ENDIAN_BITFIELD */
1767 uint32_t ack0:1;
1768 uint32_t rsvd1:29;
1769 uint32_t IR:1;
1770 uint32_t AR:1;
1771#endif
1772
1773 uint32_t edtov;
1774 uint32_t arbtov;
1775 uint32_t ratov;
1776 uint32_t rttov;
1777 uint32_t altov;
1778 uint32_t lmt;
74b72a59
JW		 1779#define LMT_RESERVED 0x000 /* Not used */
1780#define LMT_1Gb 0x004
1781#define LMT_2Gb 0x008
1782#define LMT_4Gb 0x040
1783#define LMT_8Gb 0x080
1784#define LMT_10Gb 0x100
dea3101e 1785 uint32_t rsvd2;
1786 uint32_t rsvd3;
1787 uint32_t max_xri;
1788 uint32_t max_iocb;
1789 uint32_t max_rpi;
1790 uint32_t avail_xri;
1791 uint32_t avail_iocb;
1792 uint32_t avail_rpi;
858c9f6c
JS		 1793 uint32_t max_vpi;
1794 uint32_t rsvd4;
1795 uint32_t rsvd5;
1796 uint32_t avail_vpi;
dea3101e 1797} READ_CONFIG_VAR;
1798
1799/* Structure for MB Command READ_RCONFIG (12) */
1800
1801typedef struct {
1802#ifdef __BIG_ENDIAN_BITFIELD
1803 uint32_t rsvd2:7;
1804 uint32_t recvNotify:1;
1805 uint32_t numMask:8;
1806 uint32_t profile:8;
1807 uint32_t rsvd1:4;
1808 uint32_t ring:4;
1809#else /* __LITTLE_ENDIAN_BITFIELD */
1810 uint32_t ring:4;
1811 uint32_t rsvd1:4;
1812 uint32_t profile:8;
1813 uint32_t numMask:8;
1814 uint32_t recvNotify:1;
1815 uint32_t rsvd2:7;
1816#endif
1817
1818#ifdef __BIG_ENDIAN_BITFIELD
1819 uint16_t maxResp;
1820 uint16_t maxOrig;
1821#else /* __LITTLE_ENDIAN_BITFIELD */
1822 uint16_t maxOrig;
1823 uint16_t maxResp;
1824#endif
1825
1826 RR_REG rrRegs[6];
1827
1828#ifdef __BIG_ENDIAN_BITFIELD
1829 uint16_t cmdRingOffset;
1830 uint16_t cmdEntryCnt;
1831 uint16_t rspRingOffset;
1832 uint16_t rspEntryCnt;
1833 uint16_t nextCmdOffset;
1834 uint16_t rsvd3;
1835 uint16_t nextRspOffset;
1836 uint16_t rsvd4;
1837#else /* __LITTLE_ENDIAN_BITFIELD */
1838 uint16_t cmdEntryCnt;
1839 uint16_t cmdRingOffset;
1840 uint16_t rspEntryCnt;
1841 uint16_t rspRingOffset;
1842 uint16_t rsvd3;
1843 uint16_t nextCmdOffset;
1844 uint16_t rsvd4;
1845 uint16_t nextRspOffset;
1846#endif
1847} READ_RCONF_VAR;
1848
1849/* Structure for MB Command READ_SPARM (13) */
1850/* Structure for MB Command READ_SPARM64 (0x8D) */
1851
1852typedef struct {
1853 uint32_t rsvd1;
1854 uint32_t rsvd2;
1855 union {
1856 struct ulp_bde sp; /* This BDE points to struct serv_parm
1857 structure */
1858 struct ulp_bde64 sp64;
1859 } un;
ed957684
JS		 1860#ifdef __BIG_ENDIAN_BITFIELD
1861 uint16_t rsvd3;
1862 uint16_t vpi;
1863#else /* __LITTLE_ENDIAN_BITFIELD */
1864 uint16_t vpi;
1865 uint16_t rsvd3;
1866#endif
dea3101e 1867} READ_SPARM_VAR;
1868
1869/* Structure for MB Command READ_STATUS (14) */
1870
1871typedef struct {
1872#ifdef __BIG_ENDIAN_BITFIELD
1873 uint32_t rsvd1:31;
1874 uint32_t clrCounters:1;
1875 uint16_t activeXriCnt;
1876 uint16_t activeRpiCnt;
1877#else /* __LITTLE_ENDIAN_BITFIELD */
1878 uint32_t clrCounters:1;
1879 uint32_t rsvd1:31;
1880 uint16_t activeRpiCnt;
1881 uint16_t activeXriCnt;
1882#endif
1883
1884 uint32_t xmitByteCnt;
1885 uint32_t rcvByteCnt;
1886 uint32_t xmitFrameCnt;
1887 uint32_t rcvFrameCnt;
1888 uint32_t xmitSeqCnt;
1889 uint32_t rcvSeqCnt;
1890 uint32_t totalOrigExchanges;
1891 uint32_t totalRespExchanges;
1892 uint32_t rcvPbsyCnt;
1893 uint32_t rcvFbsyCnt;
1894} READ_STATUS_VAR;
1895
1896/* Structure for MB Command READ_RPI (15) */
1897/* Structure for MB Command READ_RPI64 (0x8F) */
1898
1899typedef struct {
1900#ifdef __BIG_ENDIAN_BITFIELD
1901 uint16_t nextRpi;
1902 uint16_t reqRpi;
1903 uint32_t rsvd2:8;
1904 uint32_t DID:24;
1905#else /* __LITTLE_ENDIAN_BITFIELD */
1906 uint16_t reqRpi;
1907 uint16_t nextRpi;
1908 uint32_t DID:24;
1909 uint32_t rsvd2:8;
1910#endif
1911
1912 union {
1913 struct ulp_bde sp;
1914 struct ulp_bde64 sp64;
1915 } un;
1916
1917} READ_RPI_VAR;
1918
1919/* Structure for MB Command READ_XRI (16) */
1920
1921typedef struct {
1922#ifdef __BIG_ENDIAN_BITFIELD
1923 uint16_t nextXri;
1924 uint16_t reqXri;
1925 uint16_t rsvd1;
1926 uint16_t rpi;
1927 uint32_t rsvd2:8;
1928 uint32_t DID:24;
1929 uint32_t rsvd3:8;
1930 uint32_t SID:24;
1931 uint32_t rsvd4;
1932 uint8_t seqId;
1933 uint8_t rsvd5;
1934 uint16_t seqCount;
1935 uint16_t oxId;
1936 uint16_t rxId;
1937 uint32_t rsvd6:30;
1938 uint32_t si:1;
1939 uint32_t exchOrig:1;
1940#else /* __LITTLE_ENDIAN_BITFIELD */
1941 uint16_t reqXri;
1942 uint16_t nextXri;
1943 uint16_t rpi;
1944 uint16_t rsvd1;
1945 uint32_t DID:24;
1946 uint32_t rsvd2:8;
1947 uint32_t SID:24;
1948 uint32_t rsvd3:8;
1949 uint32_t rsvd4;
1950 uint16_t seqCount;
1951 uint8_t rsvd5;
1952 uint8_t seqId;
1953 uint16_t rxId;
1954 uint16_t oxId;
1955 uint32_t exchOrig:1;
1956 uint32_t si:1;
1957 uint32_t rsvd6:30;
1958#endif
1959} READ_XRI_VAR;
1960
1961/* Structure for MB Command READ_REV (17) */
1962
1963typedef struct {
1964#ifdef __BIG_ENDIAN_BITFIELD
1965 uint32_t cv:1;
1966 uint32_t rr:1;
ed957684
JS		 1967 uint32_t rsvd2:2;
1968 uint32_t v3req:1;
1969 uint32_t v3rsp:1;
1970 uint32_t rsvd1:25;
dea3101e 1971 uint32_t rv:1;
1972#else /* __LITTLE_ENDIAN_BITFIELD */
1973 uint32_t rv:1;
ed957684
JS		 1974 uint32_t rsvd1:25;
1975 uint32_t v3rsp:1;
1976 uint32_t v3req:1;
1977 uint32_t rsvd2:2;
dea3101e 1978 uint32_t rr:1;
1979 uint32_t cv:1;
1980#endif
1981
1982 uint32_t biuRev;
1983 uint32_t smRev;
1984 union {
1985 uint32_t smFwRev;
1986 struct {
1987#ifdef __BIG_ENDIAN_BITFIELD
1988 uint8_t ProgType;
1989 uint8_t ProgId;
1990 uint16_t ProgVer:4;
1991 uint16_t ProgRev:4;
1992 uint16_t ProgFixLvl:2;
1993 uint16_t ProgDistType:2;
1994 uint16_t DistCnt:4;
1995#else /* __LITTLE_ENDIAN_BITFIELD */
1996 uint16_t DistCnt:4;
1997 uint16_t ProgDistType:2;
1998 uint16_t ProgFixLvl:2;
1999 uint16_t ProgRev:4;
2000 uint16_t ProgVer:4;
2001 uint8_t ProgId;
2002 uint8_t ProgType;
2003#endif
2004
2005 } b;
2006 } un;
2007 uint32_t endecRev;
2008#ifdef __BIG_ENDIAN_BITFIELD
2009 uint8_t feaLevelHigh;
2010 uint8_t feaLevelLow;
2011 uint8_t fcphHigh;
2012 uint8_t fcphLow;
2013#else /* __LITTLE_ENDIAN_BITFIELD */
2014 uint8_t fcphLow;
2015 uint8_t fcphHigh;
2016 uint8_t feaLevelLow;
2017 uint8_t feaLevelHigh;
2018#endif
2019
2020 uint32_t postKernRev;
2021 uint32_t opFwRev;
2022 uint8_t opFwName[16];
2023 uint32_t sli1FwRev;
2024 uint8_t sli1FwName[16];
2025 uint32_t sli2FwRev;
2026 uint8_t sli2FwName[16];
ed957684
JS		 2027 uint32_t sli3Feat;
2028 uint32_t RandomData[6];
dea3101e 2029} READ_REV_VAR;
2030
2031/* Structure for MB Command READ_LINK_STAT (18) */
2032
2033typedef struct {
2034 uint32_t rsvd1;
2035 uint32_t linkFailureCnt;
2036 uint32_t lossSyncCnt;
2037
2038 uint32_t lossSignalCnt;
2039 uint32_t primSeqErrCnt;
2040 uint32_t invalidXmitWord;
2041 uint32_t crcCnt;
2042 uint32_t primSeqTimeout;
2043 uint32_t elasticOverrun;
2044 uint32_t arbTimeout;
2045} READ_LNK_VAR;
2046
2047/* Structure for MB Command REG_LOGIN (19) */
2048/* Structure for MB Command REG_LOGIN64 (0x93) */
2049
2050typedef struct {
2051#ifdef __BIG_ENDIAN_BITFIELD
2052 uint16_t rsvd1;
2053 uint16_t rpi;
2054 uint32_t rsvd2:8;
2055 uint32_t did:24;
2056#else /* __LITTLE_ENDIAN_BITFIELD */
2057 uint16_t rpi;
2058 uint16_t rsvd1;
2059 uint32_t did:24;
2060 uint32_t rsvd2:8;
2061#endif
2062
2063 union {
2064 struct ulp_bde sp;
2065 struct ulp_bde64 sp64;
2066 } un;
2067
ed957684
JS		 2068#ifdef __BIG_ENDIAN_BITFIELD
2069 uint16_t rsvd6;
2070 uint16_t vpi;
2071#else /* __LITTLE_ENDIAN_BITFIELD */
2072 uint16_t vpi;
2073 uint16_t rsvd6;
2074#endif
2075
dea3101e 2076} REG_LOGIN_VAR;
2077
2078/* Word 30 contents for REG_LOGIN */
2079typedef union {
2080 struct {
2081#ifdef __BIG_ENDIAN_BITFIELD
2082 uint16_t rsvd1:12;
2083 uint16_t wd30_class:4;
2084 uint16_t xri;
2085#else /* __LITTLE_ENDIAN_BITFIELD */
2086 uint16_t xri;
2087 uint16_t wd30_class:4;
2088 uint16_t rsvd1:12;
2089#endif
2090 } f;
2091 uint32_t word;
2092} REG_WD30;
2093
2094/* Structure for MB Command UNREG_LOGIN (20) */
2095
2096typedef struct {
2097#ifdef __BIG_ENDIAN_BITFIELD
2098 uint16_t rsvd1;
2099 uint16_t rpi;
ed957684
JS		 2100 uint32_t rsvd2;
2101 uint32_t rsvd3;
2102 uint32_t rsvd4;
2103 uint32_t rsvd5;
2104 uint16_t rsvd6;
2105 uint16_t vpi;
dea3101e 2106#else /* __LITTLE_ENDIAN_BITFIELD */
2107 uint16_t rpi;
2108 uint16_t rsvd1;
ed957684
JS		 2109 uint32_t rsvd2;
2110 uint32_t rsvd3;
2111 uint32_t rsvd4;
2112 uint32_t rsvd5;
2113 uint16_t vpi;
2114 uint16_t rsvd6;
dea3101e 2115#endif
2116} UNREG_LOGIN_VAR;
2117
92d7f7b0
JS		 2118/* Structure for MB Command REG_VPI (0x96) */
2119typedef struct {
2120#ifdef __BIG_ENDIAN_BITFIELD
2121 uint32_t rsvd1;
2122 uint32_t rsvd2:8;
2123 uint32_t sid:24;
2124 uint32_t rsvd3;
2125 uint32_t rsvd4;
2126 uint32_t rsvd5;
2127 uint16_t rsvd6;
2128 uint16_t vpi;
2129#else /* __LITTLE_ENDIAN */
2130 uint32_t rsvd1;
2131 uint32_t sid:24;
2132 uint32_t rsvd2:8;
2133 uint32_t rsvd3;
2134 uint32_t rsvd4;
2135 uint32_t rsvd5;
2136 uint16_t vpi;
2137 uint16_t rsvd6;
2138#endif
2139} REG_VPI_VAR;
2140
2141/* Structure for MB Command UNREG_VPI (0x97) */
2142typedef struct {
2143 uint32_t rsvd1;
2144 uint32_t rsvd2;
2145 uint32_t rsvd3;
2146 uint32_t rsvd4;
2147 uint32_t rsvd5;
2148#ifdef __BIG_ENDIAN_BITFIELD
2149 uint16_t rsvd6;
2150 uint16_t vpi;
2151#else /* __LITTLE_ENDIAN */
2152 uint16_t vpi;
2153 uint16_t rsvd6;
2154#endif
2155} UNREG_VPI_VAR;
2156
dea3101e 2157/* Structure for MB Command UNREG_D_ID (0x23) */
2158
2159typedef struct {
2160 uint32_t did;
ed957684
JS		 2161 uint32_t rsvd2;
2162 uint32_t rsvd3;
2163 uint32_t rsvd4;
2164 uint32_t rsvd5;
2165#ifdef __BIG_ENDIAN_BITFIELD
2166 uint16_t rsvd6;
2167 uint16_t vpi;
2168#else
2169 uint16_t vpi;
2170 uint16_t rsvd6;
2171#endif
dea3101e 2172} UNREG_D_ID_VAR;
2173
2174/* Structure for MB Command READ_LA (21) */
2175/* Structure for MB Command READ_LA64 (0x95) */
2176
2177typedef struct {
2178 uint32_t eventTag; /* Event tag */
2179#ifdef __BIG_ENDIAN_BITFIELD
2180 uint32_t rsvd1:22;
2181 uint32_t pb:1;
2182 uint32_t il:1;
2183 uint32_t attType:8;
2184#else /* __LITTLE_ENDIAN_BITFIELD */
2185 uint32_t attType:8;
2186 uint32_t il:1;
2187 uint32_t pb:1;
2188 uint32_t rsvd1:22;
2189#endif
2190
2191#define AT_RESERVED 0x00 /* Reserved - attType */
2192#define AT_LINK_UP 0x01 /* Link is up */
2193#define AT_LINK_DOWN 0x02 /* Link is down */
2194
2195#ifdef __BIG_ENDIAN_BITFIELD
2196 uint8_t granted_AL_PA;
2197 uint8_t lipAlPs;
2198 uint8_t lipType;
2199 uint8_t topology;
2200#else /* __LITTLE_ENDIAN_BITFIELD */
2201 uint8_t topology;
2202 uint8_t lipType;
2203 uint8_t lipAlPs;
2204 uint8_t granted_AL_PA;
2205#endif
2206
2207#define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2208#define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2209
2210 union {
2211 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer
2212 to */
2213 /* store the LILP AL_PA position map into */
2214 struct ulp_bde64 lilpBde64;
2215 } un;
2216
2217#ifdef __BIG_ENDIAN_BITFIELD
2218 uint32_t Dlu:1;
2219 uint32_t Dtf:1;
2220 uint32_t Drsvd2:14;
2221 uint32_t DlnkSpeed:8;
2222 uint32_t DnlPort:4;
2223 uint32_t Dtx:2;
2224 uint32_t Drx:2;
2225#else /* __LITTLE_ENDIAN_BITFIELD */
2226 uint32_t Drx:2;
2227 uint32_t Dtx:2;
2228 uint32_t DnlPort:4;
2229 uint32_t DlnkSpeed:8;
2230 uint32_t Drsvd2:14;
2231 uint32_t Dtf:1;
2232 uint32_t Dlu:1;
2233#endif
2234
2235#ifdef __BIG_ENDIAN_BITFIELD
2236 uint32_t Ulu:1;
2237 uint32_t Utf:1;
2238 uint32_t Ursvd2:14;
2239 uint32_t UlnkSpeed:8;
2240 uint32_t UnlPort:4;
2241 uint32_t Utx:2;
2242 uint32_t Urx:2;
2243#else /* __LITTLE_ENDIAN_BITFIELD */
2244 uint32_t Urx:2;
2245 uint32_t Utx:2;
2246 uint32_t UnlPort:4;
2247 uint32_t UlnkSpeed:8;
2248 uint32_t Ursvd2:14;
2249 uint32_t Utf:1;
2250 uint32_t Ulu:1;
2251#endif
2252
2253#define LA_UNKNW_LINK 0x0 /* lnkSpeed */
2254#define LA_1GHZ_LINK 0x04 /* lnkSpeed */
2255#define LA_2GHZ_LINK 0x08 /* lnkSpeed */
2256#define LA_4GHZ_LINK 0x10 /* lnkSpeed */
2257#define LA_8GHZ_LINK 0x20 /* lnkSpeed */
2258#define LA_10GHZ_LINK 0x40 /* lnkSpeed */
2259
2260} READ_LA_VAR;
2261
2262/* Structure for MB Command CLEAR_LA (22) */
2263
2264typedef struct {
2265 uint32_t eventTag; /* Event tag */
2266 uint32_t rsvd1;
2267} CLEAR_LA_VAR;
2268
2269/* Structure for MB Command DUMP */
2270
2271typedef struct {
2272#ifdef __BIG_ENDIAN_BITFIELD
2273 uint32_t rsvd:25;
2274 uint32_t ra:1;
2275 uint32_t co:1;
2276 uint32_t cv:1;
2277 uint32_t type:4;
2278 uint32_t entry_index:16;
2279 uint32_t region_id:16;
2280#else /* __LITTLE_ENDIAN_BITFIELD */
2281 uint32_t type:4;
2282 uint32_t cv:1;
2283 uint32_t co:1;
2284 uint32_t ra:1;
2285 uint32_t rsvd:25;
2286 uint32_t region_id:16;
2287 uint32_t entry_index:16;
2288#endif
2289
2290 uint32_t rsvd1;
2291 uint32_t word_cnt;
2292 uint32_t resp_offset;
2293} DUMP_VAR;
2294
2295#define DMP_MEM_REG 0x1
2296#define DMP_NV_PARAMS 0x2
2297
2298#define DMP_REGION_VPD 0xe
2299#define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2300#define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2301#define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2302
ed957684
JS		 2303struct hbq_mask {
2304#ifdef __BIG_ENDIAN_BITFIELD
2305 uint8_t tmatch;
2306 uint8_t tmask;
2307 uint8_t rctlmatch;
2308 uint8_t rctlmask;
2309#else /* __LITTLE_ENDIAN */
2310 uint8_t rctlmask;
2311 uint8_t rctlmatch;
2312 uint8_t tmask;
2313 uint8_t tmatch;
2314#endif
2315};
2316
2317
2318/* Structure for MB Command CONFIG_HBQ (7c) */
2319
2320struct config_hbq_var {
2321#ifdef __BIG_ENDIAN_BITFIELD
2322 uint32_t rsvd1 :7;
2323 uint32_t recvNotify :1; /* Receive Notification */
2324 uint32_t numMask :8; /* # Mask Entries */
2325 uint32_t profile :8; /* Selection Profile */
2326 uint32_t rsvd2 :8;
2327#else /* __LITTLE_ENDIAN */
2328 uint32_t rsvd2 :8;
2329 uint32_t profile :8; /* Selection Profile */
2330 uint32_t numMask :8; /* # Mask Entries */
2331 uint32_t recvNotify :1; /* Receive Notification */
2332 uint32_t rsvd1 :7;
2333#endif
2334
2335#ifdef __BIG_ENDIAN_BITFIELD
2336 uint32_t hbqId :16;
2337 uint32_t rsvd3 :12;
2338 uint32_t ringMask :4;
2339#else /* __LITTLE_ENDIAN */
2340 uint32_t ringMask :4;
2341 uint32_t rsvd3 :12;
2342 uint32_t hbqId :16;
2343#endif
2344
2345#ifdef __BIG_ENDIAN_BITFIELD
2346 uint32_t entry_count :16;
2347 uint32_t rsvd4 :8;
2348 uint32_t headerLen :8;
2349#else /* __LITTLE_ENDIAN */
2350 uint32_t headerLen :8;
2351 uint32_t rsvd4 :8;
2352 uint32_t entry_count :16;
2353#endif
2354
2355 uint32_t hbqaddrLow;
2356 uint32_t hbqaddrHigh;
2357
2358#ifdef __BIG_ENDIAN_BITFIELD
2359 uint32_t rsvd5 :31;
2360 uint32_t logEntry :1;
2361#else /* __LITTLE_ENDIAN */
2362 uint32_t logEntry :1;
2363 uint32_t rsvd5 :31;
2364#endif
2365
2366 uint32_t rsvd6; /* w7 */
2367 uint32_t rsvd7; /* w8 */
2368 uint32_t rsvd8; /* w9 */
2369
2370 struct hbq_mask hbqMasks[6];
2371
2372
2373 union {
2374 uint32_t allprofiles[12];
2375
2376 struct {
2377 #ifdef __BIG_ENDIAN_BITFIELD
2378 uint32_t seqlenoff :16;
2379 uint32_t maxlen :16;
2380 #else /* __LITTLE_ENDIAN */
2381 uint32_t maxlen :16;
2382 uint32_t seqlenoff :16;
2383 #endif
2384 #ifdef __BIG_ENDIAN_BITFIELD
2385 uint32_t rsvd1 :28;
2386 uint32_t seqlenbcnt :4;
2387 #else /* __LITTLE_ENDIAN */
2388 uint32_t seqlenbcnt :4;
2389 uint32_t rsvd1 :28;
2390 #endif
2391 uint32_t rsvd[10];
2392 } profile2;
2393
2394 struct {
2395 #ifdef __BIG_ENDIAN_BITFIELD
2396 uint32_t seqlenoff :16;
2397 uint32_t maxlen :16;
2398 #else /* __LITTLE_ENDIAN */
2399 uint32_t maxlen :16;
2400 uint32_t seqlenoff :16;
2401 #endif
2402 #ifdef __BIG_ENDIAN_BITFIELD
2403 uint32_t cmdcodeoff :28;
2404 uint32_t rsvd1 :12;
2405 uint32_t seqlenbcnt :4;
2406 #else /* __LITTLE_ENDIAN */
2407 uint32_t seqlenbcnt :4;
2408 uint32_t rsvd1 :12;
2409 uint32_t cmdcodeoff :28;
2410 #endif
2411 uint32_t cmdmatch[8];
2412
2413 uint32_t rsvd[2];
2414 } profile3;
2415
2416 struct {
2417 #ifdef __BIG_ENDIAN_BITFIELD
2418 uint32_t seqlenoff :16;
2419 uint32_t maxlen :16;
2420 #else /* __LITTLE_ENDIAN */
2421 uint32_t maxlen :16;
2422 uint32_t seqlenoff :16;
2423 #endif
2424 #ifdef __BIG_ENDIAN_BITFIELD
2425 uint32_t cmdcodeoff :28;
2426 uint32_t rsvd1 :12;
2427 uint32_t seqlenbcnt :4;
2428 #else /* __LITTLE_ENDIAN */
2429 uint32_t seqlenbcnt :4;
2430 uint32_t rsvd1 :12;
2431 uint32_t cmdcodeoff :28;
2432 #endif
2433 uint32_t cmdmatch[8];
2434
2435 uint32_t rsvd[2];
2436 } profile5;
2437
2438 } profiles;
2439
2440};
2441
2442
dea3101e 2443
2e0fef85 2444/* Structure for MB Command CONFIG_PORT (0x88) */
dea3101e 2445typedef struct {
ed957684
JS		 2446#ifdef __BIG_ENDIAN_BITFIELD
2447 uint32_t cBE : 1;
2448 uint32_t cET : 1;
2449 uint32_t cHpcb : 1;
2450 uint32_t cMA : 1;
2451 uint32_t sli_mode : 4;
2452 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2453 * config block */
2454#else /* __LITTLE_ENDIAN */
2455 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2456 * config block */
2457 uint32_t sli_mode : 4;
2458 uint32_t cMA : 1;
2459 uint32_t cHpcb : 1;
2460 uint32_t cET : 1;
2461 uint32_t cBE : 1;
2462#endif
2463
dea3101e 2464 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2465 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
ed957684
JS		 2466 uint32_t hbainit[6];
2467
2468#ifdef __BIG_ENDIAN_BITFIELD
2469 uint32_t rsvd : 24; /* Reserved */
2470 uint32_t cmv : 1; /* Configure Max VPIs */
2471 uint32_t ccrp : 1; /* Config Command Ring Polling */
2472 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2473 uint32_t chbs : 1; /* Cofigure Host Backing store */
2474 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2475 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2476 uint32_t cmx : 1; /* Configure Max XRIs */
2477 uint32_t cmr : 1; /* Configure Max RPIs */
2478#else /* __LITTLE_ENDIAN */
2479 uint32_t cmr : 1; /* Configure Max RPIs */
2480 uint32_t cmx : 1; /* Configure Max XRIs */
2481 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2482 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2483 uint32_t chbs : 1; /* Cofigure Host Backing store */
2484 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2485 uint32_t ccrp : 1; /* Config Command Ring Polling */
2486 uint32_t cmv : 1; /* Configure Max VPIs */
2487 uint32_t rsvd : 24; /* Reserved */
2488#endif
2489#ifdef __BIG_ENDIAN_BITFIELD
2490 uint32_t rsvd2 : 24; /* Reserved */
2491 uint32_t gmv : 1; /* Grant Max VPIs */
2492 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2493 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2494 uint32_t ghbs : 1; /* Grant Host Backing Store */
2495 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2496 uint32_t gerbm : 1; /* Grant ERBM Request */
2497 uint32_t gmx : 1; /* Grant Max XRIs */
2498 uint32_t gmr : 1; /* Grant Max RPIs */
2499#else /* __LITTLE_ENDIAN */
2500 uint32_t gmr : 1; /* Grant Max RPIs */
2501 uint32_t gmx : 1; /* Grant Max XRIs */
2502 uint32_t gerbm : 1; /* Grant ERBM Request */
2503 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2504 uint32_t ghbs : 1; /* Grant Host Backing Store */
2505 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2506 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2507 uint32_t gmv : 1; /* Grant Max VPIs */
2508 uint32_t rsvd2 : 24; /* Reserved */
2509#endif
2510
2511#ifdef __BIG_ENDIAN_BITFIELD
2512 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2513 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2514#else /* __LITTLE_ENDIAN */
2515 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2516 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2517#endif
2518
2519#ifdef __BIG_ENDIAN_BITFIELD
2520 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2521 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */
2522#else /* __LITTLE_ENDIAN */
2523 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */
2524 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2525#endif
2526
2527 uint32_t rsvd4; /* Reserved */
2528
2529#ifdef __BIG_ENDIAN_BITFIELD
2530 uint32_t rsvd5 : 16; /* Reserved */
2531 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2532#else /* __LITTLE_ENDIAN */
2533 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2534 uint32_t rsvd5 : 16; /* Reserved */
2535#endif
2536
dea3101e 2537} CONFIG_PORT_VAR;
2538
2539/* SLI-2 Port Control Block */
2540
2541/* SLIM POINTER */
2542#define SLIMOFF 0x30 /* WORD */
2543
2544typedef struct _SLI2_RDSC {
2545 uint32_t cmdEntries;
2546 uint32_t cmdAddrLow;
2547 uint32_t cmdAddrHigh;
2548
2549 uint32_t rspEntries;
2550 uint32_t rspAddrLow;
2551 uint32_t rspAddrHigh;
2552} SLI2_RDSC;
2553
2554typedef struct _PCB {
2555#ifdef __BIG_ENDIAN_BITFIELD
2556 uint32_t type:8;
2557#define TYPE_NATIVE_SLI2 0x01;
2558 uint32_t feature:8;
2559#define FEATURE_INITIAL_SLI2 0x01;
2560 uint32_t rsvd:12;
2561 uint32_t maxRing:4;
2562#else /* __LITTLE_ENDIAN_BITFIELD */
2563 uint32_t maxRing:4;
2564 uint32_t rsvd:12;
2565 uint32_t feature:8;
2566#define FEATURE_INITIAL_SLI2 0x01;
2567 uint32_t type:8;
2568#define TYPE_NATIVE_SLI2 0x01;
2569#endif
2570
2571 uint32_t mailBoxSize;
2572 uint32_t mbAddrLow;
2573 uint32_t mbAddrHigh;
2574
2575 uint32_t hgpAddrLow;
2576 uint32_t hgpAddrHigh;
2577
2578 uint32_t pgpAddrLow;
2579 uint32_t pgpAddrHigh;
2580 SLI2_RDSC rdsc[MAX_RINGS];
2581} PCB_t;
2582
2583/* NEW_FEATURE */
2584typedef struct {
2585#ifdef __BIG_ENDIAN_BITFIELD
2586 uint32_t rsvd0:27;
2587 uint32_t discardFarp:1;
2588 uint32_t IPEnable:1;
2589 uint32_t nodeName:1;
2590 uint32_t portName:1;
2591 uint32_t filterEnable:1;
2592#else /* __LITTLE_ENDIAN_BITFIELD */
2593 uint32_t filterEnable:1;
2594 uint32_t portName:1;
2595 uint32_t nodeName:1;
2596 uint32_t IPEnable:1;
2597 uint32_t discardFarp:1;
2598 uint32_t rsvd:27;
2599#endif
2600
2601 uint8_t portname[8]; /* Used to be struct lpfc_name */
2602 uint8_t nodename[8];
2603 uint32_t rsvd1;
2604 uint32_t rsvd2;
2605 uint32_t rsvd3;
2606 uint32_t IPAddress;
2607} CONFIG_FARP_VAR;
2608
2609/* Union of all Mailbox Command types */
2610#define MAILBOX_CMD_WSIZE 32
2611#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2612
2613typedef union {
ed957684
JS		 2614 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
2615 * feature/max ring number
2616 */
2617 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
2618 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
2619 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
311464ec
JS		 2620 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
2621 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
dea3101e 2622 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
ed957684
JS		 2623 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
2624 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
dea3101e 2625 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
2626 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
2627 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
2628 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
2629 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
2630 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
ed957684
JS		 2631 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
2632 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
2633 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
2634 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
dea3101e 2635 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
2636 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
ed957684 2637 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */
dea3101e 2638 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
ed957684
JS		 2639 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
2640 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
2641 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
2642 * NEW_FEATURE
2643 */
2644 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
2645 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
92d7f7b0
JS		 2646 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
2647 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
dea3101e 2648} MAILVARIANTS;
2649
2650/*
2651 * SLI-2 specific structures
2652 */
2653
4cc2da1d
JSEC		 2654struct lpfc_hgp {
2655 __le32 cmdPutInx;
2656 __le32 rspGetInx;
2657};
dea3101e 2658
4cc2da1d
JSEC		 2659struct lpfc_pgp {
2660 __le32 cmdGetInx;
2661 __le32 rspPutInx;
2662};
dea3101e 2663
ed957684 2664struct sli2_desc {
dea3101e 2665 uint32_t unused1[16];
ed957684
JS		 2666 struct lpfc_hgp host[MAX_RINGS];
2667 struct lpfc_pgp port[MAX_RINGS];
2668};
2669
2670struct sli3_desc {
2671 struct lpfc_hgp host[MAX_RINGS];
2672 uint32_t reserved[8];
2673 uint32_t hbq_put[16];
2674};
2675
2676struct sli3_pgp {
4cc2da1d 2677 struct lpfc_pgp port[MAX_RINGS];
ed957684
JS		 2678 uint32_t hbq_get[16];
2679};
dea3101e 2680
2681typedef union {
ed957684
JS		 2682 struct sli2_desc s2;
2683 struct sli3_desc s3;
2684 struct sli3_pgp s3_pgp;
dea3101e 2685} SLI_VAR;
2686
2687typedef struct {
2688#ifdef __BIG_ENDIAN_BITFIELD
2689 uint16_t mbxStatus;
2690 uint8_t mbxCommand;
2691 uint8_t mbxReserved:6;
2692 uint8_t mbxHc:1;
2693 uint8_t mbxOwner:1; /* Low order bit first word */
2694#else /* __LITTLE_ENDIAN_BITFIELD */
2695 uint8_t mbxOwner:1; /* Low order bit first word */
2696 uint8_t mbxHc:1;
2697 uint8_t mbxReserved:6;
2698 uint8_t mbxCommand;
2699 uint16_t mbxStatus;
2700#endif
2701
2702 MAILVARIANTS un;
2703 SLI_VAR us;
2704} MAILBOX_t;
2705
2706/*
2707 * Begin Structure Definitions for IOCB Commands
2708 */
2709
2710typedef struct {
2711#ifdef __BIG_ENDIAN_BITFIELD
2712 uint8_t statAction;
2713 uint8_t statRsn;
2714 uint8_t statBaExp;
2715 uint8_t statLocalError;
2716#else /* __LITTLE_ENDIAN_BITFIELD */
2717 uint8_t statLocalError;
2718 uint8_t statBaExp;
2719 uint8_t statRsn;
2720 uint8_t statAction;
2721#endif
2722 /* statRsn P/F_RJT reason codes */
2723#define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
2724#define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
2725#define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
2726#define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
2727#define RJT_UNSUP_CLASS 0x05 /* Class not supported */
2728#define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
2729#define RJT_UNSUP_TYPE 0x07 /* Type not supported */
2730#define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
2731#define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
2732#define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
2733#define RJT_BAD_OXID 0x0B /* OX_ID invalid */
2734#define RJT_BAD_RXID 0x0C /* RX_ID invalid */
2735#define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
2736#define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
2737#define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
2738#define RJT_BAD_PARM 0x10 /* Param. field invalid */
2739#define RJT_XCHG_ERR 0x11 /* Exchange error */
2740#define RJT_PROT_ERR 0x12 /* Protocol error */
2741#define RJT_BAD_LENGTH 0x13 /* Invalid Length */
2742#define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
2743#define RJT_LOGIN_REQUIRED 0x16 /* Login required */
2744#define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
2745#define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
2746#define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
2747#define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
2748#define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
2749
2750#define IOERR_SUCCESS 0x00 /* statLocalError */
2751#define IOERR_MISSING_CONTINUE 0x01
2752#define IOERR_SEQUENCE_TIMEOUT 0x02
2753#define IOERR_INTERNAL_ERROR 0x03
2754#define IOERR_INVALID_RPI 0x04
2755#define IOERR_NO_XRI 0x05
2756#define IOERR_ILLEGAL_COMMAND 0x06
2757#define IOERR_XCHG_DROPPED 0x07
2758#define IOERR_ILLEGAL_FIELD 0x08
2759#define IOERR_BAD_CONTINUE 0x09
2760#define IOERR_TOO_MANY_BUFFERS 0x0A
2761#define IOERR_RCV_BUFFER_WAITING 0x0B
2762#define IOERR_NO_CONNECTION 0x0C
2763#define IOERR_TX_DMA_FAILED 0x0D
2764#define IOERR_RX_DMA_FAILED 0x0E
2765#define IOERR_ILLEGAL_FRAME 0x0F
2766#define IOERR_EXTRA_DATA 0x10
2767#define IOERR_NO_RESOURCES 0x11
2768#define IOERR_RESERVED 0x12
2769#define IOERR_ILLEGAL_LENGTH 0x13
2770#define IOERR_UNSUPPORTED_FEATURE 0x14
2771#define IOERR_ABORT_IN_PROGRESS 0x15
2772#define IOERR_ABORT_REQUESTED 0x16
2773#define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
2774#define IOERR_LOOP_OPEN_FAILURE 0x18
2775#define IOERR_RING_RESET 0x19
2776#define IOERR_LINK_DOWN 0x1A
2777#define IOERR_CORRUPTED_DATA 0x1B
2778#define IOERR_CORRUPTED_RPI 0x1C
2779#define IOERR_OUT_OF_ORDER_DATA 0x1D
2780#define IOERR_OUT_OF_ORDER_ACK 0x1E
2781#define IOERR_DUP_FRAME 0x1F
2782#define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
2783#define IOERR_BAD_HOST_ADDRESS 0x21
2784#define IOERR_RCV_HDRBUF_WAITING 0x22
2785#define IOERR_MISSING_HDR_BUFFER 0x23
2786#define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
2787#define IOERR_ABORTMULT_REQUESTED 0x25
2788#define IOERR_BUFFER_SHORTAGE 0x28
2789#define IOERR_DEFAULT 0x29
2790#define IOERR_CNT 0x2A
2791
2792#define IOERR_DRVR_MASK 0x100
2793#define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
2794#define IOERR_SLI_BRESET 0x102
2795#define IOERR_SLI_ABORTED 0x103
2796} PARM_ERR;
2797
2798typedef union {
2799 struct {
2800#ifdef __BIG_ENDIAN_BITFIELD
2801 uint8_t Rctl; /* R_CTL field */
2802 uint8_t Type; /* TYPE field */
2803 uint8_t Dfctl; /* DF_CTL field */
2804 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2805#else /* __LITTLE_ENDIAN_BITFIELD */
2806 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2807 uint8_t Dfctl; /* DF_CTL field */
2808 uint8_t Type; /* TYPE field */
2809 uint8_t Rctl; /* R_CTL field */
2810#endif
2811
2812#define BC 0x02 /* Broadcast Received - Fctl */
2813#define SI 0x04 /* Sequence Initiative */
2814#define LA 0x08 /* Ignore Link Attention state */
2815#define LS 0x80 /* Last Sequence */
2816 } hcsw;
2817 uint32_t reserved;
2818} WORD5;
2819
2820/* IOCB Command template for a generic response */
2821typedef struct {
2822 uint32_t reserved[4];
2823 PARM_ERR perr;
2824} GENERIC_RSP;
2825
2826/* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
2827typedef struct {
2828 struct ulp_bde xrsqbde[2];
2829 uint32_t xrsqRo; /* Starting Relative Offset */
2830 WORD5 w5; /* Header control/status word */
2831} XR_SEQ_FIELDS;
2832
2833/* IOCB Command template for ELS_REQUEST */
2834typedef struct {
2835 struct ulp_bde elsReq;
2836 struct ulp_bde elsRsp;
2837
2838#ifdef __BIG_ENDIAN_BITFIELD
2839 uint32_t word4Rsvd:7;
2840 uint32_t fl:1;
2841 uint32_t myID:24;
2842 uint32_t word5Rsvd:8;
2843 uint32_t remoteID:24;
2844#else /* __LITTLE_ENDIAN_BITFIELD */
2845 uint32_t myID:24;
2846 uint32_t fl:1;
2847 uint32_t word4Rsvd:7;
2848 uint32_t remoteID:24;
2849 uint32_t word5Rsvd:8;
2850#endif
2851} ELS_REQUEST;
2852
2853/* IOCB Command template for RCV_ELS_REQ */
2854typedef struct {
2855 struct ulp_bde elsReq[2];
2856 uint32_t parmRo;
2857
2858#ifdef __BIG_ENDIAN_BITFIELD
2859 uint32_t word5Rsvd:8;
2860 uint32_t remoteID:24;
2861#else /* __LITTLE_ENDIAN_BITFIELD */
2862 uint32_t remoteID:24;
2863 uint32_t word5Rsvd:8;
2864#endif
2865} RCV_ELS_REQ;
2866
2867/* IOCB Command template for ABORT / CLOSE_XRI */
2868typedef struct {
2869 uint32_t rsvd[3];
2870 uint32_t abortType;
2871#define ABORT_TYPE_ABTX 0x00000000
2872#define ABORT_TYPE_ABTS 0x00000001
2873 uint32_t parm;
2874#ifdef __BIG_ENDIAN_BITFIELD
2875 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2876 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2877#else /* __LITTLE_ENDIAN_BITFIELD */
2878 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2879 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2880#endif
2881} AC_XRI;
2882
2883/* IOCB Command template for ABORT_MXRI64 */
2884typedef struct {
2885 uint32_t rsvd[3];
2886 uint32_t abortType;
2887 uint32_t parm;
2888 uint32_t iotag32;
2889} A_MXRI64;
2890
2891/* IOCB Command template for GET_RPI */
2892typedef struct {
2893 uint32_t rsvd[4];
2894 uint32_t parmRo;
2895#ifdef __BIG_ENDIAN_BITFIELD
2896 uint32_t word5Rsvd:8;
2897 uint32_t remoteID:24;
2898#else /* __LITTLE_ENDIAN_BITFIELD */
2899 uint32_t remoteID:24;
2900 uint32_t word5Rsvd:8;
2901#endif
2902} GET_RPI;
2903
2904/* IOCB Command template for all FCP Initiator commands */
2905typedef struct {
2906 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
2907 struct ulp_bde fcpi_rsp; /* Rcv buffer */
2908 uint32_t fcpi_parm;
2909 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
2910} FCPI_FIELDS;
2911
2912/* IOCB Command template for all FCP Target commands */
2913typedef struct {
2914 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
2915 uint32_t fcpt_Offset;
2916 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2917} FCPT_FIELDS;
2918
2919/* SLI-2 IOCB structure definitions */
2920
2921/* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
2922typedef struct {
2923 ULP_BDL bdl;
2924 uint32_t xrsqRo; /* Starting Relative Offset */
2925 WORD5 w5; /* Header control/status word */
2926} XMT_SEQ_FIELDS64;
2927
2928/* IOCB Command template for 64 bit RCV_SEQUENCE64 */
2929typedef struct {
2930 struct ulp_bde64 rcvBde;
2931 uint32_t rsvd1;
2932 uint32_t xrsqRo; /* Starting Relative Offset */
2933 WORD5 w5; /* Header control/status word */
2934} RCV_SEQ_FIELDS64;
2935
2936/* IOCB Command template for ELS_REQUEST64 */
2937typedef struct {
2938 ULP_BDL bdl;
2939#ifdef __BIG_ENDIAN_BITFIELD
2940 uint32_t word4Rsvd:7;
2941 uint32_t fl:1;
2942 uint32_t myID:24;
2943 uint32_t word5Rsvd:8;
2944 uint32_t remoteID:24;
2945#else /* __LITTLE_ENDIAN_BITFIELD */
2946 uint32_t myID:24;
2947 uint32_t fl:1;
2948 uint32_t word4Rsvd:7;
2949 uint32_t remoteID:24;
2950 uint32_t word5Rsvd:8;
2951#endif
2952} ELS_REQUEST64;
2953
2954/* IOCB Command template for GEN_REQUEST64 */
2955typedef struct {
2956 ULP_BDL bdl;
2957 uint32_t xrsqRo; /* Starting Relative Offset */
2958 WORD5 w5; /* Header control/status word */
2959} GEN_REQUEST64;
2960
2961/* IOCB Command template for RCV_ELS_REQ64 */
2962typedef struct {
2963 struct ulp_bde64 elsReq;
2964 uint32_t rcvd1;
2965 uint32_t parmRo;
2966
2967#ifdef __BIG_ENDIAN_BITFIELD
2968 uint32_t word5Rsvd:8;
2969 uint32_t remoteID:24;
2970#else /* __LITTLE_ENDIAN_BITFIELD */
2971 uint32_t remoteID:24;
2972 uint32_t word5Rsvd:8;
2973#endif
2974} RCV_ELS_REQ64;
2975
2976/* IOCB Command template for all 64 bit FCP Initiator commands */
2977typedef struct {
2978 ULP_BDL bdl;
2979 uint32_t fcpi_parm;
2980 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
2981} FCPI_FIELDS64;
2982
2983/* IOCB Command template for all 64 bit FCP Target commands */
2984typedef struct {
2985 ULP_BDL bdl;
2986 uint32_t fcpt_Offset;
2987 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2988} FCPT_FIELDS64;
2989
ed957684
JS		 2990/* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
2991 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
2992
2993struct rcv_sli3 {
2994 uint32_t word8Rsvd;
2995#ifdef __BIG_ENDIAN_BITFIELD
2996 uint16_t vpi;
2997 uint16_t word9Rsvd;
2998#else /* __LITTLE_ENDIAN */
2999 uint16_t word9Rsvd;
3000 uint16_t vpi;
3001#endif
3002 uint32_t word10Rsvd;
3003 uint32_t acc_len; /* accumulated length */
3004 struct ulp_bde64 bde2;
3005};
3006
92d7f7b0
JS		 3007
3008
dea3101e 3009typedef struct _IOCB { /* IOCB structure */
3010 union {
3011 GENERIC_RSP grsp; /* Generic response */
3012 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
3013 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3014 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
3015 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
3016 A_MXRI64 amxri; /* abort multiple xri command overlay */
3017 GET_RPI getrpi; /* GET_RPI template */
3018 FCPI_FIELDS fcpi; /* FCP Initiator template */
3019 FCPT_FIELDS fcpt; /* FCP target template */
3020
3021 /* SLI-2 structures */
3022
ed957684
JS		 3023 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
3024 * bde_64s */
dea3101e 3025 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3026 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3027 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3028 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
3029 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
3030 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
3031
3032 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
3033 } un;
3034 union {
3035 struct {
3036#ifdef __BIG_ENDIAN_BITFIELD
3037 uint16_t ulpContext; /* High order bits word 6 */
3038 uint16_t ulpIoTag; /* Low order bits word 6 */
3039#else /* __LITTLE_ENDIAN_BITFIELD */
3040 uint16_t ulpIoTag; /* Low order bits word 6 */
3041 uint16_t ulpContext; /* High order bits word 6 */
3042#endif
3043 } t1;
3044 struct {
3045#ifdef __BIG_ENDIAN_BITFIELD
3046 uint16_t ulpContext; /* High order bits word 6 */
3047 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3048 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3049#else /* __LITTLE_ENDIAN_BITFIELD */
3050 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3051 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3052 uint16_t ulpContext; /* High order bits word 6 */
3053#endif
3054 } t2;
3055 } un1;
3056#define ulpContext un1.t1.ulpContext
3057#define ulpIoTag un1.t1.ulpIoTag
3058#define ulpIoTag0 un1.t2.ulpIoTag0
3059
3060#ifdef __BIG_ENDIAN_BITFIELD
3061 uint32_t ulpTimeout:8;
3062 uint32_t ulpXS:1;
3063 uint32_t ulpFCP2Rcvy:1;
3064 uint32_t ulpPU:2;
3065 uint32_t ulpIr:1;
3066 uint32_t ulpClass:3;
3067 uint32_t ulpCommand:8;
3068 uint32_t ulpStatus:4;
3069 uint32_t ulpBdeCount:2;
3070 uint32_t ulpLe:1;
3071 uint32_t ulpOwner:1; /* Low order bit word 7 */
3072#else /* __LITTLE_ENDIAN_BITFIELD */
3073 uint32_t ulpOwner:1; /* Low order bit word 7 */
3074 uint32_t ulpLe:1;
3075 uint32_t ulpBdeCount:2;
3076 uint32_t ulpStatus:4;
3077 uint32_t ulpCommand:8;
3078 uint32_t ulpClass:3;
3079 uint32_t ulpIr:1;
3080 uint32_t ulpPU:2;
3081 uint32_t ulpFCP2Rcvy:1;
3082 uint32_t ulpXS:1;
3083 uint32_t ulpTimeout:8;
3084#endif
92d7f7b0 3085
ed957684
JS		 3086 union {
3087 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3088 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3089 } unsli3;
3090
3091#define ulpCt_h ulpXS
3092#define ulpCt_l ulpFCP2Rcvy
dea3101e 3093
ed957684
JS		 3094#define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3095#define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
dea3101e 3096#define PARM_UNUSED 0 /* PU field (Word 4) not used */
3097#define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
3098#define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
92d7f7b0 3099#define PARM_NPIV_DID 3
dea3101e 3100#define CLASS1 0 /* Class 1 */
3101#define CLASS2 1 /* Class 2 */
3102#define CLASS3 2 /* Class 3 */
3103#define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
3104
3105#define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
3106#define IOSTAT_FCP_RSP_ERROR 0x1
3107#define IOSTAT_REMOTE_STOP 0x2
3108#define IOSTAT_LOCAL_REJECT 0x3
3109#define IOSTAT_NPORT_RJT 0x4
3110#define IOSTAT_FABRIC_RJT 0x5
3111#define IOSTAT_NPORT_BSY 0x6
3112#define IOSTAT_FABRIC_BSY 0x7
3113#define IOSTAT_INTERMED_RSP 0x8
3114#define IOSTAT_LS_RJT 0x9
3115#define IOSTAT_BA_RJT 0xA
3116#define IOSTAT_RSVD1 0xB
3117#define IOSTAT_RSVD2 0xC
3118#define IOSTAT_RSVD3 0xD
3119#define IOSTAT_RSVD4 0xE
92d7f7b0 3120#define IOSTAT_NEED_BUFFER 0xF
dea3101e 3121#define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
3122#define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
3123#define IOSTAT_CNT 0x11
3124
3125} IOCB_t;
3126
ed957684
JS		 3127/* Structure used for a single HBQ entry */
3128struct lpfc_hbq_entry {
3129 struct ulp_bde64 bde;
3130 uint32_t buffer_tag;
3131};
3132
dea3101e 3133
3134#define SLI1_SLIM_SIZE (4 * 1024)
3135
3136/* Up to 498 IOCBs will fit into 16k
3137 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3138 */
ed957684 3139#define SLI2_SLIM_SIZE (64 * 1024)
dea3101e 3140
3141/* Maximum IOCBs that will fit in SLI2 slim */
3142#define MAX_SLI2_IOCB 498
ed957684
JS		 3143#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3144 (sizeof(MAILBOX_t) + sizeof(PCB_t)))
3145
3146/* HBQ entries are 4 words each = 4k */
3147#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
3148 lpfc_sli_hbq_count())
dea3101e 3149
3150struct lpfc_sli2_slim {
3151 MAILBOX_t mbx;
3152 PCB_t pcb;
ed957684 3153 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
dea3101e 3154};
3155
2e0fef85
JS		 3156/*
3157 * This function checks PCI device to allow special handling for LC HBAs.
3158 *
3159 * Parameters:
3160 * device : struct pci_dev 's device field
3161 *
3162 * return 1 => TRUE
3163 * 0 => FALSE
3164 */
dea3101e 3165static inline int
3166lpfc_is_LC_HBA(unsigned short device)
3167{
3168 if ((device == PCI_DEVICE_ID_TFLY) ||
3169 (device == PCI_DEVICE_ID_PFLY) ||
3170 (device == PCI_DEVICE_ID_LP101) ||
3171 (device == PCI_DEVICE_ID_BMID) ||
3172 (device == PCI_DEVICE_ID_BSMB) ||
3173 (device == PCI_DEVICE_ID_ZMID) ||
3174 (device == PCI_DEVICE_ID_ZSMB) ||
3175 (device == PCI_DEVICE_ID_RFLY))
3176 return 1;
3177 else
3178 return 0;
3179}
858c9f6c
JS		 3180
3181/*
3182 * Determine if an IOCB failed because of a link event or firmware reset.
3183 */
3184
3185static inline int
3186lpfc_error_lost_link(IOCB_t *iocbp)
3187{
3188 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
3189 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
3190 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
3191 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
3192}
Linux kernel - Deliverables
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