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[SCSI] lpfc 8.3.22: Add support for PCI Adapter Failure
[deliverable/linux.git] / drivers / scsi / lpfc / lpfc_hw.h
CommitLineData
dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
4fede78f 4 * Copyright (C) 2004-2010 Emulex. All rights reserved. *
c44ce173 5 * EMULEX and SLI are trademarks of Emulex. *
dea3101e 6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC		 9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
dea3101e 19 *******************************************************************/
20
dea3101e 21#define FDMI_DID 0xfffffaU
22#define NameServer_DID 0xfffffcU
23#define SCR_DID 0xfffffdU
24#define Fabric_DID 0xfffffeU
25#define Bcast_DID 0xffffffU
26#define Mask_DID 0xffffffU
27#define CT_DID_MASK 0xffff00U
28#define Fabric_DID_MASK 0xfff000U
29#define WELL_KNOWN_DID_MASK 0xfffff0U
30
31#define PT2PT_LocalID 1
32#define PT2PT_RemoteID 2
33
34#define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35#define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36#define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */
37#define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
38
39#define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
40 0 */
41
42#define FCELSSIZE 1024 /* maximum ELS transfer size */
43
44#define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
a4bc3379 45#define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
dea3101e 46#define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47#define LPFC_FCP_NEXT_RING 3
48
49#define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
50#define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
a4bc3379
JS		 51#define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
52#define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
dea3101e 53#define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
54#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
55#define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
56#define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
57#define SLI2_IOCB_CMD_R3_ENTRIES 0
58#define SLI2_IOCB_RSP_R3_ENTRIES 0
59#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
61
ed957684
JS		 62#define SLI2_IOCB_CMD_SIZE 32
63#define SLI2_IOCB_RSP_SIZE 32
64#define SLI3_IOCB_CMD_SIZE 128
65#define SLI3_IOCB_RSP_SIZE 64
66
92d7f7b0 67
ddcc50f0
JS		 68/* vendor ID used in SCSI netlink calls */
69#define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
70
dea3101e 71/* Common Transport structures and definitions */
72
73union CtRevisionId {
74 /* Structure is in Big Endian format */
75 struct {
76 uint32_t Revision:8;
77 uint32_t InId:24;
78 } bits;
79 uint32_t word;
80};
81
82union CtCommandResponse {
83 /* Structure is in Big Endian format */
84 struct {
85 uint32_t CmdRsp:16;
86 uint32_t Size:16;
87 } bits;
88 uint32_t word;
89};
90
92d7f7b0
JS		 91#define FC4_FEATURE_INIT 0x2
92#define FC4_FEATURE_TARGET 0x1
93
dea3101e 94struct lpfc_sli_ct_request {
95 /* Structure is in Big Endian format */
96 union CtRevisionId RevisionId;
97 uint8_t FsType;
98 uint8_t FsSubType;
99 uint8_t Options;
100 uint8_t Rsrvd1;
101 union CtCommandResponse CommandResponse;
102 uint8_t Rsrvd2;
103 uint8_t ReasonCode;
104 uint8_t Explanation;
105 uint8_t VendorUnique;
106
107 union {
108 uint32_t PortID;
109 struct gid {
110 uint8_t PortType; /* for GID_PT requests */
111 uint8_t DomainScope;
112 uint8_t AreaScope;
113 uint8_t Fc4Type; /* for GID_FT requests */
114 } gid;
115 struct rft {
116 uint32_t PortId; /* For RFT_ID requests */
117
118#ifdef __BIG_ENDIAN_BITFIELD
119 uint32_t rsvd0:16;
120 uint32_t rsvd1:7;
121 uint32_t fcpReg:1; /* Type 8 */
122 uint32_t rsvd2:2;
123 uint32_t ipReg:1; /* Type 5 */
124 uint32_t rsvd3:5;
125#else /* __LITTLE_ENDIAN_BITFIELD */
126 uint32_t rsvd0:16;
127 uint32_t fcpReg:1; /* Type 8 */
128 uint32_t rsvd1:7;
129 uint32_t rsvd3:5;
130 uint32_t ipReg:1; /* Type 5 */
131 uint32_t rsvd2:2;
132#endif
133
134 uint32_t rsvd[7];
135 } rft;
136 struct rnn {
137 uint32_t PortId; /* For RNN_ID requests */
138 uint8_t wwnn[8];
139 } rnn;
140 struct rsnn { /* For RSNN_ID requests */
141 uint8_t wwnn[8];
142 uint8_t len;
143 uint8_t symbname[255];
144 } rsnn;
7ee5d43e
JS		 145 struct da_id { /* For DA_ID requests */
146 uint32_t port_id;
147 } da_id;
92d7f7b0
JS		 148 struct rspn { /* For RSPN_ID requests */
149 uint32_t PortId;
150 uint8_t len;
151 uint8_t symbname[255];
152 } rspn;
153 struct gff {
154 uint32_t PortId;
155 } gff;
156 struct gff_acc {
157 uint8_t fbits[128];
158 } gff_acc;
51ef4c26 159#define FCP_TYPE_FEATURE_OFFSET 7
92d7f7b0
JS		 160 struct rff {
161 uint32_t PortId;
162 uint8_t reserved[2];
163 uint8_t fbits;
164 uint8_t type_code; /* type=8 for FCP */
165 } rff;
dea3101e 166 } un;
167};
168
169#define SLI_CT_REVISION 1
92d7f7b0
JS		 170#define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
171 sizeof(struct gid))
172#define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
173 sizeof(struct gff))
174#define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
175 sizeof(struct rft))
176#define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
177 sizeof(struct rff))
178#define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
179 sizeof(struct rnn))
180#define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
181 sizeof(struct rsnn))
7ee5d43e
JS		 182#define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
183 sizeof(struct da_id))
92d7f7b0
JS		 184#define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
185 sizeof(struct rspn))
dea3101e 186
187/*
188 * FsType Definitions
189 */
190
191#define SLI_CT_MANAGEMENT_SERVICE 0xFA
192#define SLI_CT_TIME_SERVICE 0xFB
193#define SLI_CT_DIRECTORY_SERVICE 0xFC
194#define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
195
196/*
197 * Directory Service Subtypes
198 */
199
200#define SLI_CT_DIRECTORY_NAME_SERVER 0x02
201
202/*
203 * Response Codes
204 */
205
206#define SLI_CT_RESPONSE_FS_RJT 0x8001
207#define SLI_CT_RESPONSE_FS_ACC 0x8002
208
209/*
210 * Reason Codes
211 */
212
213#define SLI_CT_NO_ADDITIONAL_EXPL 0x0
214#define SLI_CT_INVALID_COMMAND 0x01
215#define SLI_CT_INVALID_VERSION 0x02
216#define SLI_CT_LOGICAL_ERROR 0x03
217#define SLI_CT_INVALID_IU_SIZE 0x04
218#define SLI_CT_LOGICAL_BUSY 0x05
219#define SLI_CT_PROTOCOL_ERROR 0x07
220#define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
221#define SLI_CT_REQ_NOT_SUPPORTED 0x0b
222#define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
223#define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
224#define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
225#define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
226#define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
227#define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
228#define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
229#define SLI_CT_VENDOR_UNIQUE 0xff
230
231/*
232 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
233 */
234
235#define SLI_CT_NO_PORT_ID 0x01
236#define SLI_CT_NO_PORT_NAME 0x02
237#define SLI_CT_NO_NODE_NAME 0x03
238#define SLI_CT_NO_CLASS_OF_SERVICE 0x04
239#define SLI_CT_NO_IP_ADDRESS 0x05
240#define SLI_CT_NO_IPA 0x06
241#define SLI_CT_NO_FC4_TYPES 0x07
242#define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
243#define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
244#define SLI_CT_NO_PORT_TYPE 0x0A
245#define SLI_CT_ACCESS_DENIED 0x10
246#define SLI_CT_INVALID_PORT_ID 0x11
247#define SLI_CT_DATABASE_EMPTY 0x12
248
249/*
250 * Name Server Command Codes
251 */
252
253#define SLI_CTNS_GA_NXT 0x0100
254#define SLI_CTNS_GPN_ID 0x0112
255#define SLI_CTNS_GNN_ID 0x0113
256#define SLI_CTNS_GCS_ID 0x0114
257#define SLI_CTNS_GFT_ID 0x0117
258#define SLI_CTNS_GSPN_ID 0x0118
259#define SLI_CTNS_GPT_ID 0x011A
92d7f7b0 260#define SLI_CTNS_GFF_ID 0x011F
dea3101e 261#define SLI_CTNS_GID_PN 0x0121
262#define SLI_CTNS_GID_NN 0x0131
263#define SLI_CTNS_GIP_NN 0x0135
264#define SLI_CTNS_GIPA_NN 0x0136
265#define SLI_CTNS_GSNN_NN 0x0139
266#define SLI_CTNS_GNN_IP 0x0153
267#define SLI_CTNS_GIPA_IP 0x0156
268#define SLI_CTNS_GID_FT 0x0171
269#define SLI_CTNS_GID_PT 0x01A1
270#define SLI_CTNS_RPN_ID 0x0212
271#define SLI_CTNS_RNN_ID 0x0213
272#define SLI_CTNS_RCS_ID 0x0214
273#define SLI_CTNS_RFT_ID 0x0217
274#define SLI_CTNS_RSPN_ID 0x0218
275#define SLI_CTNS_RPT_ID 0x021A
92d7f7b0 276#define SLI_CTNS_RFF_ID 0x021F
dea3101e 277#define SLI_CTNS_RIP_NN 0x0235
278#define SLI_CTNS_RIPA_NN 0x0236
279#define SLI_CTNS_RSNN_NN 0x0239
280#define SLI_CTNS_DA_ID 0x0300
281
282/*
283 * Port Types
284 */
285
286#define SLI_CTPT_N_PORT 0x01
287#define SLI_CTPT_NL_PORT 0x02
288#define SLI_CTPT_FNL_PORT 0x03
289#define SLI_CTPT_IP 0x04
290#define SLI_CTPT_FCP 0x08
291#define SLI_CTPT_NX_PORT 0x7F
292#define SLI_CTPT_F_PORT 0x81
293#define SLI_CTPT_FL_PORT 0x82
294#define SLI_CTPT_E_PORT 0x84
295
296#define SLI_CT_LAST_ENTRY 0x80000000
297
298/* Fibre Channel Service Parameter definitions */
299
300#define FC_PH_4_0 6 /* FC-PH version 4.0 */
301#define FC_PH_4_1 7 /* FC-PH version 4.1 */
302#define FC_PH_4_2 8 /* FC-PH version 4.2 */
303#define FC_PH_4_3 9 /* FC-PH version 4.3 */
304
305#define FC_PH_LOW 8 /* Lowest supported FC-PH version */
306#define FC_PH_HIGH 9 /* Highest supported FC-PH version */
307#define FC_PH3 0x20 /* FC-PH-3 version */
308
309#define FF_FRAME_SIZE 2048
310
311struct lpfc_name {
f631b4be
AV		 312 union {
313 struct {
dea3101e 314#ifdef __BIG_ENDIAN_BITFIELD
f631b4be 315 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
1de933f3
JSEC		 316 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
317 8:11 of IEEE ext */
dea3101e 318#else /* __LITTLE_ENDIAN_BITFIELD */
1de933f3
JSEC		 319 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
320 8:11 of IEEE ext */
f631b4be 321 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
dea3101e 322#endif
323
324#define NAME_IEEE 0x1 /* IEEE name - nameType */
325#define NAME_IEEE_EXT 0x2 /* IEEE extended name */
326#define NAME_FC_TYPE 0x3 /* FC native name type */
327#define NAME_IP_TYPE 0x4 /* IP address */
328#define NAME_CCITT_TYPE 0xC
329#define NAME_CCITT_GR_TYPE 0xE
1de933f3
JSEC		 330 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
331 extended Lsb */
f631b4be 332 uint8_t IEEE[6]; /* FC IEEE address */
68ce1eb5 333 } s;
f631b4be 334 uint8_t wwn[8];
68ce1eb5 335 } u;
dea3101e 336};
337
338struct csp {
339 uint8_t fcphHigh; /* FC Word 0, byte 0 */
340 uint8_t fcphLow;
341 uint8_t bbCreditMsb;
342 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
343
92494144
JS		 344/*
345 * Word 1 Bit 31 in common service parameter is overloaded.
346 * Word 1 Bit 31 in FLOGI request is multiple NPort request
347 * Word 1 Bit 31 in FLOGI response is clean address bit
348 */
349#define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
dea3101e 350#ifdef __BIG_ENDIAN_BITFIELD
92d7f7b0
JS		 351 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
352 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
353 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
dea3101e 354 uint16_t fPort:1; /* FC Word 1, bit 28 */
355 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
356 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
357 uint16_t multicast:1; /* FC Word 1, bit 25 */
358 uint16_t broadcast:1; /* FC Word 1, bit 24 */
359
360 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
361 uint16_t simplex:1; /* FC Word 1, bit 22 */
362 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
363 uint16_t dhd:1; /* FC Word 1, bit 18 */
364 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
365 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
366#else /* __LITTLE_ENDIAN_BITFIELD */
367 uint16_t broadcast:1; /* FC Word 1, bit 24 */
368 uint16_t multicast:1; /* FC Word 1, bit 25 */
369 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
370 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
371 uint16_t fPort:1; /* FC Word 1, bit 28 */
92d7f7b0 372 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
dea3101e 373 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
92d7f7b0 374 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
dea3101e 375
376 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
377 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
378 uint16_t dhd:1; /* FC Word 1, bit 18 */
379 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
380 uint16_t simplex:1; /* FC Word 1, bit 22 */
381 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
382#endif
383
384 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
385 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
386 union {
387 struct {
388 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
389
390 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
391 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
392
393 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
394 } nPort;
395 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
396 } w2;
397
398 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
399};
400
401struct class_parms {
402#ifdef __BIG_ENDIAN_BITFIELD
403 uint8_t classValid:1; /* FC Word 0, bit 31 */
404 uint8_t intermix:1; /* FC Word 0, bit 30 */
405 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
406 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
407 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
408 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
409#else /* __LITTLE_ENDIAN_BITFIELD */
410 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
411 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
412 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
413 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
414 uint8_t intermix:1; /* FC Word 0, bit 30 */
415 uint8_t classValid:1; /* FC Word 0, bit 31 */
416
417#endif
418
419 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
420
421#ifdef __BIG_ENDIAN_BITFIELD
422 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
423 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
424 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
425 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
426 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
427#else /* __LITTLE_ENDIAN_BITFIELD */
428 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
429 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
430 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
431 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
432 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
433#endif
434
435 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
436
437#ifdef __BIG_ENDIAN_BITFIELD
438 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
439 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
440 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
441 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
442 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
443 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
444#else /* __LITTLE_ENDIAN_BITFIELD */
445 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
446 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
447 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
448 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
449 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
450 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
451#endif
452
453 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
454 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
455 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
456
457 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
458 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
459 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
460 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
461
462 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
463 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
464 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
465 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
466};
467
468struct serv_parm { /* Structure is in Big Endian format */
469 struct csp cmn;
470 struct lpfc_name portName;
471 struct lpfc_name nodeName;
472 struct class_parms cls1;
473 struct class_parms cls2;
474 struct class_parms cls3;
475 struct class_parms cls4;
476 uint8_t vendorVersion[16];
477};
478
da0436e9
JS		 479/*
480 * Virtual Fabric Tagging Header
481 */
482struct fc_vft_header {
483 uint32_t word0;
484#define fc_vft_hdr_r_ctl_SHIFT 24
485#define fc_vft_hdr_r_ctl_MASK 0xFF
486#define fc_vft_hdr_r_ctl_WORD word0
487#define fc_vft_hdr_ver_SHIFT 22
488#define fc_vft_hdr_ver_MASK 0x3
489#define fc_vft_hdr_ver_WORD word0
490#define fc_vft_hdr_type_SHIFT 18
491#define fc_vft_hdr_type_MASK 0xF
492#define fc_vft_hdr_type_WORD word0
493#define fc_vft_hdr_e_SHIFT 16
494#define fc_vft_hdr_e_MASK 0x1
495#define fc_vft_hdr_e_WORD word0
496#define fc_vft_hdr_priority_SHIFT 13
497#define fc_vft_hdr_priority_MASK 0x7
498#define fc_vft_hdr_priority_WORD word0
499#define fc_vft_hdr_vf_id_SHIFT 1
500#define fc_vft_hdr_vf_id_MASK 0xFFF
501#define fc_vft_hdr_vf_id_WORD word0
502 uint32_t word1;
503#define fc_vft_hdr_hopct_SHIFT 24
504#define fc_vft_hdr_hopct_MASK 0xFF
505#define fc_vft_hdr_hopct_WORD word1
506};
507
dea3101e 508/*
509 * Extended Link Service LS_COMMAND codes (Payload Word 0)
510 */
511#ifdef __BIG_ENDIAN_BITFIELD
512#define ELS_CMD_MASK 0xffff0000
513#define ELS_RSP_MASK 0xff000000
514#define ELS_CMD_LS_RJT 0x01000000
515#define ELS_CMD_ACC 0x02000000
516#define ELS_CMD_PLOGI 0x03000000
517#define ELS_CMD_FLOGI 0x04000000
518#define ELS_CMD_LOGO 0x05000000
519#define ELS_CMD_ABTX 0x06000000
520#define ELS_CMD_RCS 0x07000000
521#define ELS_CMD_RES 0x08000000
522#define ELS_CMD_RSS 0x09000000
523#define ELS_CMD_RSI 0x0A000000
524#define ELS_CMD_ESTS 0x0B000000
525#define ELS_CMD_ESTC 0x0C000000
526#define ELS_CMD_ADVC 0x0D000000
527#define ELS_CMD_RTV 0x0E000000
528#define ELS_CMD_RLS 0x0F000000
529#define ELS_CMD_ECHO 0x10000000
530#define ELS_CMD_TEST 0x11000000
531#define ELS_CMD_RRQ 0x12000000
532#define ELS_CMD_PRLI 0x20100014
533#define ELS_CMD_PRLO 0x21100014
82d9a2a2 534#define ELS_CMD_PRLO_ACC 0x02100014
dea3101e 535#define ELS_CMD_PDISC 0x50000000
536#define ELS_CMD_FDISC 0x51000000
537#define ELS_CMD_ADISC 0x52000000
538#define ELS_CMD_FARP 0x54000000
539#define ELS_CMD_FARPR 0x55000000
7bb3b137
JW		 540#define ELS_CMD_RPS 0x56000000
541#define ELS_CMD_RPL 0x57000000
dea3101e 542#define ELS_CMD_FAN 0x60000000
543#define ELS_CMD_RSCN 0x61040000
544#define ELS_CMD_SCR 0x62000000
545#define ELS_CMD_RNID 0x78000000
7bb3b137 546#define ELS_CMD_LIRR 0x7A000000
dea3101e 547#else /* __LITTLE_ENDIAN_BITFIELD */
548#define ELS_CMD_MASK 0xffff
549#define ELS_RSP_MASK 0xff
550#define ELS_CMD_LS_RJT 0x01
551#define ELS_CMD_ACC 0x02
552#define ELS_CMD_PLOGI 0x03
553#define ELS_CMD_FLOGI 0x04
554#define ELS_CMD_LOGO 0x05
555#define ELS_CMD_ABTX 0x06
556#define ELS_CMD_RCS 0x07
557#define ELS_CMD_RES 0x08
558#define ELS_CMD_RSS 0x09
559#define ELS_CMD_RSI 0x0A
560#define ELS_CMD_ESTS 0x0B
561#define ELS_CMD_ESTC 0x0C
562#define ELS_CMD_ADVC 0x0D
563#define ELS_CMD_RTV 0x0E
564#define ELS_CMD_RLS 0x0F
565#define ELS_CMD_ECHO 0x10
566#define ELS_CMD_TEST 0x11
567#define ELS_CMD_RRQ 0x12
568#define ELS_CMD_PRLI 0x14001020
569#define ELS_CMD_PRLO 0x14001021
82d9a2a2 570#define ELS_CMD_PRLO_ACC 0x14001002
dea3101e 571#define ELS_CMD_PDISC 0x50
572#define ELS_CMD_FDISC 0x51
573#define ELS_CMD_ADISC 0x52
574#define ELS_CMD_FARP 0x54
575#define ELS_CMD_FARPR 0x55
7bb3b137
JW		 576#define ELS_CMD_RPS 0x56
577#define ELS_CMD_RPL 0x57
dea3101e 578#define ELS_CMD_FAN 0x60
579#define ELS_CMD_RSCN 0x0461
580#define ELS_CMD_SCR 0x62
581#define ELS_CMD_RNID 0x78
7bb3b137 582#define ELS_CMD_LIRR 0x7A
dea3101e 583#endif
584
585/*
586 * LS_RJT Payload Definition
587 */
588
589struct ls_rjt { /* Structure is in Big Endian format */
590 union {
591 uint32_t lsRjtError;
592 struct {
593 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
594
595 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
596 /* LS_RJT reason codes */
597#define LSRJT_INVALID_CMD 0x01
598#define LSRJT_LOGICAL_ERR 0x03
599#define LSRJT_LOGICAL_BSY 0x05
600#define LSRJT_PROTOCOL_ERR 0x07
601#define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
602#define LSRJT_CMD_UNSUPPORTED 0x0B
603#define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
604
605 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
606 /* LS_RJT reason explanation */
607#define LSEXP_NOTHING_MORE 0x00
608#define LSEXP_SPARM_OPTIONS 0x01
609#define LSEXP_SPARM_ICTL 0x03
610#define LSEXP_SPARM_RCTL 0x05
611#define LSEXP_SPARM_RCV_SIZE 0x07
612#define LSEXP_SPARM_CONCUR_SEQ 0x09
613#define LSEXP_SPARM_CREDIT 0x0B
614#define LSEXP_INVALID_PNAME 0x0D
615#define LSEXP_INVALID_NNAME 0x0E
616#define LSEXP_INVALID_CSP 0x0F
617#define LSEXP_INVALID_ASSOC_HDR 0x11
618#define LSEXP_ASSOC_HDR_REQ 0x13
619#define LSEXP_INVALID_O_SID 0x15
620#define LSEXP_INVALID_OX_RX 0x17
621#define LSEXP_CMD_IN_PROGRESS 0x19
7f5f3d0d 622#define LSEXP_PORT_LOGIN_REQ 0x1E
dea3101e 623#define LSEXP_INVALID_NPORT_ID 0x1F
624#define LSEXP_INVALID_SEQ_ID 0x21
625#define LSEXP_INVALID_XCHG 0x23
626#define LSEXP_INACTIVE_XCHG 0x25
627#define LSEXP_RQ_REQUIRED 0x27
628#define LSEXP_OUT_OF_RESOURCE 0x29
629#define LSEXP_CANT_GIVE_DATA 0x2A
630#define LSEXP_REQ_UNSUPPORTED 0x2C
631 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
632 } b;
633 } un;
634};
635
636/*
637 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
638 */
639
640typedef struct _LOGO { /* Structure is in Big Endian format */
641 union {
642 uint32_t nPortId32; /* Access nPortId as a word */
643 struct {
644 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
645 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
646 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
647 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
648 } b;
649 } un;
650 struct lpfc_name portName; /* N_port name field */
651} LOGO;
652
653/*
654 * FCP Login (PRLI Request / ACC) Payload Definition
655 */
656
657#define PRLX_PAGE_LEN 0x10
658#define TPRLO_PAGE_LEN 0x14
659
660typedef struct _PRLI { /* Structure is in Big Endian format */
661 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
662
663#define PRLI_FCP_TYPE 0x08
664 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
665
666#ifdef __BIG_ENDIAN_BITFIELD
667 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
668 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
669 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
670
671 /* ACC = imagePairEstablished */
672 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
673 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
674#else /* __LITTLE_ENDIAN_BITFIELD */
675 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
676 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
677 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
678 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
679 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
680 /* ACC = imagePairEstablished */
681#endif
682
683#define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
684#define PRLI_NO_RESOURCES 0x2
685#define PRLI_INIT_INCOMPLETE 0x3
686#define PRLI_NO_SUCH_PA 0x4
687#define PRLI_PREDEF_CONFIG 0x5
688#define PRLI_PARTIAL_SUCCESS 0x6
689#define PRLI_INVALID_PAGE_CNT 0x7
690 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
691
692 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
693
694 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
695
696 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
697 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
698
699#ifdef __BIG_ENDIAN_BITFIELD
700 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
701 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
702 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
703 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
704 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
705 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
706 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
707 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
708 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
709 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
710 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
711 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
712 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
713 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
714 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
715 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
716#else /* __LITTLE_ENDIAN_BITFIELD */
717 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
718 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
719 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
720 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
721 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
722 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
723 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
724 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
725 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
726 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
727 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
728 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
729 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
730 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
731 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
732 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
733#endif
734} PRLI;
735
736/*
737 * FCP Logout (PRLO Request / ACC) Payload Definition
738 */
739
740typedef struct _PRLO { /* Structure is in Big Endian format */
741 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
742
743#define PRLO_FCP_TYPE 0x08
744 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
745
746#ifdef __BIG_ENDIAN_BITFIELD
747 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
748 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
749 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
750 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
751#else /* __LITTLE_ENDIAN_BITFIELD */
752 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
753 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
754 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
755 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
756#endif
757
758#define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
759#define PRLO_NO_SUCH_IMAGE 0x4
760#define PRLO_INVALID_PAGE_CNT 0x7
761
762 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
763
764 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
765
766 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
767
768 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
769} PRLO;
770
771typedef struct _ADISC { /* Structure is in Big Endian format */
772 uint32_t hardAL_PA;
773 struct lpfc_name portName;
774 struct lpfc_name nodeName;
775 uint32_t DID;
776} ADISC;
777
778typedef struct _FARP { /* Structure is in Big Endian format */
779 uint32_t Mflags:8;
780 uint32_t Odid:24;
781#define FARP_NO_ACTION 0 /* FARP information enclosed, no
782 action */
783#define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
784#define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
785#define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
786#define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
787 supported */
788#define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
789 supported */
790 uint32_t Rflags:8;
791 uint32_t Rdid:24;
792#define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
793#define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
794 struct lpfc_name OportName;
795 struct lpfc_name OnodeName;
796 struct lpfc_name RportName;
797 struct lpfc_name RnodeName;
798 uint8_t Oipaddr[16];
799 uint8_t Ripaddr[16];
800} FARP;
801
802typedef struct _FAN { /* Structure is in Big Endian format */
803 uint32_t Fdid;
804 struct lpfc_name FportName;
805 struct lpfc_name FnodeName;
806} FAN;
807
808typedef struct _SCR { /* Structure is in Big Endian format */
809 uint8_t resvd1;
810 uint8_t resvd2;
811 uint8_t resvd3;
812 uint8_t Function;
813#define SCR_FUNC_FABRIC 0x01
814#define SCR_FUNC_NPORT 0x02
815#define SCR_FUNC_FULL 0x03
816#define SCR_CLEAR 0xff
817} SCR;
818
819typedef struct _RNID_TOP_DISC {
820 struct lpfc_name portName;
821 uint8_t resvd[8];
822 uint32_t unitType;
823#define RNID_HBA 0x7
824#define RNID_HOST 0xa
825#define RNID_DRIVER 0xd
826 uint32_t physPort;
827 uint32_t attachedNodes;
828 uint16_t ipVersion;
829#define RNID_IPV4 0x1
830#define RNID_IPV6 0x2
831 uint16_t UDPport;
832 uint8_t ipAddr[16];
833 uint16_t resvd1;
834 uint16_t flags;
835#define RNID_TD_SUPPORT 0x1
836#define RNID_LP_VALID 0x2
837} RNID_TOP_DISC;
838
839typedef struct _RNID { /* Structure is in Big Endian format */
840 uint8_t Format;
841#define RNID_TOPOLOGY_DISC 0xdf
842 uint8_t CommonLen;
843 uint8_t resvd1;
844 uint8_t SpecificLen;
845 struct lpfc_name portName;
846 struct lpfc_name nodeName;
847 union {
848 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
849 } un;
850} RNID;
851
311464ec 852typedef struct _RPS { /* Structure is in Big Endian format */
7bb3b137
JW		 853 union {
854 uint32_t portNum;
855 struct lpfc_name portName;
856 } un;
857} RPS;
858
859typedef struct _RPS_RSP { /* Structure is in Big Endian format */
860 uint16_t rsvd1;
861 uint16_t portStatus;
862 uint32_t linkFailureCnt;
863 uint32_t lossSyncCnt;
864 uint32_t lossSignalCnt;
865 uint32_t primSeqErrCnt;
866 uint32_t invalidXmitWord;
867 uint32_t crcCnt;
868} RPS_RSP;
869
12265f68
JS		 870struct RLS { /* Structure is in Big Endian format */
871 uint32_t rls;
872#define rls_rsvd_SHIFT 24
873#define rls_rsvd_MASK 0x000000ff
874#define rls_rsvd_WORD rls
875#define rls_did_SHIFT 0
876#define rls_did_MASK 0x00ffffff
877#define rls_did_WORD rls
878};
879
880struct RLS_RSP { /* Structure is in Big Endian format */
881 uint32_t linkFailureCnt;
882 uint32_t lossSyncCnt;
883 uint32_t lossSignalCnt;
884 uint32_t primSeqErrCnt;
885 uint32_t invalidXmitWord;
886 uint32_t crcCnt;
887};
888
19ca7609
JS		 889struct RRQ { /* Structure is in Big Endian format */
890 uint32_t rrq;
891#define rrq_rsvd_SHIFT 24
892#define rrq_rsvd_MASK 0x000000ff
893#define rrq_rsvd_WORD rrq
894#define rrq_did_SHIFT 0
895#define rrq_did_MASK 0x00ffffff
896#define rrq_did_WORD rrq
897 uint32_t rrq_exchg;
898#define rrq_oxid_SHIFT 16
899#define rrq_oxid_MASK 0xffff
900#define rrq_oxid_WORD rrq_exchg
901#define rrq_rxid_SHIFT 0
902#define rrq_rxid_MASK 0xffff
903#define rrq_rxid_WORD rrq_exchg
904};
905
906
12265f68
JS		 907struct RTV_RSP { /* Structure is in Big Endian format */
908 uint32_t ratov;
909 uint32_t edtov;
910 uint32_t qtov;
911#define qtov_rsvd0_SHIFT 28
912#define qtov_rsvd0_MASK 0x0000000f
913#define qtov_rsvd0_WORD qtov /* reserved */
914#define qtov_edtovres_SHIFT 27
915#define qtov_edtovres_MASK 0x00000001
916#define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
917#define qtov__rsvd1_SHIFT 19
918#define qtov_rsvd1_MASK 0x0000003f
919#define qtov_rsvd1_WORD qtov /* reserved */
920#define qtov_rttov_SHIFT 18
921#define qtov_rttov_MASK 0x00000001
922#define qtov_rttov_WORD qtov /* R_T_TOV value */
923#define qtov_rsvd2_SHIFT 0
924#define qtov_rsvd2_MASK 0x0003ffff
925#define qtov_rsvd2_WORD qtov /* reserved */
926};
927
928
311464ec 929typedef struct _RPL { /* Structure is in Big Endian format */
7bb3b137
JW		 930 uint32_t maxsize;
931 uint32_t index;
932} RPL;
933
934typedef struct _PORT_NUM_BLK {
935 uint32_t portNum;
936 uint32_t portID;
937 struct lpfc_name portName;
938} PORT_NUM_BLK;
939
311464ec 940typedef struct _RPL_RSP { /* Structure is in Big Endian format */
7bb3b137
JW		 941 uint32_t listLen;
942 uint32_t index;
943 PORT_NUM_BLK port_num_blk;
944} RPL_RSP;
dea3101e 945
946/* This is used for RSCN command */
947typedef struct _D_ID { /* Structure is in Big Endian format */
948 union {
949 uint32_t word;
950 struct {
951#ifdef __BIG_ENDIAN_BITFIELD
952 uint8_t resv;
953 uint8_t domain;
954 uint8_t area;
955 uint8_t id;
956#else /* __LITTLE_ENDIAN_BITFIELD */
957 uint8_t id;
958 uint8_t area;
959 uint8_t domain;
960 uint8_t resv;
961#endif
962 } b;
963 } un;
964} D_ID;
965
eaf15d5b
JS		 966#define RSCN_ADDRESS_FORMAT_PORT 0x0
967#define RSCN_ADDRESS_FORMAT_AREA 0x1
968#define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
969#define RSCN_ADDRESS_FORMAT_FABRIC 0x3
970#define RSCN_ADDRESS_FORMAT_MASK 0x3
971
dea3101e 972/*
973 * Structure to define all ELS Payload types
974 */
975
976typedef struct _ELS_PKT { /* Structure is in Big Endian format */
977 uint8_t elsCode; /* FC Word 0, bit 24:31 */
978 uint8_t elsByte1;
979 uint8_t elsByte2;
980 uint8_t elsByte3;
981 union {
982 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
983 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
984 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
985 PRLI prli; /* Payload for PRLI/ACC */
986 PRLO prlo; /* Payload for PRLO/ACC */
987 ADISC adisc; /* Payload for ADISC/ACC */
988 FARP farp; /* Payload for FARP/ACC */
989 FAN fan; /* Payload for FAN */
990 SCR scr; /* Payload for SCR/ACC */
dea3101e 991 RNID rnid; /* Payload for RNID */
992 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
993 } un;
994} ELS_PKT;
995
996/*
997 * FDMI
998 * HBA MAnagement Operations Command Codes
999 */
1000#define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1001#define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1002#define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1003#define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1004#define SLI_MGMT_RHBA 0x200 /* Register HBA */
1005#define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */
1006#define SLI_MGMT_RPRT 0x210 /* Register Port */
1007#define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1008#define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1009#define SLI_MGMT_DPRT 0x310 /* De-register Port */
1010
1011/*
1012 * Management Service Subtypes
1013 */
1014#define SLI_CT_FDMI_Subtypes 0x10
1015
1016/*
1017 * HBA Management Service Reject Code
1018 */
1019#define REJECT_CODE 0x9 /* Unable to perform command request */
1020
1021/*
1022 * HBA Management Service Reject Reason Code
1023 * Please refer to the Reason Codes above
1024 */
1025
1026/*
1027 * HBA Attribute Types
1028 */
1029#define NODE_NAME 0x1
1030#define MANUFACTURER 0x2
1031#define SERIAL_NUMBER 0x3
1032#define MODEL 0x4
1033#define MODEL_DESCRIPTION 0x5
1034#define HARDWARE_VERSION 0x6
1035#define DRIVER_VERSION 0x7
1036#define OPTION_ROM_VERSION 0x8
1037#define FIRMWARE_VERSION 0x9
1038#define OS_NAME_VERSION 0xa
1039#define MAX_CT_PAYLOAD_LEN 0xb
1040
1041/*
1042 * Port Attrubute Types
1043 */
1044#define SUPPORTED_FC4_TYPES 0x1
1045#define SUPPORTED_SPEED 0x2
1046#define PORT_SPEED 0x3
1047#define MAX_FRAME_SIZE 0x4
1048#define OS_DEVICE_NAME 0x5
1049#define HOST_NAME 0x6
1050
1051union AttributesDef {
1052 /* Structure is in Big Endian format */
1053 struct {
1054 uint32_t AttrType:16;
1055 uint32_t AttrLen:16;
1056 } bits;
1057 uint32_t word;
1058};
1059
1060
1061/*
1062 * HBA Attribute Entry (8 - 260 bytes)
1063 */
1064typedef struct {
1065 union AttributesDef ad;
1066 union {
1067 uint32_t VendorSpecific;
1068 uint8_t Manufacturer[64];
1069 uint8_t SerialNumber[64];
1070 uint8_t Model[256];
1071 uint8_t ModelDescription[256];
1072 uint8_t HardwareVersion[256];
1073 uint8_t DriverVersion[256];
1074 uint8_t OptionROMVersion[256];
1075 uint8_t FirmwareVersion[256];
1076 struct lpfc_name NodeName;
1077 uint8_t SupportFC4Types[32];
1078 uint32_t SupportSpeed;
1079 uint32_t PortSpeed;
1080 uint32_t MaxFrameSize;
1081 uint8_t OsDeviceName[256];
1082 uint8_t OsNameVersion[256];
1083 uint32_t MaxCTPayloadLen;
1084 uint8_t HostName[256];
1085 } un;
1086} ATTRIBUTE_ENTRY;
1087
1088/*
1089 * HBA Attribute Block
1090 */
1091typedef struct {
1092 uint32_t EntryCnt; /* Number of HBA attribute entries */
1093 ATTRIBUTE_ENTRY Entry; /* Variable-length array */
1094} ATTRIBUTE_BLOCK;
1095
1096/*
1097 * Port Entry
1098 */
1099typedef struct {
1100 struct lpfc_name PortName;
1101} PORT_ENTRY;
1102
1103/*
1104 * HBA Identifier
1105 */
1106typedef struct {
1107 struct lpfc_name PortName;
1108} HBA_IDENTIFIER;
1109
1110/*
1111 * Registered Port List Format
1112 */
1113typedef struct {
1114 uint32_t EntryCnt;
1115 PORT_ENTRY pe; /* Variable-length array */
1116} REG_PORT_LIST;
1117
1118/*
1119 * Register HBA(RHBA)
1120 */
1121typedef struct {
1122 HBA_IDENTIFIER hi;
1123 REG_PORT_LIST rpl; /* variable-length array */
1124/* ATTRIBUTE_BLOCK ab; */
1125} REG_HBA;
1126
1127/*
1128 * Register HBA Attributes (RHAT)
1129 */
1130typedef struct {
1131 struct lpfc_name HBA_PortName;
1132 ATTRIBUTE_BLOCK ab;
1133} REG_HBA_ATTRIBUTE;
1134
1135/*
1136 * Register Port Attributes (RPA)
1137 */
1138typedef struct {
1139 struct lpfc_name PortName;
1140 ATTRIBUTE_BLOCK ab;
1141} REG_PORT_ATTRIBUTE;
1142
1143/*
1144 * Get Registered HBA List (GRHL) Accept Payload Format
1145 */
1146typedef struct {
1147 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1148 struct lpfc_name HBA_PortName; /* Variable-length array */
1149} GRHL_ACC_PAYLOAD;
1150
1151/*
1152 * Get Registered Port List (GRPL) Accept Payload Format
1153 */
1154typedef struct {
1155 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1156 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */
1157} GRPL_ACC_PAYLOAD;
1158
1159/*
1160 * Get Port Attributes (GPAT) Accept Payload Format
1161 */
1162
1163typedef struct {
1164 ATTRIBUTE_BLOCK pab;
1165} GPAT_ACC_PAYLOAD;
1166
1167
1168/*
1169 * Begin HBA configuration parameters.
1170 * The PCI configuration register BAR assignments are:
1171 * BAR0, offset 0x10 - SLIM base memory address
1172 * BAR1, offset 0x14 - SLIM base memory high address
1173 * BAR2, offset 0x18 - REGISTER base memory address
1174 * BAR3, offset 0x1c - REGISTER base memory high address
1175 * BAR4, offset 0x20 - BIU I/O registers
1176 * BAR5, offset 0x24 - REGISTER base io high address
1177 */
1178
1179/* Number of rings currently used and available. */
1180#define MAX_CONFIGURED_RINGS 3
1181#define MAX_RINGS 4
1182
1183/* IOCB / Mailbox is owned by FireFly */
1184#define OWN_CHIP 1
1185
1186/* IOCB / Mailbox is owned by Host */
1187#define OWN_HOST 0
1188
1189/* Number of 4-byte words in an IOCB. */
1190#define IOCB_WORD_SZ 8
1191
dea3101e 1192/* network headers for Dfctl field */
1193#define FC_NET_HDR 0x20
1194
1195/* Start FireFly Register definitions */
1196#define PCI_VENDOR_ID_EMULEX 0x10df
1197#define PCI_DEVICE_ID_FIREFLY 0x1ae5
84774a4d 1198#define PCI_DEVICE_ID_PROTEUS_VF 0xe100
085c647c 1199#define PCI_DEVICE_ID_BALIUS 0xe131
84774a4d 1200#define PCI_DEVICE_ID_PROTEUS_PF 0xe180
085c647c
JS		 1201#define PCI_DEVICE_ID_LANCER_FC 0xe200
1202#define PCI_DEVICE_ID_LANCER_FCOE 0xe260
b87eab38
JS		 1203#define PCI_DEVICE_ID_SAT_SMB 0xf011
1204#define PCI_DEVICE_ID_SAT_MID 0xf015
dea3101e 1205#define PCI_DEVICE_ID_RFLY 0xf095
1206#define PCI_DEVICE_ID_PFLY 0xf098
e4adb204 1207#define PCI_DEVICE_ID_LP101 0xf0a1
dea3101e 1208#define PCI_DEVICE_ID_TFLY 0xf0a5
e4adb204
JSEC		 1209#define PCI_DEVICE_ID_BSMB 0xf0d1
1210#define PCI_DEVICE_ID_BMID 0xf0d5
1211#define PCI_DEVICE_ID_ZSMB 0xf0e1
1212#define PCI_DEVICE_ID_ZMID 0xf0e5
1213#define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1214#define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1215#define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
b87eab38
JS		 1216#define PCI_DEVICE_ID_SAT 0xf100
1217#define PCI_DEVICE_ID_SAT_SCSP 0xf111
1218#define PCI_DEVICE_ID_SAT_DCSP 0xf112
085c647c 1219#define PCI_DEVICE_ID_FALCON 0xf180
e4adb204
JSEC		 1220#define PCI_DEVICE_ID_SUPERFLY 0xf700
1221#define PCI_DEVICE_ID_DRAGONFLY 0xf800
dea3101e 1222#define PCI_DEVICE_ID_CENTAUR 0xf900
1223#define PCI_DEVICE_ID_PEGASUS 0xf980
1224#define PCI_DEVICE_ID_THOR 0xfa00
1225#define PCI_DEVICE_ID_VIPER 0xfb00
e4adb204
JSEC		 1226#define PCI_DEVICE_ID_LP10000S 0xfc00
1227#define PCI_DEVICE_ID_LP11000S 0xfc10
1228#define PCI_DEVICE_ID_LPE11000S 0xfc20
b87eab38 1229#define PCI_DEVICE_ID_SAT_S 0xfc40
84774a4d 1230#define PCI_DEVICE_ID_PROTEUS_S 0xfc50
dea3101e 1231#define PCI_DEVICE_ID_HELIOS 0xfd00
e4adb204
JSEC		 1232#define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1233#define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
dea3101e 1234#define PCI_DEVICE_ID_ZEPHYR 0xfe00
84774a4d 1235#define PCI_DEVICE_ID_HORNET 0xfe05
e4adb204
JSEC		 1236#define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1237#define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
da0436e9
JS		 1238#define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1239#define PCI_DEVICE_ID_TIGERSHARK 0x0704
a747c9ce 1240#define PCI_DEVICE_ID_TOMCAT 0x0714
dea3101e 1241
1242#define JEDEC_ID_ADDRESS 0x0080001c
1243#define FIREFLY_JEDEC_ID 0x1ACC
1244#define SUPERFLY_JEDEC_ID 0x0020
1245#define DRAGONFLY_JEDEC_ID 0x0021
1246#define DRAGONFLY_V2_JEDEC_ID 0x0025
1247#define CENTAUR_2G_JEDEC_ID 0x0026
1248#define CENTAUR_1G_JEDEC_ID 0x0028
1249#define PEGASUS_ORION_JEDEC_ID 0x0036
1250#define PEGASUS_JEDEC_ID 0x0038
1251#define THOR_JEDEC_ID 0x0012
1252#define HELIOS_JEDEC_ID 0x0364
1253#define ZEPHYR_JEDEC_ID 0x0577
1254#define VIPER_JEDEC_ID 0x4838
b87eab38 1255#define SATURN_JEDEC_ID 0x1004
84774a4d 1256#define HORNET_JDEC_ID 0x2057706D
dea3101e 1257
1258#define JEDEC_ID_MASK 0x0FFFF000
1259#define JEDEC_ID_SHIFT 12
1260#define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1261
1262typedef struct { /* FireFly BIU registers */
1263 uint32_t hostAtt; /* See definitions for Host Attention
1264 register */
1265 uint32_t chipAtt; /* See definitions for Chip Attention
1266 register */
1267 uint32_t hostStatus; /* See definitions for Host Status register */
1268 uint32_t hostControl; /* See definitions for Host Control register */
1269 uint32_t buiConfig; /* See definitions for BIU configuration
1270 register */
1271} FF_REGS;
1272
1273/* IO Register size in bytes */
1274#define FF_REG_AREA_SIZE 256
1275
1276/* Host Attention Register */
1277
1278#define HA_REG_OFFSET 0 /* Byte offset from register base address */
1279
1280#define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1281#define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1282#define HA_R0ATT 0x00000008 /* Bit 3 */
1283#define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1284#define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1285#define HA_R1ATT 0x00000080 /* Bit 7 */
1286#define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1287#define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1288#define HA_R2ATT 0x00000800 /* Bit 11 */
1289#define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1290#define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1291#define HA_R3ATT 0x00008000 /* Bit 15 */
1292#define HA_LATT 0x20000000 /* Bit 29 */
1293#define HA_MBATT 0x40000000 /* Bit 30 */
1294#define HA_ERATT 0x80000000 /* Bit 31 */
1295
1296#define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1297#define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1298#define HA_RXATT 0x00000008 /* Bit 3 */
1299#define HA_RXMASK 0x0000000f
1300
9399627f
JS		 1301#define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1302#define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1303#define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1304#define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1305
1306#define HA_R0_POS 3
1307#define HA_R1_POS 7
1308#define HA_R2_POS 11
1309#define HA_R3_POS 15
1310#define HA_LE_POS 29
1311#define HA_MB_POS 30
1312#define HA_ER_POS 31
dea3101e 1313/* Chip Attention Register */
1314
1315#define CA_REG_OFFSET 4 /* Byte offset from register base address */
1316
1317#define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1318#define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1319#define CA_R0ATT 0x00000008 /* Bit 3 */
1320#define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1321#define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1322#define CA_R1ATT 0x00000080 /* Bit 7 */
1323#define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1324#define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1325#define CA_R2ATT 0x00000800 /* Bit 11 */
1326#define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1327#define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1328#define CA_R3ATT 0x00008000 /* Bit 15 */
1329#define CA_MBATT 0x40000000 /* Bit 30 */
1330
1331/* Host Status Register */
1332
1333#define HS_REG_OFFSET 8 /* Byte offset from register base address */
1334
1335#define HS_MBRDY 0x00400000 /* Bit 22 */
1336#define HS_FFRDY 0x00800000 /* Bit 23 */
1337#define HS_FFER8 0x01000000 /* Bit 24 */
1338#define HS_FFER7 0x02000000 /* Bit 25 */
1339#define HS_FFER6 0x04000000 /* Bit 26 */
1340#define HS_FFER5 0x08000000 /* Bit 27 */
1341#define HS_FFER4 0x10000000 /* Bit 28 */
1342#define HS_FFER3 0x20000000 /* Bit 29 */
1343#define HS_FFER2 0x40000000 /* Bit 30 */
1344#define HS_FFER1 0x80000000 /* Bit 31 */
57127f15
JS		 1345#define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1346#define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
9940b97b 1347#define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
dea3101e 1348/* Host Control Register */
1349
9399627f 1350#define HC_REG_OFFSET 12 /* Byte offset from register base address */
dea3101e 1351
1352#define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1353#define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1354#define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1355#define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1356#define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1357#define HC_INITHBI 0x02000000 /* Bit 25 */
1358#define HC_INITMB 0x04000000 /* Bit 26 */
1359#define HC_INITFF 0x08000000 /* Bit 27 */
1360#define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1361#define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1362
9399627f
JS		 1363/* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1364#define MSIX_DFLT_ID 0
1365#define MSIX_RNG0_ID 0
1366#define MSIX_RNG1_ID 1
1367#define MSIX_RNG2_ID 2
1368#define MSIX_RNG3_ID 3
1369
1370#define MSIX_LINK_ID 4
1371#define MSIX_MBOX_ID 5
1372
1373#define MSIX_SPARE0_ID 6
1374#define MSIX_SPARE1_ID 7
1375
dea3101e 1376/* Mailbox Commands */
1377#define MBX_SHUTDOWN 0x00 /* terminate testing */
1378#define MBX_LOAD_SM 0x01
1379#define MBX_READ_NV 0x02
1380#define MBX_WRITE_NV 0x03
1381#define MBX_RUN_BIU_DIAG 0x04
1382#define MBX_INIT_LINK 0x05
1383#define MBX_DOWN_LINK 0x06
1384#define MBX_CONFIG_LINK 0x07
1385#define MBX_CONFIG_RING 0x09
1386#define MBX_RESET_RING 0x0A
1387#define MBX_READ_CONFIG 0x0B
1388#define MBX_READ_RCONFIG 0x0C
1389#define MBX_READ_SPARM 0x0D
1390#define MBX_READ_STATUS 0x0E
1391#define MBX_READ_RPI 0x0F
1392#define MBX_READ_XRI 0x10
1393#define MBX_READ_REV 0x11
1394#define MBX_READ_LNK_STAT 0x12
1395#define MBX_REG_LOGIN 0x13
1396#define MBX_UNREG_LOGIN 0x14
dea3101e 1397#define MBX_CLEAR_LA 0x16
1398#define MBX_DUMP_MEMORY 0x17
1399#define MBX_DUMP_CONTEXT 0x18
1400#define MBX_RUN_DIAGS 0x19
1401#define MBX_RESTART 0x1A
1402#define MBX_UPDATE_CFG 0x1B
1403#define MBX_DOWN_LOAD 0x1C
1404#define MBX_DEL_LD_ENTRY 0x1D
1405#define MBX_RUN_PROGRAM 0x1E
1406#define MBX_SET_MASK 0x20
09372820 1407#define MBX_SET_VARIABLE 0x21
dea3101e 1408#define MBX_UNREG_D_ID 0x23
41415862 1409#define MBX_KILL_BOARD 0x24
dea3101e 1410#define MBX_CONFIG_FARP 0x25
41415862 1411#define MBX_BEACON 0x2A
9399627f 1412#define MBX_CONFIG_MSI 0x30
858c9f6c 1413#define MBX_HEARTBEAT 0x31
a8adb832
JS		 1414#define MBX_WRITE_VPARMS 0x32
1415#define MBX_ASYNCEVT_ENABLE 0x33
4fede78f
JS		 1416#define MBX_READ_EVENT_LOG_STATUS 0x37
1417#define MBX_READ_EVENT_LOG 0x38
1418#define MBX_WRITE_EVENT_LOG 0x39
dea3101e 1419
84774a4d
JS		 1420#define MBX_PORT_CAPABILITIES 0x3B
1421#define MBX_PORT_IOV_CONTROL 0x3C
1422
ed957684 1423#define MBX_CONFIG_HBQ 0x7C
dea3101e 1424#define MBX_LOAD_AREA 0x81
1425#define MBX_RUN_BIU_DIAG64 0x84
1426#define MBX_CONFIG_PORT 0x88
1427#define MBX_READ_SPARM64 0x8D
1428#define MBX_READ_RPI64 0x8F
1429#define MBX_REG_LOGIN64 0x93
76a95d75 1430#define MBX_READ_TOPOLOGY 0x95
92d7f7b0
JS		 1431#define MBX_REG_VPI 0x96
1432#define MBX_UNREG_VPI 0x97
dea3101e 1433
09372820 1434#define MBX_WRITE_WWN 0x98
dea3101e 1435#define MBX_SET_DEBUG 0x99
1436#define MBX_LOAD_EXP_ROM 0x9C
da0436e9
JS		 1437#define MBX_SLI4_CONFIG 0x9B
1438#define MBX_SLI4_REQ_FTRS 0x9D
1439#define MBX_MAX_CMDS 0x9E
1440#define MBX_RESUME_RPI 0x9E
dea3101e 1441#define MBX_SLI2_CMD_MASK 0x80
da0436e9
JS		 1442#define MBX_REG_VFI 0x9F
1443#define MBX_REG_FCFI 0xA0
1444#define MBX_UNREG_VFI 0xA1
1445#define MBX_UNREG_FCFI 0xA2
1446#define MBX_INIT_VFI 0xA3
1447#define MBX_INIT_VPI 0xA4
dea3101e 1448
dcf2a4e0
JS		 1449#define MBX_AUTH_PORT 0xF8
1450#define MBX_SECURITY_MGMT 0xF9
1451
dea3101e 1452/* IOCB Commands */
1453
1454#define CMD_RCV_SEQUENCE_CX 0x01
1455#define CMD_XMIT_SEQUENCE_CR 0x02
1456#define CMD_XMIT_SEQUENCE_CX 0x03
1457#define CMD_XMIT_BCAST_CN 0x04
1458#define CMD_XMIT_BCAST_CX 0x05
1459#define CMD_QUE_RING_BUF_CN 0x06
1460#define CMD_QUE_XRI_BUF_CX 0x07
1461#define CMD_IOCB_CONTINUE_CN 0x08
1462#define CMD_RET_XRI_BUF_CX 0x09
1463#define CMD_ELS_REQUEST_CR 0x0A
1464#define CMD_ELS_REQUEST_CX 0x0B
1465#define CMD_RCV_ELS_REQ_CX 0x0D
1466#define CMD_ABORT_XRI_CN 0x0E
1467#define CMD_ABORT_XRI_CX 0x0F
1468#define CMD_CLOSE_XRI_CN 0x10
1469#define CMD_CLOSE_XRI_CX 0x11
1470#define CMD_CREATE_XRI_CR 0x12
1471#define CMD_CREATE_XRI_CX 0x13
1472#define CMD_GET_RPI_CN 0x14
1473#define CMD_XMIT_ELS_RSP_CX 0x15
1474#define CMD_GET_RPI_CR 0x16
1475#define CMD_XRI_ABORTED_CX 0x17
1476#define CMD_FCP_IWRITE_CR 0x18
1477#define CMD_FCP_IWRITE_CX 0x19
1478#define CMD_FCP_IREAD_CR 0x1A
1479#define CMD_FCP_IREAD_CX 0x1B
1480#define CMD_FCP_ICMND_CR 0x1C
1481#define CMD_FCP_ICMND_CX 0x1D
f5603511
JS		 1482#define CMD_FCP_TSEND_CX 0x1F
1483#define CMD_FCP_TRECEIVE_CX 0x21
1484#define CMD_FCP_TRSP_CX 0x23
1485#define CMD_FCP_AUTO_TRSP_CX 0x29
dea3101e 1486
1487#define CMD_ADAPTER_MSG 0x20
1488#define CMD_ADAPTER_DUMP 0x22
1489
1490/* SLI_2 IOCB Command Set */
1491
57127f15 1492#define CMD_ASYNC_STATUS 0x7C
dea3101e 1493#define CMD_RCV_SEQUENCE64_CX 0x81
1494#define CMD_XMIT_SEQUENCE64_CR 0x82
1495#define CMD_XMIT_SEQUENCE64_CX 0x83
1496#define CMD_XMIT_BCAST64_CN 0x84
1497#define CMD_XMIT_BCAST64_CX 0x85
1498#define CMD_QUE_RING_BUF64_CN 0x86
1499#define CMD_QUE_XRI_BUF64_CX 0x87
1500#define CMD_IOCB_CONTINUE64_CN 0x88
1501#define CMD_RET_XRI_BUF64_CX 0x89
1502#define CMD_ELS_REQUEST64_CR 0x8A
1503#define CMD_ELS_REQUEST64_CX 0x8B
1504#define CMD_ABORT_MXRI64_CN 0x8C
1505#define CMD_RCV_ELS_REQ64_CX 0x8D
1506#define CMD_XMIT_ELS_RSP64_CX 0x95
6669f9bb 1507#define CMD_XMIT_BLS_RSP64_CX 0x97
dea3101e 1508#define CMD_FCP_IWRITE64_CR 0x98
1509#define CMD_FCP_IWRITE64_CX 0x99
1510#define CMD_FCP_IREAD64_CR 0x9A
1511#define CMD_FCP_IREAD64_CX 0x9B
1512#define CMD_FCP_ICMND64_CR 0x9C
1513#define CMD_FCP_ICMND64_CX 0x9D
f5603511
JS		 1514#define CMD_FCP_TSEND64_CX 0x9F
1515#define CMD_FCP_TRECEIVE64_CX 0xA1
1516#define CMD_FCP_TRSP64_CX 0xA3
dea3101e 1517
76bb24ef 1518#define CMD_QUE_XRI64_CX 0xB3
ed957684
JS		 1519#define CMD_IOCB_RCV_SEQ64_CX 0xB5
1520#define CMD_IOCB_RCV_ELS64_CX 0xB7
3163f725 1521#define CMD_IOCB_RET_XRI64_CX 0xB9
ed957684
JS		 1522#define CMD_IOCB_RCV_CONT64_CX 0xBB
1523
dea3101e 1524#define CMD_GEN_REQUEST64_CR 0xC2
1525#define CMD_GEN_REQUEST64_CX 0xC3
1526
3163f725
JS		 1527/* Unhandled SLI-3 Commands */
1528#define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1529#define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1530#define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1531#define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1532#define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1533#define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1534#define CMD_IOCB_RET_HBQE64_CN 0xCA
1535#define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1536#define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1537#define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1538#define CMD_IOCB_LOGENTRY_CN 0x94
1539#define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1540
341af102
JS		 1541/* Data Security SLI Commands */
1542#define DSSCMD_IWRITE64_CR 0xF8
1543#define DSSCMD_IWRITE64_CX 0xF9
1544#define DSSCMD_IREAD64_CR 0xFA
1545#define DSSCMD_IREAD64_CX 0xFB
1546
1547#define CMD_MAX_IOCB_CMD 0xFB
dea3101e 1548#define CMD_IOCB_MASK 0xff
1549
1550#define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1551 iocb */
1552#define LPFC_MAX_ADPTMSG 32 /* max msg data */
1553/*
1554 * Define Status
1555 */
1556#define MBX_SUCCESS 0
1557#define MBXERR_NUM_RINGS 1
1558#define MBXERR_NUM_IOCBS 2
1559#define MBXERR_IOCBS_EXCEEDED 3
1560#define MBXERR_BAD_RING_NUMBER 4
1561#define MBXERR_MASK_ENTRIES_RANGE 5
1562#define MBXERR_MASKS_EXCEEDED 6
1563#define MBXERR_BAD_PROFILE 7
1564#define MBXERR_BAD_DEF_CLASS 8
1565#define MBXERR_BAD_MAX_RESPONDER 9
1566#define MBXERR_BAD_MAX_ORIGINATOR 10
1567#define MBXERR_RPI_REGISTERED 11
1568#define MBXERR_RPI_FULL 12
1569#define MBXERR_NO_RESOURCES 13
1570#define MBXERR_BAD_RCV_LENGTH 14
1571#define MBXERR_DMA_ERROR 15
1572#define MBXERR_ERROR 16
da0436e9 1573#define MBXERR_LINK_DOWN 0x33
dcf2a4e0
JS		 1574#define MBXERR_SEC_NO_PERMISSION 0xF02
1575#define MBX_NOT_FINISHED 255
dea3101e 1576
1577#define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1578#define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1579
57127f15
JS		 1580#define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1581
dea3101e 1582/*
1583 * Begin Structure Definitions for Mailbox Commands
1584 */
1585
1586typedef struct {
1587#ifdef __BIG_ENDIAN_BITFIELD
1588 uint8_t tval;
1589 uint8_t tmask;
1590 uint8_t rval;
1591 uint8_t rmask;
1592#else /* __LITTLE_ENDIAN_BITFIELD */
1593 uint8_t rmask;
1594 uint8_t rval;
1595 uint8_t tmask;
1596 uint8_t tval;
1597#endif
1598} RR_REG;
1599
1600struct ulp_bde {
1601 uint32_t bdeAddress;
1602#ifdef __BIG_ENDIAN_BITFIELD
1603 uint32_t bdeReserved:4;
1604 uint32_t bdeAddrHigh:4;
1605 uint32_t bdeSize:24;
1606#else /* __LITTLE_ENDIAN_BITFIELD */
1607 uint32_t bdeSize:24;
1608 uint32_t bdeAddrHigh:4;
1609 uint32_t bdeReserved:4;
1610#endif
1611};
1612
dea3101e 1613typedef struct ULP_BDL { /* SLI-2 */
1614#ifdef __BIG_ENDIAN_BITFIELD
1615 uint32_t bdeFlags:8; /* BDL Flags */
1616 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1617#else /* __LITTLE_ENDIAN_BITFIELD */
1618 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1619 uint32_t bdeFlags:8; /* BDL Flags */
1620#endif
1621
1622 uint32_t addrLow; /* Address 0:31 */
1623 uint32_t addrHigh; /* Address 32:63 */
1624 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1625} ULP_BDL;
1626
81301a9b
JS		 1627/*
1628 * BlockGuard Definitions
1629 */
1630
1631enum lpfc_protgrp_type {
1632 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
1633 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
1634 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
1635 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
1636};
1637
1638/* PDE Descriptors */
6c8eea54
JS		 1639#define LPFC_PDE5_DESCRIPTOR 0x85
1640#define LPFC_PDE6_DESCRIPTOR 0x86
1641#define LPFC_PDE7_DESCRIPTOR 0x87
1642
1643/* BlockGuard Opcodes */
1644#define BG_OP_IN_NODIF_OUT_CRC 0x0
1645#define BG_OP_IN_CRC_OUT_NODIF 0x1
1646#define BG_OP_IN_NODIF_OUT_CSUM 0x2
1647#define BG_OP_IN_CSUM_OUT_NODIF 0x3
1648#define BG_OP_IN_CRC_OUT_CRC 0x4
1649#define BG_OP_IN_CSUM_OUT_CSUM 0x5
1650#define BG_OP_IN_CRC_OUT_CSUM 0x6
1651#define BG_OP_IN_CSUM_OUT_CRC 0x7
1652
1653struct lpfc_pde5 {
1654 uint32_t word0;
1655#define pde5_type_SHIFT 24
1656#define pde5_type_MASK 0x000000ff
1657#define pde5_type_WORD word0
1658#define pde5_rsvd0_SHIFT 0
1659#define pde5_rsvd0_MASK 0x00ffffff
1660#define pde5_rsvd0_WORD word0
1661 uint32_t reftag; /* Reference Tag Value */
1662 uint32_t reftagtr; /* Reference Tag Translation Value */
81301a9b
JS		 1663};
1664
6c8eea54
JS		 1665struct lpfc_pde6 {
1666 uint32_t word0;
1667#define pde6_type_SHIFT 24
1668#define pde6_type_MASK 0x000000ff
1669#define pde6_type_WORD word0
1670#define pde6_rsvd0_SHIFT 0
1671#define pde6_rsvd0_MASK 0x00ffffff
1672#define pde6_rsvd0_WORD word0
1673 uint32_t word1;
1674#define pde6_rsvd1_SHIFT 26
1675#define pde6_rsvd1_MASK 0x0000003f
1676#define pde6_rsvd1_WORD word1
1677#define pde6_na_SHIFT 25
1678#define pde6_na_MASK 0x00000001
1679#define pde6_na_WORD word1
1680#define pde6_rsvd2_SHIFT 16
1681#define pde6_rsvd2_MASK 0x000001FF
1682#define pde6_rsvd2_WORD word1
1683#define pde6_apptagtr_SHIFT 0
1684#define pde6_apptagtr_MASK 0x0000ffff
1685#define pde6_apptagtr_WORD word1
1686 uint32_t word2;
1687#define pde6_optx_SHIFT 28
1688#define pde6_optx_MASK 0x0000000f
1689#define pde6_optx_WORD word2
1690#define pde6_oprx_SHIFT 24
1691#define pde6_oprx_MASK 0x0000000f
1692#define pde6_oprx_WORD word2
1693#define pde6_nr_SHIFT 23
1694#define pde6_nr_MASK 0x00000001
1695#define pde6_nr_WORD word2
1696#define pde6_ce_SHIFT 22
1697#define pde6_ce_MASK 0x00000001
1698#define pde6_ce_WORD word2
1699#define pde6_re_SHIFT 21
1700#define pde6_re_MASK 0x00000001
1701#define pde6_re_WORD word2
1702#define pde6_ae_SHIFT 20
1703#define pde6_ae_MASK 0x00000001
1704#define pde6_ae_WORD word2
1705#define pde6_ai_SHIFT 19
1706#define pde6_ai_MASK 0x00000001
1707#define pde6_ai_WORD word2
1708#define pde6_bs_SHIFT 16
1709#define pde6_bs_MASK 0x00000007
1710#define pde6_bs_WORD word2
1711#define pde6_apptagval_SHIFT 0
1712#define pde6_apptagval_MASK 0x0000ffff
1713#define pde6_apptagval_WORD word2
81301a9b
JS		 1714};
1715
7f86059a
JS		 1716struct lpfc_pde7 {
1717 uint32_t word0;
1718#define pde7_type_SHIFT 24
1719#define pde7_type_MASK 0x000000ff
1720#define pde7_type_WORD word0
1721#define pde7_rsvd0_SHIFT 0
1722#define pde7_rsvd0_MASK 0x00ffffff
1723#define pde7_rsvd0_WORD word0
1724 uint32_t addrHigh;
1725 uint32_t addrLow;
1726};
81301a9b 1727
dea3101e 1728/* Structure for MB Command LOAD_SM and DOWN_LOAD */
1729
1730typedef struct {
1731#ifdef __BIG_ENDIAN_BITFIELD
1732 uint32_t rsvd2:25;
1733 uint32_t acknowledgment:1;
1734 uint32_t version:1;
1735 uint32_t erase_or_prog:1;
1736 uint32_t update_flash:1;
1737 uint32_t update_ram:1;
1738 uint32_t method:1;
1739 uint32_t load_cmplt:1;
1740#else /* __LITTLE_ENDIAN_BITFIELD */
1741 uint32_t load_cmplt:1;
1742 uint32_t method:1;
1743 uint32_t update_ram:1;
1744 uint32_t update_flash:1;
1745 uint32_t erase_or_prog:1;
1746 uint32_t version:1;
1747 uint32_t acknowledgment:1;
1748 uint32_t rsvd2:25;
1749#endif
1750
1751 uint32_t dl_to_adr_low;
1752 uint32_t dl_to_adr_high;
1753 uint32_t dl_len;
1754 union {
1755 uint32_t dl_from_mbx_offset;
1756 struct ulp_bde dl_from_bde;
1757 struct ulp_bde64 dl_from_bde64;
1758 } un;
1759
1760} LOAD_SM_VAR;
1761
1762/* Structure for MB Command READ_NVPARM (02) */
1763
1764typedef struct {
1765 uint32_t rsvd1[3]; /* Read as all one's */
1766 uint32_t rsvd2; /* Read as all zero's */
1767 uint32_t portname[2]; /* N_PORT name */
1768 uint32_t nodename[2]; /* NODE name */
1769
1770#ifdef __BIG_ENDIAN_BITFIELD
1771 uint32_t pref_DID:24;
1772 uint32_t hardAL_PA:8;
1773#else /* __LITTLE_ENDIAN_BITFIELD */
1774 uint32_t hardAL_PA:8;
1775 uint32_t pref_DID:24;
1776#endif
1777
1778 uint32_t rsvd3[21]; /* Read as all one's */
1779} READ_NV_VAR;
1780
1781/* Structure for MB Command WRITE_NVPARMS (03) */
1782
1783typedef struct {
1784 uint32_t rsvd1[3]; /* Must be all one's */
1785 uint32_t rsvd2; /* Must be all zero's */
1786 uint32_t portname[2]; /* N_PORT name */
1787 uint32_t nodename[2]; /* NODE name */
1788
1789#ifdef __BIG_ENDIAN_BITFIELD
1790 uint32_t pref_DID:24;
1791 uint32_t hardAL_PA:8;
1792#else /* __LITTLE_ENDIAN_BITFIELD */
1793 uint32_t hardAL_PA:8;
1794 uint32_t pref_DID:24;
1795#endif
1796
1797 uint32_t rsvd3[21]; /* Must be all one's */
1798} WRITE_NV_VAR;
1799
1800/* Structure for MB Command RUN_BIU_DIAG (04) */
1801/* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1802
1803typedef struct {
1804 uint32_t rsvd1;
1805 union {
1806 struct {
1807 struct ulp_bde xmit_bde;
1808 struct ulp_bde rcv_bde;
1809 } s1;
1810 struct {
1811 struct ulp_bde64 xmit_bde64;
1812 struct ulp_bde64 rcv_bde64;
1813 } s2;
1814 } un;
1815} BIU_DIAG_VAR;
1816
c7495937
JS		 1817/* Structure for MB command READ_EVENT_LOG (0x38) */
1818struct READ_EVENT_LOG_VAR {
1819 uint32_t word1;
1820#define lpfc_event_log_SHIFT 29
1821#define lpfc_event_log_MASK 0x00000001
1822#define lpfc_event_log_WORD word1
1823#define USE_MAILBOX_RESPONSE 1
1824 uint32_t offset;
1825 struct ulp_bde64 rcv_bde64;
1826};
1827
dea3101e 1828/* Structure for MB Command INIT_LINK (05) */
1829
1830typedef struct {
1831#ifdef __BIG_ENDIAN_BITFIELD
1832 uint32_t rsvd1:24;
1833 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1834#else /* __LITTLE_ENDIAN_BITFIELD */
1835 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1836 uint32_t rsvd1:24;
1837#endif
1838
1839#ifdef __BIG_ENDIAN_BITFIELD
1840 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1841 uint8_t rsvd2;
1842 uint16_t link_flags;
1843#else /* __LITTLE_ENDIAN_BITFIELD */
1844 uint16_t link_flags;
1845 uint8_t rsvd2;
1846 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1847#endif
1848
1849#define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1850#define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1851#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1852#define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1853#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
92d7f7b0 1854#define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
dea3101e 1855#define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1856
1857#define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1858#define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
4b0b91d4 1859#define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
dea3101e 1860
1861 uint32_t link_speed;
76a95d75
JS		 1862#define LINK_SPEED_AUTO 0x0 /* Auto selection */
1863#define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
1864#define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
1865#define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
1866#define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
1867#define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
1868#define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
dea3101e 1869
1870} INIT_LINK_VAR;
1871
1872/* Structure for MB Command DOWN_LINK (06) */
1873
1874typedef struct {
1875 uint32_t rsvd1;
1876} DOWN_LINK_VAR;
1877
1878/* Structure for MB Command CONFIG_LINK (07) */
1879
1880typedef struct {
1881#ifdef __BIG_ENDIAN_BITFIELD
1882 uint32_t cr:1;
1883 uint32_t ci:1;
1884 uint32_t cr_delay:6;
1885 uint32_t cr_count:8;
1886 uint32_t rsvd1:8;
1887 uint32_t MaxBBC:8;
1888#else /* __LITTLE_ENDIAN_BITFIELD */
1889 uint32_t MaxBBC:8;
1890 uint32_t rsvd1:8;
1891 uint32_t cr_count:8;
1892 uint32_t cr_delay:6;
1893 uint32_t ci:1;
1894 uint32_t cr:1;
1895#endif
1896
1897 uint32_t myId;
1898 uint32_t rsvd2;
1899 uint32_t edtov;
1900 uint32_t arbtov;
1901 uint32_t ratov;
1902 uint32_t rttov;
1903 uint32_t altov;
1904 uint32_t crtov;
1905 uint32_t citov;
1906#ifdef __BIG_ENDIAN_BITFIELD
1907 uint32_t rrq_enable:1;
1908 uint32_t rrq_immed:1;
1909 uint32_t rsvd4:29;
1910 uint32_t ack0_enable:1;
1911#else /* __LITTLE_ENDIAN_BITFIELD */
1912 uint32_t ack0_enable:1;
1913 uint32_t rsvd4:29;
1914 uint32_t rrq_immed:1;
1915 uint32_t rrq_enable:1;
1916#endif
1917} CONFIG_LINK;
1918
1919/* Structure for MB Command PART_SLIM (08)
1920 * will be removed since SLI1 is no longer supported!
1921 */
1922typedef struct {
1923#ifdef __BIG_ENDIAN_BITFIELD
1924 uint16_t offCiocb;
1925 uint16_t numCiocb;
1926 uint16_t offRiocb;
1927 uint16_t numRiocb;
1928#else /* __LITTLE_ENDIAN_BITFIELD */
1929 uint16_t numCiocb;
1930 uint16_t offCiocb;
1931 uint16_t numRiocb;
1932 uint16_t offRiocb;
1933#endif
1934} RING_DEF;
1935
1936typedef struct {
1937#ifdef __BIG_ENDIAN_BITFIELD
1938 uint32_t unused1:24;
1939 uint32_t numRing:8;
1940#else /* __LITTLE_ENDIAN_BITFIELD */
1941 uint32_t numRing:8;
1942 uint32_t unused1:24;
1943#endif
1944
1945 RING_DEF ringdef[4];
1946 uint32_t hbainit;
1947} PART_SLIM_VAR;
1948
1949/* Structure for MB Command CONFIG_RING (09) */
1950
1951typedef struct {
1952#ifdef __BIG_ENDIAN_BITFIELD
1953 uint32_t unused2:6;
1954 uint32_t recvSeq:1;
1955 uint32_t recvNotify:1;
1956 uint32_t numMask:8;
1957 uint32_t profile:8;
1958 uint32_t unused1:4;
1959 uint32_t ring:4;
1960#else /* __LITTLE_ENDIAN_BITFIELD */
1961 uint32_t ring:4;
1962 uint32_t unused1:4;
1963 uint32_t profile:8;
1964 uint32_t numMask:8;
1965 uint32_t recvNotify:1;
1966 uint32_t recvSeq:1;
1967 uint32_t unused2:6;
1968#endif
1969
1970#ifdef __BIG_ENDIAN_BITFIELD
1971 uint16_t maxRespXchg;
1972 uint16_t maxOrigXchg;
1973#else /* __LITTLE_ENDIAN_BITFIELD */
1974 uint16_t maxOrigXchg;
1975 uint16_t maxRespXchg;
1976#endif
1977
1978 RR_REG rrRegs[6];
1979} CONFIG_RING_VAR;
1980
1981/* Structure for MB Command RESET_RING (10) */
1982
1983typedef struct {
1984 uint32_t ring_no;
1985} RESET_RING_VAR;
1986
1987/* Structure for MB Command READ_CONFIG (11) */
1988
1989typedef struct {
1990#ifdef __BIG_ENDIAN_BITFIELD
1991 uint32_t cr:1;
1992 uint32_t ci:1;
1993 uint32_t cr_delay:6;
1994 uint32_t cr_count:8;
1995 uint32_t InitBBC:8;
1996 uint32_t MaxBBC:8;
1997#else /* __LITTLE_ENDIAN_BITFIELD */
1998 uint32_t MaxBBC:8;
1999 uint32_t InitBBC:8;
2000 uint32_t cr_count:8;
2001 uint32_t cr_delay:6;
2002 uint32_t ci:1;
2003 uint32_t cr:1;
2004#endif
2005
2006#ifdef __BIG_ENDIAN_BITFIELD
2007 uint32_t topology:8;
2008 uint32_t myDid:24;
2009#else /* __LITTLE_ENDIAN_BITFIELD */
2010 uint32_t myDid:24;
2011 uint32_t topology:8;
2012#endif
2013
2014 /* Defines for topology (defined previously) */
2015#ifdef __BIG_ENDIAN_BITFIELD
2016 uint32_t AR:1;
2017 uint32_t IR:1;
2018 uint32_t rsvd1:29;
2019 uint32_t ack0:1;
2020#else /* __LITTLE_ENDIAN_BITFIELD */
2021 uint32_t ack0:1;
2022 uint32_t rsvd1:29;
2023 uint32_t IR:1;
2024 uint32_t AR:1;
2025#endif
2026
2027 uint32_t edtov;
2028 uint32_t arbtov;
2029 uint32_t ratov;
2030 uint32_t rttov;
2031 uint32_t altov;
2032 uint32_t lmt;
74b72a59
JW		 2033#define LMT_RESERVED 0x000 /* Not used */
2034#define LMT_1Gb 0x004
2035#define LMT_2Gb 0x008
2036#define LMT_4Gb 0x040
2037#define LMT_8Gb 0x080
2038#define LMT_10Gb 0x100
76a95d75 2039#define LMT_16Gb 0x200
dea3101e 2040 uint32_t rsvd2;
2041 uint32_t rsvd3;
2042 uint32_t max_xri;
2043 uint32_t max_iocb;
2044 uint32_t max_rpi;
2045 uint32_t avail_xri;
2046 uint32_t avail_iocb;
2047 uint32_t avail_rpi;
858c9f6c
JS		 2048 uint32_t max_vpi;
2049 uint32_t rsvd4;
2050 uint32_t rsvd5;
2051 uint32_t avail_vpi;
dea3101e 2052} READ_CONFIG_VAR;
2053
2054/* Structure for MB Command READ_RCONFIG (12) */
2055
2056typedef struct {
2057#ifdef __BIG_ENDIAN_BITFIELD
2058 uint32_t rsvd2:7;
2059 uint32_t recvNotify:1;
2060 uint32_t numMask:8;
2061 uint32_t profile:8;
2062 uint32_t rsvd1:4;
2063 uint32_t ring:4;
2064#else /* __LITTLE_ENDIAN_BITFIELD */
2065 uint32_t ring:4;
2066 uint32_t rsvd1:4;
2067 uint32_t profile:8;
2068 uint32_t numMask:8;
2069 uint32_t recvNotify:1;
2070 uint32_t rsvd2:7;
2071#endif
2072
2073#ifdef __BIG_ENDIAN_BITFIELD
2074 uint16_t maxResp;
2075 uint16_t maxOrig;
2076#else /* __LITTLE_ENDIAN_BITFIELD */
2077 uint16_t maxOrig;
2078 uint16_t maxResp;
2079#endif
2080
2081 RR_REG rrRegs[6];
2082
2083#ifdef __BIG_ENDIAN_BITFIELD
2084 uint16_t cmdRingOffset;
2085 uint16_t cmdEntryCnt;
2086 uint16_t rspRingOffset;
2087 uint16_t rspEntryCnt;
2088 uint16_t nextCmdOffset;
2089 uint16_t rsvd3;
2090 uint16_t nextRspOffset;
2091 uint16_t rsvd4;
2092#else /* __LITTLE_ENDIAN_BITFIELD */
2093 uint16_t cmdEntryCnt;
2094 uint16_t cmdRingOffset;
2095 uint16_t rspEntryCnt;
2096 uint16_t rspRingOffset;
2097 uint16_t rsvd3;
2098 uint16_t nextCmdOffset;
2099 uint16_t rsvd4;
2100 uint16_t nextRspOffset;
2101#endif
2102} READ_RCONF_VAR;
2103
2104/* Structure for MB Command READ_SPARM (13) */
2105/* Structure for MB Command READ_SPARM64 (0x8D) */
2106
2107typedef struct {
2108 uint32_t rsvd1;
2109 uint32_t rsvd2;
2110 union {
2111 struct ulp_bde sp; /* This BDE points to struct serv_parm
2112 structure */
2113 struct ulp_bde64 sp64;
2114 } un;
ed957684
JS		 2115#ifdef __BIG_ENDIAN_BITFIELD
2116 uint16_t rsvd3;
2117 uint16_t vpi;
2118#else /* __LITTLE_ENDIAN_BITFIELD */
2119 uint16_t vpi;
2120 uint16_t rsvd3;
2121#endif
dea3101e 2122} READ_SPARM_VAR;
2123
2124/* Structure for MB Command READ_STATUS (14) */
2125
2126typedef struct {
2127#ifdef __BIG_ENDIAN_BITFIELD
2128 uint32_t rsvd1:31;
2129 uint32_t clrCounters:1;
2130 uint16_t activeXriCnt;
2131 uint16_t activeRpiCnt;
2132#else /* __LITTLE_ENDIAN_BITFIELD */
2133 uint32_t clrCounters:1;
2134 uint32_t rsvd1:31;
2135 uint16_t activeRpiCnt;
2136 uint16_t activeXriCnt;
2137#endif
2138
2139 uint32_t xmitByteCnt;
2140 uint32_t rcvByteCnt;
2141 uint32_t xmitFrameCnt;
2142 uint32_t rcvFrameCnt;
2143 uint32_t xmitSeqCnt;
2144 uint32_t rcvSeqCnt;
2145 uint32_t totalOrigExchanges;
2146 uint32_t totalRespExchanges;
2147 uint32_t rcvPbsyCnt;
2148 uint32_t rcvFbsyCnt;
2149} READ_STATUS_VAR;
2150
2151/* Structure for MB Command READ_RPI (15) */
2152/* Structure for MB Command READ_RPI64 (0x8F) */
2153
2154typedef struct {
2155#ifdef __BIG_ENDIAN_BITFIELD
2156 uint16_t nextRpi;
2157 uint16_t reqRpi;
2158 uint32_t rsvd2:8;
2159 uint32_t DID:24;
2160#else /* __LITTLE_ENDIAN_BITFIELD */
2161 uint16_t reqRpi;
2162 uint16_t nextRpi;
2163 uint32_t DID:24;
2164 uint32_t rsvd2:8;
2165#endif
2166
2167 union {
2168 struct ulp_bde sp;
2169 struct ulp_bde64 sp64;
2170 } un;
2171
2172} READ_RPI_VAR;
2173
2174/* Structure for MB Command READ_XRI (16) */
2175
2176typedef struct {
2177#ifdef __BIG_ENDIAN_BITFIELD
2178 uint16_t nextXri;
2179 uint16_t reqXri;
2180 uint16_t rsvd1;
2181 uint16_t rpi;
2182 uint32_t rsvd2:8;
2183 uint32_t DID:24;
2184 uint32_t rsvd3:8;
2185 uint32_t SID:24;
2186 uint32_t rsvd4;
2187 uint8_t seqId;
2188 uint8_t rsvd5;
2189 uint16_t seqCount;
2190 uint16_t oxId;
2191 uint16_t rxId;
2192 uint32_t rsvd6:30;
2193 uint32_t si:1;
2194 uint32_t exchOrig:1;
2195#else /* __LITTLE_ENDIAN_BITFIELD */
2196 uint16_t reqXri;
2197 uint16_t nextXri;
2198 uint16_t rpi;
2199 uint16_t rsvd1;
2200 uint32_t DID:24;
2201 uint32_t rsvd2:8;
2202 uint32_t SID:24;
2203 uint32_t rsvd3:8;
2204 uint32_t rsvd4;
2205 uint16_t seqCount;
2206 uint8_t rsvd5;
2207 uint8_t seqId;
2208 uint16_t rxId;
2209 uint16_t oxId;
2210 uint32_t exchOrig:1;
2211 uint32_t si:1;
2212 uint32_t rsvd6:30;
2213#endif
2214} READ_XRI_VAR;
2215
2216/* Structure for MB Command READ_REV (17) */
2217
2218typedef struct {
2219#ifdef __BIG_ENDIAN_BITFIELD
2220 uint32_t cv:1;
2221 uint32_t rr:1;
ed957684
JS		 2222 uint32_t rsvd2:2;
2223 uint32_t v3req:1;
2224 uint32_t v3rsp:1;
2225 uint32_t rsvd1:25;
dea3101e 2226 uint32_t rv:1;
2227#else /* __LITTLE_ENDIAN_BITFIELD */
2228 uint32_t rv:1;
ed957684
JS		 2229 uint32_t rsvd1:25;
2230 uint32_t v3rsp:1;
2231 uint32_t v3req:1;
2232 uint32_t rsvd2:2;
dea3101e 2233 uint32_t rr:1;
2234 uint32_t cv:1;
2235#endif
2236
2237 uint32_t biuRev;
2238 uint32_t smRev;
2239 union {
2240 uint32_t smFwRev;
2241 struct {
2242#ifdef __BIG_ENDIAN_BITFIELD
2243 uint8_t ProgType;
2244 uint8_t ProgId;
2245 uint16_t ProgVer:4;
2246 uint16_t ProgRev:4;
2247 uint16_t ProgFixLvl:2;
2248 uint16_t ProgDistType:2;
2249 uint16_t DistCnt:4;
2250#else /* __LITTLE_ENDIAN_BITFIELD */
2251 uint16_t DistCnt:4;
2252 uint16_t ProgDistType:2;
2253 uint16_t ProgFixLvl:2;
2254 uint16_t ProgRev:4;
2255 uint16_t ProgVer:4;
2256 uint8_t ProgId;
2257 uint8_t ProgType;
2258#endif
2259
2260 } b;
2261 } un;
2262 uint32_t endecRev;
2263#ifdef __BIG_ENDIAN_BITFIELD
2264 uint8_t feaLevelHigh;
2265 uint8_t feaLevelLow;
2266 uint8_t fcphHigh;
2267 uint8_t fcphLow;
2268#else /* __LITTLE_ENDIAN_BITFIELD */
2269 uint8_t fcphLow;
2270 uint8_t fcphHigh;
2271 uint8_t feaLevelLow;
2272 uint8_t feaLevelHigh;
2273#endif
2274
2275 uint32_t postKernRev;
2276 uint32_t opFwRev;
2277 uint8_t opFwName[16];
2278 uint32_t sli1FwRev;
2279 uint8_t sli1FwName[16];
2280 uint32_t sli2FwRev;
2281 uint8_t sli2FwName[16];
ed957684
JS		 2282 uint32_t sli3Feat;
2283 uint32_t RandomData[6];
dea3101e 2284} READ_REV_VAR;
2285
2286/* Structure for MB Command READ_LINK_STAT (18) */
2287
2288typedef struct {
2289 uint32_t rsvd1;
2290 uint32_t linkFailureCnt;
2291 uint32_t lossSyncCnt;
2292
2293 uint32_t lossSignalCnt;
2294 uint32_t primSeqErrCnt;
2295 uint32_t invalidXmitWord;
2296 uint32_t crcCnt;
2297 uint32_t primSeqTimeout;
2298 uint32_t elasticOverrun;
2299 uint32_t arbTimeout;
2300} READ_LNK_VAR;
2301
2302/* Structure for MB Command REG_LOGIN (19) */
2303/* Structure for MB Command REG_LOGIN64 (0x93) */
2304
2305typedef struct {
2306#ifdef __BIG_ENDIAN_BITFIELD
2307 uint16_t rsvd1;
2308 uint16_t rpi;
2309 uint32_t rsvd2:8;
2310 uint32_t did:24;
2311#else /* __LITTLE_ENDIAN_BITFIELD */
2312 uint16_t rpi;
2313 uint16_t rsvd1;
2314 uint32_t did:24;
2315 uint32_t rsvd2:8;
2316#endif
2317
2318 union {
2319 struct ulp_bde sp;
2320 struct ulp_bde64 sp64;
2321 } un;
2322
ed957684
JS		 2323#ifdef __BIG_ENDIAN_BITFIELD
2324 uint16_t rsvd6;
2325 uint16_t vpi;
2326#else /* __LITTLE_ENDIAN_BITFIELD */
2327 uint16_t vpi;
2328 uint16_t rsvd6;
2329#endif
2330
dea3101e 2331} REG_LOGIN_VAR;
2332
2333/* Word 30 contents for REG_LOGIN */
2334typedef union {
2335 struct {
2336#ifdef __BIG_ENDIAN_BITFIELD
2337 uint16_t rsvd1:12;
2338 uint16_t wd30_class:4;
2339 uint16_t xri;
2340#else /* __LITTLE_ENDIAN_BITFIELD */
2341 uint16_t xri;
2342 uint16_t wd30_class:4;
2343 uint16_t rsvd1:12;
2344#endif
2345 } f;
2346 uint32_t word;
2347} REG_WD30;
2348
2349/* Structure for MB Command UNREG_LOGIN (20) */
2350
2351typedef struct {
2352#ifdef __BIG_ENDIAN_BITFIELD
2353 uint16_t rsvd1;
2354 uint16_t rpi;
ed957684
JS		 2355 uint32_t rsvd2;
2356 uint32_t rsvd3;
2357 uint32_t rsvd4;
2358 uint32_t rsvd5;
2359 uint16_t rsvd6;
2360 uint16_t vpi;
dea3101e 2361#else /* __LITTLE_ENDIAN_BITFIELD */
2362 uint16_t rpi;
2363 uint16_t rsvd1;
ed957684
JS		 2364 uint32_t rsvd2;
2365 uint32_t rsvd3;
2366 uint32_t rsvd4;
2367 uint32_t rsvd5;
2368 uint16_t vpi;
2369 uint16_t rsvd6;
dea3101e 2370#endif
2371} UNREG_LOGIN_VAR;
2372
92d7f7b0
JS		 2373/* Structure for MB Command REG_VPI (0x96) */
2374typedef struct {
2375#ifdef __BIG_ENDIAN_BITFIELD
2376 uint32_t rsvd1;
38b92ef8
JS		 2377 uint32_t rsvd2:7;
2378 uint32_t upd:1;
92d7f7b0 2379 uint32_t sid:24;
c868595d 2380 uint32_t wwn[2];
92d7f7b0 2381 uint32_t rsvd5;
da0436e9 2382 uint16_t vfi;
92d7f7b0
JS		 2383 uint16_t vpi;
2384#else /* __LITTLE_ENDIAN */
2385 uint32_t rsvd1;
2386 uint32_t sid:24;
38b92ef8
JS		 2387 uint32_t upd:1;
2388 uint32_t rsvd2:7;
c868595d 2389 uint32_t wwn[2];
92d7f7b0
JS		 2390 uint32_t rsvd5;
2391 uint16_t vpi;
da0436e9 2392 uint16_t vfi;
92d7f7b0
JS		 2393#endif
2394} REG_VPI_VAR;
2395
2396/* Structure for MB Command UNREG_VPI (0x97) */
2397typedef struct {
2398 uint32_t rsvd1;
6669f9bb
JS		 2399#ifdef __BIG_ENDIAN_BITFIELD
2400 uint16_t rsvd2;
2401 uint16_t sli4_vpi;
2402#else /* __LITTLE_ENDIAN */
2403 uint16_t sli4_vpi;
2404 uint16_t rsvd2;
2405#endif
92d7f7b0
JS		 2406 uint32_t rsvd3;
2407 uint32_t rsvd4;
2408 uint32_t rsvd5;
2409#ifdef __BIG_ENDIAN_BITFIELD
2410 uint16_t rsvd6;
2411 uint16_t vpi;
2412#else /* __LITTLE_ENDIAN */
2413 uint16_t vpi;
2414 uint16_t rsvd6;
2415#endif
2416} UNREG_VPI_VAR;
2417
dea3101e 2418/* Structure for MB Command UNREG_D_ID (0x23) */
2419
2420typedef struct {
2421 uint32_t did;
ed957684
JS		 2422 uint32_t rsvd2;
2423 uint32_t rsvd3;
2424 uint32_t rsvd4;
2425 uint32_t rsvd5;
2426#ifdef __BIG_ENDIAN_BITFIELD
2427 uint16_t rsvd6;
2428 uint16_t vpi;
2429#else
2430 uint16_t vpi;
2431 uint16_t rsvd6;
2432#endif
dea3101e 2433} UNREG_D_ID_VAR;
2434
76a95d75
JS		 2435/* Structure for MB Command READ_TOPOLOGY (0x95) */
2436struct lpfc_mbx_read_top {
dea3101e 2437 uint32_t eventTag; /* Event tag */
76a95d75
JS		 2438 uint32_t word2;
2439#define lpfc_mbx_read_top_fa_SHIFT 12
2440#define lpfc_mbx_read_top_fa_MASK 0x00000001
2441#define lpfc_mbx_read_top_fa_WORD word2
2442#define lpfc_mbx_read_top_mm_SHIFT 11
2443#define lpfc_mbx_read_top_mm_MASK 0x00000001
2444#define lpfc_mbx_read_top_mm_WORD word2
2445#define lpfc_mbx_read_top_pb_SHIFT 9
2446#define lpfc_mbx_read_top_pb_MASK 0X00000001
2447#define lpfc_mbx_read_top_pb_WORD word2
2448#define lpfc_mbx_read_top_il_SHIFT 8
2449#define lpfc_mbx_read_top_il_MASK 0x00000001
2450#define lpfc_mbx_read_top_il_WORD word2
2451#define lpfc_mbx_read_top_att_type_SHIFT 0
2452#define lpfc_mbx_read_top_att_type_MASK 0x000000FF
2453#define lpfc_mbx_read_top_att_type_WORD word2
2454#define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
2455#define LPFC_ATT_LINK_UP 0x01 /* Link is up */
2456#define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
2457 uint32_t word3;
2458#define lpfc_mbx_read_top_alpa_granted_SHIFT 24
2459#define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
2460#define lpfc_mbx_read_top_alpa_granted_WORD word3
2461#define lpfc_mbx_read_top_lip_alps_SHIFT 16
2462#define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
2463#define lpfc_mbx_read_top_lip_alps_WORD word3
2464#define lpfc_mbx_read_top_lip_type_SHIFT 8
2465#define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
2466#define lpfc_mbx_read_top_lip_type_WORD word3
2467#define lpfc_mbx_read_top_topology_SHIFT 0
2468#define lpfc_mbx_read_top_topology_MASK 0x000000FF
2469#define lpfc_mbx_read_top_topology_WORD word3
2470#define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2471#define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2472#define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
2473 /* store the LILP AL_PA position map into */
2474 struct ulp_bde64 lilpBde64;
2475#define LPFC_ALPA_MAP_SIZE 128
2476 uint32_t word7;
2477#define lpfc_mbx_read_top_ld_lu_SHIFT 31
2478#define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
2479#define lpfc_mbx_read_top_ld_lu_WORD word7
2480#define lpfc_mbx_read_top_ld_tf_SHIFT 30
2481#define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
2482#define lpfc_mbx_read_top_ld_tf_WORD word7
2483#define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
2484#define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
2485#define lpfc_mbx_read_top_ld_link_spd_WORD word7
2486#define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
2487#define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
2488#define lpfc_mbx_read_top_ld_nl_port_WORD word7
2489#define lpfc_mbx_read_top_ld_tx_SHIFT 2
2490#define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
2491#define lpfc_mbx_read_top_ld_tx_WORD word7
2492#define lpfc_mbx_read_top_ld_rx_SHIFT 0
2493#define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
2494#define lpfc_mbx_read_top_ld_rx_WORD word7
2495 uint32_t word8;
2496#define lpfc_mbx_read_top_lu_SHIFT 31
2497#define lpfc_mbx_read_top_lu_MASK 0x00000001
2498#define lpfc_mbx_read_top_lu_WORD word8
2499#define lpfc_mbx_read_top_tf_SHIFT 30
2500#define lpfc_mbx_read_top_tf_MASK 0x00000001
2501#define lpfc_mbx_read_top_tf_WORD word8
2502#define lpfc_mbx_read_top_link_spd_SHIFT 8
2503#define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
2504#define lpfc_mbx_read_top_link_spd_WORD word8
2505#define lpfc_mbx_read_top_nl_port_SHIFT 4
2506#define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
2507#define lpfc_mbx_read_top_nl_port_WORD word8
2508#define lpfc_mbx_read_top_tx_SHIFT 2
2509#define lpfc_mbx_read_top_tx_MASK 0x00000003
2510#define lpfc_mbx_read_top_tx_WORD word8
2511#define lpfc_mbx_read_top_rx_SHIFT 0
2512#define lpfc_mbx_read_top_rx_MASK 0x00000003
2513#define lpfc_mbx_read_top_rx_WORD word8
2514#define LPFC_LINK_SPEED_UNKNOWN 0x0
2515#define LPFC_LINK_SPEED_1GHZ 0x04
2516#define LPFC_LINK_SPEED_2GHZ 0x08
2517#define LPFC_LINK_SPEED_4GHZ 0x10
2518#define LPFC_LINK_SPEED_8GHZ 0x20
2519#define LPFC_LINK_SPEED_10GHZ 0x40
2520#define LPFC_LINK_SPEED_16GHZ 0x80
2521};
dea3101e 2522
2523/* Structure for MB Command CLEAR_LA (22) */
2524
2525typedef struct {
2526 uint32_t eventTag; /* Event tag */
2527 uint32_t rsvd1;
2528} CLEAR_LA_VAR;
2529
2530/* Structure for MB Command DUMP */
2531
2532typedef struct {
2533#ifdef __BIG_ENDIAN_BITFIELD
2534 uint32_t rsvd:25;
2535 uint32_t ra:1;
2536 uint32_t co:1;
2537 uint32_t cv:1;
2538 uint32_t type:4;
2539 uint32_t entry_index:16;
2540 uint32_t region_id:16;
2541#else /* __LITTLE_ENDIAN_BITFIELD */
2542 uint32_t type:4;
2543 uint32_t cv:1;
2544 uint32_t co:1;
2545 uint32_t ra:1;
2546 uint32_t rsvd:25;
2547 uint32_t region_id:16;
2548 uint32_t entry_index:16;
2549#endif
2550
da0436e9 2551 uint32_t sli4_length;
dea3101e 2552 uint32_t word_cnt;
2553 uint32_t resp_offset;
2554} DUMP_VAR;
2555
2556#define DMP_MEM_REG 0x1
2557#define DMP_NV_PARAMS 0x2
2558
2559#define DMP_REGION_VPD 0xe
2560#define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2561#define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2562#define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2563
da0436e9
JS		 2564#define DMP_REGION_VPORT 0x16 /* VPort info region */
2565#define DMP_VPORT_REGION_SIZE 0x200
2566#define DMP_MBOX_OFFSET_WORD 0x5
2567
6c8eea54
JS		 2568#define DMP_REGION_23 0x17 /* fcoe param and port state region */
2569#define DMP_RGN23_SIZE 0x400
da0436e9 2570
97207482
JS		 2571#define WAKE_UP_PARMS_REGION_ID 4
2572#define WAKE_UP_PARMS_WORD_SIZE 15
2573
da0436e9
JS		 2574struct vport_rec {
2575 uint8_t wwpn[8];
2576 uint8_t wwnn[8];
2577};
2578
2579#define VPORT_INFO_SIG 0x32324752
2580#define VPORT_INFO_REV_MASK 0xff
2581#define VPORT_INFO_REV 0x1
2582#define MAX_STATIC_VPORT_COUNT 16
2583struct static_vport_info {
6c8eea54 2584 uint32_t signature;
da0436e9 2585 uint32_t rev;
6c8eea54 2586 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
da0436e9
JS		 2587 uint32_t resvd[66];
2588};
2589
97207482
JS		 2590/* Option rom version structure */
2591struct prog_id {
2592#ifdef __BIG_ENDIAN_BITFIELD
2593 uint8_t type;
2594 uint8_t id;
2595 uint32_t ver:4; /* Major Version */
2596 uint32_t rev:4; /* Revision */
2597 uint32_t lev:2; /* Level */
2598 uint32_t dist:2; /* Dist Type */
2599 uint32_t num:4; /* number after dist type */
2600#else /* __LITTLE_ENDIAN_BITFIELD */
2601 uint32_t num:4; /* number after dist type */
2602 uint32_t dist:2; /* Dist Type */
2603 uint32_t lev:2; /* Level */
2604 uint32_t rev:4; /* Revision */
2605 uint32_t ver:4; /* Major Version */
2606 uint8_t id;
2607 uint8_t type;
2608#endif
2609};
2610
d7c255b2
JS		 2611/* Structure for MB Command UPDATE_CFG (0x1B) */
2612
2613struct update_cfg_var {
2614#ifdef __BIG_ENDIAN_BITFIELD
2615 uint32_t rsvd2:16;
2616 uint32_t type:8;
2617 uint32_t rsvd:1;
2618 uint32_t ra:1;
2619 uint32_t co:1;
2620 uint32_t cv:1;
2621 uint32_t req:4;
2622 uint32_t entry_length:16;
2623 uint32_t region_id:16;
2624#else /* __LITTLE_ENDIAN_BITFIELD */
2625 uint32_t req:4;
2626 uint32_t cv:1;
2627 uint32_t co:1;
2628 uint32_t ra:1;
2629 uint32_t rsvd:1;
2630 uint32_t type:8;
2631 uint32_t rsvd2:16;
2632 uint32_t region_id:16;
2633 uint32_t entry_length:16;
2634#endif
2635
2636 uint32_t resp_info;
2637 uint32_t byte_cnt;
2638 uint32_t data_offset;
2639};
2640
ed957684
JS		 2641struct hbq_mask {
2642#ifdef __BIG_ENDIAN_BITFIELD
2643 uint8_t tmatch;
2644 uint8_t tmask;
2645 uint8_t rctlmatch;
2646 uint8_t rctlmask;
2647#else /* __LITTLE_ENDIAN */
2648 uint8_t rctlmask;
2649 uint8_t rctlmatch;
2650 uint8_t tmask;
2651 uint8_t tmatch;
2652#endif
2653};
2654
2655
2656/* Structure for MB Command CONFIG_HBQ (7c) */
2657
2658struct config_hbq_var {
2659#ifdef __BIG_ENDIAN_BITFIELD
2660 uint32_t rsvd1 :7;
2661 uint32_t recvNotify :1; /* Receive Notification */
2662 uint32_t numMask :8; /* # Mask Entries */
2663 uint32_t profile :8; /* Selection Profile */
2664 uint32_t rsvd2 :8;
2665#else /* __LITTLE_ENDIAN */
2666 uint32_t rsvd2 :8;
2667 uint32_t profile :8; /* Selection Profile */
2668 uint32_t numMask :8; /* # Mask Entries */
2669 uint32_t recvNotify :1; /* Receive Notification */
2670 uint32_t rsvd1 :7;
2671#endif
2672
2673#ifdef __BIG_ENDIAN_BITFIELD
2674 uint32_t hbqId :16;
2675 uint32_t rsvd3 :12;
2676 uint32_t ringMask :4;
2677#else /* __LITTLE_ENDIAN */
2678 uint32_t ringMask :4;
2679 uint32_t rsvd3 :12;
2680 uint32_t hbqId :16;
2681#endif
2682
2683#ifdef __BIG_ENDIAN_BITFIELD
2684 uint32_t entry_count :16;
2685 uint32_t rsvd4 :8;
2686 uint32_t headerLen :8;
2687#else /* __LITTLE_ENDIAN */
2688 uint32_t headerLen :8;
2689 uint32_t rsvd4 :8;
2690 uint32_t entry_count :16;
2691#endif
2692
2693 uint32_t hbqaddrLow;
2694 uint32_t hbqaddrHigh;
2695
2696#ifdef __BIG_ENDIAN_BITFIELD
2697 uint32_t rsvd5 :31;
2698 uint32_t logEntry :1;
2699#else /* __LITTLE_ENDIAN */
2700 uint32_t logEntry :1;
2701 uint32_t rsvd5 :31;
2702#endif
2703
2704 uint32_t rsvd6; /* w7 */
2705 uint32_t rsvd7; /* w8 */
2706 uint32_t rsvd8; /* w9 */
2707
2708 struct hbq_mask hbqMasks[6];
2709
2710
2711 union {
2712 uint32_t allprofiles[12];
2713
2714 struct {
2715 #ifdef __BIG_ENDIAN_BITFIELD
2716 uint32_t seqlenoff :16;
2717 uint32_t maxlen :16;
2718 #else /* __LITTLE_ENDIAN */
2719 uint32_t maxlen :16;
2720 uint32_t seqlenoff :16;
2721 #endif
2722 #ifdef __BIG_ENDIAN_BITFIELD
2723 uint32_t rsvd1 :28;
2724 uint32_t seqlenbcnt :4;
2725 #else /* __LITTLE_ENDIAN */
2726 uint32_t seqlenbcnt :4;
2727 uint32_t rsvd1 :28;
2728 #endif
2729 uint32_t rsvd[10];
2730 } profile2;
2731
2732 struct {
2733 #ifdef __BIG_ENDIAN_BITFIELD
2734 uint32_t seqlenoff :16;
2735 uint32_t maxlen :16;
2736 #else /* __LITTLE_ENDIAN */
2737 uint32_t maxlen :16;
2738 uint32_t seqlenoff :16;
2739 #endif
2740 #ifdef __BIG_ENDIAN_BITFIELD
2741 uint32_t cmdcodeoff :28;
2742 uint32_t rsvd1 :12;
2743 uint32_t seqlenbcnt :4;
2744 #else /* __LITTLE_ENDIAN */
2745 uint32_t seqlenbcnt :4;
2746 uint32_t rsvd1 :12;
2747 uint32_t cmdcodeoff :28;
2748 #endif
2749 uint32_t cmdmatch[8];
2750
2751 uint32_t rsvd[2];
2752 } profile3;
2753
2754 struct {
2755 #ifdef __BIG_ENDIAN_BITFIELD
2756 uint32_t seqlenoff :16;
2757 uint32_t maxlen :16;
2758 #else /* __LITTLE_ENDIAN */
2759 uint32_t maxlen :16;
2760 uint32_t seqlenoff :16;
2761 #endif
2762 #ifdef __BIG_ENDIAN_BITFIELD
2763 uint32_t cmdcodeoff :28;
2764 uint32_t rsvd1 :12;
2765 uint32_t seqlenbcnt :4;
2766 #else /* __LITTLE_ENDIAN */
2767 uint32_t seqlenbcnt :4;
2768 uint32_t rsvd1 :12;
2769 uint32_t cmdcodeoff :28;
2770 #endif
2771 uint32_t cmdmatch[8];
2772
2773 uint32_t rsvd[2];
2774 } profile5;
2775
2776 } profiles;
2777
2778};
2779
2780
dea3101e 2781
2e0fef85 2782/* Structure for MB Command CONFIG_PORT (0x88) */
dea3101e 2783typedef struct {
ed957684
JS		 2784#ifdef __BIG_ENDIAN_BITFIELD
2785 uint32_t cBE : 1;
2786 uint32_t cET : 1;
2787 uint32_t cHpcb : 1;
2788 uint32_t cMA : 1;
2789 uint32_t sli_mode : 4;
2790 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2791 * config block */
2792#else /* __LITTLE_ENDIAN */
2793 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2794 * config block */
2795 uint32_t sli_mode : 4;
2796 uint32_t cMA : 1;
2797 uint32_t cHpcb : 1;
2798 uint32_t cET : 1;
2799 uint32_t cBE : 1;
2800#endif
2801
dea3101e 2802 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2803 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
97207482
JS		 2804 uint32_t hbainit[5];
2805#ifdef __BIG_ENDIAN_BITFIELD
2806 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
2807 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
2808#else /* __LITTLE_ENDIAN */
2809 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
2810 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
2811#endif
ed957684
JS		 2812
2813#ifdef __BIG_ENDIAN_BITFIELD
da0436e9
JS		 2814 uint32_t rsvd1 : 19; /* Reserved */
2815 uint32_t cdss : 1; /* Configure Data Security SLI */
2816 uint32_t rsvd2 : 3; /* Reserved */
81301a9b
JS		 2817 uint32_t cbg : 1; /* Configure BlockGuard */
2818 uint32_t cmv : 1; /* Configure Max VPIs */
ed957684
JS		 2819 uint32_t ccrp : 1; /* Config Command Ring Polling */
2820 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2821 uint32_t chbs : 1; /* Cofigure Host Backing store */
2822 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2823 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2824 uint32_t cmx : 1; /* Configure Max XRIs */
2825 uint32_t cmr : 1; /* Configure Max RPIs */
2826#else /* __LITTLE_ENDIAN */
2827 uint32_t cmr : 1; /* Configure Max RPIs */
2828 uint32_t cmx : 1; /* Configure Max XRIs */
2829 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2830 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2831 uint32_t chbs : 1; /* Cofigure Host Backing store */
2832 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2833 uint32_t ccrp : 1; /* Config Command Ring Polling */
2834 uint32_t cmv : 1; /* Configure Max VPIs */
81301a9b 2835 uint32_t cbg : 1; /* Configure BlockGuard */
da0436e9
JS		 2836 uint32_t rsvd2 : 3; /* Reserved */
2837 uint32_t cdss : 1; /* Configure Data Security SLI */
2838 uint32_t rsvd1 : 19; /* Reserved */
ed957684
JS		 2839#endif
2840#ifdef __BIG_ENDIAN_BITFIELD
da0436e9
JS		 2841 uint32_t rsvd3 : 19; /* Reserved */
2842 uint32_t gdss : 1; /* Configure Data Security SLI */
2843 uint32_t rsvd4 : 3; /* Reserved */
81301a9b 2844 uint32_t gbg : 1; /* Grant BlockGuard */
ed957684
JS		 2845 uint32_t gmv : 1; /* Grant Max VPIs */
2846 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2847 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2848 uint32_t ghbs : 1; /* Grant Host Backing Store */
2849 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2850 uint32_t gerbm : 1; /* Grant ERBM Request */
2851 uint32_t gmx : 1; /* Grant Max XRIs */
2852 uint32_t gmr : 1; /* Grant Max RPIs */
2853#else /* __LITTLE_ENDIAN */
2854 uint32_t gmr : 1; /* Grant Max RPIs */
2855 uint32_t gmx : 1; /* Grant Max XRIs */
2856 uint32_t gerbm : 1; /* Grant ERBM Request */
2857 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2858 uint32_t ghbs : 1; /* Grant Host Backing Store */
2859 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2860 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2861 uint32_t gmv : 1; /* Grant Max VPIs */
81301a9b 2862 uint32_t gbg : 1; /* Grant BlockGuard */
da0436e9
JS		 2863 uint32_t rsvd4 : 3; /* Reserved */
2864 uint32_t gdss : 1; /* Configure Data Security SLI */
2865 uint32_t rsvd3 : 19; /* Reserved */
ed957684
JS		 2866#endif
2867
2868#ifdef __BIG_ENDIAN_BITFIELD
2869 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2870 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2871#else /* __LITTLE_ENDIAN */
2872 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2873 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2874#endif
2875
2876#ifdef __BIG_ENDIAN_BITFIELD
2877 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
da0436e9 2878 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
ed957684 2879#else /* __LITTLE_ENDIAN */
da0436e9 2880 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
ed957684
JS		 2881 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2882#endif
2883
da0436e9 2884 uint32_t rsvd6; /* Reserved */
ed957684
JS		 2885
2886#ifdef __BIG_ENDIAN_BITFIELD
bc73905a
JS		 2887 uint32_t fips_rev : 3; /* FIPS Spec Revision */
2888 uint32_t fips_level : 4; /* FIPS Level */
2889 uint32_t sec_err : 9; /* security crypto error */
ed957684
JS		 2890 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2891#else /* __LITTLE_ENDIAN */
2892 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
bc73905a
JS		 2893 uint32_t sec_err : 9; /* security crypto error */
2894 uint32_t fips_level : 4; /* FIPS Level */
2895 uint32_t fips_rev : 3; /* FIPS Spec Revision */
ed957684
JS		 2896#endif
2897
dea3101e 2898} CONFIG_PORT_VAR;
2899
9399627f
JS		 2900/* Structure for MB Command CONFIG_MSI (0x30) */
2901struct config_msi_var {
2902#ifdef __BIG_ENDIAN_BITFIELD
2903 uint32_t dfltMsgNum:8; /* Default message number */
2904 uint32_t rsvd1:11; /* Reserved */
2905 uint32_t NID:5; /* Number of secondary attention IDs */
2906 uint32_t rsvd2:5; /* Reserved */
2907 uint32_t dfltPresent:1; /* Default message number present */
2908 uint32_t addFlag:1; /* Add association flag */
2909 uint32_t reportFlag:1; /* Report association flag */
2910#else /* __LITTLE_ENDIAN_BITFIELD */
2911 uint32_t reportFlag:1; /* Report association flag */
2912 uint32_t addFlag:1; /* Add association flag */
2913 uint32_t dfltPresent:1; /* Default message number present */
2914 uint32_t rsvd2:5; /* Reserved */
2915 uint32_t NID:5; /* Number of secondary attention IDs */
2916 uint32_t rsvd1:11; /* Reserved */
2917 uint32_t dfltMsgNum:8; /* Default message number */
2918#endif
2919 uint32_t attentionConditions[2];
2920 uint8_t attentionId[16];
2921 uint8_t messageNumberByHA[64];
2922 uint8_t messageNumberByID[16];
2923 uint32_t autoClearHA[2];
2924#ifdef __BIG_ENDIAN_BITFIELD
2925 uint32_t rsvd3:16;
2926 uint32_t autoClearID:16;
2927#else /* __LITTLE_ENDIAN_BITFIELD */
2928 uint32_t autoClearID:16;
2929 uint32_t rsvd3:16;
2930#endif
2931 uint32_t rsvd4;
2932};
2933
dea3101e 2934/* SLI-2 Port Control Block */
2935
2936/* SLIM POINTER */
2937#define SLIMOFF 0x30 /* WORD */
2938
2939typedef struct _SLI2_RDSC {
2940 uint32_t cmdEntries;
2941 uint32_t cmdAddrLow;
2942 uint32_t cmdAddrHigh;
2943
2944 uint32_t rspEntries;
2945 uint32_t rspAddrLow;
2946 uint32_t rspAddrHigh;
2947} SLI2_RDSC;
2948
2949typedef struct _PCB {
2950#ifdef __BIG_ENDIAN_BITFIELD
2951 uint32_t type:8;
2952#define TYPE_NATIVE_SLI2 0x01;
2953 uint32_t feature:8;
2954#define FEATURE_INITIAL_SLI2 0x01;
2955 uint32_t rsvd:12;
2956 uint32_t maxRing:4;
2957#else /* __LITTLE_ENDIAN_BITFIELD */
2958 uint32_t maxRing:4;
2959 uint32_t rsvd:12;
2960 uint32_t feature:8;
2961#define FEATURE_INITIAL_SLI2 0x01;
2962 uint32_t type:8;
2963#define TYPE_NATIVE_SLI2 0x01;
2964#endif
2965
2966 uint32_t mailBoxSize;
2967 uint32_t mbAddrLow;
2968 uint32_t mbAddrHigh;
2969
2970 uint32_t hgpAddrLow;
2971 uint32_t hgpAddrHigh;
2972
2973 uint32_t pgpAddrLow;
2974 uint32_t pgpAddrHigh;
2975 SLI2_RDSC rdsc[MAX_RINGS];
2976} PCB_t;
2977
2978/* NEW_FEATURE */
2979typedef struct {
2980#ifdef __BIG_ENDIAN_BITFIELD
2981 uint32_t rsvd0:27;
2982 uint32_t discardFarp:1;
2983 uint32_t IPEnable:1;
2984 uint32_t nodeName:1;
2985 uint32_t portName:1;
2986 uint32_t filterEnable:1;
2987#else /* __LITTLE_ENDIAN_BITFIELD */
2988 uint32_t filterEnable:1;
2989 uint32_t portName:1;
2990 uint32_t nodeName:1;
2991 uint32_t IPEnable:1;
2992 uint32_t discardFarp:1;
2993 uint32_t rsvd:27;
2994#endif
2995
2996 uint8_t portname[8]; /* Used to be struct lpfc_name */
2997 uint8_t nodename[8];
2998 uint32_t rsvd1;
2999 uint32_t rsvd2;
3000 uint32_t rsvd3;
3001 uint32_t IPAddress;
3002} CONFIG_FARP_VAR;
3003
57127f15
JS		 3004/* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3005
3006typedef struct {
3007#ifdef __BIG_ENDIAN_BITFIELD
3008 uint32_t rsvd:30;
3009 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3010#else /* __LITTLE_ENDIAN */
3011 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3012 uint32_t rsvd:30;
3013#endif
3014} ASYNCEVT_ENABLE_VAR;
3015
dea3101e 3016/* Union of all Mailbox Command types */
3017#define MAILBOX_CMD_WSIZE 32
3018#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
7a470277
JS		 3019/* ext_wsize times 4 bytes should not be greater than max xmit size */
3020#define MAILBOX_EXT_WSIZE 512
3021#define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3022#define MAILBOX_HBA_EXT_OFFSET 0x100
3023/* max mbox xmit size is a page size for sysfs IO operations */
3024#define MAILBOX_MAX_XMIT_SIZE PAGE_SIZE
dea3101e 3025
3026typedef union {
ed957684
JS		 3027 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3028 * feature/max ring number
3029 */
3030 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3031 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3032 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
311464ec
JS		 3033 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3034 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
dea3101e 3035 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
ed957684
JS		 3036 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3037 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
dea3101e 3038 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3039 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3040 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3041 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3042 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3043 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
ed957684
JS		 3044 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3045 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3046 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3047 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
dea3101e 3048 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3049 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
dea3101e 3050 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
ed957684
JS		 3051 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3052 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3053 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3054 * NEW_FEATURE
3055 */
3056 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
d7c255b2 3057 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
ed957684 3058 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
76a95d75 3059 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
92d7f7b0
JS		 3060 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3061 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
57127f15 3062 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
c7495937
JS		 3063 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3064 * (READ_EVENT_LOG)
3065 */
9399627f 3066 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
dea3101e 3067} MAILVARIANTS;
3068
3069/*
3070 * SLI-2 specific structures
3071 */
3072
4cc2da1d
JSEC		 3073struct lpfc_hgp {
3074 __le32 cmdPutInx;
3075 __le32 rspGetInx;
3076};
dea3101e 3077
4cc2da1d
JSEC		 3078struct lpfc_pgp {
3079 __le32 cmdGetInx;
3080 __le32 rspPutInx;
3081};
dea3101e 3082
ed957684 3083struct sli2_desc {
dea3101e 3084 uint32_t unused1[16];
ed957684
JS		 3085 struct lpfc_hgp host[MAX_RINGS];
3086 struct lpfc_pgp port[MAX_RINGS];
3087};
3088
3089struct sli3_desc {
3090 struct lpfc_hgp host[MAX_RINGS];
3091 uint32_t reserved[8];
3092 uint32_t hbq_put[16];
3093};
3094
3095struct sli3_pgp {
4cc2da1d 3096 struct lpfc_pgp port[MAX_RINGS];
ed957684
JS		 3097 uint32_t hbq_get[16];
3098};
dea3101e 3099
34b02dcd
JS		 3100union sli_var {
3101 struct sli2_desc s2;
3102 struct sli3_desc s3;
3103 struct sli3_pgp s3_pgp;
34b02dcd 3104};
dea3101e 3105
3106typedef struct {
3107#ifdef __BIG_ENDIAN_BITFIELD
3108 uint16_t mbxStatus;
3109 uint8_t mbxCommand;
3110 uint8_t mbxReserved:6;
3111 uint8_t mbxHc:1;
3112 uint8_t mbxOwner:1; /* Low order bit first word */
3113#else /* __LITTLE_ENDIAN_BITFIELD */
3114 uint8_t mbxOwner:1; /* Low order bit first word */
3115 uint8_t mbxHc:1;
3116 uint8_t mbxReserved:6;
3117 uint8_t mbxCommand;
3118 uint16_t mbxStatus;
3119#endif
3120
3121 MAILVARIANTS un;
34b02dcd 3122 union sli_var us;
dea3101e 3123} MAILBOX_t;
3124
3125/*
3126 * Begin Structure Definitions for IOCB Commands
3127 */
3128
3129typedef struct {
3130#ifdef __BIG_ENDIAN_BITFIELD
3131 uint8_t statAction;
3132 uint8_t statRsn;
3133 uint8_t statBaExp;
3134 uint8_t statLocalError;
3135#else /* __LITTLE_ENDIAN_BITFIELD */
3136 uint8_t statLocalError;
3137 uint8_t statBaExp;
3138 uint8_t statRsn;
3139 uint8_t statAction;
3140#endif
3141 /* statRsn P/F_RJT reason codes */
3142#define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3143#define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3144#define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3145#define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3146#define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3147#define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3148#define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3149#define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3150#define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3151#define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3152#define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3153#define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3154#define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3155#define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3156#define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3157#define RJT_BAD_PARM 0x10 /* Param. field invalid */
3158#define RJT_XCHG_ERR 0x11 /* Exchange error */
3159#define RJT_PROT_ERR 0x12 /* Protocol error */
3160#define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3161#define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3162#define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3163#define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3164#define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3165#define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3166#define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3167#define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3168
3169#define IOERR_SUCCESS 0x00 /* statLocalError */
3170#define IOERR_MISSING_CONTINUE 0x01
3171#define IOERR_SEQUENCE_TIMEOUT 0x02
3172#define IOERR_INTERNAL_ERROR 0x03
3173#define IOERR_INVALID_RPI 0x04
3174#define IOERR_NO_XRI 0x05
3175#define IOERR_ILLEGAL_COMMAND 0x06
3176#define IOERR_XCHG_DROPPED 0x07
3177#define IOERR_ILLEGAL_FIELD 0x08
3178#define IOERR_BAD_CONTINUE 0x09
3179#define IOERR_TOO_MANY_BUFFERS 0x0A
3180#define IOERR_RCV_BUFFER_WAITING 0x0B
3181#define IOERR_NO_CONNECTION 0x0C
3182#define IOERR_TX_DMA_FAILED 0x0D
3183#define IOERR_RX_DMA_FAILED 0x0E
3184#define IOERR_ILLEGAL_FRAME 0x0F
3185#define IOERR_EXTRA_DATA 0x10
3186#define IOERR_NO_RESOURCES 0x11
3187#define IOERR_RESERVED 0x12
3188#define IOERR_ILLEGAL_LENGTH 0x13
3189#define IOERR_UNSUPPORTED_FEATURE 0x14
3190#define IOERR_ABORT_IN_PROGRESS 0x15
3191#define IOERR_ABORT_REQUESTED 0x16
3192#define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3193#define IOERR_LOOP_OPEN_FAILURE 0x18
3194#define IOERR_RING_RESET 0x19
3195#define IOERR_LINK_DOWN 0x1A
3196#define IOERR_CORRUPTED_DATA 0x1B
3197#define IOERR_CORRUPTED_RPI 0x1C
3198#define IOERR_OUT_OF_ORDER_DATA 0x1D
3199#define IOERR_OUT_OF_ORDER_ACK 0x1E
3200#define IOERR_DUP_FRAME 0x1F
3201#define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3202#define IOERR_BAD_HOST_ADDRESS 0x21
3203#define IOERR_RCV_HDRBUF_WAITING 0x22
3204#define IOERR_MISSING_HDR_BUFFER 0x23
3205#define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3206#define IOERR_ABORTMULT_REQUESTED 0x25
3207#define IOERR_BUFFER_SHORTAGE 0x28
3208#define IOERR_DEFAULT 0x29
3209#define IOERR_CNT 0x2A
b92938b4
JS		 3210#define IOERR_SLER_FAILURE 0x46
3211#define IOERR_SLER_CMD_RCV_FAILURE 0x47
3212#define IOERR_SLER_REC_RJT_ERR 0x48
3213#define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3214#define IOERR_SLER_SRR_RJT_ERR 0x4A
3215#define IOERR_SLER_RRQ_RJT_ERR 0x4C
3216#define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3217#define IOERR_SLER_ABTS_ERR 0x4E
ab56dc2e
JS		 3218#define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3219#define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3220#define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3221#define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
dea3101e 3222#define IOERR_DRVR_MASK 0x100
3223#define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3224#define IOERR_SLI_BRESET 0x102
3225#define IOERR_SLI_ABORTED 0x103
3226} PARM_ERR;
3227
3228typedef union {
3229 struct {
3230#ifdef __BIG_ENDIAN_BITFIELD
3231 uint8_t Rctl; /* R_CTL field */
3232 uint8_t Type; /* TYPE field */
3233 uint8_t Dfctl; /* DF_CTL field */
3234 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3235#else /* __LITTLE_ENDIAN_BITFIELD */
3236 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3237 uint8_t Dfctl; /* DF_CTL field */
3238 uint8_t Type; /* TYPE field */
3239 uint8_t Rctl; /* R_CTL field */
3240#endif
3241
3242#define BC 0x02 /* Broadcast Received - Fctl */
3243#define SI 0x04 /* Sequence Initiative */
3244#define LA 0x08 /* Ignore Link Attention state */
3245#define LS 0x80 /* Last Sequence */
3246 } hcsw;
3247 uint32_t reserved;
3248} WORD5;
3249
3250/* IOCB Command template for a generic response */
3251typedef struct {
3252 uint32_t reserved[4];
3253 PARM_ERR perr;
3254} GENERIC_RSP;
3255
3256/* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3257typedef struct {
3258 struct ulp_bde xrsqbde[2];
3259 uint32_t xrsqRo; /* Starting Relative Offset */
3260 WORD5 w5; /* Header control/status word */
3261} XR_SEQ_FIELDS;
3262
3263/* IOCB Command template for ELS_REQUEST */
3264typedef struct {
3265 struct ulp_bde elsReq;
3266 struct ulp_bde elsRsp;
3267
3268#ifdef __BIG_ENDIAN_BITFIELD
3269 uint32_t word4Rsvd:7;
3270 uint32_t fl:1;
3271 uint32_t myID:24;
3272 uint32_t word5Rsvd:8;
3273 uint32_t remoteID:24;
3274#else /* __LITTLE_ENDIAN_BITFIELD */
3275 uint32_t myID:24;
3276 uint32_t fl:1;
3277 uint32_t word4Rsvd:7;
3278 uint32_t remoteID:24;
3279 uint32_t word5Rsvd:8;
3280#endif
3281} ELS_REQUEST;
3282
3283/* IOCB Command template for RCV_ELS_REQ */
3284typedef struct {
3285 struct ulp_bde elsReq[2];
3286 uint32_t parmRo;
3287
3288#ifdef __BIG_ENDIAN_BITFIELD
3289 uint32_t word5Rsvd:8;
3290 uint32_t remoteID:24;
3291#else /* __LITTLE_ENDIAN_BITFIELD */
3292 uint32_t remoteID:24;
3293 uint32_t word5Rsvd:8;
3294#endif
3295} RCV_ELS_REQ;
3296
3297/* IOCB Command template for ABORT / CLOSE_XRI */
3298typedef struct {
3299 uint32_t rsvd[3];
3300 uint32_t abortType;
3301#define ABORT_TYPE_ABTX 0x00000000
3302#define ABORT_TYPE_ABTS 0x00000001
3303 uint32_t parm;
3304#ifdef __BIG_ENDIAN_BITFIELD
3305 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3306 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3307#else /* __LITTLE_ENDIAN_BITFIELD */
3308 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3309 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3310#endif
3311} AC_XRI;
3312
3313/* IOCB Command template for ABORT_MXRI64 */
3314typedef struct {
3315 uint32_t rsvd[3];
3316 uint32_t abortType;
3317 uint32_t parm;
3318 uint32_t iotag32;
3319} A_MXRI64;
3320
3321/* IOCB Command template for GET_RPI */
3322typedef struct {
3323 uint32_t rsvd[4];
3324 uint32_t parmRo;
3325#ifdef __BIG_ENDIAN_BITFIELD
3326 uint32_t word5Rsvd:8;
3327 uint32_t remoteID:24;
3328#else /* __LITTLE_ENDIAN_BITFIELD */
3329 uint32_t remoteID:24;
3330 uint32_t word5Rsvd:8;
3331#endif
3332} GET_RPI;
3333
3334/* IOCB Command template for all FCP Initiator commands */
3335typedef struct {
3336 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3337 struct ulp_bde fcpi_rsp; /* Rcv buffer */
3338 uint32_t fcpi_parm;
3339 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3340} FCPI_FIELDS;
3341
3342/* IOCB Command template for all FCP Target commands */
3343typedef struct {
3344 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3345 uint32_t fcpt_Offset;
3346 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3347} FCPT_FIELDS;
3348
3349/* SLI-2 IOCB structure definitions */
3350
3351/* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3352typedef struct {
3353 ULP_BDL bdl;
3354 uint32_t xrsqRo; /* Starting Relative Offset */
3355 WORD5 w5; /* Header control/status word */
3356} XMT_SEQ_FIELDS64;
3357
3358/* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3359typedef struct {
3360 struct ulp_bde64 rcvBde;
3361 uint32_t rsvd1;
3362 uint32_t xrsqRo; /* Starting Relative Offset */
3363 WORD5 w5; /* Header control/status word */
3364} RCV_SEQ_FIELDS64;
3365
3366/* IOCB Command template for ELS_REQUEST64 */
3367typedef struct {
3368 ULP_BDL bdl;
3369#ifdef __BIG_ENDIAN_BITFIELD
3370 uint32_t word4Rsvd:7;
3371 uint32_t fl:1;
3372 uint32_t myID:24;
3373 uint32_t word5Rsvd:8;
3374 uint32_t remoteID:24;
3375#else /* __LITTLE_ENDIAN_BITFIELD */
3376 uint32_t myID:24;
3377 uint32_t fl:1;
3378 uint32_t word4Rsvd:7;
3379 uint32_t remoteID:24;
3380 uint32_t word5Rsvd:8;
3381#endif
3382} ELS_REQUEST64;
3383
3384/* IOCB Command template for GEN_REQUEST64 */
3385typedef struct {
3386 ULP_BDL bdl;
3387 uint32_t xrsqRo; /* Starting Relative Offset */
3388 WORD5 w5; /* Header control/status word */
3389} GEN_REQUEST64;
3390
3391/* IOCB Command template for RCV_ELS_REQ64 */
3392typedef struct {
3393 struct ulp_bde64 elsReq;
3394 uint32_t rcvd1;
3395 uint32_t parmRo;
3396
3397#ifdef __BIG_ENDIAN_BITFIELD
3398 uint32_t word5Rsvd:8;
3399 uint32_t remoteID:24;
3400#else /* __LITTLE_ENDIAN_BITFIELD */
3401 uint32_t remoteID:24;
3402 uint32_t word5Rsvd:8;
3403#endif
3404} RCV_ELS_REQ64;
3405
9c2face6
JS		 3406/* IOCB Command template for RCV_SEQ64 */
3407struct rcv_seq64 {
3408 struct ulp_bde64 elsReq;
3409 uint32_t hbq_1;
3410 uint32_t parmRo;
3411#ifdef __BIG_ENDIAN_BITFIELD
3412 uint32_t rctl:8;
3413 uint32_t type:8;
3414 uint32_t dfctl:8;
3415 uint32_t ls:1;
3416 uint32_t fs:1;
3417 uint32_t rsvd2:3;
3418 uint32_t si:1;
3419 uint32_t bc:1;
3420 uint32_t rsvd3:1;
3421#else /* __LITTLE_ENDIAN_BITFIELD */
3422 uint32_t rsvd3:1;
3423 uint32_t bc:1;
3424 uint32_t si:1;
3425 uint32_t rsvd2:3;
3426 uint32_t fs:1;
3427 uint32_t ls:1;
3428 uint32_t dfctl:8;
3429 uint32_t type:8;
3430 uint32_t rctl:8;
3431#endif
3432};
3433
dea3101e 3434/* IOCB Command template for all 64 bit FCP Initiator commands */
3435typedef struct {
3436 ULP_BDL bdl;
3437 uint32_t fcpi_parm;
3438 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3439} FCPI_FIELDS64;
3440
3441/* IOCB Command template for all 64 bit FCP Target commands */
3442typedef struct {
3443 ULP_BDL bdl;
3444 uint32_t fcpt_Offset;
3445 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3446} FCPT_FIELDS64;
3447
57127f15
JS		 3448/* IOCB Command template for Async Status iocb commands */
3449typedef struct {
3450 uint32_t rsvd[4];
3451 uint32_t param;
3452#ifdef __BIG_ENDIAN_BITFIELD
3453 uint16_t evt_code; /* High order bits word 5 */
3454 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3455#else /* __LITTLE_ENDIAN_BITFIELD */
3456 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3457 uint16_t evt_code; /* Low order bits word 5 */
3458#endif
3459} ASYNCSTAT_FIELDS;
3460#define ASYNC_TEMP_WARN 0x100
3461#define ASYNC_TEMP_SAFE 0x101
3462
ed957684
JS		 3463/* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3464 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3465
3466struct rcv_sli3 {
3467 uint32_t word8Rsvd;
3468#ifdef __BIG_ENDIAN_BITFIELD
3469 uint16_t vpi;
3470 uint16_t word9Rsvd;
3471#else /* __LITTLE_ENDIAN */
3472 uint16_t word9Rsvd;
3473 uint16_t vpi;
3474#endif
3475 uint32_t word10Rsvd;
3476 uint32_t acc_len; /* accumulated length */
3477 struct ulp_bde64 bde2;
3478};
3479
76bb24ef
JS		 3480/* Structure used for a single HBQ entry */
3481struct lpfc_hbq_entry {
3482 struct ulp_bde64 bde;
3483 uint32_t buffer_tag;
3484};
92d7f7b0 3485
76bb24ef
JS		 3486/* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3487typedef struct {
3488 struct lpfc_hbq_entry buff;
3489 uint32_t rsvd;
3490 uint32_t rsvd1;
3491} QUE_XRI64_CX_FIELDS;
3492
3493struct que_xri64cx_ext_fields {
3494 uint32_t iotag64_low;
3495 uint32_t iotag64_high;
3496 uint32_t ebde_count;
3497 uint32_t rsvd;
3498 struct lpfc_hbq_entry buff[5];
3499};
92d7f7b0 3500
81301a9b
JS		 3501struct sli3_bg_fields {
3502 uint32_t filler[6]; /* word 8-13 in IOCB */
3503 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
3504/* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3505#define BGS_BIDIR_BG_PROF_MASK 0xff000000
3506#define BGS_BIDIR_BG_PROF_SHIFT 24
3507#define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3508#define BGS_BIDIR_ERR_COND_SHIFT 16
3509#define BGS_BG_PROFILE_MASK 0x0000ff00
3510#define BGS_BG_PROFILE_SHIFT 8
3511#define BGS_INVALID_PROF_MASK 0x00000020
3512#define BGS_INVALID_PROF_SHIFT 5
3513#define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3514#define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3515#define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3516#define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3517#define BGS_REFTAG_ERR_MASK 0x00000004
3518#define BGS_REFTAG_ERR_SHIFT 2
3519#define BGS_APPTAG_ERR_MASK 0x00000002
3520#define BGS_APPTAG_ERR_SHIFT 1
3521#define BGS_GUARD_ERR_MASK 0x00000001
3522#define BGS_GUARD_ERR_SHIFT 0
3523 uint32_t bgstat; /* word 15 - BlockGuard Status */
3524};
3525
3526static inline uint32_t
3527lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3528{
bc73905a 3529 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
81301a9b
JS		 3530 BGS_BIDIR_BG_PROF_SHIFT;
3531}
3532
3533static inline uint32_t
3534lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3535{
bc73905a 3536 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
81301a9b
JS		 3537 BGS_BIDIR_ERR_COND_SHIFT;
3538}
3539
3540static inline uint32_t
3541lpfc_bgs_get_bg_prof(uint32_t bgstat)
3542{
bc73905a 3543 return (bgstat & BGS_BG_PROFILE_MASK) >>
81301a9b
JS		 3544 BGS_BG_PROFILE_SHIFT;
3545}
3546
3547static inline uint32_t
3548lpfc_bgs_get_invalid_prof(uint32_t bgstat)
3549{
bc73905a 3550 return (bgstat & BGS_INVALID_PROF_MASK) >>
81301a9b
JS		 3551 BGS_INVALID_PROF_SHIFT;
3552}
3553
3554static inline uint32_t
3555lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
3556{
bc73905a 3557 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
81301a9b
JS		 3558 BGS_UNINIT_DIF_BLOCK_SHIFT;
3559}
3560
3561static inline uint32_t
3562lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
3563{
bc73905a 3564 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
81301a9b
JS		 3565 BGS_HI_WATER_MARK_PRESENT_SHIFT;
3566}
3567
3568static inline uint32_t
3569lpfc_bgs_get_reftag_err(uint32_t bgstat)
3570{
bc73905a 3571 return (bgstat & BGS_REFTAG_ERR_MASK) >>
81301a9b
JS		 3572 BGS_REFTAG_ERR_SHIFT;
3573}
3574
3575static inline uint32_t
3576lpfc_bgs_get_apptag_err(uint32_t bgstat)
3577{
bc73905a 3578 return (bgstat & BGS_APPTAG_ERR_MASK) >>
81301a9b
JS		 3579 BGS_APPTAG_ERR_SHIFT;
3580}
3581
3582static inline uint32_t
3583lpfc_bgs_get_guard_err(uint32_t bgstat)
3584{
bc73905a 3585 return (bgstat & BGS_GUARD_ERR_MASK) >>
81301a9b
JS		 3586 BGS_GUARD_ERR_SHIFT;
3587}
3588
34b02dcd
JS		 3589#define LPFC_EXT_DATA_BDE_COUNT 3
3590struct fcp_irw_ext {
3591 uint32_t io_tag64_low;
3592 uint32_t io_tag64_high;
3593#ifdef __BIG_ENDIAN_BITFIELD
3594 uint8_t reserved1;
3595 uint8_t reserved2;
3596 uint8_t reserved3;
3597 uint8_t ebde_count;
3598#else /* __LITTLE_ENDIAN */
3599 uint8_t ebde_count;
3600 uint8_t reserved3;
3601 uint8_t reserved2;
3602 uint8_t reserved1;
3603#endif
3604 uint32_t reserved4;
3605 struct ulp_bde64 rbde; /* response bde */
3606 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
3607 uint8_t icd[32]; /* immediate command data (32 bytes) */
3608};
3609
dea3101e 3610typedef struct _IOCB { /* IOCB structure */
3611 union {
3612 GENERIC_RSP grsp; /* Generic response */
3613 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
3614 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3615 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
3616 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
3617 A_MXRI64 amxri; /* abort multiple xri command overlay */
3618 GET_RPI getrpi; /* GET_RPI template */
3619 FCPI_FIELDS fcpi; /* FCP Initiator template */
3620 FCPT_FIELDS fcpt; /* FCP target template */
3621
3622 /* SLI-2 structures */
3623
ed957684
JS		 3624 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
3625 * bde_64s */
dea3101e 3626 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3627 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3628 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3629 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
3630 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
3631 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
57127f15 3632 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
76bb24ef 3633 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
9c2face6 3634 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
5ffc266e 3635 struct sli4_bls_acc bls_acc; /* UNSOL ABTS BLS_ACC params */
dea3101e 3636 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
3637 } un;
3638 union {
3639 struct {
3640#ifdef __BIG_ENDIAN_BITFIELD
3641 uint16_t ulpContext; /* High order bits word 6 */
3642 uint16_t ulpIoTag; /* Low order bits word 6 */
3643#else /* __LITTLE_ENDIAN_BITFIELD */
3644 uint16_t ulpIoTag; /* Low order bits word 6 */
3645 uint16_t ulpContext; /* High order bits word 6 */
3646#endif
3647 } t1;
3648 struct {
3649#ifdef __BIG_ENDIAN_BITFIELD
3650 uint16_t ulpContext; /* High order bits word 6 */
3651 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3652 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3653#else /* __LITTLE_ENDIAN_BITFIELD */
3654 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3655 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3656 uint16_t ulpContext; /* High order bits word 6 */
3657#endif
3658 } t2;
3659 } un1;
3660#define ulpContext un1.t1.ulpContext
3661#define ulpIoTag un1.t1.ulpIoTag
3662#define ulpIoTag0 un1.t2.ulpIoTag0
3663
3664#ifdef __BIG_ENDIAN_BITFIELD
3665 uint32_t ulpTimeout:8;
3666 uint32_t ulpXS:1;
3667 uint32_t ulpFCP2Rcvy:1;
3668 uint32_t ulpPU:2;
3669 uint32_t ulpIr:1;
3670 uint32_t ulpClass:3;
3671 uint32_t ulpCommand:8;
3672 uint32_t ulpStatus:4;
3673 uint32_t ulpBdeCount:2;
3674 uint32_t ulpLe:1;
3675 uint32_t ulpOwner:1; /* Low order bit word 7 */
3676#else /* __LITTLE_ENDIAN_BITFIELD */
3677 uint32_t ulpOwner:1; /* Low order bit word 7 */
3678 uint32_t ulpLe:1;
3679 uint32_t ulpBdeCount:2;
3680 uint32_t ulpStatus:4;
3681 uint32_t ulpCommand:8;
3682 uint32_t ulpClass:3;
3683 uint32_t ulpIr:1;
3684 uint32_t ulpPU:2;
3685 uint32_t ulpFCP2Rcvy:1;
3686 uint32_t ulpXS:1;
3687 uint32_t ulpTimeout:8;
3688#endif
92d7f7b0 3689
ed957684
JS		 3690 union {
3691 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
76bb24ef
JS		 3692
3693 /* words 8-31 used for que_xri_cx iocb */
3694 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
34b02dcd 3695 struct fcp_irw_ext fcp_ext;
ed957684 3696 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
81301a9b
JS		 3697
3698 /* words 8-15 for BlockGuard */
3699 struct sli3_bg_fields sli3_bg;
ed957684
JS		 3700 } unsli3;
3701
3702#define ulpCt_h ulpXS
3703#define ulpCt_l ulpFCP2Rcvy
dea3101e 3704
ed957684
JS		 3705#define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3706#define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
dea3101e 3707#define PARM_UNUSED 0 /* PU field (Word 4) not used */
3708#define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
3709#define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
92d7f7b0 3710#define PARM_NPIV_DID 3
dea3101e 3711#define CLASS1 0 /* Class 1 */
3712#define CLASS2 1 /* Class 2 */
3713#define CLASS3 2 /* Class 3 */
3714#define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
3715
3716#define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
3717#define IOSTAT_FCP_RSP_ERROR 0x1
3718#define IOSTAT_REMOTE_STOP 0x2
3719#define IOSTAT_LOCAL_REJECT 0x3
3720#define IOSTAT_NPORT_RJT 0x4
3721#define IOSTAT_FABRIC_RJT 0x5
3722#define IOSTAT_NPORT_BSY 0x6
3723#define IOSTAT_FABRIC_BSY 0x7
3724#define IOSTAT_INTERMED_RSP 0x8
3725#define IOSTAT_LS_RJT 0x9
3726#define IOSTAT_BA_RJT 0xA
3727#define IOSTAT_RSVD1 0xB
3728#define IOSTAT_RSVD2 0xC
3729#define IOSTAT_RSVD3 0xD
3730#define IOSTAT_RSVD4 0xE
92d7f7b0 3731#define IOSTAT_NEED_BUFFER 0xF
dea3101e 3732#define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
3733#define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
3734#define IOSTAT_CNT 0x11
3735
3736} IOCB_t;
3737
3738
3739#define SLI1_SLIM_SIZE (4 * 1024)
3740
3741/* Up to 498 IOCBs will fit into 16k
3742 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3743 */
ed957684 3744#define SLI2_SLIM_SIZE (64 * 1024)
dea3101e 3745
3746/* Maximum IOCBs that will fit in SLI2 slim */
3747#define MAX_SLI2_IOCB 498
ed957684 3748#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
7a470277
JS		 3749 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
3750 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
ed957684
JS		 3751
3752/* HBQ entries are 4 words each = 4k */
3753#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
3754 lpfc_sli_hbq_count())
dea3101e 3755
3756struct lpfc_sli2_slim {
3757 MAILBOX_t mbx;
7a470277 3758 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
dea3101e 3759 PCB_t pcb;
ed957684 3760 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
dea3101e 3761};
3762
2e0fef85
JS		 3763/*
3764 * This function checks PCI device to allow special handling for LC HBAs.
3765 *
3766 * Parameters:
3767 * device : struct pci_dev 's device field
3768 *
3769 * return 1 => TRUE
3770 * 0 => FALSE
3771 */
dea3101e 3772static inline int
3773lpfc_is_LC_HBA(unsigned short device)
3774{
3775 if ((device == PCI_DEVICE_ID_TFLY) ||
3776 (device == PCI_DEVICE_ID_PFLY) ||
3777 (device == PCI_DEVICE_ID_LP101) ||
3778 (device == PCI_DEVICE_ID_BMID) ||
3779 (device == PCI_DEVICE_ID_BSMB) ||
3780 (device == PCI_DEVICE_ID_ZMID) ||
3781 (device == PCI_DEVICE_ID_ZSMB) ||
09372820
JS		 3782 (device == PCI_DEVICE_ID_SAT_MID) ||
3783 (device == PCI_DEVICE_ID_SAT_SMB) ||
dea3101e 3784 (device == PCI_DEVICE_ID_RFLY))
3785 return 1;
3786 else
3787 return 0;
3788}
858c9f6c
JS		 3789
3790/*
3791 * Determine if an IOCB failed because of a link event or firmware reset.
3792 */
3793
3794static inline int
3795lpfc_error_lost_link(IOCB_t *iocbp)
3796{
3797 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
3798 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
3799 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
3800 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
3801}
84774a4d
JS		 3802
3803#define MENLO_TRANSPORT_TYPE 0xfe
3804#define MENLO_CONTEXT 0
3805#define MENLO_PU 3
3806#define MENLO_TIMEOUT 30
3807#define SETVAR_MLOMNT 0x103107
3808#define SETVAR_MLORST 0x103007
da0436e9
JS		 3809
3810#define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
Linux kernel - Deliverables
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