Commit | Line | Data |
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dea3101e | 1 | /******************************************************************* |
2 | * This file is part of the Emulex Linux Device Driver for * | |
c44ce173 | 3 | * Fibre Channel Host Bus Adapters. * |
9413afff | 4 | * Copyright (C) 2004-2007 Emulex. All rights reserved. * |
c44ce173 | 5 | * EMULEX and SLI are trademarks of Emulex. * |
dea3101e | 6 | * www.emulex.com * |
c44ce173 | 7 | * Portions Copyright (C) 2004-2005 Christoph Hellwig * |
dea3101e | 8 | * * |
9 | * This program is free software; you can redistribute it and/or * | |
c44ce173 JSEC |
10 | * modify it under the terms of version 2 of the GNU General * |
11 | * Public License as published by the Free Software Foundation. * | |
12 | * This program is distributed in the hope that it will be useful. * | |
13 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * | |
14 | * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * | |
15 | * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * | |
16 | * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * | |
17 | * TO BE LEGALLY INVALID. See the GNU General Public License for * | |
18 | * more details, a copy of which can be found in the file COPYING * | |
19 | * included with this package. * | |
dea3101e | 20 | *******************************************************************/ |
21 | ||
dea3101e | 22 | #include <linux/blkdev.h> |
23 | #include <linux/pci.h> | |
24 | #include <linux/interrupt.h> | |
25 | ||
f888ba3c JSEC |
26 | #include <scsi/scsi_device.h> |
27 | #include <scsi/scsi_transport_fc.h> | |
28 | ||
91886523 JSEC |
29 | #include <scsi/scsi.h> |
30 | ||
dea3101e | 31 | #include "lpfc_hw.h" |
32 | #include "lpfc_sli.h" | |
33 | #include "lpfc_disc.h" | |
34 | #include "lpfc_scsi.h" | |
35 | #include "lpfc.h" | |
36 | #include "lpfc_logmsg.h" | |
37 | #include "lpfc_crtn.h" | |
38 | #include "lpfc_compat.h" | |
39 | ||
40 | /**********************************************/ | |
41 | ||
42 | /* mailbox command */ | |
43 | /**********************************************/ | |
44 | void | |
45 | lpfc_dump_mem(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb, uint16_t offset) | |
46 | { | |
47 | MAILBOX_t *mb; | |
48 | void *ctx; | |
49 | ||
50 | mb = &pmb->mb; | |
51 | ctx = pmb->context2; | |
52 | ||
53 | /* Setup to dump VPD region */ | |
54 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
55 | mb->mbxCommand = MBX_DUMP_MEMORY; | |
56 | mb->un.varDmp.cv = 1; | |
57 | mb->un.varDmp.type = DMP_NV_PARAMS; | |
58 | mb->un.varDmp.entry_index = offset; | |
59 | mb->un.varDmp.region_id = DMP_REGION_VPD; | |
60 | mb->un.varDmp.word_cnt = (DMP_RSP_SIZE / sizeof (uint32_t)); | |
61 | mb->un.varDmp.co = 0; | |
62 | mb->un.varDmp.resp_offset = 0; | |
63 | pmb->context2 = ctx; | |
64 | mb->mbxOwner = OWN_HOST; | |
65 | return; | |
66 | } | |
67 | ||
68 | /**********************************************/ | |
69 | /* lpfc_read_nv Issue a READ NVPARAM */ | |
70 | /* mailbox command */ | |
71 | /**********************************************/ | |
72 | void | |
73 | lpfc_read_nv(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
74 | { | |
75 | MAILBOX_t *mb; | |
76 | ||
77 | mb = &pmb->mb; | |
78 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
79 | mb->mbxCommand = MBX_READ_NV; | |
80 | mb->mbxOwner = OWN_HOST; | |
81 | return; | |
82 | } | |
83 | ||
858c9f6c JS |
84 | /**********************************************/ |
85 | /* lpfc_heart_beat Issue a HEART_BEAT */ | |
86 | /* mailbox command */ | |
87 | /**********************************************/ | |
88 | void | |
89 | lpfc_heart_beat(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
90 | { | |
91 | MAILBOX_t *mb; | |
92 | ||
93 | mb = &pmb->mb; | |
94 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
95 | mb->mbxCommand = MBX_HEARTBEAT; | |
96 | mb->mbxOwner = OWN_HOST; | |
97 | return; | |
98 | } | |
99 | ||
dea3101e | 100 | /**********************************************/ |
101 | /* lpfc_read_la Issue a READ LA */ | |
102 | /* mailbox command */ | |
103 | /**********************************************/ | |
104 | int | |
105 | lpfc_read_la(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb, struct lpfc_dmabuf *mp) | |
106 | { | |
107 | MAILBOX_t *mb; | |
108 | struct lpfc_sli *psli; | |
109 | ||
110 | psli = &phba->sli; | |
111 | mb = &pmb->mb; | |
112 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
113 | ||
114 | INIT_LIST_HEAD(&mp->list); | |
115 | mb->mbxCommand = MBX_READ_LA64; | |
116 | mb->un.varReadLA.un.lilpBde64.tus.f.bdeSize = 128; | |
117 | mb->un.varReadLA.un.lilpBde64.addrHigh = putPaddrHigh(mp->phys); | |
118 | mb->un.varReadLA.un.lilpBde64.addrLow = putPaddrLow(mp->phys); | |
119 | ||
120 | /* Save address for later completion and set the owner to host so that | |
121 | * the FW knows this mailbox is available for processing. | |
122 | */ | |
123 | pmb->context1 = (uint8_t *) mp; | |
124 | mb->mbxOwner = OWN_HOST; | |
92d7f7b0 | 125 | return (0); |
dea3101e | 126 | } |
127 | ||
128 | /**********************************************/ | |
129 | /* lpfc_clear_la Issue a CLEAR LA */ | |
130 | /* mailbox command */ | |
131 | /**********************************************/ | |
132 | void | |
133 | lpfc_clear_la(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
134 | { | |
135 | MAILBOX_t *mb; | |
136 | ||
137 | mb = &pmb->mb; | |
138 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
139 | ||
140 | mb->un.varClearLA.eventTag = phba->fc_eventTag; | |
141 | mb->mbxCommand = MBX_CLEAR_LA; | |
142 | mb->mbxOwner = OWN_HOST; | |
143 | return; | |
144 | } | |
145 | ||
146 | /**************************************************/ | |
147 | /* lpfc_config_link Issue a CONFIG LINK */ | |
148 | /* mailbox command */ | |
149 | /**************************************************/ | |
150 | void | |
151 | lpfc_config_link(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
152 | { | |
2e0fef85 | 153 | struct lpfc_vport *vport = phba->pport; |
dea3101e | 154 | MAILBOX_t *mb = &pmb->mb; |
155 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
156 | ||
157 | /* NEW_FEATURE | |
158 | * SLI-2, Coalescing Response Feature. | |
159 | */ | |
160 | if (phba->cfg_cr_delay) { | |
161 | mb->un.varCfgLnk.cr = 1; | |
162 | mb->un.varCfgLnk.ci = 1; | |
163 | mb->un.varCfgLnk.cr_delay = phba->cfg_cr_delay; | |
164 | mb->un.varCfgLnk.cr_count = phba->cfg_cr_count; | |
165 | } | |
166 | ||
2e0fef85 | 167 | mb->un.varCfgLnk.myId = vport->fc_myDID; |
dea3101e | 168 | mb->un.varCfgLnk.edtov = phba->fc_edtov; |
169 | mb->un.varCfgLnk.arbtov = phba->fc_arbtov; | |
170 | mb->un.varCfgLnk.ratov = phba->fc_ratov; | |
171 | mb->un.varCfgLnk.rttov = phba->fc_rttov; | |
172 | mb->un.varCfgLnk.altov = phba->fc_altov; | |
173 | mb->un.varCfgLnk.crtov = phba->fc_crtov; | |
174 | mb->un.varCfgLnk.citov = phba->fc_citov; | |
175 | ||
176 | if (phba->cfg_ack0) | |
177 | mb->un.varCfgLnk.ack0_enable = 1; | |
178 | ||
179 | mb->mbxCommand = MBX_CONFIG_LINK; | |
180 | mb->mbxOwner = OWN_HOST; | |
181 | return; | |
182 | } | |
183 | ||
184 | /**********************************************/ | |
185 | /* lpfc_init_link Issue an INIT LINK */ | |
186 | /* mailbox command */ | |
187 | /**********************************************/ | |
188 | void | |
189 | lpfc_init_link(struct lpfc_hba * phba, | |
190 | LPFC_MBOXQ_t * pmb, uint32_t topology, uint32_t linkspeed) | |
191 | { | |
192 | lpfc_vpd_t *vpd; | |
193 | struct lpfc_sli *psli; | |
194 | MAILBOX_t *mb; | |
195 | ||
196 | mb = &pmb->mb; | |
197 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
198 | ||
199 | psli = &phba->sli; | |
200 | switch (topology) { | |
201 | case FLAGS_TOPOLOGY_MODE_LOOP_PT: | |
202 | mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_LOOP; | |
203 | mb->un.varInitLnk.link_flags |= FLAGS_TOPOLOGY_FAILOVER; | |
204 | break; | |
205 | case FLAGS_TOPOLOGY_MODE_PT_PT: | |
206 | mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_PT_PT; | |
207 | break; | |
208 | case FLAGS_TOPOLOGY_MODE_LOOP: | |
209 | mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_LOOP; | |
210 | break; | |
211 | case FLAGS_TOPOLOGY_MODE_PT_LOOP: | |
212 | mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_PT_PT; | |
213 | mb->un.varInitLnk.link_flags |= FLAGS_TOPOLOGY_FAILOVER; | |
214 | break; | |
367c2713 JW |
215 | case FLAGS_LOCAL_LB: |
216 | mb->un.varInitLnk.link_flags = FLAGS_LOCAL_LB; | |
217 | break; | |
dea3101e | 218 | } |
219 | ||
4b0b91d4 JS |
220 | /* Enable asynchronous ABTS responses from firmware */ |
221 | mb->un.varInitLnk.link_flags |= FLAGS_IMED_ABORT; | |
222 | ||
dea3101e | 223 | /* NEW_FEATURE |
224 | * Setting up the link speed | |
225 | */ | |
226 | vpd = &phba->vpd; | |
227 | if (vpd->rev.feaLevelHigh >= 0x02){ | |
92d7f7b0 | 228 | switch(linkspeed){ |
dea3101e | 229 | case LINK_SPEED_1G: |
230 | case LINK_SPEED_2G: | |
231 | case LINK_SPEED_4G: | |
b87eab38 | 232 | case LINK_SPEED_8G: |
dea3101e | 233 | mb->un.varInitLnk.link_flags |= |
234 | FLAGS_LINK_SPEED; | |
235 | mb->un.varInitLnk.link_speed = linkspeed; | |
236 | break; | |
237 | case LINK_SPEED_AUTO: | |
238 | default: | |
239 | mb->un.varInitLnk.link_speed = | |
240 | LINK_SPEED_AUTO; | |
241 | break; | |
242 | } | |
243 | ||
244 | } | |
245 | else | |
246 | mb->un.varInitLnk.link_speed = LINK_SPEED_AUTO; | |
247 | ||
248 | mb->mbxCommand = (volatile uint8_t)MBX_INIT_LINK; | |
249 | mb->mbxOwner = OWN_HOST; | |
250 | mb->un.varInitLnk.fabric_AL_PA = phba->fc_pref_ALPA; | |
251 | return; | |
252 | } | |
253 | ||
254 | /**********************************************/ | |
255 | /* lpfc_read_sparam Issue a READ SPARAM */ | |
256 | /* mailbox command */ | |
257 | /**********************************************/ | |
258 | int | |
92d7f7b0 | 259 | lpfc_read_sparam(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmb, int vpi) |
dea3101e | 260 | { |
261 | struct lpfc_dmabuf *mp; | |
262 | MAILBOX_t *mb; | |
263 | struct lpfc_sli *psli; | |
264 | ||
265 | psli = &phba->sli; | |
266 | mb = &pmb->mb; | |
267 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
268 | ||
269 | mb->mbxOwner = OWN_HOST; | |
270 | ||
271 | /* Get a buffer to hold the HBAs Service Parameters */ | |
272 | ||
273 | if (((mp = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL)) == 0) || | |
274 | ((mp->virt = lpfc_mbuf_alloc(phba, 0, &(mp->phys))) == 0)) { | |
c9475cb0 | 275 | kfree(mp); |
dea3101e | 276 | mb->mbxCommand = MBX_READ_SPARM64; |
277 | /* READ_SPARAM: no buffers */ | |
e8b62011 JS |
278 | lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX, |
279 | "0301 READ_SPARAM: no buffers\n"); | |
92d7f7b0 | 280 | return (1); |
dea3101e | 281 | } |
282 | INIT_LIST_HEAD(&mp->list); | |
283 | mb->mbxCommand = MBX_READ_SPARM64; | |
284 | mb->un.varRdSparm.un.sp64.tus.f.bdeSize = sizeof (struct serv_parm); | |
285 | mb->un.varRdSparm.un.sp64.addrHigh = putPaddrHigh(mp->phys); | |
286 | mb->un.varRdSparm.un.sp64.addrLow = putPaddrLow(mp->phys); | |
92d7f7b0 | 287 | mb->un.varRdSparm.vpi = vpi; |
dea3101e | 288 | |
289 | /* save address for completion */ | |
290 | pmb->context1 = mp; | |
291 | ||
92d7f7b0 | 292 | return (0); |
dea3101e | 293 | } |
294 | ||
295 | /********************************************/ | |
296 | /* lpfc_unreg_did Issue a UNREG_DID */ | |
297 | /* mailbox command */ | |
298 | /********************************************/ | |
299 | void | |
92d7f7b0 JS |
300 | lpfc_unreg_did(struct lpfc_hba * phba, uint16_t vpi, uint32_t did, |
301 | LPFC_MBOXQ_t * pmb) | |
dea3101e | 302 | { |
303 | MAILBOX_t *mb; | |
304 | ||
305 | mb = &pmb->mb; | |
306 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
307 | ||
308 | mb->un.varUnregDID.did = did; | |
92d7f7b0 | 309 | mb->un.varUnregDID.vpi = vpi; |
dea3101e | 310 | |
311 | mb->mbxCommand = MBX_UNREG_D_ID; | |
312 | mb->mbxOwner = OWN_HOST; | |
313 | return; | |
314 | } | |
315 | ||
dea3101e | 316 | /**********************************************/ |
317 | /* lpfc_read_nv Issue a READ CONFIG */ | |
318 | /* mailbox command */ | |
319 | /**********************************************/ | |
320 | void | |
321 | lpfc_read_config(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
322 | { | |
323 | MAILBOX_t *mb; | |
324 | ||
325 | mb = &pmb->mb; | |
326 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
327 | ||
328 | mb->mbxCommand = MBX_READ_CONFIG; | |
329 | mb->mbxOwner = OWN_HOST; | |
330 | return; | |
331 | } | |
332 | ||
7bb3b137 JW |
333 | /*************************************************/ |
334 | /* lpfc_read_lnk_stat Issue a READ LINK STATUS */ | |
335 | /* mailbox command */ | |
336 | /*************************************************/ | |
337 | void | |
338 | lpfc_read_lnk_stat(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
339 | { | |
340 | MAILBOX_t *mb; | |
341 | ||
342 | mb = &pmb->mb; | |
343 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
344 | ||
345 | mb->mbxCommand = MBX_READ_LNK_STAT; | |
346 | mb->mbxOwner = OWN_HOST; | |
347 | return; | |
348 | } | |
349 | ||
dea3101e | 350 | /********************************************/ |
351 | /* lpfc_reg_login Issue a REG_LOGIN */ | |
352 | /* mailbox command */ | |
353 | /********************************************/ | |
354 | int | |
92d7f7b0 JS |
355 | lpfc_reg_login(struct lpfc_hba *phba, uint16_t vpi, uint32_t did, |
356 | uint8_t *param, LPFC_MBOXQ_t *pmb, uint32_t flag) | |
dea3101e | 357 | { |
2e0fef85 | 358 | MAILBOX_t *mb = &pmb->mb; |
dea3101e | 359 | uint8_t *sparam; |
360 | struct lpfc_dmabuf *mp; | |
dea3101e | 361 | |
dea3101e | 362 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); |
363 | ||
364 | mb->un.varRegLogin.rpi = 0; | |
92d7f7b0 | 365 | mb->un.varRegLogin.vpi = vpi; |
dea3101e | 366 | mb->un.varRegLogin.did = did; |
367 | mb->un.varWords[30] = flag; /* Set flag to issue action on cmpl */ | |
368 | ||
369 | mb->mbxOwner = OWN_HOST; | |
370 | ||
371 | /* Get a buffer to hold NPorts Service Parameters */ | |
372 | if (((mp = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL)) == NULL) || | |
373 | ((mp->virt = lpfc_mbuf_alloc(phba, 0, &(mp->phys))) == 0)) { | |
c9475cb0 | 374 | kfree(mp); |
dea3101e | 375 | mb->mbxCommand = MBX_REG_LOGIN64; |
376 | /* REG_LOGIN: no buffers */ | |
92d7f7b0 | 377 | lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX, |
e8b62011 JS |
378 | "0302 REG_LOGIN: no buffers, VPI:%d DID:x%x, " |
379 | "flag x%x\n", vpi, did, flag); | |
92d7f7b0 | 380 | return (1); |
dea3101e | 381 | } |
382 | INIT_LIST_HEAD(&mp->list); | |
383 | sparam = mp->virt; | |
384 | ||
385 | /* Copy param's into a new buffer */ | |
386 | memcpy(sparam, param, sizeof (struct serv_parm)); | |
387 | ||
388 | /* save address for completion */ | |
389 | pmb->context1 = (uint8_t *) mp; | |
390 | ||
391 | mb->mbxCommand = MBX_REG_LOGIN64; | |
392 | mb->un.varRegLogin.un.sp64.tus.f.bdeSize = sizeof (struct serv_parm); | |
393 | mb->un.varRegLogin.un.sp64.addrHigh = putPaddrHigh(mp->phys); | |
394 | mb->un.varRegLogin.un.sp64.addrLow = putPaddrLow(mp->phys); | |
395 | ||
92d7f7b0 | 396 | return (0); |
dea3101e | 397 | } |
398 | ||
399 | /**********************************************/ | |
400 | /* lpfc_unreg_login Issue a UNREG_LOGIN */ | |
401 | /* mailbox command */ | |
402 | /**********************************************/ | |
403 | void | |
92d7f7b0 JS |
404 | lpfc_unreg_login(struct lpfc_hba *phba, uint16_t vpi, uint32_t rpi, |
405 | LPFC_MBOXQ_t * pmb) | |
dea3101e | 406 | { |
407 | MAILBOX_t *mb; | |
408 | ||
409 | mb = &pmb->mb; | |
410 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
411 | ||
412 | mb->un.varUnregLogin.rpi = (uint16_t) rpi; | |
413 | mb->un.varUnregLogin.rsvd1 = 0; | |
92d7f7b0 | 414 | mb->un.varUnregLogin.vpi = vpi; |
dea3101e | 415 | |
416 | mb->mbxCommand = MBX_UNREG_LOGIN; | |
417 | mb->mbxOwner = OWN_HOST; | |
418 | return; | |
419 | } | |
420 | ||
92d7f7b0 JS |
421 | /**************************************************/ |
422 | /* lpfc_reg_vpi Issue a REG_VPI */ | |
423 | /* mailbox command */ | |
424 | /**************************************************/ | |
425 | void | |
426 | lpfc_reg_vpi(struct lpfc_hba *phba, uint16_t vpi, uint32_t sid, | |
427 | LPFC_MBOXQ_t *pmb) | |
428 | { | |
429 | MAILBOX_t *mb = &pmb->mb; | |
430 | ||
431 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
432 | ||
433 | mb->un.varRegVpi.vpi = vpi; | |
434 | mb->un.varRegVpi.sid = sid; | |
435 | ||
436 | mb->mbxCommand = MBX_REG_VPI; | |
437 | mb->mbxOwner = OWN_HOST; | |
438 | return; | |
439 | ||
440 | } | |
441 | ||
442 | /**************************************************/ | |
443 | /* lpfc_unreg_vpi Issue a UNREG_VNPI */ | |
444 | /* mailbox command */ | |
445 | /**************************************************/ | |
446 | void | |
447 | lpfc_unreg_vpi(struct lpfc_hba *phba, uint16_t vpi, LPFC_MBOXQ_t *pmb) | |
448 | { | |
449 | MAILBOX_t *mb = &pmb->mb; | |
450 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
451 | ||
452 | mb->un.varUnregVpi.vpi = vpi; | |
453 | ||
454 | mb->mbxCommand = MBX_UNREG_VPI; | |
455 | mb->mbxOwner = OWN_HOST; | |
456 | return; | |
457 | ||
458 | } | |
459 | ||
dea3101e | 460 | static void |
461 | lpfc_config_pcb_setup(struct lpfc_hba * phba) | |
462 | { | |
463 | struct lpfc_sli *psli = &phba->sli; | |
464 | struct lpfc_sli_ring *pring; | |
465 | PCB_t *pcbp = &phba->slim2p->pcb; | |
466 | dma_addr_t pdma_addr; | |
467 | uint32_t offset; | |
2e0fef85 | 468 | uint32_t iocbCnt = 0; |
dea3101e | 469 | int i; |
470 | ||
dea3101e | 471 | pcbp->maxRing = (psli->num_rings - 1); |
472 | ||
dea3101e | 473 | for (i = 0; i < psli->num_rings; i++) { |
474 | pring = &psli->ring[i]; | |
2e0fef85 | 475 | |
ed957684 | 476 | pring->sizeCiocb = phba->sli_rev == 3 ? SLI3_IOCB_CMD_SIZE: |
92d7f7b0 | 477 | SLI2_IOCB_CMD_SIZE; |
ed957684 | 478 | pring->sizeRiocb = phba->sli_rev == 3 ? SLI3_IOCB_RSP_SIZE: |
92d7f7b0 | 479 | SLI2_IOCB_RSP_SIZE; |
dea3101e | 480 | /* A ring MUST have both cmd and rsp entries defined to be |
481 | valid */ | |
482 | if ((pring->numCiocb == 0) || (pring->numRiocb == 0)) { | |
483 | pcbp->rdsc[i].cmdEntries = 0; | |
484 | pcbp->rdsc[i].rspEntries = 0; | |
485 | pcbp->rdsc[i].cmdAddrHigh = 0; | |
486 | pcbp->rdsc[i].rspAddrHigh = 0; | |
487 | pcbp->rdsc[i].cmdAddrLow = 0; | |
488 | pcbp->rdsc[i].rspAddrLow = 0; | |
489 | pring->cmdringaddr = NULL; | |
490 | pring->rspringaddr = NULL; | |
491 | continue; | |
492 | } | |
493 | /* Command ring setup for ring */ | |
92d7f7b0 | 494 | pring->cmdringaddr = (void *) &phba->slim2p->IOCBs[iocbCnt]; |
dea3101e | 495 | pcbp->rdsc[i].cmdEntries = pring->numCiocb; |
496 | ||
92d7f7b0 JS |
497 | offset = (uint8_t *) &phba->slim2p->IOCBs[iocbCnt] - |
498 | (uint8_t *) phba->slim2p; | |
dea3101e | 499 | pdma_addr = phba->slim2p_mapping + offset; |
500 | pcbp->rdsc[i].cmdAddrHigh = putPaddrHigh(pdma_addr); | |
501 | pcbp->rdsc[i].cmdAddrLow = putPaddrLow(pdma_addr); | |
502 | iocbCnt += pring->numCiocb; | |
503 | ||
504 | /* Response ring setup for ring */ | |
92d7f7b0 | 505 | pring->rspringaddr = (void *) &phba->slim2p->IOCBs[iocbCnt]; |
dea3101e | 506 | |
507 | pcbp->rdsc[i].rspEntries = pring->numRiocb; | |
508 | offset = (uint8_t *)&phba->slim2p->IOCBs[iocbCnt] - | |
509 | (uint8_t *)phba->slim2p; | |
510 | pdma_addr = phba->slim2p_mapping + offset; | |
511 | pcbp->rdsc[i].rspAddrHigh = putPaddrHigh(pdma_addr); | |
512 | pcbp->rdsc[i].rspAddrLow = putPaddrLow(pdma_addr); | |
513 | iocbCnt += pring->numRiocb; | |
514 | } | |
515 | } | |
516 | ||
517 | void | |
518 | lpfc_read_rev(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
519 | { | |
2e0fef85 | 520 | MAILBOX_t *mb = &pmb->mb; |
dea3101e | 521 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); |
522 | mb->un.varRdRev.cv = 1; | |
ed957684 | 523 | mb->un.varRdRev.v3req = 1; /* Request SLI3 info */ |
dea3101e | 524 | mb->mbxCommand = MBX_READ_REV; |
525 | mb->mbxOwner = OWN_HOST; | |
526 | return; | |
527 | } | |
528 | ||
ed957684 JS |
529 | static void |
530 | lpfc_build_hbq_profile2(struct config_hbq_var *hbqmb, | |
531 | struct lpfc_hbq_init *hbq_desc) | |
532 | { | |
533 | hbqmb->profiles.profile2.seqlenbcnt = hbq_desc->seqlenbcnt; | |
534 | hbqmb->profiles.profile2.maxlen = hbq_desc->maxlen; | |
535 | hbqmb->profiles.profile2.seqlenoff = hbq_desc->seqlenoff; | |
536 | } | |
537 | ||
538 | static void | |
539 | lpfc_build_hbq_profile3(struct config_hbq_var *hbqmb, | |
540 | struct lpfc_hbq_init *hbq_desc) | |
541 | { | |
542 | hbqmb->profiles.profile3.seqlenbcnt = hbq_desc->seqlenbcnt; | |
543 | hbqmb->profiles.profile3.maxlen = hbq_desc->maxlen; | |
544 | hbqmb->profiles.profile3.cmdcodeoff = hbq_desc->cmdcodeoff; | |
545 | hbqmb->profiles.profile3.seqlenoff = hbq_desc->seqlenoff; | |
546 | memcpy(&hbqmb->profiles.profile3.cmdmatch, hbq_desc->cmdmatch, | |
547 | sizeof(hbqmb->profiles.profile3.cmdmatch)); | |
548 | } | |
549 | ||
550 | static void | |
551 | lpfc_build_hbq_profile5(struct config_hbq_var *hbqmb, | |
552 | struct lpfc_hbq_init *hbq_desc) | |
553 | { | |
554 | hbqmb->profiles.profile5.seqlenbcnt = hbq_desc->seqlenbcnt; | |
555 | hbqmb->profiles.profile5.maxlen = hbq_desc->maxlen; | |
556 | hbqmb->profiles.profile5.cmdcodeoff = hbq_desc->cmdcodeoff; | |
557 | hbqmb->profiles.profile5.seqlenoff = hbq_desc->seqlenoff; | |
558 | memcpy(&hbqmb->profiles.profile5.cmdmatch, hbq_desc->cmdmatch, | |
559 | sizeof(hbqmb->profiles.profile5.cmdmatch)); | |
560 | } | |
561 | ||
562 | void | |
51ef4c26 JS |
563 | lpfc_config_hbq(struct lpfc_hba *phba, uint32_t id, |
564 | struct lpfc_hbq_init *hbq_desc, | |
ed957684 JS |
565 | uint32_t hbq_entry_index, LPFC_MBOXQ_t *pmb) |
566 | { | |
567 | int i; | |
568 | MAILBOX_t *mb = &pmb->mb; | |
569 | struct config_hbq_var *hbqmb = &mb->un.varCfgHbq; | |
570 | ||
571 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
51ef4c26 | 572 | hbqmb->hbqId = id; |
ed957684 JS |
573 | hbqmb->entry_count = hbq_desc->entry_count; /* # entries in HBQ */ |
574 | hbqmb->recvNotify = hbq_desc->rn; /* Receive | |
575 | * Notification */ | |
576 | hbqmb->numMask = hbq_desc->mask_count; /* # R_CTL/TYPE masks | |
577 | * # in words 0-19 */ | |
92d7f7b0 | 578 | hbqmb->profile = hbq_desc->profile; /* Selection profile: |
ed957684 JS |
579 | * 0 = all, |
580 | * 7 = logentry */ | |
581 | hbqmb->ringMask = hbq_desc->ring_mask; /* Binds HBQ to a ring | |
582 | * e.g. Ring0=b0001, | |
583 | * ring2=b0100 */ | |
584 | hbqmb->headerLen = hbq_desc->headerLen; /* 0 if not profile 4 | |
585 | * or 5 */ | |
586 | hbqmb->logEntry = hbq_desc->logEntry; /* Set to 1 if this | |
587 | * HBQ will be used | |
588 | * for LogEntry | |
589 | * buffers */ | |
590 | hbqmb->hbqaddrLow = putPaddrLow(phba->hbqslimp.phys) + | |
591 | hbq_entry_index * sizeof(struct lpfc_hbq_entry); | |
592 | hbqmb->hbqaddrHigh = putPaddrHigh(phba->hbqslimp.phys); | |
593 | ||
594 | mb->mbxCommand = MBX_CONFIG_HBQ; | |
595 | mb->mbxOwner = OWN_HOST; | |
596 | ||
92d7f7b0 JS |
597 | /* Copy info for profiles 2,3,5. Other |
598 | * profiles this area is reserved | |
599 | */ | |
ed957684 JS |
600 | if (hbq_desc->profile == 2) |
601 | lpfc_build_hbq_profile2(hbqmb, hbq_desc); | |
602 | else if (hbq_desc->profile == 3) | |
603 | lpfc_build_hbq_profile3(hbqmb, hbq_desc); | |
604 | else if (hbq_desc->profile == 5) | |
605 | lpfc_build_hbq_profile5(hbqmb, hbq_desc); | |
606 | ||
607 | /* Return if no rctl / type masks for this HBQ */ | |
608 | if (!hbq_desc->mask_count) | |
609 | return; | |
610 | ||
611 | /* Otherwise we setup specific rctl / type masks for this HBQ */ | |
612 | for (i = 0; i < hbq_desc->mask_count; i++) { | |
613 | hbqmb->hbqMasks[i].tmatch = hbq_desc->hbqMasks[i].tmatch; | |
614 | hbqmb->hbqMasks[i].tmask = hbq_desc->hbqMasks[i].tmask; | |
615 | hbqmb->hbqMasks[i].rctlmatch = hbq_desc->hbqMasks[i].rctlmatch; | |
616 | hbqmb->hbqMasks[i].rctlmask = hbq_desc->hbqMasks[i].rctlmask; | |
617 | } | |
618 | ||
619 | return; | |
620 | } | |
621 | ||
92d7f7b0 JS |
622 | |
623 | ||
dea3101e | 624 | void |
625 | lpfc_config_ring(struct lpfc_hba * phba, int ring, LPFC_MBOXQ_t * pmb) | |
626 | { | |
627 | int i; | |
628 | MAILBOX_t *mb = &pmb->mb; | |
629 | struct lpfc_sli *psli; | |
630 | struct lpfc_sli_ring *pring; | |
631 | ||
632 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
633 | ||
634 | mb->un.varCfgRing.ring = ring; | |
635 | mb->un.varCfgRing.maxOrigXchg = 0; | |
636 | mb->un.varCfgRing.maxRespXchg = 0; | |
637 | mb->un.varCfgRing.recvNotify = 1; | |
638 | ||
639 | psli = &phba->sli; | |
640 | pring = &psli->ring[ring]; | |
641 | mb->un.varCfgRing.numMask = pring->num_mask; | |
642 | mb->mbxCommand = MBX_CONFIG_RING; | |
643 | mb->mbxOwner = OWN_HOST; | |
644 | ||
645 | /* Is this ring configured for a specific profile */ | |
646 | if (pring->prt[0].profile) { | |
647 | mb->un.varCfgRing.profile = pring->prt[0].profile; | |
648 | return; | |
649 | } | |
650 | ||
651 | /* Otherwise we setup specific rctl / type masks for this ring */ | |
652 | for (i = 0; i < pring->num_mask; i++) { | |
653 | mb->un.varCfgRing.rrRegs[i].rval = pring->prt[i].rctl; | |
654 | if (mb->un.varCfgRing.rrRegs[i].rval != FC_ELS_REQ) | |
655 | mb->un.varCfgRing.rrRegs[i].rmask = 0xff; | |
656 | else | |
657 | mb->un.varCfgRing.rrRegs[i].rmask = 0xfe; | |
658 | mb->un.varCfgRing.rrRegs[i].tval = pring->prt[i].type; | |
659 | mb->un.varCfgRing.rrRegs[i].tmask = 0xff; | |
660 | } | |
661 | ||
662 | return; | |
663 | } | |
664 | ||
665 | void | |
92d7f7b0 | 666 | lpfc_config_port(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmb) |
dea3101e | 667 | { |
ed957684 | 668 | MAILBOX_t __iomem *mb_slim = (MAILBOX_t __iomem *) phba->MBslimaddr; |
dea3101e | 669 | MAILBOX_t *mb = &pmb->mb; |
670 | dma_addr_t pdma_addr; | |
671 | uint32_t bar_low, bar_high; | |
672 | size_t offset; | |
4cc2da1d | 673 | struct lpfc_hgp hgp; |
f91b392c | 674 | int i; |
ed957684 | 675 | uint32_t pgp_offset; |
dea3101e | 676 | |
677 | memset(pmb, 0, sizeof(LPFC_MBOXQ_t)); | |
678 | mb->mbxCommand = MBX_CONFIG_PORT; | |
679 | mb->mbxOwner = OWN_HOST; | |
680 | ||
681 | mb->un.varCfgPort.pcbLen = sizeof(PCB_t); | |
682 | ||
683 | offset = (uint8_t *)&phba->slim2p->pcb - (uint8_t *)phba->slim2p; | |
684 | pdma_addr = phba->slim2p_mapping + offset; | |
685 | mb->un.varCfgPort.pcbLow = putPaddrLow(pdma_addr); | |
686 | mb->un.varCfgPort.pcbHigh = putPaddrHigh(pdma_addr); | |
687 | ||
ed957684 JS |
688 | /* If HBA supports SLI=3 ask for it */ |
689 | ||
92d7f7b0 | 690 | if (phba->sli_rev == 3 && phba->vpd.sli3Feat.cerbm) { |
ed957684 | 691 | mb->un.varCfgPort.cerbm = 1; /* Request HBQs */ |
51ef4c26 | 692 | mb->un.varCfgPort.max_hbq = lpfc_sli_hbq_count(); |
78b2d852 | 693 | if (phba->max_vpi && phba->cfg_enable_npiv && |
92d7f7b0 JS |
694 | phba->vpd.sli3Feat.cmv) { |
695 | mb->un.varCfgPort.max_vpi = phba->max_vpi; | |
696 | mb->un.varCfgPort.cmv = 1; | |
697 | phba->sli3_options |= LPFC_SLI3_NPIV_ENABLED; | |
698 | } else | |
699 | mb->un.varCfgPort.max_vpi = phba->max_vpi = 0; | |
700 | } else | |
701 | phba->sli_rev = 2; | |
702 | mb->un.varCfgPort.sli_mode = phba->sli_rev; | |
ed957684 | 703 | |
dea3101e | 704 | /* Now setup pcb */ |
705 | phba->slim2p->pcb.type = TYPE_NATIVE_SLI2; | |
706 | phba->slim2p->pcb.feature = FEATURE_INITIAL_SLI2; | |
707 | ||
708 | /* Setup Mailbox pointers */ | |
ed957684 JS |
709 | phba->slim2p->pcb.mailBoxSize = offsetof(MAILBOX_t, us) + |
710 | sizeof(struct sli2_desc); | |
dea3101e | 711 | offset = (uint8_t *)&phba->slim2p->mbx - (uint8_t *)phba->slim2p; |
712 | pdma_addr = phba->slim2p_mapping + offset; | |
713 | phba->slim2p->pcb.mbAddrHigh = putPaddrHigh(pdma_addr); | |
714 | phba->slim2p->pcb.mbAddrLow = putPaddrLow(pdma_addr); | |
715 | ||
716 | /* | |
717 | * Setup Host Group ring pointer. | |
718 | * | |
719 | * For efficiency reasons, the ring get/put pointers can be | |
720 | * placed in adapter memory (SLIM) rather than in host memory. | |
721 | * This allows firmware to avoid PCI reads/writes when updating | |
722 | * and checking pointers. | |
723 | * | |
724 | * The firmware recognizes the use of SLIM memory by comparing | |
725 | * the address of the get/put pointers structure with that of | |
726 | * the SLIM BAR (BAR0). | |
727 | * | |
728 | * Caution: be sure to use the PCI config space value of BAR0/BAR1 | |
729 | * (the hardware's view of the base address), not the OS's | |
730 | * value of pci_resource_start() as the OS value may be a cookie | |
731 | * for ioremap/iomap. | |
732 | */ | |
733 | ||
734 | ||
735 | pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_0, &bar_low); | |
736 | pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_1, &bar_high); | |
737 | ||
ed957684 JS |
738 | /* |
739 | * Set up HGP - Port Memory | |
740 | * | |
741 | * The port expects the host get/put pointers to reside in memory | |
742 | * following the "non-diagnostic" mode mailbox (32 words, 0x80 bytes) | |
743 | * area of SLIM. In SLI-2 mode, there's an additional 16 reserved | |
744 | * words (0x40 bytes). This area is not reserved if HBQs are | |
745 | * configured in SLI-3. | |
746 | * | |
747 | * CR0Put - SLI2(no HBQs) = 0xc0, With HBQs = 0x80 | |
748 | * RR0Get 0xc4 0x84 | |
749 | * CR1Put 0xc8 0x88 | |
750 | * RR1Get 0xcc 0x8c | |
751 | * CR2Put 0xd0 0x90 | |
752 | * RR2Get 0xd4 0x94 | |
753 | * CR3Put 0xd8 0x98 | |
754 | * RR3Get 0xdc 0x9c | |
755 | * | |
756 | * Reserved 0xa0-0xbf | |
757 | * If HBQs configured: | |
758 | * HBQ 0 Put ptr 0xc0 | |
759 | * HBQ 1 Put ptr 0xc4 | |
760 | * HBQ 2 Put ptr 0xc8 | |
761 | * ...... | |
762 | * HBQ(M-1)Put Pointer 0xc0+(M-1)*4 | |
763 | * | |
764 | */ | |
765 | ||
766 | if (phba->sli_rev == 3) { | |
767 | phba->host_gp = &mb_slim->us.s3.host[0]; | |
768 | phba->hbq_put = &mb_slim->us.s3.hbq_put[0]; | |
769 | } else { | |
770 | phba->host_gp = &mb_slim->us.s2.host[0]; | |
771 | phba->hbq_put = NULL; | |
772 | } | |
dea3101e | 773 | |
774 | /* mask off BAR0's flag bits 0 - 3 */ | |
775 | phba->slim2p->pcb.hgpAddrLow = (bar_low & PCI_BASE_ADDRESS_MEM_MASK) + | |
ed957684 JS |
776 | (void __iomem *) phba->host_gp - |
777 | (void __iomem *)phba->MBslimaddr; | |
dea3101e | 778 | if (bar_low & PCI_BASE_ADDRESS_MEM_TYPE_64) |
779 | phba->slim2p->pcb.hgpAddrHigh = bar_high; | |
780 | else | |
781 | phba->slim2p->pcb.hgpAddrHigh = 0; | |
782 | /* write HGP data to SLIM at the required longword offset */ | |
4cc2da1d | 783 | memset(&hgp, 0, sizeof(struct lpfc_hgp)); |
f91b392c JSEC |
784 | |
785 | for (i=0; i < phba->sli.num_rings; i++) { | |
ed957684 JS |
786 | lpfc_memcpy_to_slim(phba->host_gp + i, &hgp, |
787 | sizeof(*phba->host_gp)); | |
f91b392c | 788 | } |
dea3101e | 789 | |
790 | /* Setup Port Group ring pointer */ | |
ed957684 JS |
791 | if (phba->sli_rev == 3) |
792 | pgp_offset = (uint8_t *)&phba->slim2p->mbx.us.s3_pgp.port - | |
793 | (uint8_t *)phba->slim2p; | |
794 | else | |
795 | pgp_offset = (uint8_t *)&phba->slim2p->mbx.us.s2.port - | |
796 | (uint8_t *)phba->slim2p; | |
797 | ||
798 | pdma_addr = phba->slim2p_mapping + pgp_offset; | |
dea3101e | 799 | phba->slim2p->pcb.pgpAddrHigh = putPaddrHigh(pdma_addr); |
800 | phba->slim2p->pcb.pgpAddrLow = putPaddrLow(pdma_addr); | |
ed957684 | 801 | phba->hbq_get = &phba->slim2p->mbx.us.s3_pgp.hbq_get[0]; |
dea3101e | 802 | |
803 | /* Use callback routine to setp rings in the pcb */ | |
804 | lpfc_config_pcb_setup(phba); | |
805 | ||
806 | /* special handling for LC HBAs */ | |
807 | if (lpfc_is_LC_HBA(phba->pcidev->device)) { | |
808 | uint32_t hbainit[5]; | |
809 | ||
810 | lpfc_hba_init(phba, hbainit); | |
811 | ||
812 | memcpy(&mb->un.varCfgPort.hbainit, hbainit, 20); | |
813 | } | |
814 | ||
815 | /* Swap PCB if needed */ | |
816 | lpfc_sli_pcimem_bcopy(&phba->slim2p->pcb, &phba->slim2p->pcb, | |
92d7f7b0 | 817 | sizeof(PCB_t)); |
dea3101e | 818 | } |
819 | ||
41415862 JW |
820 | void |
821 | lpfc_kill_board(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
822 | { | |
823 | MAILBOX_t *mb = &pmb->mb; | |
824 | ||
825 | memset(pmb, 0, sizeof(LPFC_MBOXQ_t)); | |
826 | mb->mbxCommand = MBX_KILL_BOARD; | |
827 | mb->mbxOwner = OWN_HOST; | |
828 | return; | |
829 | } | |
830 | ||
dea3101e | 831 | void |
832 | lpfc_mbox_put(struct lpfc_hba * phba, LPFC_MBOXQ_t * mbq) | |
833 | { | |
834 | struct lpfc_sli *psli; | |
835 | ||
836 | psli = &phba->sli; | |
837 | ||
838 | list_add_tail(&mbq->list, &psli->mboxq); | |
839 | ||
840 | psli->mboxq_cnt++; | |
841 | ||
842 | return; | |
843 | } | |
844 | ||
845 | LPFC_MBOXQ_t * | |
846 | lpfc_mbox_get(struct lpfc_hba * phba) | |
847 | { | |
848 | LPFC_MBOXQ_t *mbq = NULL; | |
849 | struct lpfc_sli *psli = &phba->sli; | |
850 | ||
2e0fef85 | 851 | list_remove_head((&psli->mboxq), mbq, LPFC_MBOXQ_t, list); |
92d7f7b0 | 852 | if (mbq) |
dea3101e | 853 | psli->mboxq_cnt--; |
dea3101e | 854 | |
855 | return mbq; | |
856 | } | |
a309a6b6 | 857 | |
92d7f7b0 JS |
858 | void |
859 | lpfc_mbox_cmpl_put(struct lpfc_hba * phba, LPFC_MBOXQ_t * mbq) | |
860 | { | |
861 | /* This function expects to be called from interupt context */ | |
862 | spin_lock(&phba->hbalock); | |
863 | list_add_tail(&mbq->list, &phba->sli.mboxq_cmpl); | |
864 | spin_unlock(&phba->hbalock); | |
865 | return; | |
866 | } | |
867 | ||
a309a6b6 JS |
868 | int |
869 | lpfc_mbox_tmo_val(struct lpfc_hba *phba, int cmd) | |
870 | { | |
871 | switch (cmd) { | |
872 | case MBX_WRITE_NV: /* 0x03 */ | |
873 | case MBX_UPDATE_CFG: /* 0x1B */ | |
874 | case MBX_DOWN_LOAD: /* 0x1C */ | |
875 | case MBX_DEL_LD_ENTRY: /* 0x1D */ | |
876 | case MBX_LOAD_AREA: /* 0x81 */ | |
877 | case MBX_FLASH_WR_ULA: /* 0x98 */ | |
878 | case MBX_LOAD_EXP_ROM: /* 0x9C */ | |
879 | return LPFC_MBOX_TMO_FLASH_CMD; | |
880 | } | |
881 | return LPFC_MBOX_TMO; | |
882 | } |