projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SCSI] lpfc: NPIV: add SLI-3 interface
[deliverable/linux.git] / drivers / scsi / lpfc / lpfc_mbox.c
CommitLineData
dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
9413afff 4 * Copyright (C) 2004-2007 Emulex. All rights reserved. *
c44ce173 5 * EMULEX and SLI are trademarks of Emulex. *
dea3101e 6 * www.emulex.com *
c44ce173 7 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e 8 * *
9 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC		 10 * modify it under the terms of version 2 of the GNU General *
11 * Public License as published by the Free Software Foundation. *
12 * This program is distributed in the hope that it will be useful. *
13 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
14 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
15 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
16 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
17 * TO BE LEGALLY INVALID. See the GNU General Public License for *
18 * more details, a copy of which can be found in the file COPYING *
19 * included with this package. *
dea3101e 20 *******************************************************************/
21
dea3101e 22#include <linux/blkdev.h>
23#include <linux/pci.h>
24#include <linux/interrupt.h>
25
f888ba3c
JSEC		 26#include <scsi/scsi_device.h>
27#include <scsi/scsi_transport_fc.h>
28
91886523
JSEC		 29#include <scsi/scsi.h>
30
dea3101e 31#include "lpfc_hw.h"
32#include "lpfc_sli.h"
33#include "lpfc_disc.h"
34#include "lpfc_scsi.h"
35#include "lpfc.h"
36#include "lpfc_logmsg.h"
37#include "lpfc_crtn.h"
38#include "lpfc_compat.h"
39
40/**********************************************/
41
42/* mailbox command */
43/**********************************************/
44void
45lpfc_dump_mem(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb, uint16_t offset)
46{
47 MAILBOX_t *mb;
48 void *ctx;
49
50 mb = &pmb->mb;
51 ctx = pmb->context2;
52
53 /* Setup to dump VPD region */
54 memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
55 mb->mbxCommand = MBX_DUMP_MEMORY;
56 mb->un.varDmp.cv = 1;
57 mb->un.varDmp.type = DMP_NV_PARAMS;
58 mb->un.varDmp.entry_index = offset;
59 mb->un.varDmp.region_id = DMP_REGION_VPD;
60 mb->un.varDmp.word_cnt = (DMP_RSP_SIZE / sizeof (uint32_t));
61 mb->un.varDmp.co = 0;
62 mb->un.varDmp.resp_offset = 0;
63 pmb->context2 = ctx;
64 mb->mbxOwner = OWN_HOST;
65 return;
66}
67
68/**********************************************/
69/* lpfc_read_nv Issue a READ NVPARAM */
70/* mailbox command */
71/**********************************************/
72void
73lpfc_read_nv(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
74{
75 MAILBOX_t *mb;
76
77 mb = &pmb->mb;
78 memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
79 mb->mbxCommand = MBX_READ_NV;
80 mb->mbxOwner = OWN_HOST;
81 return;
82}
83
84/**********************************************/
85/* lpfc_read_la Issue a READ LA */
86/* mailbox command */
87/**********************************************/
88int
89lpfc_read_la(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb, struct lpfc_dmabuf *mp)
90{
91 MAILBOX_t *mb;
92 struct lpfc_sli *psli;
93
94 psli = &phba->sli;
95 mb = &pmb->mb;
96 memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
97
98 INIT_LIST_HEAD(&mp->list);
99 mb->mbxCommand = MBX_READ_LA64;
100 mb->un.varReadLA.un.lilpBde64.tus.f.bdeSize = 128;
101 mb->un.varReadLA.un.lilpBde64.addrHigh = putPaddrHigh(mp->phys);
102 mb->un.varReadLA.un.lilpBde64.addrLow = putPaddrLow(mp->phys);
103
104 /* Save address for later completion and set the owner to host so that
105 * the FW knows this mailbox is available for processing.
106 */
107 pmb->context1 = (uint8_t *) mp;
108 mb->mbxOwner = OWN_HOST;
2e0fef85 109 return 0;
dea3101e 110}
111
112/**********************************************/
113/* lpfc_clear_la Issue a CLEAR LA */
114/* mailbox command */
115/**********************************************/
116void
117lpfc_clear_la(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
118{
119 MAILBOX_t *mb;
120
121 mb = &pmb->mb;
122 memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
123
124 mb->un.varClearLA.eventTag = phba->fc_eventTag;
125 mb->mbxCommand = MBX_CLEAR_LA;
126 mb->mbxOwner = OWN_HOST;
127 return;
128}
129
130/**************************************************/
131/* lpfc_config_link Issue a CONFIG LINK */
132/* mailbox command */
133/**************************************************/
134void
135lpfc_config_link(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
136{
2e0fef85 137 struct lpfc_vport *vport = phba->pport;
dea3101e 138 MAILBOX_t *mb = &pmb->mb;
139 memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
140
141 /* NEW_FEATURE
142 * SLI-2, Coalescing Response Feature.
143 */
144 if (phba->cfg_cr_delay) {
145 mb->un.varCfgLnk.cr = 1;
146 mb->un.varCfgLnk.ci = 1;
147 mb->un.varCfgLnk.cr_delay = phba->cfg_cr_delay;
148 mb->un.varCfgLnk.cr_count = phba->cfg_cr_count;
149 }
150
2e0fef85 151 mb->un.varCfgLnk.myId = vport->fc_myDID;
dea3101e 152 mb->un.varCfgLnk.edtov = phba->fc_edtov;
153 mb->un.varCfgLnk.arbtov = phba->fc_arbtov;
154 mb->un.varCfgLnk.ratov = phba->fc_ratov;
155 mb->un.varCfgLnk.rttov = phba->fc_rttov;
156 mb->un.varCfgLnk.altov = phba->fc_altov;
157 mb->un.varCfgLnk.crtov = phba->fc_crtov;
158 mb->un.varCfgLnk.citov = phba->fc_citov;
159
160 if (phba->cfg_ack0)
161 mb->un.varCfgLnk.ack0_enable = 1;
162
163 mb->mbxCommand = MBX_CONFIG_LINK;
164 mb->mbxOwner = OWN_HOST;
165 return;
166}
167
168/**********************************************/
169/* lpfc_init_link Issue an INIT LINK */
170/* mailbox command */
171/**********************************************/
172void
173lpfc_init_link(struct lpfc_hba * phba,
174 LPFC_MBOXQ_t * pmb, uint32_t topology, uint32_t linkspeed)
175{
176 lpfc_vpd_t *vpd;
177 struct lpfc_sli *psli;
178 MAILBOX_t *mb;
179
180 mb = &pmb->mb;
181 memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
182
183 psli = &phba->sli;
184 switch (topology) {
185 case FLAGS_TOPOLOGY_MODE_LOOP_PT:
186 mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_LOOP;
187 mb->un.varInitLnk.link_flags |= FLAGS_TOPOLOGY_FAILOVER;
188 break;
189 case FLAGS_TOPOLOGY_MODE_PT_PT:
190 mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_PT_PT;
191 break;
192 case FLAGS_TOPOLOGY_MODE_LOOP:
193 mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_LOOP;
194 break;
195 case FLAGS_TOPOLOGY_MODE_PT_LOOP:
196 mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_PT_PT;
197 mb->un.varInitLnk.link_flags |= FLAGS_TOPOLOGY_FAILOVER;
198 break;
367c2713
JW		 199 case FLAGS_LOCAL_LB:
200 mb->un.varInitLnk.link_flags = FLAGS_LOCAL_LB;
201 break;
dea3101e 202 }
203
4b0b91d4
JS		 204 /* Enable asynchronous ABTS responses from firmware */
205 mb->un.varInitLnk.link_flags |= FLAGS_IMED_ABORT;
206
dea3101e 207 /* NEW_FEATURE
208 * Setting up the link speed
209 */
210 vpd = &phba->vpd;
211 if (vpd->rev.feaLevelHigh >= 0x02){
2e0fef85 212 switch (linkspeed){
dea3101e 213 case LINK_SPEED_1G:
214 case LINK_SPEED_2G:
215 case LINK_SPEED_4G:
b87eab38 216 case LINK_SPEED_8G:
dea3101e 217 mb->un.varInitLnk.link_flags |=
218 FLAGS_LINK_SPEED;
219 mb->un.varInitLnk.link_speed = linkspeed;
220 break;
221 case LINK_SPEED_AUTO:
222 default:
223 mb->un.varInitLnk.link_speed =
224 LINK_SPEED_AUTO;
225 break;
226 }
227
228 }
229 else
230 mb->un.varInitLnk.link_speed = LINK_SPEED_AUTO;
231
232 mb->mbxCommand = (volatile uint8_t)MBX_INIT_LINK;
233 mb->mbxOwner = OWN_HOST;
234 mb->un.varInitLnk.fabric_AL_PA = phba->fc_pref_ALPA;
ed957684 235 mb->un.varInitLnk.link_flags |= FLAGS_UNREG_LOGIN_ALL;
dea3101e 236 return;
237}
238
239/**********************************************/
240/* lpfc_read_sparam Issue a READ SPARAM */
241/* mailbox command */
242/**********************************************/
243int
244lpfc_read_sparam(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
245{
246 struct lpfc_dmabuf *mp;
247 MAILBOX_t *mb;
248 struct lpfc_sli *psli;
249
250 psli = &phba->sli;
251 mb = &pmb->mb;
252 memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
253
254 mb->mbxOwner = OWN_HOST;
255
256 /* Get a buffer to hold the HBAs Service Parameters */
257
258 if (((mp = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL)) == 0) ||
259 ((mp->virt = lpfc_mbuf_alloc(phba, 0, &(mp->phys))) == 0)) {
c9475cb0 260 kfree(mp);
dea3101e 261 mb->mbxCommand = MBX_READ_SPARM64;
262 /* READ_SPARAM: no buffers */
263 lpfc_printf_log(phba,
264 KERN_WARNING,
265 LOG_MBOX,
266 "%d:0301 READ_SPARAM: no buffers\n",
267 phba->brd_no);
2e0fef85 268 return 1;
dea3101e 269 }
270 INIT_LIST_HEAD(&mp->list);
271 mb->mbxCommand = MBX_READ_SPARM64;
272 mb->un.varRdSparm.un.sp64.tus.f.bdeSize = sizeof (struct serv_parm);
273 mb->un.varRdSparm.un.sp64.addrHigh = putPaddrHigh(mp->phys);
274 mb->un.varRdSparm.un.sp64.addrLow = putPaddrLow(mp->phys);
275
276 /* save address for completion */
277 pmb->context1 = mp;
278
2e0fef85 279 return 0;
dea3101e 280}
281
282/********************************************/
283/* lpfc_unreg_did Issue a UNREG_DID */
284/* mailbox command */
285/********************************************/
286void
2e0fef85 287lpfc_unreg_did(struct lpfc_hba *phba, uint32_t did, LPFC_MBOXQ_t *pmb)
dea3101e 288{
289 MAILBOX_t *mb;
290
291 mb = &pmb->mb;
292 memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
293
294 mb->un.varUnregDID.did = did;
295
296 mb->mbxCommand = MBX_UNREG_D_ID;
297 mb->mbxOwner = OWN_HOST;
298 return;
299}
300
dea3101e 301/**********************************************/
302/* lpfc_read_nv Issue a READ CONFIG */
303/* mailbox command */
304/**********************************************/
305void
306lpfc_read_config(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
307{
308 MAILBOX_t *mb;
309
310 mb = &pmb->mb;
311 memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
312
313 mb->mbxCommand = MBX_READ_CONFIG;
314 mb->mbxOwner = OWN_HOST;
315 return;
316}
317
7bb3b137
JW		 318/*************************************************/
319/* lpfc_read_lnk_stat Issue a READ LINK STATUS */
320/* mailbox command */
321/*************************************************/
322void
323lpfc_read_lnk_stat(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
324{
325 MAILBOX_t *mb;
326
327 mb = &pmb->mb;
328 memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
329
330 mb->mbxCommand = MBX_READ_LNK_STAT;
331 mb->mbxOwner = OWN_HOST;
332 return;
333}
334
dea3101e 335/********************************************/
336/* lpfc_reg_login Issue a REG_LOGIN */
337/* mailbox command */
338/********************************************/
339int
2e0fef85
JS		 340lpfc_reg_login(struct lpfc_hba *phba, uint32_t did, uint8_t *param,
341 LPFC_MBOXQ_t *pmb, uint32_t flag)
dea3101e 342{
2e0fef85 343 MAILBOX_t *mb = &pmb->mb;
dea3101e 344 uint8_t *sparam;
345 struct lpfc_dmabuf *mp;
dea3101e 346
dea3101e 347 memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
348
349 mb->un.varRegLogin.rpi = 0;
350 mb->un.varRegLogin.did = did;
351 mb->un.varWords[30] = flag; /* Set flag to issue action on cmpl */
352
353 mb->mbxOwner = OWN_HOST;
354
355 /* Get a buffer to hold NPorts Service Parameters */
356 if (((mp = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL)) == NULL) ||
357 ((mp->virt = lpfc_mbuf_alloc(phba, 0, &(mp->phys))) == 0)) {
c9475cb0 358 kfree(mp);
dea3101e 359 mb->mbxCommand = MBX_REG_LOGIN64;
360 /* REG_LOGIN: no buffers */
361 lpfc_printf_log(phba,
362 KERN_WARNING,
363 LOG_MBOX,
364 "%d:0302 REG_LOGIN: no buffers Data x%x x%x\n",
365 phba->brd_no,
366 (uint32_t) did, (uint32_t) flag);
2e0fef85 367 return 1;
dea3101e 368 }
369 INIT_LIST_HEAD(&mp->list);
370 sparam = mp->virt;
371
372 /* Copy param's into a new buffer */
373 memcpy(sparam, param, sizeof (struct serv_parm));
374
375 /* save address for completion */
376 pmb->context1 = (uint8_t *) mp;
377
378 mb->mbxCommand = MBX_REG_LOGIN64;
379 mb->un.varRegLogin.un.sp64.tus.f.bdeSize = sizeof (struct serv_parm);
380 mb->un.varRegLogin.un.sp64.addrHigh = putPaddrHigh(mp->phys);
381 mb->un.varRegLogin.un.sp64.addrLow = putPaddrLow(mp->phys);
382
2e0fef85 383 return 0;
dea3101e 384}
385
386/**********************************************/
387/* lpfc_unreg_login Issue a UNREG_LOGIN */
388/* mailbox command */
389/**********************************************/
390void
2e0fef85 391lpfc_unreg_login(struct lpfc_hba *phba, uint32_t rpi, LPFC_MBOXQ_t * pmb)
dea3101e 392{
393 MAILBOX_t *mb;
394
395 mb = &pmb->mb;
396 memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
397
398 mb->un.varUnregLogin.rpi = (uint16_t) rpi;
399 mb->un.varUnregLogin.rsvd1 = 0;
400
401 mb->mbxCommand = MBX_UNREG_LOGIN;
402 mb->mbxOwner = OWN_HOST;
403 return;
404}
405
406static void
407lpfc_config_pcb_setup(struct lpfc_hba * phba)
408{
409 struct lpfc_sli *psli = &phba->sli;
410 struct lpfc_sli_ring *pring;
411 PCB_t *pcbp = &phba->slim2p->pcb;
412 dma_addr_t pdma_addr;
413 uint32_t offset;
2e0fef85 414 uint32_t iocbCnt = 0;
dea3101e 415 int i;
416
dea3101e 417 pcbp->maxRing = (psli->num_rings - 1);
418
dea3101e 419 for (i = 0; i < psli->num_rings; i++) {
420 pring = &psli->ring[i];
2e0fef85 421
ed957684
JS		 422 pring->sizeCiocb = phba->sli_rev == 3 ? SLI3_IOCB_CMD_SIZE:
423 SLI2_IOCB_CMD_SIZE;
424 pring->sizeRiocb = phba->sli_rev == 3 ? SLI3_IOCB_RSP_SIZE:
425 SLI2_IOCB_RSP_SIZE;
dea3101e 426 /* A ring MUST have both cmd and rsp entries defined to be
427 valid */
428 if ((pring->numCiocb == 0) || (pring->numRiocb == 0)) {
429 pcbp->rdsc[i].cmdEntries = 0;
430 pcbp->rdsc[i].rspEntries = 0;
431 pcbp->rdsc[i].cmdAddrHigh = 0;
432 pcbp->rdsc[i].rspAddrHigh = 0;
433 pcbp->rdsc[i].cmdAddrLow = 0;
434 pcbp->rdsc[i].rspAddrLow = 0;
435 pring->cmdringaddr = NULL;
436 pring->rspringaddr = NULL;
437 continue;
438 }
439 /* Command ring setup for ring */
ed957684 440 pring->cmdringaddr = (void *)&phba->slim2p->IOCBs[iocbCnt];
dea3101e 441 pcbp->rdsc[i].cmdEntries = pring->numCiocb;
442
443 offset = (uint8_t *)&phba->slim2p->IOCBs[iocbCnt] -
444 (uint8_t *)phba->slim2p;
445 pdma_addr = phba->slim2p_mapping + offset;
446 pcbp->rdsc[i].cmdAddrHigh = putPaddrHigh(pdma_addr);
447 pcbp->rdsc[i].cmdAddrLow = putPaddrLow(pdma_addr);
448 iocbCnt += pring->numCiocb;
449
450 /* Response ring setup for ring */
ed957684 451 pring->rspringaddr = (void *)&phba->slim2p->IOCBs[iocbCnt];
dea3101e 452
453 pcbp->rdsc[i].rspEntries = pring->numRiocb;
454 offset = (uint8_t *)&phba->slim2p->IOCBs[iocbCnt] -
455 (uint8_t *)phba->slim2p;
456 pdma_addr = phba->slim2p_mapping + offset;
457 pcbp->rdsc[i].rspAddrHigh = putPaddrHigh(pdma_addr);
458 pcbp->rdsc[i].rspAddrLow = putPaddrLow(pdma_addr);
459 iocbCnt += pring->numRiocb;
460 }
461}
462
463void
464lpfc_read_rev(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
465{
2e0fef85 466 MAILBOX_t *mb = &pmb->mb;
dea3101e 467 memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
468 mb->un.varRdRev.cv = 1;
ed957684 469 mb->un.varRdRev.v3req = 1; /* Request SLI3 info */
dea3101e 470 mb->mbxCommand = MBX_READ_REV;
471 mb->mbxOwner = OWN_HOST;
472 return;
473}
474
ed957684
JS		 475static void
476lpfc_build_hbq_profile2(struct config_hbq_var *hbqmb,
477 struct lpfc_hbq_init *hbq_desc)
478{
479 hbqmb->profiles.profile2.seqlenbcnt = hbq_desc->seqlenbcnt;
480 hbqmb->profiles.profile2.maxlen = hbq_desc->maxlen;
481 hbqmb->profiles.profile2.seqlenoff = hbq_desc->seqlenoff;
482}
483
484static void
485lpfc_build_hbq_profile3(struct config_hbq_var *hbqmb,
486 struct lpfc_hbq_init *hbq_desc)
487{
488 hbqmb->profiles.profile3.seqlenbcnt = hbq_desc->seqlenbcnt;
489 hbqmb->profiles.profile3.maxlen = hbq_desc->maxlen;
490 hbqmb->profiles.profile3.cmdcodeoff = hbq_desc->cmdcodeoff;
491 hbqmb->profiles.profile3.seqlenoff = hbq_desc->seqlenoff;
492 memcpy(&hbqmb->profiles.profile3.cmdmatch, hbq_desc->cmdmatch,
493 sizeof(hbqmb->profiles.profile3.cmdmatch));
494}
495
496static void
497lpfc_build_hbq_profile5(struct config_hbq_var *hbqmb,
498 struct lpfc_hbq_init *hbq_desc)
499{
500 hbqmb->profiles.profile5.seqlenbcnt = hbq_desc->seqlenbcnt;
501 hbqmb->profiles.profile5.maxlen = hbq_desc->maxlen;
502 hbqmb->profiles.profile5.cmdcodeoff = hbq_desc->cmdcodeoff;
503 hbqmb->profiles.profile5.seqlenoff = hbq_desc->seqlenoff;
504 memcpy(&hbqmb->profiles.profile5.cmdmatch, hbq_desc->cmdmatch,
505 sizeof(hbqmb->profiles.profile5.cmdmatch));
506}
507
508void
509lpfc_config_hbq(struct lpfc_hba *phba, struct lpfc_hbq_init *hbq_desc,
510 uint32_t hbq_entry_index, LPFC_MBOXQ_t *pmb)
511{
512 int i;
513 MAILBOX_t *mb = &pmb->mb;
514 struct config_hbq_var *hbqmb = &mb->un.varCfgHbq;
515
516 memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
517 hbqmb->entry_count = hbq_desc->entry_count; /* # entries in HBQ */
518 hbqmb->recvNotify = hbq_desc->rn; /* Receive
519 * Notification */
520 hbqmb->numMask = hbq_desc->mask_count; /* # R_CTL/TYPE masks
521 * # in words 0-19 */
522 hbqmb->profile = hbq_desc->profile; /* Selection profile:
523 * 0 = all,
524 * 7 = logentry */
525 hbqmb->ringMask = hbq_desc->ring_mask; /* Binds HBQ to a ring
526 * e.g. Ring0=b0001,
527 * ring2=b0100 */
528 hbqmb->headerLen = hbq_desc->headerLen; /* 0 if not profile 4
529 * or 5 */
530 hbqmb->logEntry = hbq_desc->logEntry; /* Set to 1 if this
531 * HBQ will be used
532 * for LogEntry
533 * buffers */
534 hbqmb->hbqaddrLow = putPaddrLow(phba->hbqslimp.phys) +
535 hbq_entry_index * sizeof(struct lpfc_hbq_entry);
536 hbqmb->hbqaddrHigh = putPaddrHigh(phba->hbqslimp.phys);
537
538 mb->mbxCommand = MBX_CONFIG_HBQ;
539 mb->mbxOwner = OWN_HOST;
540
541 /* Copy info for profiles 2,3,5. Other
542 * profiles this area is reserved
543 */
544 if (hbq_desc->profile == 2)
545 lpfc_build_hbq_profile2(hbqmb, hbq_desc);
546 else if (hbq_desc->profile == 3)
547 lpfc_build_hbq_profile3(hbqmb, hbq_desc);
548 else if (hbq_desc->profile == 5)
549 lpfc_build_hbq_profile5(hbqmb, hbq_desc);
550
551 /* Return if no rctl / type masks for this HBQ */
552 if (!hbq_desc->mask_count)
553 return;
554
555 /* Otherwise we setup specific rctl / type masks for this HBQ */
556 for (i = 0; i < hbq_desc->mask_count; i++) {
557 hbqmb->hbqMasks[i].tmatch = hbq_desc->hbqMasks[i].tmatch;
558 hbqmb->hbqMasks[i].tmask = hbq_desc->hbqMasks[i].tmask;
559 hbqmb->hbqMasks[i].rctlmatch = hbq_desc->hbqMasks[i].rctlmatch;
560 hbqmb->hbqMasks[i].rctlmask = hbq_desc->hbqMasks[i].rctlmask;
561 }
562
563 return;
564}
565
dea3101e 566void
567lpfc_config_ring(struct lpfc_hba * phba, int ring, LPFC_MBOXQ_t * pmb)
568{
569 int i;
570 MAILBOX_t *mb = &pmb->mb;
571 struct lpfc_sli *psli;
572 struct lpfc_sli_ring *pring;
573
574 memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
575
576 mb->un.varCfgRing.ring = ring;
577 mb->un.varCfgRing.maxOrigXchg = 0;
578 mb->un.varCfgRing.maxRespXchg = 0;
579 mb->un.varCfgRing.recvNotify = 1;
580
581 psli = &phba->sli;
582 pring = &psli->ring[ring];
583 mb->un.varCfgRing.numMask = pring->num_mask;
584 mb->mbxCommand = MBX_CONFIG_RING;
585 mb->mbxOwner = OWN_HOST;
586
587 /* Is this ring configured for a specific profile */
588 if (pring->prt[0].profile) {
589 mb->un.varCfgRing.profile = pring->prt[0].profile;
590 return;
591 }
592
593 /* Otherwise we setup specific rctl / type masks for this ring */
594 for (i = 0; i < pring->num_mask; i++) {
595 mb->un.varCfgRing.rrRegs[i].rval = pring->prt[i].rctl;
596 if (mb->un.varCfgRing.rrRegs[i].rval != FC_ELS_REQ)
597 mb->un.varCfgRing.rrRegs[i].rmask = 0xff;
598 else
599 mb->un.varCfgRing.rrRegs[i].rmask = 0xfe;
600 mb->un.varCfgRing.rrRegs[i].tval = pring->prt[i].type;
601 mb->un.varCfgRing.rrRegs[i].tmask = 0xff;
602 }
603
604 return;
605}
606
607void
608lpfc_config_port(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
609{
ed957684 610 MAILBOX_t __iomem *mb_slim = (MAILBOX_t __iomem *) phba->MBslimaddr;
dea3101e 611 MAILBOX_t *mb = &pmb->mb;
612 dma_addr_t pdma_addr;
613 uint32_t bar_low, bar_high;
614 size_t offset;
4cc2da1d 615 struct lpfc_hgp hgp;
f91b392c 616 int i;
ed957684 617 uint32_t pgp_offset;
dea3101e 618
619 memset(pmb, 0, sizeof(LPFC_MBOXQ_t));
620 mb->mbxCommand = MBX_CONFIG_PORT;
621 mb->mbxOwner = OWN_HOST;
622
623 mb->un.varCfgPort.pcbLen = sizeof(PCB_t);
624
625 offset = (uint8_t *)&phba->slim2p->pcb - (uint8_t *)phba->slim2p;
626 pdma_addr = phba->slim2p_mapping + offset;
627 mb->un.varCfgPort.pcbLow = putPaddrLow(pdma_addr);
628 mb->un.varCfgPort.pcbHigh = putPaddrHigh(pdma_addr);
629
ed957684
JS		 630 /* If HBA supports SLI=3 ask for it */
631
632 mb->un.varCfgPort.sli_mode = phba->sli_rev;
633 if (phba->sli_rev == 3) {
634 mb->un.varCfgPort.cerbm = 1; /* Request HBQs */
635 mb->un.varCfgPort.max_hbq = 1; /* Requesting 2 HBQs */
636 }
637
dea3101e 638 /* Now setup pcb */
639 phba->slim2p->pcb.type = TYPE_NATIVE_SLI2;
640 phba->slim2p->pcb.feature = FEATURE_INITIAL_SLI2;
641
642 /* Setup Mailbox pointers */
ed957684
JS		 643 phba->slim2p->pcb.mailBoxSize = offsetof(MAILBOX_t, us) +
644 sizeof(struct sli2_desc);
dea3101e 645 offset = (uint8_t *)&phba->slim2p->mbx - (uint8_t *)phba->slim2p;
646 pdma_addr = phba->slim2p_mapping + offset;
647 phba->slim2p->pcb.mbAddrHigh = putPaddrHigh(pdma_addr);
648 phba->slim2p->pcb.mbAddrLow = putPaddrLow(pdma_addr);
649
650 /*
651 * Setup Host Group ring pointer.
652 *
653 * For efficiency reasons, the ring get/put pointers can be
654 * placed in adapter memory (SLIM) rather than in host memory.
655 * This allows firmware to avoid PCI reads/writes when updating
656 * and checking pointers.
657 *
658 * The firmware recognizes the use of SLIM memory by comparing
659 * the address of the get/put pointers structure with that of
660 * the SLIM BAR (BAR0).
661 *
662 * Caution: be sure to use the PCI config space value of BAR0/BAR1
663 * (the hardware's view of the base address), not the OS's
664 * value of pci_resource_start() as the OS value may be a cookie
665 * for ioremap/iomap.
666 */
667
668
669 pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_0, &bar_low);
670 pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_1, &bar_high);
671
ed957684
JS		 672 /*
673 * Set up HGP - Port Memory
674 *
675 * The port expects the host get/put pointers to reside in memory
676 * following the "non-diagnostic" mode mailbox (32 words, 0x80 bytes)
677 * area of SLIM. In SLI-2 mode, there's an additional 16 reserved
678 * words (0x40 bytes). This area is not reserved if HBQs are
679 * configured in SLI-3.
680 *
681 * CR0Put - SLI2(no HBQs) = 0xc0, With HBQs = 0x80
682 * RR0Get 0xc4 0x84
683 * CR1Put 0xc8 0x88
684 * RR1Get 0xcc 0x8c
685 * CR2Put 0xd0 0x90
686 * RR2Get 0xd4 0x94
687 * CR3Put 0xd8 0x98
688 * RR3Get 0xdc 0x9c
689 *
690 * Reserved 0xa0-0xbf
691 * If HBQs configured:
692 * HBQ 0 Put ptr 0xc0
693 * HBQ 1 Put ptr 0xc4
694 * HBQ 2 Put ptr 0xc8
695 * ......
696 * HBQ(M-1)Put Pointer 0xc0+(M-1)*4
697 *
698 */
699
700 if (phba->sli_rev == 3) {
701 phba->host_gp = &mb_slim->us.s3.host[0];
702 phba->hbq_put = &mb_slim->us.s3.hbq_put[0];
703 } else {
704 phba->host_gp = &mb_slim->us.s2.host[0];
705 phba->hbq_put = NULL;
706 }
dea3101e 707
708 /* mask off BAR0's flag bits 0 - 3 */
709 phba->slim2p->pcb.hgpAddrLow = (bar_low & PCI_BASE_ADDRESS_MEM_MASK) +
ed957684
JS		 710 (void __iomem *) phba->host_gp -
711 (void __iomem *)phba->MBslimaddr;
dea3101e 712 if (bar_low & PCI_BASE_ADDRESS_MEM_TYPE_64)
713 phba->slim2p->pcb.hgpAddrHigh = bar_high;
714 else
715 phba->slim2p->pcb.hgpAddrHigh = 0;
716 /* write HGP data to SLIM at the required longword offset */
4cc2da1d 717 memset(&hgp, 0, sizeof(struct lpfc_hgp));
f91b392c
JSEC		 718
719 for (i=0; i < phba->sli.num_rings; i++) {
ed957684
JS		 720 lpfc_memcpy_to_slim(phba->host_gp + i, &hgp,
721 sizeof(*phba->host_gp));
f91b392c 722 }
dea3101e 723
724 /* Setup Port Group ring pointer */
ed957684
JS		 725 if (phba->sli_rev == 3)
726 pgp_offset = (uint8_t *)&phba->slim2p->mbx.us.s3_pgp.port -
727 (uint8_t *)phba->slim2p;
728 else
729 pgp_offset = (uint8_t *)&phba->slim2p->mbx.us.s2.port -
730 (uint8_t *)phba->slim2p;
731
732 pdma_addr = phba->slim2p_mapping + pgp_offset;
dea3101e 733 phba->slim2p->pcb.pgpAddrHigh = putPaddrHigh(pdma_addr);
734 phba->slim2p->pcb.pgpAddrLow = putPaddrLow(pdma_addr);
ed957684 735 phba->hbq_get = &phba->slim2p->mbx.us.s3_pgp.hbq_get[0];
dea3101e 736
737 /* Use callback routine to setp rings in the pcb */
738 lpfc_config_pcb_setup(phba);
739
740 /* special handling for LC HBAs */
741 if (lpfc_is_LC_HBA(phba->pcidev->device)) {
742 uint32_t hbainit[5];
743
744 lpfc_hba_init(phba, hbainit);
745
746 memcpy(&mb->un.varCfgPort.hbainit, hbainit, 20);
747 }
748
749 /* Swap PCB if needed */
750 lpfc_sli_pcimem_bcopy(&phba->slim2p->pcb, &phba->slim2p->pcb,
751 sizeof (PCB_t));
dea3101e 752}
753
41415862
JW		 754void
755lpfc_kill_board(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
756{
757 MAILBOX_t *mb = &pmb->mb;
758
759 memset(pmb, 0, sizeof(LPFC_MBOXQ_t));
760 mb->mbxCommand = MBX_KILL_BOARD;
761 mb->mbxOwner = OWN_HOST;
762 return;
763}
764
dea3101e 765void
766lpfc_mbox_put(struct lpfc_hba * phba, LPFC_MBOXQ_t * mbq)
767{
768 struct lpfc_sli *psli;
769
770 psli = &phba->sli;
771
772 list_add_tail(&mbq->list, &psli->mboxq);
773
774 psli->mboxq_cnt++;
775
776 return;
777}
778
779LPFC_MBOXQ_t *
780lpfc_mbox_get(struct lpfc_hba * phba)
781{
782 LPFC_MBOXQ_t *mbq = NULL;
783 struct lpfc_sli *psli = &phba->sli;
784
2e0fef85 785 list_remove_head((&psli->mboxq), mbq, LPFC_MBOXQ_t, list);
dea3101e 786 if (mbq) {
787 psli->mboxq_cnt--;
788 }
789
790 return mbq;
791}
a309a6b6
JS		 792
793int
794lpfc_mbox_tmo_val(struct lpfc_hba *phba, int cmd)
795{
796 switch (cmd) {
797 case MBX_WRITE_NV: /* 0x03 */
798 case MBX_UPDATE_CFG: /* 0x1B */
799 case MBX_DOWN_LOAD: /* 0x1C */
800 case MBX_DEL_LD_ENTRY: /* 0x1D */
801 case MBX_LOAD_AREA: /* 0x81 */
802 case MBX_FLASH_WR_ULA: /* 0x98 */
803 case MBX_LOAD_EXP_ROM: /* 0x9C */
804 return LPFC_MBOX_TMO_FLASH_CMD;
805 }
806 return LPFC_MBOX_TMO;
807}
Linux kernel - Deliverables
This page took 0.239175 seconds and 5 git commands to generate.