projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SCSI] lpfc: NPIV: add SLI-3 interface
[deliverable/linux.git] / drivers / scsi / lpfc / lpfc_sli.c
CommitLineData
dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
9413afff 4 * Copyright (C) 2004-2007 Emulex. All rights reserved. *
c44ce173 5 * EMULEX and SLI are trademarks of Emulex. *
dea3101e 6 * www.emulex.com *
c44ce173 7 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e 8 * *
9 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC		 10 * modify it under the terms of version 2 of the GNU General *
11 * Public License as published by the Free Software Foundation. *
12 * This program is distributed in the hope that it will be useful. *
13 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
14 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
15 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
16 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
17 * TO BE LEGALLY INVALID. See the GNU General Public License for *
18 * more details, a copy of which can be found in the file COPYING *
19 * included with this package. *
dea3101e 20 *******************************************************************/
21
dea3101e 22#include <linux/blkdev.h>
23#include <linux/pci.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26
91886523 27#include <scsi/scsi.h>
dea3101e 28#include <scsi/scsi_cmnd.h>
29#include <scsi/scsi_device.h>
30#include <scsi/scsi_host.h>
f888ba3c 31#include <scsi/scsi_transport_fc.h>
dea3101e 32
33#include "lpfc_hw.h"
34#include "lpfc_sli.h"
35#include "lpfc_disc.h"
36#include "lpfc_scsi.h"
37#include "lpfc.h"
38#include "lpfc_crtn.h"
39#include "lpfc_logmsg.h"
40#include "lpfc_compat.h"
41
42/*
43 * Define macro to log: Mailbox command x%x cannot issue Data
44 * This allows multiple uses of lpfc_msgBlk0311
45 * w/o perturbing log msg utility.
46 */
47#define LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag) \
48 lpfc_printf_log(phba, \
49 KERN_INFO, \
50 LOG_MBOX | LOG_SLI, \
51 "%d:0311 Mailbox command x%x cannot issue " \
52 "Data: x%x x%x x%x\n", \
53 phba->brd_no, \
54 mb->mbxCommand, \
2e0fef85 55 phba->pport->port_state, \
dea3101e 56 psli->sli_flag, \
2e0fef85 57 flag)
dea3101e 58
59
60/* There are only four IOCB completion types. */
61typedef enum _lpfc_iocb_type {
62 LPFC_UNKNOWN_IOCB,
63 LPFC_UNSOL_IOCB,
64 LPFC_SOL_IOCB,
65 LPFC_ABORT_IOCB
66} lpfc_iocb_type;
67
ed957684
JS		 68/*
69 * SLI-2/SLI-3 provide different sized iocbs. Given a pointer to the start of
70 * the ring, and the slot number of the desired iocb entry, calc a pointer to
71 * that entry.
72 */
73static inline IOCB_t *
74lpfc_cmd_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
75{
76 return (IOCB_t *) (((char *) pring->cmdringaddr) +
77 pring->cmdidx * phba->iocb_cmd_size);
78}
79
80static inline IOCB_t *
81lpfc_resp_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
82{
83 return (IOCB_t *) (((char *) pring->rspringaddr) +
84 pring->rspidx * phba->iocb_rsp_size);
85}
86
2e0fef85
JS		 87static struct lpfc_iocbq *
88__lpfc_sli_get_iocbq(struct lpfc_hba *phba)
0bd4ca25
JSEC		 89{
90 struct list_head *lpfc_iocb_list = &phba->lpfc_iocb_list;
91 struct lpfc_iocbq * iocbq = NULL;
92
93 list_remove_head(lpfc_iocb_list, iocbq, struct lpfc_iocbq, list);
94 return iocbq;
95}
96
2e0fef85
JS		 97struct lpfc_iocbq *
98lpfc_sli_get_iocbq(struct lpfc_hba *phba)
99{
100 struct lpfc_iocbq * iocbq = NULL;
101 unsigned long iflags;
102
103 spin_lock_irqsave(&phba->hbalock, iflags);
104 iocbq = __lpfc_sli_get_iocbq(phba);
105 spin_unlock_irqrestore(&phba->hbalock, iflags);
106 return iocbq;
107}
108
604a3e30 109void
2e0fef85 110__lpfc_sli_release_iocbq(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq)
604a3e30 111{
2e0fef85 112 size_t start_clean = offsetof(struct lpfc_iocbq, iocb);
604a3e30
JB		 113
114 /*
115 * Clean all volatile data fields, preserve iotag and node struct.
116 */
117 memset((char*)iocbq + start_clean, 0, sizeof(*iocbq) - start_clean);
118 list_add_tail(&iocbq->list, &phba->lpfc_iocb_list);
119}
120
2e0fef85
JS		 121void
122lpfc_sli_release_iocbq(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq)
123{
124 unsigned long iflags;
125
126 /*
127 * Clean all volatile data fields, preserve iotag and node struct.
128 */
129 spin_lock_irqsave(&phba->hbalock, iflags);
130 __lpfc_sli_release_iocbq(phba, iocbq);
131 spin_unlock_irqrestore(&phba->hbalock, iflags);
132}
133
dea3101e 134/*
135 * Translate the iocb command to an iocb command type used to decide the final
136 * disposition of each completed IOCB.
137 */
138static lpfc_iocb_type
139lpfc_sli_iocb_cmd_type(uint8_t iocb_cmnd)
140{
141 lpfc_iocb_type type = LPFC_UNKNOWN_IOCB;
142
143 if (iocb_cmnd > CMD_MAX_IOCB_CMD)
144 return 0;
145
146 switch (iocb_cmnd) {
147 case CMD_XMIT_SEQUENCE_CR:
148 case CMD_XMIT_SEQUENCE_CX:
149 case CMD_XMIT_BCAST_CN:
150 case CMD_XMIT_BCAST_CX:
151 case CMD_ELS_REQUEST_CR:
152 case CMD_ELS_REQUEST_CX:
153 case CMD_CREATE_XRI_CR:
154 case CMD_CREATE_XRI_CX:
155 case CMD_GET_RPI_CN:
156 case CMD_XMIT_ELS_RSP_CX:
157 case CMD_GET_RPI_CR:
158 case CMD_FCP_IWRITE_CR:
159 case CMD_FCP_IWRITE_CX:
160 case CMD_FCP_IREAD_CR:
161 case CMD_FCP_IREAD_CX:
162 case CMD_FCP_ICMND_CR:
163 case CMD_FCP_ICMND_CX:
f5603511
JS		 164 case CMD_FCP_TSEND_CX:
165 case CMD_FCP_TRSP_CX:
166 case CMD_FCP_TRECEIVE_CX:
167 case CMD_FCP_AUTO_TRSP_CX:
dea3101e 168 case CMD_ADAPTER_MSG:
169 case CMD_ADAPTER_DUMP:
170 case CMD_XMIT_SEQUENCE64_CR:
171 case CMD_XMIT_SEQUENCE64_CX:
172 case CMD_XMIT_BCAST64_CN:
173 case CMD_XMIT_BCAST64_CX:
174 case CMD_ELS_REQUEST64_CR:
175 case CMD_ELS_REQUEST64_CX:
176 case CMD_FCP_IWRITE64_CR:
177 case CMD_FCP_IWRITE64_CX:
178 case CMD_FCP_IREAD64_CR:
179 case CMD_FCP_IREAD64_CX:
180 case CMD_FCP_ICMND64_CR:
181 case CMD_FCP_ICMND64_CX:
f5603511
JS		 182 case CMD_FCP_TSEND64_CX:
183 case CMD_FCP_TRSP64_CX:
184 case CMD_FCP_TRECEIVE64_CX:
dea3101e 185 case CMD_GEN_REQUEST64_CR:
186 case CMD_GEN_REQUEST64_CX:
187 case CMD_XMIT_ELS_RSP64_CX:
188 type = LPFC_SOL_IOCB;
189 break;
190 case CMD_ABORT_XRI_CN:
191 case CMD_ABORT_XRI_CX:
192 case CMD_CLOSE_XRI_CN:
193 case CMD_CLOSE_XRI_CX:
194 case CMD_XRI_ABORTED_CX:
195 case CMD_ABORT_MXRI64_CN:
196 type = LPFC_ABORT_IOCB;
197 break;
198 case CMD_RCV_SEQUENCE_CX:
199 case CMD_RCV_ELS_REQ_CX:
200 case CMD_RCV_SEQUENCE64_CX:
201 case CMD_RCV_ELS_REQ64_CX:
ed957684
JS		 202 case CMD_IOCB_RCV_SEQ64_CX:
203 case CMD_IOCB_RCV_ELS64_CX:
204 case CMD_IOCB_RCV_CONT64_CX:
dea3101e 205 type = LPFC_UNSOL_IOCB;
206 break;
207 default:
208 type = LPFC_UNKNOWN_IOCB;
209 break;
210 }
211
212 return type;
213}
214
215static int
ed957684 216lpfc_sli_ring_map(struct lpfc_hba *phba)
dea3101e 217{
218 struct lpfc_sli *psli = &phba->sli;
ed957684
JS		 219 LPFC_MBOXQ_t *pmb;
220 MAILBOX_t *pmbox;
221 int i, rc, ret = 0;
dea3101e 222
ed957684
JS		 223 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
224 if (!pmb)
225 return -ENOMEM;
226 pmbox = &pmb->mb;
227 phba->link_state = LPFC_INIT_MBX_CMDS;
dea3101e 228 for (i = 0; i < psli->num_rings; i++) {
dea3101e 229 lpfc_config_ring(phba, i, pmb);
230 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
231 if (rc != MBX_SUCCESS) {
232 lpfc_printf_log(phba,
233 KERN_ERR,
234 LOG_INIT,
235 "%d:0446 Adapter failed to init, "
236 "mbxCmd x%x CFG_RING, mbxStatus x%x, "
237 "ring %d\n",
238 phba->brd_no,
239 pmbox->mbxCommand,
240 pmbox->mbxStatus,
241 i);
2e0fef85 242 phba->link_state = LPFC_HBA_ERROR;
ed957684
JS		 243 ret = -ENXIO;
244 break;
dea3101e 245 }
246 }
ed957684
JS		 247 mempool_free(pmb, phba->mbox_mem_pool);
248 return ret;
dea3101e 249}
250
251static int
2e0fef85
JS		 252lpfc_sli_ringtxcmpl_put(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
253 struct lpfc_iocbq *piocb)
dea3101e 254{
dea3101e 255 list_add_tail(&piocb->list, &pring->txcmplq);
256 pring->txcmplq_cnt++;
257 if (unlikely(pring->ringno == LPFC_ELS_RING))
2e0fef85
JS		 258 mod_timer(&piocb->vport->els_tmofunc,
259 jiffies + HZ * (phba->fc_ratov << 1));
dea3101e 260
2e0fef85 261 return 0;
dea3101e 262}
263
264static struct lpfc_iocbq *
2e0fef85 265lpfc_sli_ringtx_get(struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
dea3101e 266{
267 struct list_head *dlp;
268 struct lpfc_iocbq *cmd_iocb;
269
270 dlp = &pring->txq;
271 cmd_iocb = NULL;
272 list_remove_head((&pring->txq), cmd_iocb,
273 struct lpfc_iocbq,
274 list);
275 if (cmd_iocb) {
276 /* If the first ptr is not equal to the list header,
277 * deque the IOCBQ_t and return it.
278 */
279 pring->txq_cnt--;
280 }
2e0fef85 281 return cmd_iocb;
dea3101e 282}
283
284static IOCB_t *
285lpfc_sli_next_iocb_slot (struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
286{
ed957684
JS		 287 struct lpfc_pgp *pgp = (phba->sli_rev == 3) ?
288 &phba->slim2p->mbx.us.s3_pgp.port[pring->ringno] :
289 &phba->slim2p->mbx.us.s2.port[pring->ringno];
dea3101e 290 uint32_t max_cmd_idx = pring->numCiocb;
dea3101e 291
292 if ((pring->next_cmdidx == pring->cmdidx) &&
293 (++pring->next_cmdidx >= max_cmd_idx))
294 pring->next_cmdidx = 0;
295
296 if (unlikely(pring->local_getidx == pring->next_cmdidx)) {
297
298 pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
299
300 if (unlikely(pring->local_getidx >= max_cmd_idx)) {
301 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
302 "%d:0315 Ring %d issue: portCmdGet %d "
303 "is bigger then cmd ring %d\n",
304 phba->brd_no, pring->ringno,
305 pring->local_getidx, max_cmd_idx);
306
2e0fef85 307 phba->link_state = LPFC_HBA_ERROR;
dea3101e 308 /*
309 * All error attention handlers are posted to
310 * worker thread
311 */
312 phba->work_ha |= HA_ERATT;
313 phba->work_hs = HS_FFER3;
314 if (phba->work_wait)
315 wake_up(phba->work_wait);
316
317 return NULL;
318 }
319
320 if (pring->local_getidx == pring->next_cmdidx)
321 return NULL;
322 }
323
ed957684 324 return lpfc_cmd_iocb(phba, pring);
dea3101e 325}
326
604a3e30 327uint16_t
2e0fef85 328lpfc_sli_next_iotag(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq)
dea3101e 329{
2e0fef85
JS		 330 struct lpfc_iocbq **new_arr;
331 struct lpfc_iocbq **old_arr;
604a3e30
JB		 332 size_t new_len;
333 struct lpfc_sli *psli = &phba->sli;
334 uint16_t iotag;
dea3101e 335
2e0fef85 336 spin_lock_irq(&phba->hbalock);
604a3e30
JB		 337 iotag = psli->last_iotag;
338 if(++iotag < psli->iocbq_lookup_len) {
339 psli->last_iotag = iotag;
340 psli->iocbq_lookup[iotag] = iocbq;
2e0fef85 341 spin_unlock_irq(&phba->hbalock);
604a3e30
JB		 342 iocbq->iotag = iotag;
343 return iotag;
2e0fef85 344 } else if (psli->iocbq_lookup_len < (0xffff
604a3e30
JB		 345 - LPFC_IOCBQ_LOOKUP_INCREMENT)) {
346 new_len = psli->iocbq_lookup_len + LPFC_IOCBQ_LOOKUP_INCREMENT;
2e0fef85
JS		 347 spin_unlock_irq(&phba->hbalock);
348 new_arr = kzalloc(new_len * sizeof (struct lpfc_iocbq *),
604a3e30
JB		 349 GFP_KERNEL);
350 if (new_arr) {
2e0fef85 351 spin_lock_irq(&phba->hbalock);
604a3e30
JB		 352 old_arr = psli->iocbq_lookup;
353 if (new_len <= psli->iocbq_lookup_len) {
354 /* highly unprobable case */
355 kfree(new_arr);
356 iotag = psli->last_iotag;
357 if(++iotag < psli->iocbq_lookup_len) {
358 psli->last_iotag = iotag;
359 psli->iocbq_lookup[iotag] = iocbq;
2e0fef85 360 spin_unlock_irq(&phba->hbalock);
604a3e30
JB		 361 iocbq->iotag = iotag;
362 return iotag;
363 }
2e0fef85 364 spin_unlock_irq(&phba->hbalock);
604a3e30
JB		 365 return 0;
366 }
367 if (psli->iocbq_lookup)
368 memcpy(new_arr, old_arr,
369 ((psli->last_iotag + 1) *
370 sizeof (struct lpfc_iocbq *)));
371 psli->iocbq_lookup = new_arr;
372 psli->iocbq_lookup_len = new_len;
373 psli->last_iotag = iotag;
374 psli->iocbq_lookup[iotag] = iocbq;
2e0fef85 375 spin_unlock_irq(&phba->hbalock);
604a3e30
JB		 376 iocbq->iotag = iotag;
377 kfree(old_arr);
378 return iotag;
379 }
8f6d98d2 380 } else
2e0fef85 381 spin_unlock_irq(&phba->hbalock);
dea3101e 382
604a3e30
JB		 383 lpfc_printf_log(phba, KERN_ERR,LOG_SLI,
384 "%d:0318 Failed to allocate IOTAG.last IOTAG is %d\n",
385 phba->brd_no, psli->last_iotag);
dea3101e 386
604a3e30 387 return 0;
dea3101e 388}
389
390static void
391lpfc_sli_submit_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
392 IOCB_t *iocb, struct lpfc_iocbq *nextiocb)
393{
394 /*
604a3e30 395 * Set up an iotag
dea3101e 396 */
604a3e30 397 nextiocb->iocb.ulpIoTag = (nextiocb->iocb_cmpl) ? nextiocb->iotag : 0;
dea3101e 398
399 /*
400 * Issue iocb command to adapter
401 */
402 lpfc_sli_pcimem_bcopy(&nextiocb->iocb, iocb, sizeof (IOCB_t));
403 wmb();
404 pring->stats.iocb_cmd++;
405
406 /*
407 * If there is no completion routine to call, we can release the
408 * IOCB buffer back right now. For IOCBs, like QUE_RING_BUF,
409 * that have no rsp ring completion, iocb_cmpl MUST be NULL.
410 */
411 if (nextiocb->iocb_cmpl)
412 lpfc_sli_ringtxcmpl_put(phba, pring, nextiocb);
604a3e30 413 else
2e0fef85 414 __lpfc_sli_release_iocbq(phba, nextiocb);
dea3101e 415
416 /*
417 * Let the HBA know what IOCB slot will be the next one the
418 * driver will put a command into.
419 */
420 pring->cmdidx = pring->next_cmdidx;
ed957684 421 writel(pring->cmdidx, &phba->host_gp[pring->ringno].cmdPutInx);
dea3101e 422}
423
424static void
2e0fef85 425lpfc_sli_update_full_ring(struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
dea3101e 426{
427 int ringno = pring->ringno;
428
429 pring->flag |= LPFC_CALL_RING_AVAILABLE;
430
431 wmb();
432
433 /*
434 * Set ring 'ringno' to SET R0CE_REQ in Chip Att register.
435 * The HBA will tell us when an IOCB entry is available.
436 */
437 writel((CA_R0ATT|CA_R0CE_REQ) << (ringno*4), phba->CAregaddr);
438 readl(phba->CAregaddr); /* flush */
439
440 pring->stats.iocb_cmd_full++;
441}
442
443static void
2e0fef85 444lpfc_sli_update_ring(struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
dea3101e 445{
446 int ringno = pring->ringno;
447
448 /*
449 * Tell the HBA that there is work to do in this ring.
450 */
451 wmb();
452 writel(CA_R0ATT << (ringno * 4), phba->CAregaddr);
453 readl(phba->CAregaddr); /* flush */
454}
455
456static void
2e0fef85 457lpfc_sli_resume_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
dea3101e 458{
459 IOCB_t *iocb;
460 struct lpfc_iocbq *nextiocb;
461
462 /*
463 * Check to see if:
464 * (a) there is anything on the txq to send
465 * (b) link is up
466 * (c) link attention events can be processed (fcp ring only)
467 * (d) IOCB processing is not blocked by the outstanding mbox command.
468 */
469 if (pring->txq_cnt &&
2e0fef85 470 lpfc_is_link_up(phba) &&
dea3101e 471 (pring->ringno != phba->sli.fcp_ring ||
472 phba->sli.sli_flag & LPFC_PROCESS_LA) &&
473 !(pring->flag & LPFC_STOP_IOCB_MBX)) {
474
475 while ((iocb = lpfc_sli_next_iocb_slot(phba, pring)) &&
476 (nextiocb = lpfc_sli_ringtx_get(phba, pring)))
477 lpfc_sli_submit_iocb(phba, pring, iocb, nextiocb);
478
479 if (iocb)
480 lpfc_sli_update_ring(phba, pring);
481 else
482 lpfc_sli_update_full_ring(phba, pring);
483 }
484
485 return;
486}
487
488/* lpfc_sli_turn_on_ring is only called by lpfc_sli_handle_mb_event below */
489static void
2e0fef85 490lpfc_sli_turn_on_ring(struct lpfc_hba *phba, int ringno)
dea3101e 491{
ed957684
JS		 492 struct lpfc_pgp *pgp = (phba->sli_rev == 3) ?
493 &phba->slim2p->mbx.us.s3_pgp.port[ringno] :
494 &phba->slim2p->mbx.us.s2.port[ringno];
2e0fef85 495 unsigned long iflags;
dea3101e 496
497 /* If the ring is active, flag it */
2e0fef85 498 spin_lock_irqsave(&phba->hbalock, iflags);
dea3101e 499 if (phba->sli.ring[ringno].cmdringaddr) {
500 if (phba->sli.ring[ringno].flag & LPFC_STOP_IOCB_MBX) {
501 phba->sli.ring[ringno].flag &= ~LPFC_STOP_IOCB_MBX;
502 /*
503 * Force update of the local copy of cmdGetInx
504 */
505 phba->sli.ring[ringno].local_getidx
506 = le32_to_cpu(pgp->cmdGetInx);
dea3101e 507 lpfc_sli_resume_iocb(phba, &phba->sli.ring[ringno]);
dea3101e 508 }
509 }
2e0fef85 510 spin_unlock_irqrestore(&phba->hbalock, iflags);
dea3101e 511}
512
ed957684
JS		 513struct lpfc_hbq_entry *
514lpfc_sli_next_hbq_slot(struct lpfc_hba *phba, uint32_t hbqno)
515{
516 struct hbq_s *hbqp = &phba->hbqs[hbqno];
517
518 if (hbqp->next_hbqPutIdx == hbqp->hbqPutIdx &&
519 ++hbqp->next_hbqPutIdx >= hbqp->entry_count)
520 hbqp->next_hbqPutIdx = 0;
521
522 if (unlikely(hbqp->local_hbqGetIdx == hbqp->next_hbqPutIdx)) {
523 uint32_t raw_index = readl(&phba->hbq_get[hbqno]);
524 uint32_t getidx = le32_to_cpu(raw_index);
525
526 hbqp->local_hbqGetIdx = getidx;
527
528 if (unlikely(hbqp->local_hbqGetIdx >= hbqp->entry_count)) {
529 lpfc_printf_log(phba, KERN_ERR,
530 LOG_SLI,
531 "%d:1802 HBQ %d: local_hbqGetIdx "
532 "%u is > than hbqp->entry_count %u\n",
533 phba->brd_no, hbqno,
534 hbqp->local_hbqGetIdx,
535 hbqp->entry_count);
536
537 phba->link_state = LPFC_HBA_ERROR;
538 return NULL;
539 }
540
541 if (hbqp->local_hbqGetIdx == hbqp->next_hbqPutIdx)
542 return NULL;
543 }
544
545 return (struct lpfc_hbq_entry *) phba->hbqslimp.virt + hbqp->hbqPutIdx;
546}
547
548void
549lpfc_sli_hbqbuf_free_all(struct lpfc_hba *phba)
550{
551 uint32_t i;
552
553 if (!phba->hbq_buffer_pool)
554 return;
555 /* Return all memory used by all HBQs */
556 for (i = 0; i < phba->hbq_buffer_count; i++) {
557 lpfc_hbq_free(phba, phba->hbq_buffer_pool[i].dbuf.virt,
558 phba->hbq_buffer_pool[i].dbuf.phys);
559 }
560 kfree(phba->hbq_buffer_pool);
561 phba->hbq_buffer_pool = NULL;
562}
563
564static void
565lpfc_sli_hbq_to_firmware(struct lpfc_hba *phba, uint32_t hbqno,
566 struct hbq_dmabuf *hbq_buf_desc)
567{
568 struct lpfc_hbq_entry *hbqe;
569
570 /* Get next HBQ entry slot to use */
571 hbqe = lpfc_sli_next_hbq_slot(phba, hbqno);
572 if (hbqe) {
573 struct hbq_s *hbqp = &phba->hbqs[hbqno];
574
575 hbqe->bde.addrHigh = putPaddrHigh(hbq_buf_desc->dbuf.phys);
576 hbqe->bde.addrLow = putPaddrLow(hbq_buf_desc->dbuf.phys);
577 hbqe->bde.tus.f.bdeSize = FCELSSIZE;
578 hbqe->bde.tus.f.bdeFlags = 0;
579 hbqe->buffer_tag = hbq_buf_desc->tag;
580 /* Sync SLIM */
581 hbqp->hbqPutIdx = hbqp->next_hbqPutIdx;
582 writel(hbqp->hbqPutIdx, phba->hbq_put + hbqno);
583 /* flush */
584 readl(phba->hbq_put + hbqno);
585 phba->hbq_buff_count++;
586 }
587}
588
589static void
590lpfc_sli_fill_hbq(struct lpfc_hba *phba, uint32_t hbqno, uint32_t buffer_index)
591{
592 struct hbq_dmabuf *hbq_buf_desc;
593 uint32_t i;
594
595 for (i = 0; i < phba->hbqs[hbqno].entry_count; i++) {
596 /* Search hbqbufq, from the begining,
597 * looking for an unused entry
598 */
599 phba->hbq_buffer_pool[buffer_index + i].tag |= hbqno << 16;
600 hbq_buf_desc = phba->hbq_buffer_pool + buffer_index + i;
601 lpfc_sli_hbq_to_firmware(phba, hbqno, hbq_buf_desc);
602 }
603}
604
605int
606lpfc_sli_hbqbuf_fill_hbq(struct lpfc_hba *phba)
607{
608 return 0;
609}
610
611static int
612lpfc_sli_hbqbuf_fill_hbqs(struct lpfc_hba *phba)
613{
614 uint32_t buffer_index = 0;
615 uint32_t hbqno;
616
617 /* Populate HBQ entries */
618 for (hbqno = 0; hbqno < phba->hbq_count; ++hbqno) {
619 /* Find ring associated with HBQ */
620
621 lpfc_sli_fill_hbq(phba, hbqno, buffer_index);
622 buffer_index += phba->hbqs[hbqno].entry_count;
623 }
624 return 0;
625}
626
627struct hbq_dmabuf *
628lpfc_sli_hbqbuf_find(struct lpfc_hba *phba, uint32_t tag)
629{
630 if ((tag & 0xffff) < phba->hbq_buffer_count)
631 return phba->hbq_buffer_pool + (tag & 0xffff);
632
633 lpfc_printf_log(phba, KERN_ERR,
634 LOG_SLI,
635 "%d:1803 Bad hbq tag. Data: x%x x%x\n",
636 phba->brd_no, tag,
637 phba->hbq_buffer_count);
638 return NULL;
639}
640
641void
642lpfc_sli_hbqbuf_free(struct lpfc_hba *phba, void *virt, dma_addr_t phys)
643{
644 uint32_t i, hbqno;
645
646 for (i = 0; i < phba->hbq_buffer_count; i++) {
647 /* Search hbqbufq, from the begining, looking for a match on
648 phys */
649 if (phba->hbq_buffer_pool[i].dbuf.phys == phys) {
650 hbqno = phba->hbq_buffer_pool[i].tag >> 16;
651 lpfc_sli_hbq_to_firmware(phba, hbqno,
652 phba->hbq_buffer_pool + i);
653 return;
654 }
655 }
656
657 lpfc_printf_log(phba, KERN_ERR,
658 LOG_SLI,
659 "%d:1804 Cannot find virtual addr for "
660 "mapped buf. Data x%llx\n",
661 phba->brd_no, (unsigned long long) phys);
662}
663
664void
665lpfc_sli_free_hbq(struct lpfc_hba *phba, struct hbq_dmabuf *sp)
666{
667 uint32_t hbqno;
668
669 if (sp) {
670 hbqno = sp->tag >> 16;
671 lpfc_sli_hbq_to_firmware(phba, hbqno, sp);
672 }
673}
674
dea3101e 675static int
676lpfc_sli_chk_mbx_command(uint8_t mbxCommand)
677{
678 uint8_t ret;
679
680 switch (mbxCommand) {
681 case MBX_LOAD_SM:
682 case MBX_READ_NV:
683 case MBX_WRITE_NV:
684 case MBX_RUN_BIU_DIAG:
685 case MBX_INIT_LINK:
686 case MBX_DOWN_LINK:
687 case MBX_CONFIG_LINK:
688 case MBX_CONFIG_RING:
689 case MBX_RESET_RING:
690 case MBX_READ_CONFIG:
691 case MBX_READ_RCONFIG:
692 case MBX_READ_SPARM:
693 case MBX_READ_STATUS:
694 case MBX_READ_RPI:
695 case MBX_READ_XRI:
696 case MBX_READ_REV:
697 case MBX_READ_LNK_STAT:
698 case MBX_REG_LOGIN:
699 case MBX_UNREG_LOGIN:
700 case MBX_READ_LA:
701 case MBX_CLEAR_LA:
702 case MBX_DUMP_MEMORY:
703 case MBX_DUMP_CONTEXT:
704 case MBX_RUN_DIAGS:
705 case MBX_RESTART:
706 case MBX_UPDATE_CFG:
707 case MBX_DOWN_LOAD:
708 case MBX_DEL_LD_ENTRY:
709 case MBX_RUN_PROGRAM:
710 case MBX_SET_MASK:
711 case MBX_SET_SLIM:
712 case MBX_UNREG_D_ID:
41415862 713 case MBX_KILL_BOARD:
dea3101e 714 case MBX_CONFIG_FARP:
41415862 715 case MBX_BEACON:
dea3101e 716 case MBX_LOAD_AREA:
717 case MBX_RUN_BIU_DIAG64:
718 case MBX_CONFIG_PORT:
719 case MBX_READ_SPARM64:
720 case MBX_READ_RPI64:
721 case MBX_REG_LOGIN64:
722 case MBX_READ_LA64:
723 case MBX_FLASH_WR_ULA:
724 case MBX_SET_DEBUG:
725 case MBX_LOAD_EXP_ROM:
726 ret = mbxCommand;
727 break;
728 default:
729 ret = MBX_SHUTDOWN;
730 break;
731 }
2e0fef85 732 return ret;
dea3101e 733}
734static void
2e0fef85 735lpfc_sli_wake_mbox_wait(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmboxq)
dea3101e 736{
737 wait_queue_head_t *pdone_q;
738
739 /*
740 * If pdone_q is empty, the driver thread gave up waiting and
741 * continued running.
742 */
7054a606 743 pmboxq->mbox_flag |= LPFC_MBX_WAKE;
dea3101e 744 pdone_q = (wait_queue_head_t *) pmboxq->context1;
745 if (pdone_q)
746 wake_up_interruptible(pdone_q);
747 return;
748}
749
750void
2e0fef85 751lpfc_sli_def_mbox_cmpl(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmb)
dea3101e 752{
753 struct lpfc_dmabuf *mp;
7054a606
JS		 754 uint16_t rpi;
755 int rc;
756
dea3101e 757 mp = (struct lpfc_dmabuf *) (pmb->context1);
7054a606 758
dea3101e 759 if (mp) {
760 lpfc_mbuf_free(phba, mp->virt, mp->phys);
761 kfree(mp);
762 }
7054a606
JS		 763
764 /*
765 * If a REG_LOGIN succeeded after node is destroyed or node
766 * is in re-discovery driver need to cleanup the RPI.
767 */
2e0fef85
JS		 768 if (!(phba->pport->load_flag & FC_UNLOADING) &&
769 pmb->mb.mbxCommand == MBX_REG_LOGIN64 &&
770 !pmb->mb.mbxStatus) {
7054a606
JS		 771
772 rpi = pmb->mb.un.varWords[0];
773 lpfc_unreg_login(phba, rpi, pmb);
774 pmb->mbox_cmpl=lpfc_sli_def_mbox_cmpl;
775 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
776 if (rc != MBX_NOT_FINISHED)
777 return;
778 }
779
2e0fef85 780 mempool_free(pmb, phba->mbox_mem_pool);
dea3101e 781 return;
782}
783
784int
2e0fef85 785lpfc_sli_handle_mb_event(struct lpfc_hba *phba)
dea3101e 786{
2e0fef85 787 MAILBOX_t *mbox, *pmbox;
dea3101e 788 LPFC_MBOXQ_t *pmb;
dea3101e 789 int i, rc;
790 uint32_t process_next;
2e0fef85 791 unsigned long iflags;
dea3101e 792
dea3101e 793 /* We should only get here if we are in SLI2 mode */
794 if (!(phba->sli.sli_flag & LPFC_SLI2_ACTIVE)) {
2e0fef85 795 return 1;
dea3101e 796 }
797
798 phba->sli.slistat.mbox_event++;
799
800 /* Get a Mailbox buffer to setup mailbox commands for callback */
801 if ((pmb = phba->sli.mbox_active)) {
802 pmbox = &pmb->mb;
4cc2da1d 803 mbox = &phba->slim2p->mbx;
dea3101e 804
805 /* First check out the status word */
806 lpfc_sli_pcimem_bcopy(mbox, pmbox, sizeof (uint32_t));
807
808 /* Sanity check to ensure the host owns the mailbox */
809 if (pmbox->mbxOwner != OWN_HOST) {
810 /* Lets try for a while */
811 for (i = 0; i < 10240; i++) {
812 /* First copy command data */
813 lpfc_sli_pcimem_bcopy(mbox, pmbox,
814 sizeof (uint32_t));
815 if (pmbox->mbxOwner == OWN_HOST)
816 goto mbout;
817 }
818 /* Stray Mailbox Interrupt, mbxCommand <cmd> mbxStatus
819 <status> */
820 lpfc_printf_log(phba,
b4c02652 821 KERN_WARNING,
dea3101e 822 LOG_MBOX | LOG_SLI,
823 "%d:0304 Stray Mailbox Interrupt "
824 "mbxCommand x%x mbxStatus x%x\n",
825 phba->brd_no,
826 pmbox->mbxCommand,
827 pmbox->mbxStatus);
828
2e0fef85 829 spin_lock_irq(&phba->hbalock);
dea3101e 830 phba->sli.sli_flag |= LPFC_SLI_MBOX_ACTIVE;
2e0fef85
JS		 831 spin_unlock_irq(&phba->hbalock);
832 return 1;
dea3101e 833 }
834
835 mbout:
836 del_timer_sync(&phba->sli.mbox_tmo);
2e0fef85
JS		 837
838 spin_lock_irqsave(&phba->pport->work_port_lock, iflags);
839 phba->pport->work_port_events &= ~WORKER_MBOX_TMO;
840 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflags);
dea3101e 841
842 /*
843 * It is a fatal error if unknown mbox command completion.
844 */
845 if (lpfc_sli_chk_mbx_command(pmbox->mbxCommand) ==
846 MBX_SHUTDOWN) {
847
848 /* Unknow mailbox command compl */
849 lpfc_printf_log(phba,
850 KERN_ERR,
851 LOG_MBOX | LOG_SLI,
852 "%d:0323 Unknown Mailbox command %x Cmpl\n",
853 phba->brd_no,
854 pmbox->mbxCommand);
2e0fef85 855 phba->link_state = LPFC_HBA_ERROR;
dea3101e 856 phba->work_hs = HS_FFER3;
857 lpfc_handle_eratt(phba);
2e0fef85 858 return 0;
dea3101e 859 }
860
861 phba->sli.mbox_active = NULL;
862 if (pmbox->mbxStatus) {
863 phba->sli.slistat.mbox_stat_err++;
864 if (pmbox->mbxStatus == MBXERR_NO_RESOURCES) {
865 /* Mbox cmd cmpl error - RETRYing */
866 lpfc_printf_log(phba,
867 KERN_INFO,
868 LOG_MBOX | LOG_SLI,
869 "%d:0305 Mbox cmd cmpl error - "
870 "RETRYing Data: x%x x%x x%x x%x\n",
871 phba->brd_no,
872 pmbox->mbxCommand,
873 pmbox->mbxStatus,
874 pmbox->un.varWords[0],
2e0fef85 875 phba->pport->port_state);
dea3101e 876 pmbox->mbxStatus = 0;
877 pmbox->mbxOwner = OWN_HOST;
2e0fef85 878 spin_lock_irq(&phba->hbalock);
dea3101e 879 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
2e0fef85 880 spin_unlock_irq(&phba->hbalock);
dea3101e 881 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
882 if (rc == MBX_SUCCESS)
2e0fef85 883 return 0;
dea3101e 884 }
885 }
886
887 /* Mailbox cmd <cmd> Cmpl <cmpl> */
888 lpfc_printf_log(phba,
889 KERN_INFO,
890 LOG_MBOX | LOG_SLI,
891 "%d:0307 Mailbox cmd x%x Cmpl x%p "
892 "Data: x%x x%x x%x x%x x%x x%x x%x x%x x%x\n",
893 phba->brd_no,
894 pmbox->mbxCommand,
895 pmb->mbox_cmpl,
896 *((uint32_t *) pmbox),
897 pmbox->un.varWords[0],
898 pmbox->un.varWords[1],
899 pmbox->un.varWords[2],
900 pmbox->un.varWords[3],
901 pmbox->un.varWords[4],
902 pmbox->un.varWords[5],
903 pmbox->un.varWords[6],
904 pmbox->un.varWords[7]);
905
906 if (pmb->mbox_cmpl) {
907 lpfc_sli_pcimem_bcopy(mbox, pmbox, MAILBOX_CMD_SIZE);
908 pmb->mbox_cmpl(phba,pmb);
909 }
910 }
911
912
913 do {
914 process_next = 0; /* by default don't loop */
2e0fef85 915 spin_lock_irq(&phba->hbalock);
dea3101e 916 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
917
918 /* Process next mailbox command if there is one */
919 if ((pmb = lpfc_mbox_get(phba))) {
2e0fef85 920 spin_unlock_irq(&phba->hbalock);
dea3101e 921 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
922 if (rc == MBX_NOT_FINISHED) {
923 pmb->mb.mbxStatus = MBX_NOT_FINISHED;
924 pmb->mbox_cmpl(phba,pmb);
925 process_next = 1;
926 continue; /* loop back */
927 }
928 } else {
2e0fef85 929 spin_unlock_irq(&phba->hbalock);
dea3101e 930 /* Turn on IOCB processing */
1dcb58e5 931 for (i = 0; i < phba->sli.num_rings; i++)
dea3101e 932 lpfc_sli_turn_on_ring(phba, i);
dea3101e 933 }
934
935 } while (process_next);
936
2e0fef85 937 return 0;
dea3101e 938}
939static int
940lpfc_sli_process_unsol_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
941 struct lpfc_iocbq *saveq)
942{
943 IOCB_t * irsp;
944 WORD5 * w5p;
945 uint32_t Rctl, Type;
946 uint32_t match, i;
947
948 match = 0;
949 irsp = &(saveq->iocb);
950 if ((irsp->ulpCommand == CMD_RCV_ELS_REQ64_CX)
ed957684
JS		 951 || (irsp->ulpCommand == CMD_RCV_ELS_REQ_CX)
952 || (irsp->ulpCommand == CMD_IOCB_RCV_ELS64_CX)
953 || (irsp->ulpCommand == CMD_IOCB_RCV_CONT64_CX)) {
dea3101e 954 Rctl = FC_ELS_REQ;
955 Type = FC_ELS_DATA;
956 } else {
957 w5p =
958 (WORD5 *) & (saveq->iocb.un.
959 ulpWord[5]);
960 Rctl = w5p->hcsw.Rctl;
961 Type = w5p->hcsw.Type;
962
963 /* Firmware Workaround */
964 if ((Rctl == 0) && (pring->ringno == LPFC_ELS_RING) &&
ed957684
JS		 965 (irsp->ulpCommand == CMD_RCV_SEQUENCE64_CX ||
966 irsp->ulpCommand == CMD_IOCB_RCV_SEQ64_CX)) {
dea3101e 967 Rctl = FC_ELS_REQ;
968 Type = FC_ELS_DATA;
969 w5p->hcsw.Rctl = Rctl;
970 w5p->hcsw.Type = Type;
971 }
972 }
973 /* unSolicited Responses */
974 if (pring->prt[0].profile) {
cf5bf97e
JW		 975 if (pring->prt[0].lpfc_sli_rcv_unsol_event)
976 (pring->prt[0].lpfc_sli_rcv_unsol_event) (phba, pring,
977 saveq);
dea3101e 978 match = 1;
979 } else {
980 /* We must search, based on rctl / type
981 for the right routine */
982 for (i = 0; i < pring->num_mask;
983 i++) {
984 if ((pring->prt[i].rctl ==
985 Rctl)
986 && (pring->prt[i].
987 type == Type)) {
cf5bf97e
JW		 988 if (pring->prt[i].lpfc_sli_rcv_unsol_event)
989 (pring->prt[i].lpfc_sli_rcv_unsol_event)
990 (phba, pring, saveq);
dea3101e 991 match = 1;
992 break;
993 }
994 }
995 }
996 if (match == 0) {
997 /* Unexpected Rctl / Type received */
998 /* Ring <ringno> handler: unexpected
999 Rctl <Rctl> Type <Type> received */
1000 lpfc_printf_log(phba,
1001 KERN_WARNING,
1002 LOG_SLI,
1003 "%d:0313 Ring %d handler: unexpected Rctl x%x "
1004 "Type x%x received \n",
1005 phba->brd_no,
1006 pring->ringno,
1007 Rctl,
1008 Type);
1009 }
1010 return(1);
1011}
1012
1013static struct lpfc_iocbq *
2e0fef85
JS		 1014lpfc_sli_iocbq_lookup(struct lpfc_hba *phba,
1015 struct lpfc_sli_ring *pring,
1016 struct lpfc_iocbq *prspiocb)
dea3101e 1017{
dea3101e 1018 struct lpfc_iocbq *cmd_iocb = NULL;
1019 uint16_t iotag;
1020
604a3e30
JB		 1021 iotag = prspiocb->iocb.ulpIoTag;
1022
1023 if (iotag != 0 && iotag <= phba->sli.last_iotag) {
1024 cmd_iocb = phba->sli.iocbq_lookup[iotag];
1025 list_del(&cmd_iocb->list);
1026 pring->txcmplq_cnt--;
1027 return cmd_iocb;
dea3101e 1028 }
1029
dea3101e 1030 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
604a3e30
JB		 1031 "%d:0317 iotag x%x is out off "
1032 "range: max iotag x%x wd0 x%x\n",
1033 phba->brd_no, iotag,
1034 phba->sli.last_iotag,
1035 *(((uint32_t *) &prspiocb->iocb) + 7));
dea3101e 1036 return NULL;
1037}
1038
1039static int
2e0fef85 1040lpfc_sli_process_sol_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
dea3101e 1041 struct lpfc_iocbq *saveq)
1042{
2e0fef85 1043 struct lpfc_iocbq *cmdiocbp;
dea3101e 1044 int rc = 1;
1045 unsigned long iflag;
1046
1047 /* Based on the iotag field, get the cmd IOCB from the txcmplq */
2e0fef85 1048 spin_lock_irqsave(&phba->hbalock, iflag);
604a3e30 1049 cmdiocbp = lpfc_sli_iocbq_lookup(phba, pring, saveq);
2e0fef85
JS		 1050 spin_unlock_irqrestore(&phba->hbalock, iflag);
1051
dea3101e 1052 if (cmdiocbp) {
1053 if (cmdiocbp->iocb_cmpl) {
1054 /*
1055 * Post all ELS completions to the worker thread.
1056 * All other are passed to the completion callback.
1057 */
1058 if (pring->ringno == LPFC_ELS_RING) {
07951076
JS		 1059 if (cmdiocbp->iocb_flag & LPFC_DRIVER_ABORTED) {
1060 cmdiocbp->iocb_flag &=
1061 ~LPFC_DRIVER_ABORTED;
1062 saveq->iocb.ulpStatus =
1063 IOSTAT_LOCAL_REJECT;
1064 saveq->iocb.un.ulpWord[4] =
1065 IOERR_SLI_ABORTED;
1066 }
dea3101e 1067 }
2e0fef85 1068 (cmdiocbp->iocb_cmpl) (phba, cmdiocbp, saveq);
604a3e30
JB		 1069 } else
1070 lpfc_sli_release_iocbq(phba, cmdiocbp);
dea3101e 1071 } else {
1072 /*
1073 * Unknown initiating command based on the response iotag.
1074 * This could be the case on the ELS ring because of
1075 * lpfc_els_abort().
1076 */
1077 if (pring->ringno != LPFC_ELS_RING) {
1078 /*
1079 * Ring <ringno> handler: unexpected completion IoTag
1080 * <IoTag>
1081 */
1082 lpfc_printf_log(phba,
1083 KERN_WARNING,
1084 LOG_SLI,
1085 "%d:0322 Ring %d handler: unexpected "
1086 "completion IoTag x%x Data: x%x x%x x%x x%x\n",
1087 phba->brd_no,
1088 pring->ringno,
1089 saveq->iocb.ulpIoTag,
1090 saveq->iocb.ulpStatus,
1091 saveq->iocb.un.ulpWord[4],
1092 saveq->iocb.ulpCommand,
1093 saveq->iocb.ulpContext);
1094 }
1095 }
68876920 1096
dea3101e 1097 return rc;
1098}
1099
2e0fef85
JS		 1100static void
1101lpfc_sli_rsp_pointers_error(struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
875fbdfe 1102{
ed957684
JS		 1103 struct lpfc_pgp *pgp = (phba->sli_rev == 3) ?
1104 &phba->slim2p->mbx.us.s3_pgp.port[pring->ringno] :
1105 &phba->slim2p->mbx.us.s2.port[pring->ringno];
1106
875fbdfe
JSEC		 1107 /*
1108 * Ring <ringno> handler: portRspPut <portRspPut> is bigger then
1109 * rsp ring <portRspMax>
1110 */
1111 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
1112 "%d:0312 Ring %d handler: portRspPut %d "
1113 "is bigger then rsp ring %d\n",
1114 phba->brd_no, pring->ringno,
1115 le32_to_cpu(pgp->rspPutInx),
1116 pring->numRiocb);
1117
2e0fef85 1118 phba->link_state = LPFC_HBA_ERROR;
875fbdfe
JSEC		 1119
1120 /*
1121 * All error attention handlers are posted to
1122 * worker thread
1123 */
1124 phba->work_ha |= HA_ERATT;
1125 phba->work_hs = HS_FFER3;
1126 if (phba->work_wait)
1127 wake_up(phba->work_wait);
1128
1129 return;
1130}
1131
2e0fef85 1132void lpfc_sli_poll_fcp_ring(struct lpfc_hba *phba)
875fbdfe 1133{
2e0fef85
JS		 1134 struct lpfc_sli *psli = &phba->sli;
1135 struct lpfc_sli_ring *pring = &psli->ring[LPFC_FCP_RING];
875fbdfe
JSEC		 1136 IOCB_t *irsp = NULL;
1137 IOCB_t *entry = NULL;
1138 struct lpfc_iocbq *cmdiocbq = NULL;
1139 struct lpfc_iocbq rspiocbq;
1140 struct lpfc_pgp *pgp;
1141 uint32_t status;
1142 uint32_t portRspPut, portRspMax;
1143 int type;
1144 uint32_t rsp_cmpl = 0;
875fbdfe 1145 uint32_t ha_copy;
2e0fef85 1146 unsigned long iflags;
875fbdfe
JSEC		 1147
1148 pring->stats.iocb_event++;
1149
ed957684
JS		 1150 pgp = (phba->sli_rev == 3) ?
1151 &phba->slim2p->mbx.us.s3_pgp.port[pring->ringno] :
1152 &phba->slim2p->mbx.us.s2.port[pring->ringno];
1153
875fbdfe
JSEC		 1154
1155 /*
1156 * The next available response entry should never exceed the maximum
1157 * entries. If it does, treat it as an adapter hardware error.
1158 */
1159 portRspMax = pring->numRiocb;
1160 portRspPut = le32_to_cpu(pgp->rspPutInx);
1161 if (unlikely(portRspPut >= portRspMax)) {
1162 lpfc_sli_rsp_pointers_error(phba, pring);
1163 return;
1164 }
1165
1166 rmb();
1167 while (pring->rspidx != portRspPut) {
ed957684 1168 entry = lpfc_resp_iocb(phba, pring);
875fbdfe
JSEC		 1169 if (++pring->rspidx >= portRspMax)
1170 pring->rspidx = 0;
1171
1172 lpfc_sli_pcimem_bcopy((uint32_t *) entry,
1173 (uint32_t *) &rspiocbq.iocb,
2e0fef85 1174 sizeof(IOCB_t));
875fbdfe
JSEC		 1175 irsp = &rspiocbq.iocb;
1176 type = lpfc_sli_iocb_cmd_type(irsp->ulpCommand & CMD_IOCB_MASK);
1177 pring->stats.iocb_rsp++;
1178 rsp_cmpl++;
1179
1180 if (unlikely(irsp->ulpStatus)) {
1181 /* Rsp ring <ringno> error: IOCB */
1182 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
1183 "%d:0326 Rsp Ring %d error: IOCB Data: "
1184 "x%x x%x x%x x%x x%x x%x x%x x%x\n",
1185 phba->brd_no, pring->ringno,
1186 irsp->un.ulpWord[0],
1187 irsp->un.ulpWord[1],
1188 irsp->un.ulpWord[2],
1189 irsp->un.ulpWord[3],
1190 irsp->un.ulpWord[4],
1191 irsp->un.ulpWord[5],
1192 *(((uint32_t *) irsp) + 6),
1193 *(((uint32_t *) irsp) + 7));
1194 }
1195
1196 switch (type) {
1197 case LPFC_ABORT_IOCB:
1198 case LPFC_SOL_IOCB:
1199 /*
1200 * Idle exchange closed via ABTS from port. No iocb
1201 * resources need to be recovered.
1202 */
1203 if (unlikely(irsp->ulpCommand == CMD_XRI_ABORTED_CX)) {
dca9479b
JS		 1204 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
1205 "%d:0314 IOCB cmd 0x%x"
1206 " processed. Skipping"
1207 " completion", phba->brd_no,
1208 irsp->ulpCommand);
875fbdfe
JSEC		 1209 break;
1210 }
1211
2e0fef85 1212 spin_lock_irqsave(&phba->hbalock, iflags);
875fbdfe
JSEC		 1213 cmdiocbq = lpfc_sli_iocbq_lookup(phba, pring,
1214 &rspiocbq);
2e0fef85 1215 spin_unlock_irqrestore(&phba->hbalock, iflags);
875fbdfe
JSEC		 1216 if ((cmdiocbq) && (cmdiocbq->iocb_cmpl)) {
1217 (cmdiocbq->iocb_cmpl)(phba, cmdiocbq,
1218 &rspiocbq);
1219 }
1220 break;
1221 default:
1222 if (irsp->ulpCommand == CMD_ADAPTER_MSG) {
1223 char adaptermsg[LPFC_MAX_ADPTMSG];
1224 memset(adaptermsg, 0, LPFC_MAX_ADPTMSG);
1225 memcpy(&adaptermsg[0], (uint8_t *) irsp,
1226 MAX_MSG_DATA);
1227 dev_warn(&((phba->pcidev)->dev), "lpfc%d: %s",
1228 phba->brd_no, adaptermsg);
1229 } else {
1230 /* Unknown IOCB command */
1231 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
1232 "%d:0321 Unknown IOCB command "
1233 "Data: x%x, x%x x%x x%x x%x\n",
1234 phba->brd_no, type,
1235 irsp->ulpCommand,
1236 irsp->ulpStatus,
1237 irsp->ulpIoTag,
1238 irsp->ulpContext);
1239 }
1240 break;
1241 }
1242
1243 /*
1244 * The response IOCB has been processed. Update the ring
1245 * pointer in SLIM. If the port response put pointer has not
1246 * been updated, sync the pgp->rspPutInx and fetch the new port
1247 * response put pointer.
1248 */
ed957684 1249 writel(pring->rspidx, &phba->host_gp[pring->ringno].rspGetInx);
875fbdfe
JSEC		 1250
1251 if (pring->rspidx == portRspPut)
1252 portRspPut = le32_to_cpu(pgp->rspPutInx);
1253 }
1254
1255 ha_copy = readl(phba->HAregaddr);
1256 ha_copy >>= (LPFC_FCP_RING * 4);
1257
1258 if ((rsp_cmpl > 0) && (ha_copy & HA_R0RE_REQ)) {
2e0fef85 1259 spin_lock_irqsave(&phba->hbalock, iflags);
875fbdfe
JSEC		 1260 pring->stats.iocb_rsp_full++;
1261 status = ((CA_R0ATT | CA_R0RE_RSP) << (LPFC_FCP_RING * 4));
1262 writel(status, phba->CAregaddr);
1263 readl(phba->CAregaddr);
2e0fef85 1264 spin_unlock_irqrestore(&phba->hbalock, iflags);
875fbdfe
JSEC		 1265 }
1266 if ((ha_copy & HA_R0CE_RSP) &&
1267 (pring->flag & LPFC_CALL_RING_AVAILABLE)) {
2e0fef85 1268 spin_lock_irqsave(&phba->hbalock, iflags);
875fbdfe
JSEC		 1269 pring->flag &= ~LPFC_CALL_RING_AVAILABLE;
1270 pring->stats.iocb_cmd_empty++;
1271
1272 /* Force update of the local copy of cmdGetInx */
1273 pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
1274 lpfc_sli_resume_iocb(phba, pring);
1275
1276 if ((pring->lpfc_sli_cmd_available))
1277 (pring->lpfc_sli_cmd_available) (phba, pring);
1278
2e0fef85 1279 spin_unlock_irqrestore(&phba->hbalock, iflags);
875fbdfe
JSEC		 1280 }
1281
1282 return;
1283}
1284
dea3101e 1285/*
1286 * This routine presumes LPFC_FCP_RING handling and doesn't bother
1287 * to check it explicitly.
1288 */
1289static int
2e0fef85
JS		 1290lpfc_sli_handle_fast_ring_event(struct lpfc_hba *phba,
1291 struct lpfc_sli_ring *pring, uint32_t mask)
dea3101e 1292{
ed957684
JS		 1293 struct lpfc_pgp *pgp = (phba->sli_rev == 3) ?
1294 &phba->slim2p->mbx.us.s3_pgp.port[pring->ringno] :
1295 &phba->slim2p->mbx.us.s2.port[pring->ringno];
dea3101e 1296 IOCB_t *irsp = NULL;
87f6eaff 1297 IOCB_t *entry = NULL;
dea3101e 1298 struct lpfc_iocbq *cmdiocbq = NULL;
1299 struct lpfc_iocbq rspiocbq;
dea3101e 1300 uint32_t status;
1301 uint32_t portRspPut, portRspMax;
1302 int rc = 1;
1303 lpfc_iocb_type type;
1304 unsigned long iflag;
1305 uint32_t rsp_cmpl = 0;
dea3101e 1306
2e0fef85 1307 spin_lock_irqsave(&phba->hbalock, iflag);
dea3101e 1308 pring->stats.iocb_event++;
1309
dea3101e 1310 /*
1311 * The next available response entry should never exceed the maximum
1312 * entries. If it does, treat it as an adapter hardware error.
1313 */
1314 portRspMax = pring->numRiocb;
1315 portRspPut = le32_to_cpu(pgp->rspPutInx);
1316 if (unlikely(portRspPut >= portRspMax)) {
875fbdfe 1317 lpfc_sli_rsp_pointers_error(phba, pring);
2e0fef85 1318 spin_unlock_irqrestore(&phba->hbalock, iflag);
dea3101e 1319 return 1;
1320 }
1321
1322 rmb();
1323 while (pring->rspidx != portRspPut) {
87f6eaff
JSEC		 1324 /*
1325 * Fetch an entry off the ring and copy it into a local data
1326 * structure. The copy involves a byte-swap since the
1327 * network byte order and pci byte orders are different.
1328 */
ed957684 1329 entry = lpfc_resp_iocb(phba, pring);
875fbdfe
JSEC		 1330
1331 if (++pring->rspidx >= portRspMax)
1332 pring->rspidx = 0;
1333
87f6eaff
JSEC		 1334 lpfc_sli_pcimem_bcopy((uint32_t *) entry,
1335 (uint32_t *) &rspiocbq.iocb,
ed957684 1336 phba->iocb_rsp_size);
a4bc3379 1337 INIT_LIST_HEAD(&(rspiocbq.list));
87f6eaff
JSEC		 1338 irsp = &rspiocbq.iocb;
1339
dea3101e 1340 type = lpfc_sli_iocb_cmd_type(irsp->ulpCommand & CMD_IOCB_MASK);
1341 pring->stats.iocb_rsp++;
1342 rsp_cmpl++;
1343
1344 if (unlikely(irsp->ulpStatus)) {
1345 /* Rsp ring <ringno> error: IOCB */
1346 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
dca9479b 1347 "%d:0336 Rsp Ring %d error: IOCB Data: "
dea3101e 1348 "x%x x%x x%x x%x x%x x%x x%x x%x\n",
1349 phba->brd_no, pring->ringno,
1350 irsp->un.ulpWord[0], irsp->un.ulpWord[1],
1351 irsp->un.ulpWord[2], irsp->un.ulpWord[3],
1352 irsp->un.ulpWord[4], irsp->un.ulpWord[5],
1353 *(((uint32_t *) irsp) + 6),
1354 *(((uint32_t *) irsp) + 7));
1355 }
1356
1357 switch (type) {
1358 case LPFC_ABORT_IOCB:
1359 case LPFC_SOL_IOCB:
1360 /*
1361 * Idle exchange closed via ABTS from port. No iocb
1362 * resources need to be recovered.
1363 */
1364 if (unlikely(irsp->ulpCommand == CMD_XRI_ABORTED_CX)) {
dca9479b
JS		 1365 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
1366 "%d:0333 IOCB cmd 0x%x"
1367 " processed. Skipping"
1368 " completion\n", phba->brd_no,
1369 irsp->ulpCommand);
dea3101e 1370 break;
1371 }
1372
604a3e30
JB		 1373 cmdiocbq = lpfc_sli_iocbq_lookup(phba, pring,
1374 &rspiocbq);
dea3101e 1375 if ((cmdiocbq) && (cmdiocbq->iocb_cmpl)) {
b808608b
JW		 1376 if (phba->cfg_poll & ENABLE_FCP_RING_POLLING) {
1377 (cmdiocbq->iocb_cmpl)(phba, cmdiocbq,
1378 &rspiocbq);
1379 } else {
2e0fef85
JS		 1380 spin_unlock_irqrestore(&phba->hbalock,
1381 iflag);
b808608b
JW		 1382 (cmdiocbq->iocb_cmpl)(phba, cmdiocbq,
1383 &rspiocbq);
2e0fef85 1384 spin_lock_irqsave(&phba->hbalock,
b808608b
JW		 1385 iflag);
1386 }
dea3101e 1387 }
1388 break;
a4bc3379 1389 case LPFC_UNSOL_IOCB:
2e0fef85 1390 spin_unlock_irqrestore(&phba->hbalock, iflag);
a4bc3379 1391 lpfc_sli_process_unsol_iocb(phba, pring, &rspiocbq);
2e0fef85 1392 spin_lock_irqsave(&phba->hbalock, iflag);
a4bc3379 1393 break;
dea3101e 1394 default:
1395 if (irsp->ulpCommand == CMD_ADAPTER_MSG) {
1396 char adaptermsg[LPFC_MAX_ADPTMSG];
1397 memset(adaptermsg, 0, LPFC_MAX_ADPTMSG);
1398 memcpy(&adaptermsg[0], (uint8_t *) irsp,
1399 MAX_MSG_DATA);
1400 dev_warn(&((phba->pcidev)->dev), "lpfc%d: %s",
1401 phba->brd_no, adaptermsg);
1402 } else {
1403 /* Unknown IOCB command */
1404 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
dca9479b 1405 "%d:0334 Unknown IOCB command "
dea3101e 1406 "Data: x%x, x%x x%x x%x x%x\n",
1407 phba->brd_no, type, irsp->ulpCommand,
1408 irsp->ulpStatus, irsp->ulpIoTag,
1409 irsp->ulpContext);
1410 }
1411 break;
1412 }
1413
1414 /*
1415 * The response IOCB has been processed. Update the ring
1416 * pointer in SLIM. If the port response put pointer has not
1417 * been updated, sync the pgp->rspPutInx and fetch the new port
1418 * response put pointer.
1419 */
ed957684 1420 writel(pring->rspidx, &phba->host_gp[pring->ringno].rspGetInx);
dea3101e 1421
1422 if (pring->rspidx == portRspPut)
1423 portRspPut = le32_to_cpu(pgp->rspPutInx);
1424 }
1425
1426 if ((rsp_cmpl > 0) && (mask & HA_R0RE_REQ)) {
1427 pring->stats.iocb_rsp_full++;
1428 status = ((CA_R0ATT | CA_R0RE_RSP) << (pring->ringno * 4));
1429 writel(status, phba->CAregaddr);
1430 readl(phba->CAregaddr);
1431 }
1432 if ((mask & HA_R0CE_RSP) && (pring->flag & LPFC_CALL_RING_AVAILABLE)) {
1433 pring->flag &= ~LPFC_CALL_RING_AVAILABLE;
1434 pring->stats.iocb_cmd_empty++;
1435
1436 /* Force update of the local copy of cmdGetInx */
1437 pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
1438 lpfc_sli_resume_iocb(phba, pring);
1439
1440 if ((pring->lpfc_sli_cmd_available))
1441 (pring->lpfc_sli_cmd_available) (phba, pring);
1442
1443 }
1444
2e0fef85 1445 spin_unlock_irqrestore(&phba->hbalock, iflag);
dea3101e 1446 return rc;
1447}
1448
1449
1450int
2e0fef85
JS		 1451lpfc_sli_handle_slow_ring_event(struct lpfc_hba *phba,
1452 struct lpfc_sli_ring *pring, uint32_t mask)
dea3101e 1453{
ed957684
JS		 1454 struct lpfc_pgp *pgp = (phba->sli_rev == 3) ?
1455 &phba->slim2p->mbx.us.s3_pgp.port[pring->ringno] :
1456 &phba->slim2p->mbx.us.s2.port[pring->ringno];
dea3101e 1457 IOCB_t *entry;
1458 IOCB_t *irsp = NULL;
1459 struct lpfc_iocbq *rspiocbp = NULL;
1460 struct lpfc_iocbq *next_iocb;
1461 struct lpfc_iocbq *cmdiocbp;
1462 struct lpfc_iocbq *saveq;
dea3101e 1463 uint8_t iocb_cmd_type;
1464 lpfc_iocb_type type;
1465 uint32_t status, free_saveq;
1466 uint32_t portRspPut, portRspMax;
1467 int rc = 1;
1468 unsigned long iflag;
dea3101e 1469
2e0fef85 1470 spin_lock_irqsave(&phba->hbalock, iflag);
dea3101e 1471 pring->stats.iocb_event++;
1472
dea3101e 1473 /*
1474 * The next available response entry should never exceed the maximum
1475 * entries. If it does, treat it as an adapter hardware error.
1476 */
1477 portRspMax = pring->numRiocb;
1478 portRspPut = le32_to_cpu(pgp->rspPutInx);
1479 if (portRspPut >= portRspMax) {
1480 /*
1481 * Ring <ringno> handler: portRspPut <portRspPut> is bigger then
1482 * rsp ring <portRspMax>
1483 */
ed957684 1484 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
dca9479b 1485 "%d:0303 Ring %d handler: portRspPut %d "
dea3101e 1486 "is bigger then rsp ring %d\n",
1487 phba->brd_no,
1488 pring->ringno, portRspPut, portRspMax);
1489
2e0fef85
JS		 1490 phba->link_state = LPFC_HBA_ERROR;
1491 spin_unlock_irqrestore(&phba->hbalock, iflag);
dea3101e 1492
1493 phba->work_hs = HS_FFER3;
1494 lpfc_handle_eratt(phba);
1495
1496 return 1;
1497 }
1498
1499 rmb();
dea3101e 1500 while (pring->rspidx != portRspPut) {
1501 /*
1502 * Build a completion list and call the appropriate handler.
1503 * The process is to get the next available response iocb, get
1504 * a free iocb from the list, copy the response data into the
1505 * free iocb, insert to the continuation list, and update the
1506 * next response index to slim. This process makes response
1507 * iocb's in the ring available to DMA as fast as possible but
1508 * pays a penalty for a copy operation. Since the iocb is
1509 * only 32 bytes, this penalty is considered small relative to
1510 * the PCI reads for register values and a slim write. When
1511 * the ulpLe field is set, the entire Command has been
1512 * received.
1513 */
ed957684
JS		 1514 entry = lpfc_resp_iocb(phba, pring);
1515
2e0fef85 1516 rspiocbp = __lpfc_sli_get_iocbq(phba);
dea3101e 1517 if (rspiocbp == NULL) {
1518 printk(KERN_ERR "%s: out of buffers! Failing "
1519 "completion.\n", __FUNCTION__);
1520 break;
1521 }
1522
ed957684
JS		 1523 lpfc_sli_pcimem_bcopy(entry, &rspiocbp->iocb,
1524 phba->iocb_rsp_size);
dea3101e 1525 irsp = &rspiocbp->iocb;
1526
1527 if (++pring->rspidx >= portRspMax)
1528 pring->rspidx = 0;
1529
ed957684 1530 writel(pring->rspidx, &phba->host_gp[pring->ringno].rspGetInx);
dea3101e 1531
1532 if (list_empty(&(pring->iocb_continueq))) {
1533 list_add(&rspiocbp->list, &(pring->iocb_continueq));
1534 } else {
1535 list_add_tail(&rspiocbp->list,
1536 &(pring->iocb_continueq));
1537 }
1538
1539 pring->iocb_continueq_cnt++;
1540 if (irsp->ulpLe) {
1541 /*
1542 * By default, the driver expects to free all resources
1543 * associated with this iocb completion.
1544 */
1545 free_saveq = 1;
1546 saveq = list_get_first(&pring->iocb_continueq,
1547 struct lpfc_iocbq, list);
1548 irsp = &(saveq->iocb);
1549 list_del_init(&pring->iocb_continueq);
1550 pring->iocb_continueq_cnt = 0;
1551
1552 pring->stats.iocb_rsp++;
1553
1554 if (irsp->ulpStatus) {
1555 /* Rsp ring <ringno> error: IOCB */
ed957684
JS		 1556 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
1557 "%d:0328 Rsp Ring %d error: "
1558 "IOCB Data: "
1559 "x%x x%x x%x x%x "
1560 "x%x x%x x%x x%x "
1561 "x%x x%x x%x x%x "
1562 "x%x x%x x%x x%x\n",
1563 phba->brd_no,
1564 pring->ringno,
1565 irsp->un.ulpWord[0],
1566 irsp->un.ulpWord[1],
1567 irsp->un.ulpWord[2],
1568 irsp->un.ulpWord[3],
1569 irsp->un.ulpWord[4],
1570 irsp->un.ulpWord[5],
1571 *(((uint32_t *) irsp) + 6),
1572 *(((uint32_t *) irsp) + 7),
1573 *(((uint32_t *) irsp) + 8),
1574 *(((uint32_t *) irsp) + 9),
1575 *(((uint32_t *) irsp) + 10),
1576 *(((uint32_t *) irsp) + 11),
1577 *(((uint32_t *) irsp) + 12),
1578 *(((uint32_t *) irsp) + 13),
1579 *(((uint32_t *) irsp) + 14),
1580 *(((uint32_t *) irsp) + 15));
dea3101e 1581 }
1582
1583 /*
1584 * Fetch the IOCB command type and call the correct
1585 * completion routine. Solicited and Unsolicited
1586 * IOCBs on the ELS ring get freed back to the
1587 * lpfc_iocb_list by the discovery kernel thread.
1588 */
1589 iocb_cmd_type = irsp->ulpCommand & CMD_IOCB_MASK;
1590 type = lpfc_sli_iocb_cmd_type(iocb_cmd_type);
1591 if (type == LPFC_SOL_IOCB) {
2e0fef85 1592 spin_unlock_irqrestore(&phba->hbalock,
dea3101e 1593 iflag);
1594 rc = lpfc_sli_process_sol_iocb(phba, pring,
2e0fef85
JS		 1595 saveq);
1596 spin_lock_irqsave(&phba->hbalock, iflag);
dea3101e 1597 } else if (type == LPFC_UNSOL_IOCB) {
2e0fef85 1598 spin_unlock_irqrestore(&phba->hbalock,
dea3101e 1599 iflag);
1600 rc = lpfc_sli_process_unsol_iocb(phba, pring,
2e0fef85
JS		 1601 saveq);
1602 spin_lock_irqsave(&phba->hbalock, iflag);
dea3101e 1603 } else if (type == LPFC_ABORT_IOCB) {
1604 if ((irsp->ulpCommand != CMD_XRI_ABORTED_CX) &&
1605 ((cmdiocbp =
604a3e30
JB		 1606 lpfc_sli_iocbq_lookup(phba, pring,
1607 saveq)))) {
dea3101e 1608 /* Call the specified completion
1609 routine */
1610 if (cmdiocbp->iocb_cmpl) {
1611 spin_unlock_irqrestore(
2e0fef85 1612 &phba->hbalock,
dea3101e 1613 iflag);
1614 (cmdiocbp->iocb_cmpl) (phba,
1615 cmdiocbp, saveq);
1616 spin_lock_irqsave(
2e0fef85 1617 &phba->hbalock,
dea3101e 1618 iflag);
604a3e30 1619 } else
2e0fef85 1620 __lpfc_sli_release_iocbq(phba,
604a3e30 1621 cmdiocbp);
dea3101e 1622 }
1623 } else if (type == LPFC_UNKNOWN_IOCB) {
1624 if (irsp->ulpCommand == CMD_ADAPTER_MSG) {
1625
1626 char adaptermsg[LPFC_MAX_ADPTMSG];
1627
1628 memset(adaptermsg, 0,
1629 LPFC_MAX_ADPTMSG);
1630 memcpy(&adaptermsg[0], (uint8_t *) irsp,
1631 MAX_MSG_DATA);
1632 dev_warn(&((phba->pcidev)->dev),
1633 "lpfc%d: %s",
1634 phba->brd_no, adaptermsg);
1635 } else {
1636 /* Unknown IOCB command */
1637 lpfc_printf_log(phba,
1638 KERN_ERR,
1639 LOG_SLI,
dca9479b 1640 "%d:0335 Unknown IOCB command "
dea3101e 1641 "Data: x%x x%x x%x x%x\n",
1642 phba->brd_no,
1643 irsp->ulpCommand,
1644 irsp->ulpStatus,
1645 irsp->ulpIoTag,
1646 irsp->ulpContext);
1647 }
1648 }
1649
1650 if (free_saveq) {
2e0fef85
JS		 1651 list_for_each_entry_safe(rspiocbp, next_iocb,
1652 &saveq->list, list) {
1653 list_del(&rspiocbp->list);
1654 __lpfc_sli_release_iocbq(phba,
1655 rspiocbp);
dea3101e 1656 }
2e0fef85 1657 __lpfc_sli_release_iocbq(phba, saveq);
dea3101e 1658 }
1659 }
1660
1661 /*
1662 * If the port response put pointer has not been updated, sync
1663 * the pgp->rspPutInx in the MAILBOX_tand fetch the new port
1664 * response put pointer.
1665 */
1666 if (pring->rspidx == portRspPut) {
1667 portRspPut = le32_to_cpu(pgp->rspPutInx);
1668 }
1669 } /* while (pring->rspidx != portRspPut) */
1670
1671 if ((rspiocbp != 0) && (mask & HA_R0RE_REQ)) {
1672 /* At least one response entry has been freed */
1673 pring->stats.iocb_rsp_full++;
1674 /* SET RxRE_RSP in Chip Att register */
1675 status = ((CA_R0ATT | CA_R0RE_RSP) << (pring->ringno * 4));
1676 writel(status, phba->CAregaddr);
1677 readl(phba->CAregaddr); /* flush */
1678 }
1679 if ((mask & HA_R0CE_RSP) && (pring->flag & LPFC_CALL_RING_AVAILABLE)) {
1680 pring->flag &= ~LPFC_CALL_RING_AVAILABLE;
1681 pring->stats.iocb_cmd_empty++;
1682
1683 /* Force update of the local copy of cmdGetInx */
1684 pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
1685 lpfc_sli_resume_iocb(phba, pring);
1686
1687 if ((pring->lpfc_sli_cmd_available))
1688 (pring->lpfc_sli_cmd_available) (phba, pring);
1689
1690 }
1691
2e0fef85 1692 spin_unlock_irqrestore(&phba->hbalock, iflag);
dea3101e 1693 return rc;
1694}
1695
2e0fef85 1696void
dea3101e 1697lpfc_sli_abort_iocb_ring(struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
1698{
2534ba75 1699 LIST_HEAD(completions);
dea3101e 1700 struct lpfc_iocbq *iocb, *next_iocb;
2534ba75 1701 IOCB_t *cmd = NULL;
dea3101e 1702
1703 /* Error everything on txq and txcmplq
1704 * First do the txq.
1705 */
2e0fef85 1706 spin_lock_irq(&phba->hbalock);
2534ba75 1707 list_splice_init(&pring->txq, &completions);
dea3101e 1708 pring->txq_cnt = 0;
dea3101e 1709
1710 /* Next issue ABTS for everything on the txcmplq */
2534ba75
JS		 1711 list_for_each_entry_safe(iocb, next_iocb, &pring->txcmplq, list)
1712 lpfc_sli_issue_abort_iotag(phba, pring, iocb);
dea3101e 1713
2e0fef85 1714 spin_unlock_irq(&phba->hbalock);
dea3101e 1715
2534ba75
JS		 1716 while (!list_empty(&completions)) {
1717 iocb = list_get_first(&completions, struct lpfc_iocbq, list);
1718 cmd = &iocb->iocb;
1719 list_del(&iocb->list);
dea3101e 1720
2e0fef85
JS		 1721 if (!iocb->iocb_cmpl)
1722 lpfc_sli_release_iocbq(phba, iocb);
1723 else {
dea3101e 1724 cmd->ulpStatus = IOSTAT_LOCAL_REJECT;
1725 cmd->un.ulpWord[4] = IOERR_SLI_ABORTED;
dea3101e 1726 (iocb->iocb_cmpl) (phba, iocb, iocb);
2e0fef85 1727 }
dea3101e 1728 }
dea3101e 1729}
1730
41415862 1731int
2e0fef85 1732lpfc_sli_brdready(struct lpfc_hba *phba, uint32_t mask)
dea3101e 1733{
41415862
JW		 1734 uint32_t status;
1735 int i = 0;
1736 int retval = 0;
dea3101e 1737
41415862
JW		 1738 /* Read the HBA Host Status Register */
1739 status = readl(phba->HSregaddr);
dea3101e 1740
41415862
JW		 1741 /*
1742 * Check status register every 100ms for 5 retries, then every
1743 * 500ms for 5, then every 2.5 sec for 5, then reset board and
1744 * every 2.5 sec for 4.
1745 * Break our of the loop if errors occurred during init.
1746 */
1747 while (((status & mask) != mask) &&
1748 !(status & HS_FFERM) &&
1749 i++ < 20) {
dea3101e 1750
41415862
JW		 1751 if (i <= 5)
1752 msleep(10);
1753 else if (i <= 10)
1754 msleep(500);
1755 else
1756 msleep(2500);
dea3101e 1757
41415862 1758 if (i == 15) {
2e0fef85
JS		 1759 /* Do post */
1760 phba->pport->port_state = LPFC_STATE_UNKNOWN;
41415862
JW		 1761 lpfc_sli_brdrestart(phba);
1762 }
1763 /* Read the HBA Host Status Register */
1764 status = readl(phba->HSregaddr);
1765 }
dea3101e 1766
41415862
JW		 1767 /* Check to see if any errors occurred during init */
1768 if ((status & HS_FFERM) || (i >= 20)) {
2e0fef85 1769 phba->link_state = LPFC_HBA_ERROR;
41415862 1770 retval = 1;
dea3101e 1771 }
dea3101e 1772
41415862
JW		 1773 return retval;
1774}
dea3101e 1775
9290831f
JS		 1776#define BARRIER_TEST_PATTERN (0xdeadbeef)
1777
2e0fef85 1778void lpfc_reset_barrier(struct lpfc_hba *phba)
9290831f 1779{
65a29c16
JS		 1780 uint32_t __iomem *resp_buf;
1781 uint32_t __iomem *mbox_buf;
9290831f
JS		 1782 volatile uint32_t mbox;
1783 uint32_t hc_copy;
1784 int i;
1785 uint8_t hdrtype;
1786
1787 pci_read_config_byte(phba->pcidev, PCI_HEADER_TYPE, &hdrtype);
1788 if (hdrtype != 0x80 ||
1789 (FC_JEDEC_ID(phba->vpd.rev.biuRev) != HELIOS_JEDEC_ID &&
1790 FC_JEDEC_ID(phba->vpd.rev.biuRev) != THOR_JEDEC_ID))
1791 return;
1792
1793 /*
1794 * Tell the other part of the chip to suspend temporarily all
1795 * its DMA activity.
1796 */
65a29c16 1797 resp_buf = phba->MBslimaddr;
9290831f
JS		 1798
1799 /* Disable the error attention */
1800 hc_copy = readl(phba->HCregaddr);
1801 writel((hc_copy & ~HC_ERINT_ENA), phba->HCregaddr);
1802 readl(phba->HCregaddr); /* flush */
2e0fef85 1803 phba->link_flag |= LS_IGNORE_ERATT;
9290831f
JS		 1804
1805 if (readl(phba->HAregaddr) & HA_ERATT) {
1806 /* Clear Chip error bit */
1807 writel(HA_ERATT, phba->HAregaddr);
2e0fef85 1808 phba->pport->stopped = 1;
9290831f
JS		 1809 }
1810
1811 mbox = 0;
1812 ((MAILBOX_t *)&mbox)->mbxCommand = MBX_KILL_BOARD;
1813 ((MAILBOX_t *)&mbox)->mbxOwner = OWN_CHIP;
1814
1815 writel(BARRIER_TEST_PATTERN, (resp_buf + 1));
65a29c16 1816 mbox_buf = phba->MBslimaddr;
9290831f
JS		 1817 writel(mbox, mbox_buf);
1818
1819 for (i = 0;
1820 readl(resp_buf + 1) != ~(BARRIER_TEST_PATTERN) && i < 50; i++)
1821 mdelay(1);
1822
1823 if (readl(resp_buf + 1) != ~(BARRIER_TEST_PATTERN)) {
1824 if (phba->sli.sli_flag & LPFC_SLI2_ACTIVE ||
2e0fef85 1825 phba->pport->stopped)
9290831f
JS		 1826 goto restore_hc;
1827 else
1828 goto clear_errat;
1829 }
1830
1831 ((MAILBOX_t *)&mbox)->mbxOwner = OWN_HOST;
1832 for (i = 0; readl(resp_buf) != mbox && i < 500; i++)
1833 mdelay(1);
1834
1835clear_errat:
1836
1837 while (!(readl(phba->HAregaddr) & HA_ERATT) && ++i < 500)
1838 mdelay(1);
1839
1840 if (readl(phba->HAregaddr) & HA_ERATT) {
1841 writel(HA_ERATT, phba->HAregaddr);
2e0fef85 1842 phba->pport->stopped = 1;
9290831f
JS		 1843 }
1844
1845restore_hc:
2e0fef85 1846 phba->link_flag &= ~LS_IGNORE_ERATT;
9290831f
JS		 1847 writel(hc_copy, phba->HCregaddr);
1848 readl(phba->HCregaddr); /* flush */
1849}
1850
41415862 1851int
2e0fef85 1852lpfc_sli_brdkill(struct lpfc_hba *phba)
41415862
JW		 1853{
1854 struct lpfc_sli *psli;
1855 LPFC_MBOXQ_t *pmb;
1856 uint32_t status;
1857 uint32_t ha_copy;
1858 int retval;
1859 int i = 0;
dea3101e 1860
41415862 1861 psli = &phba->sli;
dea3101e 1862
41415862 1863 /* Kill HBA */
ed957684 1864 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
41415862 1865 "%d:0329 Kill HBA Data: x%x x%x\n",
ed957684 1866 phba->brd_no, phba->pport->port_state, psli->sli_flag);
41415862
JW		 1867
1868 if ((pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
9290831f 1869 GFP_KERNEL)) == 0)
41415862 1870 return 1;
41415862
JW		 1871
1872 /* Disable the error attention */
2e0fef85 1873 spin_lock_irq(&phba->hbalock);
41415862
JW		 1874 status = readl(phba->HCregaddr);
1875 status &= ~HC_ERINT_ENA;
1876 writel(status, phba->HCregaddr);
1877 readl(phba->HCregaddr); /* flush */
2e0fef85
JS		 1878 phba->link_flag |= LS_IGNORE_ERATT;
1879 spin_unlock_irq(&phba->hbalock);
41415862
JW		 1880
1881 lpfc_kill_board(phba, pmb);
1882 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
1883 retval = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
1884
1885 if (retval != MBX_SUCCESS) {
1886 if (retval != MBX_BUSY)
1887 mempool_free(pmb, phba->mbox_mem_pool);
2e0fef85
JS		 1888 spin_lock_irq(&phba->hbalock);
1889 phba->link_flag &= ~LS_IGNORE_ERATT;
1890 spin_unlock_irq(&phba->hbalock);
41415862
JW		 1891 return 1;
1892 }
1893
9290831f
JS		 1894 psli->sli_flag &= ~LPFC_SLI2_ACTIVE;
1895
41415862
JW		 1896 mempool_free(pmb, phba->mbox_mem_pool);
1897
1898 /* There is no completion for a KILL_BOARD mbox cmd. Check for an error
1899 * attention every 100ms for 3 seconds. If we don't get ERATT after
1900 * 3 seconds we still set HBA_ERROR state because the status of the
1901 * board is now undefined.
1902 */
1903 ha_copy = readl(phba->HAregaddr);
1904
1905 while ((i++ < 30) && !(ha_copy & HA_ERATT)) {
1906 mdelay(100);
1907 ha_copy = readl(phba->HAregaddr);
1908 }
1909
1910 del_timer_sync(&psli->mbox_tmo);
9290831f
JS		 1911 if (ha_copy & HA_ERATT) {
1912 writel(HA_ERATT, phba->HAregaddr);
2e0fef85 1913 phba->pport->stopped = 1;
9290831f 1914 }
2e0fef85 1915 spin_lock_irq(&phba->hbalock);
41415862 1916 psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
2e0fef85
JS		 1917 phba->link_flag &= ~LS_IGNORE_ERATT;
1918 spin_unlock_irq(&phba->hbalock);
41415862
JW		 1919
1920 psli->mbox_active = NULL;
1921 lpfc_hba_down_post(phba);
2e0fef85 1922 phba->link_state = LPFC_HBA_ERROR;
41415862 1923
2e0fef85 1924 return ha_copy & HA_ERATT ? 0 : 1;
dea3101e 1925}
1926
41415862 1927int
2e0fef85 1928lpfc_sli_brdreset(struct lpfc_hba *phba)
dea3101e 1929{
41415862 1930 struct lpfc_sli *psli;
dea3101e 1931 struct lpfc_sli_ring *pring;
41415862 1932 uint16_t cfg_value;
dea3101e 1933 int i;
dea3101e 1934
41415862 1935 psli = &phba->sli;
dea3101e 1936
41415862
JW		 1937 /* Reset HBA */
1938 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
1939 "%d:0325 Reset HBA Data: x%x x%x\n", phba->brd_no,
2e0fef85 1940 phba->pport->port_state, psli->sli_flag);
dea3101e 1941
1942 /* perform board reset */
1943 phba->fc_eventTag = 0;
2e0fef85
JS		 1944 phba->pport->fc_myDID = 0;
1945 phba->pport->fc_prevDID = 0;
dea3101e 1946
41415862
JW		 1947 /* Turn off parity checking and serr during the physical reset */
1948 pci_read_config_word(phba->pcidev, PCI_COMMAND, &cfg_value);
1949 pci_write_config_word(phba->pcidev, PCI_COMMAND,
1950 (cfg_value &
1951 ~(PCI_COMMAND_PARITY | PCI_COMMAND_SERR)));
1952
1c067a42 1953 psli->sli_flag &= ~(LPFC_SLI2_ACTIVE | LPFC_PROCESS_LA);
41415862
JW		 1954 /* Now toggle INITFF bit in the Host Control Register */
1955 writel(HC_INITFF, phba->HCregaddr);
1956 mdelay(1);
1957 readl(phba->HCregaddr); /* flush */
1958 writel(0, phba->HCregaddr);
1959 readl(phba->HCregaddr); /* flush */
1960
1961 /* Restore PCI cmd register */
1962 pci_write_config_word(phba->pcidev, PCI_COMMAND, cfg_value);
dea3101e 1963
1964 /* Initialize relevant SLI info */
41415862
JW		 1965 for (i = 0; i < psli->num_rings; i++) {
1966 pring = &psli->ring[i];
dea3101e 1967 pring->flag = 0;
1968 pring->rspidx = 0;
1969 pring->next_cmdidx = 0;
1970 pring->local_getidx = 0;
1971 pring->cmdidx = 0;
1972 pring->missbufcnt = 0;
1973 }
dea3101e 1974
2e0fef85 1975 phba->link_state = LPFC_WARM_START;
41415862
JW		 1976 return 0;
1977}
1978
1979int
2e0fef85 1980lpfc_sli_brdrestart(struct lpfc_hba *phba)
41415862
JW		 1981{
1982 MAILBOX_t *mb;
1983 struct lpfc_sli *psli;
1984 uint16_t skip_post;
1985 volatile uint32_t word0;
1986 void __iomem *to_slim;
1987
2e0fef85 1988 spin_lock_irq(&phba->hbalock);
41415862
JW		 1989
1990 psli = &phba->sli;
1991
1992 /* Restart HBA */
1993 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
dca9479b 1994 "%d:0337 Restart HBA Data: x%x x%x\n", phba->brd_no,
2e0fef85 1995 phba->pport->port_state, psli->sli_flag);
41415862
JW		 1996
1997 word0 = 0;
1998 mb = (MAILBOX_t *) &word0;
1999 mb->mbxCommand = MBX_RESTART;
2000 mb->mbxHc = 1;
2001
9290831f
JS		 2002 lpfc_reset_barrier(phba);
2003
41415862
JW		 2004 to_slim = phba->MBslimaddr;
2005 writel(*(uint32_t *) mb, to_slim);
2006 readl(to_slim); /* flush */
2007
2008 /* Only skip post after fc_ffinit is completed */
2e0fef85 2009 if (phba->pport->port_state) {
41415862
JW		 2010 skip_post = 1;
2011 word0 = 1; /* This is really setting up word1 */
dea3101e 2012 } else {
41415862
JW		 2013 skip_post = 0;
2014 word0 = 0; /* This is really setting up word1 */
dea3101e 2015 }
65a29c16 2016 to_slim = phba->MBslimaddr + sizeof (uint32_t);
41415862
JW		 2017 writel(*(uint32_t *) mb, to_slim);
2018 readl(to_slim); /* flush */
dea3101e 2019
41415862 2020 lpfc_sli_brdreset(phba);
2e0fef85
JS		 2021 phba->pport->stopped = 0;
2022 phba->link_state = LPFC_INIT_START;
41415862 2023
2e0fef85 2024 spin_unlock_irq(&phba->hbalock);
41415862 2025
64ba8818
JS		 2026 memset(&psli->lnk_stat_offsets, 0, sizeof(psli->lnk_stat_offsets));
2027 psli->stats_start = get_seconds();
2028
41415862
JW		 2029 if (skip_post)
2030 mdelay(100);
2031 else
2032 mdelay(2000);
2033
2034 lpfc_hba_down_post(phba);
dea3101e 2035
2036 return 0;
2037}
2038
2039static int
2040lpfc_sli_chipset_init(struct lpfc_hba *phba)
2041{
2042 uint32_t status, i = 0;
2043
2044 /* Read the HBA Host Status Register */
2045 status = readl(phba->HSregaddr);
2046
2047 /* Check status register to see what current state is */
2048 i = 0;
2049 while ((status & (HS_FFRDY | HS_MBRDY)) != (HS_FFRDY | HS_MBRDY)) {
2050
2051 /* Check every 100ms for 5 retries, then every 500ms for 5, then
2052 * every 2.5 sec for 5, then reset board and every 2.5 sec for
2053 * 4.
2054 */
2055 if (i++ >= 20) {
2056 /* Adapter failed to init, timeout, status reg
2057 <status> */
ed957684 2058 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
dea3101e 2059 "%d:0436 Adapter failed to init, "
2060 "timeout, status reg x%x\n",
ed957684 2061 phba->brd_no, status);
2e0fef85 2062 phba->link_state = LPFC_HBA_ERROR;
dea3101e 2063 return -ETIMEDOUT;
2064 }
2065
2066 /* Check to see if any errors occurred during init */
2067 if (status & HS_FFERM) {
2068 /* ERROR: During chipset initialization */
2069 /* Adapter failed to init, chipset, status reg
2070 <status> */
ed957684 2071 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
dea3101e 2072 "%d:0437 Adapter failed to init, "
2073 "chipset, status reg x%x\n",
2074 phba->brd_no,
2075 status);
2e0fef85 2076 phba->link_state = LPFC_HBA_ERROR;
dea3101e 2077 return -EIO;
2078 }
2079
2080 if (i <= 5) {
2081 msleep(10);
2082 } else if (i <= 10) {
2083 msleep(500);
2084 } else {
2085 msleep(2500);
2086 }
2087
2088 if (i == 15) {
2e0fef85
JS		 2089 /* Do post */
2090 phba->pport->port_state = LPFC_STATE_UNKNOWN;
41415862 2091 lpfc_sli_brdrestart(phba);
dea3101e 2092 }
2093 /* Read the HBA Host Status Register */
2094 status = readl(phba->HSregaddr);
2095 }
2096
2097 /* Check to see if any errors occurred during init */
2098 if (status & HS_FFERM) {
2099 /* ERROR: During chipset initialization */
2100 /* Adapter failed to init, chipset, status reg <status> */
ed957684 2101 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
dea3101e 2102 "%d:0438 Adapter failed to init, chipset, "
2103 "status reg x%x\n",
2104 phba->brd_no,
2105 status);
2e0fef85 2106 phba->link_state = LPFC_HBA_ERROR;
dea3101e 2107 return -EIO;
2108 }
2109
2110 /* Clear all interrupt enable conditions */
2111 writel(0, phba->HCregaddr);
2112 readl(phba->HCregaddr); /* flush */
2113
2114 /* setup host attn register */
2115 writel(0xffffffff, phba->HAregaddr);
2116 readl(phba->HAregaddr); /* flush */
2117 return 0;
2118}
2119
ed957684
JS		 2120static struct hbq_dmabuf *
2121lpfc_alloc_hbq_buffers(struct lpfc_hba *phba, int count)
2122{
2123 struct hbq_dmabuf *hbq_buffer_pool;
2124 int i;
2125
2126 hbq_buffer_pool = kmalloc(count * sizeof(struct hbq_dmabuf),
2127 GFP_KERNEL);
2128 if (!hbq_buffer_pool)
2129 goto out;
2130
2131 for (i = 0; i < count; ++i) {
2132 hbq_buffer_pool[i].dbuf.virt =
2133 lpfc_hbq_alloc(phba, MEM_PRI,
2134 &hbq_buffer_pool[i].dbuf.phys);
2135 if (hbq_buffer_pool[i].dbuf.virt == NULL)
2136 goto alloc_failed;
2137 hbq_buffer_pool[i].tag = i;
2138 }
2139 goto out;
2140
2141alloc_failed:
2142 while (--i >= 0)
2143 lpfc_hbq_free(phba, hbq_buffer_pool[i].dbuf.virt,
2144 hbq_buffer_pool[i].dbuf.phys);
2145 kfree(hbq_buffer_pool);
2146 hbq_buffer_pool = NULL;
2147
2148out:
2149 phba->hbq_buffer_pool = hbq_buffer_pool;
2150 return hbq_buffer_pool;
2151}
2152
2153static struct lpfc_hbq_init lpfc_els_hbq = {
2154 .rn = 1,
2155 .entry_count = 1200,
2156 .mask_count = 0,
2157 .profile = 0,
2158 .ring_mask = 1 << LPFC_ELS_RING,
2159};
2160
2161static struct lpfc_hbq_init *lpfc_hbq_definitions[] = {
2162 &lpfc_els_hbq,
2163};
2164
2165static int
2166lpfc_sli_hbq_count(void)
2167{
2168 return ARRAY_SIZE(lpfc_hbq_definitions);
2169}
2170
2171static int
2172lpfc_sli_hbq_entry_count(void)
2173{
2174 int hbq_count = lpfc_sli_hbq_count();
2175 int count = 0;
2176 int i;
2177
2178 for (i = 0; i < hbq_count; ++i)
2179 count += lpfc_hbq_definitions[i]->entry_count;
2180 return count;
2181}
2182
dea3101e 2183int
ed957684
JS		 2184lpfc_sli_hbq_size(void)
2185{
2186 return lpfc_sli_hbq_entry_count() * sizeof(struct lpfc_hbq_entry);
2187}
2188
2189static int
2190lpfc_sli_hbq_setup(struct lpfc_hba *phba)
2191{
2192 int hbq_count = lpfc_sli_hbq_count();
2193 LPFC_MBOXQ_t *pmb;
2194 MAILBOX_t *pmbox;
2195 uint32_t hbqno;
2196 uint32_t hbq_entry_index;
2197 uint32_t hbq_buffer_count;
2198
2199 /* count hbq buffers */
2200 hbq_buffer_count = lpfc_sli_hbq_entry_count();
2201 if (!lpfc_alloc_hbq_buffers(phba, hbq_buffer_count))
2202 return -ENOMEM;
2203
2204 phba->hbq_buffer_count = hbq_buffer_count;
2205
2206 /* Get a Mailbox buffer to setup mailbox
2207 * commands for HBA initialization
2208 */
2209 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
2210
2211 if (!pmb)
2212 return -ENOMEM;
2213
2214 pmbox = &pmb->mb;
2215
2216 /* Initialize the struct lpfc_sli_hbq structure for each hbq */
2217 phba->link_state = LPFC_INIT_MBX_CMDS;
2218
2219 hbq_entry_index = 0;
2220 for (hbqno = 0; hbqno < hbq_count; ++hbqno) {
2221 phba->hbqs[hbqno].next_hbqPutIdx = 0;
2222 phba->hbqs[hbqno].hbqPutIdx = 0;
2223 phba->hbqs[hbqno].local_hbqGetIdx = 0;
2224 phba->hbqs[hbqno].entry_count =
2225 lpfc_hbq_definitions[hbqno]->entry_count;
2226 lpfc_config_hbq(phba, lpfc_hbq_definitions[hbqno],
2227 hbq_entry_index, pmb);
2228 hbq_entry_index += phba->hbqs[hbqno].entry_count;
2229
2230 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
2231 /* Adapter failed to init, mbxCmd <cmd> CFG_RING,
2232 mbxStatus <status>, ring <num> */
2233
2234 lpfc_printf_log(phba, KERN_ERR,
2235 LOG_SLI,
2236 "%d:1805 Adapter failed to init. "
2237 "Data: x%x x%x x%x\n",
2238 phba->brd_no, pmbox->mbxCommand,
2239 pmbox->mbxStatus, hbqno);
2240
2241 phba->link_state = LPFC_HBA_ERROR;
2242 mempool_free(pmb, phba->mbox_mem_pool);
2243 /* Free all HBQ memory */
2244 lpfc_sli_hbqbuf_free_all(phba);
2245 return ENXIO;
2246 }
2247 }
2248 phba->hbq_count = hbq_count;
2249
2250 /* Initially populate or replenish the HBQs */
2251 lpfc_sli_hbqbuf_fill_hbqs(phba);
2252 mempool_free(pmb, phba->mbox_mem_pool);
2253
2254 return 0;
2255}
2256
2257static int
2258lpfc_do_config_port(struct lpfc_hba *phba, int sli_mode)
dea3101e 2259{
2260 LPFC_MBOXQ_t *pmb;
2261 uint32_t resetcount = 0, rc = 0, done = 0;
2262
2263 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
2264 if (!pmb) {
2e0fef85 2265 phba->link_state = LPFC_HBA_ERROR;
dea3101e 2266 return -ENOMEM;
2267 }
2268
ed957684 2269 phba->sli_rev = sli_mode;
dea3101e 2270 while (resetcount < 2 && !done) {
2e0fef85 2271 spin_lock_irq(&phba->hbalock);
1c067a42 2272 phba->sli.sli_flag |= LPFC_SLI_MBOX_ACTIVE;
2e0fef85
JS		 2273 spin_unlock_irq(&phba->hbalock);
2274 phba->pport->port_state = LPFC_STATE_UNKNOWN;
41415862 2275 lpfc_sli_brdrestart(phba);
dea3101e 2276 msleep(2500);
2277 rc = lpfc_sli_chipset_init(phba);
2278 if (rc)
2279 break;
2280
2e0fef85 2281 spin_lock_irq(&phba->hbalock);
1c067a42 2282 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
2e0fef85 2283 spin_unlock_irq(&phba->hbalock);
dea3101e 2284 resetcount++;
2285
ed957684
JS		 2286 /* Call pre CONFIG_PORT mailbox command initialization. A
2287 * value of 0 means the call was successful. Any other
2288 * nonzero value is a failure, but if ERESTART is returned,
2289 * the driver may reset the HBA and try again.
2290 */
dea3101e 2291 rc = lpfc_config_port_prep(phba);
2292 if (rc == -ERESTART) {
ed957684 2293 phba->link_state = LPFC_LINK_UNKNOWN;
dea3101e 2294 continue;
2295 } else if (rc) {
2296 break;
2297 }
2298
2e0fef85 2299 phba->link_state = LPFC_INIT_MBX_CMDS;
dea3101e 2300 lpfc_config_port(phba, pmb);
2301 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
ed957684 2302 if (rc != MBX_SUCCESS) {
dea3101e 2303 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
ed957684
JS		 2304 "%d:0442 Adapter failed to init, "
2305 "mbxCmd x%x CONFIG_PORT, mbxStatus "
2306 "x%x Data: x%x\n",
2307 phba->brd_no, pmb->mb.mbxCommand,
2308 pmb->mb.mbxStatus, 0);
2e0fef85 2309 spin_lock_irq(&phba->hbalock);
dea3101e 2310 phba->sli.sli_flag &= ~LPFC_SLI2_ACTIVE;
2e0fef85
JS		 2311 spin_unlock_irq(&phba->hbalock);
2312 rc = -ENXIO;
ed957684
JS		 2313 } else {
2314 done = 1;
2315 /* DBG: Do we need max_vpi, reg_vpi for that matter
2316 phba->max_vpi = 0;
2317 */
dea3101e 2318 }
2319 }
ed957684
JS		 2320
2321 if (!done) {
2322 rc = -EINVAL;
2323 goto do_prep_failed;
2324 }
2325
2326 if ((pmb->mb.un.varCfgPort.sli_mode == 3) &&
2327 (!pmb->mb.un.varCfgPort.cMA)) {
2328 rc = -ENXIO;
2329 goto do_prep_failed;
2330 }
2331 return rc;
2332
2333 do_prep_failed:
2334 mempool_free(pmb, phba->mbox_mem_pool);
2335 return rc;
2336}
2337
2338int
2339lpfc_sli_hba_setup(struct lpfc_hba *phba)
2340{
2341 uint32_t rc;
2342 int mode = 3;
2343
2344 switch (lpfc_sli_mode) {
2345 case 2:
2346 mode = 2;
2347 break;
2348 case 0:
2349 case 3:
2350 break;
2351 default:
2352 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
2353 "%d:1819 Unrecognized lpfc_sli_mode "
2354 "parameter: %d.\n",
2355 phba->brd_no, lpfc_sli_mode);
2356
2357 break;
2358 }
2359
2360 rc = lpfc_do_config_port(phba, mode);
2361 if (rc && lpfc_sli_mode == 3)
2362 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
2363 "%d:1820 Unable to select SLI-3. "
2364 "Not supported by adapter.\n",
2365 phba->brd_no);
2366 if (rc && mode != 2)
2367 rc = lpfc_do_config_port(phba, 2);
2368 if (rc)
dea3101e 2369 goto lpfc_sli_hba_setup_error;
2370
ed957684
JS		 2371 if (phba->sli_rev == 3) {
2372 phba->iocb_cmd_size = SLI3_IOCB_CMD_SIZE;
2373 phba->iocb_rsp_size = SLI3_IOCB_RSP_SIZE;
2374 phba->sli3_options |= LPFC_SLI3_ENABLED;
2375 phba->sli3_options |= LPFC_SLI3_HBQ_ENABLED;
2376
2377 } else {
2378 phba->iocb_cmd_size = SLI2_IOCB_CMD_SIZE;
2379 phba->iocb_rsp_size = SLI2_IOCB_RSP_SIZE;
2380 phba->sli3_options = 0x0;
2381 }
2382
2383 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
2384 "%d:0444 Firmware in SLI %x mode.\n",
2385 phba->brd_no, phba->sli_rev);
2386 rc = lpfc_sli_ring_map(phba);
dea3101e 2387
2388 if (rc)
2389 goto lpfc_sli_hba_setup_error;
2390
ed957684
JS		 2391 /* Init HBQs */
2392
2393 if (phba->sli3_options & LPFC_SLI3_HBQ_ENABLED) {
2394 rc = lpfc_sli_hbq_setup(phba);
2395 if (rc)
2396 goto lpfc_sli_hba_setup_error;
2397 }
2398
dea3101e 2399 phba->sli.sli_flag |= LPFC_PROCESS_LA;
2400
2401 rc = lpfc_config_port_post(phba);
2402 if (rc)
2403 goto lpfc_sli_hba_setup_error;
2404
ed957684
JS		 2405 return rc;
2406
2407 lpfc_sli_hba_setup_error:
2e0fef85 2408 phba->link_state = LPFC_HBA_ERROR;
ed957684
JS		 2409 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
2410 "%d:0445 Firmware initialization failed\n",
2411 phba->brd_no);
dea3101e 2412 return rc;
2413}
2414
dea3101e 2415/*! lpfc_mbox_timeout
2416 *
2417 * \pre
2418 * \post
2419 * \param hba Pointer to per struct lpfc_hba structure
2420 * \param l1 Pointer to the driver's mailbox queue.
2421 * \return
2422 * void
2423 *
2424 * \b Description:
2425 *
2426 * This routine handles mailbox timeout events at timer interrupt context.
2427 */
2428void
2429lpfc_mbox_timeout(unsigned long ptr)
2430{
2e0fef85 2431 struct lpfc_hba *phba = (struct lpfc_hba *) phba;
dea3101e 2432 unsigned long iflag;
2e0fef85 2433 uint32_t tmo_posted;
dea3101e 2434
2e0fef85 2435 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
ed957684 2436 tmo_posted = (phba->pport->work_port_events & WORKER_MBOX_TMO);
2e0fef85
JS		 2437 if (!tmo_posted)
2438 phba->pport->work_port_events |= WORKER_MBOX_TMO;
2439 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
2440
2441 if (!tmo_posted) {
dea3101e 2442 if (phba->work_wait)
2443 wake_up(phba->work_wait);
2444 }
dea3101e 2445}
2446
2447void
2448lpfc_mbox_timeout_handler(struct lpfc_hba *phba)
2449{
2e0fef85
JS		 2450 LPFC_MBOXQ_t *pmbox = phba->sli.mbox_active;
2451 MAILBOX_t *mb = &pmbox->mb;
1dcb58e5
JS		 2452 struct lpfc_sli *psli = &phba->sli;
2453 struct lpfc_sli_ring *pring;
dea3101e 2454
2e0fef85 2455 if (!(phba->pport->work_port_events & WORKER_MBOX_TMO)) {
dea3101e 2456 return;
2457 }
2458
dea3101e 2459 /* Mbox cmd <mbxCommand> timeout */
ed957684 2460 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX | LOG_SLI,
dea3101e 2461 "%d:0310 Mailbox command x%x timeout Data: x%x x%x x%p\n",
2462 phba->brd_no,
2463 mb->mbxCommand,
2e0fef85 2464 phba->pport->port_state,
dea3101e 2465 phba->sli.sli_flag,
2466 phba->sli.mbox_active);
2467
1dcb58e5
JS		 2468 /* Setting state unknown so lpfc_sli_abort_iocb_ring
2469 * would get IOCB_ERROR from lpfc_sli_issue_iocb, allowing
2470 * it to fail all oustanding SCSI IO.
2471 */
2e0fef85
JS		 2472 spin_lock_irq(&phba->pport->work_port_lock);
2473 phba->pport->work_port_events &= ~WORKER_MBOX_TMO;
2474 spin_unlock_irq(&phba->pport->work_port_lock);
2475 spin_lock_irq(&phba->hbalock);
2476 phba->link_state = LPFC_LINK_UNKNOWN;
2477 phba->pport->fc_flag |= FC_ESTABLISH_LINK;
1dcb58e5 2478 psli->sli_flag &= ~LPFC_SLI2_ACTIVE;
2e0fef85 2479 spin_unlock_irq(&phba->hbalock);
1dcb58e5
JS		 2480
2481 pring = &psli->ring[psli->fcp_ring];
2482 lpfc_sli_abort_iocb_ring(phba, pring);
2483
2484 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX | LOG_SLI,
2485 "%d:0316 Resetting board due to mailbox timeout\n",
2486 phba->brd_no);
2487 /*
2488 * lpfc_offline calls lpfc_sli_hba_down which will clean up
2489 * on oustanding mailbox commands.
2490 */
2491 lpfc_offline_prep(phba);
2492 lpfc_offline(phba);
2493 lpfc_sli_brdrestart(phba);
2494 if (lpfc_online(phba) == 0) /* Initialize the HBA */
2495 mod_timer(&phba->fc_estabtmo, jiffies + HZ * 60);
2496 lpfc_unblock_mgmt_io(phba);
dea3101e 2497 return;
2498}
2499
2500int
2e0fef85 2501lpfc_sli_issue_mbox(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmbox, uint32_t flag)
dea3101e 2502{
dea3101e 2503 MAILBOX_t *mb;
2e0fef85 2504 struct lpfc_sli *psli = &phba->sli;
dea3101e 2505 uint32_t status, evtctr;
2506 uint32_t ha_copy;
2507 int i;
2508 unsigned long drvr_flag = 0;
2509 volatile uint32_t word0, ldata;
2510 void __iomem *to_slim;
2511
ed957684
JS		 2512 if (pmbox->mbox_cmpl && pmbox->mbox_cmpl != lpfc_sli_def_mbox_cmpl &&
2513 pmbox->mbox_cmpl != lpfc_sli_wake_mbox_wait) {
2514 if(!pmbox->vport) {
2515 lpfc_printf_log(phba, KERN_ERR,
2516 LOG_MBOX,
2517 "%d:1806 Mbox x%x failed. No vport\n",
2518 phba->brd_no,
2519 pmbox->mb.mbxCommand);
2520 dump_stack();
2521 return MBXERR_ERROR;
2522 }
2523 }
2524
8d63f375
LV		 2525 /* If the PCI channel is in offline state, do not post mbox. */
2526 if (unlikely(pci_channel_offline(phba->pcidev)))
2527 return MBX_NOT_FINISHED;
2528
2e0fef85 2529 spin_lock_irqsave(&phba->hbalock, drvr_flag);
dea3101e 2530 psli = &phba->sli;
dea3101e 2531 mb = &pmbox->mb;
2532 status = MBX_SUCCESS;
2533
2e0fef85
JS		 2534 if (phba->link_state == LPFC_HBA_ERROR) {
2535 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
41415862
JW		 2536
2537 /* Mbox command <mbxCommand> cannot issue */
2538 LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag)
2e0fef85 2539 return MBX_NOT_FINISHED;
41415862
JW		 2540 }
2541
9290831f
JS		 2542 if (mb->mbxCommand != MBX_KILL_BOARD && flag & MBX_NOWAIT &&
2543 !(readl(phba->HCregaddr) & HC_MBINT_ENA)) {
2e0fef85 2544 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
9290831f 2545 LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag)
2e0fef85 2546 return MBX_NOT_FINISHED;
9290831f
JS		 2547 }
2548
dea3101e 2549 if (psli->sli_flag & LPFC_SLI_MBOX_ACTIVE) {
2550 /* Polling for a mbox command when another one is already active
2551 * is not allowed in SLI. Also, the driver must have established
2552 * SLI2 mode to queue and process multiple mbox commands.
2553 */
2554
2555 if (flag & MBX_POLL) {
2e0fef85 2556 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
dea3101e 2557
2558 /* Mbox command <mbxCommand> cannot issue */
2e0fef85
JS		 2559 LOG_MBOX_CANNOT_ISSUE_DATA(phba, mb, psli, flag);
2560 return MBX_NOT_FINISHED;
dea3101e 2561 }
2562
2563 if (!(psli->sli_flag & LPFC_SLI2_ACTIVE)) {
2e0fef85 2564 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
dea3101e 2565 /* Mbox command <mbxCommand> cannot issue */
2e0fef85
JS		 2566 LOG_MBOX_CANNOT_ISSUE_DATA(phba, mb, psli, flag);
2567 return MBX_NOT_FINISHED;
dea3101e 2568 }
2569
2570 /* Handle STOP IOCB processing flag. This is only meaningful
2571 * if we are not polling for mbox completion.
2572 */
2573 if (flag & MBX_STOP_IOCB) {
2574 flag &= ~MBX_STOP_IOCB;
2575 /* Now flag each ring */
2576 for (i = 0; i < psli->num_rings; i++) {
2577 /* If the ring is active, flag it */
2578 if (psli->ring[i].cmdringaddr) {
2579 psli->ring[i].flag |=
2580 LPFC_STOP_IOCB_MBX;
2581 }
2582 }
2583 }
2584
2585 /* Another mailbox command is still being processed, queue this
2586 * command to be processed later.
2587 */
2588 lpfc_mbox_put(phba, pmbox);
2589
2590 /* Mbox cmd issue - BUSY */
ed957684 2591 lpfc_printf_log(phba, KERN_INFO, LOG_MBOX | LOG_SLI,
dea3101e 2592 "%d:0308 Mbox cmd issue - BUSY Data: x%x x%x x%x x%x\n",
2593 phba->brd_no,
ed957684
JS		 2594 mb->mbxCommand, phba->pport->port_state,
2595 psli->sli_flag, flag);
dea3101e 2596
2597 psli->slistat.mbox_busy++;
2e0fef85 2598 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
dea3101e 2599
2e0fef85 2600 return MBX_BUSY;
dea3101e 2601 }
2602
2603 /* Handle STOP IOCB processing flag. This is only meaningful
2604 * if we are not polling for mbox completion.
2605 */
2606 if (flag & MBX_STOP_IOCB) {
2607 flag &= ~MBX_STOP_IOCB;
2608 if (flag == MBX_NOWAIT) {
2609 /* Now flag each ring */
2610 for (i = 0; i < psli->num_rings; i++) {
2611 /* If the ring is active, flag it */
2612 if (psli->ring[i].cmdringaddr) {
2613 psli->ring[i].flag |=
2614 LPFC_STOP_IOCB_MBX;
2615 }
2616 }
2617 }
2618 }
2619
2620 psli->sli_flag |= LPFC_SLI_MBOX_ACTIVE;
2621
2622 /* If we are not polling, we MUST be in SLI2 mode */
2623 if (flag != MBX_POLL) {
41415862
JW		 2624 if (!(psli->sli_flag & LPFC_SLI2_ACTIVE) &&
2625 (mb->mbxCommand != MBX_KILL_BOARD)) {
dea3101e 2626 psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
2e0fef85 2627 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
dea3101e 2628 /* Mbox command <mbxCommand> cannot issue */
2629 LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag);
2e0fef85 2630 return MBX_NOT_FINISHED;
dea3101e 2631 }
2632 /* timeout active mbox command */
a309a6b6
JS		 2633 mod_timer(&psli->mbox_tmo, (jiffies +
2634 (HZ * lpfc_mbox_tmo_val(phba, mb->mbxCommand))));
dea3101e 2635 }
2636
2637 /* Mailbox cmd <cmd> issue */
ed957684 2638 lpfc_printf_log(phba, KERN_INFO, LOG_MBOX | LOG_SLI,
dea3101e 2639 "%d:0309 Mailbox cmd x%x issue Data: x%x x%x x%x\n",
2640 phba->brd_no,
ed957684
JS		 2641 mb->mbxCommand, phba->pport->port_state,
2642 psli->sli_flag, flag);
dea3101e 2643
2644 psli->slistat.mbox_cmd++;
2645 evtctr = psli->slistat.mbox_event;
2646
2647 /* next set own bit for the adapter and copy over command word */
2648 mb->mbxOwner = OWN_CHIP;
2649
2650 if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
dea3101e 2651 /* First copy command data to host SLIM area */
4cc2da1d 2652 lpfc_sli_pcimem_bcopy(mb, &phba->slim2p->mbx, MAILBOX_CMD_SIZE);
dea3101e 2653 } else {
9290831f 2654 if (mb->mbxCommand == MBX_CONFIG_PORT) {
dea3101e 2655 /* copy command data into host mbox for cmpl */
4cc2da1d
JSEC		 2656 lpfc_sli_pcimem_bcopy(mb, &phba->slim2p->mbx,
2657 MAILBOX_CMD_SIZE);
dea3101e 2658 }
2659
2660 /* First copy mbox command data to HBA SLIM, skip past first
2661 word */
2662 to_slim = phba->MBslimaddr + sizeof (uint32_t);
2663 lpfc_memcpy_to_slim(to_slim, &mb->un.varWords[0],
2664 MAILBOX_CMD_SIZE - sizeof (uint32_t));
2665
2666 /* Next copy over first word, with mbxOwner set */
2667 ldata = *((volatile uint32_t *)mb);
2668 to_slim = phba->MBslimaddr;
2669 writel(ldata, to_slim);
2670 readl(to_slim); /* flush */
2671
2672 if (mb->mbxCommand == MBX_CONFIG_PORT) {
2673 /* switch over to host mailbox */
2674 psli->sli_flag |= LPFC_SLI2_ACTIVE;
2675 }
2676 }
2677
2678 wmb();
2679 /* interrupt board to doit right away */
2680 writel(CA_MBATT, phba->CAregaddr);
2681 readl(phba->CAregaddr); /* flush */
2682
2683 switch (flag) {
2684 case MBX_NOWAIT:
2685 /* Don't wait for it to finish, just return */
2686 psli->mbox_active = pmbox;
2687 break;
2688
2689 case MBX_POLL:
dea3101e 2690 psli->mbox_active = NULL;
2691 if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
2692 /* First read mbox status word */
4cc2da1d 2693 word0 = *((volatile uint32_t *)&phba->slim2p->mbx);
dea3101e 2694 word0 = le32_to_cpu(word0);
2695 } else {
2696 /* First read mbox status word */
2697 word0 = readl(phba->MBslimaddr);
2698 }
2699
2700 /* Read the HBA Host Attention Register */
2701 ha_copy = readl(phba->HAregaddr);
2702
a309a6b6
JS		 2703 i = lpfc_mbox_tmo_val(phba, mb->mbxCommand);
2704 i *= 1000; /* Convert to ms */
2705
dea3101e 2706 /* Wait for command to complete */
41415862
JW		 2707 while (((word0 & OWN_CHIP) == OWN_CHIP) ||
2708 (!(ha_copy & HA_MBATT) &&
2e0fef85 2709 (phba->link_state > LPFC_WARM_START))) {
a309a6b6 2710 if (i-- <= 0) {
dea3101e 2711 psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
2e0fef85 2712 spin_unlock_irqrestore(&phba->hbalock,
dea3101e 2713 drvr_flag);
2e0fef85 2714 return MBX_NOT_FINISHED;
dea3101e 2715 }
2716
2717 /* Check if we took a mbox interrupt while we were
2718 polling */
2719 if (((word0 & OWN_CHIP) != OWN_CHIP)
2720 && (evtctr != psli->slistat.mbox_event))
2721 break;
2722
2e0fef85 2723 spin_unlock_irqrestore(&phba->hbalock,
dea3101e 2724 drvr_flag);
2725
1dcb58e5 2726 msleep(1);
dea3101e 2727
2e0fef85 2728 spin_lock_irqsave(&phba->hbalock, drvr_flag);
dea3101e 2729
2730 if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
2731 /* First copy command data */
4cc2da1d
JSEC		 2732 word0 = *((volatile uint32_t *)
2733 &phba->slim2p->mbx);
dea3101e 2734 word0 = le32_to_cpu(word0);
2735 if (mb->mbxCommand == MBX_CONFIG_PORT) {
2736 MAILBOX_t *slimmb;
2737 volatile uint32_t slimword0;
2738 /* Check real SLIM for any errors */
2739 slimword0 = readl(phba->MBslimaddr);
2740 slimmb = (MAILBOX_t *) & slimword0;
2741 if (((slimword0 & OWN_CHIP) != OWN_CHIP)
2742 && slimmb->mbxStatus) {
2743 psli->sli_flag &=
2744 ~LPFC_SLI2_ACTIVE;
2745 word0 = slimword0;
2746 }
2747 }
2748 } else {
2749 /* First copy command data */
2750 word0 = readl(phba->MBslimaddr);
2751 }
2752 /* Read the HBA Host Attention Register */
2753 ha_copy = readl(phba->HAregaddr);
2754 }
2755
2756 if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
dea3101e 2757 /* copy results back to user */
4cc2da1d
JSEC		 2758 lpfc_sli_pcimem_bcopy(&phba->slim2p->mbx, mb,
2759 MAILBOX_CMD_SIZE);
dea3101e 2760 } else {
2761 /* First copy command data */
2762 lpfc_memcpy_from_slim(mb, phba->MBslimaddr,
2763 MAILBOX_CMD_SIZE);
2764 if ((mb->mbxCommand == MBX_DUMP_MEMORY) &&
2765 pmbox->context2) {
2e0fef85 2766 lpfc_memcpy_from_slim((void *) pmbox->context2,
dea3101e 2767 phba->MBslimaddr + DMP_RSP_OFFSET,
2768 mb->un.varDmp.word_cnt);
2769 }
2770 }
2771
2772 writel(HA_MBATT, phba->HAregaddr);
2773 readl(phba->HAregaddr); /* flush */
2774
2775 psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
2776 status = mb->mbxStatus;
2777 }
2778
2e0fef85
JS		 2779 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
2780 return status;
dea3101e 2781}
2782
2783static int
2e0fef85
JS		 2784lpfc_sli_ringtx_put(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
2785 struct lpfc_iocbq *piocb)
dea3101e 2786{
2e0fef85
JS		 2787 unsigned long iflags;
2788
dea3101e 2789 /* Insert the caller's iocb in the txq tail for later processing. */
2e0fef85 2790 spin_lock_irqsave(&phba->hbalock, iflags);
dea3101e 2791 list_add_tail(&piocb->list, &pring->txq);
2792 pring->txq_cnt++;
2e0fef85
JS		 2793 spin_unlock_irqrestore(&phba->hbalock, iflags);
2794 return 0;
dea3101e 2795}
2796
2797static struct lpfc_iocbq *
2798lpfc_sli_next_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
2e0fef85 2799 struct lpfc_iocbq **piocb)
dea3101e 2800{
2801 struct lpfc_iocbq * nextiocb;
2802
2803 nextiocb = lpfc_sli_ringtx_get(phba, pring);
2804 if (!nextiocb) {
2805 nextiocb = *piocb;
2806 *piocb = NULL;
2807 }
2808
2809 return nextiocb;
2810}
2811
2812int
2813lpfc_sli_issue_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
2814 struct lpfc_iocbq *piocb, uint32_t flag)
2815{
2816 struct lpfc_iocbq *nextiocb;
2e0fef85 2817 unsigned long iflags;
dea3101e 2818 IOCB_t *iocb;
2819
8d63f375
LV		 2820 /* If the PCI channel is in offline state, do not post iocbs. */
2821 if (unlikely(pci_channel_offline(phba->pcidev)))
2822 return IOCB_ERROR;
2823
dea3101e 2824 /*
2825 * We should never get an IOCB if we are in a < LINK_DOWN state
2826 */
2e0fef85 2827 if (unlikely(phba->link_state < LPFC_LINK_DOWN))
dea3101e 2828 return IOCB_ERROR;
2829
2830 /*
2831 * Check to see if we are blocking IOCB processing because of a
2832 * outstanding mbox command.
2833 */
2834 if (unlikely(pring->flag & LPFC_STOP_IOCB_MBX))
2835 goto iocb_busy;
2836
2e0fef85 2837 if (unlikely(phba->link_state == LPFC_LINK_DOWN)) {
dea3101e 2838 /*
2680eeaa 2839 * Only CREATE_XRI, CLOSE_XRI, and QUE_RING_BUF
dea3101e 2840 * can be issued if the link is not up.
2841 */
2842 switch (piocb->iocb.ulpCommand) {
2843 case CMD_QUE_RING_BUF_CN:
2844 case CMD_QUE_RING_BUF64_CN:
dea3101e 2845 /*
2846 * For IOCBs, like QUE_RING_BUF, that have no rsp ring
2847 * completion, iocb_cmpl MUST be 0.
2848 */
2849 if (piocb->iocb_cmpl)
2850 piocb->iocb_cmpl = NULL;
2851 /*FALLTHROUGH*/
2852 case CMD_CREATE_XRI_CR:
2680eeaa
JS		 2853 case CMD_CLOSE_XRI_CN:
2854 case CMD_CLOSE_XRI_CX:
dea3101e 2855 break;
2856 default:
2857 goto iocb_busy;
2858 }
2859
2860 /*
2861 * For FCP commands, we must be in a state where we can process link
2862 * attention events.
2863 */
2864 } else if (unlikely(pring->ringno == phba->sli.fcp_ring &&
2865 !(phba->sli.sli_flag & LPFC_PROCESS_LA)))
2866 goto iocb_busy;
2867
2e0fef85 2868 spin_lock_irqsave(&phba->hbalock, iflags);
dea3101e 2869 while ((iocb = lpfc_sli_next_iocb_slot(phba, pring)) &&
2870 (nextiocb = lpfc_sli_next_iocb(phba, pring, &piocb)))
2871 lpfc_sli_submit_iocb(phba, pring, iocb, nextiocb);
2872
2873 if (iocb)
2874 lpfc_sli_update_ring(phba, pring);
2875 else
2876 lpfc_sli_update_full_ring(phba, pring);
2e0fef85 2877 spin_unlock_irqrestore(&phba->hbalock, iflags);
dea3101e 2878
2879 if (!piocb)
2880 return IOCB_SUCCESS;
2881
2882 goto out_busy;
2883
2884 iocb_busy:
2e0fef85 2885 spin_lock_irqsave(&phba->hbalock, iflags);
dea3101e 2886 pring->stats.iocb_cmd_delay++;
2e0fef85 2887 spin_unlock_irqrestore(&phba->hbalock, iflags);
dea3101e 2888
2889 out_busy:
2890
2891 if (!(flag & SLI_IOCB_RET_IOCB)) {
2892 lpfc_sli_ringtx_put(phba, pring, piocb);
2893 return IOCB_SUCCESS;
2894 }
2895
2896 return IOCB_BUSY;
2897}
2898
cf5bf97e
JW		 2899static int
2900lpfc_extra_ring_setup( struct lpfc_hba *phba)
2901{
2902 struct lpfc_sli *psli;
2903 struct lpfc_sli_ring *pring;
2904
2905 psli = &phba->sli;
2906
2907 /* Adjust cmd/rsp ring iocb entries more evenly */
a4bc3379
JS		 2908
2909 /* Take some away from the FCP ring */
cf5bf97e
JW		 2910 pring = &psli->ring[psli->fcp_ring];
2911 pring->numCiocb -= SLI2_IOCB_CMD_R1XTRA_ENTRIES;
2912 pring->numRiocb -= SLI2_IOCB_RSP_R1XTRA_ENTRIES;
2913 pring->numCiocb -= SLI2_IOCB_CMD_R3XTRA_ENTRIES;
2914 pring->numRiocb -= SLI2_IOCB_RSP_R3XTRA_ENTRIES;
2915
a4bc3379
JS		 2916 /* and give them to the extra ring */
2917 pring = &psli->ring[psli->extra_ring];
2918
cf5bf97e
JW		 2919 pring->numCiocb += SLI2_IOCB_CMD_R1XTRA_ENTRIES;
2920 pring->numRiocb += SLI2_IOCB_RSP_R1XTRA_ENTRIES;
2921 pring->numCiocb += SLI2_IOCB_CMD_R3XTRA_ENTRIES;
2922 pring->numRiocb += SLI2_IOCB_RSP_R3XTRA_ENTRIES;
2923
2924 /* Setup default profile for this ring */
2925 pring->iotag_max = 4096;
2926 pring->num_mask = 1;
2927 pring->prt[0].profile = 0; /* Mask 0 */
a4bc3379
JS		 2928 pring->prt[0].rctl = phba->cfg_multi_ring_rctl;
2929 pring->prt[0].type = phba->cfg_multi_ring_type;
cf5bf97e
JW		 2930 pring->prt[0].lpfc_sli_rcv_unsol_event = NULL;
2931 return 0;
2932}
2933
dea3101e 2934int
2935lpfc_sli_setup(struct lpfc_hba *phba)
2936{
ed957684 2937 int i, totiocbsize = 0;
dea3101e 2938 struct lpfc_sli *psli = &phba->sli;
2939 struct lpfc_sli_ring *pring;
2940
2941 psli->num_rings = MAX_CONFIGURED_RINGS;
2942 psli->sli_flag = 0;
2943 psli->fcp_ring = LPFC_FCP_RING;
2944 psli->next_ring = LPFC_FCP_NEXT_RING;
a4bc3379 2945 psli->extra_ring = LPFC_EXTRA_RING;
dea3101e 2946
604a3e30
JB		 2947 psli->iocbq_lookup = NULL;
2948 psli->iocbq_lookup_len = 0;
2949 psli->last_iotag = 0;
2950
dea3101e 2951 for (i = 0; i < psli->num_rings; i++) {
2952 pring = &psli->ring[i];
2953 switch (i) {
2954 case LPFC_FCP_RING: /* ring 0 - FCP */
2955 /* numCiocb and numRiocb are used in config_port */
2956 pring->numCiocb = SLI2_IOCB_CMD_R0_ENTRIES;
2957 pring->numRiocb = SLI2_IOCB_RSP_R0_ENTRIES;
2958 pring->numCiocb += SLI2_IOCB_CMD_R1XTRA_ENTRIES;
2959 pring->numRiocb += SLI2_IOCB_RSP_R1XTRA_ENTRIES;
2960 pring->numCiocb += SLI2_IOCB_CMD_R3XTRA_ENTRIES;
2961 pring->numRiocb += SLI2_IOCB_RSP_R3XTRA_ENTRIES;
ed957684
JS		 2962 pring->sizeCiocb = (phba->sli_rev == 3) ?
2963 SLI3_IOCB_CMD_SIZE :
2964 SLI2_IOCB_CMD_SIZE;
2965 pring->sizeRiocb = (phba->sli_rev == 3) ?
2966 SLI3_IOCB_RSP_SIZE :
2967 SLI2_IOCB_RSP_SIZE;
dea3101e 2968 pring->iotag_ctr = 0;
2969 pring->iotag_max =
ed957684 2970 (phba->cfg_hba_queue_depth * 2);
dea3101e 2971 pring->fast_iotag = pring->iotag_max;
2972 pring->num_mask = 0;
2973 break;
a4bc3379 2974 case LPFC_EXTRA_RING: /* ring 1 - EXTRA */
dea3101e 2975 /* numCiocb and numRiocb are used in config_port */
2976 pring->numCiocb = SLI2_IOCB_CMD_R1_ENTRIES;
2977 pring->numRiocb = SLI2_IOCB_RSP_R1_ENTRIES;
ed957684
JS		 2978 pring->sizeCiocb = (phba->sli_rev == 3) ?
2979 SLI3_IOCB_CMD_SIZE :
2980 SLI2_IOCB_CMD_SIZE;
2981 pring->sizeRiocb = (phba->sli_rev == 3) ?
2982 SLI3_IOCB_RSP_SIZE :
2983 SLI2_IOCB_RSP_SIZE;
2e0fef85 2984 pring->iotag_max = phba->cfg_hba_queue_depth;
dea3101e 2985 pring->num_mask = 0;
2986 break;
2987 case LPFC_ELS_RING: /* ring 2 - ELS / CT */
2988 /* numCiocb and numRiocb are used in config_port */
2989 pring->numCiocb = SLI2_IOCB_CMD_R2_ENTRIES;
2990 pring->numRiocb = SLI2_IOCB_RSP_R2_ENTRIES;
ed957684
JS		 2991 pring->sizeCiocb = (phba->sli_rev == 3) ?
2992 SLI3_IOCB_CMD_SIZE :
2993 SLI2_IOCB_CMD_SIZE;
2994 pring->sizeRiocb = (phba->sli_rev == 3) ?
2995 SLI3_IOCB_RSP_SIZE :
2996 SLI2_IOCB_RSP_SIZE;
dea3101e 2997 pring->fast_iotag = 0;
2998 pring->iotag_ctr = 0;
2999 pring->iotag_max = 4096;
3000 pring->num_mask = 4;
3001 pring->prt[0].profile = 0; /* Mask 0 */
3002 pring->prt[0].rctl = FC_ELS_REQ;
3003 pring->prt[0].type = FC_ELS_DATA;
3004 pring->prt[0].lpfc_sli_rcv_unsol_event =
ed957684 3005 lpfc_els_unsol_event;
dea3101e 3006 pring->prt[1].profile = 0; /* Mask 1 */
3007 pring->prt[1].rctl = FC_ELS_RSP;
3008 pring->prt[1].type = FC_ELS_DATA;
3009 pring->prt[1].lpfc_sli_rcv_unsol_event =
ed957684 3010 lpfc_els_unsol_event;
dea3101e 3011 pring->prt[2].profile = 0; /* Mask 2 */
3012 /* NameServer Inquiry */
3013 pring->prt[2].rctl = FC_UNSOL_CTL;
3014 /* NameServer */
3015 pring->prt[2].type = FC_COMMON_TRANSPORT_ULP;
3016 pring->prt[2].lpfc_sli_rcv_unsol_event =
ed957684 3017 lpfc_ct_unsol_event;
dea3101e 3018 pring->prt[3].profile = 0; /* Mask 3 */
3019 /* NameServer response */
3020 pring->prt[3].rctl = FC_SOL_CTL;
3021 /* NameServer */
3022 pring->prt[3].type = FC_COMMON_TRANSPORT_ULP;
3023 pring->prt[3].lpfc_sli_rcv_unsol_event =
ed957684 3024 lpfc_ct_unsol_event;
dea3101e 3025 break;
3026 }
ed957684
JS		 3027 totiocbsize += (pring->numCiocb * pring->sizeCiocb) +
3028 (pring->numRiocb * pring->sizeRiocb);
dea3101e 3029 }
ed957684 3030 if (totiocbsize > MAX_SLIM_IOCB_SIZE) {
dea3101e 3031 /* Too many cmd / rsp ring entries in SLI2 SLIM */
3032 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
3033 "%d:0462 Too many cmd / rsp ring entries in "
ed957684
JS		 3034 "SLI2 SLIM Data: x%x x%lx\n",
3035 phba->brd_no, totiocbsize,
3036 (unsigned long) MAX_SLIM_IOCB_SIZE);
dea3101e 3037 }
cf5bf97e
JW		 3038 if (phba->cfg_multi_ring_support == 2)
3039 lpfc_extra_ring_setup(phba);
dea3101e 3040
3041 return 0;
3042}
3043
3044int
2e0fef85 3045lpfc_sli_queue_setup(struct lpfc_hba *phba)
dea3101e 3046{
3047 struct lpfc_sli *psli;
3048 struct lpfc_sli_ring *pring;
604a3e30 3049 int i;
dea3101e 3050
3051 psli = &phba->sli;
2e0fef85 3052 spin_lock_irq(&phba->hbalock);
dea3101e 3053 INIT_LIST_HEAD(&psli->mboxq);
3054 /* Initialize list headers for txq and txcmplq as double linked lists */
3055 for (i = 0; i < psli->num_rings; i++) {
3056 pring = &psli->ring[i];
3057 pring->ringno = i;
3058 pring->next_cmdidx = 0;
3059 pring->local_getidx = 0;
3060 pring->cmdidx = 0;
3061 INIT_LIST_HEAD(&pring->txq);
3062 INIT_LIST_HEAD(&pring->txcmplq);
3063 INIT_LIST_HEAD(&pring->iocb_continueq);
3064 INIT_LIST_HEAD(&pring->postbufq);
dea3101e 3065 }
2e0fef85
JS		 3066 spin_unlock_irq(&phba->hbalock);
3067 return 1;
dea3101e 3068}
3069
3070int
2e0fef85 3071lpfc_sli_hba_down(struct lpfc_hba *phba)
dea3101e 3072{
2534ba75 3073 LIST_HEAD(completions);
2e0fef85 3074 struct lpfc_sli *psli = &phba->sli;
dea3101e 3075 struct lpfc_sli_ring *pring;
3076 LPFC_MBOXQ_t *pmb;
2534ba75
JS		 3077 struct lpfc_iocbq *iocb;
3078 IOCB_t *cmd = NULL;
dea3101e 3079 int i;
3080 unsigned long flags = 0;
3081
dea3101e 3082 lpfc_hba_down_prep(phba);
3083
2e0fef85 3084 spin_lock_irqsave(&phba->hbalock, flags);
dea3101e 3085 for (i = 0; i < psli->num_rings; i++) {
3086 pring = &psli->ring[i];
3087 pring->flag |= LPFC_DEFERRED_RING_EVENT;
3088
3089 /*
3090 * Error everything on the txq since these iocbs have not been
3091 * given to the FW yet.
3092 */
2534ba75 3093 list_splice_init(&pring->txq, &completions);
dea3101e 3094 pring->txq_cnt = 0;
3095
2534ba75 3096 }
2e0fef85 3097 spin_unlock_irqrestore(&phba->hbalock, flags);
dea3101e 3098
2534ba75
JS		 3099 while (!list_empty(&completions)) {
3100 iocb = list_get_first(&completions, struct lpfc_iocbq, list);
3101 cmd = &iocb->iocb;
3102 list_del(&iocb->list);
dea3101e 3103
2e0fef85
JS		 3104 if (!iocb->iocb_cmpl)
3105 lpfc_sli_release_iocbq(phba, iocb);
3106 else {
2534ba75
JS		 3107 cmd->ulpStatus = IOSTAT_LOCAL_REJECT;
3108 cmd->un.ulpWord[4] = IOERR_SLI_DOWN;
3109 (iocb->iocb_cmpl) (phba, iocb, iocb);
2e0fef85 3110 }
dea3101e 3111 }
3112
dea3101e 3113 /* Return any active mbox cmds */
3114 del_timer_sync(&psli->mbox_tmo);
2e0fef85
JS		 3115
3116 spin_lock_irqsave(&phba->pport->work_port_lock, flags);
3117 phba->pport->work_port_events &= ~WORKER_MBOX_TMO;
3118 spin_unlock_irqrestore(&phba->pport->work_port_lock, flags);
3119
ed957684 3120 spin_lock_irqsave(&phba->hbalock, flags);
2e0fef85
JS		 3121 pmb = psli->mbox_active;
3122 if (pmb) {
3123 psli->mbox_active = NULL;
dea3101e 3124 pmb->mb.mbxStatus = MBX_NOT_FINISHED;
2e0fef85 3125 psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
dea3101e 3126 if (pmb->mbox_cmpl) {
dea3101e 3127 pmb->mbox_cmpl(phba,pmb);
dea3101e 3128 }
3129 }
dea3101e 3130
3131 /* Return any pending mbox cmds */
3132 while ((pmb = lpfc_mbox_get(phba)) != NULL) {
3133 pmb->mb.mbxStatus = MBX_NOT_FINISHED;
3134 if (pmb->mbox_cmpl) {
dea3101e 3135 pmb->mbox_cmpl(phba,pmb);
dea3101e 3136 }
3137 }
dea3101e 3138 INIT_LIST_HEAD(&psli->mboxq);
3139
ed957684
JS		 3140 /* Free all HBQ memory */
3141 lpfc_sli_hbqbuf_free_all(phba);
3142
dea3101e 3143 return 1;
3144}
3145
3146void
3147lpfc_sli_pcimem_bcopy(void *srcp, void *destp, uint32_t cnt)
3148{
3149 uint32_t *src = srcp;
3150 uint32_t *dest = destp;
3151 uint32_t ldata;
3152 int i;
3153
3154 for (i = 0; i < (int)cnt; i += sizeof (uint32_t)) {
3155 ldata = *src;
3156 ldata = le32_to_cpu(ldata);
3157 *dest = ldata;
3158 src++;
3159 dest++;
3160 }
3161}
3162
3163int
2e0fef85
JS		 3164lpfc_sli_ringpostbuf_put(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
3165 struct lpfc_dmabuf *mp)
dea3101e 3166{
3167 /* Stick struct lpfc_dmabuf at end of postbufq so driver can look it up
3168 later */
2e0fef85 3169 spin_lock_irq(&phba->hbalock);
dea3101e 3170 list_add_tail(&mp->list, &pring->postbufq);
dea3101e 3171 pring->postbufq_cnt++;
2e0fef85 3172 spin_unlock_irq(&phba->hbalock);
dea3101e 3173 return 0;
3174}
3175
3176
3177struct lpfc_dmabuf *
3178lpfc_sli_ringpostbuf_get(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
3179 dma_addr_t phys)
3180{
3181 struct lpfc_dmabuf *mp, *next_mp;
3182 struct list_head *slp = &pring->postbufq;
3183
3184 /* Search postbufq, from the begining, looking for a match on phys */
2e0fef85 3185 spin_lock_irq(&phba->hbalock);
dea3101e 3186 list_for_each_entry_safe(mp, next_mp, &pring->postbufq, list) {
3187 if (mp->phys == phys) {
3188 list_del_init(&mp->list);
3189 pring->postbufq_cnt--;
2e0fef85 3190 spin_unlock_irq(&phba->hbalock);
dea3101e 3191 return mp;
3192 }
3193 }
3194
2e0fef85 3195 spin_unlock_irq(&phba->hbalock);
dea3101e 3196 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
3197 "%d:0410 Cannot find virtual addr for mapped buf on "
3198 "ring %d Data x%llx x%p x%p x%x\n",
2e0fef85 3199 phba->brd_no, pring->ringno, (unsigned long long) phys,
dea3101e 3200 slp->next, slp->prev, pring->postbufq_cnt);
3201 return NULL;
3202}
3203
3204static void
2e0fef85
JS		 3205lpfc_sli_abort_els_cmpl(struct lpfc_hba *phba, struct lpfc_iocbq *cmdiocb,
3206 struct lpfc_iocbq *rspiocb)
dea3101e 3207{
2e0fef85 3208 IOCB_t *irsp = &rspiocb->iocb;
2680eeaa
JS		 3209 uint16_t abort_iotag, abort_context;
3210 struct lpfc_iocbq *abort_iocb, *rsp_ab_iocb;
3211 struct lpfc_sli_ring *pring = &phba->sli.ring[LPFC_ELS_RING];
3212
3213 abort_iocb = NULL;
2680eeaa
JS		 3214
3215 if (irsp->ulpStatus) {
3216 abort_context = cmdiocb->iocb.un.acxri.abortContextTag;
3217 abort_iotag = cmdiocb->iocb.un.acxri.abortIoTag;
3218
2e0fef85 3219 spin_lock_irq(&phba->hbalock);
2680eeaa
JS		 3220 if (abort_iotag != 0 && abort_iotag <= phba->sli.last_iotag)
3221 abort_iocb = phba->sli.iocbq_lookup[abort_iotag];
3222
3223 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3224 "%d:0327 Cannot abort els iocb %p"
3225 " with tag %x context %x\n",
3226 phba->brd_no, abort_iocb,
3227 abort_iotag, abort_context);
3228
3229 /*
3230 * make sure we have the right iocbq before taking it
3231 * off the txcmplq and try to call completion routine.
3232 */
2e0fef85
JS		 3233 if (!abort_iocb ||
3234 abort_iocb->iocb.ulpContext != abort_context ||
3235 (abort_iocb->iocb_flag & LPFC_DRIVER_ABORTED) == 0)
3236 spin_unlock_irq(&phba->hbalock);
3237 else {
2680eeaa
JS		 3238 list_del(&abort_iocb->list);
3239 pring->txcmplq_cnt--;
2e0fef85 3240 spin_unlock_irq(&phba->hbalock);
2680eeaa
JS		 3241
3242 rsp_ab_iocb = lpfc_sli_get_iocbq(phba);
3243 if (rsp_ab_iocb == NULL)
3244 lpfc_sli_release_iocbq(phba, abort_iocb);
3245 else {
2e0fef85 3246 abort_iocb->iocb_flag &= ~LPFC_DRIVER_ABORTED;
2680eeaa
JS		 3247 rsp_ab_iocb->iocb.ulpStatus =
3248 IOSTAT_LOCAL_REJECT;
3249 rsp_ab_iocb->iocb.un.ulpWord[4] =
3250 IOERR_SLI_ABORTED;
2e0fef85
JS		 3251 (abort_iocb->iocb_cmpl)(phba, abort_iocb,
3252 rsp_ab_iocb);
2680eeaa
JS		 3253 lpfc_sli_release_iocbq(phba, rsp_ab_iocb);
3254 }
3255 }
3256 }
3257
604a3e30 3258 lpfc_sli_release_iocbq(phba, cmdiocb);
dea3101e 3259 return;
3260}
3261
3262int
2e0fef85
JS		 3263lpfc_sli_issue_abort_iotag(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
3264 struct lpfc_iocbq *cmdiocb)
dea3101e 3265{
2e0fef85 3266 struct lpfc_vport *vport = cmdiocb->vport;
0bd4ca25 3267 struct lpfc_iocbq *abtsiocbp;
dea3101e 3268 IOCB_t *icmd = NULL;
3269 IOCB_t *iabt = NULL;
07951076
JS		 3270 int retval = IOCB_ERROR;
3271
3272 /* There are certain command types we don't want
3273 * to abort.
3274 */
3275 icmd = &cmdiocb->iocb;
2e0fef85
JS		 3276 if (icmd->ulpCommand == CMD_ABORT_XRI_CN ||
3277 icmd->ulpCommand == CMD_CLOSE_XRI_CN)
07951076
JS		 3278 return 0;
3279
3280 /* If we're unloading, interrupts are disabled so we
3281 * need to cleanup the iocb here.
3282 */
2e0fef85 3283 if (vport->load_flag & FC_UNLOADING)
07951076 3284 goto abort_iotag_exit;
dea3101e 3285
3286 /* issue ABTS for this IOCB based on iotag */
0bd4ca25 3287 abtsiocbp = lpfc_sli_get_iocbq(phba);
dea3101e 3288 if (abtsiocbp == NULL)
3289 return 0;
dea3101e 3290
07951076
JS		 3291 /* This signals the response to set the correct status
3292 * before calling the completion handler.
3293 */
3294 cmdiocb->iocb_flag |= LPFC_DRIVER_ABORTED;
3295
dea3101e 3296 iabt = &abtsiocbp->iocb;
07951076
JS		 3297 iabt->un.acxri.abortType = ABORT_TYPE_ABTS;
3298 iabt->un.acxri.abortContextTag = icmd->ulpContext;
3299 iabt->un.acxri.abortIoTag = icmd->ulpIoTag;
3300 iabt->ulpLe = 1;
3301 iabt->ulpClass = icmd->ulpClass;
dea3101e 3302
2e0fef85 3303 if (phba->link_state >= LPFC_LINK_UP)
07951076
JS		 3304 iabt->ulpCommand = CMD_ABORT_XRI_CN;
3305 else
3306 iabt->ulpCommand = CMD_CLOSE_XRI_CN;
dea3101e 3307
07951076 3308 abtsiocbp->iocb_cmpl = lpfc_sli_abort_els_cmpl;
5b8bd0c9
JS		 3309
3310 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3311 "%d:0339 Abort xri x%x, original iotag x%x, abort "
3312 "cmd iotag x%x\n",
3313 phba->brd_no, iabt->un.acxri.abortContextTag,
3314 iabt->un.acxri.abortIoTag, abtsiocbp->iotag);
07951076 3315 retval = lpfc_sli_issue_iocb(phba, pring, abtsiocbp, 0);
dea3101e 3316
07951076 3317abort_iotag_exit:
2e0fef85
JS		 3318 /*
3319 * Caller to this routine should check for IOCB_ERROR
3320 * and handle it properly. This routine no longer removes
3321 * iocb off txcmplq and call compl in case of IOCB_ERROR.
07951076 3322 */
2e0fef85 3323 return retval;
dea3101e 3324}
3325
3326static int
0bd4ca25
JSEC		 3327lpfc_sli_validate_fcp_iocb(struct lpfc_iocbq *iocbq, uint16_t tgt_id,
3328 uint64_t lun_id, uint32_t ctx,
3329 lpfc_ctx_cmd ctx_cmd)
dea3101e 3330{
0bd4ca25
JSEC		 3331 struct lpfc_scsi_buf *lpfc_cmd;
3332 struct scsi_cmnd *cmnd;
dea3101e 3333 int rc = 1;
3334
0bd4ca25
JSEC		 3335 if (!(iocbq->iocb_flag & LPFC_IO_FCP))
3336 return rc;
3337
3338 lpfc_cmd = container_of(iocbq, struct lpfc_scsi_buf, cur_iocbq);
3339 cmnd = lpfc_cmd->pCmd;
3340
3341 if (cmnd == NULL)
dea3101e 3342 return rc;
3343
3344 switch (ctx_cmd) {
3345 case LPFC_CTX_LUN:
0bd4ca25
JSEC		 3346 if ((cmnd->device->id == tgt_id) &&
3347 (cmnd->device->lun == lun_id))
dea3101e 3348 rc = 0;
3349 break;
3350 case LPFC_CTX_TGT:
0bd4ca25 3351 if (cmnd->device->id == tgt_id)
dea3101e 3352 rc = 0;
3353 break;
3354 case LPFC_CTX_CTX:
0bd4ca25 3355 if (iocbq->iocb.ulpContext == ctx)
dea3101e 3356 rc = 0;
0bd4ca25 3357 break;
dea3101e 3358 case LPFC_CTX_HOST:
3359 rc = 0;
3360 break;
3361 default:
3362 printk(KERN_ERR "%s: Unknown context cmd type, value %d\n",
3363 __FUNCTION__, ctx_cmd);
3364 break;
3365 }
3366
3367 return rc;
3368}
3369
3370int
3371lpfc_sli_sum_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
2e0fef85 3372 uint16_t tgt_id, uint64_t lun_id, lpfc_ctx_cmd ctx_cmd)
dea3101e 3373{
0bd4ca25
JSEC		 3374 struct lpfc_iocbq *iocbq;
3375 int sum, i;
dea3101e 3376
0bd4ca25
JSEC		 3377 for (i = 1, sum = 0; i <= phba->sli.last_iotag; i++) {
3378 iocbq = phba->sli.iocbq_lookup[i];
dea3101e 3379
0bd4ca25
JSEC		 3380 if (lpfc_sli_validate_fcp_iocb (iocbq, tgt_id, lun_id,
3381 0, ctx_cmd) == 0)
3382 sum++;
dea3101e 3383 }
0bd4ca25 3384
dea3101e 3385 return sum;
3386}
3387
5eb95af0 3388void
2e0fef85
JS		 3389lpfc_sli_abort_fcp_cmpl(struct lpfc_hba *phba, struct lpfc_iocbq *cmdiocb,
3390 struct lpfc_iocbq *rspiocb)
5eb95af0 3391{
604a3e30 3392 lpfc_sli_release_iocbq(phba, cmdiocb);
5eb95af0
JSEC		 3393 return;
3394}
3395
dea3101e 3396int
3397lpfc_sli_abort_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
3398 uint16_t tgt_id, uint64_t lun_id, uint32_t ctx,
3399 lpfc_ctx_cmd abort_cmd)
3400{
0bd4ca25
JSEC		 3401 struct lpfc_iocbq *iocbq;
3402 struct lpfc_iocbq *abtsiocb;
dea3101e 3403 IOCB_t *cmd = NULL;
dea3101e 3404 int errcnt = 0, ret_val = 0;
0bd4ca25 3405 int i;
dea3101e 3406
0bd4ca25
JSEC		 3407 for (i = 1; i <= phba->sli.last_iotag; i++) {
3408 iocbq = phba->sli.iocbq_lookup[i];
dea3101e 3409
2e0fef85
JS		 3410 if (lpfc_sli_validate_fcp_iocb(iocbq, tgt_id, lun_id, 0,
3411 abort_cmd) != 0)
dea3101e 3412 continue;
3413
3414 /* issue ABTS for this IOCB based on iotag */
0bd4ca25 3415 abtsiocb = lpfc_sli_get_iocbq(phba);
dea3101e 3416 if (abtsiocb == NULL) {
3417 errcnt++;
3418 continue;
3419 }
dea3101e 3420
0bd4ca25 3421 cmd = &iocbq->iocb;
dea3101e 3422 abtsiocb->iocb.un.acxri.abortType = ABORT_TYPE_ABTS;
3423 abtsiocb->iocb.un.acxri.abortContextTag = cmd->ulpContext;
3424 abtsiocb->iocb.un.acxri.abortIoTag = cmd->ulpIoTag;
3425 abtsiocb->iocb.ulpLe = 1;
3426 abtsiocb->iocb.ulpClass = cmd->ulpClass;
2e0fef85 3427 abtsiocb->vport = phba->pport;
dea3101e 3428
2e0fef85 3429 if (lpfc_is_link_up(phba))
dea3101e 3430 abtsiocb->iocb.ulpCommand = CMD_ABORT_XRI_CN;
3431 else
3432 abtsiocb->iocb.ulpCommand = CMD_CLOSE_XRI_CN;
3433
5eb95af0
JSEC		 3434 /* Setup callback routine and issue the command. */
3435 abtsiocb->iocb_cmpl = lpfc_sli_abort_fcp_cmpl;
dea3101e 3436 ret_val = lpfc_sli_issue_iocb(phba, pring, abtsiocb, 0);
3437 if (ret_val == IOCB_ERROR) {
604a3e30 3438 lpfc_sli_release_iocbq(phba, abtsiocb);
dea3101e 3439 errcnt++;
3440 continue;
3441 }
3442 }
3443
3444 return errcnt;
3445}
3446
68876920
JSEC		 3447static void
3448lpfc_sli_wake_iocb_wait(struct lpfc_hba *phba,
3449 struct lpfc_iocbq *cmdiocbq,
3450 struct lpfc_iocbq *rspiocbq)
dea3101e 3451{
68876920
JSEC		 3452 wait_queue_head_t *pdone_q;
3453 unsigned long iflags;
dea3101e 3454
2e0fef85 3455 spin_lock_irqsave(&phba->hbalock, iflags);
68876920
JSEC		 3456 cmdiocbq->iocb_flag |= LPFC_IO_WAKE;
3457 if (cmdiocbq->context2 && rspiocbq)
3458 memcpy(&((struct lpfc_iocbq *)cmdiocbq->context2)->iocb,
3459 &rspiocbq->iocb, sizeof(IOCB_t));
3460
3461 pdone_q = cmdiocbq->context_un.wait_queue;
2e0fef85 3462 spin_unlock_irqrestore(&phba->hbalock, iflags);
68876920
JSEC		 3463 if (pdone_q)
3464 wake_up(pdone_q);
dea3101e 3465 return;
3466}
3467
68876920
JSEC		 3468/*
3469 * Issue the caller's iocb and wait for its completion, but no longer than the
3470 * caller's timeout. Note that iocb_flags is cleared before the
3471 * lpfc_sli_issue_call since the wake routine sets a unique value and by
3472 * definition this is a wait function.
3473 */
dea3101e 3474int
2e0fef85
JS		 3475lpfc_sli_issue_iocb_wait(struct lpfc_hba *phba,
3476 struct lpfc_sli_ring *pring,
3477 struct lpfc_iocbq *piocb,
3478 struct lpfc_iocbq *prspiocbq,
68876920 3479 uint32_t timeout)
dea3101e 3480{
7259f0d0 3481 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_q);
68876920
JSEC		 3482 long timeleft, timeout_req = 0;
3483 int retval = IOCB_SUCCESS;
875fbdfe 3484 uint32_t creg_val;
dea3101e 3485
3486 /*
68876920
JSEC		 3487 * If the caller has provided a response iocbq buffer, then context2
3488 * is NULL or its an error.
dea3101e 3489 */
68876920
JSEC		 3490 if (prspiocbq) {
3491 if (piocb->context2)
3492 return IOCB_ERROR;
3493 piocb->context2 = prspiocbq;
dea3101e 3494 }
3495
68876920
JSEC		 3496 piocb->iocb_cmpl = lpfc_sli_wake_iocb_wait;
3497 piocb->context_un.wait_queue = &done_q;
3498 piocb->iocb_flag &= ~LPFC_IO_WAKE;
dea3101e 3499
875fbdfe
JSEC		 3500 if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
3501 creg_val = readl(phba->HCregaddr);
3502 creg_val |= (HC_R0INT_ENA << LPFC_FCP_RING);
3503 writel(creg_val, phba->HCregaddr);
3504 readl(phba->HCregaddr); /* flush */
3505 }
3506
68876920
JSEC		 3507 retval = lpfc_sli_issue_iocb(phba, pring, piocb, 0);
3508 if (retval == IOCB_SUCCESS) {
3509 timeout_req = timeout * HZ;
68876920
JSEC		 3510 timeleft = wait_event_timeout(done_q,
3511 piocb->iocb_flag & LPFC_IO_WAKE,
3512 timeout_req);
dea3101e 3513
7054a606
JS		 3514 if (piocb->iocb_flag & LPFC_IO_WAKE) {
3515 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3516 "%d:0331 IOCB wake signaled\n",
3517 phba->brd_no);
3518 } else if (timeleft == 0) {
68876920 3519 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
dca9479b 3520 "%d:0338 IOCB wait timeout error - no "
68876920
JSEC		 3521 "wake response Data x%x\n",
3522 phba->brd_no, timeout);
3523 retval = IOCB_TIMEDOUT;
7054a606 3524 } else {
68876920
JSEC		 3525 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3526 "%d:0330 IOCB wake NOT set, "
3527 "Data x%x x%lx\n", phba->brd_no,
3528 timeout, (timeleft / jiffies));
3529 retval = IOCB_TIMEDOUT;
dea3101e 3530 }
68876920
JSEC		 3531 } else {
3532 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3533 "%d:0332 IOCB wait issue failed, Data x%x\n",
3534 phba->brd_no, retval);
3535 retval = IOCB_ERROR;
dea3101e 3536 }
3537
875fbdfe
JSEC		 3538 if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
3539 creg_val = readl(phba->HCregaddr);
3540 creg_val &= ~(HC_R0INT_ENA << LPFC_FCP_RING);
3541 writel(creg_val, phba->HCregaddr);
3542 readl(phba->HCregaddr); /* flush */
3543 }
3544
68876920
JSEC		 3545 if (prspiocbq)
3546 piocb->context2 = NULL;
3547
3548 piocb->context_un.wait_queue = NULL;
3549 piocb->iocb_cmpl = NULL;
dea3101e 3550 return retval;
3551}
68876920 3552
dea3101e 3553int
2e0fef85 3554lpfc_sli_issue_mbox_wait(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmboxq,
dea3101e 3555 uint32_t timeout)
3556{
7259f0d0 3557 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_q);
dea3101e 3558 int retval;
3559
3560 /* The caller must leave context1 empty. */
3561 if (pmboxq->context1 != 0) {
2e0fef85 3562 return MBX_NOT_FINISHED;
dea3101e 3563 }
3564
3565 /* setup wake call as IOCB callback */
3566 pmboxq->mbox_cmpl = lpfc_sli_wake_mbox_wait;
3567 /* setup context field to pass wait_queue pointer to wake function */
3568 pmboxq->context1 = &done_q;
3569
dea3101e 3570 /* now issue the command */
3571 retval = lpfc_sli_issue_mbox(phba, pmboxq, MBX_NOWAIT);
3572
3573 if (retval == MBX_BUSY || retval == MBX_SUCCESS) {
7054a606
JS		 3574 wait_event_interruptible_timeout(done_q,
3575 pmboxq->mbox_flag & LPFC_MBX_WAKE,
3576 timeout * HZ);
3577
dea3101e 3578 pmboxq->context1 = NULL;
7054a606
JS		 3579 /*
3580 * if LPFC_MBX_WAKE flag is set the mailbox is completed
3581 * else do not free the resources.
3582 */
3583 if (pmboxq->mbox_flag & LPFC_MBX_WAKE)
dea3101e 3584 retval = MBX_SUCCESS;
7054a606
JS		 3585 else
3586 retval = MBX_TIMEOUT;
dea3101e 3587 }
3588
dea3101e 3589 return retval;
3590}
3591
b4c02652
JS		 3592int
3593lpfc_sli_flush_mbox_queue(struct lpfc_hba * phba)
3594{
2e0fef85 3595 struct lpfc_vport *vport = phba->pport;
b4c02652 3596 int i = 0;
ed957684 3597 uint32_t ha_copy;
b4c02652 3598
2e0fef85 3599 while (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE && !vport->stopped) {
b4c02652
JS		 3600 if (i++ > LPFC_MBOX_TMO * 1000)
3601 return 1;
3602
ed957684
JS		 3603 /*
3604 * Call lpfc_sli_handle_mb_event only if a mailbox cmd
3605 * did finish. This way we won't get the misleading
3606 * "Stray Mailbox Interrupt" message.
3607 */
3608 spin_lock_irq(&phba->hbalock);
3609 ha_copy = phba->work_ha;
3610 phba->work_ha &= ~HA_MBATT;
3611 spin_unlock_irq(&phba->hbalock);
3612
3613 if (ha_copy & HA_MBATT)
3614 if (lpfc_sli_handle_mb_event(phba) == 0)
3615 i = 0;
b4c02652
JS		 3616
3617 msleep(1);
3618 }
3619
3620 return (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) ? 1 : 0;
3621}
3622
dea3101e 3623irqreturn_t
7d12e780 3624lpfc_intr_handler(int irq, void *dev_id)
dea3101e 3625{
2e0fef85 3626 struct lpfc_hba *phba;
dea3101e 3627 uint32_t ha_copy;
3628 uint32_t work_ha_copy;
3629 unsigned long status;
3630 int i;
3631 uint32_t control;
3632
3633 /*
3634 * Get the driver's phba structure from the dev_id and
3635 * assume the HBA is not interrupting.
3636 */
3637 phba = (struct lpfc_hba *) dev_id;
3638
3639 if (unlikely(!phba))
3640 return IRQ_NONE;
3641
8d63f375
LV		 3642 /* If the pci channel is offline, ignore all the interrupts. */
3643 if (unlikely(pci_channel_offline(phba->pcidev)))
3644 return IRQ_NONE;
3645
dea3101e 3646 phba->sli.slistat.sli_intr++;
3647
3648 /*
3649 * Call the HBA to see if it is interrupting. If not, don't claim
3650 * the interrupt
3651 */
3652
3653 /* Ignore all interrupts during initialization. */
2e0fef85 3654 if (unlikely(phba->link_state < LPFC_LINK_DOWN))
dea3101e 3655 return IRQ_NONE;
3656
3657 /*
3658 * Read host attention register to determine interrupt source
3659 * Clear Attention Sources, except Error Attention (to
3660 * preserve status) and Link Attention
3661 */
2e0fef85 3662 spin_lock(&phba->hbalock);
dea3101e 3663 ha_copy = readl(phba->HAregaddr);
ebdbe65f
JS		 3664 /* If somebody is waiting to handle an eratt don't process it
3665 * here. The brdkill function will do this.
3666 */
2e0fef85 3667 if (phba->link_flag & LS_IGNORE_ERATT)
ebdbe65f 3668 ha_copy &= ~HA_ERATT;
dea3101e 3669 writel((ha_copy & ~(HA_LATT | HA_ERATT)), phba->HAregaddr);
3670 readl(phba->HAregaddr); /* flush */
2e0fef85 3671 spin_unlock(&phba->hbalock);
dea3101e 3672
3673 if (unlikely(!ha_copy))
3674 return IRQ_NONE;
3675
3676 work_ha_copy = ha_copy & phba->work_ha_mask;
3677
3678 if (unlikely(work_ha_copy)) {
3679 if (work_ha_copy & HA_LATT) {
3680 if (phba->sli.sli_flag & LPFC_PROCESS_LA) {
3681 /*
3682 * Turn off Link Attention interrupts
3683 * until CLEAR_LA done
3684 */
2e0fef85 3685 spin_lock(&phba->hbalock);
dea3101e 3686 phba->sli.sli_flag &= ~LPFC_PROCESS_LA;
3687 control = readl(phba->HCregaddr);
3688 control &= ~HC_LAINT_ENA;
3689 writel(control, phba->HCregaddr);
3690 readl(phba->HCregaddr); /* flush */
2e0fef85 3691 spin_unlock(&phba->hbalock);
dea3101e 3692 }
3693 else
3694 work_ha_copy &= ~HA_LATT;
3695 }
3696
3697 if (work_ha_copy & ~(HA_ERATT|HA_MBATT|HA_LATT)) {
3698 for (i = 0; i < phba->sli.num_rings; i++) {
3699 if (work_ha_copy & (HA_RXATT << (4*i))) {
3700 /*
3701 * Turn off Slow Rings interrupts
3702 */
2e0fef85 3703 spin_lock(&phba->hbalock);
dea3101e 3704 control = readl(phba->HCregaddr);
3705 control &= ~(HC_R0INT_ENA << i);
3706 writel(control, phba->HCregaddr);
3707 readl(phba->HCregaddr); /* flush */
2e0fef85 3708 spin_unlock(&phba->hbalock);
dea3101e 3709 }
3710 }
3711 }
3712
3713 if (work_ha_copy & HA_ERATT) {
2e0fef85 3714 phba->link_state = LPFC_HBA_ERROR;
dea3101e 3715 /*
3716 * There was a link/board error. Read the
3717 * status register to retrieve the error event
3718 * and process it.
3719 */
3720 phba->sli.slistat.err_attn_event++;
3721 /* Save status info */
3722 phba->work_hs = readl(phba->HSregaddr);
3723 phba->work_status[0] = readl(phba->MBslimaddr + 0xa8);
3724 phba->work_status[1] = readl(phba->MBslimaddr + 0xac);
3725
3726 /* Clear Chip error bit */
3727 writel(HA_ERATT, phba->HAregaddr);
3728 readl(phba->HAregaddr); /* flush */
2e0fef85 3729 phba->pport->stopped = 1;
dea3101e 3730 }
3731
2e0fef85 3732 spin_lock(&phba->hbalock);
dea3101e 3733 phba->work_ha |= work_ha_copy;
3734 if (phba->work_wait)
3735 wake_up(phba->work_wait);
2e0fef85 3736 spin_unlock(&phba->hbalock);
dea3101e 3737 }
3738
3739 ha_copy &= ~(phba->work_ha_mask);
3740
3741 /*
3742 * Process all events on FCP ring. Take the optimized path for
3743 * FCP IO. Any other IO is slow path and is handled by
3744 * the worker thread.
3745 */
3746 status = (ha_copy & (HA_RXMASK << (4*LPFC_FCP_RING)));
3747 status >>= (4*LPFC_FCP_RING);
3748 if (status & HA_RXATT)
3749 lpfc_sli_handle_fast_ring_event(phba,
3750 &phba->sli.ring[LPFC_FCP_RING],
3751 status);
a4bc3379
JS		 3752
3753 if (phba->cfg_multi_ring_support == 2) {
3754 /*
3755 * Process all events on extra ring. Take the optimized path
3756 * for extra ring IO. Any other IO is slow path and is handled
3757 * by the worker thread.
3758 */
3759 status = (ha_copy & (HA_RXMASK << (4*LPFC_EXTRA_RING)));
3760 status >>= (4*LPFC_EXTRA_RING);
3761 if (status & HA_RXATT) {
3762 lpfc_sli_handle_fast_ring_event(phba,
3763 &phba->sli.ring[LPFC_EXTRA_RING],
3764 status);
3765 }
3766 }
dea3101e 3767 return IRQ_HANDLED;
3768
3769} /* lpfc_intr_handler */
Linux kernel - Deliverables
This page took 0.446732 seconds and 5 git commands to generate.